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2022-04-28crypto:starfive: Write the security clock tree and reset description filewilliam.qiu1-0/+81
Write the security clock tree and reset description file Signed-off-by: william.qiu <william.qiu@starfivetech.com>
2022-04-28defconfig: add crypto defconfig support.william.qiu1-0/+3
add defconfig for jh7110 crypto. Signed-off-by: william.qiu <william.qiu@starfivetech.com>
2022-04-28dt-bingings:crypto: add crypto node for jh7110 soc.william.qiu1-0/+34
add support for jh7110 crypto. Signed-off-by: william.qiu <william.qiu@starfivetech.com>
2022-04-28dmaengine:pl080: add support for starfive jh7110 soc sec.william.qiu3-1/+139
dd support for starfive jh7110 soc sec. Signed-off-by: william.qiu <william.qiu@starfivetech.com>
2022-04-28crypto: add patch for 5.15william.qiu6-79/+299
crypto need this patch to work. Signed-off-by: william.qiu <william.qiu@starfivetech.com>
2022-04-28Merge branch 'CR_880_MBX_shanlong.li' into 'jh7110_fpga_dev_5.15'andy.hu6-528/+556
Cr 880 mbx shanlong.li See merge request sdk/sft-riscvpi-linux-5.10!25
2022-04-27v4l2: add isp clk tree supportchanghuang.liang7-236/+97
v4l2: delete isp top clk configure riscv:dts:starfive: vin add isp clk handle Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>
2022-04-27riscv:linux:driver:DC8200keith.zhao37-1258/+1716
for DC8200 drm driver,update clk reset pinctrl and syscon api Signed-off-by: keith.zhao<keith.zhao@statfivetech.com>
2022-04-26V4L2: clk and reset use bulk getchanghuang.liang4-80/+55
Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>
2022-04-26v4l2: mipi channel add reset control suppurtchanghuang.liang5-90/+71
2022-04-26v4l2: external modules resource use ioremapchanghuang.liang2-38/+51
2022-04-26v4l2: sc2235 sensor use pinctrl set powerchanghuang.liang3-27/+162
2022-04-26v4l2: add sys clk tree supportchanghuang.liang4-12/+65
2022-04-26v4l2: add reset control supportchanghuang.liang4-18/+113
2022-04-26dts: modify sc2235 namechanghuang.liang1-1/+1
2022-04-26v4l2: add pinctrl supportchanghuang.liang3-3/+12
2022-04-26v4l2: fixed sys_crg ioremap error!changhuang.liang2-6/+5
2022-04-26e24:driver: add e24 drever , use clk/rst api ,syscon spishanlong.li2-0/+3
add e24 drever, use clk/rst api, syscon spi Signed-off-by: shanlong.li <shanlong.li@starfivetech.com>
2022-04-26dt-bingings:e24: add e24 devicetree, use clk/rst/syscon.shanlong.li2-0/+33
add e24 devicetree, use clk/rst/syscon. Signed-off-by: shanlong.li <shanlong.li@starfivetech.com>
2022-04-26mailbox:starfive: use clk/rst API.shanlong.li2-528/+516
1) use clk/rst api 2) fix coding style. Signed-off-by: shanlong.li <shanlong.li@starfivetech.com>
2022-04-25dt-bingings:mailbox: Add clk/rst single.shanlong.li1-0/+4
Add clk/rst single for mailbox. Signed-off-by: shanlong.li <shanlong.li@starfivetech.com>
2022-04-25Merge branch 'CR_854_RTC_hal.feng' into 'jh7110_fpga_dev_5.15'andy.hu2-30/+65
rtc: starfive: Use stardand clock and reset apis for initialization See merge request sdk/sft-riscvpi-linux-5.10!30
2022-04-25Merge branch 'CR_853_TRNG_hal.feng' into 'jh7110_fpga_dev_5.15'andy.hu2-81/+98
Cr 853 trng hal.feng See merge request sdk/sft-riscvpi-linux-5.10!29
2022-04-25Merge branch 'CR_871_PWM_hal.feng' into 'jh7110_fpga_dev_5.15'andy.hu3-130/+162
Cr 871 pwm hal.feng See merge request sdk/sft-riscvpi-linux-5.10!28
2022-04-25rtc: starfive: Use stardand clock and reset apis for initializationHal Feng2-30/+65
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2022-04-25Merge branch 'CR_786_CAN_clivia.cai' into 'jh7110_fpga_dev_5.15'andy.hu5-132/+103
Cr 786 can clivia.cai See merge request sdk/sft-riscvpi-linux-5.10!24
2022-04-25Merge branch 'CR_886_I2C_hal.feng' into 'jh7110_fpga_dev_5.15'andy.hu2-0/+18
riscv: dts: starfive: Add clock and reset for i2c See merge request sdk/sft-riscvpi-linux-5.10!27
2022-04-25riscv: dts: starfive: Add clock and reset for i2cHal Feng2-0/+18
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2022-04-24hw_random: starfive-trng: Use stardand clock and reset apis for initializationHal Feng2-11/+48
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2022-04-24hw_random: starfive-trng: Follow linux coding styleHal Feng1-70/+50
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2022-04-24Merge branch 'CR_877_Timer_Xingyu.Wu' into 'jh7110_fpga_dev_5.15'andy.hu5-9/+33
risv:dts:starfive:Add timer clocktree See merge request sdk/sft-riscvpi-linux-5.10!26
2022-04-24pwm: pwm-starfive-ptc: Use standard clock, reset, pinctrl framework for ↵Hal Feng3-13/+47
initialization Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2022-04-24riscv: dts: starfive: Fix string mismatch problem of ptc (pwm)Hal Feng1-2/+2
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2022-04-24pwm: pwm-starfive-ptc: Follow linux coding styleHal Feng1-121/+119
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2022-04-24risv:dts:starfive:Add timer clocktreexingyu.wu5-9/+33
1.Modify the clock tree driver to make timer clock ignore disabled_unused. 2.Add different 'clock-frequency' node in fpga, evb and visionfive dts file. Signed-off-by: xingyu.wu <xingyu.wu@starfivetech.com>
2022-04-24Update ipms-can.yamlsamin.guo1-2/+0
2022-04-24Merge branch 'CR_865_GMAC_yanhong.wang' into 'jh7110_fpga_dev_5.15'andy.hu4-26/+192
Cr 865 gmac yanhong.wang See merge request sdk/sft-riscvpi-linux-5.10!23
2022-04-24Merge branch 'CR_872_PCIE_mason.huo' into 'jh7110_fpga_dev_5.15'andy.hu2-31/+167
Cr 872 pcie mason.huo See merge request sdk/sft-riscvpi-linux-5.10!15
2022-04-24Merge branch 'CR_785_PCIE_mason.huo' into 'jh7110_fpga_dev_5.15'andy.hu2-152/+174
Cr 785 pcie mason.huo See merge request sdk/sft-riscvpi-linux-5.10!13
2022-04-24dt-bingings:can:Add syscon register configClivia.Cai1-16/+12
Add the syscon register config for can/canfd dt-bindings. In addition, Redefine some attribute names. Signed-off-by: Clivia.Cai <Clivia.Cai@starfivetech.com>
2022-04-24dt-bingings:can:Modify referenceClivia.Cai2-5/+5
Modify the reference of ipmscanx to canx Signed-off-by: Clivia.Cai <Clivia.Cai@starfivetech.com>
2022-04-24dt-bindings:net:can:ipms-can: update ipms-can.yaml referencesClivia.Cai1-33/+25
Update CAN/CANFD binding documentation for jh7110 SoC. Signed-off-by: Clivia.Cai <Clivia.Cai@starfivetech.com>
2022-04-24can:ipms_can: Driver code optimizationClivia.Cai1-77/+62
Use the syscon framework to manage the syscon registers. In addition, Use devm_reset_control_array_get_exclusive API to manage a list of reset controllers Signed-off-by: Clivia.Cai <Clivia.Cai@starfivetech.com>
2022-04-24riscv: dts: jh7110: Fix syscon indentation issuemason.huo1-6/+6
Remove additional tabs of syscon configurations. Signed-off-by: mason.huo <mason.huo@starfivetech.com>
2022-04-24PCI: plda: Add syscon register configmason.huo2-29/+93
Add the syscon register config when plda hw initializes. Signed-off-by: mason.huo <mason.huo@starfivetech.com>
2022-04-24PCI: plda: Add pcie clk & rstmason.huo2-3/+75
Signed-off-by: mason.huo <mason.huo@starfivetech.com>
2022-04-24PCI: plda: Add port1 supportmason.huo1-3/+27
Add configuration to support plda pcie port1. Signed-off-by: mason.huo <mason.huo@starfivetech.com>
2022-04-24PCI: plda: Optimize plda pcie host drivermason.huo1-149/+147
Fix the hardcoded ATR setting. Fix some kernel coding standard issues. Signed-off-by: mason.huo <mason.huo@starfivetech.com>
2022-04-24net:stmmac:dwc-qos: Add jh7110 supportyanhong.wang1-1/+130
The StarFive JH7110 SoC contains an instance of the Synopsys DWC ethernet QOS IP core.The binding that it uses is slightly different from existing ones because of the integration (clocks, resets, ...). Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-04-24dt-bingings:gmac:jh7110: add clk and reset signals for gmacyanhong.wang2-7/+62
Gmac uses the Clock and reset framework API. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-27 15:07:16 +0300