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2022-07-26v4l2: fixed imx219 date error at the first linechanghuang.liang3-41/+39
fixed imx219 date error at the first line Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>
2022-07-26dts: starfive: Modified vbus enable pin function to be GPO_HIGHKevin.xie1-1/+1
Signed-off-by: Kevin.xie <kevin.xie@starfivetech.com>
2022-07-26pinctrl: starfive: update config descriptionJianlong Huang2-13/+7
update config desription and delete vic7100 description Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
2022-07-26riscv:linux:vout:inno hdmikeith.zhao1-358/+24
delete unless function to reduce warning Signed-off-by: keith <keith.zhao@starfivetech.com>
2022-07-26TDM:fix 32bit only has 1 channel of dataWalker Chen1-2/+8
TDM: playback or record with 32bit format, only has 1 channel of data. This bug has been resolved. Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
2022-07-26riscv:linux:vout:inno hdmikeith.zhao2-81/+28
Solve inno hdmi screen compatibility issue , include 4K display mode Signed-off-by: keith <keith.zhao@starfivetech.com>
2022-07-22Merge branch 'CR_1590_GPU_Enable_515_Andy.Hu' into 'jh7110-5.15.y-devel'Jason Zhou1-1/+1
CR_1590: defconfig: enable GPU building See merge request sdk/linux!320
2022-07-22defconfig: enable GPU buildingAndy Hu1-1/+1
Enable CONFIG_DRM_IMG and CONFIG_DRM_IMG_ROGUE in jh7110 defconfig Signed-off-by: shanlong.li <shanlong.li@starfivetech.com>
2022-07-22Merge branch 'CR_1584_pwmdac_11025_compatible_issue_minda' into ↵Jason Zhou1-0/+4
'jh7110-5.15.y-devel' CR_1584 pwmdac:sound: support 11025hz sample rate. See merge request sdk/linux!275
2022-07-22Merge branch 'CR_1649_7110_evb_5.15_vout_retbug_shengyang.chen' into ↵Jason Zhou4-18/+7
'jh7110-5.15.y-devel' CR_1649_5.15-evb_vout: fix failure problem of vout while startup See merge request sdk/linux!299
2022-07-21pwmdac:sound: support 11025hz play mode.minda.chen1-0/+4
1. set the correct clock rate and sample cnt. 2. using aplay 11.025kz wave file can pass. 3. fix issue redmine 1584 Signed-off-by: minda.chen <minda.chen@starfivetech.com>
2022-07-21Merge branch 'CR_1422_V4L2_515_mason.huo' into 'jh7110-5.15.y-devel'Jason Zhou7-55/+242
Cr 1422 v4 l2 515 mason.huo See merge request sdk/linux!316
2022-07-21Merge branch 'CR_1667_TDM_change_reset_interface_walker.chen' into ↵Jason Zhou3-78/+83
'jh7110-5.15.y-devel' CR_1667_TDM_change_reset_interface See merge request sdk/linux!304
2022-07-21Merge branch 'CR_1541_PDM_Increase_walker.chen' into 'jh7110-5.15.y-devel'Jason Zhou2-76/+67
CR_1541_PDM: support more data width and sample rate See merge request sdk/linux!310
2022-07-21Merge branch 'CR_1661_Watchdog_api_Xingyu.Wu' into 'jh7110-5.15.y-devel'Jason Zhou1-13/+7
CR_1661 watchdog:starfive:Update reset api See merge request sdk/linux!308
2022-07-21Merge branch 'CR_1600_v4l2_reset_515_changhuang.liang' into ↵Jason Zhou6-86/+19
'jh7110-5.15.y-devel' CR_1600_v4l2_reset_515_changhuang.liang See merge request sdk/linux!282
2022-07-21Merge branch 'CR_1657_clock_tree_api_Xingyu.Wu' into 'jh7110-5.15.y-devel'Jason Zhou2-142/+53
CR_1657 clock tree api xingyu.wu See merge request sdk/linux!305
2022-07-21Merge branch 'CR_1658_I2S_515_curry.zhang' into 'jh7110-5.15.y-devel'Jason Zhou3-62/+31
CR_1658_I2S [Audio: I2S] Updated the reset API See merge request sdk/linux!301
2022-07-21Merge branch 'CR_1656_RTC_hal.feng' into 'jh7110-5.15.y-devel'Jason Zhou2-30/+15
Cr 1656 rtc hal.feng See merge request sdk/linux!292
2022-07-21TDM:change reset interfaceWalker Chen3-78/+83
1.Modify reset interface with devm_reset_control_array_get_exclusive 2.Support more sample rate: 11025, 22050, 32000, 44100, 48000 Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
2022-07-21media: starfive: Fix v4l2 compliance test issuesmason.huo6-20/+96
To get the v4l2 compliance test passed: Add some v4l2 operations which are needed. Improve the ioctl operations of sensor too. Signed-off-by: mason.huo <mason.huo@starfivetech.com>
2022-07-21media: starfive: Add video format debug informationmason.huo3-6/+20
Add some debug log for set/get video format, so that we can check if the v4l2 driver accepts or not the format set by user. Signed-off-by: mason.huo <mason.huo@starfivetech.com>
2022-07-21v4l2: fixed v4l2 compliance issuechanghuang.liang3-31/+128
imx219 add set/get frameintervals Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>
2022-07-21crypto:starfive: Include bug fixes for hash/hmac found by Linux selftest.jiajie.ho1-9/+14
SHA/HMAC fixes: 1. Updated SM3 blocksize and digestsize. 2. Fixed non 32bit-aligned key input for HMAC. 3. Removed unnecessary init sequence check from SHA/HMAC. Signed-off-by: jiajie.ho <jiajie.ho@starfivetech.com>
2022-07-21PDM: support more data width and sample rateWalker Chen2-76/+67
PDM driver: support data width 16, 32 bits, sample rate 8000, 11025, 16000 Hz Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
2022-07-21[Audio: I2S] Updated the reset APIcurry.zhang3-62/+31
changed the standard reset API Signed-off-by: curry.zhang <curry.zhang@starfivetech.com>
2022-07-21Merge branch 'CR_1582_evb_515_DRM_RGB_keith.zhao' into 'jh7110-5.15.y-devel'Jason Zhou1-4/+4
riscv:linux:vout:rgb See merge request sdk/linux!278
2022-07-21rtc: starfive: Change reset apiHal Feng1-26/+11
Use devm_reset_control_array_get_exclusive() to get reset Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2022-07-21riscv: dts: starfive: Modify order of reset in rtc nodeHal Feng1-4/+4
For changing reset api used in rtc driver Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
2022-07-20clk:starfive:Update clk and reset api about voutxingyu.wu1-37/+22
Use 'clk_bulk_get' api to replace 'clk_get' and use 'share' replace 'exclusive' about reset. Signed-off-by: xingyu.wu <xingyu.wu@starfivetech.com>
2022-07-20clk:starfive:Update clk and reset api about ispxingyu.wu1-105/+31
Use 'clk_bulk_get' and 'devm_reset_control_array_get' api to replace 'clk_get' and 'devm_reset_control_get' api. Signed-off-by: xingyu.wu <xingyu.wu@starfivetech.com>
2022-07-20v4l2: modify reset apichanghuang.liang6-86/+19
modify reset api Signed-off-by: changhuang.liang <changhuang.liang@starfivetech.com>
2022-07-20Merge branch 'CR_1176_CLOCK_TREE_PLL_Xingyu.Wu' into 'jh7110-5.15.y-devel'Jason Zhou16-143/+947
CR 1176 clock tree pll xingyu.wu See merge request sdk/linux!280
2022-07-20watchdog:starfive:Update reset apixingyu.wu1-13/+7
Use 'devm_reset_control_array_get_exclusive' api to get reset controllers. Signed-off-by: xingyu.wu <xingyu.wu@starfivetech.com>
2022-07-20clk:starfive:Modify function format about 'jh7110_pll_data_from'xingyu.wu1-2/+2
Modify function format about 'jh7110_pll_data_from' Signed-off-by: xingyu.wu <xingyu.wu@starfivetech.com>
2022-07-20defconfig:Add CONFIG_CLK_STARFIVE_JH7110_PLLxingyu.wu1-0/+1
Add CONFIG_CLK_STARFIVE_JH7110_PLL Signed-off-by: xingyu.wu <xingyu.wu@starfivetech.com>
2022-07-20clk:starfive:Set PLL2 frequency when clock tree registeringxingyu.wu2-1/+14
In the file drivers/clk/starfive/clk-starfive-jh7110-pll.h, If set PLL2_DEFAULT_FREQ NULL of 0 , then PLL2 frequency is original. If set PLL2_DEFAULT_FREQ one of 'starfive_pll2_freq_value', then PLL2 frequency will be set the new rate during clock tree registering. Signed-off-by: xingyu.wu <xingyu.wu@starfivetech.com>
2022-07-20clk:starfive:Add PLL2 frequency controllerxingyu.wu4-25/+35
If enable CONFIG_CLK_STARFIVE_JH7110_PLL, also could read or set PLL1 clock's rate by reading or setting syscon registers. Signed-off-by: xingyu.wu <xingyu.wu@starfivetech.com>
2022-07-20clk:starfive:Add PLL0 frequency controllerxingyu.wu8-2/+767
If enable CONFIG_CLK_STARFIVE_JH7110_PLL, could read or set PLL0 clock's rate by reading or setting syscon registers. Signed-off-by: xingyu.wu <xingyu.wu@starfivetech.com>
2022-07-20clk:starfive:Modify the formatxingyu.wu7-110/+119
Modify the clocktree files' format Signed-off-by: xingyu.wu <xingyu.wu@starfivetech.com>
2022-07-20dt-bindings:clock:Delete external clock definitionsxingyu.wu8-34/+40
Move external clock definitions to C files that avoid illegal use. Signed-off-by: xingyu.wu <xingyu.wu@starfivetech.com>
2022-07-20vout: fix failure problem of vout while startupshengyang.chen4-18/+7
fix failure problem of vout while startup Signed-off-by: shengyang.chen<shengyang.chen@starfivetech.com>
2022-07-20Merge branch 'CR_1651_7110_evb_5.15_voutrst-1_shengyang.chen' into ↵Jason Zhou3-248/+22
'jh7110-5.15.y-devel' Cr 1651 7110 evb 5.15 voutrst 1 shengyang.chen See merge request sdk/linux!285
2022-07-20Merge branch 'CR_1562_SPI_Xingyu.Wu' into 'jh7110-5.15.y-devel'Jason Zhou1-2/+31
CR_1562 spi xingyu.wu See merge request sdk/linux!288
2022-07-20Merge branch 'CR_1564_I2C_hal.feng' into 'jh7110-5.15.y-devel'Jason Zhou1-14/+14
CR 1564 i2c hal.feng See merge request sdk/linux!290
2022-07-20Merge branch 'CR_1560_v4l2_changhuang.liang' into 'jh7110-5.15.y-devel'Jason Zhou1-6/+1
CR_1560_v4l2_changhuang.liang See merge request sdk/linux!294
2022-07-20Merge branch 'CR_1631_7110_evb_5.15_mipitx_shengyang.chen' into ↵Jason Zhou2-23/+9
'jh7110-5.15.y-devel' CR_1631-5.15 riscv:linux:drm:mipitx See merge request sdk/linux!296
2022-07-20Merge branch 'CR_1274_SEC_jiajie.ho' into 'jh7110-5.15.y-devel'Jason Zhou3-8/+4
crypto:starfive: Switch CSR polling instead of interrupt for HMAC. See merge request sdk/linux!298
2022-07-20crypto:starfive: Switch CSR polling instead of interrupt for HMAC.jiajie.ho3-8/+4
Observed interrupt signal goes HIGH before HMAC calculations has been completed. Switching to use CSR polling to check for HMAC_DONE instead. Signed-off-by: Jia Jie Ho <jiajie.ho@starfivetech.com>
2022-07-20riscv:linux:drm:shengyang.chen2-23/+9
fix mipi shifted display problem remove useless process in vs_dc_hw.c Signed-off-by:shengyang.chen<shengyang.chen@starfivetech.com>
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