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2021-12-26sifive/sifive_l2_cache: Align the address to cache lineAtish Patra1-0/+3
[Emil: fix suggested by Geert Uytterhoeven <geert@linux-m68k.org>] Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-12-26sifive/sifive_l2_cache: Print a backtrace on out-of-range flushesGeert Uytterhoeven1-2/+2
This makes it easier to find out which driver passes a wrong address range. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2021-12-26sifive/sifive_l2_cache: Add disabling IRQ option (workaround)Tom3-0/+53
2021-12-26sifive/sifive_l2_cache: Add Starfive supportTom1-0/+1
2021-12-26sifive/sifive_l2_cache: Add sifive_l2_flush64_range functionTom3-1/+59
2021-12-26drivers/hw_random: Add StarFive JH7100 Random Number Generator driverHuan Feng4-0/+437
2021-12-26watchdog: Add StarFive SI5 watchdog driverSamin Guo3-0/+788
Signed-off-by: Samin Guo <samin.guo@starfivetech.com> Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
2021-12-26hwmon: (sfctemp) Add StarFive JH7100 temperature sensorEmil Renner Berthing6-0/+401
Register definitions and conversion constants based on sfctemp driver by Samin in the StarFive 5.10 kernel. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2021-12-26dt-bindings: hwmon: add starfive,jh7100-temp bindingsEmil Renner Berthing1-0/+74
Add bindings for the temperature sensor on the StarFive JH7100 SoC. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Reviewed-by: Rob Herring <robh@kernel.org>
2021-12-26serial: 8250_dw: Add quirk for starfive,jh7100-hsuart tooEmil Renner Berthing1-1/+3
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-12-26pinctrl: starfive: Reset pinmux settingsEmil Renner Berthing2-0/+70
Current u-boot doesn't seem to take into account that some GPIOs are configured as inputs/outputs of certain peripherals on power-up. This means it ends up configuring some GPIOs as inputs to more than one peripheral which the documentation explicitly says is illegal. Similarly it also ends up configuring more than one GPIO as output of the same peripheral. While not explicitly mentioned by the documentation this also seems like a bad idea. The easiest way to remedy this mess is to just disconnect all GPIOs from peripherals and have our pinmux configuration set everything up properly. This, however, means that we'd disconnect the serial console from its pins for a while, so add a device tree property to keep certain GPIOs from being reset. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-12-26clk: starfive: jh7100: Keep more clocks aliveEmil Renner Berthing1-24/+24
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-12-26RISC-V: Add StarFive JH7100 audio reset nodeEmil Renner Berthing1-0/+6
Add device tree node for the audio resets on the StarFive JH7100 RISC-V SoC. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-12-26reset: starfive: Add JH7100 audio reset driverEmil Renner Berthing6-15/+112
The audio resets are almost identical to the system resets, there are just fewer of them. So factor out and export a generic probe function, so most of the reset controller implementation can be shared. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-12-26reset: starfive: Use 32bit I/O on 32bit registersEmil Renner Berthing1-20/+20
The driver currently uses 64bit I/O on the 32bit registers. This works because there are 4 assert registers and 4 status register, so they're only ever accessed on 64bit boundaries. There are however other reset controllers for audio and video on the SoC with only one status register that isn't 64bit aligned so 64bit I/O would result in an unaligned access exception. Switch to 32bit I/O in preparation for supporting these resets too. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-12-26reset: Create subdirectory for StarFive driversEmil Renner Berthing6-9/+13
This moves the StarFive JH7100 reset driver to a new subdirectory in preparation for adding more StarFive reset drivers. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-12-26dt-bindings: reset: Add starfive,jh7100-audrst bindingsEmil Renner Berthing1-0/+38
Add bindings for the audio reset controller on the StarFive JH7100 RISC-V SoC. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-12-26dt-bindings: reset: Add StarFive JH7100 audio reset definitionsEmil Renner Berthing1-0/+31
Add all resets for the StarFive JH7100 audio reset controller. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-12-26RISC-V: Add StarFive JH7100 audio clock nodeEmil Renner Berthing1-0/+10
Add device tree node for the audio clocks on the StarFive JH7100 RISC-V SoC. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-12-26clk: starfive: Add JH7100 audio clock driverEmil Renner Berthing4-4/+182
Add a driver for the audio clocks on the Starfive JH7100 RISC-V SoC. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-12-26clk: starfive: jh7100: Support more clock typesEmil Renner Berthing2-0/+41
Unlike the system clocks there are audio clocks that combine both multiplexer/divider and gate/multiplexer/divider, so add support for that. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-12-26clk: starfive: jh7100: Make hw clock implementation reusableEmil Renner Berthing2-89/+110
The JH7100 has additional audio and video clocks at different memory ranges, but they use the same register layout. Add a header and export the starfive_jh7100_clk_ops function so the clock implementation can be reused by drivers handling these clocks. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-12-26dt-bindings: clock: Add starfive,jh7100-audclk bindingsEmil Renner Berthing1-0/+57
Add bindings for the audio clocks on the StarFive JH7100 RISC-V SoC. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-12-26dt-bindings: clock: Add JH7100 audio clock definitionsEmil Renner Berthing1-0/+41
Add all clock outputs for the StarFive JH7100 audio clock generator. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-12-26riscv: dts: starfive: Group tuples in interrupt propertiesGeert Uytterhoeven1-4/+4
To improve human readability and enable automatic validation, the tuples in the various properties containing interrupt specifiers should be grouped. Fix this by grouping the tuples of "interrupts-extended" properties using angle brackets. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
2021-12-26clk: starfive: jh7100: Handle audio_div clock properlyEmil Renner Berthing1-1/+67
It turns out the audio_div clock is a fractional divider where the lowest byte of the ctrl register is the integer part of the divider and the 2nd byte is the number of 100th added to the divider. The children of this clock is used by the audio peripherals for their sample rate clock, so round to the closest possible rate rather than always rounding down like regular dividers. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-12-26clk: starfive: jh7100: Don't round divisor up twiceEmil Renner Berthing1-11/+3
The problem is best illustrated by an example. Suppose a consumer wants a 4MHz clock rate from a divider with a 10MHz parent. It would then call clk_round_rate(clk, 4000000) which would call into our determine_rate() callback that correctly rounds up and finds that a divisor of 3 gives the highest possible frequency below the requested 4MHz and returns 10000000 / 3 = 3333333Hz. However the consumer would then call clk_set_rate(clk, 3333333) but since 3333333 doesn't divide 10000000 evenly our set_rate() callback would again round the divisor up and set it to 4 which results in an unnecessarily low rate of 2.5MHz. Fix it by using DIV_ROUND_CLOSEST in the set_rate() callback. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-12-26riscv: Add -ffreestanding for string functionsEmil Renner Berthing1-0/+5
The string library implements memset, memcpy and other library functions, so tell the compiler not to optimise such code to just calls to themselves. This is correct for all compilers, but for some reason only Clang builds break without this flag. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-12-26riscv: optimized memsetMatteo Croce6-135/+44
The generic memset is defined as a byte at time write. This is always safe, but it's slower than a 4 byte or even 8 byte write. Write a generic memset which fills the data one byte at time until the destination is aligned, then fills using the largest size allowed, and finally fills the remaining data one byte at time. Signed-off-by: Matteo Croce <mcroce@microsoft.com>
2021-12-26riscv: optimized memmoveMatteo Croce5-70/+26
When the destination buffer is before the source one, or when the buffers doesn't overlap, it's safe to use memcpy() instead, which is optimized to use a bigger data size possible. Signed-off-by: Matteo Croce <mcroce@microsoft.com> Reported-by: kernel test robot <lkp@intel.com>
2021-12-26riscv: optimized memcpyMatteo Croce5-113/+97
Write a C version of memcpy() which uses the biggest data size allowed, without generating unaligned accesses. The procedure is made of three steps: First copy data one byte at time until the destination buffer is aligned to a long boundary. Then copy the data one long at time shifting the current and the next u8 to compose a long at every cycle. Finally, copy the remainder one byte at time. On a BeagleV, the TCP RX throughput increased by 45%: before: $ iperf3 -c beaglev Connecting to host beaglev, port 5201 [ 5] local 192.168.85.6 port 44840 connected to 192.168.85.48 port 5201 [ ID] Interval Transfer Bitrate Retr Cwnd [ 5] 0.00-1.00 sec 76.4 MBytes 641 Mbits/sec 27 624 KBytes [ 5] 1.00-2.00 sec 72.5 MBytes 608 Mbits/sec 0 708 KBytes [ 5] 2.00-3.00 sec 73.8 MBytes 619 Mbits/sec 10 451 KBytes [ 5] 3.00-4.00 sec 72.5 MBytes 608 Mbits/sec 0 564 KBytes [ 5] 4.00-5.00 sec 73.8 MBytes 619 Mbits/sec 0 658 KBytes [ 5] 5.00-6.00 sec 73.8 MBytes 619 Mbits/sec 14 522 KBytes [ 5] 6.00-7.00 sec 73.8 MBytes 619 Mbits/sec 0 621 KBytes [ 5] 7.00-8.00 sec 72.5 MBytes 608 Mbits/sec 0 706 KBytes [ 5] 8.00-9.00 sec 73.8 MBytes 619 Mbits/sec 20 580 KBytes [ 5] 9.00-10.00 sec 73.8 MBytes 619 Mbits/sec 0 672 KBytes - - - - - - - - - - - - - - - - - - - - - - - - - [ ID] Interval Transfer Bitrate Retr [ 5] 0.00-10.00 sec 736 MBytes 618 Mbits/sec 71 sender [ 5] 0.00-10.01 sec 733 MBytes 615 Mbits/sec receiver after: $ iperf3 -c beaglev Connecting to host beaglev, port 5201 [ 5] local 192.168.85.6 port 44864 connected to 192.168.85.48 port 5201 [ ID] Interval Transfer Bitrate Retr Cwnd [ 5] 0.00-1.00 sec 109 MBytes 912 Mbits/sec 48 559 KBytes [ 5] 1.00-2.00 sec 108 MBytes 902 Mbits/sec 0 690 KBytes [ 5] 2.00-3.00 sec 106 MBytes 891 Mbits/sec 36 396 KBytes [ 5] 3.00-4.00 sec 108 MBytes 902 Mbits/sec 0 567 KBytes [ 5] 4.00-5.00 sec 106 MBytes 891 Mbits/sec 0 699 KBytes [ 5] 5.00-6.00 sec 106 MBytes 891 Mbits/sec 32 414 KBytes [ 5] 6.00-7.00 sec 106 MBytes 891 Mbits/sec 0 583 KBytes [ 5] 7.00-8.00 sec 106 MBytes 891 Mbits/sec 0 708 KBytes [ 5] 8.00-9.00 sec 106 MBytes 891 Mbits/sec 28 433 KBytes [ 5] 9.00-10.00 sec 108 MBytes 902 Mbits/sec 0 591 KBytes - - - - - - - - - - - - - - - - - - - - - - - - - [ ID] Interval Transfer Bitrate Retr [ 5] 0.00-10.00 sec 1.04 GBytes 897 Mbits/sec 144 sender [ 5] 0.00-10.01 sec 1.04 GBytes 894 Mbits/sec receiver And the decreased CPU time of the memcpy() is observable with perf top. This is the `perf top -Ue task-clock` output when doing the test: before: Overhead Shared O Symbol 42.22% [kernel] [k] memcpy 35.00% [kernel] [k] __asm_copy_to_user 3.50% [kernel] [k] sifive_l2_flush64_range 2.30% [kernel] [k] stmmac_napi_poll_rx 1.11% [kernel] [k] memset after: Overhead Shared O Symbol 45.69% [kernel] [k] __asm_copy_to_user 29.06% [kernel] [k] memcpy 4.09% [kernel] [k] sifive_l2_flush64_range 2.77% [kernel] [k] stmmac_napi_poll_rx 1.24% [kernel] [k] memset Signed-off-by: Matteo Croce <mcroce@microsoft.com> Reported-by: kernel test robot <lkp@intel.com>
2021-12-26riscv: add ARCH_DMA_MINALIGN supportXianting Tian1-0/+2
Introduce ARCH_DMA_MINALIGN to riscv arch. Signed-off-by: Xianting Tian <xianting.tian@linux.alibaba.com>
2021-12-26reset: starfive-jh7100: Fix 32bit compilationEmil Renner Berthing1-0/+1
commit 299e6f788eab0b0aef97efb29ddc6971e7d0daf3 upstream. We need to include linux/io-64-nonatomic-lo-hi.h or readq/writeq won't be defined when compiling on 32bit architectures: On i386: ../drivers/reset/reset-starfive-jh7100.c: In function ‘jh7100_reset_update’: ../drivers/reset/reset-starfive-jh7100.c:81:10: error: implicit declaration of function ‘readq’; did you mean ‘readl’? [-Werror=implicit-function-declaration] value = readq(reg_assert); ^~~~~ ../drivers/reset/reset-starfive-jh7100.c:86:2: error: implicit declaration of function ‘writeq’; did you mean ‘writel’? [-Werror=implicit-function-declaration] writeq(value, reg_assert); ^~~~~~ On m68k: drivers/reset/reset-starfive-jh7100.c:81:17: error: implicit declaration of function 'readq'; did you mean 'readb'? [-Werror=implicit-function-declaration] drivers/reset/reset-starfive-jh7100.c:86:9: error: implicit declaration of function 'writeq'; did you mean 'writel'? [-Werror=implicit-function-declaration] cc1: all warnings being treated as errors make[3]: *** [scripts/Makefile.build:289: drivers/reset/reset-starfive-jh7100.o] Error 1 make[2]: *** [scripts/Makefile.build:572: drivers/reset] Error 2 make[1]: *** [Makefile:1969: drivers] Error 2 make: *** [Makefile:226: __sub-make] Error 2 Fixes: 0be3a1595bf8 ("reset: starfive-jh7100: Add StarFive JH7100 reset driver") Reported-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Link: https://lore.kernel.org/r/20211220121800.760846-1-kernel@esmil.dk' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-12-26RISC-V: Add BeagleV Starlight Beta device treeEmil Renner Berthing3-0/+167
commit a43676272a6e0b398781bc5337ca4cc187ba923d upstream. Add initial device tree for the BeagleV Starlight Beta board. About 300 of these boards were sent out as part of a now cancelled BeagleBoard.org project. I2C timing data is based on the device tree in the vendor u-boot port. Heartbeat LED added by Geert. Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Co-developed-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-12-26RISC-V: Add initial StarFive JH7100 device treeEmil Renner Berthing1-0/+230
commit ec85362fb121d0297b9f3bb56816ea6282c34fda upstream. Add initial device tree for the JH7100 RISC-V SoC by StarFive Ltd. This is a test chip for their upcoming JH7110 SoC. The CPU and cache data is based on the device tree in the vendor u-boot port. Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-12-26serial: 8250_dw: Add StarFive JH7100 quirkEmil Renner Berthing1-0/+3
commit b0ad20a3b64bf653a717860819691b262c0b2a2b upstream. On the StarFive JH7100 RISC-V SoC the UART core clocks can't be set to exactly 16 * 115200Hz and many other common bitrates. Trying this will only result in a higher input clock, but low enough that the UART's internal divisor can't come close enough to the baud rate target. So rather than try to set the input clock it's better to skip the clk_set_rate call and rely solely on the UART's internal divisor. Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-12-26dt-bindings: serial: snps-dw-apb-uart: Add JH7100 uartsEmil Renner Berthing1-0/+5
commit d0b65b1500973fef840dbc4bb9f9c237db2b761f upstream. Add compatibles for the StarFive JH7100 uarts. Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-12-26pinctrl: starfive: Add pinctrl driver for StarFive SoCsEmil Renner Berthing4-0/+1380
commit ec648f6b7686b716424e8e73eebb4c11ae199187 upstream. Add a combined pinctrl and GPIO driver for the JH7100 RISC-V SoC by StarFive Ltd. This is a test chip for their upcoming JH7110 SoC, which is said to feature only minor changes to these pinctrl/GPIO parts. For each "GPIO" there are two registers for configuring the output and output enable signals which may come from other peripherals. Among these are two special signals that are constant 0 and constant 1 respectively. Controlling the GPIOs from software is done by choosing one of these signals. In other words the same registers are used for both pin muxing and controlling the GPIOs, which makes it easier to combine the pinctrl and GPIO driver in one. I wrote the pinconf and pinmux parts, but the GPIO part of the code is based on the GPIO driver in the vendor tree written by Huan Feng with cleanups and fixes by Drew and me. Datasheet: https://github.com/starfive-tech/JH7100_Docs/blob/main/JH7100%20Data%20Sheet%20V01.01.04-EN%20(4-21-2021).pdf Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Co-developed-by: Huan Feng <huan.feng@starfivetech.com> Signed-off-by: Huan Feng <huan.feng@starfivetech.com> Co-developed-by: Drew Fustini <drew@beagleboard.org> Signed-off-by: Drew Fustini <drew@beagleboard.org> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-12-26dt-bindings: pinctrl: Add StarFive JH7100 bindingsEmil Renner Berthing1-0/+307
commit 7431b391df95f5b8d08fd0f9fa1a75cc038ee290 upstream. Add bindings for the GPIO/pin controller on the JH7100 RISC-V SoC by StarFive Ltd. This is a test chip for their upcoming JH7110 SoC. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-12-26dt-bindings: pinctrl: Add StarFive pinctrl definitionsEmil Renner Berthing1-0/+275
commit 3021114b3d172cf80c074c81425741f9e26c6679 upstream. Add definitons for pins and GPIO input, output and output enable signals on the StarFive JH7100 SoC. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-12-26reset: starfive-jh7100: Add StarFive JH7100 reset driverEmil Renner Berthing4-0/+187
commit 0be3a1595bf8c7f39153be02c9aae61dd2108576 upstream. Add a driver for the StarFive JH7100 reset controller. Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-12-26dt-bindings: reset: Add Starfive JH7100 reset bindingsEmil Renner Berthing1-0/+38
commit d7d456a5201d2e707318bbdc4fb69a3407eed29e upstream. Add bindings for the reset controller on the JH7100 RISC-V SoC by StarFive Ltd. This is a test chip for their upcoming JH7110 SoC. Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-12-26dt-bindings: reset: Add StarFive JH7100 reset definitionsGeert Uytterhoeven1-0/+126
commit 810e287e83b69ff8563bde15cae9120c802ac5d7 upstream. Add all resets for the StarFive JH7100 reset controller. Based on work by Ahmad Fatoum for Barebox, with "JH7100_" prefixes added to all definitions. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-12-26clk: starfive: Add JH7100 clock generator driverGeert Uytterhoeven6-0/+710
commit 4210be668a09ee20e4e1c7adf61b47d33d05c480 upstream. Add a driver for the StarFive JH7100 clock generator. Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Co-developed-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-12-26dt-bindings: clock: starfive: Add JH7100 bindingsGeert Uytterhoeven1-0/+56
commit af35098f4fcd1f9bfc58dc37479e0786a4d85e96 upstream. Add bindings for the clock generator on the JH7100 RISC-V SoC by StarFive Ltd. This is a test chip for their upcoming JH7110 SoC. Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-12-26dt-bindings: clock: starfive: Add JH7100 clock definitionsGeert Uytterhoeven1-0/+202
commit 38bb8a7264daf0ff5bb3024ae94bc465de78203d upstream. Add all clock outputs for the StarFive JH7100 clock generator. Based on work by Ahmad Fatoum for Barebox, with "JH7100_" prefixes added to all definitions. Acked-by: Rob Herring <robh@kernel.org> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-12-26dt-bindings: interrupt-controller: Add StarFive JH7100 plicEmil Renner Berthing1-0/+1
commit 9ac16169b4d4359d3832669bf06aab9e51184828 upstream. Add compatible string for StarFive JH7100 plic. Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-12-26dt-bindings: timer: Add StarFive JH7100 clintEmil Renner Berthing1-0/+1
commit 3234d3a1374308615c0cde5e83e52f6b644eaf53 upstream. Add compatible string for the StarFive JH7100 clint. Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-12-26RISC-V: Add StarFive SoC Kconfig optionEmil Renner Berthing1-0/+8
commit 3d24568b01c5a7a9e88f73f917477b60edb35bfe upstream. Add StarFive Kconfig option to select SoC specific and common drivers required for these SoCs. Select subsystems required to boot so the required drivers gets enabled by default. Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
2021-12-26dmaengine: dw-axi-dmac: Fix uninitialized variable in ↵Tim Gardner1-2/+2
axi_chan_block_xfer_start() commit 885633075847f475f26a29249d772cc0da85d8cd upstream. Coverity complains of an uninitialized variable: 5. uninit_use_in_call: Using uninitialized value config.dst_per when calling axi_chan_config_write. [show details] 6. uninit_use_in_call: Using uninitialized value config.hs_sel_src when calling axi_chan_config_write. [show details] CID 121164 (#1-3 of 3): Uninitialized scalar variable (UNINIT) 7. uninit_use_in_call: Using uninitialized value config.src_per when calling axi_chan_config_write. [show details] 418 axi_chan_config_write(chan, &config); Fix this by initializing the structure to 0 which should at least be benign in axi_chan_config_write(). Also fix what looks like a cut-n-paste error when initializing config.hs_sel_dst. Fixes: 824351668a413 ("dmaengine: dw-axi-dmac: support DMAX_NUM_CHANNELS > 8") Cc: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Cc: Vinod Koul <vkoul@kernel.org> Cc: dmaengine@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Tim Gardner <tim.gardner@canonical.com> Link: https://lore.kernel.org/r/20211025181656.31658-1-tim.gardner@canonical.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
generated by cgit v1.2.3 (git 2.39.0) at 2025-03-19 19:35:21 +0300