diff options
Diffstat (limited to 'tools/perf/pmu-events/arch/x86/jaketown/pipeline.json')
| -rw-r--r-- | tools/perf/pmu-events/arch/x86/jaketown/pipeline.json | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/tools/perf/pmu-events/arch/x86/jaketown/pipeline.json b/tools/perf/pmu-events/arch/x86/jaketown/pipeline.json index 87737c92c067..61a3db4d67d5 100644 --- a/tools/perf/pmu-events/arch/x86/jaketown/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/jaketown/pipeline.json @@ -410,8 +410,8 @@ }, { "BriefDescription": "Reference cycles when the core is not in halt state.", - "Counter": "Fixed counter 3", - "CounterHTOff": "Fixed counter 3", + "Counter": "Fixed counter 2", + "CounterHTOff": "Fixed counter 2", "EventName": "CPU_CLK_UNHALTED.REF_TSC", "PublicDescription": "This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.", "SampleAfterValue": "2000003", @@ -439,8 +439,8 @@ }, { "BriefDescription": "Core cycles when the thread is not in halt state.", - "Counter": "Fixed counter 2", - "CounterHTOff": "Fixed counter 2", + "Counter": "Fixed counter 1", + "CounterHTOff": "Fixed counter 1", "EventName": "CPU_CLK_UNHALTED.THREAD", "PublicDescription": "This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.", "SampleAfterValue": "2000003", @@ -542,8 +542,8 @@ }, { "BriefDescription": "Instructions retired from execution.", - "Counter": "Fixed counter 1", - "CounterHTOff": "Fixed counter 1", + "Counter": "Fixed counter 0", + "CounterHTOff": "Fixed counter 0", "EventName": "INST_RETIRED.ANY", "PublicDescription": "This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers.", "SampleAfterValue": "2000003", @@ -599,7 +599,7 @@ "UMask": "0x3" }, { - "BriefDescription": "Number of occurences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...).", + "BriefDescription": "Number of occurrences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...).", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", @@ -1199,4 +1199,4 @@ "SampleAfterValue": "2000003", "UMask": "0x1" } -]
\ No newline at end of file +] |