diff options
Diffstat (limited to 'sound/soc/fsl/fsl_xcvr.c')
| -rw-r--r-- | sound/soc/fsl/fsl_xcvr.c | 406 |
1 files changed, 315 insertions, 91 deletions
diff --git a/sound/soc/fsl/fsl_xcvr.c b/sound/soc/fsl/fsl_xcvr.c index 1e0bfd59d511..c59c1af5a98a 100644 --- a/sound/soc/fsl/fsl_xcvr.c +++ b/sound/soc/fsl/fsl_xcvr.c @@ -19,6 +19,7 @@ #include "imx-pcm.h" #define FSL_XCVR_CAPDS_SIZE 256 +#define SPDIF_NUM_RATES 7 enum fsl_xcvr_pll_verison { PLL_MX8MP, @@ -37,6 +38,8 @@ struct fsl_xcvr { const struct fsl_xcvr_soc_data *soc_data; struct platform_device *pdev; struct regmap *regmap; + struct regmap *regmap_phy; + struct regmap *regmap_pll; struct clk *ipg_clk; struct clk *pll_ipg_clk; struct clk *phy_clk; @@ -55,6 +58,8 @@ struct fsl_xcvr { u8 cap_ds[FSL_XCVR_CAPDS_SIZE]; struct work_struct work_rst; spinlock_t lock; /* Protect hw_reset and trigger */ + struct snd_pcm_hw_constraint_list spdif_constr_rates; + u32 spdif_constr_rates_list[SPDIF_NUM_RATES]; }; static const struct fsl_xcvr_pll_conf { @@ -171,7 +176,7 @@ static int fsl_xcvr_capds_put(struct snd_kcontrol *kcontrol, } static struct snd_kcontrol_new fsl_xcvr_earc_capds_kctl = { - .iface = SNDRV_CTL_ELEM_IFACE_PCM, + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = "Capabilities Data Structure", .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, .info = fsl_xcvr_type_capds_bytes_info, @@ -257,7 +262,7 @@ static int fsl_xcvr_ai_write(struct fsl_xcvr *xcvr, u8 reg, u32 data, bool phy) idx = BIT(phy ? 26 : 24); tidx = BIT(phy ? 27 : 25); - regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_CLR, 0xFF); + regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_CLR, 0xFF | FSL_XCVR_PHY_AI_CTRL_AI_RWB); regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET, reg); regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_WDATA, data); regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_TOG, idx); @@ -271,6 +276,59 @@ static int fsl_xcvr_ai_write(struct fsl_xcvr *xcvr, u8 reg, u32 data, bool phy) return ret; } +static int fsl_xcvr_ai_read(struct fsl_xcvr *xcvr, u8 reg, u32 *data, bool phy) +{ + struct device *dev = &xcvr->pdev->dev; + u32 val, idx, tidx; + int ret; + + idx = BIT(phy ? 26 : 24); + tidx = BIT(phy ? 27 : 25); + + regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_CLR, 0xFF | FSL_XCVR_PHY_AI_CTRL_AI_RWB); + regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET, reg | FSL_XCVR_PHY_AI_CTRL_AI_RWB); + regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_TOG, idx); + + ret = regmap_read_poll_timeout(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL, val, + (val & idx) == ((val & tidx) >> 1), + 10, 10000); + if (ret) + dev_err(dev, "AI timeout: failed to read %s reg 0x%02x\n", + phy ? "PHY" : "PLL", reg); + + regmap_read(xcvr->regmap, FSL_XCVR_PHY_AI_RDATA, data); + + return ret; +} + +static int fsl_xcvr_phy_reg_read(void *context, unsigned int reg, unsigned int *val) +{ + struct fsl_xcvr *xcvr = context; + + return fsl_xcvr_ai_read(xcvr, reg, val, 1); +} + +static int fsl_xcvr_phy_reg_write(void *context, unsigned int reg, unsigned int val) +{ + struct fsl_xcvr *xcvr = context; + + return fsl_xcvr_ai_write(xcvr, reg, val, 1); +} + +static int fsl_xcvr_pll_reg_read(void *context, unsigned int reg, unsigned int *val) +{ + struct fsl_xcvr *xcvr = context; + + return fsl_xcvr_ai_read(xcvr, reg, val, 0); +} + +static int fsl_xcvr_pll_reg_write(void *context, unsigned int reg, unsigned int val) +{ + struct fsl_xcvr *xcvr = context; + + return fsl_xcvr_ai_write(xcvr, reg, val, 0); +} + static int fsl_xcvr_en_phy_pll(struct fsl_xcvr *xcvr, u32 freq, bool tx) { struct device *dev = &xcvr->pdev->dev; @@ -303,55 +361,55 @@ static int fsl_xcvr_en_phy_pll(struct fsl_xcvr *xcvr, u32 freq, bool tx) switch (xcvr->soc_data->pll_ver) { case PLL_MX8MP: /* PLL: BANDGAP_SET: EN_VBG (enable bandgap) */ - fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_BANDGAP_SET, - FSL_XCVR_PLL_BANDGAP_EN_VBG, 0); + regmap_set_bits(xcvr->regmap_pll, FSL_XCVR_PLL_BANDGAP, + FSL_XCVR_PLL_BANDGAP_EN_VBG); /* PLL: CTRL0: DIV_INTEGER */ - fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0, fsl_xcvr_pll_cfg[i].mfi, 0); + regmap_write(xcvr->regmap_pll, FSL_XCVR_PLL_CTRL0, fsl_xcvr_pll_cfg[i].mfi); /* PLL: NUMERATOR: MFN */ - fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_NUM, fsl_xcvr_pll_cfg[i].mfn, 0); + regmap_write(xcvr->regmap_pll, FSL_XCVR_PLL_NUM, fsl_xcvr_pll_cfg[i].mfn); /* PLL: DENOMINATOR: MFD */ - fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_DEN, fsl_xcvr_pll_cfg[i].mfd, 0); + regmap_write(xcvr->regmap_pll, FSL_XCVR_PLL_DEN, fsl_xcvr_pll_cfg[i].mfd); /* PLL: CTRL0_SET: HOLD_RING_OFF, POWER_UP */ - fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_SET, - FSL_XCVR_PLL_CTRL0_HROFF | FSL_XCVR_PLL_CTRL0_PWP, 0); + regmap_set_bits(xcvr->regmap_pll, FSL_XCVR_PLL_CTRL0, + FSL_XCVR_PLL_CTRL0_HROFF | FSL_XCVR_PLL_CTRL0_PWP); udelay(25); /* PLL: CTRL0: Clear Hold Ring Off */ - fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_CLR, - FSL_XCVR_PLL_CTRL0_HROFF, 0); + regmap_clear_bits(xcvr->regmap_pll, FSL_XCVR_PLL_CTRL0, + FSL_XCVR_PLL_CTRL0_HROFF); udelay(100); if (tx) { /* TX is enabled for SPDIF only */ /* PLL: POSTDIV: PDIV0 */ - fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_PDIV, - FSL_XCVR_PLL_PDIVx(log2, 0), 0); + regmap_write(xcvr->regmap_pll, FSL_XCVR_PLL_PDIV, + FSL_XCVR_PLL_PDIVx(log2, 0)); /* PLL: CTRL_SET: CLKMUX0_EN */ - fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_SET, - FSL_XCVR_PLL_CTRL0_CM0_EN, 0); + regmap_set_bits(xcvr->regmap_pll, FSL_XCVR_PLL_CTRL0, + FSL_XCVR_PLL_CTRL0_CM0_EN); } else if (xcvr->mode == FSL_XCVR_MODE_EARC) { /* eARC RX */ /* PLL: POSTDIV: PDIV1 */ - fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_PDIV, - FSL_XCVR_PLL_PDIVx(log2, 1), 0); + regmap_write(xcvr->regmap_pll, FSL_XCVR_PLL_PDIV, + FSL_XCVR_PLL_PDIVx(log2, 1)); /* PLL: CTRL_SET: CLKMUX1_EN */ - fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_SET, - FSL_XCVR_PLL_CTRL0_CM1_EN, 0); + regmap_set_bits(xcvr->regmap_pll, FSL_XCVR_PLL_CTRL0, + FSL_XCVR_PLL_CTRL0_CM1_EN); } else { /* SPDIF / ARC RX */ /* PLL: POSTDIV: PDIV2 */ - fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_PDIV, - FSL_XCVR_PLL_PDIVx(log2, 2), 0); + regmap_write(xcvr->regmap_pll, FSL_XCVR_PLL_PDIV, + FSL_XCVR_PLL_PDIVx(log2, 2)); /* PLL: CTRL_SET: CLKMUX2_EN */ - fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_SET, - FSL_XCVR_PLL_CTRL0_CM2_EN, 0); + regmap_set_bits(xcvr->regmap_pll, FSL_XCVR_PLL_CTRL0, + FSL_XCVR_PLL_CTRL0_CM2_EN); } break; case PLL_MX95: val = fsl_xcvr_pll_cfg[i].mfi << FSL_XCVR_GP_PLL_DIV_MFI_SHIFT | div; - fsl_xcvr_ai_write(xcvr, FSL_XCVR_GP_PLL_DIV, val, 0); + regmap_write(xcvr->regmap_pll, FSL_XCVR_GP_PLL_DIV, val); val = fsl_xcvr_pll_cfg[i].mfn << FSL_XCVR_GP_PLL_NUMERATOR_MFN_SHIFT; - fsl_xcvr_ai_write(xcvr, FSL_XCVR_GP_PLL_NUMERATOR, val, 0); - fsl_xcvr_ai_write(xcvr, FSL_XCVR_GP_PLL_DENOMINATOR, - fsl_xcvr_pll_cfg[i].mfd, 0); + regmap_write(xcvr->regmap_pll, FSL_XCVR_GP_PLL_NUMERATOR, val); + regmap_write(xcvr->regmap_pll, FSL_XCVR_GP_PLL_DENOMINATOR, + fsl_xcvr_pll_cfg[i].mfd); val = FSL_XCVR_GP_PLL_CTRL_POWERUP | FSL_XCVR_GP_PLL_CTRL_CLKMUX_EN; - fsl_xcvr_ai_write(xcvr, FSL_XCVR_GP_PLL_CTRL, val, 0); + regmap_write(xcvr->regmap_pll, FSL_XCVR_GP_PLL_CTRL, val); break; default: dev_err(dev, "Error for PLL version %d\n", xcvr->soc_data->pll_ver); @@ -360,22 +418,22 @@ static int fsl_xcvr_en_phy_pll(struct fsl_xcvr *xcvr, u32 freq, bool tx) if (xcvr->mode == FSL_XCVR_MODE_EARC) { /* eARC mode */ /* PHY: CTRL_SET: TX_DIFF_OE, PHY_EN */ - fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET, - FSL_XCVR_PHY_CTRL_TSDIFF_OE | - FSL_XCVR_PHY_CTRL_PHY_EN, 1); + regmap_set_bits(xcvr->regmap_phy, FSL_XCVR_PHY_CTRL, + FSL_XCVR_PHY_CTRL_TSDIFF_OE | + FSL_XCVR_PHY_CTRL_PHY_EN); /* PHY: CTRL2_SET: EARC_TX_MODE */ - fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL2_SET, - FSL_XCVR_PHY_CTRL2_EARC_TXMS, 1); + regmap_set_bits(xcvr->regmap_phy, FSL_XCVR_PHY_CTRL2, + FSL_XCVR_PHY_CTRL2_EARC_TXMS); } else if (!tx) { /* SPDIF / ARC RX mode */ if (xcvr->mode == FSL_XCVR_MODE_SPDIF) /* PHY: CTRL_SET: SPDIF_EN */ - fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET, - FSL_XCVR_PHY_CTRL_SPDIF_EN, 1); + regmap_set_bits(xcvr->regmap_phy, FSL_XCVR_PHY_CTRL, + FSL_XCVR_PHY_CTRL_SPDIF_EN); else /* PHY: CTRL_SET: ARC RX setup */ - fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET, - FSL_XCVR_PHY_CTRL_PHY_EN | - FSL_XCVR_PHY_CTRL_RX_CM_EN | - fsl_xcvr_phy_arc_cfg[xcvr->arc_mode], 1); + regmap_set_bits(xcvr->regmap_phy, FSL_XCVR_PHY_CTRL, + FSL_XCVR_PHY_CTRL_PHY_EN | + FSL_XCVR_PHY_CTRL_RX_CM_EN | + fsl_xcvr_phy_arc_cfg[xcvr->arc_mode]); } dev_dbg(dev, "PLL Fexp: %u, Fout: %u, mfi: %u, mfn: %u, mfd: %d, div: %u, pdiv0: %u\n", @@ -416,17 +474,17 @@ static int fsl_xcvr_en_aud_pll(struct fsl_xcvr *xcvr, u32 freq) if (xcvr->mode == FSL_XCVR_MODE_EARC) { /* eARC mode */ /* PHY: CTRL_SET: TX_DIFF_OE, PHY_EN */ - fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET, - FSL_XCVR_PHY_CTRL_TSDIFF_OE | - FSL_XCVR_PHY_CTRL_PHY_EN, 1); + regmap_set_bits(xcvr->regmap_phy, FSL_XCVR_PHY_CTRL, + FSL_XCVR_PHY_CTRL_TSDIFF_OE | + FSL_XCVR_PHY_CTRL_PHY_EN); /* PHY: CTRL2_SET: EARC_TX_MODE */ - fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL2_SET, - FSL_XCVR_PHY_CTRL2_EARC_TXMS, 1); + regmap_set_bits(xcvr->regmap_phy, FSL_XCVR_PHY_CTRL2, + FSL_XCVR_PHY_CTRL2_EARC_TXMS); } else { /* SPDIF mode */ /* PHY: CTRL_SET: TX_CLK_AUD_SS | SPDIF_EN */ - fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET, - FSL_XCVR_PHY_CTRL_TX_CLK_AUD_SS | - FSL_XCVR_PHY_CTRL_SPDIF_EN, 1); + regmap_set_bits(xcvr->regmap_phy, FSL_XCVR_PHY_CTRL, + FSL_XCVR_PHY_CTRL_TX_CLK_AUD_SS | + FSL_XCVR_PHY_CTRL_SPDIF_EN); } dev_dbg(dev, "PLL Fexp: %u\n", freq); @@ -448,7 +506,7 @@ static int fsl_xcvr_prepare(struct snd_pcm_substream *substream, switch (xcvr->mode) { case FSL_XCVR_MODE_SPDIF: if (xcvr->soc_data->spdif_only && tx) { - ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_TX_DPTH_CTRL_SET, + ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_TX_DPTH_CTRL, FSL_XCVR_TX_DPTH_CTRL_BYPASS_FEM, FSL_XCVR_TX_DPTH_CTRL_BYPASS_FEM); if (ret < 0) { @@ -466,8 +524,8 @@ static int fsl_xcvr_prepare(struct snd_pcm_substream *substream, return ret; } - ret = regmap_write(xcvr->regmap, FSL_XCVR_TX_DPTH_CTRL_SET, - FSL_XCVR_TX_DPTH_CTRL_FRM_FMT); + ret = regmap_set_bits(xcvr->regmap, FSL_XCVR_TX_DPTH_CTRL, + FSL_XCVR_TX_DPTH_CTRL_FRM_FMT); if (ret < 0) { dev_err(dai->dev, "Failed to set TX_DPTH: %d\n", ret); return ret; @@ -484,11 +542,11 @@ static int fsl_xcvr_prepare(struct snd_pcm_substream *substream, * Clear RX FIFO, flip RX FIFO bits, * disable eARC related HW mode detects */ - ret = regmap_write(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL_SET, - FSL_XCVR_RX_DPTH_CTRL_STORE_FMT | - FSL_XCVR_RX_DPTH_CTRL_CLR_RX_FIFO | - FSL_XCVR_RX_DPTH_CTRL_COMP | - FSL_XCVR_RX_DPTH_CTRL_LAYB_CTRL); + ret = regmap_set_bits(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL, + FSL_XCVR_RX_DPTH_CTRL_STORE_FMT | + FSL_XCVR_RX_DPTH_CTRL_CLR_RX_FIFO | + FSL_XCVR_RX_DPTH_CTRL_COMP | + FSL_XCVR_RX_DPTH_CTRL_LAYB_CTRL); if (ret < 0) { dev_err(dai->dev, "Failed to set RX_DPTH: %d\n", ret); return ret; @@ -505,18 +563,18 @@ static int fsl_xcvr_prepare(struct snd_pcm_substream *substream, case FSL_XCVR_MODE_EARC: if (!tx) { /** Clear RX FIFO, flip RX FIFO bits */ - ret = regmap_write(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL_SET, - FSL_XCVR_RX_DPTH_CTRL_STORE_FMT | - FSL_XCVR_RX_DPTH_CTRL_CLR_RX_FIFO); + ret = regmap_set_bits(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL, + FSL_XCVR_RX_DPTH_CTRL_STORE_FMT | + FSL_XCVR_RX_DPTH_CTRL_CLR_RX_FIFO); if (ret < 0) { dev_err(dai->dev, "Failed to set RX_DPTH: %d\n", ret); return ret; } /** Enable eARC related HW mode detects */ - ret = regmap_write(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL_CLR, - FSL_XCVR_RX_DPTH_CTRL_COMP | - FSL_XCVR_RX_DPTH_CTRL_LAYB_CTRL); + ret = regmap_clear_bits(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL, + FSL_XCVR_RX_DPTH_CTRL_COMP | + FSL_XCVR_RX_DPTH_CTRL_LAYB_CTRL); if (ret < 0) { dev_err(dai->dev, "Failed to clr TX_DPTH: %d\n", ret); return ret; @@ -585,8 +643,12 @@ static int fsl_xcvr_startup(struct snd_pcm_substream *substream, switch (xcvr->mode) { case FSL_XCVR_MODE_SPDIF: case FSL_XCVR_MODE_ARC: - ret = fsl_xcvr_constr(substream, &fsl_xcvr_spdif_channels_constr, - &fsl_xcvr_spdif_rates_constr); + if (xcvr->soc_data->spdif_only && tx) + ret = fsl_xcvr_constr(substream, &fsl_xcvr_spdif_channels_constr, + &xcvr->spdif_constr_rates); + else + ret = fsl_xcvr_constr(substream, &fsl_xcvr_spdif_channels_constr, + &fsl_xcvr_spdif_rates_constr); break; case FSL_XCVR_MODE_EARC: ret = fsl_xcvr_constr(substream, &fsl_xcvr_earc_channels_constr, @@ -696,9 +758,9 @@ static int fsl_xcvr_trigger(struct snd_pcm_substream *substream, int cmd, } fallthrough; case FSL_XCVR_MODE_SPDIF: - ret = regmap_write(xcvr->regmap, - FSL_XCVR_TX_DPTH_CTRL_SET, - FSL_XCVR_TX_DPTH_CTRL_STRT_DATA_TX); + ret = regmap_set_bits(xcvr->regmap, + FSL_XCVR_TX_DPTH_CTRL, + FSL_XCVR_TX_DPTH_CTRL_STRT_DATA_TX); if (ret < 0) { dev_err(dai->dev, "Failed to start DATA_TX: %d\n", ret); goto release_lock; @@ -754,9 +816,9 @@ static int fsl_xcvr_trigger(struct snd_pcm_substream *substream, int cmd, if (tx) { switch (xcvr->mode) { case FSL_XCVR_MODE_SPDIF: - ret = regmap_write(xcvr->regmap, - FSL_XCVR_TX_DPTH_CTRL_CLR, - FSL_XCVR_TX_DPTH_CTRL_STRT_DATA_TX); + ret = regmap_clear_bits(xcvr->regmap, + FSL_XCVR_TX_DPTH_CTRL, + FSL_XCVR_TX_DPTH_CTRL_STRT_DATA_TX); if (ret < 0) { dev_err(dai->dev, "Failed to stop DATA_TX: %d\n", ret); goto release_lock; @@ -1169,6 +1231,7 @@ static bool fsl_xcvr_writeable_reg(struct device *dev, unsigned int reg) case FSL_XCVR_RX_DPTH_CNTR_CTRL_SET: case FSL_XCVR_RX_DPTH_CNTR_CTRL_CLR: case FSL_XCVR_RX_DPTH_CNTR_CTRL_TOG: + case FSL_XCVR_TX_DPTH_CTRL: case FSL_XCVR_TX_DPTH_CTRL_SET: case FSL_XCVR_TX_DPTH_CTRL_CLR: case FSL_XCVR_TX_DPTH_CTRL_TOG: @@ -1190,7 +1253,49 @@ static bool fsl_xcvr_writeable_reg(struct device *dev, unsigned int reg) static bool fsl_xcvr_volatile_reg(struct device *dev, unsigned int reg) { - return fsl_xcvr_readable_reg(dev, reg); + switch (reg) { + case FSL_XCVR_EXT_STATUS: + case FSL_XCVR_EXT_ISR: + case FSL_XCVR_EXT_ISR_SET: + case FSL_XCVR_EXT_ISR_CLR: + case FSL_XCVR_EXT_ISR_TOG: + case FSL_XCVR_ISR: + case FSL_XCVR_ISR_SET: + case FSL_XCVR_ISR_CLR: + case FSL_XCVR_ISR_TOG: + case FSL_XCVR_PHY_AI_CTRL: + case FSL_XCVR_PHY_AI_CTRL_SET: + case FSL_XCVR_PHY_AI_CTRL_CLR: + case FSL_XCVR_PHY_AI_CTRL_TOG: + case FSL_XCVR_PHY_AI_RDATA: + case FSL_XCVR_RX_CS_DATA_0: + case FSL_XCVR_RX_CS_DATA_1: + case FSL_XCVR_RX_CS_DATA_2: + case FSL_XCVR_RX_CS_DATA_3: + case FSL_XCVR_RX_CS_DATA_4: + case FSL_XCVR_RX_CS_DATA_5: + case FSL_XCVR_RX_DPTH_CNTR_CTRL: + case FSL_XCVR_RX_DPTH_CNTR_CTRL_SET: + case FSL_XCVR_RX_DPTH_CNTR_CTRL_CLR: + case FSL_XCVR_RX_DPTH_CNTR_CTRL_TOG: + case FSL_XCVR_RX_DPTH_TSCR: + case FSL_XCVR_RX_DPTH_BCR: + case FSL_XCVR_RX_DPTH_BCTR: + case FSL_XCVR_RX_DPTH_BCRR: + case FSL_XCVR_TX_DPTH_CNTR_CTRL: + case FSL_XCVR_TX_DPTH_CNTR_CTRL_SET: + case FSL_XCVR_TX_DPTH_CNTR_CTRL_CLR: + case FSL_XCVR_TX_DPTH_CNTR_CTRL_TOG: + case FSL_XCVR_TX_DPTH_TSCR: + case FSL_XCVR_TX_DPTH_BCR: + case FSL_XCVR_TX_DPTH_BCTR: + case FSL_XCVR_TX_DPTH_BCRR: + case FSL_XCVR_DEBUG_REG_0: + case FSL_XCVR_DEBUG_REG_1: + return true; + default: + return false; + } } static const struct regmap_config fsl_xcvr_regmap_cfg = { @@ -1206,6 +1311,49 @@ static const struct regmap_config fsl_xcvr_regmap_cfg = { .cache_type = REGCACHE_FLAT, }; +static const struct reg_default fsl_xcvr_phy_reg_defaults[] = { + { FSL_XCVR_PHY_CTRL, 0x58200804 }, + { FSL_XCVR_PHY_STATUS, 0x00000000 }, + { FSL_XCVR_PHY_ANALOG_TRIM, 0x00260F13 }, + { FSL_XCVR_PHY_SLEW_RATE_TRIM, 0x00000411 }, + { FSL_XCVR_PHY_DATA_TEST_DELAY, 0x00990000 }, + { FSL_XCVR_PHY_TEST_CTRL, 0x00000000 }, + { FSL_XCVR_PHY_DIFF_CDR_CTRL, 0x016D0009 }, + { FSL_XCVR_PHY_CTRL2, 0x80000000 }, +}; + +static const struct regmap_config fsl_xcvr_regmap_phy_cfg = { + .reg_bits = 8, + .reg_stride = 4, + .val_bits = 32, + .max_register = FSL_XCVR_PHY_CTRL2_TOG, + .reg_defaults = fsl_xcvr_phy_reg_defaults, + .num_reg_defaults = ARRAY_SIZE(fsl_xcvr_phy_reg_defaults), + .cache_type = REGCACHE_FLAT, + .reg_read = fsl_xcvr_phy_reg_read, + .reg_write = fsl_xcvr_phy_reg_write, +}; + +static const struct regmap_config fsl_xcvr_regmap_pllv0_cfg = { + .reg_bits = 8, + .reg_stride = 4, + .val_bits = 32, + .max_register = FSL_XCVR_PLL_STAT0_TOG, + .cache_type = REGCACHE_FLAT, + .reg_read = fsl_xcvr_pll_reg_read, + .reg_write = fsl_xcvr_pll_reg_write, +}; + +static const struct regmap_config fsl_xcvr_regmap_pllv1_cfg = { + .reg_bits = 8, + .reg_stride = 4, + .val_bits = 32, + .max_register = FSL_XCVR_GP_PLL_STATUS_TOG, + .cache_type = REGCACHE_FLAT, + .reg_read = fsl_xcvr_pll_reg_read, + .reg_write = fsl_xcvr_pll_reg_write, +}; + static void reset_rx_work(struct work_struct *work) { struct fsl_xcvr *xcvr = container_of(work, struct fsl_xcvr, work_rst); @@ -1405,6 +1553,15 @@ static int fsl_xcvr_probe(struct platform_device *pdev) fsl_asoc_get_pll_clocks(dev, &xcvr->pll8k_clk, &xcvr->pll11k_clk); + if (xcvr->soc_data->spdif_only) { + if (!(xcvr->pll8k_clk || xcvr->pll11k_clk)) + xcvr->pll8k_clk = xcvr->phy_clk; + fsl_asoc_constrain_rates(&xcvr->spdif_constr_rates, + &fsl_xcvr_spdif_rates_constr, + xcvr->pll8k_clk, xcvr->pll11k_clk, NULL, + xcvr->spdif_constr_rates_list); + } + xcvr->ram_addr = devm_platform_ioremap_resource_byname(pdev, "ram"); if (IS_ERR(xcvr->ram_addr)) return PTR_ERR(xcvr->ram_addr); @@ -1421,6 +1578,40 @@ static int fsl_xcvr_probe(struct platform_device *pdev) return PTR_ERR(xcvr->regmap); } + if (xcvr->soc_data->use_phy) { + xcvr->regmap_phy = devm_regmap_init(dev, NULL, xcvr, + &fsl_xcvr_regmap_phy_cfg); + if (IS_ERR(xcvr->regmap_phy)) { + dev_err(dev, "failed to init XCVR PHY regmap: %ld\n", + PTR_ERR(xcvr->regmap_phy)); + return PTR_ERR(xcvr->regmap_phy); + } + + switch (xcvr->soc_data->pll_ver) { + case PLL_MX8MP: + xcvr->regmap_pll = devm_regmap_init(dev, NULL, xcvr, + &fsl_xcvr_regmap_pllv0_cfg); + if (IS_ERR(xcvr->regmap_pll)) { + dev_err(dev, "failed to init XCVR PLL regmap: %ld\n", + PTR_ERR(xcvr->regmap_pll)); + return PTR_ERR(xcvr->regmap_pll); + } + break; + case PLL_MX95: + xcvr->regmap_pll = devm_regmap_init(dev, NULL, xcvr, + &fsl_xcvr_regmap_pllv1_cfg); + if (IS_ERR(xcvr->regmap_pll)) { + dev_err(dev, "failed to init XCVR PLL regmap: %ld\n", + PTR_ERR(xcvr->regmap_pll)); + return PTR_ERR(xcvr->regmap_pll); + } + break; + default: + dev_err(dev, "Error for PLL version %d\n", xcvr->soc_data->pll_ver); + return -EINVAL; + } + } + xcvr->reset = devm_reset_control_get_optional_exclusive(dev, NULL); if (IS_ERR(xcvr->reset)) { dev_err(dev, "failed to get XCVR reset control\n"); @@ -1454,6 +1645,10 @@ static int fsl_xcvr_probe(struct platform_device *pdev) platform_set_drvdata(pdev, xcvr); pm_runtime_enable(dev); regcache_cache_only(xcvr->regmap, true); + if (xcvr->soc_data->use_phy) { + regcache_cache_only(xcvr->regmap_phy, true); + regcache_cache_only(xcvr->regmap_pll, true); + } /* * Register platform component before registering cpu dai for there @@ -1492,7 +1687,8 @@ static int fsl_xcvr_runtime_suspend(struct device *dev) struct fsl_xcvr *xcvr = dev_get_drvdata(dev); int ret; - if (!xcvr->soc_data->spdif_only) { + if (!xcvr->soc_data->spdif_only && + xcvr->mode == FSL_XCVR_MODE_EARC) { /* Assert M0+ reset */ ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, FSL_XCVR_EXT_CTRL_CORE_RESET, @@ -1502,6 +1698,10 @@ static int fsl_xcvr_runtime_suspend(struct device *dev) } regcache_cache_only(xcvr->regmap, true); + if (xcvr->soc_data->use_phy) { + regcache_cache_only(xcvr->regmap_phy, true); + regcache_cache_only(xcvr->regmap_pll, true); + } clk_disable_unprepare(xcvr->spba_clk); clk_disable_unprepare(xcvr->phy_clk); @@ -1546,6 +1746,12 @@ static int fsl_xcvr_runtime_resume(struct device *dev) goto stop_phy_clk; } + ret = reset_control_deassert(xcvr->reset); + if (ret) { + dev_err(dev, "failed to deassert M0+ reset.\n"); + goto stop_spba_clk; + } + regcache_cache_only(xcvr->regmap, false); regcache_mark_dirty(xcvr->regmap); ret = regcache_sync(xcvr->regmap); @@ -1555,31 +1761,49 @@ static int fsl_xcvr_runtime_resume(struct device *dev) goto stop_spba_clk; } - if (xcvr->soc_data->spdif_only) - return 0; + if (xcvr->soc_data->use_phy) { + ret = regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET, + FSL_XCVR_PHY_AI_CTRL_AI_RESETN); + if (ret < 0) { + dev_err(dev, "Error while release PHY reset: %d\n", ret); + goto stop_spba_clk; + } - ret = reset_control_deassert(xcvr->reset); - if (ret) { - dev_err(dev, "failed to deassert M0+ reset.\n"); - goto stop_spba_clk; - } + regcache_cache_only(xcvr->regmap_phy, false); + regcache_mark_dirty(xcvr->regmap_phy); + ret = regcache_sync(xcvr->regmap_phy); + if (ret) { + dev_err(dev, "failed to sync phy regcache.\n"); + goto stop_spba_clk; + } - ret = fsl_xcvr_load_firmware(xcvr); - if (ret) { - dev_err(dev, "failed to load firmware.\n"); - goto stop_spba_clk; + regcache_cache_only(xcvr->regmap_pll, false); + regcache_mark_dirty(xcvr->regmap_pll); + ret = regcache_sync(xcvr->regmap_pll); + if (ret) { + dev_err(dev, "failed to sync pll regcache.\n"); + goto stop_spba_clk; + } } - /* Release M0+ reset */ - ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, - FSL_XCVR_EXT_CTRL_CORE_RESET, 0); - if (ret < 0) { - dev_err(dev, "M0+ core release failed: %d\n", ret); - goto stop_spba_clk; - } + if (xcvr->mode == FSL_XCVR_MODE_EARC) { + ret = fsl_xcvr_load_firmware(xcvr); + if (ret) { + dev_err(dev, "failed to load firmware.\n"); + goto stop_spba_clk; + } + + /* Release M0+ reset */ + ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, + FSL_XCVR_EXT_CTRL_CORE_RESET, 0); + if (ret < 0) { + dev_err(dev, "M0+ core release failed: %d\n", ret); + goto stop_spba_clk; + } - /* Let M0+ core complete firmware initialization */ - msleep(50); + /* Let M0+ core complete firmware initialization */ + msleep(50); + } return 0; |