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-rw-r--r--include/dt-bindings/bus/ti-sysc.h1
-rw-r--r--include/dt-bindings/clock/omap5.h3
-rw-r--r--include/dt-bindings/pinctrl/k3.h3
-rw-r--r--include/linux/platform_data/ti-sysc.h8
4 files changed, 13 insertions, 2 deletions
diff --git a/include/dt-bindings/bus/ti-sysc.h b/include/dt-bindings/bus/ti-sysc.h
index 7138384e2ef9..babd08a1d226 100644
--- a/include/dt-bindings/bus/ti-sysc.h
+++ b/include/dt-bindings/bus/ti-sysc.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0 */
/* TI sysc interconnect target module defines */
/* Generic sysc found on omap2 and later, also known as type1 */
diff --git a/include/dt-bindings/clock/omap5.h b/include/dt-bindings/clock/omap5.h
index f3283957f48d..e5411938983c 100644
--- a/include/dt-bindings/clock/omap5.h
+++ b/include/dt-bindings/clock/omap5.h
@@ -89,6 +89,9 @@
/* dss clocks */
#define OMAP5_DSS_CORE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
+/* gpu clocks */
+#define OMAP5_GPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
+
/* l3init clocks */
#define OMAP5_MMC1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
#define OMAP5_MMC2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
diff --git a/include/dt-bindings/pinctrl/k3.h b/include/dt-bindings/pinctrl/k3.h
index 45e11b6170ca..499de6216581 100644
--- a/include/dt-bindings/pinctrl/k3.h
+++ b/include/dt-bindings/pinctrl/k3.h
@@ -32,4 +32,7 @@
#define AM65X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
#define AM65X_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
+#define J721E_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
+#define J721E_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
+
#endif
diff --git a/include/linux/platform_data/ti-sysc.h b/include/linux/platform_data/ti-sysc.h
index 0c587d4fc718..b5b7a3423ca8 100644
--- a/include/linux/platform_data/ti-sysc.h
+++ b/include/linux/platform_data/ti-sysc.h
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
#ifndef __TI_SYSC_DATA_H__
#define __TI_SYSC_DATA_H__
@@ -47,6 +49,7 @@ struct sysc_regbits {
s8 emufree_shift;
};
+#define SYSC_MODULE_QUIRK_SGX BIT(18)
#define SYSC_MODULE_QUIRK_HDQ1W BIT(17)
#define SYSC_MODULE_QUIRK_I2C BIT(16)
#define SYSC_MODULE_QUIRK_WDT BIT(15)
@@ -70,7 +73,7 @@ struct sysc_regbits {
/**
* struct sysc_capabilities - capabilities for an interconnect target module
- *
+ * @type: sysc type identifier for the module
* @sysc_mask: bitmask of supported SYSCONFIG register bits
* @regbits: bitmask of SYSCONFIG register bits
* @mod_quirks: bitmask of module specific quirks
@@ -85,8 +88,9 @@ struct sysc_capabilities {
/**
* struct sysc_config - configuration for an interconnect target module
* @sysc_val: configured value for sysc register
+ * @syss_mask: configured mask value for SYSSTATUS register
* @midlemodes: bitmask of supported master idle modes
- * @sidlemodes: bitmask of supported master idle modes
+ * @sidlemodes: bitmask of supported slave idle modes
* @srst_udelay: optional delay needed after OCP soft reset
* @quirks: bitmask of enabled quirks
*/