diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/linux/fsl-diu-fb.h | 9 | ||||
| -rw-r--r-- | include/video/da8xx-fb.h | 25 | ||||
| -rw-r--r-- | include/video/omapdss.h | 91 | ||||
| -rw-r--r-- | include/video/samsung_fimd.h | 168 | ||||
| -rw-r--r-- | include/video/sh_mipi_dsi.h | 4 | ||||
| -rw-r--r-- | include/video/sh_mobile_lcdc.h | 1 |
6 files changed, 147 insertions, 151 deletions
diff --git a/include/linux/fsl-diu-fb.h b/include/linux/fsl-diu-fb.h index 11c16a1fb9e3..a1e8277120c7 100644 --- a/include/linux/fsl-diu-fb.h +++ b/include/linux/fsl-diu-fb.h @@ -47,6 +47,15 @@ struct aoi_display_offset { #define MFB_GET_PIXFMT _IOR('M', 8, __u32) /* + * The MPC5121 BSP comes with a gamma_set utility that initializes the + * gamma table. Unfortunately, it uses bad values for the IOCTL commands, + * but there's nothing we can do about it now. These ioctls are only + * supported on the MPC5121. + */ +#define MFB_SET_GAMMA _IOW('M', 1, __u8) +#define MFB_GET_GAMMA _IOR('M', 1, __u8) + +/* * The original definitions of MFB_SET_PIXFMT and MFB_GET_PIXFMT used the * wrong value for 'size' field of the ioctl. The current macros above use the * right size, but we still need to provide backwards compatibility, at least diff --git a/include/video/da8xx-fb.h b/include/video/da8xx-fb.h index 5a0e4f9efb53..f88825928dd1 100644 --- a/include/video/da8xx-fb.h +++ b/include/video/da8xx-fb.h @@ -12,10 +12,6 @@ #ifndef DA8XX_FB_H #define DA8XX_FB_H -enum panel_type { - QVGA = 0 -}; - enum panel_shade { MONOCHROME = 0, COLOR_ACTIVE, @@ -27,13 +23,6 @@ enum raster_load_mode { LOAD_PALETTE, }; -struct display_panel { - enum panel_type panel_type; /* QVGA */ - int max_bpp; - int min_bpp; - enum panel_shade panel_shade; -}; - struct da8xx_lcdc_platform_data { const char manu_name[10]; void *controller_data; @@ -42,7 +31,7 @@ struct da8xx_lcdc_platform_data { }; struct lcd_ctrl_config { - const struct display_panel *p_disp_panel; + enum panel_shade panel_shade; /* AC Bias Pin Frequency */ int ac_bias; @@ -68,18 +57,9 @@ struct lcd_ctrl_config { /* Mono 8-bit Mode: 1=D0-D7 or 0=D0-D3 */ unsigned char mono_8bit_mode; - /* Invert line clock */ - unsigned char invert_line_clock; - - /* Invert frame clock */ - unsigned char invert_frm_clock; - /* Horizontal and Vertical Sync Edge: 0=rising 1=falling */ unsigned char sync_edge; - /* Horizontal and Vertical Sync: Control: 0=ignore */ - unsigned char sync_ctrl; - /* Raster Data Order Select: 1=Most-to-least 0=Least-to-most */ unsigned char raster_order; @@ -103,5 +83,8 @@ struct lcd_sync_arg { #define FBIPUT_HSYNC _IOW('F', 9, int) #define FBIPUT_VSYNC _IOW('F', 10, int) +/* Proprietary FB_SYNC_ flags */ +#define FB_SYNC_CLK_INVERT 0x40000000 + #endif /* ifndef DA8XX_FB_H */ diff --git a/include/video/omapdss.h b/include/video/omapdss.h index 88c829466fc1..caefa093337d 100644 --- a/include/video/omapdss.h +++ b/include/video/omapdss.h @@ -21,6 +21,7 @@ #include <linux/list.h> #include <linux/kobject.h> #include <linux/device.h> +#include <linux/interrupt.h> #define DISPC_IRQ_FRAMEDONE (1 << 0) #define DISPC_IRQ_VSYNC (1 << 1) @@ -55,6 +56,7 @@ struct omap_dss_device; struct omap_overlay_manager; +struct dss_lcd_mgr_config; struct snd_aes_iec958; struct snd_cea_861_aud_if; @@ -158,7 +160,6 @@ enum omap_display_caps { enum omap_dss_display_state { OMAP_DSS_DISPLAY_DISABLED = 0, OMAP_DSS_DISPLAY_ACTIVE, - OMAP_DSS_DISPLAY_SUSPENDED, }; enum omap_dss_audio_state { @@ -621,10 +622,6 @@ struct omap_dss_device { struct { struct omap_video_timings timings; - int acbi; /* ac-bias pin transitions per interrupt */ - /* Unit: line clocks */ - int acb; /* ac-bias pin frequency */ - enum omap_dss_dsi_pixel_format dsi_pix_fmt; enum omap_dss_dsi_mode dsi_mode; struct omap_dss_dsi_videomode_timings dsi_vm_timings; @@ -686,8 +683,6 @@ struct omap_dss_driver { int (*enable)(struct omap_dss_device *display); void (*disable)(struct omap_dss_device *display); - int (*suspend)(struct omap_dss_device *display); - int (*resume)(struct omap_dss_device *display); int (*run_test)(struct omap_dss_device *display, int test); int (*update)(struct omap_dss_device *dssdev, @@ -745,6 +740,8 @@ struct omap_dss_driver { }; +enum omapdss_version omapdss_get_version(void); + int omap_dss_register_driver(struct omap_dss_driver *); void omap_dss_unregister_driver(struct omap_dss_driver *); @@ -754,10 +751,19 @@ void omap_dss_put_device(struct omap_dss_device *dssdev); struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from); struct omap_dss_device *omap_dss_find_device(void *data, int (*match)(struct omap_dss_device *dssdev, void *data)); +const char *omapdss_get_default_display_name(void); int omap_dss_start_device(struct omap_dss_device *dssdev); void omap_dss_stop_device(struct omap_dss_device *dssdev); +int dss_feat_get_num_mgrs(void); +int dss_feat_get_num_ovls(void); +enum omap_display_type dss_feat_get_supported_displays(enum omap_channel channel); +enum omap_dss_output_id dss_feat_get_supported_outputs(enum omap_channel channel); +enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane); + + + int omap_dss_get_num_overlay_managers(void); struct omap_overlay_manager *omap_dss_get_overlay_manager(int num); @@ -779,9 +785,43 @@ typedef void (*omap_dispc_isr_t) (void *arg, u32 mask); int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask); int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask); -int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout); -int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask, - unsigned long timeout); +u32 dispc_read_irqstatus(void); +void dispc_clear_irqstatus(u32 mask); +u32 dispc_read_irqenable(void); +void dispc_write_irqenable(u32 mask); + +int dispc_request_irq(irq_handler_t handler, void *dev_id); +void dispc_free_irq(void *dev_id); + +int dispc_runtime_get(void); +void dispc_runtime_put(void); + +void dispc_mgr_enable(enum omap_channel channel, bool enable); +bool dispc_mgr_is_enabled(enum omap_channel channel); +u32 dispc_mgr_get_vsync_irq(enum omap_channel channel); +u32 dispc_mgr_get_framedone_irq(enum omap_channel channel); +u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel); +bool dispc_mgr_go_busy(enum omap_channel channel); +void dispc_mgr_go(enum omap_channel channel); +void dispc_mgr_set_lcd_config(enum omap_channel channel, + const struct dss_lcd_mgr_config *config); +void dispc_mgr_set_timings(enum omap_channel channel, + const struct omap_video_timings *timings); +void dispc_mgr_setup(enum omap_channel channel, + const struct omap_overlay_manager_info *info); + +int dispc_ovl_check(enum omap_plane plane, enum omap_channel channel, + const struct omap_overlay_info *oi, + const struct omap_video_timings *timings, + int *x_predecim, int *y_predecim); + +int dispc_ovl_enable(enum omap_plane plane, bool enable); +bool dispc_ovl_enabled(enum omap_plane plane); +void dispc_ovl_set_channel_out(enum omap_plane plane, + enum omap_channel channel); +int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi, + bool replication, const struct omap_video_timings *mgr_timings, + bool mem_to_mem); #define to_dss_driver(x) container_of((x), struct omap_dss_driver, driver) #define to_dss_device(x) container_of((x), struct omap_dss_device, dev) @@ -840,4 +880,35 @@ void omapdss_rfbi_set_data_lines(struct omap_dss_device *dssdev, void omapdss_rfbi_set_interface_timings(struct omap_dss_device *dssdev, struct rfbi_timings *timings); +int omapdss_compat_init(void); +void omapdss_compat_uninit(void); + +struct dss_mgr_ops { + void (*start_update)(struct omap_overlay_manager *mgr); + int (*enable)(struct omap_overlay_manager *mgr); + void (*disable)(struct omap_overlay_manager *mgr); + void (*set_timings)(struct omap_overlay_manager *mgr, + const struct omap_video_timings *timings); + void (*set_lcd_config)(struct omap_overlay_manager *mgr, + const struct dss_lcd_mgr_config *config); + int (*register_framedone_handler)(struct omap_overlay_manager *mgr, + void (*handler)(void *), void *data); + void (*unregister_framedone_handler)(struct omap_overlay_manager *mgr, + void (*handler)(void *), void *data); +}; + +int dss_install_mgr_ops(const struct dss_mgr_ops *mgr_ops); +void dss_uninstall_mgr_ops(void); + +void dss_mgr_set_timings(struct omap_overlay_manager *mgr, + const struct omap_video_timings *timings); +void dss_mgr_set_lcd_config(struct omap_overlay_manager *mgr, + const struct dss_lcd_mgr_config *config); +int dss_mgr_enable(struct omap_overlay_manager *mgr); +void dss_mgr_disable(struct omap_overlay_manager *mgr); +void dss_mgr_start_update(struct omap_overlay_manager *mgr); +int dss_mgr_register_framedone_handler(struct omap_overlay_manager *mgr, + void (*handler)(void *), void *data); +void dss_mgr_unregister_framedone_handler(struct omap_overlay_manager *mgr, + void (*handler)(void *), void *data); #endif diff --git a/include/video/samsung_fimd.h b/include/video/samsung_fimd.h index 7ae6c07f2ef8..e7554486a2b7 100644 --- a/include/video/samsung_fimd.h +++ b/include/video/samsung_fimd.h @@ -24,12 +24,15 @@ #define VIDCON0 (0x00) #define VIDCON0_INTERLACE (1 << 29) -#define VIDCON0_VIDOUT_MASK (0x3 << 26) +#define VIDCON0_VIDOUT_MASK (0x7 << 26) #define VIDCON0_VIDOUT_SHIFT (26) #define VIDCON0_VIDOUT_RGB (0x0 << 26) #define VIDCON0_VIDOUT_TV (0x1 << 26) #define VIDCON0_VIDOUT_I80_LDI0 (0x2 << 26) #define VIDCON0_VIDOUT_I80_LDI1 (0x3 << 26) +#define VIDCON0_VIDOUT_WB_RGB (0x4 << 26) +#define VIDCON0_VIDOUT_WB_I80_LDI0 (0x6 << 26) +#define VIDCON0_VIDOUT_WB_I80_LDI1 (0x7 << 26) #define VIDCON0_L1_DATA_MASK (0x7 << 23) #define VIDCON0_L1_DATA_SHIFT (23) @@ -77,6 +80,7 @@ #define VIDCON1_LINECNT_MASK (0x7ff << 16) #define VIDCON1_LINECNT_SHIFT (16) #define VIDCON1_LINECNT_GET(_v) (((_v) >> 16) & 0x7ff) +#define VIDCON1_FSTATUS_EVEN (1 << 15) #define VIDCON1_VSTATUS_MASK (0x3 << 13) #define VIDCON1_VSTATUS_SHIFT (13) #define VIDCON1_VSTATUS_VSYNC (0x0 << 13) @@ -116,6 +120,7 @@ /* VIDTCON0 */ +#define VIDTCON0 (0x10) #define VIDTCON0_VBPDE_MASK (0xff << 24) #define VIDTCON0_VBPDE_SHIFT (24) #define VIDTCON0_VBPDE_LIMIT (0xff) @@ -138,6 +143,7 @@ /* VIDTCON1 */ +#define VIDTCON1 (0x14) #define VIDTCON1_VFPDE_MASK (0xff << 24) #define VIDTCON1_VFPDE_SHIFT (24) #define VIDTCON1_VFPDE_LIMIT (0xff) @@ -159,6 +165,7 @@ #define VIDTCON1_HSPW(_x) ((_x) << 0) #define VIDTCON2 (0x18) +#define VIDTCON2 (0x18) #define VIDTCON2_LINEVAL_E(_x) ((((_x) & 0x800) >> 11) << 23) #define VIDTCON2_LINEVAL_MASK (0x7ff << 11) #define VIDTCON2_LINEVAL_SHIFT (11) @@ -173,18 +180,27 @@ /* WINCONx */ - +#define WINCON(_win) (0x20 + ((_win) * 4)) +#define WINCONx_CSCWIDTH_MASK (0x3 << 26) +#define WINCONx_CSCWIDTH_SHIFT (26) +#define WINCONx_CSCWIDTH_WIDE (0x0 << 26) +#define WINCONx_CSCWIDTH_NARROW (0x3 << 26) +#define WINCONx_ENLOCAL (1 << 22) +#define WINCONx_BUFSTATUS (1 << 21) +#define WINCONx_BUFSEL (1 << 20) +#define WINCONx_BUFAUTOEN (1 << 19) #define WINCONx_BITSWP (1 << 18) #define WINCONx_BYTSWP (1 << 17) #define WINCONx_HAWSWP (1 << 16) #define WINCONx_WSWP (1 << 15) +#define WINCONx_YCbCr (1 << 13) #define WINCONx_BURSTLEN_MASK (0x3 << 9) #define WINCONx_BURSTLEN_SHIFT (9) #define WINCONx_BURSTLEN_16WORD (0x0 << 9) #define WINCONx_BURSTLEN_8WORD (0x1 << 9) #define WINCONx_BURSTLEN_4WORD (0x2 << 9) - #define WINCONx_ENWIN (1 << 0) + #define WINCON0_BPPMODE_MASK (0xf << 2) #define WINCON0_BPPMODE_SHIFT (2) #define WINCON0_BPPMODE_1BPP (0x0 << 2) @@ -196,9 +212,8 @@ #define WINCON0_BPPMODE_18BPP_666 (0x8 << 2) #define WINCON0_BPPMODE_24BPP_888 (0xb << 2) +#define WINCON1_LOCALSEL_CAMIF (1 << 23) #define WINCON1_BLD_PIX (1 << 6) - -#define WINCON1_ALPHA_SEL (1 << 1) #define WINCON1_BPPMODE_MASK (0xf << 2) #define WINCON1_BPPMODE_SHIFT (2) #define WINCON1_BPPMODE_1BPP (0x0 << 2) @@ -216,6 +231,7 @@ #define WINCON1_BPPMODE_24BPP_A1887 (0xc << 2) #define WINCON1_BPPMODE_25BPP_A1888 (0xd << 2) #define WINCON1_BPPMODE_28BPP_A4888 (0xd << 2) +#define WINCON1_ALPHA_SEL (1 << 1) /* S5PV210 */ #define SHADOWCON (0x34) @@ -225,6 +241,9 @@ /* Local input channels (windows 0-2) */ #define SHADOWCON_CHx_LOCAL_ENABLE(_win) (1 << (5 + (_win))) +/* VIDOSDx */ + +#define VIDOSD_BASE (0x40) #define VIDOSDxA_TOPLEFT_X_E(_x) ((((_x) & 0x800) >> 11) << 23) #define VIDOSDxA_TOPLEFT_X_MASK (0x7ff << 11) #define VIDOSDxA_TOPLEFT_X_SHIFT (11) @@ -293,6 +312,7 @@ /* Interrupt controls and status */ +#define VIDINTCON0 (0x130) #define VIDINTCON0_FIFOINTERVAL_MASK (0x3f << 20) #define VIDINTCON0_FIFOINTERVAL_SHIFT (20) #define VIDINTCON0_FIFOINTERVAL_LIMIT (0x3f) @@ -321,6 +341,9 @@ #define VIDINTCON0_FIFIOSEL_SHIFT (5) #define VIDINTCON0_FIFIOSEL_WINDOW0 (0x1 << 5) #define VIDINTCON0_FIFIOSEL_WINDOW1 (0x2 << 5) +#define VIDINTCON0_FIFIOSEL_WINDOW2 (0x10 << 5) +#define VIDINTCON0_FIFIOSEL_WINDOW3 (0x20 << 5) +#define VIDINTCON0_FIFIOSEL_WINDOW4 (0x40 << 5) #define VIDINTCON0_FIFOLEVEL_MASK (0x7 << 2) #define VIDINTCON0_FIFOLEVEL_SHIFT (2) @@ -357,16 +380,39 @@ #define WxKEYCON1_COLVAL_LIMIT (0xffffff) #define WxKEYCON1_COLVAL(_x) ((_x) << 0) +/* Dithering control */ +#define DITHMODE (0x170) +#define DITHMODE_R_POS_MASK (0x3 << 5) +#define DITHMODE_R_POS_SHIFT (5) +#define DITHMODE_R_POS_8BIT (0x0 << 5) +#define DITHMODE_R_POS_6BIT (0x1 << 5) +#define DITHMODE_R_POS_5BIT (0x2 << 5) +#define DITHMODE_G_POS_MASK (0x3 << 3) +#define DITHMODE_G_POS_SHIFT (3) +#define DITHMODE_G_POS_8BIT (0x0 << 3) +#define DITHMODE_G_POS_6BIT (0x1 << 3) +#define DITHMODE_G_POS_5BIT (0x2 << 3) +#define DITHMODE_B_POS_MASK (0x3 << 1) +#define DITHMODE_B_POS_SHIFT (1) +#define DITHMODE_B_POS_8BIT (0x0 << 1) +#define DITHMODE_B_POS_6BIT (0x1 << 1) +#define DITHMODE_B_POS_5BIT (0x2 << 1) +#define DITHMODE_DITH_EN (1 << 0) /* Window blanking (MAP) */ - +#define WINxMAP(_win) (0x180 + ((_win) * 4)) #define WINxMAP_MAP (1 << 24) #define WINxMAP_MAP_COLOUR_MASK (0xffffff << 0) #define WINxMAP_MAP_COLOUR_SHIFT (0) #define WINxMAP_MAP_COLOUR_LIMIT (0xffffff) #define WINxMAP_MAP_COLOUR(_x) ((_x) << 0) +/* Winodw palette control */ +#define WPALCON (0x1A0) #define WPALCON_PAL_UPDATE (1 << 9) +#define WPALCON_W4PAL_16BPP_A555 (1 << 8) +#define WPALCON_W3PAL_16BPP_A555 (1 << 7) +#define WPALCON_W2PAL_16BPP_A555 (1 << 6) #define WPALCON_W1PAL_MASK (0x7 << 3) #define WPALCON_W1PAL_SHIFT (3) #define WPALCON_W1PAL_25BPP_A888 (0x0 << 3) @@ -376,7 +422,6 @@ #define WPALCON_W1PAL_18BPP (0x4 << 3) #define WPALCON_W1PAL_16BPP_A555 (0x5 << 3) #define WPALCON_W1PAL_16BPP_565 (0x6 << 3) - #define WPALCON_W0PAL_MASK (0x7 << 0) #define WPALCON_W0PAL_SHIFT (0) #define WPALCON_W0PAL_25BPP_A888 (0x0 << 0) @@ -394,115 +439,6 @@ #define BLENDCON_NEW_4BIT_ALPHA_VALUE (0 << 0) #define S3C_FB_MAX_WIN (5) /* number of hardware windows available. */ -#define VIDCON1_FSTATUS_EVEN (1 << 15) - -/* Video timing controls */ -#define VIDTCON0 (0x10) -#define VIDTCON1 (0x14) -#define VIDTCON2 (0x18) - -/* Window position controls */ - -#define WINCON(_win) (0x20 + ((_win) * 4)) - -/* OSD1 and OSD4 do not have register D */ - -#define VIDOSD_BASE (0x40) - -#define VIDINTCON0 (0x130) - -/* WINCONx */ - -#define WINCONx_CSCWIDTH_MASK (0x3 << 26) -#define WINCONx_CSCWIDTH_SHIFT (26) -#define WINCONx_CSCWIDTH_WIDE (0x0 << 26) -#define WINCONx_CSCWIDTH_NARROW (0x3 << 26) - -#define WINCONx_ENLOCAL (1 << 22) -#define WINCONx_BUFSTATUS (1 << 21) -#define WINCONx_BUFSEL (1 << 20) -#define WINCONx_BUFAUTOEN (1 << 19) -#define WINCONx_YCbCr (1 << 13) - -#define WINCON1_LOCALSEL_CAMIF (1 << 23) - -#define WINCON2_LOCALSEL_CAMIF (1 << 23) -#define WINCON2_BLD_PIX (1 << 6) - -#define WINCON2_ALPHA_SEL (1 << 1) -#define WINCON2_BPPMODE_MASK (0xf << 2) -#define WINCON2_BPPMODE_SHIFT (2) -#define WINCON2_BPPMODE_1BPP (0x0 << 2) -#define WINCON2_BPPMODE_2BPP (0x1 << 2) -#define WINCON2_BPPMODE_4BPP (0x2 << 2) -#define WINCON2_BPPMODE_8BPP_1232 (0x4 << 2) -#define WINCON2_BPPMODE_16BPP_565 (0x5 << 2) -#define WINCON2_BPPMODE_16BPP_A1555 (0x6 << 2) -#define WINCON2_BPPMODE_16BPP_I1555 (0x7 << 2) -#define WINCON2_BPPMODE_18BPP_666 (0x8 << 2) -#define WINCON2_BPPMODE_18BPP_A1665 (0x9 << 2) -#define WINCON2_BPPMODE_19BPP_A1666 (0xa << 2) -#define WINCON2_BPPMODE_24BPP_888 (0xb << 2) -#define WINCON2_BPPMODE_24BPP_A1887 (0xc << 2) -#define WINCON2_BPPMODE_25BPP_A1888 (0xd << 2) -#define WINCON2_BPPMODE_28BPP_A4888 (0xd << 2) - -#define WINCON3_BLD_PIX (1 << 6) - -#define WINCON3_ALPHA_SEL (1 << 1) -#define WINCON3_BPPMODE_MASK (0xf << 2) -#define WINCON3_BPPMODE_SHIFT (2) -#define WINCON3_BPPMODE_1BPP (0x0 << 2) -#define WINCON3_BPPMODE_2BPP (0x1 << 2) -#define WINCON3_BPPMODE_4BPP (0x2 << 2) -#define WINCON3_BPPMODE_16BPP_565 (0x5 << 2) -#define WINCON3_BPPMODE_16BPP_A1555 (0x6 << 2) -#define WINCON3_BPPMODE_16BPP_I1555 (0x7 << 2) -#define WINCON3_BPPMODE_18BPP_666 (0x8 << 2) -#define WINCON3_BPPMODE_18BPP_A1665 (0x9 << 2) -#define WINCON3_BPPMODE_19BPP_A1666 (0xa << 2) -#define WINCON3_BPPMODE_24BPP_888 (0xb << 2) -#define WINCON3_BPPMODE_24BPP_A1887 (0xc << 2) -#define WINCON3_BPPMODE_25BPP_A1888 (0xd << 2) -#define WINCON3_BPPMODE_28BPP_A4888 (0xd << 2) - -#define VIDINTCON0_FIFIOSEL_WINDOW2 (0x10 << 5) -#define VIDINTCON0_FIFIOSEL_WINDOW3 (0x20 << 5) -#define VIDINTCON0_FIFIOSEL_WINDOW4 (0x40 << 5) - -#define DITHMODE (0x170) -#define WINxMAP(_win) (0x180 + ((_win) * 4)) - - -#define DITHMODE_R_POS_MASK (0x3 << 5) -#define DITHMODE_R_POS_SHIFT (5) -#define DITHMODE_R_POS_8BIT (0x0 << 5) -#define DITHMODE_R_POS_6BIT (0x1 << 5) -#define DITHMODE_R_POS_5BIT (0x2 << 5) - -#define DITHMODE_G_POS_MASK (0x3 << 3) -#define DITHMODE_G_POS_SHIFT (3) -#define DITHMODE_G_POS_8BIT (0x0 << 3) -#define DITHMODE_G_POS_6BIT (0x1 << 3) -#define DITHMODE_G_POS_5BIT (0x2 << 3) - -#define DITHMODE_B_POS_MASK (0x3 << 1) -#define DITHMODE_B_POS_SHIFT (1) -#define DITHMODE_B_POS_8BIT (0x0 << 1) -#define DITHMODE_B_POS_6BIT (0x1 << 1) -#define DITHMODE_B_POS_5BIT (0x2 << 1) - -#define DITHMODE_DITH_EN (1 << 0) - -#define WPALCON (0x1A0) - -/* Palette control */ -/* Note for S5PC100: you can still use those macros on WPALCON (aka WPALCON_L), - * but make sure that WPALCON_H W2PAL-W4PAL entries are zeroed out */ -#define WPALCON_W4PAL_16BPP_A555 (1 << 8) -#define WPALCON_W3PAL_16BPP_A555 (1 << 7) -#define WPALCON_W2PAL_16BPP_A555 (1 << 6) - /* Notes on per-window bpp settings * diff --git a/include/video/sh_mipi_dsi.h b/include/video/sh_mipi_dsi.h index 06c67fbc4eee..a01f197e6ac1 100644 --- a/include/video/sh_mipi_dsi.h +++ b/include/video/sh_mipi_dsi.h @@ -25,8 +25,6 @@ enum sh_mipi_dsi_data_fmt { MIPI_YUV420, }; -struct sh_mobile_lcdc_chan_cfg; - #define SH_MIPI_DSI_HSABM (1 << 0) #define SH_MIPI_DSI_HBPBM (1 << 1) #define SH_MIPI_DSI_HFPBM (1 << 2) @@ -47,7 +45,7 @@ struct sh_mobile_lcdc_chan_cfg; struct sh_mipi_dsi_info { enum sh_mipi_dsi_data_fmt data_format; - struct sh_mobile_lcdc_chan_cfg *lcd_chan; + int channel; int lane; unsigned long flags; u32 clksrc; diff --git a/include/video/sh_mobile_lcdc.h b/include/video/sh_mobile_lcdc.h index ff43ffc1aab2..2605fa8adb9c 100644 --- a/include/video/sh_mobile_lcdc.h +++ b/include/video/sh_mobile_lcdc.h @@ -163,7 +163,6 @@ struct sh_mobile_lcdc_bl_info { const char *name; int max_brightness; int (*set_brightness)(int brightness); - int (*get_brightness)(void); }; struct sh_mobile_lcdc_overlay_cfg { |