diff options
Diffstat (limited to 'include/dt-bindings')
168 files changed, 10348 insertions, 411 deletions
diff --git a/include/dt-bindings/bus/ti-sysc.h b/include/dt-bindings/bus/ti-sysc.h index 2c005376ac0e..7138384e2ef9 100644 --- a/include/dt-bindings/bus/ti-sysc.h +++ b/include/dt-bindings/bus/ti-sysc.h @@ -15,6 +15,8 @@ /* SmartReflex sysc found on 36xx and later */ #define SYSC_OMAP3_SR_ENAWAKEUP (1 << 26) +#define SYSC_DRA7_MCAN_ENAWAKEUP (1 << 4) + /* SYSCONFIG STANDBYMODE/MIDLEMODE/SIDLEMODE supported by hardware */ #define SYSC_IDLE_FORCE 0 #define SYSC_IDLE_NO 1 diff --git a/include/dt-bindings/clock/actions,s700-cmu.h b/include/dt-bindings/clock/actions,s700-cmu.h new file mode 100644 index 000000000000..3e1942996724 --- /dev/null +++ b/include/dt-bindings/clock/actions,s700-cmu.h @@ -0,0 +1,118 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Device Tree binding constants for Actions Semi S700 Clock Management Unit + * + * Copyright (c) 2014 Actions Semi Inc. + * Author: David Liu <liuwei@actions-semi.com> + * + * Author: Pathiban Nallathambi <pn@denx.de> + * Author: Saravanan Sekar <sravanhome@gmail.com> + */ + +#ifndef __DT_BINDINGS_CLOCK_S700_H +#define __DT_BINDINGS_CLOCK_S700_H + +#define CLK_NONE 0 + +/* pll clocks */ +#define CLK_CORE_PLL 1 +#define CLK_DEV_PLL 2 +#define CLK_DDR_PLL 3 +#define CLK_NAND_PLL 4 +#define CLK_DISPLAY_PLL 5 +#define CLK_TVOUT_PLL 6 +#define CLK_CVBS_PLL 7 +#define CLK_AUDIO_PLL 8 +#define CLK_ETHERNET_PLL 9 + +/* system clock */ +#define CLK_CPU 10 +#define CLK_DEV 11 +#define CLK_AHB 12 +#define CLK_APB 13 +#define CLK_DMAC 14 +#define CLK_NOC0_CLK_MUX 15 +#define CLK_NOC1_CLK_MUX 16 +#define CLK_HP_CLK_MUX 17 +#define CLK_HP_CLK_DIV 18 +#define CLK_NOC1_CLK_DIV 19 +#define CLK_NOC0 20 +#define CLK_NOC1 21 +#define CLK_SENOR_SRC 22 + +/* peripheral device clock */ +#define CLK_GPIO 23 +#define CLK_TIMER 24 +#define CLK_DSI 25 +#define CLK_CSI 26 +#define CLK_SI 27 +#define CLK_DE 28 +#define CLK_HDE 29 +#define CLK_VDE 30 +#define CLK_VCE 31 +#define CLK_NAND 32 +#define CLK_SD0 33 +#define CLK_SD1 34 +#define CLK_SD2 35 + +#define CLK_UART0 36 +#define CLK_UART1 37 +#define CLK_UART2 38 +#define CLK_UART3 39 +#define CLK_UART4 40 +#define CLK_UART5 41 +#define CLK_UART6 42 + +#define CLK_PWM0 43 +#define CLK_PWM1 44 +#define CLK_PWM2 45 +#define CLK_PWM3 46 +#define CLK_PWM4 47 +#define CLK_PWM5 48 +#define CLK_GPU3D 49 + +#define CLK_I2C0 50 +#define CLK_I2C1 51 +#define CLK_I2C2 52 +#define CLK_I2C3 53 + +#define CLK_SPI0 54 +#define CLK_SPI1 55 +#define CLK_SPI2 56 +#define CLK_SPI3 57 + +#define CLK_USB3_480MPLL0 58 +#define CLK_USB3_480MPHY0 59 +#define CLK_USB3_5GPHY 60 +#define CLK_USB3_CCE 61 +#define CLK_USB3_MAC 62 + +#define CLK_LCD 63 +#define CLK_HDMI_AUDIO 64 +#define CLK_I2SRX 65 +#define CLK_I2STX 66 + +#define CLK_SENSOR0 67 +#define CLK_SENSOR1 68 + +#define CLK_HDMI_DEV 69 + +#define CLK_ETHERNET 70 +#define CLK_RMII_REF 71 + +#define CLK_USB2H0_PLLEN 72 +#define CLK_USB2H0_PHY 73 +#define CLK_USB2H0_CCE 74 +#define CLK_USB2H1_PLLEN 75 +#define CLK_USB2H1_PHY 76 +#define CLK_USB2H1_CCE 77 + +#define CLK_TVOUT 78 + +#define CLK_THERMAL_SENSOR 79 + +#define CLK_IRC_SWITCH 80 +#define CLK_PCM1 81 +#define CLK_NR_CLKS (CLK_PCM1 + 1) + +#endif /* __DT_BINDINGS_CLOCK_S700_H */ diff --git a/include/dt-bindings/clock/actions,s900-cmu.h b/include/dt-bindings/clock/actions,s900-cmu.h new file mode 100644 index 000000000000..7c1251565f43 --- /dev/null +++ b/include/dt-bindings/clock/actions,s900-cmu.h @@ -0,0 +1,129 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Device Tree binding constants for Actions Semi S900 Clock Management Unit +// +// Copyright (c) 2014 Actions Semi Inc. +// Copyright (c) 2018 Linaro Ltd. + +#ifndef __DT_BINDINGS_CLOCK_S900_CMU_H +#define __DT_BINDINGS_CLOCK_S900_CMU_H + +#define CLK_NONE 0 + +/* fixed rate clocks */ +#define CLK_LOSC 1 +#define CLK_HOSC 2 + +/* pll clocks */ +#define CLK_CORE_PLL 3 +#define CLK_DEV_PLL 4 +#define CLK_DDR_PLL 5 +#define CLK_NAND_PLL 6 +#define CLK_DISPLAY_PLL 7 +#define CLK_DSI_PLL 8 +#define CLK_ASSIST_PLL 9 +#define CLK_AUDIO_PLL 10 + +/* system clock */ +#define CLK_CPU 15 +#define CLK_DEV 16 +#define CLK_NOC 17 +#define CLK_NOC_MUX 18 +#define CLK_NOC_DIV 19 +#define CLK_AHB 20 +#define CLK_APB 21 +#define CLK_DMAC 22 + +/* peripheral device clock */ +#define CLK_GPIO 23 + +#define CLK_BISP 24 +#define CLK_CSI0 25 +#define CLK_CSI1 26 + +#define CLK_DE0 27 +#define CLK_DE1 28 +#define CLK_DE2 29 +#define CLK_DE3 30 +#define CLK_DSI 32 + +#define CLK_GPU 33 +#define CLK_GPU_CORE 34 +#define CLK_GPU_MEM 35 +#define CLK_GPU_SYS 36 + +#define CLK_HDE 37 +#define CLK_I2C0 38 +#define CLK_I2C1 39 +#define CLK_I2C2 40 +#define CLK_I2C3 41 +#define CLK_I2C4 42 +#define CLK_I2C5 43 +#define CLK_I2SRX 44 +#define CLK_I2STX 45 +#define CLK_IMX 46 +#define CLK_LCD 47 +#define CLK_NAND0 48 +#define CLK_NAND1 49 +#define CLK_PWM0 50 +#define CLK_PWM1 51 +#define CLK_PWM2 52 +#define CLK_PWM3 53 +#define CLK_PWM4 54 +#define CLK_PWM5 55 +#define CLK_SD0 56 +#define CLK_SD1 57 +#define CLK_SD2 58 +#define CLK_SD3 59 +#define CLK_SENSOR 60 +#define CLK_SPEED_SENSOR 61 +#define CLK_SPI0 62 +#define CLK_SPI1 63 +#define CLK_SPI2 64 +#define CLK_SPI3 65 +#define CLK_THERMAL_SENSOR 66 +#define CLK_UART0 67 +#define CLK_UART1 68 +#define CLK_UART2 69 +#define CLK_UART3 70 +#define CLK_UART4 71 +#define CLK_UART5 72 +#define CLK_UART6 73 +#define CLK_VCE 74 +#define CLK_VDE 75 + +#define CLK_USB3_480MPLL0 76 +#define CLK_USB3_480MPHY0 77 +#define CLK_USB3_5GPHY 78 +#define CLK_USB3_CCE 79 +#define CLK_USB3_MAC 80 + +#define CLK_TIMER 83 + +#define CLK_HDMI_AUDIO 84 + +#define CLK_24M 85 + +#define CLK_EDP 86 + +#define CLK_24M_EDP 87 +#define CLK_EDP_PLL 88 +#define CLK_EDP_LINK 89 + +#define CLK_USB2H0_PLLEN 90 +#define CLK_USB2H0_PHY 91 +#define CLK_USB2H0_CCE 92 +#define CLK_USB2H1_PLLEN 93 +#define CLK_USB2H1_PHY 94 +#define CLK_USB2H1_CCE 95 + +#define CLK_DDR0 96 +#define CLK_DDR1 97 +#define CLK_DMM 98 + +#define CLK_ETH_MAC 99 +#define CLK_RMII_REF 100 + +#define CLK_NR_CLKS (CLK_RMII_REF + 1) + +#endif /* __DT_BINDINGS_CLOCK_S900_CMU_H */ diff --git a/include/dt-bindings/clock/am3.h b/include/dt-bindings/clock/am3.h index b396f00e481d..86a8806e2140 100644 --- a/include/dt-bindings/clock/am3.h +++ b/include/dt-bindings/clock/am3.h @@ -16,6 +16,8 @@ #define AM3_CLKCTRL_OFFSET 0x0 #define AM3_CLKCTRL_INDEX(offset) ((offset) - AM3_CLKCTRL_OFFSET) +/* XXX: Compatibility part begin, remove this once compatibility support is no longer needed */ + /* l4_per clocks */ #define AM3_L4_PER_CLKCTRL_OFFSET 0x14 #define AM3_L4_PER_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_PER_CLKCTRL_OFFSET) @@ -105,4 +107,121 @@ #define AM3_L4_CEFUSE_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_CEFUSE_CLKCTRL_OFFSET) #define AM3_CEFUSE_CLKCTRL AM3_L4_CEFUSE_CLKCTRL_INDEX(0x20) +/* XXX: Compatibility part end */ + +/* l4ls clocks */ +#define AM3_L4LS_CLKCTRL_OFFSET 0x38 +#define AM3_L4LS_CLKCTRL_INDEX(offset) ((offset) - AM3_L4LS_CLKCTRL_OFFSET) +#define AM3_L4LS_UART6_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x38) +#define AM3_L4LS_MMC1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x3c) +#define AM3_L4LS_ELM_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x40) +#define AM3_L4LS_I2C3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x44) +#define AM3_L4LS_I2C2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x48) +#define AM3_L4LS_SPI0_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x4c) +#define AM3_L4LS_SPI1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x50) +#define AM3_L4LS_L4_LS_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x60) +#define AM3_L4LS_UART2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x6c) +#define AM3_L4LS_UART3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x70) +#define AM3_L4LS_UART4_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x74) +#define AM3_L4LS_UART5_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x78) +#define AM3_L4LS_TIMER7_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x7c) +#define AM3_L4LS_TIMER2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x80) +#define AM3_L4LS_TIMER3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x84) +#define AM3_L4LS_TIMER4_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x88) +#define AM3_L4LS_RNG_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x90) +#define AM3_L4LS_GPIO2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xac) +#define AM3_L4LS_GPIO3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xb0) +#define AM3_L4LS_GPIO4_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xb4) +#define AM3_L4LS_D_CAN0_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xc0) +#define AM3_L4LS_D_CAN1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xc4) +#define AM3_L4LS_EPWMSS1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xcc) +#define AM3_L4LS_EPWMSS0_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xd4) +#define AM3_L4LS_EPWMSS2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xd8) +#define AM3_L4LS_TIMER5_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xec) +#define AM3_L4LS_TIMER6_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xf0) +#define AM3_L4LS_MMC2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xf4) +#define AM3_L4LS_SPINLOCK_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x10c) +#define AM3_L4LS_MAILBOX_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x110) +#define AM3_L4LS_OCPWP_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x130) + +/* l3s clocks */ +#define AM3_L3S_CLKCTRL_OFFSET 0x1c +#define AM3_L3S_CLKCTRL_INDEX(offset) ((offset) - AM3_L3S_CLKCTRL_OFFSET) +#define AM3_L3S_USB_OTG_HS_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x1c) +#define AM3_L3S_GPMC_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x30) +#define AM3_L3S_MCASP0_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x34) +#define AM3_L3S_MCASP1_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x68) +#define AM3_L3S_MMC3_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0xf8) + +/* l3 clocks */ +#define AM3_L3_CLKCTRL_OFFSET 0x24 +#define AM3_L3_CLKCTRL_INDEX(offset) ((offset) - AM3_L3_CLKCTRL_OFFSET) +#define AM3_L3_TPTC0_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x24) +#define AM3_L3_EMIF_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x28) +#define AM3_L3_OCMCRAM_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x2c) +#define AM3_L3_AES_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x94) +#define AM3_L3_SHAM_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xa0) +#define AM3_L3_TPCC_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xbc) +#define AM3_L3_L3_INSTR_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xdc) +#define AM3_L3_L3_MAIN_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xe0) +#define AM3_L3_TPTC1_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xfc) +#define AM3_L3_TPTC2_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x100) + +/* l4hs clocks */ +#define AM3_L4HS_CLKCTRL_OFFSET 0x120 +#define AM3_L4HS_CLKCTRL_INDEX(offset) ((offset) - AM3_L4HS_CLKCTRL_OFFSET) +#define AM3_L4HS_L4_HS_CLKCTRL AM3_L4HS_CLKCTRL_INDEX(0x120) + +/* pruss_ocp clocks */ +#define AM3_PRUSS_OCP_CLKCTRL_OFFSET 0xe8 +#define AM3_PRUSS_OCP_CLKCTRL_INDEX(offset) ((offset) - AM3_PRUSS_OCP_CLKCTRL_OFFSET) +#define AM3_PRUSS_OCP_PRUSS_CLKCTRL AM3_PRUSS_OCP_CLKCTRL_INDEX(0xe8) + +/* cpsw_125mhz clocks */ +#define AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL AM3_CLKCTRL_INDEX(0x14) + +/* lcdc clocks */ +#define AM3_LCDC_CLKCTRL_OFFSET 0x18 +#define AM3_LCDC_CLKCTRL_INDEX(offset) ((offset) - AM3_LCDC_CLKCTRL_OFFSET) +#define AM3_LCDC_LCDC_CLKCTRL AM3_LCDC_CLKCTRL_INDEX(0x18) + +/* clk_24mhz clocks */ +#define AM3_CLK_24MHZ_CLKCTRL_OFFSET 0x14c +#define AM3_CLK_24MHZ_CLKCTRL_INDEX(offset) ((offset) - AM3_CLK_24MHZ_CLKCTRL_OFFSET) +#define AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL AM3_CLK_24MHZ_CLKCTRL_INDEX(0x14c) + +/* l4_wkup clocks */ +#define AM3_L4_WKUP_CONTROL_CLKCTRL AM3_CLKCTRL_INDEX(0x4) +#define AM3_L4_WKUP_GPIO1_CLKCTRL AM3_CLKCTRL_INDEX(0x8) +#define AM3_L4_WKUP_L4_WKUP_CLKCTRL AM3_CLKCTRL_INDEX(0xc) +#define AM3_L4_WKUP_UART1_CLKCTRL AM3_CLKCTRL_INDEX(0xb4) +#define AM3_L4_WKUP_I2C1_CLKCTRL AM3_CLKCTRL_INDEX(0xb8) +#define AM3_L4_WKUP_ADC_TSC_CLKCTRL AM3_CLKCTRL_INDEX(0xbc) +#define AM3_L4_WKUP_SMARTREFLEX0_CLKCTRL AM3_CLKCTRL_INDEX(0xc0) +#define AM3_L4_WKUP_TIMER1_CLKCTRL AM3_CLKCTRL_INDEX(0xc4) +#define AM3_L4_WKUP_SMARTREFLEX1_CLKCTRL AM3_CLKCTRL_INDEX(0xc8) +#define AM3_L4_WKUP_WD_TIMER2_CLKCTRL AM3_CLKCTRL_INDEX(0xd4) + +/* l3_aon clocks */ +#define AM3_L3_AON_CLKCTRL_OFFSET 0x14 +#define AM3_L3_AON_CLKCTRL_INDEX(offset) ((offset) - AM3_L3_AON_CLKCTRL_OFFSET) +#define AM3_L3_AON_DEBUGSS_CLKCTRL AM3_L3_AON_CLKCTRL_INDEX(0x14) + +/* l4_wkup_aon clocks */ +#define AM3_L4_WKUP_AON_CLKCTRL_OFFSET 0xb0 +#define AM3_L4_WKUP_AON_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_WKUP_AON_CLKCTRL_OFFSET) +#define AM3_L4_WKUP_AON_WKUP_M3_CLKCTRL AM3_L4_WKUP_AON_CLKCTRL_INDEX(0xb0) + +/* mpu clocks */ +#define AM3_MPU_MPU_CLKCTRL AM3_CLKCTRL_INDEX(0x4) + +/* l4_rtc clocks */ +#define AM3_L4_RTC_RTC_CLKCTRL AM3_CLKCTRL_INDEX(0x0) + +/* gfx_l3 clocks */ +#define AM3_GFX_L3_GFX_CLKCTRL AM3_CLKCTRL_INDEX(0x4) + +/* l4_cefuse clocks */ +#define AM3_L4_CEFUSE_CEFUSE_CLKCTRL AM3_CLKCTRL_INDEX(0x20) + #endif diff --git a/include/dt-bindings/clock/am4.h b/include/dt-bindings/clock/am4.h index d21df00b3270..0f545b5afd60 100644 --- a/include/dt-bindings/clock/am4.h +++ b/include/dt-bindings/clock/am4.h @@ -16,6 +16,8 @@ #define AM4_CLKCTRL_OFFSET 0x20 #define AM4_CLKCTRL_INDEX(offset) ((offset) - AM4_CLKCTRL_OFFSET) +/* XXX: Compatibility part begin, remove this once compatibility support is no longer needed */ + /* l4_wkup clocks */ #define AM4_ADC_TSC_CLKCTRL AM4_CLKCTRL_INDEX(0x120) #define AM4_L4_WKUP_CLKCTRL AM4_CLKCTRL_INDEX(0x220) @@ -110,4 +112,134 @@ #define AM4_DSS_CORE_CLKCTRL AM4_CLKCTRL_INDEX(0xa20) #define AM4_CPGMAC0_CLKCTRL AM4_CLKCTRL_INDEX(0xb20) +/* XXX: Compatibility part end. */ + +/* l3s_tsc clocks */ +#define AM4_L3S_TSC_CLKCTRL_OFFSET 0x120 +#define AM4_L3S_TSC_CLKCTRL_INDEX(offset) ((offset) - AM4_L3S_TSC_CLKCTRL_OFFSET) +#define AM4_L3S_TSC_ADC_TSC_CLKCTRL AM4_L3S_TSC_CLKCTRL_INDEX(0x120) + +/* l4_wkup_aon clocks */ +#define AM4_L4_WKUP_AON_CLKCTRL_OFFSET 0x228 +#define AM4_L4_WKUP_AON_CLKCTRL_INDEX(offset) ((offset) - AM4_L4_WKUP_AON_CLKCTRL_OFFSET) +#define AM4_L4_WKUP_AON_WKUP_M3_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x228) +#define AM4_L4_WKUP_AON_COUNTER_32K_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x230) + +/* l4_wkup clocks */ +#define AM4_L4_WKUP_CLKCTRL_OFFSET 0x220 +#define AM4_L4_WKUP_CLKCTRL_INDEX(offset) ((offset) - AM4_L4_WKUP_CLKCTRL_OFFSET) +#define AM4_L4_WKUP_L4_WKUP_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x220) +#define AM4_L4_WKUP_TIMER1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x328) +#define AM4_L4_WKUP_WD_TIMER2_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x338) +#define AM4_L4_WKUP_I2C1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x340) +#define AM4_L4_WKUP_UART1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x348) +#define AM4_L4_WKUP_SMARTREFLEX0_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x350) +#define AM4_L4_WKUP_SMARTREFLEX1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x358) +#define AM4_L4_WKUP_CONTROL_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x360) +#define AM4_L4_WKUP_GPIO1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x368) + +/* mpu clocks */ +#define AM4_MPU_MPU_CLKCTRL AM4_CLKCTRL_INDEX(0x20) + +/* gfx_l3 clocks */ +#define AM4_GFX_L3_GFX_CLKCTRL AM4_CLKCTRL_INDEX(0x20) + +/* l4_rtc clocks */ +#define AM4_L4_RTC_RTC_CLKCTRL AM4_CLKCTRL_INDEX(0x20) + +/* l3 clocks */ +#define AM4_L3_L3_MAIN_CLKCTRL AM4_CLKCTRL_INDEX(0x20) +#define AM4_L3_AES_CLKCTRL AM4_CLKCTRL_INDEX(0x28) +#define AM4_L3_DES_CLKCTRL AM4_CLKCTRL_INDEX(0x30) +#define AM4_L3_L3_INSTR_CLKCTRL AM4_CLKCTRL_INDEX(0x40) +#define AM4_L3_OCMCRAM_CLKCTRL AM4_CLKCTRL_INDEX(0x50) +#define AM4_L3_SHAM_CLKCTRL AM4_CLKCTRL_INDEX(0x58) +#define AM4_L3_TPCC_CLKCTRL AM4_CLKCTRL_INDEX(0x78) +#define AM4_L3_TPTC0_CLKCTRL AM4_CLKCTRL_INDEX(0x80) +#define AM4_L3_TPTC1_CLKCTRL AM4_CLKCTRL_INDEX(0x88) +#define AM4_L3_TPTC2_CLKCTRL AM4_CLKCTRL_INDEX(0x90) +#define AM4_L3_L4_HS_CLKCTRL AM4_CLKCTRL_INDEX(0xa0) + +/* l3s clocks */ +#define AM4_L3S_CLKCTRL_OFFSET 0x68 +#define AM4_L3S_CLKCTRL_INDEX(offset) ((offset) - AM4_L3S_CLKCTRL_OFFSET) +#define AM4_L3S_VPFE0_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x68) +#define AM4_L3S_VPFE1_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x70) +#define AM4_L3S_GPMC_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x220) +#define AM4_L3S_MCASP0_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x238) +#define AM4_L3S_MCASP1_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x240) +#define AM4_L3S_MMC3_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x248) +#define AM4_L3S_QSPI_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x258) +#define AM4_L3S_USB_OTG_SS0_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x260) +#define AM4_L3S_USB_OTG_SS1_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x268) + +/* pruss_ocp clocks */ +#define AM4_PRUSS_OCP_CLKCTRL_OFFSET 0x320 +#define AM4_PRUSS_OCP_CLKCTRL_INDEX(offset) ((offset) - AM4_PRUSS_OCP_CLKCTRL_OFFSET) +#define AM4_PRUSS_OCP_PRUSS_CLKCTRL AM4_PRUSS_OCP_CLKCTRL_INDEX(0x320) + +/* l4ls clocks */ +#define AM4_L4LS_CLKCTRL_OFFSET 0x420 +#define AM4_L4LS_CLKCTRL_INDEX(offset) ((offset) - AM4_L4LS_CLKCTRL_OFFSET) +#define AM4_L4LS_L4_LS_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x420) +#define AM4_L4LS_D_CAN0_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x428) +#define AM4_L4LS_D_CAN1_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x430) +#define AM4_L4LS_EPWMSS0_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x438) +#define AM4_L4LS_EPWMSS1_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x440) +#define AM4_L4LS_EPWMSS2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x448) +#define AM4_L4LS_EPWMSS3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x450) +#define AM4_L4LS_EPWMSS4_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x458) +#define AM4_L4LS_EPWMSS5_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x460) +#define AM4_L4LS_ELM_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x468) +#define AM4_L4LS_GPIO2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x478) +#define AM4_L4LS_GPIO3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x480) +#define AM4_L4LS_GPIO4_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x488) +#define AM4_L4LS_GPIO5_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x490) +#define AM4_L4LS_GPIO6_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x498) +#define AM4_L4LS_HDQ1W_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4a0) +#define AM4_L4LS_I2C2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4a8) +#define AM4_L4LS_I2C3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4b0) +#define AM4_L4LS_MAILBOX_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4b8) +#define AM4_L4LS_MMC1_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4c0) +#define AM4_L4LS_MMC2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4c8) +#define AM4_L4LS_RNG_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x4e0) +#define AM4_L4LS_SPI0_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x500) +#define AM4_L4LS_SPI1_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x508) +#define AM4_L4LS_SPI2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x510) +#define AM4_L4LS_SPI3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x518) +#define AM4_L4LS_SPI4_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x520) +#define AM4_L4LS_SPINLOCK_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x528) +#define AM4_L4LS_TIMER2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x530) +#define AM4_L4LS_TIMER3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x538) +#define AM4_L4LS_TIMER4_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x540) +#define AM4_L4LS_TIMER5_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x548) +#define AM4_L4LS_TIMER6_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x550) +#define AM4_L4LS_TIMER7_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x558) +#define AM4_L4LS_TIMER8_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x560) +#define AM4_L4LS_TIMER9_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x568) +#define AM4_L4LS_TIMER10_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x570) +#define AM4_L4LS_TIMER11_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x578) +#define AM4_L4LS_UART2_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x580) +#define AM4_L4LS_UART3_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x588) +#define AM4_L4LS_UART4_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x590) +#define AM4_L4LS_UART5_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x598) +#define AM4_L4LS_UART6_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x5a0) +#define AM4_L4LS_OCP2SCP0_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x5b8) +#define AM4_L4LS_OCP2SCP1_CLKCTRL AM4_L4LS_CLKCTRL_INDEX(0x5c0) + +/* emif clocks */ +#define AM4_EMIF_CLKCTRL_OFFSET 0x720 +#define AM4_EMIF_CLKCTRL_INDEX(offset) ((offset) - AM4_EMIF_CLKCTRL_OFFSET) +#define AM4_EMIF_EMIF_CLKCTRL AM4_EMIF_CLKCTRL_INDEX(0x720) + +/* dss clocks */ +#define AM4_DSS_CLKCTRL_OFFSET 0xa20 +#define AM4_DSS_CLKCTRL_INDEX(offset) ((offset) - AM4_DSS_CLKCTRL_OFFSET) +#define AM4_DSS_DSS_CORE_CLKCTRL AM4_DSS_CLKCTRL_INDEX(0xa20) + +/* cpsw_125mhz clocks */ +#define AM4_CPSW_125MHZ_CLKCTRL_OFFSET 0xb20 +#define AM4_CPSW_125MHZ_CLKCTRL_INDEX(offset) ((offset) - AM4_CPSW_125MHZ_CLKCTRL_OFFSET) +#define AM4_CPSW_125MHZ_CPGMAC0_CLKCTRL AM4_CPSW_125MHZ_CLKCTRL_INDEX(0xb20) + #endif diff --git a/include/dt-bindings/clock/aspeed-clock.h b/include/dt-bindings/clock/aspeed-clock.h index d3558d897a4d..f43738607d77 100644 --- a/include/dt-bindings/clock/aspeed-clock.h +++ b/include/dt-bindings/clock/aspeed-clock.h @@ -25,7 +25,7 @@ #define ASPEED_CLK_GATE_RSACLK 19 #define ASPEED_CLK_GATE_UART3CLK 20 #define ASPEED_CLK_GATE_UART4CLK 21 -#define ASPEED_CLK_GATE_SDCLKCLK 22 +#define ASPEED_CLK_GATE_SDCLK 22 #define ASPEED_CLK_GATE_LHCCLK 23 #define ASPEED_CLK_HPLL 24 #define ASPEED_CLK_AHB 25 @@ -38,6 +38,7 @@ #define ASPEED_CLK_MAC 32 #define ASPEED_CLK_BCLK 33 #define ASPEED_CLK_MPLL 34 +#define ASPEED_CLK_24M 35 #define ASPEED_RESET_XDMA 0 #define ASPEED_RESET_MCTP 1 @@ -45,8 +46,9 @@ #define ASPEED_RESET_JTAG_MASTER 3 #define ASPEED_RESET_MIC 4 #define ASPEED_RESET_PWM 5 -#define ASPEED_RESET_PCIVGA 6 +#define ASPEED_RESET_PECI 6 #define ASPEED_RESET_I2C 7 #define ASPEED_RESET_AHB 8 +#define ASPEED_RESET_CRT1 9 #endif diff --git a/include/dt-bindings/clock/at91.h b/include/dt-bindings/clock/at91.h index ab3ee241d10c..ed30da28d820 100644 --- a/include/dt-bindings/clock/at91.h +++ b/include/dt-bindings/clock/at91.h @@ -9,6 +9,20 @@ #ifndef _DT_BINDINGS_CLK_AT91_H #define _DT_BINDINGS_CLK_AT91_H +#define PMC_TYPE_CORE 0 +#define PMC_TYPE_SYSTEM 1 +#define PMC_TYPE_PERIPHERAL 2 +#define PMC_TYPE_GCK 3 + +#define PMC_SLOW 0 +#define PMC_MCK 1 +#define PMC_UTMI 2 +#define PMC_MAIN 3 +#define PMC_MCK2 4 +#define PMC_I2S0_MUX 5 +#define PMC_I2S1_MUX 6 + +#ifndef AT91_PMC_MOSCS #define AT91_PMC_MOSCS 0 /* MOSCS Flag */ #define AT91_PMC_LOCKA 1 /* PLLA Lock */ #define AT91_PMC_LOCKB 2 /* PLLB Lock */ @@ -19,5 +33,6 @@ #define AT91_PMC_MOSCRCS 17 /* Main On-Chip RC */ #define AT91_PMC_CFDEV 18 /* Clock Failure Detector Event */ #define AT91_PMC_GCKRDY 24 /* Generated Clocks */ +#endif #endif diff --git a/include/dt-bindings/clock/axg-aoclkc.h b/include/dt-bindings/clock/axg-aoclkc.h new file mode 100644 index 000000000000..61955016a55b --- /dev/null +++ b/include/dt-bindings/clock/axg-aoclkc.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ +/* + * Copyright (c) 2016 BayLibre, SAS + * Author: Neil Armstrong <narmstrong@baylibre.com> + * + * Copyright (c) 2018 Amlogic, inc. + * Author: Qiufang Dai <qiufang.dai@amlogic.com> + */ + +#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK +#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK + +#define CLKID_AO_REMOTE 0 +#define CLKID_AO_I2C_MASTER 1 +#define CLKID_AO_I2C_SLAVE 2 +#define CLKID_AO_UART1 3 +#define CLKID_AO_UART2 4 +#define CLKID_AO_IR_BLASTER 5 +#define CLKID_AO_SAR_ADC 6 +#define CLKID_AO_CLK81 7 +#define CLKID_AO_SAR_ADC_SEL 8 +#define CLKID_AO_SAR_ADC_DIV 9 +#define CLKID_AO_SAR_ADC_CLK 10 +#define CLKID_AO_ALT_XTAL 11 + +#endif diff --git a/include/dt-bindings/clock/axg-audio-clkc.h b/include/dt-bindings/clock/axg-audio-clkc.h new file mode 100644 index 000000000000..fd9c362099d9 --- /dev/null +++ b/include/dt-bindings/clock/axg-audio-clkc.h @@ -0,0 +1,94 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright (c) 2018 Baylibre SAS. + * Author: Jerome Brunet <jbrunet@baylibre.com> + */ + +#ifndef __AXG_AUDIO_CLKC_BINDINGS_H +#define __AXG_AUDIO_CLKC_BINDINGS_H + +#define AUD_CLKID_SLV_SCLK0 9 +#define AUD_CLKID_SLV_SCLK1 10 +#define AUD_CLKID_SLV_SCLK2 11 +#define AUD_CLKID_SLV_SCLK3 12 +#define AUD_CLKID_SLV_SCLK4 13 +#define AUD_CLKID_SLV_SCLK5 14 +#define AUD_CLKID_SLV_SCLK6 15 +#define AUD_CLKID_SLV_SCLK7 16 +#define AUD_CLKID_SLV_SCLK8 17 +#define AUD_CLKID_SLV_SCLK9 18 +#define AUD_CLKID_SLV_LRCLK0 19 +#define AUD_CLKID_SLV_LRCLK1 20 +#define AUD_CLKID_SLV_LRCLK2 21 +#define AUD_CLKID_SLV_LRCLK3 22 +#define AUD_CLKID_SLV_LRCLK4 23 +#define AUD_CLKID_SLV_LRCLK5 24 +#define AUD_CLKID_SLV_LRCLK6 25 +#define AUD_CLKID_SLV_LRCLK7 26 +#define AUD_CLKID_SLV_LRCLK8 27 +#define AUD_CLKID_SLV_LRCLK9 28 +#define AUD_CLKID_DDR_ARB 29 +#define AUD_CLKID_PDM 30 +#define AUD_CLKID_TDMIN_A 31 +#define AUD_CLKID_TDMIN_B 32 +#define AUD_CLKID_TDMIN_C 33 +#define AUD_CLKID_TDMIN_LB 34 +#define AUD_CLKID_TDMOUT_A 35 +#define AUD_CLKID_TDMOUT_B 36 +#define AUD_CLKID_TDMOUT_C 37 +#define AUD_CLKID_FRDDR_A 38 +#define AUD_CLKID_FRDDR_B 39 +#define AUD_CLKID_FRDDR_C 40 +#define AUD_CLKID_TODDR_A 41 +#define AUD_CLKID_TODDR_B 42 +#define AUD_CLKID_TODDR_C 43 +#define AUD_CLKID_LOOPBACK 44 +#define AUD_CLKID_SPDIFIN 45 +#define AUD_CLKID_SPDIFOUT 46 +#define AUD_CLKID_RESAMPLE 47 +#define AUD_CLKID_POWER_DETECT 48 +#define AUD_CLKID_MST_A_MCLK 49 +#define AUD_CLKID_MST_B_MCLK 50 +#define AUD_CLKID_MST_C_MCLK 51 +#define AUD_CLKID_MST_D_MCLK 52 +#define AUD_CLKID_MST_E_MCLK 53 +#define AUD_CLKID_MST_F_MCLK 54 +#define AUD_CLKID_SPDIFOUT_CLK 55 +#define AUD_CLKID_SPDIFIN_CLK 56 +#define AUD_CLKID_PDM_DCLK 57 +#define AUD_CLKID_PDM_SYSCLK 58 +#define AUD_CLKID_MST_A_SCLK 79 +#define AUD_CLKID_MST_B_SCLK 80 +#define AUD_CLKID_MST_C_SCLK 81 +#define AUD_CLKID_MST_D_SCLK 82 +#define AUD_CLKID_MST_E_SCLK 83 +#define AUD_CLKID_MST_F_SCLK 84 +#define AUD_CLKID_MST_A_LRCLK 86 +#define AUD_CLKID_MST_B_LRCLK 87 +#define AUD_CLKID_MST_C_LRCLK 88 +#define AUD_CLKID_MST_D_LRCLK 89 +#define AUD_CLKID_MST_E_LRCLK 90 +#define AUD_CLKID_MST_F_LRCLK 91 +#define AUD_CLKID_TDMIN_A_SCLK_SEL 116 +#define AUD_CLKID_TDMIN_B_SCLK_SEL 117 +#define AUD_CLKID_TDMIN_C_SCLK_SEL 118 +#define AUD_CLKID_TDMIN_LB_SCLK_SEL 119 +#define AUD_CLKID_TDMOUT_A_SCLK_SEL 120 +#define AUD_CLKID_TDMOUT_B_SCLK_SEL 121 +#define AUD_CLKID_TDMOUT_C_SCLK_SEL 122 +#define AUD_CLKID_TDMIN_A_SCLK 123 +#define AUD_CLKID_TDMIN_B_SCLK 124 +#define AUD_CLKID_TDMIN_C_SCLK 125 +#define AUD_CLKID_TDMIN_LB_SCLK 126 +#define AUD_CLKID_TDMOUT_A_SCLK 127 +#define AUD_CLKID_TDMOUT_B_SCLK 128 +#define AUD_CLKID_TDMOUT_C_SCLK 129 +#define AUD_CLKID_TDMIN_A_LRCLK 130 +#define AUD_CLKID_TDMIN_B_LRCLK 131 +#define AUD_CLKID_TDMIN_C_LRCLK 132 +#define AUD_CLKID_TDMIN_LB_LRCLK 133 +#define AUD_CLKID_TDMOUT_A_LRCLK 134 +#define AUD_CLKID_TDMOUT_B_LRCLK 135 +#define AUD_CLKID_TDMOUT_C_LRCLK 136 + +#endif /* __AXG_AUDIO_CLKC_BINDINGS_H */ diff --git a/include/dt-bindings/clock/axg-clkc.h b/include/dt-bindings/clock/axg-clkc.h index 555937a25504..fd1f938c38d1 100644 --- a/include/dt-bindings/clock/axg-clkc.h +++ b/include/dt-bindings/clock/axg-clkc.h @@ -68,5 +68,9 @@ #define CLKID_SD_EMMC_B_CLK0 59 #define CLKID_SD_EMMC_C_CLK0 60 #define CLKID_HIFI_PLL 69 +#define CLKID_PCIE_CML_EN0 79 +#define CLKID_PCIE_CML_EN1 80 +#define CLKID_MIPI_ENABLE 81 +#define CLKID_GEN_CLK 84 #endif /* __AXG_CLKC_H */ diff --git a/include/dt-bindings/clock/bcm-sr.h b/include/dt-bindings/clock/bcm-sr.h index cff6c6fe2947..419011ba1a94 100644 --- a/include/dt-bindings/clock/bcm-sr.h +++ b/include/dt-bindings/clock/bcm-sr.h @@ -35,7 +35,7 @@ /* GENPLL 0 clock channel ID SCR HSLS FS PCIE */ #define BCM_SR_GENPLL0 0 -#define BCM_SR_GENPLL0_SATA_CLK 1 +#define BCM_SR_GENPLL0_125M_CLK 1 #define BCM_SR_GENPLL0_SCR_CLK 2 #define BCM_SR_GENPLL0_250M_CLK 3 #define BCM_SR_GENPLL0_PCIE_AXI_CLK 4 @@ -50,9 +50,11 @@ /* GENPLL 2 clock channel ID NITRO MHB*/ #define BCM_SR_GENPLL2 0 #define BCM_SR_GENPLL2_NIC_CLK 1 -#define BCM_SR_GENPLL2_250_NITRO_CLK 2 +#define BCM_SR_GENPLL2_TS_500_CLK 2 #define BCM_SR_GENPLL2_125_NITRO_CLK 3 #define BCM_SR_GENPLL2_CHIMP_CLK 4 +#define BCM_SR_GENPLL2_NIC_FLASH_CLK 5 +#define BCM_SR_GENPLL2_FS4_CLK 6 /* GENPLL 3 HSLS clock channel ID */ #define BCM_SR_GENPLL3 0 @@ -62,11 +64,16 @@ /* GENPLL 4 SCR clock channel ID */ #define BCM_SR_GENPLL4 0 #define BCM_SR_GENPLL4_CCN_CLK 1 +#define BCM_SR_GENPLL4_TPIU_PLL_CLK 2 +#define BCM_SR_GENPLL4_NOC_CLK 3 +#define BCM_SR_GENPLL4_CHCLK_FS4_CLK 4 +#define BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK 5 /* GENPLL 5 FS4 clock channel ID */ #define BCM_SR_GENPLL5 0 -#define BCM_SR_GENPLL5_FS_CLK 1 -#define BCM_SR_GENPLL5_SPU_CLK 2 +#define BCM_SR_GENPLL5_FS4_HF_CLK 1 +#define BCM_SR_GENPLL5_CRYPTO_AE_CLK 2 +#define BCM_SR_GENPLL5_RAID_AE_CLK 3 /* GENPLL 6 NITRO clock channel ID */ #define BCM_SR_GENPLL6 0 @@ -74,13 +81,16 @@ /* LCPLL0 clock channel ID */ #define BCM_SR_LCPLL0 0 -#define BCM_SR_LCPLL0_SATA_REF_CLK 1 -#define BCM_SR_LCPLL0_USB_REF_CLK 2 -#define BCM_SR_LCPLL0_SATA_REFPN_CLK 3 +#define BCM_SR_LCPLL0_SATA_REFP_CLK 1 +#define BCM_SR_LCPLL0_SATA_REFN_CLK 2 +#define BCM_SR_LCPLL0_SATA_350_CLK 3 +#define BCM_SR_LCPLL0_SATA_500_CLK 4 /* LCPLL1 clock channel ID */ #define BCM_SR_LCPLL1 0 #define BCM_SR_LCPLL1_WAN_CLK 1 +#define BCM_SR_LCPLL1_USB_REF_CLK 2 +#define BCM_SR_LCPLL1_CRMU_TS_CLK 3 /* LCPLL PCIE clock channel ID */ #define BCM_SR_LCPLL_PCIE 0 diff --git a/include/dt-bindings/clock/bcm2835-aux.h b/include/dt-bindings/clock/bcm2835-aux.h index d91156e2658d..bb79de383a3b 100644 --- a/include/dt-bindings/clock/bcm2835-aux.h +++ b/include/dt-bindings/clock/bcm2835-aux.h @@ -1,14 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2015 Broadcom Corporation - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #define BCM2835_AUX_CLOCK_UART 0 diff --git a/include/dt-bindings/clock/bcm2835.h b/include/dt-bindings/clock/bcm2835.h index a0c812b0fa39..2cec01f96897 100644 --- a/include/dt-bindings/clock/bcm2835.h +++ b/include/dt-bindings/clock/bcm2835.h @@ -1,14 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2015 Broadcom Corporation - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #define BCM2835_PLLA 0 diff --git a/include/dt-bindings/clock/dra7.h b/include/dt-bindings/clock/dra7.h index 5e1061b15aed..ec969b5aeb25 100644 --- a/include/dt-bindings/clock/dra7.h +++ b/include/dt-bindings/clock/dra7.h @@ -16,19 +16,21 @@ #define DRA7_CLKCTRL_OFFSET 0x20 #define DRA7_CLKCTRL_INDEX(offset) ((offset) - DRA7_CLKCTRL_OFFSET) +/* XXX: Compatibility part begin, remove this once compatibility support is no longer needed */ + /* mpu clocks */ #define DRA7_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) /* ipu clocks */ -#define DRA7_IPU_CLKCTRL_OFFSET 0x40 -#define DRA7_IPU_CLKCTRL_INDEX(offset) ((offset) - DRA7_IPU_CLKCTRL_OFFSET) -#define DRA7_MCASP1_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x50) -#define DRA7_TIMER5_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x58) -#define DRA7_TIMER6_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x60) -#define DRA7_TIMER7_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x68) -#define DRA7_TIMER8_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x70) -#define DRA7_I2C5_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x78) -#define DRA7_UART6_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x80) +#define _DRA7_IPU_CLKCTRL_OFFSET 0x40 +#define _DRA7_IPU_CLKCTRL_INDEX(offset) ((offset) - _DRA7_IPU_CLKCTRL_OFFSET) +#define DRA7_MCASP1_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x50) +#define DRA7_TIMER5_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x58) +#define DRA7_TIMER6_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x60) +#define DRA7_TIMER7_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x68) +#define DRA7_TIMER8_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x70) +#define DRA7_I2C5_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x78) +#define DRA7_UART6_CLKCTRL _DRA7_IPU_CLKCTRL_INDEX(0x80) /* rtc clocks */ #define DRA7_RTC_CLKCTRL_OFFSET 0x40 @@ -99,65 +101,65 @@ #define DRA7_USB_OTG_SS1_CLKCTRL DRA7_CLKCTRL_INDEX(0xf0) /* l4per clocks */ -#define DRA7_L4PER_CLKCTRL_OFFSET 0x0 -#define DRA7_L4PER_CLKCTRL_INDEX(offset) ((offset) - DRA7_L4PER_CLKCTRL_OFFSET) -#define DRA7_L4_PER2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xc) -#define DRA7_L4_PER3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x14) -#define DRA7_TIMER10_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x28) -#define DRA7_TIMER11_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x30) -#define DRA7_TIMER2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x38) -#define DRA7_TIMER3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x40) -#define DRA7_TIMER4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x48) -#define DRA7_TIMER9_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x50) -#define DRA7_ELM_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x58) -#define DRA7_GPIO2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x60) -#define DRA7_GPIO3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x68) -#define DRA7_GPIO4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x70) -#define DRA7_GPIO5_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x78) -#define DRA7_GPIO6_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x80) -#define DRA7_HDQ1W_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x88) -#define DRA7_EPWMSS1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x90) -#define DRA7_EPWMSS2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x98) -#define DRA7_I2C1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xa0) -#define DRA7_I2C2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xa8) -#define DRA7_I2C3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xb0) -#define DRA7_I2C4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xb8) -#define DRA7_L4_PER1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xc0) -#define DRA7_EPWMSS0_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xc4) -#define DRA7_TIMER13_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xc8) -#define DRA7_TIMER14_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xd0) -#define DRA7_TIMER15_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xd8) -#define DRA7_MCSPI1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xf0) -#define DRA7_MCSPI2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xf8) -#define DRA7_MCSPI3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x100) -#define DRA7_MCSPI4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x108) -#define DRA7_GPIO7_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x110) -#define DRA7_GPIO8_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x118) -#define DRA7_MMC3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x120) -#define DRA7_MMC4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x128) -#define DRA7_TIMER16_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x130) -#define DRA7_QSPI_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x138) -#define DRA7_UART1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x140) -#define DRA7_UART2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x148) -#define DRA7_UART3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x150) -#define DRA7_UART4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x158) -#define DRA7_MCASP2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x160) -#define DRA7_MCASP3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x168) -#define DRA7_UART5_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x170) -#define DRA7_MCASP5_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x178) -#define DRA7_MCASP8_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x190) -#define DRA7_MCASP4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x198) -#define DRA7_AES1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1a0) -#define DRA7_AES2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1a8) -#define DRA7_DES_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1b0) -#define DRA7_RNG_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1c0) -#define DRA7_SHAM_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1c8) -#define DRA7_UART7_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1d0) -#define DRA7_UART8_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1e0) -#define DRA7_UART9_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1e8) -#define DRA7_DCAN2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1f0) -#define DRA7_MCASP6_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x204) -#define DRA7_MCASP7_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x208) +#define _DRA7_L4PER_CLKCTRL_OFFSET 0x0 +#define _DRA7_L4PER_CLKCTRL_INDEX(offset) ((offset) - _DRA7_L4PER_CLKCTRL_OFFSET) +#define DRA7_L4_PER2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xc) +#define DRA7_L4_PER3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x14) +#define DRA7_TIMER10_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x28) +#define DRA7_TIMER11_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x30) +#define DRA7_TIMER2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x38) +#define DRA7_TIMER3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x40) +#define DRA7_TIMER4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x48) +#define DRA7_TIMER9_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x50) +#define DRA7_ELM_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x58) +#define DRA7_GPIO2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x60) +#define DRA7_GPIO3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x68) +#define DRA7_GPIO4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x70) +#define DRA7_GPIO5_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x78) +#define DRA7_GPIO6_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x80) +#define DRA7_HDQ1W_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x88) +#define DRA7_EPWMSS1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x90) +#define DRA7_EPWMSS2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x98) +#define DRA7_I2C1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xa0) +#define DRA7_I2C2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xa8) +#define DRA7_I2C3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xb0) +#define DRA7_I2C4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xb8) +#define DRA7_L4_PER1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xc0) +#define DRA7_EPWMSS0_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xc4) +#define DRA7_TIMER13_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xc8) +#define DRA7_TIMER14_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xd0) +#define DRA7_TIMER15_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xd8) +#define DRA7_MCSPI1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xf0) +#define DRA7_MCSPI2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0xf8) +#define DRA7_MCSPI3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x100) +#define DRA7_MCSPI4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x108) +#define DRA7_GPIO7_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x110) +#define DRA7_GPIO8_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x118) +#define DRA7_MMC3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x120) +#define DRA7_MMC4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x128) +#define DRA7_TIMER16_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x130) +#define DRA7_QSPI_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x138) +#define DRA7_UART1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x140) +#define DRA7_UART2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x148) +#define DRA7_UART3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x150) +#define DRA7_UART4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x158) +#define DRA7_MCASP2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x160) +#define DRA7_MCASP3_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x168) +#define DRA7_UART5_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x170) +#define DRA7_MCASP5_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x178) +#define DRA7_MCASP8_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x190) +#define DRA7_MCASP4_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x198) +#define DRA7_AES1_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1a0) +#define DRA7_AES2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1a8) +#define DRA7_DES_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1b0) +#define DRA7_RNG_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1c0) +#define DRA7_SHAM_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1c8) +#define DRA7_UART7_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1d0) +#define DRA7_UART8_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1e0) +#define DRA7_UART9_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1e8) +#define DRA7_DCAN2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x1f0) +#define DRA7_MCASP6_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x204) +#define DRA7_MCASP7_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x208) /* wkupaon clocks */ #define DRA7_L4_WKUP_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) @@ -168,5 +170,194 @@ #define DRA7_COUNTER_32K_CLKCTRL DRA7_CLKCTRL_INDEX(0x50) #define DRA7_UART10_CLKCTRL DRA7_CLKCTRL_INDEX(0x80) #define DRA7_DCAN1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) +#define DRA7_ADC_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0) + +/* XXX: Compatibility part end. */ + +/* mpu clocks */ +#define DRA7_MPU_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) + +/* dsp1 clocks */ +#define DRA7_DSP1_MMU0_DSP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) + +/* ipu1 clocks */ +#define DRA7_IPU1_MMU_IPU1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) + +/* ipu clocks */ +#define DRA7_IPU_CLKCTRL_OFFSET 0x50 +#define DRA7_IPU_CLKCTRL_INDEX(offset) ((offset) - DRA7_IPU_CLKCTRL_OFFSET) +#define DRA7_IPU_MCASP1_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x50) +#define DRA7_IPU_TIMER5_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x58) +#define DRA7_IPU_TIMER6_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x60) +#define DRA7_IPU_TIMER7_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x68) +#define DRA7_IPU_TIMER8_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x70) +#define DRA7_IPU_I2C5_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x78) +#define DRA7_IPU_UART6_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x80) + +/* dsp2 clocks */ +#define DRA7_DSP2_MMU0_DSP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) + +/* rtc clocks */ +#define DRA7_RTC_RTCSS_CLKCTRL DRA7_CLKCTRL_INDEX(0x44) + +/* coreaon clocks */ +#define DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) +#define DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x38) + +/* l3main1 clocks */ +#define DRA7_L3MAIN1_L3_MAIN_1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) +#define DRA7_L3MAIN1_GPMC_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) +#define DRA7_L3MAIN1_TPCC_CLKCTRL DRA7_CLKCTRL_INDEX(0x70) +#define DRA7_L3MAIN1_TPTC0_CLKCTRL DRA7_CLKCTRL_INDEX(0x78) +#define DRA7_L3MAIN1_TPTC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x80) +#define DRA7_L3MAIN1_VCP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) +#define DRA7_L3MAIN1_VCP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x90) + +/* ipu2 clocks */ +#define DRA7_IPU2_MMU_IPU2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) + +/* dma clocks */ +#define DRA7_DMA_DMA_SYSTEM_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) + +/* emif clocks */ +#define DRA7_EMIF_DMM_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) + +/* atl clocks */ +#define DRA7_ATL_CLKCTRL_OFFSET 0x0 +#define DRA7_ATL_CLKCTRL_INDEX(offset) ((offset) - DRA7_ATL_CLKCTRL_OFFSET) +#define DRA7_ATL_ATL_CLKCTRL DRA7_ATL_CLKCTRL_INDEX(0x0) + +/* l4cfg clocks */ +#define DRA7_L4CFG_L4_CFG_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) +#define DRA7_L4CFG_SPINLOCK_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) +#define DRA7_L4CFG_MAILBOX1_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) +#define DRA7_L4CFG_MAILBOX2_CLKCTRL DRA7_CLKCTRL_INDEX(0x48) +#define DRA7_L4CFG_MAILBOX3_CLKCTRL DRA7_CLKCTRL_INDEX(0x50) +#define DRA7_L4CFG_MAILBOX4_CLKCTRL DRA7_CLKCTRL_INDEX(0x58) +#define DRA7_L4CFG_MAILBOX5_CLKCTRL DRA7_CLKCTRL_INDEX(0x60) +#define DRA7_L4CFG_MAILBOX6_CLKCTRL DRA7_CLKCTRL_INDEX(0x68) +#define DRA7_L4CFG_MAILBOX7_CLKCTRL DRA7_CLKCTRL_INDEX(0x70) +#define DRA7_L4CFG_MAILBOX8_CLKCTRL DRA7_CLKCTRL_INDEX(0x78) +#define DRA7_L4CFG_MAILBOX9_CLKCTRL DRA7_CLKCTRL_INDEX(0x80) +#define DRA7_L4CFG_MAILBOX10_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) +#define DRA7_L4CFG_MAILBOX11_CLKCTRL DRA7_CLKCTRL_INDEX(0x90) +#define DRA7_L4CFG_MAILBOX12_CLKCTRL DRA7_CLKCTRL_INDEX(0x98) +#define DRA7_L4CFG_MAILBOX13_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0) + +/* l3instr clocks */ +#define DRA7_L3INSTR_L3_MAIN_2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) +#define DRA7_L3INSTR_L3_INSTR_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) + +/* dss clocks */ +#define DRA7_DSS_DSS_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) +#define DRA7_DSS_BB2D_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) + +/* l3init clocks */ +#define DRA7_L3INIT_MMC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) +#define DRA7_L3INIT_MMC2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) +#define DRA7_L3INIT_USB_OTG_SS2_CLKCTRL DRA7_CLKCTRL_INDEX(0x40) +#define DRA7_L3INIT_USB_OTG_SS3_CLKCTRL DRA7_CLKCTRL_INDEX(0x48) +#define DRA7_L3INIT_USB_OTG_SS4_CLKCTRL DRA7_CLKCTRL_INDEX(0x50) +#define DRA7_L3INIT_SATA_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) +#define DRA7_L3INIT_OCP2SCP1_CLKCTRL DRA7_CLKCTRL_INDEX(0xe0) +#define DRA7_L3INIT_OCP2SCP3_CLKCTRL DRA7_CLKCTRL_INDEX(0xe8) +#define DRA7_L3INIT_USB_OTG_SS1_CLKCTRL DRA7_CLKCTRL_INDEX(0xf0) + +/* pcie clocks */ +#define DRA7_PCIE_CLKCTRL_OFFSET 0xb0 +#define DRA7_PCIE_CLKCTRL_INDEX(offset) ((offset) - DRA7_PCIE_CLKCTRL_OFFSET) +#define DRA7_PCIE_PCIE1_CLKCTRL DRA7_PCIE_CLKCTRL_INDEX(0xb0) +#define DRA7_PCIE_PCIE2_CLKCTRL DRA7_PCIE_CLKCTRL_INDEX(0xb8) + +/* gmac clocks */ +#define DRA7_GMAC_CLKCTRL_OFFSET 0xd0 +#define DRA7_GMAC_CLKCTRL_INDEX(offset) ((offset) - DRA7_GMAC_CLKCTRL_OFFSET) +#define DRA7_GMAC_GMAC_CLKCTRL DRA7_GMAC_CLKCTRL_INDEX(0xd0) + +/* l4per clocks */ +#define DRA7_L4PER_CLKCTRL_OFFSET 0x28 +#define DRA7_L4PER_CLKCTRL_INDEX(offset) ((offset) - DRA7_L4PER_CLKCTRL_OFFSET) +#define DRA7_L4PER_TIMER10_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x28) +#define DRA7_L4PER_TIMER11_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x30) +#define DRA7_L4PER_TIMER2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x38) +#define DRA7_L4PER_TIMER3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x40) +#define DRA7_L4PER_TIMER4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x48) +#define DRA7_L4PER_TIMER9_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x50) +#define DRA7_L4PER_ELM_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x58) +#define DRA7_L4PER_GPIO2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x60) +#define DRA7_L4PER_GPIO3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x68) +#define DRA7_L4PER_GPIO4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x70) +#define DRA7_L4PER_GPIO5_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x78) +#define DRA7_L4PER_GPIO6_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x80) +#define DRA7_L4PER_HDQ1W_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x88) +#define DRA7_L4PER_I2C1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xa0) +#define DRA7_L4PER_I2C2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xa8) +#define DRA7_L4PER_I2C3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xb0) +#define DRA7_L4PER_I2C4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xb8) +#define DRA7_L4PER_L4_PER1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xc0) +#define DRA7_L4PER_MCSPI1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xf0) +#define DRA7_L4PER_MCSPI2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xf8) +#define DRA7_L4PER_MCSPI3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x100) +#define DRA7_L4PER_MCSPI4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x108) +#define DRA7_L4PER_GPIO7_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x110) +#define DRA7_L4PER_GPIO8_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x118) +#define DRA7_L4PER_MMC3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x120) +#define DRA7_L4PER_MMC4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x128) +#define DRA7_L4PER_UART1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x140) +#define DRA7_L4PER_UART2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x148) +#define DRA7_L4PER_UART3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x150) +#define DRA7_L4PER_UART4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x158) +#define DRA7_L4PER_UART5_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x170) + +/* l4sec clocks */ +#define DRA7_L4SEC_CLKCTRL_OFFSET 0x1a0 +#define DRA7_L4SEC_CLKCTRL_INDEX(offset) ((offset) - DRA7_L4SEC_CLKCTRL_OFFSET) +#define DRA7_L4SEC_AES1_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1a0) +#define DRA7_L4SEC_AES2_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1a8) +#define DRA7_L4SEC_DES_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1b0) +#define DRA7_L4SEC_RNG_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1c0) +#define DRA7_L4SEC_SHAM_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1c8) + +/* l4per2 clocks */ +#define DRA7_L4PER2_CLKCTRL_OFFSET 0xc +#define DRA7_L4PER2_CLKCTRL_INDEX(offset) ((offset) - DRA7_L4PER2_CLKCTRL_OFFSET) +#define DRA7_L4PER2_L4_PER2_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0xc) +#define DRA7_L4PER2_PRUSS1_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x18) +#define DRA7_L4PER2_PRUSS2_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x20) +#define DRA7_L4PER2_EPWMSS1_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x90) +#define DRA7_L4PER2_EPWMSS2_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x98) +#define DRA7_L4PER2_EPWMSS0_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0xc4) +#define DRA7_L4PER2_QSPI_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x138) +#define DRA7_L4PER2_MCASP2_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x160) +#define DRA7_L4PER2_MCASP3_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x168) +#define DRA7_L4PER2_MCASP5_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x178) +#define DRA7_L4PER2_MCASP8_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x190) +#define DRA7_L4PER2_MCASP4_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x198) +#define DRA7_L4PER2_UART7_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x1d0) +#define DRA7_L4PER2_UART8_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x1e0) +#define DRA7_L4PER2_UART9_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x1e8) +#define DRA7_L4PER2_DCAN2_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x1f0) +#define DRA7_L4PER2_MCASP6_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x204) +#define DRA7_L4PER2_MCASP7_CLKCTRL DRA7_L4PER2_CLKCTRL_INDEX(0x208) + +/* l4per3 clocks */ +#define DRA7_L4PER3_CLKCTRL_OFFSET 0x14 +#define DRA7_L4PER3_CLKCTRL_INDEX(offset) ((offset) - DRA7_L4PER3_CLKCTRL_OFFSET) +#define DRA7_L4PER3_L4_PER3_CLKCTRL DRA7_L4PER3_CLKCTRL_INDEX(0x14) +#define DRA7_L4PER3_TIMER13_CLKCTRL DRA7_L4PER3_CLKCTRL_INDEX(0xc8) +#define DRA7_L4PER3_TIMER14_CLKCTRL DRA7_L4PER3_CLKCTRL_INDEX(0xd0) +#define DRA7_L4PER3_TIMER15_CLKCTRL DRA7_L4PER3_CLKCTRL_INDEX(0xd8) +#define DRA7_L4PER3_TIMER16_CLKCTRL DRA7_L4PER3_CLKCTRL_INDEX(0x130) + +/* wkupaon clocks */ +#define DRA7_WKUPAON_L4_WKUP_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) +#define DRA7_WKUPAON_WD_TIMER2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) +#define DRA7_WKUPAON_GPIO1_CLKCTRL DRA7_CLKCTRL_INDEX(0x38) +#define DRA7_WKUPAON_TIMER1_CLKCTRL DRA7_CLKCTRL_INDEX(0x40) +#define DRA7_WKUPAON_TIMER12_CLKCTRL DRA7_CLKCTRL_INDEX(0x48) +#define DRA7_WKUPAON_COUNTER_32K_CLKCTRL DRA7_CLKCTRL_INDEX(0x50) +#define DRA7_WKUPAON_UART10_CLKCTRL DRA7_CLKCTRL_INDEX(0x80) +#define DRA7_WKUPAON_DCAN1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) +#define DRA7_WKUPAON_ADC_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0) #endif diff --git a/include/dt-bindings/clock/exynos3250.h b/include/dt-bindings/clock/exynos3250.h index c796ff02ceeb..fe8214017b46 100644 --- a/include/dt-bindings/clock/exynos3250.h +++ b/include/dt-bindings/clock/exynos3250.h @@ -1,11 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (c) 2014 Samsung Electronics Co., Ltd. * Author: Tomasz Figa <t.figa@samsung.com> * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * * Device Tree binding constants for Samsung Exynos3250 clock controllers. */ diff --git a/include/dt-bindings/clock/exynos4.h b/include/dt-bindings/clock/exynos4.h index e9f9d400c322..a0439ce8e8d3 100644 --- a/include/dt-bindings/clock/exynos4.h +++ b/include/dt-bindings/clock/exynos4.h @@ -1,13 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (c) 2013 Samsung Electronics Co., Ltd. * Author: Andrzej Hajda <a.hajda@samsung.com> * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * * Device Tree binding constants for Exynos4 clock controller. -*/ + */ #ifndef _DT_BINDINGS_CLOCK_EXYNOS_4_H #define _DT_BINDINGS_CLOCK_EXYNOS_4_H @@ -190,32 +187,6 @@ #define CLK_MIPI_HSI 349 /* Exynos4210 only */ #define CLK_PIXELASYNCM0 351 #define CLK_PIXELASYNCM1 352 -#define CLK_FIMC_LITE0 353 /* Exynos4x12 only */ -#define CLK_FIMC_LITE1 354 /* Exynos4x12 only */ -#define CLK_PPMUISPX 355 /* Exynos4x12 only */ -#define CLK_PPMUISPMX 356 /* Exynos4x12 only */ -#define CLK_FIMC_ISP 357 /* Exynos4x12 only */ -#define CLK_FIMC_DRC 358 /* Exynos4x12 only */ -#define CLK_FIMC_FD 359 /* Exynos4x12 only */ -#define CLK_MCUISP 360 /* Exynos4x12 only */ -#define CLK_GICISP 361 /* Exynos4x12 only */ -#define CLK_SMMU_ISP 362 /* Exynos4x12 only */ -#define CLK_SMMU_DRC 363 /* Exynos4x12 only */ -#define CLK_SMMU_FD 364 /* Exynos4x12 only */ -#define CLK_SMMU_LITE0 365 /* Exynos4x12 only */ -#define CLK_SMMU_LITE1 366 /* Exynos4x12 only */ -#define CLK_MCUCTL_ISP 367 /* Exynos4x12 only */ -#define CLK_MPWM_ISP 368 /* Exynos4x12 only */ -#define CLK_I2C0_ISP 369 /* Exynos4x12 only */ -#define CLK_I2C1_ISP 370 /* Exynos4x12 only */ -#define CLK_MTCADC_ISP 371 /* Exynos4x12 only */ -#define CLK_PWM_ISP 372 /* Exynos4x12 only */ -#define CLK_WDT_ISP 373 /* Exynos4x12 only */ -#define CLK_UART_ISP 374 /* Exynos4x12 only */ -#define CLK_ASYNCAXIM 375 /* Exynos4x12 only */ -#define CLK_SMMU_ISPCX 376 /* Exynos4x12 only */ -#define CLK_SPI0_ISP 377 /* Exynos4x12 only */ -#define CLK_SPI1_ISP 378 /* Exynos4x12 only */ #define CLK_PWM_ISP_SCLK 379 /* Exynos4x12 only */ #define CLK_SPI0_ISP_SCLK 380 /* Exynos4x12 only */ #define CLK_SPI1_ISP_SCLK 381 /* Exynos4x12 only */ @@ -257,10 +228,6 @@ #define CLK_PPMUACP 415 /* div clocks */ -#define CLK_DIV_ISP0 450 /* Exynos4x12 only */ -#define CLK_DIV_ISP1 451 /* Exynos4x12 only */ -#define CLK_DIV_MCUISP0 452 /* Exynos4x12 only */ -#define CLK_DIV_MCUISP1 453 /* Exynos4x12 only */ #define CLK_DIV_ACLK200 454 /* Exynos4x12 only */ #define CLK_DIV_ACLK400_MCUISP 455 /* Exynos4x12 only */ #define CLK_DIV_ACP 456 diff --git a/include/dt-bindings/clock/exynos5250.h b/include/dt-bindings/clock/exynos5250.h index 15508adcdfde..bc8a3c53a54b 100644 --- a/include/dt-bindings/clock/exynos5250.h +++ b/include/dt-bindings/clock/exynos5250.h @@ -1,13 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (c) 2013 Samsung Electronics Co., Ltd. * Author: Andrzej Hajda <a.hajda@samsung.com> * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * * Device Tree binding constants for Exynos5250 clock controller. -*/ + */ #ifndef _DT_BINDINGS_CLOCK_EXYNOS_5250_H #define _DT_BINDINGS_CLOCK_EXYNOS_5250_H diff --git a/include/dt-bindings/clock/exynos5260-clk.h b/include/dt-bindings/clock/exynos5260-clk.h index a4bac9a1764f..98a58cbd81b2 100644 --- a/include/dt-bindings/clock/exynos5260-clk.h +++ b/include/dt-bindings/clock/exynos5260-clk.h @@ -1,13 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (c) 2014 Samsung Electronics Co., Ltd. * Author: Rahul Sharma <rahul.sharma@samsung.com> * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * * Provides Constants for Exynos5260 clocks. -*/ + */ #ifndef _DT_BINDINGS_CLK_EXYNOS5260_H #define _DT_BINDINGS_CLK_EXYNOS5260_H diff --git a/include/dt-bindings/clock/exynos5410.h b/include/dt-bindings/clock/exynos5410.h index 6cb4e90f81fc..f179eabbcdb7 100644 --- a/include/dt-bindings/clock/exynos5410.h +++ b/include/dt-bindings/clock/exynos5410.h @@ -1,13 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (c) 2014 Samsung Electronics Co., Ltd. * Copyright (c) 2016 Krzysztof Kozlowski * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * * Device Tree binding constants for Exynos5421 clock controller. -*/ + */ #ifndef _DT_BINDINGS_CLOCK_EXYNOS_5410_H #define _DT_BINDINGS_CLOCK_EXYNOS_5410_H diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h index 2740ae0424a9..355f469943f1 100644 --- a/include/dt-bindings/clock/exynos5420.h +++ b/include/dt-bindings/clock/exynos5420.h @@ -1,13 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (c) 2013 Samsung Electronics Co., Ltd. * Author: Andrzej Hajda <a.hajda@samsung.com> * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * * Device Tree binding constants for Exynos5420 clock controller. -*/ + */ #ifndef _DT_BINDINGS_CLOCK_EXYNOS_5420_H #define _DT_BINDINGS_CLOCK_EXYNOS_5420_H diff --git a/include/dt-bindings/clock/exynos5433.h b/include/dt-bindings/clock/exynos5433.h index be39d23e6a32..98bd85ce1e45 100644 --- a/include/dt-bindings/clock/exynos5433.h +++ b/include/dt-bindings/clock/exynos5433.h @@ -1,10 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (c) 2014 Samsung Electronics Co., Ltd. * Author: Chanwoo Choi <cw00.choi@samsung.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #ifndef _DT_BINDINGS_CLOCK_EXYNOS5433_H diff --git a/include/dt-bindings/clock/exynos5440.h b/include/dt-bindings/clock/exynos5440.h deleted file mode 100644 index 842cdc0adff1..000000000000 --- a/include/dt-bindings/clock/exynos5440.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * Author: Andrzej Hajda <a.hajda@samsung.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Device Tree binding constants for Exynos5440 clock controller. -*/ - -#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5440_H -#define _DT_BINDINGS_CLOCK_EXYNOS_5440_H - -#define CLK_XTAL 1 -#define CLK_ARM_CLK 2 -#define CLK_CPLLA 3 -#define CLK_CPLLB 4 -#define CLK_SPI_BAUD 16 -#define CLK_PB0_250 17 -#define CLK_PR0_250 18 -#define CLK_PR1_250 19 -#define CLK_B_250 20 -#define CLK_B_125 21 -#define CLK_B_200 22 -#define CLK_SATA 23 -#define CLK_USB 24 -#define CLK_GMAC0 25 -#define CLK_CS250 26 -#define CLK_PB0_250_O 27 -#define CLK_PR0_250_O 28 -#define CLK_PR1_250_O 29 -#define CLK_B_250_O 30 -#define CLK_B_125_O 31 -#define CLK_B_200_O 32 -#define CLK_SATA_O 33 -#define CLK_USB_O 34 -#define CLK_GMAC0_O 35 -#define CLK_CS250_O 36 - -/* must be greater than maximal clock id */ -#define CLK_NR_CLKS 37 - -#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5440_H */ diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h index 10c558611085..fce33c7050c8 100644 --- a/include/dt-bindings/clock/exynos7-clk.h +++ b/include/dt-bindings/clock/exynos7-clk.h @@ -1,11 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (c) 2014 Samsung Electronics Co., Ltd. * Author: Naveen Krishna Ch <naveenkrishna.ch@gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ + */ #ifndef _DT_BINDINGS_CLOCK_EXYNOS7_H #define _DT_BINDINGS_CLOCK_EXYNOS7_H diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h index 8ba99a5e3fd3..db0763e96173 100644 --- a/include/dt-bindings/clock/gxbb-clkc.h +++ b/include/dt-bindings/clock/gxbb-clkc.h @@ -125,5 +125,26 @@ #define CLKID_VAPB_1 138 #define CLKID_VAPB_SEL 139 #define CLKID_VAPB 140 +#define CLKID_VDEC_1 153 +#define CLKID_VDEC_HEVC 156 +#define CLKID_GEN_CLK 159 +#define CLKID_VID_PLL 166 +#define CLKID_VCLK 175 +#define CLKID_VCLK2 176 +#define CLKID_VCLK_DIV1 185 +#define CLKID_VCLK_DIV2 186 +#define CLKID_VCLK_DIV4 187 +#define CLKID_VCLK_DIV6 188 +#define CLKID_VCLK_DIV12 189 +#define CLKID_VCLK2_DIV1 190 +#define CLKID_VCLK2_DIV2 191 +#define CLKID_VCLK2_DIV4 192 +#define CLKID_VCLK2_DIV6 193 +#define CLKID_VCLK2_DIV12 194 +#define CLKID_CTS_ENCI 199 +#define CLKID_CTS_ENCP 200 +#define CLKID_CTS_VDAC 201 +#define CLKID_HDMI_TX 202 +#define CLKID_HDMI 205 #endif /* __GXBB_CLKC_H */ diff --git a/include/dt-bindings/clock/hi3670-clock.h b/include/dt-bindings/clock/hi3670-clock.h new file mode 100644 index 000000000000..fa48583f87d6 --- /dev/null +++ b/include/dt-bindings/clock/hi3670-clock.h @@ -0,0 +1,348 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Device Tree binding constants for HiSilicon Hi3670 SoC + * + * Copyright (c) 2001-2021, Huawei Tech. Co., Ltd. + * Copyright (c) 2018 Linaro Ltd. + */ + +#ifndef __DT_BINDINGS_CLOCK_HI3670_H +#define __DT_BINDINGS_CLOCK_HI3670_H + +/* clk in stub clock */ +#define HI3670_CLK_STUB_CLUSTER0 0 +#define HI3670_CLK_STUB_CLUSTER1 1 +#define HI3670_CLK_STUB_GPU 2 +#define HI3670_CLK_STUB_DDR 3 +#define HI3670_CLK_STUB_DDR_VOTE 4 +#define HI3670_CLK_STUB_DDR_LIMIT 5 +#define HI3670_CLK_STUB_NUM 6 + +/* clk in crg clock */ +#define HI3670_CLKIN_SYS 0 +#define HI3670_CLKIN_REF 1 +#define HI3670_CLK_FLL_SRC 2 +#define HI3670_CLK_PPLL0 3 +#define HI3670_CLK_PPLL1 4 +#define HI3670_CLK_PPLL2 5 +#define HI3670_CLK_PPLL3 6 +#define HI3670_CLK_PPLL4 7 +#define HI3670_CLK_PPLL6 8 +#define HI3670_CLK_PPLL7 9 +#define HI3670_CLK_PPLL_PCIE 10 +#define HI3670_CLK_PCIEPLL_REV 11 +#define HI3670_CLK_SCPLL 12 +#define HI3670_PCLK 13 +#define HI3670_CLK_UART0_DBG 14 +#define HI3670_CLK_UART6 15 +#define HI3670_OSC32K 16 +#define HI3670_OSC19M 17 +#define HI3670_CLK_480M 18 +#define HI3670_CLK_INVALID 19 +#define HI3670_CLK_DIV_SYSBUS 20 +#define HI3670_CLK_FACTOR_MMC 21 +#define HI3670_CLK_SD_SYS 22 +#define HI3670_CLK_SDIO_SYS 23 +#define HI3670_CLK_DIV_A53HPM 24 +#define HI3670_CLK_DIV_320M 25 +#define HI3670_PCLK_GATE_UART0 26 +#define HI3670_CLK_FACTOR_UART0 27 +#define HI3670_CLK_FACTOR_USB3PHY_PLL 28 +#define HI3670_CLK_GATE_ABB_USB 29 +#define HI3670_CLK_GATE_UFSPHY_REF 30 +#define HI3670_ICS_VOLT_HIGH 31 +#define HI3670_ICS_VOLT_MIDDLE 32 +#define HI3670_VENC_VOLT_HOLD 33 +#define HI3670_VDEC_VOLT_HOLD 34 +#define HI3670_EDC_VOLT_HOLD 35 +#define HI3670_CLK_ISP_SNCLK_FAC 36 +#define HI3670_CLK_FACTOR_RXDPHY 37 +#define HI3670_AUTODIV_SYSBUS 38 +#define HI3670_AUTODIV_EMMC0BUS 39 +#define HI3670_PCLK_ANDGT_MMC1_PCIE 40 +#define HI3670_CLK_GATE_VCODECBUS_GT 41 +#define HI3670_CLK_ANDGT_SD 42 +#define HI3670_CLK_SD_SYS_GT 43 +#define HI3670_CLK_ANDGT_SDIO 44 +#define HI3670_CLK_SDIO_SYS_GT 45 +#define HI3670_CLK_A53HPM_ANDGT 46 +#define HI3670_CLK_320M_PLL_GT 47 +#define HI3670_CLK_ANDGT_UARTH 48 +#define HI3670_CLK_ANDGT_UARTL 49 +#define HI3670_CLK_ANDGT_UART0 50 +#define HI3670_CLK_ANDGT_SPI 51 +#define HI3670_CLK_ANDGT_PCIEAXI 52 +#define HI3670_CLK_DIV_AO_ASP_GT 53 +#define HI3670_CLK_GATE_CSI_TRANS 54 +#define HI3670_CLK_GATE_DSI_TRANS 55 +#define HI3670_CLK_ANDGT_PTP 56 +#define HI3670_CLK_ANDGT_OUT0 57 +#define HI3670_CLK_ANDGT_OUT1 58 +#define HI3670_CLKGT_DP_AUDIO_PLL_AO 59 +#define HI3670_CLK_ANDGT_VDEC 60 +#define HI3670_CLK_ANDGT_VENC 61 +#define HI3670_CLK_ISP_SNCLK_ANGT 62 +#define HI3670_CLK_ANDGT_RXDPHY 63 +#define HI3670_CLK_ANDGT_ICS 64 +#define HI3670_AUTODIV_DMABUS 65 +#define HI3670_CLK_MUX_SYSBUS 66 +#define HI3670_CLK_MUX_VCODECBUS 67 +#define HI3670_CLK_MUX_SD_SYS 68 +#define HI3670_CLK_MUX_SD_PLL 69 +#define HI3670_CLK_MUX_SDIO_SYS 70 +#define HI3670_CLK_MUX_SDIO_PLL 71 +#define HI3670_CLK_MUX_A53HPM 72 +#define HI3670_CLK_MUX_320M 73 +#define HI3670_CLK_MUX_UARTH 74 +#define HI3670_CLK_MUX_UARTL 75 +#define HI3670_CLK_MUX_UART0 76 +#define HI3670_CLK_MUX_I2C 77 +#define HI3670_CLK_MUX_SPI 78 +#define HI3670_CLK_MUX_PCIEAXI 79 +#define HI3670_CLK_MUX_AO_ASP 80 +#define HI3670_CLK_MUX_VDEC 81 +#define HI3670_CLK_MUX_VENC 82 +#define HI3670_CLK_ISP_SNCLK_MUX0 83 +#define HI3670_CLK_ISP_SNCLK_MUX1 84 +#define HI3670_CLK_ISP_SNCLK_MUX2 85 +#define HI3670_CLK_MUX_RXDPHY_CFG 86 +#define HI3670_CLK_MUX_ICS 87 +#define HI3670_CLK_DIV_CFGBUS 88 +#define HI3670_CLK_DIV_MMC0BUS 89 +#define HI3670_CLK_DIV_MMC1BUS 90 +#define HI3670_PCLK_DIV_MMC1_PCIE 91 +#define HI3670_CLK_DIV_VCODECBUS 92 +#define HI3670_CLK_DIV_SD 93 +#define HI3670_CLK_DIV_SDIO 94 +#define HI3670_CLK_DIV_UARTH 95 +#define HI3670_CLK_DIV_UARTL 96 +#define HI3670_CLK_DIV_UART0 97 +#define HI3670_CLK_DIV_I2C 98 +#define HI3670_CLK_DIV_SPI 99 +#define HI3670_CLK_DIV_PCIEAXI 100 +#define HI3670_CLK_DIV_AO_ASP 101 +#define HI3670_CLK_DIV_CSI_TRANS 102 +#define HI3670_CLK_DIV_DSI_TRANS 103 +#define HI3670_CLK_DIV_PTP 104 +#define HI3670_CLK_DIV_CLKOUT0_PLL 105 +#define HI3670_CLK_DIV_CLKOUT1_PLL 106 +#define HI3670_CLKDIV_DP_AUDIO_PLL_AO 107 +#define HI3670_CLK_DIV_VDEC 108 +#define HI3670_CLK_DIV_VENC 109 +#define HI3670_CLK_ISP_SNCLK_DIV0 110 +#define HI3670_CLK_ISP_SNCLK_DIV1 111 +#define HI3670_CLK_ISP_SNCLK_DIV2 112 +#define HI3670_CLK_DIV_ICS 113 +#define HI3670_PPLL1_EN_ACPU 114 +#define HI3670_PPLL2_EN_ACPU 115 +#define HI3670_PPLL3_EN_ACPU 116 +#define HI3670_PPLL1_GT_CPU 117 +#define HI3670_PPLL2_GT_CPU 118 +#define HI3670_PPLL3_GT_CPU 119 +#define HI3670_CLK_GATE_PPLL2_MEDIA 120 +#define HI3670_CLK_GATE_PPLL3_MEDIA 121 +#define HI3670_CLK_GATE_PPLL4_MEDIA 122 +#define HI3670_CLK_GATE_PPLL6_MEDIA 123 +#define HI3670_CLK_GATE_PPLL7_MEDIA 124 +#define HI3670_PCLK_GPIO0 125 +#define HI3670_PCLK_GPIO1 126 +#define HI3670_PCLK_GPIO2 127 +#define HI3670_PCLK_GPIO3 128 +#define HI3670_PCLK_GPIO4 129 +#define HI3670_PCLK_GPIO5 130 +#define HI3670_PCLK_GPIO6 131 +#define HI3670_PCLK_GPIO7 132 +#define HI3670_PCLK_GPIO8 133 +#define HI3670_PCLK_GPIO9 134 +#define HI3670_PCLK_GPIO10 135 +#define HI3670_PCLK_GPIO11 136 +#define HI3670_PCLK_GPIO12 137 +#define HI3670_PCLK_GPIO13 138 +#define HI3670_PCLK_GPIO14 139 +#define HI3670_PCLK_GPIO15 140 +#define HI3670_PCLK_GPIO16 141 +#define HI3670_PCLK_GPIO17 142 +#define HI3670_PCLK_GPIO20 143 +#define HI3670_PCLK_GPIO21 144 +#define HI3670_PCLK_GATE_DSI0 145 +#define HI3670_PCLK_GATE_DSI1 146 +#define HI3670_HCLK_GATE_USB3OTG 147 +#define HI3670_ACLK_GATE_USB3DVFS 148 +#define HI3670_HCLK_GATE_SDIO 149 +#define HI3670_PCLK_GATE_PCIE_SYS 150 +#define HI3670_PCLK_GATE_PCIE_PHY 151 +#define HI3670_PCLK_GATE_MMC1_PCIE 152 +#define HI3670_PCLK_GATE_MMC0_IOC 153 +#define HI3670_PCLK_GATE_MMC1_IOC 154 +#define HI3670_CLK_GATE_DMAC 155 +#define HI3670_CLK_GATE_VCODECBUS2DDR 156 +#define HI3670_CLK_CCI400_BYPASS 157 +#define HI3670_CLK_GATE_CCI400 158 +#define HI3670_CLK_GATE_SD 159 +#define HI3670_HCLK_GATE_SD 160 +#define HI3670_CLK_GATE_SDIO 161 +#define HI3670_CLK_GATE_A57HPM 162 +#define HI3670_CLK_GATE_A53HPM 163 +#define HI3670_CLK_GATE_PA_A53 164 +#define HI3670_CLK_GATE_PA_A57 165 +#define HI3670_CLK_GATE_PA_G3D 166 +#define HI3670_CLK_GATE_GPUHPM 167 +#define HI3670_CLK_GATE_PERIHPM 168 +#define HI3670_CLK_GATE_AOHPM 169 +#define HI3670_CLK_GATE_UART1 170 +#define HI3670_CLK_GATE_UART4 171 +#define HI3670_PCLK_GATE_UART1 172 +#define HI3670_PCLK_GATE_UART4 173 +#define HI3670_CLK_GATE_UART2 174 +#define HI3670_CLK_GATE_UART5 175 +#define HI3670_PCLK_GATE_UART2 176 +#define HI3670_PCLK_GATE_UART5 177 +#define HI3670_CLK_GATE_UART0 178 +#define HI3670_CLK_GATE_I2C3 179 +#define HI3670_CLK_GATE_I2C4 180 +#define HI3670_CLK_GATE_I2C7 181 +#define HI3670_PCLK_GATE_I2C3 182 +#define HI3670_PCLK_GATE_I2C4 183 +#define HI3670_PCLK_GATE_I2C7 184 +#define HI3670_CLK_GATE_SPI1 185 +#define HI3670_CLK_GATE_SPI4 186 +#define HI3670_PCLK_GATE_SPI1 187 +#define HI3670_PCLK_GATE_SPI4 188 +#define HI3670_CLK_GATE_USB3OTG_REF 189 +#define HI3670_CLK_GATE_USB2PHY_REF 190 +#define HI3670_CLK_GATE_PCIEAUX 191 +#define HI3670_ACLK_GATE_PCIE 192 +#define HI3670_CLK_GATE_MMC1_PCIEAXI 193 +#define HI3670_CLK_GATE_PCIEPHY_REF 194 +#define HI3670_CLK_GATE_PCIE_DEBOUNCE 195 +#define HI3670_CLK_GATE_PCIEIO 196 +#define HI3670_CLK_GATE_PCIE_HP 197 +#define HI3670_CLK_GATE_AO_ASP 198 +#define HI3670_PCLK_GATE_PCTRL 199 +#define HI3670_CLK_CSI_TRANS_GT 200 +#define HI3670_CLK_DSI_TRANS_GT 201 +#define HI3670_CLK_GATE_PWM 202 +#define HI3670_ABB_AUDIO_EN0 203 +#define HI3670_ABB_AUDIO_EN1 204 +#define HI3670_ABB_AUDIO_GT_EN0 205 +#define HI3670_ABB_AUDIO_GT_EN1 206 +#define HI3670_CLK_GATE_DP_AUDIO_PLL_AO 207 +#define HI3670_PERI_VOLT_HOLD 208 +#define HI3670_PERI_VOLT_MIDDLE 209 +#define HI3670_CLK_GATE_ISP_SNCLK0 210 +#define HI3670_CLK_GATE_ISP_SNCLK1 211 +#define HI3670_CLK_GATE_ISP_SNCLK2 212 +#define HI3670_CLK_GATE_RXDPHY0_CFG 213 +#define HI3670_CLK_GATE_RXDPHY1_CFG 214 +#define HI3670_CLK_GATE_RXDPHY2_CFG 215 +#define HI3670_CLK_GATE_TXDPHY0_CFG 216 +#define HI3670_CLK_GATE_TXDPHY0_REF 217 +#define HI3670_CLK_GATE_TXDPHY1_CFG 218 +#define HI3670_CLK_GATE_TXDPHY1_REF 219 +#define HI3670_CLK_GATE_MEDIA_TCXO 220 + +/* clk in sctrl */ +#define HI3670_CLK_ANDGT_IOPERI 0 +#define HI3670_CLKANDGT_ASP_SUBSYS_PERI 1 +#define HI3670_CLK_ANGT_ASP_SUBSYS 2 +#define HI3670_CLK_MUX_UFS_SUBSYS 3 +#define HI3670_CLK_MUX_CLKOUT0 4 +#define HI3670_CLK_MUX_CLKOUT1 5 +#define HI3670_CLK_MUX_ASP_SUBSYS_PERI 6 +#define HI3670_CLK_MUX_ASP_PLL 7 +#define HI3670_CLK_DIV_AOBUS 8 +#define HI3670_CLK_DIV_UFS_SUBSYS 9 +#define HI3670_CLK_DIV_IOPERI 10 +#define HI3670_CLK_DIV_CLKOUT0_TCXO 11 +#define HI3670_CLK_DIV_CLKOUT1_TCXO 12 +#define HI3670_CLK_ASP_SUBSYS_PERI_DIV 13 +#define HI3670_CLK_DIV_ASP_SUBSYS 14 +#define HI3670_PPLL0_EN_ACPU 15 +#define HI3670_PPLL0_GT_CPU 16 +#define HI3670_CLK_GATE_PPLL0_MEDIA 17 +#define HI3670_PCLK_GPIO18 18 +#define HI3670_PCLK_GPIO19 19 +#define HI3670_CLK_GATE_SPI 20 +#define HI3670_PCLK_GATE_SPI 21 +#define HI3670_CLK_GATE_UFS_SUBSYS 22 +#define HI3670_CLK_GATE_UFSIO_REF 23 +#define HI3670_PCLK_AO_GPIO0 24 +#define HI3670_PCLK_AO_GPIO1 25 +#define HI3670_PCLK_AO_GPIO2 26 +#define HI3670_PCLK_AO_GPIO3 27 +#define HI3670_PCLK_AO_GPIO4 28 +#define HI3670_PCLK_AO_GPIO5 29 +#define HI3670_PCLK_AO_GPIO6 30 +#define HI3670_CLK_GATE_OUT0 31 +#define HI3670_CLK_GATE_OUT1 32 +#define HI3670_PCLK_GATE_SYSCNT 33 +#define HI3670_CLK_GATE_SYSCNT 34 +#define HI3670_CLK_GATE_ASP_SUBSYS_PERI 35 +#define HI3670_CLK_GATE_ASP_SUBSYS 36 +#define HI3670_CLK_GATE_ASP_TCXO 37 +#define HI3670_CLK_GATE_DP_AUDIO_PLL 38 + +/* clk in pmuctrl */ +#define HI3670_GATE_ABB_192 0 + +/* clk in pctrl */ +#define HI3670_GATE_UFS_TCXO_EN 0 +#define HI3670_GATE_USB_TCXO_EN 1 + +/* clk in iomcu */ +#define HI3670_CLK_GATE_I2C0 0 +#define HI3670_CLK_GATE_I2C1 1 +#define HI3670_CLK_GATE_I2C2 2 +#define HI3670_CLK_GATE_SPI0 3 +#define HI3670_CLK_GATE_SPI2 4 +#define HI3670_CLK_GATE_UART3 5 +#define HI3670_CLK_I2C0_GATE_IOMCU 6 +#define HI3670_CLK_I2C1_GATE_IOMCU 7 +#define HI3670_CLK_I2C2_GATE_IOMCU 8 +#define HI3670_CLK_SPI0_GATE_IOMCU 9 +#define HI3670_CLK_SPI2_GATE_IOMCU 10 +#define HI3670_CLK_UART3_GATE_IOMCU 11 +#define HI3670_CLK_GATE_PERI0_IOMCU 12 + +/* clk in media1 */ +#define HI3670_CLK_GATE_VIVOBUS_ANDGT 0 +#define HI3670_CLK_ANDGT_EDC0 1 +#define HI3670_CLK_ANDGT_LDI0 2 +#define HI3670_CLK_ANDGT_LDI1 3 +#define HI3670_CLK_MMBUF_PLL_ANDGT 4 +#define HI3670_PCLK_MMBUF_ANDGT 5 +#define HI3670_CLK_MUX_VIVOBUS 6 +#define HI3670_CLK_MUX_EDC0 7 +#define HI3670_CLK_MUX_LDI0 8 +#define HI3670_CLK_MUX_LDI1 9 +#define HI3670_CLK_SW_MMBUF 10 +#define HI3670_CLK_DIV_VIVOBUS 11 +#define HI3670_CLK_DIV_EDC0 12 +#define HI3670_CLK_DIV_LDI0 13 +#define HI3670_CLK_DIV_LDI1 14 +#define HI3670_ACLK_DIV_MMBUF 15 +#define HI3670_PCLK_DIV_MMBUF 16 +#define HI3670_ACLK_GATE_NOC_DSS 17 +#define HI3670_PCLK_GATE_NOC_DSS_CFG 18 +#define HI3670_PCLK_GATE_MMBUF_CFG 19 +#define HI3670_PCLK_GATE_DISP_NOC_SUBSYS 20 +#define HI3670_ACLK_GATE_DISP_NOC_SUBSYS 21 +#define HI3670_PCLK_GATE_DSS 22 +#define HI3670_ACLK_GATE_DSS 23 +#define HI3670_CLK_GATE_VIVOBUSFREQ 24 +#define HI3670_CLK_GATE_EDC0 25 +#define HI3670_CLK_GATE_LDI0 26 +#define HI3670_CLK_GATE_LDI1FREQ 27 +#define HI3670_CLK_GATE_BRG 28 +#define HI3670_ACLK_GATE_ASC 29 +#define HI3670_CLK_GATE_DSS_AXI_MM 30 +#define HI3670_CLK_GATE_MMBUF 31 +#define HI3670_PCLK_GATE_MMBUF 32 +#define HI3670_CLK_GATE_ATDIV_VIVO 33 + +/* clk in media2 */ +#define HI3670_CLK_GATE_VDECFREQ 0 +#define HI3670_CLK_GATE_VENCFREQ 1 +#define HI3670_CLK_GATE_ICSFREQ 2 + +#endif /* __DT_BINDINGS_CLOCK_HI3670_H */ diff --git a/include/dt-bindings/clock/histb-clock.h b/include/dt-bindings/clock/histb-clock.h index fab30b3f78b2..136de24733be 100644 --- a/include/dt-bindings/clock/histb-clock.h +++ b/include/dt-bindings/clock/histb-clock.h @@ -62,6 +62,14 @@ #define HISTB_USB2_PHY1_REF_CLK 40 #define HISTB_USB2_PHY2_REF_CLK 41 #define HISTB_COMBPHY0_CLK 42 +#define HISTB_USB3_BUS_CLK 43 +#define HISTB_USB3_UTMI_CLK 44 +#define HISTB_USB3_PIPE_CLK 45 +#define HISTB_USB3_SUSPEND_CLK 46 +#define HISTB_USB3_BUS_CLK1 47 +#define HISTB_USB3_UTMI_CLK1 48 +#define HISTB_USB3_PIPE_CLK1 49 +#define HISTB_USB3_SUSPEND_CLK1 50 /* clocks provided by mcu CRG */ #define HISTB_MCE_CLK 1 diff --git a/include/dt-bindings/clock/imx6qdl-clock.h b/include/dt-bindings/clock/imx6qdl-clock.h index da59fd9cdb5e..b3cef297d5df 100644 --- a/include/dt-bindings/clock/imx6qdl-clock.h +++ b/include/dt-bindings/clock/imx6qdl-clock.h @@ -271,6 +271,11 @@ #define IMX6QDL_CLK_PRE_AXI 258 #define IMX6QDL_CLK_MLB_SEL 259 #define IMX6QDL_CLK_MLB_PODF 260 -#define IMX6QDL_CLK_END 261 +#define IMX6QDL_CLK_EPIT1 261 +#define IMX6QDL_CLK_EPIT2 262 +#define IMX6QDL_CLK_MMDC_P0_IPG 263 +#define IMX6QDL_CLK_DCIC1 264 +#define IMX6QDL_CLK_DCIC2 265 +#define IMX6QDL_CLK_END 266 #endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */ diff --git a/include/dt-bindings/clock/imx6sl-clock.h b/include/dt-bindings/clock/imx6sl-clock.h index e14573e293c5..cfbfc39d1878 100644 --- a/include/dt-bindings/clock/imx6sl-clock.h +++ b/include/dt-bindings/clock/imx6sl-clock.h @@ -175,6 +175,8 @@ #define IMX6SL_CLK_SSI2_IPG 162 #define IMX6SL_CLK_SSI3_IPG 163 #define IMX6SL_CLK_SPDIF_GCLK 164 -#define IMX6SL_CLK_END 165 +#define IMX6SL_CLK_MMDC_P0_IPG 165 +#define IMX6SL_CLK_MMDC_P1_IPG 166 +#define IMX6SL_CLK_END 167 #endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */ diff --git a/include/dt-bindings/clock/imx6sll-clock.h b/include/dt-bindings/clock/imx6sll-clock.h index 151111e68f4f..f446710fe63d 100644 --- a/include/dt-bindings/clock/imx6sll-clock.h +++ b/include/dt-bindings/clock/imx6sll-clock.h @@ -197,6 +197,14 @@ #define IMX6SLL_CLK_EXTERN_AUDIO_PODF 171 #define IMX6SLL_CLK_EXTERN_AUDIO 172 -#define IMX6SLL_CLK_END 173 +#define IMX6SLL_CLK_GPIO1 173 +#define IMX6SLL_CLK_GPIO2 174 +#define IMX6SLL_CLK_GPIO3 175 +#define IMX6SLL_CLK_GPIO4 176 +#define IMX6SLL_CLK_GPIO5 177 +#define IMX6SLL_CLK_GPIO6 178 +#define IMX6SLL_CLK_MMDC_P1_IPG 179 + +#define IMX6SLL_CLK_END 180 #endif /* __DT_BINDINGS_CLOCK_IMX6SLL_H */ diff --git a/include/dt-bindings/clock/imx6sx-clock.h b/include/dt-bindings/clock/imx6sx-clock.h index 36f0324902a5..fb420c734774 100644 --- a/include/dt-bindings/clock/imx6sx-clock.h +++ b/include/dt-bindings/clock/imx6sx-clock.h @@ -275,6 +275,11 @@ #define IMX6SX_PLL6_BYPASS 262 #define IMX6SX_PLL7_BYPASS 263 #define IMX6SX_CLK_SPDIF_GCLK 264 -#define IMX6SX_CLK_CLK_END 265 +#define IMX6SX_CLK_LVDS2_SEL 265 +#define IMX6SX_CLK_LVDS2_OUT 266 +#define IMX6SX_CLK_LVDS2_IN 267 +#define IMX6SX_CLK_ANACLK2 268 +#define IMX6SX_CLK_MMDC_P1_IPG 269 +#define IMX6SX_CLK_CLK_END 270 #endif /* __DT_BINDINGS_CLOCK_IMX6SX_H */ diff --git a/include/dt-bindings/clock/imx6ul-clock.h b/include/dt-bindings/clock/imx6ul-clock.h index ee9f1a508d2f..f718aac9b9da 100644 --- a/include/dt-bindings/clock/imx6ul-clock.h +++ b/include/dt-bindings/clock/imx6ul-clock.h @@ -235,8 +235,6 @@ #define IMX6UL_CLK_CSI_PODF 222 #define IMX6UL_CLK_PLL3_120M 223 #define IMX6UL_CLK_KPP 224 - -/* For i.MX6ULL */ #define IMX6ULL_CLK_ESAI_PRED 225 #define IMX6ULL_CLK_ESAI_PODF 226 #define IMX6ULL_CLK_ESAI_EXTAL 227 @@ -249,6 +247,20 @@ #define IMX6ULL_CLK_EPDC_ACLK 234 #define IMX6ULL_CLK_EPDC_PIX 235 #define IMX6ULL_CLK_ESAI_SEL 236 -#define IMX6UL_CLK_END 237 +#define IMX6UL_CLK_CKO1_SEL 237 +#define IMX6UL_CLK_CKO1_PODF 238 +#define IMX6UL_CLK_CKO1 239 +#define IMX6UL_CLK_CKO2_SEL 240 +#define IMX6UL_CLK_CKO2_PODF 241 +#define IMX6UL_CLK_CKO2 242 +#define IMX6UL_CLK_CKO 243 +#define IMX6UL_CLK_GPIO1 244 +#define IMX6UL_CLK_GPIO2 245 +#define IMX6UL_CLK_GPIO3 246 +#define IMX6UL_CLK_GPIO4 247 +#define IMX6UL_CLK_GPIO5 248 +#define IMX6UL_CLK_MMDC_P1_IPG 249 + +#define IMX6UL_CLK_END 250 #endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */ diff --git a/include/dt-bindings/clock/imx7d-clock.h b/include/dt-bindings/clock/imx7d-clock.h index b2325d3e236a..0d67f53bba93 100644 --- a/include/dt-bindings/clock/imx7d-clock.h +++ b/include/dt-bindings/clock/imx7d-clock.h @@ -168,7 +168,7 @@ #define IMX7D_SPDIF_ROOT_SRC 155 #define IMX7D_SPDIF_ROOT_CG 156 #define IMX7D_SPDIF_ROOT_DIV 157 -#define IMX7D_ENET1_REF_ROOT_CLK 158 +#define IMX7D_ENET1_IPG_ROOT_CLK 158 #define IMX7D_ENET1_REF_ROOT_SRC 159 #define IMX7D_ENET1_REF_ROOT_CG 160 #define IMX7D_ENET1_REF_ROOT_DIV 161 @@ -176,7 +176,7 @@ #define IMX7D_ENET1_TIME_ROOT_SRC 163 #define IMX7D_ENET1_TIME_ROOT_CG 164 #define IMX7D_ENET1_TIME_ROOT_DIV 165 -#define IMX7D_ENET2_REF_ROOT_CLK 166 +#define IMX7D_ENET2_IPG_ROOT_CLK 166 #define IMX7D_ENET2_REF_ROOT_SRC 167 #define IMX7D_ENET2_REF_ROOT_CG 168 #define IMX7D_ENET2_REF_ROOT_DIV 169 diff --git a/include/dt-bindings/clock/imx7ulp-clock.h b/include/dt-bindings/clock/imx7ulp-clock.h new file mode 100644 index 000000000000..21d872e69cb1 --- /dev/null +++ b/include/dt-bindings/clock/imx7ulp-clock.h @@ -0,0 +1,116 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017~2018 NXP + * + */ + +#ifndef __DT_BINDINGS_CLOCK_IMX7ULP_H +#define __DT_BINDINGS_CLOCK_IMX7ULP_H + +/* SCG1 */ + +#define IMX7ULP_CLK_DUMMY 0 +#define IMX7ULP_CLK_ROSC 1 +#define IMX7ULP_CLK_SOSC 2 +#define IMX7ULP_CLK_FIRC 3 +#define IMX7ULP_CLK_SPLL_PRE_SEL 4 +#define IMX7ULP_CLK_SPLL_PRE_DIV 5 +#define IMX7ULP_CLK_SPLL 6 +#define IMX7ULP_CLK_SPLL_POST_DIV1 7 +#define IMX7ULP_CLK_SPLL_POST_DIV2 8 +#define IMX7ULP_CLK_SPLL_PFD0 9 +#define IMX7ULP_CLK_SPLL_PFD1 10 +#define IMX7ULP_CLK_SPLL_PFD2 11 +#define IMX7ULP_CLK_SPLL_PFD3 12 +#define IMX7ULP_CLK_SPLL_PFD_SEL 13 +#define IMX7ULP_CLK_SPLL_SEL 14 +#define IMX7ULP_CLK_APLL_PRE_SEL 15 +#define IMX7ULP_CLK_APLL_PRE_DIV 16 +#define IMX7ULP_CLK_APLL 17 +#define IMX7ULP_CLK_APLL_POST_DIV1 18 +#define IMX7ULP_CLK_APLL_POST_DIV2 19 +#define IMX7ULP_CLK_APLL_PFD0 20 +#define IMX7ULP_CLK_APLL_PFD1 21 +#define IMX7ULP_CLK_APLL_PFD2 22 +#define IMX7ULP_CLK_APLL_PFD3 23 +#define IMX7ULP_CLK_APLL_PFD_SEL 24 +#define IMX7ULP_CLK_APLL_SEL 25 +#define IMX7ULP_CLK_UPLL 26 +#define IMX7ULP_CLK_SYS_SEL 27 +#define IMX7ULP_CLK_CORE_DIV 28 +#define IMX7ULP_CLK_BUS_DIV 29 +#define IMX7ULP_CLK_PLAT_DIV 30 +#define IMX7ULP_CLK_DDR_SEL 31 +#define IMX7ULP_CLK_DDR_DIV 32 +#define IMX7ULP_CLK_NIC_SEL 33 +#define IMX7ULP_CLK_NIC0_DIV 34 +#define IMX7ULP_CLK_GPU_DIV 35 +#define IMX7ULP_CLK_NIC1_DIV 36 +#define IMX7ULP_CLK_NIC1_BUS_DIV 37 +#define IMX7ULP_CLK_NIC1_EXT_DIV 38 +#define IMX7ULP_CLK_MIPI_PLL 39 +#define IMX7ULP_CLK_SIRC 40 +#define IMX7ULP_CLK_SOSC_BUS_CLK 41 +#define IMX7ULP_CLK_FIRC_BUS_CLK 42 +#define IMX7ULP_CLK_SPLL_BUS_CLK 43 +#define IMX7ULP_CLK_HSRUN_SYS_SEL 44 +#define IMX7ULP_CLK_HSRUN_CORE_DIV 45 + +#define IMX7ULP_CLK_SCG1_END 46 + +/* PCC2 */ +#define IMX7ULP_CLK_DMA1 0 +#define IMX7ULP_CLK_RGPIO2P1 1 +#define IMX7ULP_CLK_FLEXBUS 2 +#define IMX7ULP_CLK_SEMA42_1 3 +#define IMX7ULP_CLK_DMA_MUX1 4 +#define IMX7ULP_CLK_SNVS 5 +#define IMX7ULP_CLK_CAAM 6 +#define IMX7ULP_CLK_LPTPM4 7 +#define IMX7ULP_CLK_LPTPM5 8 +#define IMX7ULP_CLK_LPIT1 9 +#define IMX7ULP_CLK_LPSPI2 10 +#define IMX7ULP_CLK_LPSPI3 11 +#define IMX7ULP_CLK_LPI2C4 12 +#define IMX7ULP_CLK_LPI2C5 13 +#define IMX7ULP_CLK_LPUART4 14 +#define IMX7ULP_CLK_LPUART5 15 +#define IMX7ULP_CLK_FLEXIO1 16 +#define IMX7ULP_CLK_USB0 17 +#define IMX7ULP_CLK_USB1 18 +#define IMX7ULP_CLK_USB_PHY 19 +#define IMX7ULP_CLK_USB_PL301 20 +#define IMX7ULP_CLK_USDHC0 21 +#define IMX7ULP_CLK_USDHC1 22 +#define IMX7ULP_CLK_WDG1 23 +#define IMX7ULP_CLK_WDG2 24 + +#define IMX7ULP_CLK_PCC2_END 25 + +/* PCC3 */ +#define IMX7ULP_CLK_LPTPM6 0 +#define IMX7ULP_CLK_LPTPM7 1 +#define IMX7ULP_CLK_LPI2C6 2 +#define IMX7ULP_CLK_LPI2C7 3 +#define IMX7ULP_CLK_LPUART6 4 +#define IMX7ULP_CLK_LPUART7 5 +#define IMX7ULP_CLK_VIU 6 +#define IMX7ULP_CLK_DSI 7 +#define IMX7ULP_CLK_LCDIF 8 +#define IMX7ULP_CLK_MMDC 9 +#define IMX7ULP_CLK_PCTLC 10 +#define IMX7ULP_CLK_PCTLD 11 +#define IMX7ULP_CLK_PCTLE 12 +#define IMX7ULP_CLK_PCTLF 13 +#define IMX7ULP_CLK_GPU3D 14 +#define IMX7ULP_CLK_GPU2D 15 + +#define IMX7ULP_CLK_PCC3_END 16 + +/* SMC1 */ +#define IMX7ULP_CLK_ARM 0 + +#define IMX7ULP_CLK_SMC1_END 1 + +#endif /* __DT_BINDINGS_CLOCK_IMX7ULP_H */ diff --git a/include/dt-bindings/clock/imx8-clock.h b/include/dt-bindings/clock/imx8-clock.h new file mode 100644 index 000000000000..4236818e3be5 --- /dev/null +++ b/include/dt-bindings/clock/imx8-clock.h @@ -0,0 +1,289 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + * Dong Aisheng <aisheng.dong@nxp.com> + */ + +#ifndef __DT_BINDINGS_CLOCK_IMX_H +#define __DT_BINDINGS_CLOCK_IMX_H + +/* SCU Clocks */ + +#define IMX_CLK_DUMMY 0 + +/* CPU */ +#define IMX_A35_CLK 1 + +/* LSIO SS */ +#define IMX_LSIO_MEM_CLK 2 +#define IMX_LSIO_BUS_CLK 3 +#define IMX_LSIO_PWM0_CLK 10 +#define IMX_LSIO_PWM1_CLK 11 +#define IMX_LSIO_PWM2_CLK 12 +#define IMX_LSIO_PWM3_CLK 13 +#define IMX_LSIO_PWM4_CLK 14 +#define IMX_LSIO_PWM5_CLK 15 +#define IMX_LSIO_PWM6_CLK 16 +#define IMX_LSIO_PWM7_CLK 17 +#define IMX_LSIO_GPT0_CLK 18 +#define IMX_LSIO_GPT1_CLK 19 +#define IMX_LSIO_GPT2_CLK 20 +#define IMX_LSIO_GPT3_CLK 21 +#define IMX_LSIO_GPT4_CLK 22 +#define IMX_LSIO_FSPI0_CLK 23 +#define IMX_LSIO_FSPI1_CLK 24 + +/* Connectivity SS */ +#define IMX_CONN_AXI_CLK_ROOT 30 +#define IMX_CONN_AHB_CLK_ROOT 31 +#define IMX_CONN_IPG_CLK_ROOT 32 +#define IMX_CONN_SDHC0_CLK 40 +#define IMX_CONN_SDHC1_CLK 41 +#define IMX_CONN_SDHC2_CLK 42 +#define IMX_CONN_ENET0_ROOT_CLK 43 +#define IMX_CONN_ENET0_BYPASS_CLK 44 +#define IMX_CONN_ENET0_RGMII_CLK 45 +#define IMX_CONN_ENET1_ROOT_CLK 46 +#define IMX_CONN_ENET1_BYPASS_CLK 47 +#define IMX_CONN_ENET1_RGMII_CLK 48 +#define IMX_CONN_GPMI_BCH_IO_CLK 49 +#define IMX_CONN_GPMI_BCH_CLK 50 +#define IMX_CONN_USB2_ACLK 51 +#define IMX_CONN_USB2_BUS_CLK 52 +#define IMX_CONN_USB2_LPM_CLK 53 + +/* HSIO SS */ +#define IMX_HSIO_AXI_CLK 60 +#define IMX_HSIO_PER_CLK 61 + +/* Display controller SS */ +#define IMX_DC_AXI_EXT_CLK 70 +#define IMX_DC_AXI_INT_CLK 71 +#define IMX_DC_CFG_CLK 72 +#define IMX_DC0_PLL0_CLK 80 +#define IMX_DC0_PLL1_CLK 81 +#define IMX_DC0_DISP0_CLK 82 +#define IMX_DC0_DISP1_CLK 83 + +/* MIPI-LVDS SS */ +#define IMX_MIPI_IPG_CLK 90 +#define IMX_MIPI0_PIXEL_CLK 100 +#define IMX_MIPI0_BYPASS_CLK 101 +#define IMX_MIPI0_LVDS_PIXEL_CLK 102 +#define IMX_MIPI0_LVDS_BYPASS_CLK 103 +#define IMX_MIPI0_LVDS_PHY_CLK 104 +#define IMX_MIPI0_I2C0_CLK 105 +#define IMX_MIPI0_I2C1_CLK 106 +#define IMX_MIPI0_PWM0_CLK 107 +#define IMX_MIPI1_PIXEL_CLK 108 +#define IMX_MIPI1_BYPASS_CLK 109 +#define IMX_MIPI1_LVDS_PIXEL_CLK 110 +#define IMX_MIPI1_LVDS_BYPASS_CLK 111 +#define IMX_MIPI1_LVDS_PHY_CLK 112 +#define IMX_MIPI1_I2C0_CLK 113 +#define IMX_MIPI1_I2C1_CLK 114 +#define IMX_MIPI1_PWM0_CLK 115 + +/* IMG SS */ +#define IMX_IMG_AXI_CLK 120 +#define IMX_IMG_IPG_CLK 121 +#define IMX_IMG_PXL_CLK 122 + +/* MIPI-CSI SS */ +#define IMX_CSI0_CORE_CLK 130 +#define IMX_CSI0_ESC_CLK 131 +#define IMX_CSI0_PWM0_CLK 132 +#define IMX_CSI0_I2C0_CLK 133 + +/* PARALLER CSI SS */ +#define IMX_PARALLEL_CSI_DPLL_CLK 140 +#define IMX_PARALLEL_CSI_PIXEL_CLK 141 +#define IMX_PARALLEL_CSI_MCLK_CLK 142 + +/* VPU SS */ +#define IMX_VPU_ENC_CLK 150 +#define IMX_VPU_DEC_CLK 151 + +/* GPU SS */ +#define IMX_GPU0_CORE_CLK 160 +#define IMX_GPU0_SHADER_CLK 161 + +/* ADMA SS */ +#define IMX_ADMA_IPG_CLK_ROOT 165 +#define IMX_ADMA_UART0_CLK 170 +#define IMX_ADMA_UART1_CLK 171 +#define IMX_ADMA_UART2_CLK 172 +#define IMX_ADMA_UART3_CLK 173 +#define IMX_ADMA_SPI0_CLK 174 +#define IMX_ADMA_SPI1_CLK 175 +#define IMX_ADMA_SPI2_CLK 176 +#define IMX_ADMA_SPI3_CLK 177 +#define IMX_ADMA_CAN0_CLK 178 +#define IMX_ADMA_CAN1_CLK 179 +#define IMX_ADMA_CAN2_CLK 180 +#define IMX_ADMA_I2C0_CLK 181 +#define IMX_ADMA_I2C1_CLK 182 +#define IMX_ADMA_I2C2_CLK 183 +#define IMX_ADMA_I2C3_CLK 184 +#define IMX_ADMA_FTM0_CLK 185 +#define IMX_ADMA_FTM1_CLK 186 +#define IMX_ADMA_ADC0_CLK 187 +#define IMX_ADMA_PWM_CLK 188 +#define IMX_ADMA_LCD_CLK 189 + +#define IMX_SCU_CLK_END 190 + +/* LPCG clocks */ + +/* LSIO SS LPCG */ +#define IMX_LSIO_LPCG_PWM0_IPG_CLK 0 +#define IMX_LSIO_LPCG_PWM0_IPG_S_CLK 1 +#define IMX_LSIO_LPCG_PWM0_IPG_HF_CLK 2 +#define IMX_LSIO_LPCG_PWM0_IPG_SLV_CLK 3 +#define IMX_LSIO_LPCG_PWM0_IPG_MSTR_CLK 4 +#define IMX_LSIO_LPCG_PWM1_IPG_CLK 5 +#define IMX_LSIO_LPCG_PWM1_IPG_S_CLK 6 +#define IMX_LSIO_LPCG_PWM1_IPG_HF_CLK 7 +#define IMX_LSIO_LPCG_PWM1_IPG_SLV_CLK 8 +#define IMX_LSIO_LPCG_PWM1_IPG_MSTR_CLK 9 +#define IMX_LSIO_LPCG_PWM2_IPG_CLK 10 +#define IMX_LSIO_LPCG_PWM2_IPG_S_CLK 11 +#define IMX_LSIO_LPCG_PWM2_IPG_HF_CLK 12 +#define IMX_LSIO_LPCG_PWM2_IPG_SLV_CLK 13 +#define IMX_LSIO_LPCG_PWM2_IPG_MSTR_CLK 14 +#define IMX_LSIO_LPCG_PWM3_IPG_CLK 15 +#define IMX_LSIO_LPCG_PWM3_IPG_S_CLK 16 +#define IMX_LSIO_LPCG_PWM3_IPG_HF_CLK 17 +#define IMX_LSIO_LPCG_PWM3_IPG_SLV_CLK 18 +#define IMX_LSIO_LPCG_PWM3_IPG_MSTR_CLK 19 +#define IMX_LSIO_LPCG_PWM4_IPG_CLK 20 +#define IMX_LSIO_LPCG_PWM4_IPG_S_CLK 21 +#define IMX_LSIO_LPCG_PWM4_IPG_HF_CLK 22 +#define IMX_LSIO_LPCG_PWM4_IPG_SLV_CLK 23 +#define IMX_LSIO_LPCG_PWM4_IPG_MSTR_CLK 24 +#define IMX_LSIO_LPCG_PWM5_IPG_CLK 25 +#define IMX_LSIO_LPCG_PWM5_IPG_S_CLK 26 +#define IMX_LSIO_LPCG_PWM5_IPG_HF_CLK 27 +#define IMX_LSIO_LPCG_PWM5_IPG_SLV_CLK 28 +#define IMX_LSIO_LPCG_PWM5_IPG_MSTR_CLK 29 +#define IMX_LSIO_LPCG_PWM6_IPG_CLK 30 +#define IMX_LSIO_LPCG_PWM6_IPG_S_CLK 31 +#define IMX_LSIO_LPCG_PWM6_IPG_HF_CLK 32 +#define IMX_LSIO_LPCG_PWM6_IPG_SLV_CLK 33 +#define IMX_LSIO_LPCG_PWM6_IPG_MSTR_CLK 34 +#define IMX_LSIO_LPCG_PWM7_IPG_CLK 35 +#define IMX_LSIO_LPCG_PWM7_IPG_S_CLK 36 +#define IMX_LSIO_LPCG_PWM7_IPG_HF_CLK 37 +#define IMX_LSIO_LPCG_PWM7_IPG_SLV_CLK 38 +#define IMX_LSIO_LPCG_PWM7_IPG_MSTR_CLK 39 +#define IMX_LSIO_LPCG_GPT0_IPG_CLK 40 +#define IMX_LSIO_LPCG_GPT0_IPG_S_CLK 41 +#define IMX_LSIO_LPCG_GPT0_IPG_HF_CLK 42 +#define IMX_LSIO_LPCG_GPT0_IPG_SLV_CLK 43 +#define IMX_LSIO_LPCG_GPT0_IPG_MSTR_CLK 44 +#define IMX_LSIO_LPCG_GPT1_IPG_CLK 45 +#define IMX_LSIO_LPCG_GPT1_IPG_S_CLK 46 +#define IMX_LSIO_LPCG_GPT1_IPG_HF_CLK 47 +#define IMX_LSIO_LPCG_GPT1_IPG_SLV_CLK 48 +#define IMX_LSIO_LPCG_GPT1_IPG_MSTR_CLK 49 +#define IMX_LSIO_LPCG_GPT2_IPG_CLK 50 +#define IMX_LSIO_LPCG_GPT2_IPG_S_CLK 51 +#define IMX_LSIO_LPCG_GPT2_IPG_HF_CLK 52 +#define IMX_LSIO_LPCG_GPT2_IPG_SLV_CLK 53 +#define IMX_LSIO_LPCG_GPT2_IPG_MSTR_CLK 54 +#define IMX_LSIO_LPCG_GPT3_IPG_CLK 55 +#define IMX_LSIO_LPCG_GPT3_IPG_S_CLK 56 +#define IMX_LSIO_LPCG_GPT3_IPG_HF_CLK 57 +#define IMX_LSIO_LPCG_GPT3_IPG_SLV_CLK 58 +#define IMX_LSIO_LPCG_GPT3_IPG_MSTR_CLK 59 +#define IMX_LSIO_LPCG_GPT4_IPG_CLK 60 +#define IMX_LSIO_LPCG_GPT4_IPG_S_CLK 61 +#define IMX_LSIO_LPCG_GPT4_IPG_HF_CLK 62 +#define IMX_LSIO_LPCG_GPT4_IPG_SLV_CLK 63 +#define IMX_LSIO_LPCG_GPT4_IPG_MSTR_CLK 64 +#define IMX_LSIO_LPCG_FSPI0_HCLK 65 +#define IMX_LSIO_LPCG_FSPI0_IPG_CLK 66 +#define IMX_LSIO_LPCG_FSPI0_IPG_S_CLK 67 +#define IMX_LSIO_LPCG_FSPI0_IPG_SFCK 68 +#define IMX_LSIO_LPCG_FSPI1_HCLK 69 +#define IMX_LSIO_LPCG_FSPI1_IPG_CLK 70 +#define IMX_LSIO_LPCG_FSPI1_IPG_S_CLK 71 +#define IMX_LSIO_LPCG_FSPI1_IPG_SFCK 72 + +#define IMX_LSIO_LPCG_CLK_END 73 + +/* Connectivity SS LPCG */ +#define IMX_CONN_LPCG_SDHC0_IPG_CLK 0 +#define IMX_CONN_LPCG_SDHC0_PER_CLK 1 +#define IMX_CONN_LPCG_SDHC0_HCLK 2 +#define IMX_CONN_LPCG_SDHC1_IPG_CLK 3 +#define IMX_CONN_LPCG_SDHC1_PER_CLK 4 +#define IMX_CONN_LPCG_SDHC1_HCLK 5 +#define IMX_CONN_LPCG_SDHC2_IPG_CLK 6 +#define IMX_CONN_LPCG_SDHC2_PER_CLK 7 +#define IMX_CONN_LPCG_SDHC2_HCLK 8 +#define IMX_CONN_LPCG_GPMI_APB_CLK 9 +#define IMX_CONN_LPCG_GPMI_BCH_APB_CLK 10 +#define IMX_CONN_LPCG_GPMI_BCH_IO_CLK 11 +#define IMX_CONN_LPCG_GPMI_BCH_CLK 12 +#define IMX_CONN_LPCG_APBHDMA_CLK 13 +#define IMX_CONN_LPCG_ENET0_ROOT_CLK 14 +#define IMX_CONN_LPCG_ENET0_TX_CLK 15 +#define IMX_CONN_LPCG_ENET0_AHB_CLK 16 +#define IMX_CONN_LPCG_ENET0_IPG_S_CLK 17 +#define IMX_CONN_LPCG_ENET0_IPG_CLK 18 + +#define IMX_CONN_LPCG_ENET1_ROOT_CLK 19 +#define IMX_CONN_LPCG_ENET1_TX_CLK 20 +#define IMX_CONN_LPCG_ENET1_AHB_CLK 21 +#define IMX_CONN_LPCG_ENET1_IPG_S_CLK 22 +#define IMX_CONN_LPCG_ENET1_IPG_CLK 23 + +#define IMX_CONN_LPCG_CLK_END 24 + +/* ADMA SS LPCG */ +#define IMX_ADMA_LPCG_UART0_IPG_CLK 0 +#define IMX_ADMA_LPCG_UART0_BAUD_CLK 1 +#define IMX_ADMA_LPCG_UART1_IPG_CLK 2 +#define IMX_ADMA_LPCG_UART1_BAUD_CLK 3 +#define IMX_ADMA_LPCG_UART2_IPG_CLK 4 +#define IMX_ADMA_LPCG_UART2_BAUD_CLK 5 +#define IMX_ADMA_LPCG_UART3_IPG_CLK 6 +#define IMX_ADMA_LPCG_UART3_BAUD_CLK 7 +#define IMX_ADMA_LPCG_SPI0_IPG_CLK 8 +#define IMX_ADMA_LPCG_SPI1_IPG_CLK 9 +#define IMX_ADMA_LPCG_SPI2_IPG_CLK 10 +#define IMX_ADMA_LPCG_SPI3_IPG_CLK 11 +#define IMX_ADMA_LPCG_SPI0_CLK 12 +#define IMX_ADMA_LPCG_SPI1_CLK 13 +#define IMX_ADMA_LPCG_SPI2_CLK 14 +#define IMX_ADMA_LPCG_SPI3_CLK 15 +#define IMX_ADMA_LPCG_CAN0_IPG_CLK 16 +#define IMX_ADMA_LPCG_CAN0_IPG_PE_CLK 17 +#define IMX_ADMA_LPCG_CAN0_IPG_CHI_CLK 18 +#define IMX_ADMA_LPCG_CAN1_IPG_CLK 19 +#define IMX_ADMA_LPCG_CAN1_IPG_PE_CLK 20 +#define IMX_ADMA_LPCG_CAN1_IPG_CHI_CLK 21 +#define IMX_ADMA_LPCG_CAN2_IPG_CLK 22 +#define IMX_ADMA_LPCG_CAN2_IPG_PE_CLK 23 +#define IMX_ADMA_LPCG_CAN2_IPG_CHI_CLK 24 +#define IMX_ADMA_LPCG_I2C0_CLK 25 +#define IMX_ADMA_LPCG_I2C1_CLK 26 +#define IMX_ADMA_LPCG_I2C2_CLK 27 +#define IMX_ADMA_LPCG_I2C3_CLK 28 +#define IMX_ADMA_LPCG_I2C0_IPG_CLK 29 +#define IMX_ADMA_LPCG_I2C1_IPG_CLK 30 +#define IMX_ADMA_LPCG_I2C2_IPG_CLK 31 +#define IMX_ADMA_LPCG_I2C3_IPG_CLK 32 +#define IMX_ADMA_LPCG_FTM0_CLK 33 +#define IMX_ADMA_LPCG_FTM1_CLK 34 +#define IMX_ADMA_LPCG_FTM0_IPG_CLK 35 +#define IMX_ADMA_LPCG_FTM1_IPG_CLK 36 +#define IMX_ADMA_LPCG_PWM_HI_CLK 37 +#define IMX_ADMA_LPCG_PWM_IPG_CLK 38 +#define IMX_ADMA_LPCG_LCD_PIX_CLK 39 +#define IMX_ADMA_LPCG_LCD_APB_CLK 40 + +#define IMX_ADMA_LPCG_CLK_END 41 + +#endif /* __DT_BINDINGS_CLOCK_IMX_H */ diff --git a/include/dt-bindings/clock/imx8mq-clock.h b/include/dt-bindings/clock/imx8mq-clock.h new file mode 100644 index 000000000000..b53be41929be --- /dev/null +++ b/include/dt-bindings/clock/imx8mq-clock.h @@ -0,0 +1,395 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + */ + +#ifndef __DT_BINDINGS_CLOCK_IMX8MQ_H +#define __DT_BINDINGS_CLOCK_IMX8MQ_H + +#define IMX8MQ_CLK_DUMMY 0 +#define IMX8MQ_CLK_32K 1 +#define IMX8MQ_CLK_25M 2 +#define IMX8MQ_CLK_27M 3 +#define IMX8MQ_CLK_EXT1 4 +#define IMX8MQ_CLK_EXT2 5 +#define IMX8MQ_CLK_EXT3 6 +#define IMX8MQ_CLK_EXT4 7 + +/* ANAMIX PLL clocks */ +/* FRAC PLLs */ +/* ARM PLL */ +#define IMX8MQ_ARM_PLL_REF_SEL 8 +#define IMX8MQ_ARM_PLL_REF_DIV 9 +#define IMX8MQ_ARM_PLL 10 +#define IMX8MQ_ARM_PLL_BYPASS 11 +#define IMX8MQ_ARM_PLL_OUT 12 + +/* GPU PLL */ +#define IMX8MQ_GPU_PLL_REF_SEL 13 +#define IMX8MQ_GPU_PLL_REF_DIV 14 +#define IMX8MQ_GPU_PLL 15 +#define IMX8MQ_GPU_PLL_BYPASS 16 +#define IMX8MQ_GPU_PLL_OUT 17 + +/* VPU PLL */ +#define IMX8MQ_VPU_PLL_REF_SEL 18 +#define IMX8MQ_VPU_PLL_REF_DIV 19 +#define IMX8MQ_VPU_PLL 20 +#define IMX8MQ_VPU_PLL_BYPASS 21 +#define IMX8MQ_VPU_PLL_OUT 22 + +/* AUDIO PLL1 */ +#define IMX8MQ_AUDIO_PLL1_REF_SEL 23 +#define IMX8MQ_AUDIO_PLL1_REF_DIV 24 +#define IMX8MQ_AUDIO_PLL1 25 +#define IMX8MQ_AUDIO_PLL1_BYPASS 26 +#define IMX8MQ_AUDIO_PLL1_OUT 27 + +/* AUDIO PLL2 */ +#define IMX8MQ_AUDIO_PLL2_REF_SEL 28 +#define IMX8MQ_AUDIO_PLL2_REF_DIV 29 +#define IMX8MQ_AUDIO_PLL2 30 +#define IMX8MQ_AUDIO_PLL2_BYPASS 31 +#define IMX8MQ_AUDIO_PLL2_OUT 32 + +/* VIDEO PLL1 */ +#define IMX8MQ_VIDEO_PLL1_REF_SEL 33 +#define IMX8MQ_VIDEO_PLL1_REF_DIV 34 +#define IMX8MQ_VIDEO_PLL1 35 +#define IMX8MQ_VIDEO_PLL1_BYPASS 36 +#define IMX8MQ_VIDEO_PLL1_OUT 37 + +/* SYS1 PLL */ +#define IMX8MQ_SYS1_PLL1_REF_SEL 38 +#define IMX8MQ_SYS1_PLL1_REF_DIV 39 +#define IMX8MQ_SYS1_PLL1 40 +#define IMX8MQ_SYS1_PLL1_OUT 41 +#define IMX8MQ_SYS1_PLL1_OUT_DIV 42 +#define IMX8MQ_SYS1_PLL2 43 +#define IMX8MQ_SYS1_PLL2_DIV 44 +#define IMX8MQ_SYS1_PLL2_OUT 45 + +/* SYS2 PLL */ +#define IMX8MQ_SYS2_PLL1_REF_SEL 46 +#define IMX8MQ_SYS2_PLL1_REF_DIV 47 +#define IMX8MQ_SYS2_PLL1 48 +#define IMX8MQ_SYS2_PLL1_OUT 49 +#define IMX8MQ_SYS2_PLL1_OUT_DIV 50 +#define IMX8MQ_SYS2_PLL2 51 +#define IMX8MQ_SYS2_PLL2_DIV 52 +#define IMX8MQ_SYS2_PLL2_OUT 53 + +/* SYS3 PLL */ +#define IMX8MQ_SYS3_PLL1_REF_SEL 54 +#define IMX8MQ_SYS3_PLL1_REF_DIV 55 +#define IMX8MQ_SYS3_PLL1 56 +#define IMX8MQ_SYS3_PLL1_OUT 57 +#define IMX8MQ_SYS3_PLL1_OUT_DIV 58 +#define IMX8MQ_SYS3_PLL2 59 +#define IMX8MQ_SYS3_PLL2_DIV 60 +#define IMX8MQ_SYS3_PLL2_OUT 61 + +/* DRAM PLL */ +#define IMX8MQ_DRAM_PLL1_REF_SEL 62 +#define IMX8MQ_DRAM_PLL1_REF_DIV 63 +#define IMX8MQ_DRAM_PLL1 64 +#define IMX8MQ_DRAM_PLL1_OUT 65 +#define IMX8MQ_DRAM_PLL1_OUT_DIV 66 +#define IMX8MQ_DRAM_PLL2 67 +#define IMX8MQ_DRAM_PLL2_DIV 68 +#define IMX8MQ_DRAM_PLL2_OUT 69 + +/* SYS PLL DIV */ +#define IMX8MQ_SYS1_PLL_40M 70 +#define IMX8MQ_SYS1_PLL_80M 71 +#define IMX8MQ_SYS1_PLL_100M 72 +#define IMX8MQ_SYS1_PLL_133M 73 +#define IMX8MQ_SYS1_PLL_160M 74 +#define IMX8MQ_SYS1_PLL_200M 75 +#define IMX8MQ_SYS1_PLL_266M 76 +#define IMX8MQ_SYS1_PLL_400M 77 +#define IMX8MQ_SYS1_PLL_800M 78 + +#define IMX8MQ_SYS2_PLL_50M 79 +#define IMX8MQ_SYS2_PLL_100M 80 +#define IMX8MQ_SYS2_PLL_125M 81 +#define IMX8MQ_SYS2_PLL_166M 82 +#define IMX8MQ_SYS2_PLL_200M 83 +#define IMX8MQ_SYS2_PLL_250M 84 +#define IMX8MQ_SYS2_PLL_333M 85 +#define IMX8MQ_SYS2_PLL_500M 86 +#define IMX8MQ_SYS2_PLL_1000M 87 + +/* CCM ROOT clocks */ +/* A53 */ +#define IMX8MQ_CLK_A53_SRC 88 +#define IMX8MQ_CLK_A53_CG 89 +#define IMX8MQ_CLK_A53_DIV 90 +/* M4 */ +#define IMX8MQ_CLK_M4_SRC 91 +#define IMX8MQ_CLK_M4_CG 92 +#define IMX8MQ_CLK_M4_DIV 93 +/* VPU */ +#define IMX8MQ_CLK_VPU_SRC 94 +#define IMX8MQ_CLK_VPU_CG 95 +#define IMX8MQ_CLK_VPU_DIV 96 +/* GPU CORE */ +#define IMX8MQ_CLK_GPU_CORE_SRC 97 +#define IMX8MQ_CLK_GPU_CORE_CG 98 +#define IMX8MQ_CLK_GPU_CORE_DIV 99 +/* GPU SHADER */ +#define IMX8MQ_CLK_GPU_SHADER_SRC 100 +#define IMX8MQ_CLK_GPU_SHADER_CG 101 +#define IMX8MQ_CLK_GPU_SHADER_DIV 102 + +/* BUS TYPE */ +/* MAIN AXI */ +#define IMX8MQ_CLK_MAIN_AXI 103 +/* ENET AXI */ +#define IMX8MQ_CLK_ENET_AXI 104 +/* NAND_USDHC_BUS */ +#define IMX8MQ_CLK_NAND_USDHC_BUS 105 +/* VPU BUS */ +#define IMX8MQ_CLK_VPU_BUS 106 +/* DISP_AXI */ +#define IMX8MQ_CLK_DISP_AXI 107 +/* DISP APB */ +#define IMX8MQ_CLK_DISP_APB 108 +/* DISP RTRM */ +#define IMX8MQ_CLK_DISP_RTRM 109 +/* USB_BUS */ +#define IMX8MQ_CLK_USB_BUS 110 +/* GPU_AXI */ +#define IMX8MQ_CLK_GPU_AXI 111 +/* GPU_AHB */ +#define IMX8MQ_CLK_GPU_AHB 112 +/* NOC */ +#define IMX8MQ_CLK_NOC 113 +/* NOC_APB */ +#define IMX8MQ_CLK_NOC_APB 115 + +/* AHB */ +#define IMX8MQ_CLK_AHB 116 +/* AUDIO AHB */ +#define IMX8MQ_CLK_AUDIO_AHB 117 + +/* DRAM_ALT */ +#define IMX8MQ_CLK_DRAM_ALT 118 +/* DRAM APB */ +#define IMX8MQ_CLK_DRAM_APB 119 +/* VPU_G1 */ +#define IMX8MQ_CLK_VPU_G1 120 +/* VPU_G2 */ +#define IMX8MQ_CLK_VPU_G2 121 +/* DISP_DTRC */ +#define IMX8MQ_CLK_DISP_DTRC 122 +/* DISP_DC8000 */ +#define IMX8MQ_CLK_DISP_DC8000 123 +/* PCIE_CTRL */ +#define IMX8MQ_CLK_PCIE1_CTRL 124 +/* PCIE_PHY */ +#define IMX8MQ_CLK_PCIE1_PHY 125 +/* PCIE_AUX */ +#define IMX8MQ_CLK_PCIE1_AUX 126 +/* DC_PIXEL */ +#define IMX8MQ_CLK_DC_PIXEL 127 +/* LCDIF_PIXEL */ +#define IMX8MQ_CLK_LCDIF_PIXEL 128 +/* SAI1~6 */ +#define IMX8MQ_CLK_SAI1 129 + +#define IMX8MQ_CLK_SAI2 130 + +#define IMX8MQ_CLK_SAI3 131 + +#define IMX8MQ_CLK_SAI4 132 + +#define IMX8MQ_CLK_SAI5 133 + +#define IMX8MQ_CLK_SAI6 134 +/* SPDIF1 */ +#define IMX8MQ_CLK_SPDIF1 135 +/* SPDIF2 */ +#define IMX8MQ_CLK_SPDIF2 136 +/* ENET_REF */ +#define IMX8MQ_CLK_ENET_REF 137 +/* ENET_TIMER */ +#define IMX8MQ_CLK_ENET_TIMER 138 +/* ENET_PHY */ +#define IMX8MQ_CLK_ENET_PHY_REF 139 +/* NAND */ +#define IMX8MQ_CLK_NAND 140 +/* QSPI */ +#define IMX8MQ_CLK_QSPI 141 +/* USDHC1 */ +#define IMX8MQ_CLK_USDHC1 142 +/* USDHC2 */ +#define IMX8MQ_CLK_USDHC2 143 +/* I2C1 */ +#define IMX8MQ_CLK_I2C1 144 +/* I2C2 */ +#define IMX8MQ_CLK_I2C2 145 +/* I2C3 */ +#define IMX8MQ_CLK_I2C3 146 +/* I2C4 */ +#define IMX8MQ_CLK_I2C4 147 +/* UART1 */ +#define IMX8MQ_CLK_UART1 148 +/* UART2 */ +#define IMX8MQ_CLK_UART2 149 +/* UART3 */ +#define IMX8MQ_CLK_UART3 150 +/* UART4 */ +#define IMX8MQ_CLK_UART4 151 +/* USB_CORE_REF */ +#define IMX8MQ_CLK_USB_CORE_REF 152 +/* USB_PHY_REF */ +#define IMX8MQ_CLK_USB_PHY_REF 163 +/* ECSPI1 */ +#define IMX8MQ_CLK_ECSPI1 164 +/* ECSPI2 */ +#define IMX8MQ_CLK_ECSPI2 165 +/* PWM1 */ +#define IMX8MQ_CLK_PWM1 166 +/* PWM2 */ +#define IMX8MQ_CLK_PWM2 167 +/* PWM3 */ +#define IMX8MQ_CLK_PWM3 168 +/* PWM4 */ +#define IMX8MQ_CLK_PWM4 169 +/* GPT1 */ +#define IMX8MQ_CLK_GPT1 170 +/* WDOG */ +#define IMX8MQ_CLK_WDOG 171 +/* WRCLK */ +#define IMX8MQ_CLK_WRCLK 172 +/* DSI_CORE */ +#define IMX8MQ_CLK_DSI_CORE 173 +/* DSI_PHY */ +#define IMX8MQ_CLK_DSI_PHY_REF 174 +/* DSI_DBI */ +#define IMX8MQ_CLK_DSI_DBI 175 +/*DSI_ESC */ +#define IMX8MQ_CLK_DSI_ESC 176 +/* CSI1_CORE */ +#define IMX8MQ_CLK_CSI1_CORE 177 +/* CSI1_PHY */ +#define IMX8MQ_CLK_CSI1_PHY_REF 178 +/* CSI_ESC */ +#define IMX8MQ_CLK_CSI1_ESC 179 +/* CSI2_CORE */ +#define IMX8MQ_CLK_CSI2_CORE 170 +/* CSI2_PHY */ +#define IMX8MQ_CLK_CSI2_PHY_REF 181 +/* CSI2_ESC */ +#define IMX8MQ_CLK_CSI2_ESC 182 +/* PCIE2_CTRL */ +#define IMX8MQ_CLK_PCIE2_CTRL 183 +/* PCIE2_PHY */ +#define IMX8MQ_CLK_PCIE2_PHY 184 +/* PCIE2_AUX */ +#define IMX8MQ_CLK_PCIE2_AUX 185 +/* ECSPI3 */ +#define IMX8MQ_CLK_ECSPI3 186 + +/* CCGR clocks */ +#define IMX8MQ_CLK_A53_ROOT 187 +#define IMX8MQ_CLK_DRAM_ROOT 188 +#define IMX8MQ_CLK_ECSPI1_ROOT 189 +#define IMX8MQ_CLK_ECSPI2_ROOT 180 +#define IMX8MQ_CLK_ECSPI3_ROOT 181 +#define IMX8MQ_CLK_ENET1_ROOT 182 +#define IMX8MQ_CLK_GPT1_ROOT 193 +#define IMX8MQ_CLK_I2C1_ROOT 194 +#define IMX8MQ_CLK_I2C2_ROOT 195 +#define IMX8MQ_CLK_I2C3_ROOT 196 +#define IMX8MQ_CLK_I2C4_ROOT 197 +#define IMX8MQ_CLK_M4_ROOT 198 +#define IMX8MQ_CLK_PCIE1_ROOT 199 +#define IMX8MQ_CLK_PCIE2_ROOT 200 +#define IMX8MQ_CLK_PWM1_ROOT 201 +#define IMX8MQ_CLK_PWM2_ROOT 202 +#define IMX8MQ_CLK_PWM3_ROOT 203 +#define IMX8MQ_CLK_PWM4_ROOT 204 +#define IMX8MQ_CLK_QSPI_ROOT 205 +#define IMX8MQ_CLK_SAI1_ROOT 206 +#define IMX8MQ_CLK_SAI2_ROOT 207 +#define IMX8MQ_CLK_SAI3_ROOT 208 +#define IMX8MQ_CLK_SAI4_ROOT 209 +#define IMX8MQ_CLK_SAI5_ROOT 210 +#define IMX8MQ_CLK_SAI6_ROOT 212 +#define IMX8MQ_CLK_UART1_ROOT 213 +#define IMX8MQ_CLK_UART2_ROOT 214 +#define IMX8MQ_CLK_UART3_ROOT 215 +#define IMX8MQ_CLK_UART4_ROOT 216 +#define IMX8MQ_CLK_USB1_CTRL_ROOT 217 +#define IMX8MQ_CLK_USB2_CTRL_ROOT 218 +#define IMX8MQ_CLK_USB1_PHY_ROOT 219 +#define IMX8MQ_CLK_USB2_PHY_ROOT 220 +#define IMX8MQ_CLK_USDHC1_ROOT 221 +#define IMX8MQ_CLK_USDHC2_ROOT 222 +#define IMX8MQ_CLK_WDOG1_ROOT 223 +#define IMX8MQ_CLK_WDOG2_ROOT 224 +#define IMX8MQ_CLK_WDOG3_ROOT 225 +#define IMX8MQ_CLK_GPU_ROOT 226 +#define IMX8MQ_CLK_HEVC_ROOT 227 +#define IMX8MQ_CLK_AVC_ROOT 228 +#define IMX8MQ_CLK_VP9_ROOT 229 +#define IMX8MQ_CLK_HEVC_INTER_ROOT 230 +#define IMX8MQ_CLK_DISP_ROOT 231 +#define IMX8MQ_CLK_HDMI_ROOT 232 +#define IMX8MQ_CLK_HDMI_PHY_ROOT 233 +#define IMX8MQ_CLK_VPU_DEC_ROOT 234 +#define IMX8MQ_CLK_CSI1_ROOT 235 +#define IMX8MQ_CLK_CSI2_ROOT 236 +#define IMX8MQ_CLK_RAWNAND_ROOT 237 +#define IMX8MQ_CLK_SDMA1_ROOT 238 +#define IMX8MQ_CLK_SDMA2_ROOT 239 +#define IMX8MQ_CLK_VPU_G1_ROOT 240 +#define IMX8MQ_CLK_VPU_G2_ROOT 241 + +/* SCCG PLL GATE */ +#define IMX8MQ_SYS1_PLL_OUT 232 +#define IMX8MQ_SYS2_PLL_OUT 243 +#define IMX8MQ_SYS3_PLL_OUT 244 +#define IMX8MQ_DRAM_PLL_OUT 245 + +#define IMX8MQ_GPT_3M_CLK 246 + +#define IMX8MQ_CLK_IPG_ROOT 247 +#define IMX8MQ_CLK_IPG_AUDIO_ROOT 248 +#define IMX8MQ_CLK_SAI1_IPG 249 +#define IMX8MQ_CLK_SAI2_IPG 250 +#define IMX8MQ_CLK_SAI3_IPG 251 +#define IMX8MQ_CLK_SAI4_IPG 252 +#define IMX8MQ_CLK_SAI5_IPG 253 +#define IMX8MQ_CLK_SAI6_IPG 254 + +/* DSI AHB/IPG clocks */ +/* rxesc clock */ +#define IMX8MQ_CLK_DSI_AHB 255 +/* txesc clock */ +#define IMX8MQ_CLK_DSI_IPG_DIV 256 + +#define IMX8MQ_CLK_TMU_ROOT 265 + +/* Display root clocks */ +#define IMX8MQ_CLK_DISP_AXI_ROOT 266 +#define IMX8MQ_CLK_DISP_APB_ROOT 267 +#define IMX8MQ_CLK_DISP_RTRM_ROOT 268 + +#define IMX8MQ_CLK_OCOTP_ROOT 269 + +#define IMX8MQ_CLK_DRAM_ALT_ROOT 270 +#define IMX8MQ_CLK_DRAM_CORE 271 + +#define IMX8MQ_CLK_MU_ROOT 272 +#define IMX8MQ_VIDEO2_PLL_OUT 273 + +#define IMX8MQ_CLK_CLKO2 274 + +#define IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK 275 + +#define IMX8MQ_CLK_END 276 +#endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */ diff --git a/include/dt-bindings/clock/jz4725b-cgu.h b/include/dt-bindings/clock/jz4725b-cgu.h new file mode 100644 index 000000000000..460bbeff6ab8 --- /dev/null +++ b/include/dt-bindings/clock/jz4725b-cgu.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides clock numbers for the ingenic,jz4725b-cgu DT binding. + */ + +#ifndef __DT_BINDINGS_CLOCK_JZ4725B_CGU_H__ +#define __DT_BINDINGS_CLOCK_JZ4725B_CGU_H__ + +#define JZ4725B_CLK_EXT 0 +#define JZ4725B_CLK_OSC32K 1 +#define JZ4725B_CLK_PLL 2 +#define JZ4725B_CLK_PLL_HALF 3 +#define JZ4725B_CLK_CCLK 4 +#define JZ4725B_CLK_HCLK 5 +#define JZ4725B_CLK_PCLK 6 +#define JZ4725B_CLK_MCLK 7 +#define JZ4725B_CLK_IPU 8 +#define JZ4725B_CLK_LCD 9 +#define JZ4725B_CLK_I2S 10 +#define JZ4725B_CLK_SPI 11 +#define JZ4725B_CLK_MMC_MUX 12 +#define JZ4725B_CLK_UDC 13 +#define JZ4725B_CLK_UART 14 +#define JZ4725B_CLK_DMA 15 +#define JZ4725B_CLK_ADC 16 +#define JZ4725B_CLK_I2C 17 +#define JZ4725B_CLK_AIC 18 +#define JZ4725B_CLK_MMC0 19 +#define JZ4725B_CLK_MMC1 20 +#define JZ4725B_CLK_BCH 21 +#define JZ4725B_CLK_TCU 22 +#define JZ4725B_CLK_EXT512 23 +#define JZ4725B_CLK_RTC 24 + +#endif /* __DT_BINDINGS_CLOCK_JZ4725B_CGU_H__ */ diff --git a/include/dt-bindings/clock/maxim,max77686.h b/include/dt-bindings/clock/maxim,max77686.h index 7b28b0905869..af8261dcace1 100644 --- a/include/dt-bindings/clock/maxim,max77686.h +++ b/include/dt-bindings/clock/maxim,max77686.h @@ -1,10 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2014 Google, Inc * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * * Device Tree binding constants clocks for the Maxim 77686 PMIC. */ diff --git a/include/dt-bindings/clock/maxim,max77802.h b/include/dt-bindings/clock/maxim,max77802.h index 997312edcbb5..51adcbaed697 100644 --- a/include/dt-bindings/clock/maxim,max77802.h +++ b/include/dt-bindings/clock/maxim,max77802.h @@ -1,10 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2014 Google, Inc * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * * Device Tree binding constants clocks for the Maxim 77802 PMIC. */ diff --git a/include/dt-bindings/clock/maxim,max9485.h b/include/dt-bindings/clock/maxim,max9485.h new file mode 100644 index 000000000000..185b09ce1869 --- /dev/null +++ b/include/dt-bindings/clock/maxim,max9485.h @@ -0,0 +1,18 @@ +/* + * Copyright (C) 2018 Daniel Mack + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __DT_BINDINGS_MAX9485_CLK_H +#define __DT_BINDINGS_MAX9485_CLK_H + +#define MAX9485_MCLKOUT 0 +#define MAX9485_CLKOUT 1 +#define MAX9485_CLKOUT1 2 +#define MAX9485_CLKOUT2 3 + +#endif /* __DT_BINDINGS_MAX9485_CLK_H */ diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h index dea9d46d4fa7..5fe2923382d0 100644 --- a/include/dt-bindings/clock/meson8b-clkc.h +++ b/include/dt-bindings/clock/meson8b-clkc.h @@ -102,5 +102,10 @@ #define CLKID_MPLL0 93 #define CLKID_MPLL1 94 #define CLKID_MPLL2 95 +#define CLKID_NAND_CLK 112 +#define CLKID_ABP 124 +#define CLKID_PERIPH 126 +#define CLKID_AXI 128 +#define CLKID_L2_DRAM 130 #endif /* __MESON8B_CLKC_H */ diff --git a/include/dt-bindings/clock/mt2701-clk.h b/include/dt-bindings/clock/mt2701-clk.h index 24e93dfcee9f..9ac2f2b5710a 100644 --- a/include/dt-bindings/clock/mt2701-clk.h +++ b/include/dt-bindings/clock/mt2701-clk.h @@ -171,13 +171,12 @@ #define CLK_TOP_8BDAC 151 #define CLK_TOP_WBG_DIG_416M 152 #define CLK_TOP_DPI 153 -#define CLK_TOP_HDMITX_CLKDIG_CTS 154 -#define CLK_TOP_DSI0_LNTC_DSI 155 -#define CLK_TOP_AUD_EXT1 156 -#define CLK_TOP_AUD_EXT2 157 -#define CLK_TOP_NFI1X_PAD 158 -#define CLK_TOP_AXISEL_D4 159 -#define CLK_TOP_NR 160 +#define CLK_TOP_DSI0_LNTC_DSI 154 +#define CLK_TOP_AUD_EXT1 155 +#define CLK_TOP_AUD_EXT2 156 +#define CLK_TOP_NFI1X_PAD 157 +#define CLK_TOP_AXISEL_D4 158 +#define CLK_TOP_NR 159 /* APMIXEDSYS */ @@ -194,7 +193,8 @@ #define CLK_APMIXED_HADDS2PLL 11 #define CLK_APMIXED_AUD2PLL 12 #define CLK_APMIXED_TVD2PLL 13 -#define CLK_APMIXED_NR 14 +#define CLK_APMIXED_HDMI_REF 14 +#define CLK_APMIXED_NR 15 /* DDRPHY */ @@ -431,6 +431,10 @@ #define CLK_ETHSYS_CRYPTO 8 #define CLK_ETHSYS_NR 9 +/* G3DSYS */ +#define CLK_G3DSYS_CORE 1 +#define CLK_G3DSYS_NR 2 + /* BDP */ #define CLK_BDP_BRG_BA 1 diff --git a/include/dt-bindings/clock/mt7629-clk.h b/include/dt-bindings/clock/mt7629-clk.h new file mode 100644 index 000000000000..ad8e6d7f0154 --- /dev/null +++ b/include/dt-bindings/clock/mt7629-clk.h @@ -0,0 +1,203 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 MediaTek Inc. + */ + +#ifndef _DT_BINDINGS_CLK_MT7629_H +#define _DT_BINDINGS_CLK_MT7629_H + +/* TOPCKGEN */ +#define CLK_TOP_TO_U2_PHY 0 +#define CLK_TOP_TO_U2_PHY_1P 1 +#define CLK_TOP_PCIE0_PIPE_EN 2 +#define CLK_TOP_PCIE1_PIPE_EN 3 +#define CLK_TOP_SSUSB_TX250M 4 +#define CLK_TOP_SSUSB_EQ_RX250M 5 +#define CLK_TOP_SSUSB_CDR_REF 6 +#define CLK_TOP_SSUSB_CDR_FB 7 +#define CLK_TOP_SATA_ASIC 8 +#define CLK_TOP_SATA_RBC 9 +#define CLK_TOP_TO_USB3_SYS 10 +#define CLK_TOP_P1_1MHZ 11 +#define CLK_TOP_4MHZ 12 +#define CLK_TOP_P0_1MHZ 13 +#define CLK_TOP_ETH_500M 14 +#define CLK_TOP_TXCLK_SRC_PRE 15 +#define CLK_TOP_RTC 16 +#define CLK_TOP_PWM_QTR_26M 17 +#define CLK_TOP_CPUM_TCK_IN 18 +#define CLK_TOP_TO_USB3_DA_TOP 19 +#define CLK_TOP_MEMPLL 20 +#define CLK_TOP_DMPLL 21 +#define CLK_TOP_DMPLL_D4 22 +#define CLK_TOP_DMPLL_D8 23 +#define CLK_TOP_SYSPLL_D2 24 +#define CLK_TOP_SYSPLL1_D2 25 +#define CLK_TOP_SYSPLL1_D4 26 +#define CLK_TOP_SYSPLL1_D8 27 +#define CLK_TOP_SYSPLL1_D16 28 +#define CLK_TOP_SYSPLL2_D2 29 +#define CLK_TOP_SYSPLL2_D4 30 +#define CLK_TOP_SYSPLL2_D8 31 +#define CLK_TOP_SYSPLL_D5 32 +#define CLK_TOP_SYSPLL3_D2 33 +#define CLK_TOP_SYSPLL3_D4 34 +#define CLK_TOP_SYSPLL_D7 35 +#define CLK_TOP_SYSPLL4_D2 36 +#define CLK_TOP_SYSPLL4_D4 37 +#define CLK_TOP_SYSPLL4_D16 38 +#define CLK_TOP_UNIVPLL 39 +#define CLK_TOP_UNIVPLL1_D2 40 +#define CLK_TOP_UNIVPLL1_D4 41 +#define CLK_TOP_UNIVPLL1_D8 42 +#define CLK_TOP_UNIVPLL_D3 43 +#define CLK_TOP_UNIVPLL2_D2 44 +#define CLK_TOP_UNIVPLL2_D4 45 +#define CLK_TOP_UNIVPLL2_D8 46 +#define CLK_TOP_UNIVPLL2_D16 47 +#define CLK_TOP_UNIVPLL_D5 48 +#define CLK_TOP_UNIVPLL3_D2 49 +#define CLK_TOP_UNIVPLL3_D4 50 +#define CLK_TOP_UNIVPLL3_D16 51 +#define CLK_TOP_UNIVPLL_D7 52 +#define CLK_TOP_UNIVPLL_D80_D4 53 +#define CLK_TOP_UNIV48M 54 +#define CLK_TOP_SGMIIPLL_D2 55 +#define CLK_TOP_CLKXTAL_D4 56 +#define CLK_TOP_HD_FAXI 57 +#define CLK_TOP_FAXI 58 +#define CLK_TOP_F_FAUD_INTBUS 59 +#define CLK_TOP_AP2WBHIF_HCLK 60 +#define CLK_TOP_10M_INFRAO 61 +#define CLK_TOP_MSDC30_1 62 +#define CLK_TOP_SPI 63 +#define CLK_TOP_SF 64 +#define CLK_TOP_FLASH 65 +#define CLK_TOP_TO_USB3_REF 66 +#define CLK_TOP_TO_USB3_MCU 67 +#define CLK_TOP_TO_USB3_DMA 68 +#define CLK_TOP_FROM_TOP_AHB 69 +#define CLK_TOP_FROM_TOP_AXI 70 +#define CLK_TOP_PCIE1_MAC_EN 71 +#define CLK_TOP_PCIE0_MAC_EN 72 +#define CLK_TOP_AXI_SEL 73 +#define CLK_TOP_MEM_SEL 74 +#define CLK_TOP_DDRPHYCFG_SEL 75 +#define CLK_TOP_ETH_SEL 76 +#define CLK_TOP_PWM_SEL 77 +#define CLK_TOP_F10M_REF_SEL 78 +#define CLK_TOP_NFI_INFRA_SEL 79 +#define CLK_TOP_FLASH_SEL 80 +#define CLK_TOP_UART_SEL 81 +#define CLK_TOP_SPI0_SEL 82 +#define CLK_TOP_SPI1_SEL 83 +#define CLK_TOP_MSDC50_0_SEL 84 +#define CLK_TOP_MSDC30_0_SEL 85 +#define CLK_TOP_MSDC30_1_SEL 86 +#define CLK_TOP_AP2WBMCU_SEL 87 +#define CLK_TOP_AP2WBHIF_SEL 88 +#define CLK_TOP_AUDIO_SEL 89 +#define CLK_TOP_AUD_INTBUS_SEL 90 +#define CLK_TOP_PMICSPI_SEL 91 +#define CLK_TOP_SCP_SEL 92 +#define CLK_TOP_ATB_SEL 93 +#define CLK_TOP_HIF_SEL 94 +#define CLK_TOP_SATA_SEL 95 +#define CLK_TOP_U2_SEL 96 +#define CLK_TOP_AUD1_SEL 97 +#define CLK_TOP_AUD2_SEL 98 +#define CLK_TOP_IRRX_SEL 99 +#define CLK_TOP_IRTX_SEL 100 +#define CLK_TOP_SATA_MCU_SEL 101 +#define CLK_TOP_PCIE0_MCU_SEL 102 +#define CLK_TOP_PCIE1_MCU_SEL 103 +#define CLK_TOP_SSUSB_MCU_SEL 104 +#define CLK_TOP_CRYPTO_SEL 105 +#define CLK_TOP_SGMII_REF_1_SEL 106 +#define CLK_TOP_10M_SEL 107 +#define CLK_TOP_NR_CLK 108 + +/* INFRACFG */ +#define CLK_INFRA_MUX1_SEL 0 +#define CLK_INFRA_DBGCLK_PD 1 +#define CLK_INFRA_TRNG_PD 2 +#define CLK_INFRA_DEVAPC_PD 3 +#define CLK_INFRA_APXGPT_PD 4 +#define CLK_INFRA_SEJ_PD 5 +#define CLK_INFRA_NR_CLK 6 + +/* PERICFG */ +#define CLK_PERIBUS_SEL 0 +#define CLK_PERI_PWM1_PD 1 +#define CLK_PERI_PWM2_PD 2 +#define CLK_PERI_PWM3_PD 3 +#define CLK_PERI_PWM4_PD 4 +#define CLK_PERI_PWM5_PD 5 +#define CLK_PERI_PWM6_PD 6 +#define CLK_PERI_PWM7_PD 7 +#define CLK_PERI_PWM_PD 8 +#define CLK_PERI_AP_DMA_PD 9 +#define CLK_PERI_MSDC30_1_PD 10 +#define CLK_PERI_UART0_PD 11 +#define CLK_PERI_UART1_PD 12 +#define CLK_PERI_UART2_PD 13 +#define CLK_PERI_UART3_PD 14 +#define CLK_PERI_BTIF_PD 15 +#define CLK_PERI_I2C0_PD 16 +#define CLK_PERI_SPI0_PD 17 +#define CLK_PERI_SNFI_PD 18 +#define CLK_PERI_NFI_PD 19 +#define CLK_PERI_NFIECC_PD 20 +#define CLK_PERI_FLASH_PD 21 +#define CLK_PERI_NR_CLK 22 + +/* APMIXEDSYS */ +#define CLK_APMIXED_ARMPLL 0 +#define CLK_APMIXED_MAINPLL 1 +#define CLK_APMIXED_UNIV2PLL 2 +#define CLK_APMIXED_ETH1PLL 3 +#define CLK_APMIXED_ETH2PLL 4 +#define CLK_APMIXED_SGMIPLL 5 +#define CLK_APMIXED_MAIN_CORE_EN 6 +#define CLK_APMIXED_NR_CLK 7 + +/* SSUSBSYS */ +#define CLK_SSUSB_U2_PHY_1P_EN 0 +#define CLK_SSUSB_U2_PHY_EN 1 +#define CLK_SSUSB_REF_EN 2 +#define CLK_SSUSB_SYS_EN 3 +#define CLK_SSUSB_MCU_EN 4 +#define CLK_SSUSB_DMA_EN 5 +#define CLK_SSUSB_NR_CLK 6 + +/* PCIESYS */ +#define CLK_PCIE_P1_AUX_EN 0 +#define CLK_PCIE_P1_OBFF_EN 1 +#define CLK_PCIE_P1_AHB_EN 2 +#define CLK_PCIE_P1_AXI_EN 3 +#define CLK_PCIE_P1_MAC_EN 4 +#define CLK_PCIE_P1_PIPE_EN 5 +#define CLK_PCIE_P0_AUX_EN 6 +#define CLK_PCIE_P0_OBFF_EN 7 +#define CLK_PCIE_P0_AHB_EN 8 +#define CLK_PCIE_P0_AXI_EN 9 +#define CLK_PCIE_P0_MAC_EN 10 +#define CLK_PCIE_P0_PIPE_EN 11 +#define CLK_PCIE_NR_CLK 12 + +/* ETHSYS */ +#define CLK_ETH_FE_EN 0 +#define CLK_ETH_GP2_EN 1 +#define CLK_ETH_GP1_EN 2 +#define CLK_ETH_GP0_EN 3 +#define CLK_ETH_ESW_EN 4 +#define CLK_ETH_NR_CLK 5 + +/* SGMIISYS */ +#define CLK_SGMII_TX_EN 0 +#define CLK_SGMII_RX_EN 1 +#define CLK_SGMII_CDR_REF 2 +#define CLK_SGMII_CDR_FB 3 +#define CLK_SGMII_NR_CLK 4 + +#endif /* _DT_BINDINGS_CLK_MT7629_H */ diff --git a/include/dt-bindings/clock/nuvoton,npcm7xx-clock.h b/include/dt-bindings/clock/nuvoton,npcm7xx-clock.h new file mode 100644 index 000000000000..f21522605b94 --- /dev/null +++ b/include/dt-bindings/clock/nuvoton,npcm7xx-clock.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Nuvoton NPCM7xx Clock Generator binding + * clock binding number for all clocks supportted by nuvoton,npcm7xx-clk + * + * Copyright (C) 2018 Nuvoton Technologies tali.perry@nuvoton.com + * + */ + +#ifndef __DT_BINDINGS_CLOCK_NPCM7XX_H +#define __DT_BINDINGS_CLOCK_NPCM7XX_H + + +#define NPCM7XX_CLK_CPU 0 +#define NPCM7XX_CLK_GFX_PIXEL 1 +#define NPCM7XX_CLK_MC 2 +#define NPCM7XX_CLK_ADC 3 +#define NPCM7XX_CLK_AHB 4 +#define NPCM7XX_CLK_TIMER 5 +#define NPCM7XX_CLK_UART 6 +#define NPCM7XX_CLK_MMC 7 +#define NPCM7XX_CLK_SPI3 8 +#define NPCM7XX_CLK_PCI 9 +#define NPCM7XX_CLK_AXI 10 +#define NPCM7XX_CLK_APB4 11 +#define NPCM7XX_CLK_APB3 12 +#define NPCM7XX_CLK_APB2 13 +#define NPCM7XX_CLK_APB1 14 +#define NPCM7XX_CLK_APB5 15 +#define NPCM7XX_CLK_CLKOUT 16 +#define NPCM7XX_CLK_GFX 17 +#define NPCM7XX_CLK_SU 18 +#define NPCM7XX_CLK_SU48 19 +#define NPCM7XX_CLK_SDHC 20 +#define NPCM7XX_CLK_SPI0 21 +#define NPCM7XX_CLK_SPIX 22 + +#define NPCM7XX_CLK_REFCLK 23 +#define NPCM7XX_CLK_SYSBYPCK 24 +#define NPCM7XX_CLK_MCBYPCK 25 + +#define NPCM7XX_NUM_CLOCKS (NPCM7XX_CLK_MCBYPCK+1) + +#endif diff --git a/include/dt-bindings/clock/px30-cru.h b/include/dt-bindings/clock/px30-cru.h new file mode 100644 index 000000000000..00101479f7c4 --- /dev/null +++ b/include/dt-bindings/clock/px30-cru.h @@ -0,0 +1,389 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_PX30_H +#define _DT_BINDINGS_CLK_ROCKCHIP_PX30_H + +/* core clocks */ +#define PLL_APLL 1 +#define PLL_DPLL 2 +#define PLL_CPLL 3 +#define PLL_NPLL 4 +#define APLL_BOOST_H 5 +#define APLL_BOOST_L 6 +#define ARMCLK 7 + +/* sclk gates (special clocks) */ +#define USB480M 14 +#define SCLK_PDM 15 +#define SCLK_I2S0_TX 16 +#define SCLK_I2S0_TX_OUT 17 +#define SCLK_I2S0_RX 18 +#define SCLK_I2S0_RX_OUT 19 +#define SCLK_I2S1 20 +#define SCLK_I2S1_OUT 21 +#define SCLK_I2S2 22 +#define SCLK_I2S2_OUT 23 +#define SCLK_UART1 24 +#define SCLK_UART2 25 +#define SCLK_UART3 26 +#define SCLK_UART4 27 +#define SCLK_UART5 28 +#define SCLK_I2C0 29 +#define SCLK_I2C1 30 +#define SCLK_I2C2 31 +#define SCLK_I2C3 32 +#define SCLK_I2C4 33 +#define SCLK_PWM0 34 +#define SCLK_PWM1 35 +#define SCLK_SPI0 36 +#define SCLK_SPI1 37 +#define SCLK_TIMER0 38 +#define SCLK_TIMER1 39 +#define SCLK_TIMER2 40 +#define SCLK_TIMER3 41 +#define SCLK_TIMER4 42 +#define SCLK_TIMER5 43 +#define SCLK_TSADC 44 +#define SCLK_SARADC 45 +#define SCLK_OTP 46 +#define SCLK_OTP_USR 47 +#define SCLK_CRYPTO 48 +#define SCLK_CRYPTO_APK 49 +#define SCLK_DDRC 50 +#define SCLK_ISP 51 +#define SCLK_CIF_OUT 52 +#define SCLK_RGA_CORE 53 +#define SCLK_VOPB_PWM 54 +#define SCLK_NANDC 55 +#define SCLK_SDIO 56 +#define SCLK_EMMC 57 +#define SCLK_SFC 58 +#define SCLK_SDMMC 59 +#define SCLK_OTG_ADP 60 +#define SCLK_GMAC_SRC 61 +#define SCLK_GMAC 62 +#define SCLK_GMAC_RX_TX 63 +#define SCLK_MAC_REF 64 +#define SCLK_MAC_REFOUT 65 +#define SCLK_MAC_OUT 66 +#define SCLK_SDMMC_DRV 67 +#define SCLK_SDMMC_SAMPLE 68 +#define SCLK_SDIO_DRV 69 +#define SCLK_SDIO_SAMPLE 70 +#define SCLK_EMMC_DRV 71 +#define SCLK_EMMC_SAMPLE 72 +#define SCLK_GPU 73 +#define SCLK_PVTM 74 +#define SCLK_CORE_VPU 75 +#define SCLK_GMAC_RMII 76 +#define SCLK_UART2_SRC 77 +#define SCLK_NANDC_DIV 78 +#define SCLK_NANDC_DIV50 79 +#define SCLK_SDIO_DIV 80 +#define SCLK_SDIO_DIV50 81 +#define SCLK_EMMC_DIV 82 +#define SCLK_EMMC_DIV50 83 +#define SCLK_DDRCLK 84 +#define SCLK_UART1_SRC 85 + +/* dclk gates */ +#define DCLK_VOPB 150 +#define DCLK_VOPL 151 + +/* aclk gates */ +#define ACLK_GPU 170 +#define ACLK_BUS_PRE 171 +#define ACLK_CRYPTO 172 +#define ACLK_VI_PRE 173 +#define ACLK_VO_PRE 174 +#define ACLK_VPU 175 +#define ACLK_PERI_PRE 176 +#define ACLK_GMAC 178 +#define ACLK_CIF 179 +#define ACLK_ISP 180 +#define ACLK_VOPB 181 +#define ACLK_VOPL 182 +#define ACLK_RGA 183 +#define ACLK_GIC 184 +#define ACLK_DCF 186 +#define ACLK_DMAC 187 +#define ACLK_BUS_SRC 188 +#define ACLK_PERI_SRC 189 + +/* hclk gates */ +#define HCLK_BUS_PRE 240 +#define HCLK_CRYPTO 241 +#define HCLK_VI_PRE 242 +#define HCLK_VO_PRE 243 +#define HCLK_VPU 244 +#define HCLK_PERI_PRE 245 +#define HCLK_MMC_NAND 246 +#define HCLK_SDMMC 247 +#define HCLK_USB 248 +#define HCLK_CIF 249 +#define HCLK_ISP 250 +#define HCLK_VOPB 251 +#define HCLK_VOPL 252 +#define HCLK_RGA 253 +#define HCLK_NANDC 254 +#define HCLK_SDIO 255 +#define HCLK_EMMC 256 +#define HCLK_SFC 257 +#define HCLK_OTG 258 +#define HCLK_HOST 259 +#define HCLK_HOST_ARB 260 +#define HCLK_PDM 261 +#define HCLK_I2S0 262 +#define HCLK_I2S1 263 +#define HCLK_I2S2 264 + +/* pclk gates */ +#define PCLK_BUS_PRE 320 +#define PCLK_DDR 321 +#define PCLK_VO_PRE 322 +#define PCLK_GMAC 323 +#define PCLK_MIPI_DSI 324 +#define PCLK_MIPIDSIPHY 325 +#define PCLK_MIPICSIPHY 326 +#define PCLK_USB_GRF 327 +#define PCLK_DCF 328 +#define PCLK_UART1 329 +#define PCLK_UART2 330 +#define PCLK_UART3 331 +#define PCLK_UART4 332 +#define PCLK_UART5 333 +#define PCLK_I2C0 334 +#define PCLK_I2C1 335 +#define PCLK_I2C2 336 +#define PCLK_I2C3 337 +#define PCLK_I2C4 338 +#define PCLK_PWM0 339 +#define PCLK_PWM1 340 +#define PCLK_SPI0 341 +#define PCLK_SPI1 342 +#define PCLK_SARADC 343 +#define PCLK_TSADC 344 +#define PCLK_TIMER 345 +#define PCLK_OTP_NS 346 +#define PCLK_WDT_NS 347 +#define PCLK_GPIO1 348 +#define PCLK_GPIO2 349 +#define PCLK_GPIO3 350 +#define PCLK_ISP 351 +#define PCLK_CIF 352 +#define PCLK_OTP_PHY 353 + +#define CLK_NR_CLKS (PCLK_OTP_PHY + 1) + +/* pmu-clocks indices */ + +#define PLL_GPLL 1 + +#define SCLK_RTC32K_PMU 4 +#define SCLK_WIFI_PMU 5 +#define SCLK_UART0_PMU 6 +#define SCLK_PVTM_PMU 7 +#define PCLK_PMU_PRE 8 +#define SCLK_REF24M_PMU 9 +#define SCLK_USBPHY_REF 10 +#define SCLK_MIPIDSIPHY_REF 11 + +#define XIN24M_DIV 12 + +#define PCLK_GPIO0_PMU 20 +#define PCLK_UART0_PMU 21 + +#define CLKPMU_NR_CLKS (PCLK_UART0_PMU + 1) + +/* soft-reset indices */ +#define SRST_CORE0_PO 0 +#define SRST_CORE1_PO 1 +#define SRST_CORE2_PO 2 +#define SRST_CORE3_PO 3 +#define SRST_CORE0 4 +#define SRST_CORE1 5 +#define SRST_CORE2 6 +#define SRST_CORE3 7 +#define SRST_CORE0_DBG 8 +#define SRST_CORE1_DBG 9 +#define SRST_CORE2_DBG 10 +#define SRST_CORE3_DBG 11 +#define SRST_TOPDBG 12 +#define SRST_CORE_NOC 13 +#define SRST_STRC_A 14 +#define SRST_L2C 15 + +#define SRST_DAP 16 +#define SRST_CORE_PVTM 17 +#define SRST_GPU 18 +#define SRST_GPU_NIU 19 +#define SRST_UPCTL2 20 +#define SRST_UPCTL2_A 21 +#define SRST_UPCTL2_P 22 +#define SRST_MSCH 23 +#define SRST_MSCH_P 24 +#define SRST_DDRMON_P 25 +#define SRST_DDRSTDBY_P 26 +#define SRST_DDRSTDBY 27 +#define SRST_DDRGRF_p 28 +#define SRST_AXI_SPLIT_A 29 +#define SRST_AXI_CMD_A 30 +#define SRST_AXI_CMD_P 31 + +#define SRST_DDRPHY 32 +#define SRST_DDRPHYDIV 33 +#define SRST_DDRPHY_P 34 +#define SRST_VPU_A 36 +#define SRST_VPU_NIU_A 37 +#define SRST_VPU_H 38 +#define SRST_VPU_NIU_H 39 +#define SRST_VI_NIU_A 40 +#define SRST_VI_NIU_H 41 +#define SRST_ISP_H 42 +#define SRST_ISP 43 +#define SRST_CIF_A 44 +#define SRST_CIF_H 45 +#define SRST_CIF_PCLKIN 46 +#define SRST_MIPICSIPHY_P 47 + +#define SRST_VO_NIU_A 48 +#define SRST_VO_NIU_H 49 +#define SRST_VO_NIU_P 50 +#define SRST_VOPB_A 51 +#define SRST_VOPB_H 52 +#define SRST_VOPB 53 +#define SRST_PWM_VOPB 54 +#define SRST_VOPL_A 55 +#define SRST_VOPL_H 56 +#define SRST_VOPL 57 +#define SRST_RGA_A 58 +#define SRST_RGA_H 59 +#define SRST_RGA 60 +#define SRST_MIPIDSI_HOST_P 61 +#define SRST_MIPIDSIPHY_P 62 +#define SRST_VPU_CORE 63 + +#define SRST_PERI_NIU_A 64 +#define SRST_USB_NIU_H 65 +#define SRST_USB2OTG_H 66 +#define SRST_USB2OTG 67 +#define SRST_USB2OTG_ADP 68 +#define SRST_USB2HOST_H 69 +#define SRST_USB2HOST_ARB_H 70 +#define SRST_USB2HOST_AUX_H 71 +#define SRST_USB2HOST_EHCI 72 +#define SRST_USB2HOST 73 +#define SRST_USBPHYPOR 74 +#define SRST_USBPHY_OTG_PORT 75 +#define SRST_USBPHY_HOST_PORT 76 +#define SRST_USBPHY_GRF 77 +#define SRST_CPU_BOOST_P 78 +#define SRST_CPU_BOOST 79 + +#define SRST_MMC_NAND_NIU_H 80 +#define SRST_SDIO_H 81 +#define SRST_EMMC_H 82 +#define SRST_SFC_H 83 +#define SRST_SFC 84 +#define SRST_SDCARD_NIU_H 85 +#define SRST_SDMMC_H 86 +#define SRST_NANDC_H 89 +#define SRST_NANDC 90 +#define SRST_GMAC_NIU_A 92 +#define SRST_GMAC_NIU_P 93 +#define SRST_GMAC_A 94 + +#define SRST_PMU_NIU_P 96 +#define SRST_PMU_SGRF_P 97 +#define SRST_PMU_GRF_P 98 +#define SRST_PMU 99 +#define SRST_PMU_MEM_P 100 +#define SRST_PMU_GPIO0_P 101 +#define SRST_PMU_UART0_P 102 +#define SRST_PMU_CRU_P 103 +#define SRST_PMU_PVTM 104 +#define SRST_PMU_UART 105 +#define SRST_PMU_NIU_H 106 +#define SRST_PMU_DDR_FAIL_SAVE 107 +#define SRST_PMU_CORE_PERF_A 108 +#define SRST_PMU_CORE_GRF_P 109 +#define SRST_PMU_GPU_PERF_A 110 +#define SRST_PMU_GPU_GRF_P 111 + +#define SRST_CRYPTO_NIU_A 112 +#define SRST_CRYPTO_NIU_H 113 +#define SRST_CRYPTO_A 114 +#define SRST_CRYPTO_H 115 +#define SRST_CRYPTO 116 +#define SRST_CRYPTO_APK 117 +#define SRST_BUS_NIU_H 120 +#define SRST_USB_NIU_P 121 +#define SRST_BUS_TOP_NIU_P 122 +#define SRST_INTMEM_A 123 +#define SRST_GIC_A 124 +#define SRST_ROM_H 126 +#define SRST_DCF_A 127 + +#define SRST_DCF_P 128 +#define SRST_PDM_H 129 +#define SRST_PDM 130 +#define SRST_I2S0_H 131 +#define SRST_I2S0_TX 132 +#define SRST_I2S1_H 133 +#define SRST_I2S1 134 +#define SRST_I2S2_H 135 +#define SRST_I2S2 136 +#define SRST_UART1_P 137 +#define SRST_UART1 138 +#define SRST_UART2_P 139 +#define SRST_UART2 140 +#define SRST_UART3_P 141 +#define SRST_UART3 142 +#define SRST_UART4_P 143 + +#define SRST_UART4 144 +#define SRST_UART5_P 145 +#define SRST_UART5 146 +#define SRST_I2C0_P 147 +#define SRST_I2C0 148 +#define SRST_I2C1_P 149 +#define SRST_I2C1 150 +#define SRST_I2C2_P 151 +#define SRST_I2C2 152 +#define SRST_I2C3_P 153 +#define SRST_I2C3 154 +#define SRST_PWM0_P 157 +#define SRST_PWM0 158 +#define SRST_PWM1_P 159 + +#define SRST_PWM1 160 +#define SRST_SPI0_P 161 +#define SRST_SPI0 162 +#define SRST_SPI1_P 163 +#define SRST_SPI1 164 +#define SRST_SARADC_P 165 +#define SRST_SARADC 166 +#define SRST_TSADC_P 167 +#define SRST_TSADC 168 +#define SRST_TIMER_P 169 +#define SRST_TIMER0 170 +#define SRST_TIMER1 171 +#define SRST_TIMER2 172 +#define SRST_TIMER3 173 +#define SRST_TIMER4 174 +#define SRST_TIMER5 175 + +#define SRST_OTP_NS_P 176 +#define SRST_OTP_NS_SBPI 177 +#define SRST_OTP_NS_USR 178 +#define SRST_OTP_PHY_P 179 +#define SRST_OTP_PHY 180 +#define SRST_WDT_NS_P 181 +#define SRST_GPIO1_P 182 +#define SRST_GPIO2_P 183 +#define SRST_GPIO3_P 184 +#define SRST_SGRF_P 185 +#define SRST_GRF_P 186 +#define SRST_I2S0_RX 191 + +#endif diff --git a/include/dt-bindings/clock/pxa-clock.h b/include/dt-bindings/clock/pxa-clock.h index e65803b1dc7e..0b0fd2b01538 100644 --- a/include/dt-bindings/clock/pxa-clock.h +++ b/include/dt-bindings/clock/pxa-clock.h @@ -72,6 +72,7 @@ #define CLK_USIM 58 #define CLK_USIM1 59 #define CLK_USMI0 60 -#define CLK_MAX 61 +#define CLK_OSC32k768 61 +#define CLK_MAX 62 #endif diff --git a/include/dt-bindings/clock/qcom,camcc-sdm845.h b/include/dt-bindings/clock/qcom,camcc-sdm845.h new file mode 100644 index 000000000000..4f7a2d2320bf --- /dev/null +++ b/include/dt-bindings/clock/qcom,camcc-sdm845.h @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_SDM_CAM_CC_SDM845_H +#define _DT_BINDINGS_CLK_SDM_CAM_CC_SDM845_H + +/* CAM_CC clock registers */ +#define CAM_CC_BPS_AHB_CLK 0 +#define CAM_CC_BPS_AREG_CLK 1 +#define CAM_CC_BPS_AXI_CLK 2 +#define CAM_CC_BPS_CLK 3 +#define CAM_CC_BPS_CLK_SRC 4 +#define CAM_CC_CAMNOC_ATB_CLK 5 +#define CAM_CC_CAMNOC_AXI_CLK 6 +#define CAM_CC_CCI_CLK 7 +#define CAM_CC_CCI_CLK_SRC 8 +#define CAM_CC_CPAS_AHB_CLK 9 +#define CAM_CC_CPHY_RX_CLK_SRC 10 +#define CAM_CC_CSI0PHYTIMER_CLK 11 +#define CAM_CC_CSI0PHYTIMER_CLK_SRC 12 +#define CAM_CC_CSI1PHYTIMER_CLK 13 +#define CAM_CC_CSI1PHYTIMER_CLK_SRC 14 +#define CAM_CC_CSI2PHYTIMER_CLK 15 +#define CAM_CC_CSI2PHYTIMER_CLK_SRC 16 +#define CAM_CC_CSI3PHYTIMER_CLK 17 +#define CAM_CC_CSI3PHYTIMER_CLK_SRC 18 +#define CAM_CC_CSIPHY0_CLK 19 +#define CAM_CC_CSIPHY1_CLK 20 +#define CAM_CC_CSIPHY2_CLK 21 +#define CAM_CC_CSIPHY3_CLK 22 +#define CAM_CC_FAST_AHB_CLK_SRC 23 +#define CAM_CC_FD_CORE_CLK 24 +#define CAM_CC_FD_CORE_CLK_SRC 25 +#define CAM_CC_FD_CORE_UAR_CLK 26 +#define CAM_CC_ICP_APB_CLK 27 +#define CAM_CC_ICP_ATB_CLK 28 +#define CAM_CC_ICP_CLK 29 +#define CAM_CC_ICP_CLK_SRC 30 +#define CAM_CC_ICP_CTI_CLK 31 +#define CAM_CC_ICP_TS_CLK 32 +#define CAM_CC_IFE_0_AXI_CLK 33 +#define CAM_CC_IFE_0_CLK 34 +#define CAM_CC_IFE_0_CLK_SRC 35 +#define CAM_CC_IFE_0_CPHY_RX_CLK 36 +#define CAM_CC_IFE_0_CSID_CLK 37 +#define CAM_CC_IFE_0_CSID_CLK_SRC 38 +#define CAM_CC_IFE_0_DSP_CLK 39 +#define CAM_CC_IFE_1_AXI_CLK 40 +#define CAM_CC_IFE_1_CLK 41 +#define CAM_CC_IFE_1_CLK_SRC 42 +#define CAM_CC_IFE_1_CPHY_RX_CLK 43 +#define CAM_CC_IFE_1_CSID_CLK 44 +#define CAM_CC_IFE_1_CSID_CLK_SRC 45 +#define CAM_CC_IFE_1_DSP_CLK 46 +#define CAM_CC_IFE_LITE_CLK 47 +#define CAM_CC_IFE_LITE_CLK_SRC 48 +#define CAM_CC_IFE_LITE_CPHY_RX_CLK 49 +#define CAM_CC_IFE_LITE_CSID_CLK 50 +#define CAM_CC_IFE_LITE_CSID_CLK_SRC 51 +#define CAM_CC_IPE_0_AHB_CLK 52 +#define CAM_CC_IPE_0_AREG_CLK 53 +#define CAM_CC_IPE_0_AXI_CLK 54 +#define CAM_CC_IPE_0_CLK 55 +#define CAM_CC_IPE_0_CLK_SRC 56 +#define CAM_CC_IPE_1_AHB_CLK 57 +#define CAM_CC_IPE_1_AREG_CLK 58 +#define CAM_CC_IPE_1_AXI_CLK 59 +#define CAM_CC_IPE_1_CLK 60 +#define CAM_CC_IPE_1_CLK_SRC 61 +#define CAM_CC_JPEG_CLK 62 +#define CAM_CC_JPEG_CLK_SRC 63 +#define CAM_CC_LRME_CLK 64 +#define CAM_CC_LRME_CLK_SRC 65 +#define CAM_CC_MCLK0_CLK 66 +#define CAM_CC_MCLK0_CLK_SRC 67 +#define CAM_CC_MCLK1_CLK 68 +#define CAM_CC_MCLK1_CLK_SRC 69 +#define CAM_CC_MCLK2_CLK 70 +#define CAM_CC_MCLK2_CLK_SRC 71 +#define CAM_CC_MCLK3_CLK 72 +#define CAM_CC_MCLK3_CLK_SRC 73 +#define CAM_CC_PLL0 74 +#define CAM_CC_PLL0_OUT_EVEN 75 +#define CAM_CC_PLL1 76 +#define CAM_CC_PLL1_OUT_EVEN 77 +#define CAM_CC_PLL2 78 +#define CAM_CC_PLL2_OUT_EVEN 79 +#define CAM_CC_PLL3 80 +#define CAM_CC_PLL3_OUT_EVEN 81 +#define CAM_CC_SLOW_AHB_CLK_SRC 82 +#define CAM_CC_SOC_AHB_CLK 83 +#define CAM_CC_SYS_TMR_CLK 84 + +/* CAM_CC Resets */ +#define TITAN_CAM_CC_CCI_BCR 0 +#define TITAN_CAM_CC_CPAS_BCR 1 +#define TITAN_CAM_CC_CSI0PHY_BCR 2 +#define TITAN_CAM_CC_CSI1PHY_BCR 3 +#define TITAN_CAM_CC_CSI2PHY_BCR 4 +#define TITAN_CAM_CC_MCLK0_BCR 5 +#define TITAN_CAM_CC_MCLK1_BCR 6 +#define TITAN_CAM_CC_MCLK2_BCR 7 +#define TITAN_CAM_CC_MCLK3_BCR 8 +#define TITAN_CAM_CC_TITAN_TOP_BCR 9 + +/* CAM_CC GDSCRs */ +#define BPS_GDSC 0 +#define IPE_0_GDSC 1 +#define IPE_1_GDSC 2 +#define IFE_0_GDSC 3 +#define IFE_1_GDSC 4 +#define TITAN_TOP_GDSC 5 + +#endif diff --git a/include/dt-bindings/clock/qcom,dispcc-sdm845.h b/include/dt-bindings/clock/qcom,dispcc-sdm845.h new file mode 100644 index 000000000000..11eed4bc9646 --- /dev/null +++ b/include/dt-bindings/clock/qcom,dispcc-sdm845.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_SDM_DISP_CC_SDM845_H +#define _DT_BINDINGS_CLK_SDM_DISP_CC_SDM845_H + +/* DISP_CC clock registers */ +#define DISP_CC_MDSS_AHB_CLK 0 +#define DISP_CC_MDSS_AXI_CLK 1 +#define DISP_CC_MDSS_BYTE0_CLK 2 +#define DISP_CC_MDSS_BYTE0_CLK_SRC 3 +#define DISP_CC_MDSS_BYTE0_INTF_CLK 4 +#define DISP_CC_MDSS_BYTE1_CLK 5 +#define DISP_CC_MDSS_BYTE1_CLK_SRC 6 +#define DISP_CC_MDSS_BYTE1_INTF_CLK 7 +#define DISP_CC_MDSS_ESC0_CLK 8 +#define DISP_CC_MDSS_ESC0_CLK_SRC 9 +#define DISP_CC_MDSS_ESC1_CLK 10 +#define DISP_CC_MDSS_ESC1_CLK_SRC 11 +#define DISP_CC_MDSS_MDP_CLK 12 +#define DISP_CC_MDSS_MDP_CLK_SRC 13 +#define DISP_CC_MDSS_MDP_LUT_CLK 14 +#define DISP_CC_MDSS_PCLK0_CLK 15 +#define DISP_CC_MDSS_PCLK0_CLK_SRC 16 +#define DISP_CC_MDSS_PCLK1_CLK 17 +#define DISP_CC_MDSS_PCLK1_CLK_SRC 18 +#define DISP_CC_MDSS_ROT_CLK 19 +#define DISP_CC_MDSS_ROT_CLK_SRC 20 +#define DISP_CC_MDSS_RSCC_AHB_CLK 21 +#define DISP_CC_MDSS_RSCC_VSYNC_CLK 22 +#define DISP_CC_MDSS_VSYNC_CLK 23 +#define DISP_CC_MDSS_VSYNC_CLK_SRC 24 +#define DISP_CC_PLL0 25 +#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 26 +#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 27 + +/* DISP_CC Reset */ +#define DISP_CC_MDSS_RSCC_BCR 0 + +/* DISP_CC GDSCR */ +#define MDSS_GDSC 0 + +#endif diff --git a/include/dt-bindings/clock/qcom,gcc-msm8960.h b/include/dt-bindings/clock/qcom,gcc-msm8960.h index 7d20eedfee98..e02742fc81cc 100644 --- a/include/dt-bindings/clock/qcom,gcc-msm8960.h +++ b/include/dt-bindings/clock/qcom,gcc-msm8960.h @@ -319,5 +319,7 @@ #define CE3_SRC 303 #define CE3_CORE_CLK 304 #define CE3_H_CLK 305 +#define PLL16 306 +#define PLL17 307 #endif diff --git a/include/dt-bindings/clock/qcom,gcc-msm8996.h b/include/dt-bindings/clock/qcom,gcc-msm8996.h index 75b07cf5eed0..db80f2ee571b 100644 --- a/include/dt-bindings/clock/qcom,gcc-msm8996.h +++ b/include/dt-bindings/clock/qcom,gcc-msm8996.h @@ -235,6 +235,15 @@ #define GCC_RX1_USB2_CLKREF_CLK 218 #define GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK 219 #define GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK 220 +#define GCC_EDP_CLKREF_CLK 221 +#define GCC_MSS_CFG_AHB_CLK 222 +#define GCC_MSS_Q6_BIMC_AXI_CLK 223 +#define GCC_MSS_SNOC_AXI_CLK 224 +#define GCC_MSS_MNOC_BIMC_AXI_CLK 225 +#define GCC_DCC_AHB_CLK 226 +#define GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK 227 +#define GCC_MMSS_GPLL0_DIV_CLK 228 +#define GCC_MSS_GPLL0_DIV_CLK 229 #define GCC_SYSTEM_NOC_BCR 0 #define GCC_CONFIG_NOC_BCR 1 diff --git a/include/dt-bindings/clock/qcom,gcc-msm8998.h b/include/dt-bindings/clock/qcom,gcc-msm8998.h new file mode 100644 index 000000000000..ba84bbab5c83 --- /dev/null +++ b/include/dt-bindings/clock/qcom,gcc-msm8998.h @@ -0,0 +1,302 @@ +/* + * Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DT_BINDINGS_CLK_MSM_GCC_COBALT_H +#define _DT_BINDINGS_CLK_MSM_GCC_COBALT_H + +#define BLSP1_QUP1_I2C_APPS_CLK_SRC 0 +#define BLSP1_QUP1_SPI_APPS_CLK_SRC 1 +#define BLSP1_QUP2_I2C_APPS_CLK_SRC 2 +#define BLSP1_QUP2_SPI_APPS_CLK_SRC 3 +#define BLSP1_QUP3_I2C_APPS_CLK_SRC 4 +#define BLSP1_QUP3_SPI_APPS_CLK_SRC 5 +#define BLSP1_QUP4_I2C_APPS_CLK_SRC 6 +#define BLSP1_QUP4_SPI_APPS_CLK_SRC 7 +#define BLSP1_QUP5_I2C_APPS_CLK_SRC 8 +#define BLSP1_QUP5_SPI_APPS_CLK_SRC 9 +#define BLSP1_QUP6_I2C_APPS_CLK_SRC 10 +#define BLSP1_QUP6_SPI_APPS_CLK_SRC 11 +#define BLSP1_UART1_APPS_CLK_SRC 12 +#define BLSP1_UART2_APPS_CLK_SRC 13 +#define BLSP1_UART3_APPS_CLK_SRC 14 +#define BLSP2_QUP1_I2C_APPS_CLK_SRC 15 +#define BLSP2_QUP1_SPI_APPS_CLK_SRC 16 +#define BLSP2_QUP2_I2C_APPS_CLK_SRC 17 +#define BLSP2_QUP2_SPI_APPS_CLK_SRC 18 +#define BLSP2_QUP3_I2C_APPS_CLK_SRC 19 +#define BLSP2_QUP3_SPI_APPS_CLK_SRC 20 +#define BLSP2_QUP4_I2C_APPS_CLK_SRC 21 +#define BLSP2_QUP4_SPI_APPS_CLK_SRC 22 +#define BLSP2_QUP5_I2C_APPS_CLK_SRC 23 +#define BLSP2_QUP5_SPI_APPS_CLK_SRC 24 +#define BLSP2_QUP6_I2C_APPS_CLK_SRC 25 +#define BLSP2_QUP6_SPI_APPS_CLK_SRC 26 +#define BLSP2_UART1_APPS_CLK_SRC 27 +#define BLSP2_UART2_APPS_CLK_SRC 28 +#define BLSP2_UART3_APPS_CLK_SRC 29 +#define GCC_AGGRE1_NOC_XO_CLK 30 +#define GCC_AGGRE1_UFS_AXI_CLK 31 +#define GCC_AGGRE1_USB3_AXI_CLK 32 +#define GCC_APSS_QDSS_TSCTR_DIV2_CLK 33 +#define GCC_APSS_QDSS_TSCTR_DIV8_CLK 34 +#define GCC_BIMC_HMSS_AXI_CLK 35 +#define GCC_BIMC_MSS_Q6_AXI_CLK 36 +#define GCC_BLSP1_AHB_CLK 37 +#define GCC_BLSP1_QUP1_I2C_APPS_CLK 38 +#define GCC_BLSP1_QUP1_SPI_APPS_CLK 39 +#define GCC_BLSP1_QUP2_I2C_APPS_CLK 40 +#define GCC_BLSP1_QUP2_SPI_APPS_CLK 41 +#define GCC_BLSP1_QUP3_I2C_APPS_CLK 42 +#define GCC_BLSP1_QUP3_SPI_APPS_CLK 43 +#define GCC_BLSP1_QUP4_I2C_APPS_CLK 44 +#define GCC_BLSP1_QUP4_SPI_APPS_CLK 45 +#define GCC_BLSP1_QUP5_I2C_APPS_CLK 46 +#define GCC_BLSP1_QUP5_SPI_APPS_CLK 47 +#define GCC_BLSP1_QUP6_I2C_APPS_CLK 48 +#define GCC_BLSP1_QUP6_SPI_APPS_CLK 49 +#define GCC_BLSP1_SLEEP_CLK 50 +#define GCC_BLSP1_UART1_APPS_CLK 51 +#define GCC_BLSP1_UART2_APPS_CLK 52 +#define GCC_BLSP1_UART3_APPS_CLK 53 +#define GCC_BLSP2_AHB_CLK 54 +#define GCC_BLSP2_QUP1_I2C_APPS_CLK 55 +#define GCC_BLSP2_QUP1_SPI_APPS_CLK 56 +#define GCC_BLSP2_QUP2_I2C_APPS_CLK 57 +#define GCC_BLSP2_QUP2_SPI_APPS_CLK 58 +#define GCC_BLSP2_QUP3_I2C_APPS_CLK 59 +#define GCC_BLSP2_QUP3_SPI_APPS_CLK 60 +#define GCC_BLSP2_QUP4_I2C_APPS_CLK 61 +#define GCC_BLSP2_QUP4_SPI_APPS_CLK 62 +#define GCC_BLSP2_QUP5_I2C_APPS_CLK 63 +#define GCC_BLSP2_QUP5_SPI_APPS_CLK 64 +#define GCC_BLSP2_QUP6_I2C_APPS_CLK 65 +#define GCC_BLSP2_QUP6_SPI_APPS_CLK 66 +#define GCC_BLSP2_SLEEP_CLK 67 +#define GCC_BLSP2_UART1_APPS_CLK 68 +#define GCC_BLSP2_UART2_APPS_CLK 69 +#define GCC_BLSP2_UART3_APPS_CLK 70 +#define GCC_CFG_NOC_USB3_AXI_CLK 71 +#define GCC_GP1_CLK 72 +#define GCC_GP2_CLK 73 +#define GCC_GP3_CLK 74 +#define GCC_GPU_BIMC_GFX_CLK 75 +#define GCC_GPU_BIMC_GFX_SRC_CLK 76 +#define GCC_GPU_CFG_AHB_CLK 77 +#define GCC_GPU_SNOC_DVM_GFX_CLK 78 +#define GCC_HMSS_AHB_CLK 79 +#define GCC_HMSS_AT_CLK 80 +#define GCC_HMSS_DVM_BUS_CLK 81 +#define GCC_HMSS_RBCPR_CLK 82 +#define GCC_HMSS_TRIG_CLK 83 +#define GCC_LPASS_AT_CLK 84 +#define GCC_LPASS_TRIG_CLK 85 +#define GCC_MMSS_NOC_CFG_AHB_CLK 86 +#define GCC_MMSS_QM_AHB_CLK 87 +#define GCC_MMSS_QM_CORE_CLK 88 +#define GCC_MMSS_SYS_NOC_AXI_CLK 89 +#define GCC_MSS_AT_CLK 90 +#define GCC_PCIE_0_AUX_CLK 91 +#define GCC_PCIE_0_CFG_AHB_CLK 92 +#define GCC_PCIE_0_MSTR_AXI_CLK 93 +#define GCC_PCIE_0_PIPE_CLK 94 +#define GCC_PCIE_0_SLV_AXI_CLK 95 +#define GCC_PCIE_PHY_AUX_CLK 96 +#define GCC_PDM2_CLK 97 +#define GCC_PDM_AHB_CLK 98 +#define GCC_PDM_XO4_CLK 99 +#define GCC_PRNG_AHB_CLK 100 +#define GCC_SDCC2_AHB_CLK 101 +#define GCC_SDCC2_APPS_CLK 102 +#define GCC_SDCC4_AHB_CLK 103 +#define GCC_SDCC4_APPS_CLK 104 +#define GCC_TSIF_AHB_CLK 105 +#define GCC_TSIF_INACTIVITY_TIMERS_CLK 106 +#define GCC_TSIF_REF_CLK 107 +#define GCC_UFS_AHB_CLK 108 +#define GCC_UFS_AXI_CLK 109 +#define GCC_UFS_ICE_CORE_CLK 110 +#define GCC_UFS_PHY_AUX_CLK 111 +#define GCC_UFS_RX_SYMBOL_0_CLK 112 +#define GCC_UFS_RX_SYMBOL_1_CLK 113 +#define GCC_UFS_TX_SYMBOL_0_CLK 114 +#define GCC_UFS_UNIPRO_CORE_CLK 115 +#define GCC_USB30_MASTER_CLK 116 +#define GCC_USB30_MOCK_UTMI_CLK 117 +#define GCC_USB30_SLEEP_CLK 118 +#define GCC_USB3_PHY_AUX_CLK 119 +#define GCC_USB3_PHY_PIPE_CLK 120 +#define GCC_USB_PHY_CFG_AHB2PHY_CLK 121 +#define GP1_CLK_SRC 122 +#define GP2_CLK_SRC 123 +#define GP3_CLK_SRC 124 +#define GPLL0 125 +#define GPLL0_OUT_EVEN 126 +#define GPLL0_OUT_MAIN 127 +#define GPLL0_OUT_ODD 128 +#define GPLL0_OUT_TEST 129 +#define GPLL1 130 +#define GPLL1_OUT_EVEN 131 +#define GPLL1_OUT_MAIN 132 +#define GPLL1_OUT_ODD 133 +#define GPLL1_OUT_TEST 134 +#define GPLL2 135 +#define GPLL2_OUT_EVEN 136 +#define GPLL2_OUT_MAIN 137 +#define GPLL2_OUT_ODD 138 +#define GPLL2_OUT_TEST 139 +#define GPLL3 140 +#define GPLL3_OUT_EVEN 141 +#define GPLL3_OUT_MAIN 142 +#define GPLL3_OUT_ODD 143 +#define GPLL3_OUT_TEST 144 +#define GPLL4 145 +#define GPLL4_OUT_EVEN 146 +#define GPLL4_OUT_MAIN 147 +#define GPLL4_OUT_ODD 148 +#define GPLL4_OUT_TEST 149 +#define GPLL6 150 +#define GPLL6_OUT_EVEN 151 +#define GPLL6_OUT_MAIN 152 +#define GPLL6_OUT_ODD 153 +#define GPLL6_OUT_TEST 154 +#define HMSS_AHB_CLK_SRC 155 +#define HMSS_RBCPR_CLK_SRC 156 +#define PCIE_AUX_CLK_SRC 157 +#define PDM2_CLK_SRC 158 +#define SDCC2_APPS_CLK_SRC 159 +#define SDCC4_APPS_CLK_SRC 160 +#define TSIF_REF_CLK_SRC 161 +#define UFS_AXI_CLK_SRC 162 +#define USB30_MASTER_CLK_SRC 163 +#define USB30_MOCK_UTMI_CLK_SRC 164 +#define USB3_PHY_AUX_CLK_SRC 165 +#define GCC_USB3_CLKREF_CLK 166 +#define GCC_HDMI_CLKREF_CLK 167 +#define GCC_UFS_CLKREF_CLK 168 +#define GCC_PCIE_CLKREF_CLK 169 +#define GCC_RX1_USB2_CLKREF_CLK 170 + +#define PCIE_0_GDSC 0 +#define UFS_GDSC 1 +#define USB_30_GDSC 2 + +#define GCC_BLSP1_QUP1_BCR 0 +#define GCC_BLSP1_QUP2_BCR 1 +#define GCC_BLSP1_QUP3_BCR 2 +#define GCC_BLSP1_QUP4_BCR 3 +#define GCC_BLSP1_QUP5_BCR 4 +#define GCC_BLSP1_QUP6_BCR 5 +#define GCC_BLSP2_QUP1_BCR 6 +#define GCC_BLSP2_QUP2_BCR 7 +#define GCC_BLSP2_QUP3_BCR 8 +#define GCC_BLSP2_QUP4_BCR 9 +#define GCC_BLSP2_QUP5_BCR 10 +#define GCC_BLSP2_QUP6_BCR 11 +#define GCC_PCIE_0_BCR 12 +#define GCC_PDM_BCR 13 +#define GCC_SDCC2_BCR 14 +#define GCC_SDCC4_BCR 15 +#define GCC_TSIF_BCR 16 +#define GCC_UFS_BCR 17 +#define GCC_USB_30_BCR 18 +#define GCC_SYSTEM_NOC_BCR 19 +#define GCC_CONFIG_NOC_BCR 20 +#define GCC_AHB2PHY_EAST_BCR 21 +#define GCC_IMEM_BCR 22 +#define GCC_PIMEM_BCR 23 +#define GCC_MMSS_BCR 24 +#define GCC_QDSS_BCR 25 +#define GCC_WCSS_BCR 26 +#define GCC_BLSP1_BCR 27 +#define GCC_BLSP1_UART1_BCR 28 +#define GCC_BLSP1_UART2_BCR 29 +#define GCC_BLSP1_UART3_BCR 30 +#define GCC_CM_PHY_REFGEN1_BCR 31 +#define GCC_CM_PHY_REFGEN2_BCR 32 +#define GCC_BLSP2_BCR 33 +#define GCC_BLSP2_UART1_BCR 34 +#define GCC_BLSP2_UART2_BCR 35 +#define GCC_BLSP2_UART3_BCR 36 +#define GCC_SRAM_SENSOR_BCR 37 +#define GCC_PRNG_BCR 38 +#define GCC_TSIF_0_RESET 39 +#define GCC_TSIF_1_RESET 40 +#define GCC_TCSR_BCR 41 +#define GCC_BOOT_ROM_BCR 42 +#define GCC_MSG_RAM_BCR 43 +#define GCC_TLMM_BCR 44 +#define GCC_MPM_BCR 45 +#define GCC_SEC_CTRL_BCR 46 +#define GCC_SPMI_BCR 47 +#define GCC_SPDM_BCR 48 +#define GCC_CE1_BCR 49 +#define GCC_BIMC_BCR 50 +#define GCC_SNOC_BUS_TIMEOUT0_BCR 51 +#define GCC_SNOC_BUS_TIMEOUT1_BCR 52 +#define GCC_SNOC_BUS_TIMEOUT3_BCR 53 +#define GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR 54 +#define GCC_PNOC_BUS_TIMEOUT0_BCR 55 +#define GCC_CNOC_PERIPH_BUS_TIMEOUT1_BCR 56 +#define GCC_CNOC_PERIPH_BUS_TIMEOUT2_BCR 57 +#define GCC_CNOC_BUS_TIMEOUT0_BCR 58 +#define GCC_CNOC_BUS_TIMEOUT1_BCR 59 +#define GCC_CNOC_BUS_TIMEOUT2_BCR 60 +#define GCC_CNOC_BUS_TIMEOUT3_BCR 61 +#define GCC_CNOC_BUS_TIMEOUT4_BCR 62 +#define GCC_CNOC_BUS_TIMEOUT5_BCR 63 +#define GCC_CNOC_BUS_TIMEOUT6_BCR 64 +#define GCC_CNOC_BUS_TIMEOUT7_BCR 65 +#define GCC_APB2JTAG_BCR 66 +#define GCC_RBCPR_CX_BCR 67 +#define GCC_RBCPR_MX_BCR 68 +#define GCC_USB3_PHY_BCR 69 +#define GCC_USB3PHY_PHY_BCR 70 +#define GCC_USB3_DP_PHY_BCR 71 +#define GCC_SSC_BCR 72 +#define GCC_SSC_RESET 73 +#define GCC_USB_PHY_CFG_AHB2PHY_BCR 74 +#define GCC_PCIE_0_LINK_DOWN_BCR 75 +#define GCC_PCIE_0_PHY_BCR 76 +#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 77 +#define GCC_PCIE_PHY_BCR 78 +#define GCC_PCIE_PHY_NOCSR_COM_PHY_BCR 79 +#define GCC_PCIE_PHY_CFG_AHB_BCR 80 +#define GCC_PCIE_PHY_COM_BCR 81 +#define GCC_GPU_BCR 82 +#define GCC_SPSS_BCR 83 +#define GCC_OBT_ODT_BCR 84 +#define GCC_VS_BCR 85 +#define GCC_MSS_VS_RESET 86 +#define GCC_GPU_VS_RESET 87 +#define GCC_APC0_VS_RESET 88 +#define GCC_APC1_VS_RESET 89 +#define GCC_CNOC_BUS_TIMEOUT8_BCR 90 +#define GCC_CNOC_BUS_TIMEOUT9_BCR 91 +#define GCC_CNOC_BUS_TIMEOUT10_BCR 92 +#define GCC_CNOC_BUS_TIMEOUT11_BCR 93 +#define GCC_CNOC_BUS_TIMEOUT12_BCR 94 +#define GCC_CNOC_BUS_TIMEOUT13_BCR 95 +#define GCC_CNOC_BUS_TIMEOUT14_BCR 96 +#define GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR 97 +#define GCC_AGGRE1_NOC_BCR 98 +#define GCC_AGGRE2_NOC_BCR 99 +#define GCC_DCC_BCR 100 +#define GCC_QREFS_VBG_CAL_BCR 101 +#define GCC_IPA_BCR 102 +#define GCC_GLM_BCR 103 +#define GCC_SKL_BCR 104 +#define GCC_MSMPU_BCR 105 +#define GCC_QUSB2PHY_PRIM_BCR 106 +#define GCC_QUSB2PHY_SEC_BCR 107 + +#endif diff --git a/include/dt-bindings/clock/qcom,gcc-qcs404.h b/include/dt-bindings/clock/qcom,gcc-qcs404.h new file mode 100644 index 000000000000..6ceb55ed72c6 --- /dev/null +++ b/include/dt-bindings/clock/qcom,gcc-qcs404.h @@ -0,0 +1,165 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_QCS404_H +#define _DT_BINDINGS_CLK_QCOM_GCC_QCS404_H + +#define GCC_APSS_AHB_CLK_SRC 0 +#define GCC_BLSP1_QUP0_I2C_APPS_CLK_SRC 1 +#define GCC_BLSP1_QUP0_SPI_APPS_CLK_SRC 2 +#define GCC_BLSP1_QUP1_I2C_APPS_CLK_SRC 3 +#define GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC 4 +#define GCC_BLSP1_QUP2_I2C_APPS_CLK_SRC 5 +#define GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC 6 +#define GCC_BLSP1_QUP3_I2C_APPS_CLK_SRC 7 +#define GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC 8 +#define GCC_BLSP1_QUP4_I2C_APPS_CLK_SRC 9 +#define GCC_BLSP1_QUP4_SPI_APPS_CLK_SRC 10 +#define GCC_BLSP1_UART0_APPS_CLK_SRC 11 +#define GCC_BLSP1_UART1_APPS_CLK_SRC 12 +#define GCC_BLSP1_UART2_APPS_CLK_SRC 13 +#define GCC_BLSP1_UART3_APPS_CLK_SRC 14 +#define GCC_BLSP2_QUP0_I2C_APPS_CLK_SRC 15 +#define GCC_BLSP2_QUP0_SPI_APPS_CLK_SRC 16 +#define GCC_BLSP2_UART0_APPS_CLK_SRC 17 +#define GCC_BYTE0_CLK_SRC 18 +#define GCC_EMAC_CLK_SRC 19 +#define GCC_EMAC_PTP_CLK_SRC 20 +#define GCC_ESC0_CLK_SRC 21 +#define GCC_APSS_AHB_CLK 22 +#define GCC_APSS_AXI_CLK 23 +#define GCC_BIMC_APSS_AXI_CLK 24 +#define GCC_BIMC_GFX_CLK 25 +#define GCC_BIMC_MDSS_CLK 26 +#define GCC_BLSP1_AHB_CLK 27 +#define GCC_BLSP1_QUP0_I2C_APPS_CLK 28 +#define GCC_BLSP1_QUP0_SPI_APPS_CLK 29 +#define GCC_BLSP1_QUP1_I2C_APPS_CLK 30 +#define GCC_BLSP1_QUP1_SPI_APPS_CLK 31 +#define GCC_BLSP1_QUP2_I2C_APPS_CLK 32 +#define GCC_BLSP1_QUP2_SPI_APPS_CLK 33 +#define GCC_BLSP1_QUP3_I2C_APPS_CLK 34 +#define GCC_BLSP1_QUP3_SPI_APPS_CLK 35 +#define GCC_BLSP1_QUP4_I2C_APPS_CLK 36 +#define GCC_BLSP1_QUP4_SPI_APPS_CLK 37 +#define GCC_BLSP1_UART0_APPS_CLK 38 +#define GCC_BLSP1_UART1_APPS_CLK 39 +#define GCC_BLSP1_UART2_APPS_CLK 40 +#define GCC_BLSP1_UART3_APPS_CLK 41 +#define GCC_BLSP2_AHB_CLK 42 +#define GCC_BLSP2_QUP0_I2C_APPS_CLK 43 +#define GCC_BLSP2_QUP0_SPI_APPS_CLK 44 +#define GCC_BLSP2_UART0_APPS_CLK 45 +#define GCC_BOOT_ROM_AHB_CLK 46 +#define GCC_DCC_CLK 47 +#define GCC_GENI_IR_H_CLK 48 +#define GCC_ETH_AXI_CLK 49 +#define GCC_ETH_PTP_CLK 50 +#define GCC_ETH_RGMII_CLK 51 +#define GCC_ETH_SLAVE_AHB_CLK 52 +#define GCC_GENI_IR_S_CLK 53 +#define GCC_GP1_CLK 54 +#define GCC_GP2_CLK 55 +#define GCC_GP3_CLK 56 +#define GCC_MDSS_AHB_CLK 57 +#define GCC_MDSS_AXI_CLK 58 +#define GCC_MDSS_BYTE0_CLK 59 +#define GCC_MDSS_ESC0_CLK 60 +#define GCC_MDSS_HDMI_APP_CLK 61 +#define GCC_MDSS_HDMI_PCLK_CLK 62 +#define GCC_MDSS_MDP_CLK 63 +#define GCC_MDSS_PCLK0_CLK 64 +#define GCC_MDSS_VSYNC_CLK 65 +#define GCC_OXILI_AHB_CLK 66 +#define GCC_OXILI_GFX3D_CLK 67 +#define GCC_PCIE_0_AUX_CLK 68 +#define GCC_PCIE_0_CFG_AHB_CLK 69 +#define GCC_PCIE_0_MSTR_AXI_CLK 70 +#define GCC_PCIE_0_PIPE_CLK 71 +#define GCC_PCIE_0_SLV_AXI_CLK 72 +#define GCC_PCNOC_USB2_CLK 73 +#define GCC_PCNOC_USB3_CLK 74 +#define GCC_PDM2_CLK 75 +#define GCC_PDM_AHB_CLK 76 +#define GCC_VSYNC_CLK_SRC 77 +#define GCC_PRNG_AHB_CLK 78 +#define GCC_PWM0_XO512_CLK 79 +#define GCC_PWM1_XO512_CLK 80 +#define GCC_PWM2_XO512_CLK 81 +#define GCC_SDCC1_AHB_CLK 82 +#define GCC_SDCC1_APPS_CLK 83 +#define GCC_SDCC1_ICE_CORE_CLK 84 +#define GCC_SDCC2_AHB_CLK 85 +#define GCC_SDCC2_APPS_CLK 86 +#define GCC_SYS_NOC_USB3_CLK 87 +#define GCC_USB20_MOCK_UTMI_CLK 88 +#define GCC_USB2A_PHY_SLEEP_CLK 89 +#define GCC_USB30_MASTER_CLK 90 +#define GCC_USB30_MOCK_UTMI_CLK 91 +#define GCC_USB30_SLEEP_CLK 92 +#define GCC_USB3_PHY_AUX_CLK 93 +#define GCC_USB3_PHY_PIPE_CLK 94 +#define GCC_USB_HS_PHY_CFG_AHB_CLK 95 +#define GCC_USB_HS_SYSTEM_CLK 96 +#define GCC_GFX3D_CLK_SRC 97 +#define GCC_GP1_CLK_SRC 98 +#define GCC_GP2_CLK_SRC 99 +#define GCC_GP3_CLK_SRC 100 +#define GCC_GPLL0_OUT_MAIN 101 +#define GCC_GPLL1_OUT_MAIN 102 +#define GCC_GPLL3_OUT_MAIN 103 +#define GCC_GPLL4_OUT_MAIN 104 +#define GCC_HDMI_APP_CLK_SRC 105 +#define GCC_HDMI_PCLK_CLK_SRC 106 +#define GCC_MDP_CLK_SRC 107 +#define GCC_PCIE_0_AUX_CLK_SRC 108 +#define GCC_PCIE_0_PIPE_CLK_SRC 109 +#define GCC_PCLK0_CLK_SRC 110 +#define GCC_PDM2_CLK_SRC 111 +#define GCC_SDCC1_APPS_CLK_SRC 112 +#define GCC_SDCC1_ICE_CORE_CLK_SRC 113 +#define GCC_SDCC2_APPS_CLK_SRC 114 +#define GCC_USB20_MOCK_UTMI_CLK_SRC 115 +#define GCC_USB30_MASTER_CLK_SRC 116 +#define GCC_USB30_MOCK_UTMI_CLK_SRC 117 +#define GCC_USB3_PHY_AUX_CLK_SRC 118 +#define GCC_USB_HS_SYSTEM_CLK_SRC 119 +#define GCC_GPLL0_AO_CLK_SRC 120 +#define GCC_USB_HS_INACTIVITY_TIMERS_CLK 122 +#define GCC_GPLL0_AO_OUT_MAIN 123 +#define GCC_GPLL0_SLEEP_CLK_SRC 124 +#define GCC_GPLL6 125 +#define GCC_GPLL6_OUT_AUX 126 +#define GCC_MDSS_MDP_VOTE_CLK 127 +#define GCC_MDSS_ROTATOR_VOTE_CLK 128 +#define GCC_BIMC_GPU_CLK 129 +#define GCC_GTCU_AHB_CLK 130 +#define GCC_GFX_TCU_CLK 131 +#define GCC_GFX_TBU_CLK 132 +#define GCC_SMMU_CFG_CLK 133 +#define GCC_APSS_TCU_CLK 134 +#define GCC_CRYPTO_AHB_CLK 135 +#define GCC_CRYPTO_AXI_CLK 136 +#define GCC_CRYPTO_CLK 137 +#define GCC_MDP_TBU_CLK 138 +#define GCC_QDSS_DAP_CLK 139 +#define GCC_DCC_XO_CLK 140 + +#define GCC_GENI_IR_BCR 0 +#define GCC_USB_HS_BCR 1 +#define GCC_USB2_HS_PHY_ONLY_BCR 2 +#define GCC_QUSB2_PHY_BCR 3 +#define GCC_USB_HS_PHY_CFG_AHB_BCR 4 +#define GCC_USB2A_PHY_BCR 5 +#define GCC_USB3_PHY_BCR 6 +#define GCC_USB_30_BCR 7 +#define GCC_USB3PHY_PHY_BCR 8 +#define GCC_PCIE_0_BCR 9 +#define GCC_PCIE_0_PHY_BCR 10 +#define GCC_PCIE_0_LINK_DOWN_BCR 11 +#define GCC_PCIEPHY_0_PHY_BCR 12 +#define GCC_EMAC_BCR 13 + +#endif diff --git a/include/dt-bindings/clock/qcom,gcc-sdm660.h b/include/dt-bindings/clock/qcom,gcc-sdm660.h new file mode 100644 index 000000000000..468302282913 --- /dev/null +++ b/include/dt-bindings/clock/qcom,gcc-sdm660.h @@ -0,0 +1,156 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * Copyright (c) 2018, Craig Tatlor. + */ + +#ifndef _DT_BINDINGS_CLK_MSM_GCC_660_H +#define _DT_BINDINGS_CLK_MSM_GCC_660_H + +#define BLSP1_QUP1_I2C_APPS_CLK_SRC 0 +#define BLSP1_QUP1_SPI_APPS_CLK_SRC 1 +#define BLSP1_QUP2_I2C_APPS_CLK_SRC 2 +#define BLSP1_QUP2_SPI_APPS_CLK_SRC 3 +#define BLSP1_QUP3_I2C_APPS_CLK_SRC 4 +#define BLSP1_QUP3_SPI_APPS_CLK_SRC 5 +#define BLSP1_QUP4_I2C_APPS_CLK_SRC 6 +#define BLSP1_QUP4_SPI_APPS_CLK_SRC 7 +#define BLSP1_UART1_APPS_CLK_SRC 8 +#define BLSP1_UART2_APPS_CLK_SRC 9 +#define BLSP2_QUP1_I2C_APPS_CLK_SRC 10 +#define BLSP2_QUP1_SPI_APPS_CLK_SRC 11 +#define BLSP2_QUP2_I2C_APPS_CLK_SRC 12 +#define BLSP2_QUP2_SPI_APPS_CLK_SRC 13 +#define BLSP2_QUP3_I2C_APPS_CLK_SRC 14 +#define BLSP2_QUP3_SPI_APPS_CLK_SRC 15 +#define BLSP2_QUP4_I2C_APPS_CLK_SRC 16 +#define BLSP2_QUP4_SPI_APPS_CLK_SRC 17 +#define BLSP2_UART1_APPS_CLK_SRC 18 +#define BLSP2_UART2_APPS_CLK_SRC 19 +#define GCC_AGGRE2_UFS_AXI_CLK 20 +#define GCC_AGGRE2_USB3_AXI_CLK 21 +#define GCC_BIMC_GFX_CLK 22 +#define GCC_BIMC_HMSS_AXI_CLK 23 +#define GCC_BIMC_MSS_Q6_AXI_CLK 24 +#define GCC_BLSP1_AHB_CLK 25 +#define GCC_BLSP1_QUP1_I2C_APPS_CLK 26 +#define GCC_BLSP1_QUP1_SPI_APPS_CLK 27 +#define GCC_BLSP1_QUP2_I2C_APPS_CLK 28 +#define GCC_BLSP1_QUP2_SPI_APPS_CLK 29 +#define GCC_BLSP1_QUP3_I2C_APPS_CLK 30 +#define GCC_BLSP1_QUP3_SPI_APPS_CLK 31 +#define GCC_BLSP1_QUP4_I2C_APPS_CLK 32 +#define GCC_BLSP1_QUP4_SPI_APPS_CLK 33 +#define GCC_BLSP1_UART1_APPS_CLK 34 +#define GCC_BLSP1_UART2_APPS_CLK 35 +#define GCC_BLSP2_AHB_CLK 36 +#define GCC_BLSP2_QUP1_I2C_APPS_CLK 37 +#define GCC_BLSP2_QUP1_SPI_APPS_CLK 38 +#define GCC_BLSP2_QUP2_I2C_APPS_CLK 39 +#define GCC_BLSP2_QUP2_SPI_APPS_CLK 40 +#define GCC_BLSP2_QUP3_I2C_APPS_CLK 41 +#define GCC_BLSP2_QUP3_SPI_APPS_CLK 42 +#define GCC_BLSP2_QUP4_I2C_APPS_CLK 43 +#define GCC_BLSP2_QUP4_SPI_APPS_CLK 44 +#define GCC_BLSP2_UART1_APPS_CLK 45 +#define GCC_BLSP2_UART2_APPS_CLK 46 +#define GCC_BOOT_ROM_AHB_CLK 47 +#define GCC_CFG_NOC_USB2_AXI_CLK 48 +#define GCC_CFG_NOC_USB3_AXI_CLK 49 +#define GCC_DCC_AHB_CLK 50 +#define GCC_GP1_CLK 51 +#define GCC_GP2_CLK 52 +#define GCC_GP3_CLK 53 +#define GCC_GPU_BIMC_GFX_CLK 54 +#define GCC_GPU_CFG_AHB_CLK 55 +#define GCC_GPU_GPLL0_CLK 56 +#define GCC_GPU_GPLL0_DIV_CLK 57 +#define GCC_HMSS_DVM_BUS_CLK 58 +#define GCC_HMSS_RBCPR_CLK 59 +#define GCC_MMSS_GPLL0_CLK 60 +#define GCC_MMSS_GPLL0_DIV_CLK 61 +#define GCC_MMSS_NOC_CFG_AHB_CLK 62 +#define GCC_MMSS_SYS_NOC_AXI_CLK 63 +#define GCC_MSS_CFG_AHB_CLK 64 +#define GCC_MSS_GPLL0_DIV_CLK 65 +#define GCC_MSS_MNOC_BIMC_AXI_CLK 66 +#define GCC_MSS_Q6_BIMC_AXI_CLK 67 +#define GCC_MSS_SNOC_AXI_CLK 68 +#define GCC_PDM2_CLK 69 +#define GCC_PDM_AHB_CLK 70 +#define GCC_PRNG_AHB_CLK 71 +#define GCC_QSPI_AHB_CLK 72 +#define GCC_QSPI_SER_CLK 73 +#define GCC_SDCC1_AHB_CLK 74 +#define GCC_SDCC1_APPS_CLK 75 +#define GCC_SDCC1_ICE_CORE_CLK 76 +#define GCC_SDCC2_AHB_CLK 77 +#define GCC_SDCC2_APPS_CLK 78 +#define GCC_UFS_AHB_CLK 79 +#define GCC_UFS_AXI_CLK 80 +#define GCC_UFS_CLKREF_CLK 81 +#define GCC_UFS_ICE_CORE_CLK 82 +#define GCC_UFS_PHY_AUX_CLK 83 +#define GCC_UFS_RX_SYMBOL_0_CLK 84 +#define GCC_UFS_RX_SYMBOL_1_CLK 85 +#define GCC_UFS_TX_SYMBOL_0_CLK 86 +#define GCC_UFS_UNIPRO_CORE_CLK 87 +#define GCC_USB20_MASTER_CLK 88 +#define GCC_USB20_MOCK_UTMI_CLK 89 +#define GCC_USB20_SLEEP_CLK 90 +#define GCC_USB30_MASTER_CLK 91 +#define GCC_USB30_MOCK_UTMI_CLK 92 +#define GCC_USB30_SLEEP_CLK 93 +#define GCC_USB3_CLKREF_CLK 94 +#define GCC_USB3_PHY_AUX_CLK 95 +#define GCC_USB3_PHY_PIPE_CLK 96 +#define GCC_USB_PHY_CFG_AHB2PHY_CLK 97 +#define GP1_CLK_SRC 98 +#define GP2_CLK_SRC 99 +#define GP3_CLK_SRC 100 +#define GPLL0 101 +#define GPLL0_EARLY 102 +#define GPLL1 103 +#define GPLL1_EARLY 104 +#define GPLL4 105 +#define GPLL4_EARLY 106 +#define HMSS_GPLL0_CLK_SRC 107 +#define HMSS_GPLL4_CLK_SRC 108 +#define HMSS_RBCPR_CLK_SRC 109 +#define PDM2_CLK_SRC 110 +#define QSPI_SER_CLK_SRC 111 +#define SDCC1_APPS_CLK_SRC 112 +#define SDCC1_ICE_CORE_CLK_SRC 113 +#define SDCC2_APPS_CLK_SRC 114 +#define UFS_AXI_CLK_SRC 115 +#define UFS_ICE_CORE_CLK_SRC 116 +#define UFS_PHY_AUX_CLK_SRC 117 +#define UFS_UNIPRO_CORE_CLK_SRC 118 +#define USB20_MASTER_CLK_SRC 119 +#define USB20_MOCK_UTMI_CLK_SRC 120 +#define USB30_MASTER_CLK_SRC 121 +#define USB30_MOCK_UTMI_CLK_SRC 122 +#define USB3_PHY_AUX_CLK_SRC 123 +#define GPLL0_OUT_MSSCC 124 +#define GCC_UFS_AXI_HW_CTL_CLK 125 +#define GCC_UFS_ICE_CORE_HW_CTL_CLK 126 +#define GCC_UFS_PHY_AUX_HW_CTL_CLK 127 +#define GCC_UFS_UNIPRO_CORE_HW_CTL_CLK 128 +#define GCC_RX0_USB2_CLKREF_CLK 129 +#define GCC_RX1_USB2_CLKREF_CLK 130 + +#define PCIE_0_GDSC 0 +#define UFS_GDSC 1 +#define USB_30_GDSC 2 + +#define GCC_QUSB2PHY_PRIM_BCR 0 +#define GCC_QUSB2PHY_SEC_BCR 1 +#define GCC_UFS_BCR 2 +#define GCC_USB3_DP_PHY_BCR 3 +#define GCC_USB3_PHY_BCR 4 +#define GCC_USB3PHY_PHY_BCR 5 +#define GCC_USB_20_BCR 6 +#define GCC_USB_30_BCR 7 +#define GCC_USB_PHY_CFG_AHB2PHY_BCR 8 + +#endif diff --git a/include/dt-bindings/clock/qcom,gcc-sdm845.h b/include/dt-bindings/clock/qcom,gcc-sdm845.h new file mode 100644 index 000000000000..968fa65b9c42 --- /dev/null +++ b/include/dt-bindings/clock/qcom,gcc-sdm845.h @@ -0,0 +1,246 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_SDM_GCC_SDM845_H +#define _DT_BINDINGS_CLK_SDM_GCC_SDM845_H + +/* GCC clock registers */ +#define GCC_AGGRE_NOC_PCIE_TBU_CLK 0 +#define GCC_AGGRE_UFS_CARD_AXI_CLK 1 +#define GCC_AGGRE_UFS_PHY_AXI_CLK 2 +#define GCC_AGGRE_USB3_PRIM_AXI_CLK 3 +#define GCC_AGGRE_USB3_SEC_AXI_CLK 4 +#define GCC_BOOT_ROM_AHB_CLK 5 +#define GCC_CAMERA_AHB_CLK 6 +#define GCC_CAMERA_AXI_CLK 7 +#define GCC_CAMERA_XO_CLK 8 +#define GCC_CE1_AHB_CLK 9 +#define GCC_CE1_AXI_CLK 10 +#define GCC_CE1_CLK 11 +#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 12 +#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 13 +#define GCC_CPUSS_AHB_CLK 14 +#define GCC_CPUSS_AHB_CLK_SRC 15 +#define GCC_CPUSS_RBCPR_CLK 16 +#define GCC_CPUSS_RBCPR_CLK_SRC 17 +#define GCC_DDRSS_GPU_AXI_CLK 18 +#define GCC_DISP_AHB_CLK 19 +#define GCC_DISP_AXI_CLK 20 +#define GCC_DISP_GPLL0_CLK_SRC 21 +#define GCC_DISP_GPLL0_DIV_CLK_SRC 22 +#define GCC_DISP_XO_CLK 23 +#define GCC_GP1_CLK 24 +#define GCC_GP1_CLK_SRC 25 +#define GCC_GP2_CLK 26 +#define GCC_GP2_CLK_SRC 27 +#define GCC_GP3_CLK 28 +#define GCC_GP3_CLK_SRC 29 +#define GCC_GPU_CFG_AHB_CLK 30 +#define GCC_GPU_GPLL0_CLK_SRC 31 +#define GCC_GPU_GPLL0_DIV_CLK_SRC 32 +#define GCC_GPU_MEMNOC_GFX_CLK 33 +#define GCC_GPU_SNOC_DVM_GFX_CLK 34 +#define GCC_MSS_AXIS2_CLK 35 +#define GCC_MSS_CFG_AHB_CLK 36 +#define GCC_MSS_GPLL0_DIV_CLK_SRC 37 +#define GCC_MSS_MFAB_AXIS_CLK 38 +#define GCC_MSS_Q6_MEMNOC_AXI_CLK 39 +#define GCC_MSS_SNOC_AXI_CLK 40 +#define GCC_PCIE_0_AUX_CLK 41 +#define GCC_PCIE_0_AUX_CLK_SRC 42 +#define GCC_PCIE_0_CFG_AHB_CLK 43 +#define GCC_PCIE_0_CLKREF_CLK 44 +#define GCC_PCIE_0_MSTR_AXI_CLK 45 +#define GCC_PCIE_0_PIPE_CLK 46 +#define GCC_PCIE_0_SLV_AXI_CLK 47 +#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 48 +#define GCC_PCIE_1_AUX_CLK 49 +#define GCC_PCIE_1_AUX_CLK_SRC 50 +#define GCC_PCIE_1_CFG_AHB_CLK 51 +#define GCC_PCIE_1_CLKREF_CLK 52 +#define GCC_PCIE_1_MSTR_AXI_CLK 53 +#define GCC_PCIE_1_PIPE_CLK 54 +#define GCC_PCIE_1_SLV_AXI_CLK 55 +#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 56 +#define GCC_PCIE_PHY_AUX_CLK 57 +#define GCC_PCIE_PHY_REFGEN_CLK 58 +#define GCC_PCIE_PHY_REFGEN_CLK_SRC 59 +#define GCC_PDM2_CLK 60 +#define GCC_PDM2_CLK_SRC 61 +#define GCC_PDM_AHB_CLK 62 +#define GCC_PDM_XO4_CLK 63 +#define GCC_PRNG_AHB_CLK 64 +#define GCC_QMIP_CAMERA_AHB_CLK 65 +#define GCC_QMIP_DISP_AHB_CLK 66 +#define GCC_QMIP_VIDEO_AHB_CLK 67 +#define GCC_QUPV3_WRAP0_S0_CLK 68 +#define GCC_QUPV3_WRAP0_S0_CLK_SRC 69 +#define GCC_QUPV3_WRAP0_S1_CLK 70 +#define GCC_QUPV3_WRAP0_S1_CLK_SRC 71 +#define GCC_QUPV3_WRAP0_S2_CLK 72 +#define GCC_QUPV3_WRAP0_S2_CLK_SRC 73 +#define GCC_QUPV3_WRAP0_S3_CLK 74 +#define GCC_QUPV3_WRAP0_S3_CLK_SRC 75 +#define GCC_QUPV3_WRAP0_S4_CLK 76 +#define GCC_QUPV3_WRAP0_S4_CLK_SRC 77 +#define GCC_QUPV3_WRAP0_S5_CLK 78 +#define GCC_QUPV3_WRAP0_S5_CLK_SRC 79 +#define GCC_QUPV3_WRAP0_S6_CLK 80 +#define GCC_QUPV3_WRAP0_S6_CLK_SRC 81 +#define GCC_QUPV3_WRAP0_S7_CLK 82 +#define GCC_QUPV3_WRAP0_S7_CLK_SRC 83 +#define GCC_QUPV3_WRAP1_S0_CLK 84 +#define GCC_QUPV3_WRAP1_S0_CLK_SRC 85 +#define GCC_QUPV3_WRAP1_S1_CLK 86 +#define GCC_QUPV3_WRAP1_S1_CLK_SRC 87 +#define GCC_QUPV3_WRAP1_S2_CLK 88 +#define GCC_QUPV3_WRAP1_S2_CLK_SRC 89 +#define GCC_QUPV3_WRAP1_S3_CLK 90 +#define GCC_QUPV3_WRAP1_S3_CLK_SRC 91 +#define GCC_QUPV3_WRAP1_S4_CLK 92 +#define GCC_QUPV3_WRAP1_S4_CLK_SRC 93 +#define GCC_QUPV3_WRAP1_S5_CLK 94 +#define GCC_QUPV3_WRAP1_S5_CLK_SRC 95 +#define GCC_QUPV3_WRAP1_S6_CLK 96 +#define GCC_QUPV3_WRAP1_S6_CLK_SRC 97 +#define GCC_QUPV3_WRAP1_S7_CLK 98 +#define GCC_QUPV3_WRAP1_S7_CLK_SRC 99 +#define GCC_QUPV3_WRAP_0_M_AHB_CLK 100 +#define GCC_QUPV3_WRAP_0_S_AHB_CLK 101 +#define GCC_QUPV3_WRAP_1_M_AHB_CLK 102 +#define GCC_QUPV3_WRAP_1_S_AHB_CLK 103 +#define GCC_SDCC2_AHB_CLK 104 +#define GCC_SDCC2_APPS_CLK 105 +#define GCC_SDCC2_APPS_CLK_SRC 106 +#define GCC_SDCC4_AHB_CLK 107 +#define GCC_SDCC4_APPS_CLK 108 +#define GCC_SDCC4_APPS_CLK_SRC 109 +#define GCC_SYS_NOC_CPUSS_AHB_CLK 110 +#define GCC_TSIF_AHB_CLK 111 +#define GCC_TSIF_INACTIVITY_TIMERS_CLK 112 +#define GCC_TSIF_REF_CLK 113 +#define GCC_TSIF_REF_CLK_SRC 114 +#define GCC_UFS_CARD_AHB_CLK 115 +#define GCC_UFS_CARD_AXI_CLK 116 +#define GCC_UFS_CARD_AXI_CLK_SRC 117 +#define GCC_UFS_CARD_CLKREF_CLK 118 +#define GCC_UFS_CARD_ICE_CORE_CLK 119 +#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 120 +#define GCC_UFS_CARD_PHY_AUX_CLK 121 +#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 122 +#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 123 +#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 124 +#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 125 +#define GCC_UFS_CARD_UNIPRO_CORE_CLK 126 +#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 127 +#define GCC_UFS_MEM_CLKREF_CLK 128 +#define GCC_UFS_PHY_AHB_CLK 129 +#define GCC_UFS_PHY_AXI_CLK 130 +#define GCC_UFS_PHY_AXI_CLK_SRC 131 +#define GCC_UFS_PHY_ICE_CORE_CLK 132 +#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 133 +#define GCC_UFS_PHY_PHY_AUX_CLK 134 +#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 135 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 136 +#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 137 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 138 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK 139 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 140 +#define GCC_USB30_PRIM_MASTER_CLK 141 +#define GCC_USB30_PRIM_MASTER_CLK_SRC 142 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK 143 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 144 +#define GCC_USB30_PRIM_SLEEP_CLK 145 +#define GCC_USB30_SEC_MASTER_CLK 146 +#define GCC_USB30_SEC_MASTER_CLK_SRC 147 +#define GCC_USB30_SEC_MOCK_UTMI_CLK 148 +#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 149 +#define GCC_USB30_SEC_SLEEP_CLK 150 +#define GCC_USB3_PRIM_CLKREF_CLK 151 +#define GCC_USB3_PRIM_PHY_AUX_CLK 152 +#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 153 +#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 154 +#define GCC_USB3_PRIM_PHY_PIPE_CLK 155 +#define GCC_USB3_SEC_CLKREF_CLK 156 +#define GCC_USB3_SEC_PHY_AUX_CLK 157 +#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 158 +#define GCC_USB3_SEC_PHY_PIPE_CLK 159 +#define GCC_USB3_SEC_PHY_COM_AUX_CLK 160 +#define GCC_USB_PHY_CFG_AHB2PHY_CLK 161 +#define GCC_VIDEO_AHB_CLK 162 +#define GCC_VIDEO_AXI_CLK 163 +#define GCC_VIDEO_XO_CLK 164 +#define GPLL0 165 +#define GPLL0_OUT_EVEN 166 +#define GPLL0_OUT_MAIN 167 +#define GCC_GPU_IREF_CLK 168 +#define GCC_SDCC1_AHB_CLK 169 +#define GCC_SDCC1_APPS_CLK 170 +#define GCC_SDCC1_ICE_CORE_CLK 171 +#define GCC_SDCC1_APPS_CLK_SRC 172 +#define GCC_SDCC1_ICE_CORE_CLK_SRC 173 +#define GCC_APC_VS_CLK 174 +#define GCC_GPU_VS_CLK 175 +#define GCC_MSS_VS_CLK 176 +#define GCC_VDDA_VS_CLK 177 +#define GCC_VDDCX_VS_CLK 178 +#define GCC_VDDMX_VS_CLK 179 +#define GCC_VS_CTRL_AHB_CLK 180 +#define GCC_VS_CTRL_CLK 181 +#define GCC_VS_CTRL_CLK_SRC 182 +#define GCC_VSENSOR_CLK_SRC 183 +#define GPLL4 184 +#define GCC_CPUSS_DVM_BUS_CLK 185 +#define GCC_CPUSS_GNOC_CLK 186 +#define GCC_QSPI_CORE_CLK_SRC 187 +#define GCC_QSPI_CORE_CLK 188 +#define GCC_QSPI_CNOC_PERIPH_AHB_CLK 189 +#define GCC_LPASS_Q6_AXI_CLK 190 +#define GCC_LPASS_SWAY_CLK 191 + +/* GCC Resets */ +#define GCC_MMSS_BCR 0 +#define GCC_PCIE_0_BCR 1 +#define GCC_PCIE_1_BCR 2 +#define GCC_PCIE_PHY_BCR 3 +#define GCC_PDM_BCR 4 +#define GCC_PRNG_BCR 5 +#define GCC_QUPV3_WRAPPER_0_BCR 6 +#define GCC_QUPV3_WRAPPER_1_BCR 7 +#define GCC_QUSB2PHY_PRIM_BCR 8 +#define GCC_QUSB2PHY_SEC_BCR 9 +#define GCC_SDCC2_BCR 10 +#define GCC_SDCC4_BCR 11 +#define GCC_TSIF_BCR 12 +#define GCC_UFS_CARD_BCR 13 +#define GCC_UFS_PHY_BCR 14 +#define GCC_USB30_PRIM_BCR 15 +#define GCC_USB30_SEC_BCR 16 +#define GCC_USB3_PHY_PRIM_BCR 17 +#define GCC_USB3PHY_PHY_PRIM_BCR 18 +#define GCC_USB3_DP_PHY_PRIM_BCR 19 +#define GCC_USB3_PHY_SEC_BCR 20 +#define GCC_USB3PHY_PHY_SEC_BCR 21 +#define GCC_USB3_DP_PHY_SEC_BCR 22 +#define GCC_USB_PHY_CFG_AHB2PHY_BCR 23 +#define GCC_PCIE_0_PHY_BCR 24 +#define GCC_PCIE_1_PHY_BCR 25 + +/* GCC GDSCRs */ +#define PCIE_0_GDSC 0 +#define PCIE_1_GDSC 1 +#define UFS_CARD_GDSC 2 +#define UFS_PHY_GDSC 3 +#define USB30_PRIM_GDSC 4 +#define USB30_SEC_GDSC 5 +#define HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC 6 +#define HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC 7 +#define HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC 8 +#define HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC 9 +#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 10 +#define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC 11 +#define HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC 12 + +#endif diff --git a/include/dt-bindings/clock/qcom,gpucc-sdm845.h b/include/dt-bindings/clock/qcom,gpucc-sdm845.h new file mode 100644 index 000000000000..9690d901b50a --- /dev/null +++ b/include/dt-bindings/clock/qcom,gpucc-sdm845.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_SDM_GPU_CC_SDM845_H +#define _DT_BINDINGS_CLK_SDM_GPU_CC_SDM845_H + +/* GPU_CC clock registers */ +#define GPU_CC_CX_GMU_CLK 0 +#define GPU_CC_CXO_CLK 1 +#define GPU_CC_GMU_CLK_SRC 2 +#define GPU_CC_PLL1 3 + +/* GPU_CC Resets */ +#define GPUCC_GPU_CC_CX_BCR 0 +#define GPUCC_GPU_CC_GMU_BCR 1 +#define GPUCC_GPU_CC_XO_BCR 2 + +/* GPU_CC GDSCRs */ +#define GPU_CX_GDSC 0 +#define GPU_GX_GDSC 1 + +#endif diff --git a/include/dt-bindings/clock/qcom,lpass-sdm845.h b/include/dt-bindings/clock/qcom,lpass-sdm845.h new file mode 100644 index 000000000000..659050846f61 --- /dev/null +++ b/include/dt-bindings/clock/qcom,lpass-sdm845.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_SDM_LPASS_SDM845_H +#define _DT_BINDINGS_CLK_SDM_LPASS_SDM845_H + +#define LPASS_Q6SS_AHBM_AON_CLK 0 +#define LPASS_Q6SS_AHBS_AON_CLK 1 +#define LPASS_QDSP6SS_XO_CLK 2 +#define LPASS_QDSP6SS_SLEEP_CLK 3 +#define LPASS_QDSP6SS_CORE_CLK 4 + +#endif diff --git a/include/dt-bindings/clock/qcom,rpmcc.h b/include/dt-bindings/clock/qcom,rpmcc.h index c585b82b9c05..3658b0c14966 100644 --- a/include/dt-bindings/clock/qcom,rpmcc.h +++ b/include/dt-bindings/clock/qcom,rpmcc.h @@ -123,5 +123,9 @@ #define RPM_SMD_DIV_A_CLK3 73 #define RPM_SMD_LN_BB_CLK 74 #define RPM_SMD_LN_BB_A_CLK 75 +#define RPM_SMD_BIMC_GPU_CLK 76 +#define RPM_SMD_BIMC_GPU_A_CLK 77 +#define RPM_SMD_QPIC_CLK 78 +#define RPM_SMD_QPIC_CLK_A 79 #endif diff --git a/include/dt-bindings/clock/qcom,rpmh.h b/include/dt-bindings/clock/qcom,rpmh.h new file mode 100644 index 000000000000..f48fbd6f2095 --- /dev/null +++ b/include/dt-bindings/clock/qcom,rpmh.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. */ + + +#ifndef _DT_BINDINGS_CLK_MSM_RPMH_H +#define _DT_BINDINGS_CLK_MSM_RPMH_H + +/* RPMh controlled clocks */ +#define RPMH_CXO_CLK 0 +#define RPMH_CXO_CLK_A 1 +#define RPMH_LN_BB_CLK2 2 +#define RPMH_LN_BB_CLK2_A 3 +#define RPMH_LN_BB_CLK3 4 +#define RPMH_LN_BB_CLK3_A 5 +#define RPMH_RF_CLK1 6 +#define RPMH_RF_CLK1_A 7 +#define RPMH_RF_CLK2 8 +#define RPMH_RF_CLK2_A 9 +#define RPMH_RF_CLK3 10 +#define RPMH_RF_CLK3_A 11 + +#endif diff --git a/include/dt-bindings/clock/qcom,videocc-sdm845.h b/include/dt-bindings/clock/qcom,videocc-sdm845.h new file mode 100644 index 000000000000..1b868165e8ce --- /dev/null +++ b/include/dt-bindings/clock/qcom,videocc-sdm845.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_SDM_VIDEO_CC_SDM845_H +#define _DT_BINDINGS_CLK_SDM_VIDEO_CC_SDM845_H + +/* VIDEO_CC clock registers */ +#define VIDEO_CC_APB_CLK 0 +#define VIDEO_CC_AT_CLK 1 +#define VIDEO_CC_QDSS_TRIG_CLK 2 +#define VIDEO_CC_QDSS_TSCTR_DIV8_CLK 3 +#define VIDEO_CC_VCODEC0_AXI_CLK 4 +#define VIDEO_CC_VCODEC0_CORE_CLK 5 +#define VIDEO_CC_VCODEC1_AXI_CLK 6 +#define VIDEO_CC_VCODEC1_CORE_CLK 7 +#define VIDEO_CC_VENUS_AHB_CLK 8 +#define VIDEO_CC_VENUS_CLK_SRC 9 +#define VIDEO_CC_VENUS_CTL_AXI_CLK 10 +#define VIDEO_CC_VENUS_CTL_CORE_CLK 11 +#define VIDEO_PLL0 12 + +/* VIDEO_CC Resets */ +#define VIDEO_CC_VENUS_BCR 0 +#define VIDEO_CC_VCODEC0_BCR 1 +#define VIDEO_CC_VCODEC1_BCR 2 +#define VIDEO_CC_INTERFACE_BCR 3 + +/* VIDEO_CC GDSCRs */ +#define VENUS_GDSC 0 +#define VCODEC0_GDSC 1 +#define VCODEC1_GDSC 2 + +#endif diff --git a/include/dt-bindings/clock/r7s72100-clock.h b/include/dt-bindings/clock/r7s72100-clock.h index 0dcb3e87d44c..a267ac250143 100644 --- a/include/dt-bindings/clock/r7s72100-clock.h +++ b/include/dt-bindings/clock/r7s72100-clock.h @@ -1,10 +1,7 @@ -/* +/* SPDX-License-Identifier: GPL-2.0 + * * Copyright (C) 2014 Renesas Solutions Corp. * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. */ #ifndef __DT_BINDINGS_CLOCK_R7S72100_H__ diff --git a/include/dt-bindings/clock/r7s9210-cpg-mssr.h b/include/dt-bindings/clock/r7s9210-cpg-mssr.h new file mode 100644 index 000000000000..b6f85ca149aa --- /dev/null +++ b/include/dt-bindings/clock/r7s9210-cpg-mssr.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2018 Renesas Electronics Corp. + * + */ + +#ifndef __DT_BINDINGS_CLOCK_R7S9210_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_R7S9210_CPG_MSSR_H__ + +#include <dt-bindings/clock/renesas-cpg-mssr.h> + +/* R7S9210 CPG Core Clocks */ +#define R7S9210_CLK_I 0 +#define R7S9210_CLK_G 1 +#define R7S9210_CLK_B 2 +#define R7S9210_CLK_P1 3 +#define R7S9210_CLK_P1C 4 +#define R7S9210_CLK_P0 5 + +#endif /* __DT_BINDINGS_CLOCK_R7S9210_CPG_MSSR_H__ */ diff --git a/include/dt-bindings/clock/r8a7743-cpg-mssr.h b/include/dt-bindings/clock/r8a7743-cpg-mssr.h index e1d1f3c6a99e..3ba936029d9f 100644 --- a/include/dt-bindings/clock/r8a7743-cpg-mssr.h +++ b/include/dt-bindings/clock/r8a7743-cpg-mssr.h @@ -1,10 +1,6 @@ -/* - * Copyright (C) 2016 Cogent Embedded Inc. +/* SPDX-License-Identifier: GPL-2.0+ * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. + * Copyright (C) 2016 Cogent Embedded Inc. */ #ifndef __DT_BINDINGS_CLOCK_R8A7743_CPG_MSSR_H__ #define __DT_BINDINGS_CLOCK_R8A7743_CPG_MSSR_H__ diff --git a/include/dt-bindings/clock/r8a7744-cpg-mssr.h b/include/dt-bindings/clock/r8a7744-cpg-mssr.h new file mode 100644 index 000000000000..2690be0c3e22 --- /dev/null +++ b/include/dt-bindings/clock/r8a7744-cpg-mssr.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2018 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_R8A7744_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_R8A7744_CPG_MSSR_H__ + +#include <dt-bindings/clock/renesas-cpg-mssr.h> + +/* r8a7744 CPG Core Clocks */ +#define R8A7744_CLK_Z 0 +#define R8A7744_CLK_ZG 1 +#define R8A7744_CLK_ZTR 2 +#define R8A7744_CLK_ZTRD2 3 +#define R8A7744_CLK_ZT 4 +#define R8A7744_CLK_ZX 5 +#define R8A7744_CLK_ZS 6 +#define R8A7744_CLK_HP 7 +#define R8A7744_CLK_B 9 +#define R8A7744_CLK_LB 10 +#define R8A7744_CLK_P 11 +#define R8A7744_CLK_CL 12 +#define R8A7744_CLK_M2 13 +#define R8A7744_CLK_ZB3 15 +#define R8A7744_CLK_ZB3D2 16 +#define R8A7744_CLK_DDR 17 +#define R8A7744_CLK_SDH 18 +#define R8A7744_CLK_SD0 19 +#define R8A7744_CLK_SD2 20 +#define R8A7744_CLK_SD3 21 +#define R8A7744_CLK_MMC0 22 +#define R8A7744_CLK_MP 23 +#define R8A7744_CLK_QSPI 26 +#define R8A7744_CLK_CP 27 +#define R8A7744_CLK_RCAN 28 +#define R8A7744_CLK_R 29 +#define R8A7744_CLK_OSC 30 + +#endif /* __DT_BINDINGS_CLOCK_R8A7744_CPG_MSSR_H__ */ diff --git a/include/dt-bindings/clock/r8a7745-cpg-mssr.h b/include/dt-bindings/clock/r8a7745-cpg-mssr.h index 56ad6f0c6760..f81066c9d192 100644 --- a/include/dt-bindings/clock/r8a7745-cpg-mssr.h +++ b/include/dt-bindings/clock/r8a7745-cpg-mssr.h @@ -1,10 +1,6 @@ -/* - * Copyright (C) 2016 Cogent Embedded Inc. +/* SPDX-License-Identifier: GPL-2.0+ * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. + * Copyright (C) 2016 Cogent Embedded Inc. */ #ifndef __DT_BINDINGS_CLOCK_R8A7745_CPG_MSSR_H__ #define __DT_BINDINGS_CLOCK_R8A7745_CPG_MSSR_H__ diff --git a/include/dt-bindings/clock/r8a77470-cpg-mssr.h b/include/dt-bindings/clock/r8a77470-cpg-mssr.h new file mode 100644 index 000000000000..34cba49d0f84 --- /dev/null +++ b/include/dt-bindings/clock/r8a77470-cpg-mssr.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2018 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__ + +#include <dt-bindings/clock/renesas-cpg-mssr.h> + +/* r8a77470 CPG Core Clocks */ +#define R8A77470_CLK_Z2 0 +#define R8A77470_CLK_ZTR 1 +#define R8A77470_CLK_ZTRD2 2 +#define R8A77470_CLK_ZT 3 +#define R8A77470_CLK_ZX 4 +#define R8A77470_CLK_ZS 5 +#define R8A77470_CLK_HP 6 +#define R8A77470_CLK_B 7 +#define R8A77470_CLK_LB 8 +#define R8A77470_CLK_P 9 +#define R8A77470_CLK_CL 10 +#define R8A77470_CLK_CP 11 +#define R8A77470_CLK_M2 12 +#define R8A77470_CLK_ZB3 13 +#define R8A77470_CLK_SDH 14 +#define R8A77470_CLK_SD0 15 +#define R8A77470_CLK_SD1 16 +#define R8A77470_CLK_SD2 17 +#define R8A77470_CLK_MP 18 +#define R8A77470_CLK_QSPI 19 +#define R8A77470_CLK_CPEX 20 +#define R8A77470_CLK_RCAN 21 +#define R8A77470_CLK_R 22 +#define R8A77470_CLK_OSC 23 + +#endif /* __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__ */ diff --git a/include/dt-bindings/clock/r8a774a1-cpg-mssr.h b/include/dt-bindings/clock/r8a774a1-cpg-mssr.h new file mode 100644 index 000000000000..9bc5d45ff4b5 --- /dev/null +++ b/include/dt-bindings/clock/r8a774a1-cpg-mssr.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2018 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__ + +#include <dt-bindings/clock/renesas-cpg-mssr.h> + +/* r8a774a1 CPG Core Clocks */ +#define R8A774A1_CLK_Z 0 +#define R8A774A1_CLK_Z2 1 +#define R8A774A1_CLK_ZG 2 +#define R8A774A1_CLK_ZTR 3 +#define R8A774A1_CLK_ZTRD2 4 +#define R8A774A1_CLK_ZT 5 +#define R8A774A1_CLK_ZX 6 +#define R8A774A1_CLK_S0D1 7 +#define R8A774A1_CLK_S0D2 8 +#define R8A774A1_CLK_S0D3 9 +#define R8A774A1_CLK_S0D4 10 +#define R8A774A1_CLK_S0D6 11 +#define R8A774A1_CLK_S0D8 12 +#define R8A774A1_CLK_S0D12 13 +#define R8A774A1_CLK_S1D2 14 +#define R8A774A1_CLK_S1D4 15 +#define R8A774A1_CLK_S2D1 16 +#define R8A774A1_CLK_S2D2 17 +#define R8A774A1_CLK_S2D4 18 +#define R8A774A1_CLK_S3D1 19 +#define R8A774A1_CLK_S3D2 20 +#define R8A774A1_CLK_S3D4 21 +#define R8A774A1_CLK_LB 22 +#define R8A774A1_CLK_CL 23 +#define R8A774A1_CLK_ZB3 24 +#define R8A774A1_CLK_ZB3D2 25 +#define R8A774A1_CLK_ZB3D4 26 +#define R8A774A1_CLK_CR 27 +#define R8A774A1_CLK_CRD2 28 +#define R8A774A1_CLK_SD0H 29 +#define R8A774A1_CLK_SD0 30 +#define R8A774A1_CLK_SD1H 31 +#define R8A774A1_CLK_SD1 32 +#define R8A774A1_CLK_SD2H 33 +#define R8A774A1_CLK_SD2 34 +#define R8A774A1_CLK_SD3H 35 +#define R8A774A1_CLK_SD3 36 +#define R8A774A1_CLK_RPC 37 +#define R8A774A1_CLK_RPCD2 38 +#define R8A774A1_CLK_MSO 39 +#define R8A774A1_CLK_HDMI 40 +#define R8A774A1_CLK_CSI0 41 +#define R8A774A1_CLK_CP 42 +#define R8A774A1_CLK_CPEX 43 +#define R8A774A1_CLK_R 44 +#define R8A774A1_CLK_OSC 45 + +#endif /* __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__ */ diff --git a/include/dt-bindings/clock/r8a774c0-cpg-mssr.h b/include/dt-bindings/clock/r8a774c0-cpg-mssr.h new file mode 100644 index 000000000000..8fe51b6aca28 --- /dev/null +++ b/include/dt-bindings/clock/r8a774c0-cpg-mssr.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_R8A774C0_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_R8A774C0_CPG_MSSR_H__ + +#include <dt-bindings/clock/renesas-cpg-mssr.h> + +/* r8a774c0 CPG Core Clocks */ +#define R8A774C0_CLK_Z2 0 +#define R8A774C0_CLK_ZG 1 +#define R8A774C0_CLK_ZTR 2 +#define R8A774C0_CLK_ZT 3 +#define R8A774C0_CLK_ZX 4 +#define R8A774C0_CLK_S0D1 5 +#define R8A774C0_CLK_S0D3 6 +#define R8A774C0_CLK_S0D6 7 +#define R8A774C0_CLK_S0D12 8 +#define R8A774C0_CLK_S0D24 9 +#define R8A774C0_CLK_S1D1 10 +#define R8A774C0_CLK_S1D2 11 +#define R8A774C0_CLK_S1D4 12 +#define R8A774C0_CLK_S2D1 13 +#define R8A774C0_CLK_S2D2 14 +#define R8A774C0_CLK_S2D4 15 +#define R8A774C0_CLK_S3D1 16 +#define R8A774C0_CLK_S3D2 17 +#define R8A774C0_CLK_S3D4 18 +#define R8A774C0_CLK_S0D6C 19 +#define R8A774C0_CLK_S3D1C 20 +#define R8A774C0_CLK_S3D2C 21 +#define R8A774C0_CLK_S3D4C 22 +#define R8A774C0_CLK_LB 23 +#define R8A774C0_CLK_CL 24 +#define R8A774C0_CLK_ZB3 25 +#define R8A774C0_CLK_ZB3D2 26 +#define R8A774C0_CLK_CR 27 +#define R8A774C0_CLK_CRD2 28 +#define R8A774C0_CLK_SD0H 29 +#define R8A774C0_CLK_SD0 30 +#define R8A774C0_CLK_SD1H 31 +#define R8A774C0_CLK_SD1 32 +#define R8A774C0_CLK_SD3H 33 +#define R8A774C0_CLK_SD3 34 +#define R8A774C0_CLK_RPC 35 +#define R8A774C0_CLK_RPCD2 36 +#define R8A774C0_CLK_ZA2 37 +#define R8A774C0_CLK_ZA8 38 +#define R8A774C0_CLK_Z2D 39 +#define R8A774C0_CLK_MSO 40 +#define R8A774C0_CLK_R 41 +#define R8A774C0_CLK_OSC 42 +#define R8A774C0_CLK_LV0 43 +#define R8A774C0_CLK_LV1 44 +#define R8A774C0_CLK_CSI0 45 +#define R8A774C0_CLK_CP 46 +#define R8A774C0_CLK_CPEX 47 + +#endif /* __DT_BINDINGS_CLOCK_R8A774C0_CPG_MSSR_H__ */ diff --git a/include/dt-bindings/clock/r8a7790-cpg-mssr.h b/include/dt-bindings/clock/r8a7790-cpg-mssr.h index 1625b8bf3482..c5955b56b36d 100644 --- a/include/dt-bindings/clock/r8a7790-cpg-mssr.h +++ b/include/dt-bindings/clock/r8a7790-cpg-mssr.h @@ -1,10 +1,6 @@ -/* - * Copyright (C) 2015 Renesas Electronics Corp. +/* SPDX-License-Identifier: GPL-2.0+ * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. + * Copyright (C) 2015 Renesas Electronics Corp. */ #ifndef __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__ diff --git a/include/dt-bindings/clock/r8a7791-cpg-mssr.h b/include/dt-bindings/clock/r8a7791-cpg-mssr.h index e8823410c01c..aadd06c566c0 100644 --- a/include/dt-bindings/clock/r8a7791-cpg-mssr.h +++ b/include/dt-bindings/clock/r8a7791-cpg-mssr.h @@ -1,10 +1,6 @@ -/* - * Copyright (C) 2015 Renesas Electronics Corp. +/* SPDX-License-Identifier: GPL-2.0+ * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. + * Copyright (C) 2015 Renesas Electronics Corp. */ #ifndef __DT_BINDINGS_CLOCK_R8A7791_CPG_MSSR_H__ diff --git a/include/dt-bindings/clock/r8a7792-cpg-mssr.h b/include/dt-bindings/clock/r8a7792-cpg-mssr.h index 72ce85cb2f94..829c44db0271 100644 --- a/include/dt-bindings/clock/r8a7792-cpg-mssr.h +++ b/include/dt-bindings/clock/r8a7792-cpg-mssr.h @@ -1,10 +1,6 @@ -/* - * Copyright (C) 2015 Renesas Electronics Corp. +/* SPDX-License-Identifier: GPL-2.0+ * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. + * Copyright (C) 2015 Renesas Electronics Corp. */ #ifndef __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__ diff --git a/include/dt-bindings/clock/r8a7793-clock.h b/include/dt-bindings/clock/r8a7793-clock.h index 7318d45d4e7e..49c66d8ed178 100644 --- a/include/dt-bindings/clock/r8a7793-clock.h +++ b/include/dt-bindings/clock/r8a7793-clock.h @@ -1,16 +1,8 @@ -/* +/* SPDX-License-Identifier: GPL-2.0 + * * r8a7793 clock definition * * Copyright (C) 2014 Renesas Electronics Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #ifndef __DT_BINDINGS_CLOCK_R8A7793_H__ diff --git a/include/dt-bindings/clock/r8a7793-cpg-mssr.h b/include/dt-bindings/clock/r8a7793-cpg-mssr.h index 8809b0f62d61..d1ff646c31f2 100644 --- a/include/dt-bindings/clock/r8a7793-cpg-mssr.h +++ b/include/dt-bindings/clock/r8a7793-cpg-mssr.h @@ -1,10 +1,6 @@ -/* - * Copyright (C) 2015 Renesas Electronics Corp. +/* SPDX-License-Identifier: GPL-2.0+ * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. + * Copyright (C) 2015 Renesas Electronics Corp. */ #ifndef __DT_BINDINGS_CLOCK_R8A7793_CPG_MSSR_H__ diff --git a/include/dt-bindings/clock/r8a7794-clock.h b/include/dt-bindings/clock/r8a7794-clock.h index 93e99c3ffc8d..649f005782d0 100644 --- a/include/dt-bindings/clock/r8a7794-clock.h +++ b/include/dt-bindings/clock/r8a7794-clock.h @@ -1,11 +1,7 @@ -/* +/* SPDX-License-Identifier: GPL-2.0+ + * * Copyright (C) 2014 Renesas Electronics Corporation * Copyright 2013 Ideas On Board SPRL - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. */ #ifndef __DT_BINDINGS_CLOCK_R8A7794_H__ diff --git a/include/dt-bindings/clock/r8a7794-cpg-mssr.h b/include/dt-bindings/clock/r8a7794-cpg-mssr.h index 9d720311ae3a..6314e23b51af 100644 --- a/include/dt-bindings/clock/r8a7794-cpg-mssr.h +++ b/include/dt-bindings/clock/r8a7794-cpg-mssr.h @@ -1,10 +1,6 @@ -/* - * Copyright (C) 2015 Renesas Electronics Corp. +/* SPDX-License-Identifier: GPL-2.0+ * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. + * Copyright (C) 2015 Renesas Electronics Corp. */ #ifndef __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__ diff --git a/include/dt-bindings/clock/r8a7795-cpg-mssr.h b/include/dt-bindings/clock/r8a7795-cpg-mssr.h index f047eaf261f3..92b3e2a95179 100644 --- a/include/dt-bindings/clock/r8a7795-cpg-mssr.h +++ b/include/dt-bindings/clock/r8a7795-cpg-mssr.h @@ -1,10 +1,6 @@ -/* - * Copyright (C) 2015 Renesas Electronics Corp. +/* SPDX-License-Identifier: GPL-2.0+ * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. + * Copyright (C) 2015 Renesas Electronics Corp. */ #ifndef __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__ #define __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__ @@ -54,7 +50,7 @@ #define R8A7795_CLK_CANFD 39 #define R8A7795_CLK_HDMI 40 #define R8A7795_CLK_CSI0 41 -#define R8A7795_CLK_CSIREF 42 +/* CLK_CSIREF was removed */ #define R8A7795_CLK_CP 43 #define R8A7795_CLK_CPEX 44 #define R8A7795_CLK_R 45 diff --git a/include/dt-bindings/clock/r8a7796-cpg-mssr.h b/include/dt-bindings/clock/r8a7796-cpg-mssr.h index 1e5942695f0d..c0957cf45840 100644 --- a/include/dt-bindings/clock/r8a7796-cpg-mssr.h +++ b/include/dt-bindings/clock/r8a7796-cpg-mssr.h @@ -1,10 +1,6 @@ -/* - * Copyright (C) 2016 Renesas Electronics Corp. +/* SPDX-License-Identifier: GPL-2.0+ * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. + * Copyright (C) 2016 Renesas Electronics Corp. */ #ifndef __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__ #define __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__ @@ -60,7 +56,7 @@ #define R8A7796_CLK_CANFD 45 #define R8A7796_CLK_HDMI 46 #define R8A7796_CLK_CSI0 47 -#define R8A7796_CLK_CSIREF 48 +/* CLK_CSIREF was removed */ #define R8A7796_CLK_CP 49 #define R8A7796_CLK_CPEX 50 #define R8A7796_CLK_R 51 diff --git a/include/dt-bindings/clock/r8a77970-cpg-mssr.h b/include/dt-bindings/clock/r8a77970-cpg-mssr.h index 4146395595b1..6145ebe66361 100644 --- a/include/dt-bindings/clock/r8a77970-cpg-mssr.h +++ b/include/dt-bindings/clock/r8a77970-cpg-mssr.h @@ -1,11 +1,7 @@ -/* +/* SPDX-License-Identifier: GPL-2.0+ + * * Copyright (C) 2016 Renesas Electronics Corp. * Copyright (C) 2017 Cogent Embedded, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. */ #ifndef __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__ #define __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__ diff --git a/include/dt-bindings/clock/r8a77990-cpg-mssr.h b/include/dt-bindings/clock/r8a77990-cpg-mssr.h new file mode 100644 index 000000000000..a596a482f3a9 --- /dev/null +++ b/include/dt-bindings/clock/r8a77990-cpg-mssr.h @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__ + +#include <dt-bindings/clock/renesas-cpg-mssr.h> + +/* r8a77990 CPG Core Clocks */ +#define R8A77990_CLK_Z2 0 +#define R8A77990_CLK_ZR 1 +#define R8A77990_CLK_ZG 2 +#define R8A77990_CLK_ZTR 3 +#define R8A77990_CLK_ZT 4 +#define R8A77990_CLK_ZX 5 +#define R8A77990_CLK_S0D1 6 +#define R8A77990_CLK_S0D3 7 +#define R8A77990_CLK_S0D6 8 +#define R8A77990_CLK_S0D12 9 +#define R8A77990_CLK_S0D24 10 +#define R8A77990_CLK_S1D1 11 +#define R8A77990_CLK_S1D2 12 +#define R8A77990_CLK_S1D4 13 +#define R8A77990_CLK_S2D1 14 +#define R8A77990_CLK_S2D2 15 +#define R8A77990_CLK_S2D4 16 +#define R8A77990_CLK_S3D1 17 +#define R8A77990_CLK_S3D2 18 +#define R8A77990_CLK_S3D4 19 +#define R8A77990_CLK_S0D6C 20 +#define R8A77990_CLK_S3D1C 21 +#define R8A77990_CLK_S3D2C 22 +#define R8A77990_CLK_S3D4C 23 +#define R8A77990_CLK_LB 24 +#define R8A77990_CLK_CL 25 +#define R8A77990_CLK_ZB3 26 +#define R8A77990_CLK_ZB3D2 27 +#define R8A77990_CLK_CR 28 +#define R8A77990_CLK_CRD2 29 +#define R8A77990_CLK_SD0H 30 +#define R8A77990_CLK_SD0 31 +#define R8A77990_CLK_SD1H 32 +#define R8A77990_CLK_SD1 33 +#define R8A77990_CLK_SD3H 34 +#define R8A77990_CLK_SD3 35 +#define R8A77990_CLK_RPC 36 +#define R8A77990_CLK_RPCD2 37 +#define R8A77990_CLK_ZA2 38 +#define R8A77990_CLK_ZA8 39 +#define R8A77990_CLK_Z2D 40 +#define R8A77990_CLK_CANFD 41 +#define R8A77990_CLK_MSO 42 +#define R8A77990_CLK_R 43 +#define R8A77990_CLK_OSC 44 +#define R8A77990_CLK_LV0 45 +#define R8A77990_CLK_LV1 46 +#define R8A77990_CLK_CSI0 47 +#define R8A77990_CLK_CP 48 +#define R8A77990_CLK_CPEX 49 + +#endif /* __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__ */ diff --git a/include/dt-bindings/clock/r8a77995-cpg-mssr.h b/include/dt-bindings/clock/r8a77995-cpg-mssr.h index 4e8ae3dee590..fd701c4e87cf 100644 --- a/include/dt-bindings/clock/r8a77995-cpg-mssr.h +++ b/include/dt-bindings/clock/r8a77995-cpg-mssr.h @@ -1,10 +1,6 @@ -/* - * Copyright (C) 2017 Glider bvba +/* SPDX-License-Identifier: GPL-2.0+ * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. + * Copyright (C) 2017 Glider bvba */ #ifndef __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__ #define __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__ @@ -39,8 +35,8 @@ #define R8A77995_CLK_CRD2 24 #define R8A77995_CLK_SD0H 25 #define R8A77995_CLK_SD0 26 -#define R8A77995_CLK_SSP2 27 -#define R8A77995_CLK_SSP1 28 +/* CLK_SSP2 was removed */ +/* CLK_SSP1 was removed */ #define R8A77995_CLK_RPC 29 #define R8A77995_CLK_RPCD2 30 #define R8A77995_CLK_ZA2 31 @@ -53,5 +49,6 @@ #define R8A77995_CLK_LV0 38 #define R8A77995_CLK_LV1 39 #define R8A77995_CLK_CP 40 +#define R8A77995_CLK_CPEX 41 #endif /* __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__ */ diff --git a/include/dt-bindings/clock/r9a06g032-sysctrl.h b/include/dt-bindings/clock/r9a06g032-sysctrl.h new file mode 100644 index 000000000000..90c0f3dc1ba1 --- /dev/null +++ b/include/dt-bindings/clock/r9a06g032-sysctrl.h @@ -0,0 +1,148 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * R9A06G032 sysctrl IDs + * + * Copyright (C) 2018 Renesas Electronics Europe Limited + * + * Michel Pollet <michel.pollet@bp.renesas.com>, <buserror@gmail.com> + */ + +#ifndef __DT_BINDINGS_R9A06G032_SYSCTRL_H__ +#define __DT_BINDINGS_R9A06G032_SYSCTRL_H__ + +#define R9A06G032_CLK_PLL_USB 1 +#define R9A06G032_CLK_48 1 /* AKA CLK_PLL_USB */ +#define R9A06G032_MSEBIS_CLK 3 /* AKA CLKOUT_D16 */ +#define R9A06G032_MSEBIM_CLK 3 /* AKA CLKOUT_D16 */ +#define R9A06G032_CLK_DDRPHY_PLLCLK 5 /* AKA CLKOUT_D1OR2 */ +#define R9A06G032_CLK50 6 /* AKA CLKOUT_D20 */ +#define R9A06G032_CLK25 7 /* AKA CLKOUT_D40 */ +#define R9A06G032_CLK125 9 /* AKA CLKOUT_D8 */ +#define R9A06G032_CLK_P5_PG1 17 /* AKA DIV_P5_PG */ +#define R9A06G032_CLK_REF_SYNC 21 /* AKA DIV_REF_SYNC */ +#define R9A06G032_CLK_25_PG4 26 +#define R9A06G032_CLK_25_PG5 27 +#define R9A06G032_CLK_25_PG6 28 +#define R9A06G032_CLK_25_PG7 29 +#define R9A06G032_CLK_25_PG8 30 +#define R9A06G032_CLK_ADC 31 +#define R9A06G032_CLK_ECAT100 32 +#define R9A06G032_CLK_HSR100 33 +#define R9A06G032_CLK_I2C0 34 +#define R9A06G032_CLK_I2C1 35 +#define R9A06G032_CLK_MII_REF 36 +#define R9A06G032_CLK_NAND 37 +#define R9A06G032_CLK_NOUSBP2_PG6 38 +#define R9A06G032_CLK_P1_PG2 39 +#define R9A06G032_CLK_P1_PG3 40 +#define R9A06G032_CLK_P1_PG4 41 +#define R9A06G032_CLK_P4_PG3 42 +#define R9A06G032_CLK_P4_PG4 43 +#define R9A06G032_CLK_P6_PG1 44 +#define R9A06G032_CLK_P6_PG2 45 +#define R9A06G032_CLK_P6_PG3 46 +#define R9A06G032_CLK_P6_PG4 47 +#define R9A06G032_CLK_PCI_USB 48 +#define R9A06G032_CLK_QSPI0 49 +#define R9A06G032_CLK_QSPI1 50 +#define R9A06G032_CLK_RGMII_REF 51 +#define R9A06G032_CLK_RMII_REF 52 +#define R9A06G032_CLK_SDIO0 53 +#define R9A06G032_CLK_SDIO1 54 +#define R9A06G032_CLK_SERCOS100 55 +#define R9A06G032_CLK_SLCD 56 +#define R9A06G032_CLK_SPI0 57 +#define R9A06G032_CLK_SPI1 58 +#define R9A06G032_CLK_SPI2 59 +#define R9A06G032_CLK_SPI3 60 +#define R9A06G032_CLK_SPI4 61 +#define R9A06G032_CLK_SPI5 62 +#define R9A06G032_CLK_SWITCH 63 +#define R9A06G032_HCLK_ECAT125 65 +#define R9A06G032_HCLK_PINCONFIG 66 +#define R9A06G032_HCLK_SERCOS 67 +#define R9A06G032_HCLK_SGPIO2 68 +#define R9A06G032_HCLK_SGPIO3 69 +#define R9A06G032_HCLK_SGPIO4 70 +#define R9A06G032_HCLK_TIMER0 71 +#define R9A06G032_HCLK_TIMER1 72 +#define R9A06G032_HCLK_USBF 73 +#define R9A06G032_HCLK_USBH 74 +#define R9A06G032_HCLK_USBPM 75 +#define R9A06G032_CLK_48_PG_F 76 +#define R9A06G032_CLK_48_PG4 77 +#define R9A06G032_CLK_DDRPHY_PCLK 81 /* AKA CLK_REF_SYNC_D4 */ +#define R9A06G032_CLK_FW 81 /* AKA CLK_REF_SYNC_D4 */ +#define R9A06G032_CLK_CRYPTO 81 /* AKA CLK_REF_SYNC_D4 */ +#define R9A06G032_CLK_A7MP 84 /* AKA DIV_CA7 */ +#define R9A06G032_HCLK_CAN0 85 +#define R9A06G032_HCLK_CAN1 86 +#define R9A06G032_HCLK_DELTASIGMA 87 +#define R9A06G032_HCLK_PWMPTO 88 +#define R9A06G032_HCLK_RSV 89 +#define R9A06G032_HCLK_SGPIO0 90 +#define R9A06G032_HCLK_SGPIO1 91 +#define R9A06G032_RTOS_MDC 92 +#define R9A06G032_CLK_CM3 93 +#define R9A06G032_CLK_DDRC 94 +#define R9A06G032_CLK_ECAT25 95 +#define R9A06G032_CLK_HSR50 96 +#define R9A06G032_CLK_HW_RTOS 97 +#define R9A06G032_CLK_SERCOS50 98 +#define R9A06G032_HCLK_ADC 99 +#define R9A06G032_HCLK_CM3 100 +#define R9A06G032_HCLK_CRYPTO_EIP150 101 +#define R9A06G032_HCLK_CRYPTO_EIP93 102 +#define R9A06G032_HCLK_DDRC 103 +#define R9A06G032_HCLK_DMA0 104 +#define R9A06G032_HCLK_DMA1 105 +#define R9A06G032_HCLK_GMAC0 106 +#define R9A06G032_HCLK_GMAC1 107 +#define R9A06G032_HCLK_GPIO0 108 +#define R9A06G032_HCLK_GPIO1 109 +#define R9A06G032_HCLK_GPIO2 110 +#define R9A06G032_HCLK_HSR 111 +#define R9A06G032_HCLK_I2C0 112 +#define R9A06G032_HCLK_I2C1 113 +#define R9A06G032_HCLK_LCD 114 +#define R9A06G032_HCLK_MSEBI_M 115 +#define R9A06G032_HCLK_MSEBI_S 116 +#define R9A06G032_HCLK_NAND 117 +#define R9A06G032_HCLK_PG_I 118 +#define R9A06G032_HCLK_PG19 119 +#define R9A06G032_HCLK_PG20 120 +#define R9A06G032_HCLK_PG3 121 +#define R9A06G032_HCLK_PG4 122 +#define R9A06G032_HCLK_QSPI0 123 +#define R9A06G032_HCLK_QSPI1 124 +#define R9A06G032_HCLK_ROM 125 +#define R9A06G032_HCLK_RTC 126 +#define R9A06G032_HCLK_SDIO0 127 +#define R9A06G032_HCLK_SDIO1 128 +#define R9A06G032_HCLK_SEMAP 129 +#define R9A06G032_HCLK_SPI0 130 +#define R9A06G032_HCLK_SPI1 131 +#define R9A06G032_HCLK_SPI2 132 +#define R9A06G032_HCLK_SPI3 133 +#define R9A06G032_HCLK_SPI4 134 +#define R9A06G032_HCLK_SPI5 135 +#define R9A06G032_HCLK_SWITCH 136 +#define R9A06G032_HCLK_SWITCH_RG 137 +#define R9A06G032_HCLK_UART0 138 +#define R9A06G032_HCLK_UART1 139 +#define R9A06G032_HCLK_UART2 140 +#define R9A06G032_HCLK_UART3 141 +#define R9A06G032_HCLK_UART4 142 +#define R9A06G032_HCLK_UART5 143 +#define R9A06G032_HCLK_UART6 144 +#define R9A06G032_HCLK_UART7 145 +#define R9A06G032_CLK_UART0 146 +#define R9A06G032_CLK_UART1 147 +#define R9A06G032_CLK_UART2 148 +#define R9A06G032_CLK_UART3 149 +#define R9A06G032_CLK_UART4 150 +#define R9A06G032_CLK_UART5 151 +#define R9A06G032_CLK_UART6 152 +#define R9A06G032_CLK_UART7 153 + +#endif /* __DT_BINDINGS_R9A06G032_SYSCTRL_H__ */ diff --git a/include/dt-bindings/clock/renesas-cpg-mssr.h b/include/dt-bindings/clock/renesas-cpg-mssr.h index 569a3cc33ffb..8169ad063f0a 100644 --- a/include/dt-bindings/clock/renesas-cpg-mssr.h +++ b/include/dt-bindings/clock/renesas-cpg-mssr.h @@ -1,10 +1,6 @@ -/* - * Copyright (C) 2015 Renesas Electronics Corp. +/* SPDX-License-Identifier: GPL-2.0+ * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. + * Copyright (C) 2015 Renesas Electronics Corp. */ #ifndef __DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H__ #define __DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H__ diff --git a/include/dt-bindings/clock/rk3188-cru-common.h b/include/dt-bindings/clock/rk3188-cru-common.h index b9462b7d3dfe..dc2101a634be 100644 --- a/include/dt-bindings/clock/rk3188-cru-common.h +++ b/include/dt-bindings/clock/rk3188-cru-common.h @@ -139,8 +139,9 @@ #define HCLK_CIF1 470 #define HCLK_VEPU 471 #define HCLK_VDPU 472 +#define HCLK_HDMI 473 -#define CLK_NR_CLKS (HCLK_VDPU + 1) +#define CLK_NR_CLKS (HCLK_HDMI + 1) /* soft-reset indices */ #define SRST_MCORE 2 diff --git a/include/dt-bindings/clock/rk3328-cru.h b/include/dt-bindings/clock/rk3328-cru.h index a82a0109faff..bcaa4559ab1b 100644 --- a/include/dt-bindings/clock/rk3328-cru.h +++ b/include/dt-bindings/clock/rk3328-cru.h @@ -172,13 +172,14 @@ #define PCLK_HDCP 232 #define PCLK_DCF 233 #define PCLK_SARADC 234 +#define PCLK_ACODECPHY 235 /* hclk gates */ #define HCLK_PERI 308 #define HCLK_TSP 309 #define HCLK_GMAC 310 #define HCLK_I2S0_8CH 311 -#define HCLK_I2S1_8CH 313 +#define HCLK_I2S1_8CH 312 #define HCLK_I2S2_2CH 313 #define HCLK_SPDIF_8CH 314 #define HCLK_VOP 315 diff --git a/include/dt-bindings/clock/rk3399-ddr.h b/include/dt-bindings/clock/rk3399-ddr.h new file mode 100644 index 000000000000..ed2280844963 --- /dev/null +++ b/include/dt-bindings/clock/rk3399-ddr.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ + +#ifndef DT_BINDINGS_DDR_H +#define DT_BINDINGS_DDR_H + +/* + * DDR3 SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for + * each corresponding bin. + */ + +/* DDR3-800 (5-5-5) */ +#define DDR3_800D 0 +/* DDR3-800 (6-6-6) */ +#define DDR3_800E 1 +/* DDR3-1066 (6-6-6) */ +#define DDR3_1066E 2 +/* DDR3-1066 (7-7-7) */ +#define DDR3_1066F 3 +/* DDR3-1066 (8-8-8) */ +#define DDR3_1066G 4 +/* DDR3-1333 (7-7-7) */ +#define DDR3_1333F 5 +/* DDR3-1333 (8-8-8) */ +#define DDR3_1333G 6 +/* DDR3-1333 (9-9-9) */ +#define DDR3_1333H 7 +/* DDR3-1333 (10-10-10) */ +#define DDR3_1333J 8 +/* DDR3-1600 (8-8-8) */ +#define DDR3_1600G 9 +/* DDR3-1600 (9-9-9) */ +#define DDR3_1600H 10 +/* DDR3-1600 (10-10-10) */ +#define DDR3_1600J 11 +/* DDR3-1600 (11-11-11) */ +#define DDR3_1600K 12 +/* DDR3-1600 (10-10-10) */ +#define DDR3_1866J 13 +/* DDR3-1866 (11-11-11) */ +#define DDR3_1866K 14 +/* DDR3-1866 (12-12-12) */ +#define DDR3_1866L 15 +/* DDR3-1866 (13-13-13) */ +#define DDR3_1866M 16 +/* DDR3-2133 (11-11-11) */ +#define DDR3_2133K 17 +/* DDR3-2133 (12-12-12) */ +#define DDR3_2133L 18 +/* DDR3-2133 (13-13-13) */ +#define DDR3_2133M 19 +/* DDR3-2133 (14-14-14) */ +#define DDR3_2133N 20 +/* DDR3 ATF default */ +#define DDR3_DEFAULT 21 + +#endif diff --git a/include/dt-bindings/clock/s3c2410.h b/include/dt-bindings/clock/s3c2410.h index 352a7673fc69..0fb65c3f2f59 100644 --- a/include/dt-bindings/clock/s3c2410.h +++ b/include/dt-bindings/clock/s3c2410.h @@ -1,10 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de> * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * * Device Tree binding constants clock controllers of Samsung S3C2410 and later. */ diff --git a/include/dt-bindings/clock/s3c2412.h b/include/dt-bindings/clock/s3c2412.h index aac1dcfda81c..b4656156cc0f 100644 --- a/include/dt-bindings/clock/s3c2412.h +++ b/include/dt-bindings/clock/s3c2412.h @@ -1,10 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de> * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * * Device Tree binding constants clock controllers of Samsung S3C2412. */ diff --git a/include/dt-bindings/clock/s3c2443.h b/include/dt-bindings/clock/s3c2443.h index f3ba68a25ecb..a9d2f105d536 100644 --- a/include/dt-bindings/clock/s3c2443.h +++ b/include/dt-bindings/clock/s3c2443.h @@ -1,10 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de> * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * * Device Tree binding constants clock controllers of Samsung S3C2443 and later. */ diff --git a/include/dt-bindings/clock/samsung,s2mps11.h b/include/dt-bindings/clock/samsung,s2mps11.h index b903d7de27c9..5ece35d429ff 100644 --- a/include/dt-bindings/clock/samsung,s2mps11.h +++ b/include/dt-bindings/clock/samsung,s2mps11.h @@ -1,10 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2015 Markus Reichl * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * * Device Tree binding constants clocks for the Samsung S2MPS11 PMIC. */ diff --git a/include/dt-bindings/clock/samsung,s3c64xx-clock.h b/include/dt-bindings/clock/samsung,s3c64xx-clock.h index ad95c7f50090..19d233f37e2f 100644 --- a/include/dt-bindings/clock/samsung,s3c64xx-clock.h +++ b/include/dt-bindings/clock/samsung,s3c64xx-clock.h @@ -1,12 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (c) 2013 Tomasz Figa <tomasz.figa at gmail.com> * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * * Device Tree binding constants for Samsung S3C64xx clock controller. -*/ + */ #ifndef _DT_BINDINGS_CLOCK_SAMSUNG_S3C64XX_CLOCK_H #define _DT_BINDINGS_CLOCK_SAMSUNG_S3C64XX_CLOCK_H diff --git a/include/dt-bindings/clock/sun50i-a64-ccu.h b/include/dt-bindings/clock/sun50i-a64-ccu.h index d66432c6e675..a8ac4cfcdcbc 100644 --- a/include/dt-bindings/clock/sun50i-a64-ccu.h +++ b/include/dt-bindings/clock/sun50i-a64-ccu.h @@ -43,6 +43,7 @@ #ifndef _DT_BINDINGS_CLK_SUN50I_A64_H_ #define _DT_BINDINGS_CLK_SUN50I_A64_H_ +#define CLK_PLL_VIDEO0 7 #define CLK_PLL_PERIPH0 11 #define CLK_BUS_MIPI_DSI 28 diff --git a/include/dt-bindings/clock/sun50i-h6-r-ccu.h b/include/dt-bindings/clock/sun50i-h6-r-ccu.h new file mode 100644 index 000000000000..76136132a13e --- /dev/null +++ b/include/dt-bindings/clock/sun50i-h6-r-ccu.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.xyz> + */ + +#ifndef _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_ +#define _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_ + +#define CLK_AR100 0 + +#define CLK_R_APB1 2 + +#define CLK_R_APB1_TIMER 4 +#define CLK_R_APB1_TWD 5 +#define CLK_R_APB1_PWM 6 +#define CLK_R_APB2_UART 7 +#define CLK_R_APB2_I2C 8 +#define CLK_R_APB1_IR 9 +#define CLK_R_APB1_W1 10 + +#define CLK_IR 11 +#define CLK_W1 12 + +#endif /* _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_ */ diff --git a/include/dt-bindings/clock/sun8i-de2.h b/include/dt-bindings/clock/sun8i-de2.h index 3bed63b524aa..7768f73b051e 100644 --- a/include/dt-bindings/clock/sun8i-de2.h +++ b/include/dt-bindings/clock/sun8i-de2.h @@ -15,4 +15,7 @@ #define CLK_MIXER1 7 #define CLK_WB 8 +#define CLK_BUS_ROT 9 +#define CLK_ROT 10 + #endif /* _DT_BINDINGS_CLOCK_SUN8I_DE2_H_ */ diff --git a/include/dt-bindings/clock/sun8i-r40-ccu.h b/include/dt-bindings/clock/sun8i-r40-ccu.h index 4fa5f69fc297..f9e15a235626 100644 --- a/include/dt-bindings/clock/sun8i-r40-ccu.h +++ b/include/dt-bindings/clock/sun8i-r40-ccu.h @@ -43,6 +43,10 @@ #ifndef _DT_BINDINGS_CLK_SUN8I_R40_H_ #define _DT_BINDINGS_CLK_SUN8I_R40_H_ +#define CLK_PLL_VIDEO0 7 + +#define CLK_PLL_VIDEO1 16 + #define CLK_CPU 24 #define CLK_BUS_MIPI_DSI 29 diff --git a/include/dt-bindings/clock/sun8i-tcon-top.h b/include/dt-bindings/clock/sun8i-tcon-top.h new file mode 100644 index 000000000000..25164d767835 --- /dev/null +++ b/include/dt-bindings/clock/sun8i-tcon-top.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* Copyright (C) 2018 Jernej Skrabec <jernej.skrabec@siol.net> */ + +#ifndef _DT_BINDINGS_CLOCK_SUN8I_TCON_TOP_H_ +#define _DT_BINDINGS_CLOCK_SUN8I_TCON_TOP_H_ + +#define CLK_TCON_TOP_TV0 0 +#define CLK_TCON_TOP_TV1 1 +#define CLK_TCON_TOP_DSI 2 + +#endif /* _DT_BINDINGS_CLOCK_SUN8I_TCON_TOP_H_ */ diff --git a/include/dt-bindings/clock/suniv-ccu-f1c100s.h b/include/dt-bindings/clock/suniv-ccu-f1c100s.h new file mode 100644 index 000000000000..f5ac155c9c70 --- /dev/null +++ b/include/dt-bindings/clock/suniv-ccu-f1c100s.h @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) + * + * Copyright (c) 2018 Icenowy Zheng <icenowy@aosc.xyz> + * + */ + +#ifndef _DT_BINDINGS_CLK_SUNIV_F1C100S_H_ +#define _DT_BINDINGS_CLK_SUNIV_F1C100S_H_ + +#define CLK_CPU 11 + +#define CLK_BUS_DMA 14 +#define CLK_BUS_MMC0 15 +#define CLK_BUS_MMC1 16 +#define CLK_BUS_DRAM 17 +#define CLK_BUS_SPI0 18 +#define CLK_BUS_SPI1 19 +#define CLK_BUS_OTG 20 +#define CLK_BUS_VE 21 +#define CLK_BUS_LCD 22 +#define CLK_BUS_DEINTERLACE 23 +#define CLK_BUS_CSI 24 +#define CLK_BUS_TVD 25 +#define CLK_BUS_TVE 26 +#define CLK_BUS_DE_BE 27 +#define CLK_BUS_DE_FE 28 +#define CLK_BUS_CODEC 29 +#define CLK_BUS_SPDIF 30 +#define CLK_BUS_IR 31 +#define CLK_BUS_RSB 32 +#define CLK_BUS_I2S0 33 +#define CLK_BUS_I2C0 34 +#define CLK_BUS_I2C1 35 +#define CLK_BUS_I2C2 36 +#define CLK_BUS_PIO 37 +#define CLK_BUS_UART0 38 +#define CLK_BUS_UART1 39 +#define CLK_BUS_UART2 40 + +#define CLK_MMC0 41 +#define CLK_MMC0_SAMPLE 42 +#define CLK_MMC0_OUTPUT 43 +#define CLK_MMC1 44 +#define CLK_MMC1_SAMPLE 45 +#define CLK_MMC1_OUTPUT 46 +#define CLK_I2S 47 +#define CLK_SPDIF 48 + +#define CLK_USB_PHY0 49 + +#define CLK_DRAM_VE 50 +#define CLK_DRAM_CSI 51 +#define CLK_DRAM_DEINTERLACE 52 +#define CLK_DRAM_TVD 53 +#define CLK_DRAM_DE_FE 54 +#define CLK_DRAM_DE_BE 55 + +#define CLK_DE_BE 56 +#define CLK_DE_FE 57 +#define CLK_TCON 58 +#define CLK_DEINTERLACE 59 +#define CLK_TVE2_CLK 60 +#define CLK_TVE1_CLK 61 +#define CLK_TVD 62 +#define CLK_CSI 63 +#define CLK_VE 64 +#define CLK_CODEC 65 +#define CLK_AVS 66 + +#endif diff --git a/include/dt-bindings/clock/xlnx,zynqmp-clk.h b/include/dt-bindings/clock/xlnx,zynqmp-clk.h new file mode 100644 index 000000000000..4aebe6e2049e --- /dev/null +++ b/include/dt-bindings/clock/xlnx,zynqmp-clk.h @@ -0,0 +1,116 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Xilinx Zynq MPSoC Firmware layer + * + * Copyright (C) 2014-2018 Xilinx, Inc. + * + */ + +#ifndef _DT_BINDINGS_CLK_ZYNQMP_H +#define _DT_BINDINGS_CLK_ZYNQMP_H + +#define IOPLL 0 +#define RPLL 1 +#define APLL 2 +#define DPLL 3 +#define VPLL 4 +#define IOPLL_TO_FPD 5 +#define RPLL_TO_FPD 6 +#define APLL_TO_LPD 7 +#define DPLL_TO_LPD 8 +#define VPLL_TO_LPD 9 +#define ACPU 10 +#define ACPU_HALF 11 +#define DBF_FPD 12 +#define DBF_LPD 13 +#define DBG_TRACE 14 +#define DBG_TSTMP 15 +#define DP_VIDEO_REF 16 +#define DP_AUDIO_REF 17 +#define DP_STC_REF 18 +#define GDMA_REF 19 +#define DPDMA_REF 20 +#define DDR_REF 21 +#define SATA_REF 22 +#define PCIE_REF 23 +#define GPU_REF 24 +#define GPU_PP0_REF 25 +#define GPU_PP1_REF 26 +#define TOPSW_MAIN 27 +#define TOPSW_LSBUS 28 +#define GTGREF0_REF 29 +#define LPD_SWITCH 30 +#define LPD_LSBUS 31 +#define USB0_BUS_REF 32 +#define USB1_BUS_REF 33 +#define USB3_DUAL_REF 34 +#define USB0 35 +#define USB1 36 +#define CPU_R5 37 +#define CPU_R5_CORE 38 +#define CSU_SPB 39 +#define CSU_PLL 40 +#define PCAP 41 +#define IOU_SWITCH 42 +#define GEM_TSU_REF 43 +#define GEM_TSU 44 +#define GEM0_REF 45 +#define GEM1_REF 46 +#define GEM2_REF 47 +#define GEM3_REF 48 +#define GEM0_TX 49 +#define GEM1_TX 50 +#define GEM2_TX 51 +#define GEM3_TX 52 +#define QSPI_REF 53 +#define SDIO0_REF 54 +#define SDIO1_REF 55 +#define UART0_REF 56 +#define UART1_REF 57 +#define SPI0_REF 58 +#define SPI1_REF 59 +#define NAND_REF 60 +#define I2C0_REF 61 +#define I2C1_REF 62 +#define CAN0_REF 63 +#define CAN1_REF 64 +#define CAN0 65 +#define CAN1 66 +#define DLL_REF 67 +#define ADMA_REF 68 +#define TIMESTAMP_REF 69 +#define AMS_REF 70 +#define PL0_REF 71 +#define PL1_REF 72 +#define PL2_REF 73 +#define PL3_REF 74 +#define WDT 75 +#define IOPLL_INT 76 +#define IOPLL_PRE_SRC 77 +#define IOPLL_HALF 78 +#define IOPLL_INT_MUX 79 +#define IOPLL_POST_SRC 80 +#define RPLL_INT 81 +#define RPLL_PRE_SRC 82 +#define RPLL_HALF 83 +#define RPLL_INT_MUX 84 +#define RPLL_POST_SRC 85 +#define APLL_INT 86 +#define APLL_PRE_SRC 87 +#define APLL_HALF 88 +#define APLL_INT_MUX 89 +#define APLL_POST_SRC 90 +#define DPLL_INT 91 +#define DPLL_PRE_SRC 92 +#define DPLL_HALF 93 +#define DPLL_INT_MUX 94 +#define DPLL_POST_SRC 95 +#define VPLL_INT 96 +#define VPLL_PRE_SRC 97 +#define VPLL_HALF 98 +#define VPLL_INT_MUX 99 +#define VPLL_POST_SRC 100 +#define CAN0_MIO 101 +#define CAN1_MIO 102 + +#endif diff --git a/include/dt-bindings/dma/dw-dmac.h b/include/dt-bindings/dma/dw-dmac.h new file mode 100644 index 000000000000..d1ca705c95b3 --- /dev/null +++ b/include/dt-bindings/dma/dw-dmac.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ + +#ifndef __DT_BINDINGS_DMA_DW_DMAC_H__ +#define __DT_BINDINGS_DMA_DW_DMAC_H__ + +/* + * Protection Control bits provide protection against illegal transactions. + * The protection bits[0:2] are one-to-one mapped to AHB HPROT[3:1] signals. + */ +#define DW_DMAC_HPROT1_PRIVILEGED_MODE (1 << 0) /* Privileged Mode */ +#define DW_DMAC_HPROT2_BUFFERABLE (1 << 1) /* DMA is bufferable */ +#define DW_DMAC_HPROT3_CACHEABLE (1 << 2) /* DMA is cacheable */ + +#endif /* __DT_BINDINGS_DMA_DW_DMAC_H__ */ diff --git a/include/dt-bindings/dma/jz4780-dma.h b/include/dt-bindings/dma/jz4780-dma.h new file mode 100644 index 000000000000..df017fdfb44e --- /dev/null +++ b/include/dt-bindings/dma/jz4780-dma.h @@ -0,0 +1,49 @@ +#ifndef __DT_BINDINGS_DMA_JZ4780_DMA_H__ +#define __DT_BINDINGS_DMA_JZ4780_DMA_H__ + +/* + * Request type numbers for the JZ4780 DMA controller (written to the DRTn + * register for the channel). + */ +#define JZ4780_DMA_I2S1_TX 0x4 +#define JZ4780_DMA_I2S1_RX 0x5 +#define JZ4780_DMA_I2S0_TX 0x6 +#define JZ4780_DMA_I2S0_RX 0x7 +#define JZ4780_DMA_AUTO 0x8 +#define JZ4780_DMA_SADC_RX 0x9 +#define JZ4780_DMA_UART4_TX 0xc +#define JZ4780_DMA_UART4_RX 0xd +#define JZ4780_DMA_UART3_TX 0xe +#define JZ4780_DMA_UART3_RX 0xf +#define JZ4780_DMA_UART2_TX 0x10 +#define JZ4780_DMA_UART2_RX 0x11 +#define JZ4780_DMA_UART1_TX 0x12 +#define JZ4780_DMA_UART1_RX 0x13 +#define JZ4780_DMA_UART0_TX 0x14 +#define JZ4780_DMA_UART0_RX 0x15 +#define JZ4780_DMA_SSI0_TX 0x16 +#define JZ4780_DMA_SSI0_RX 0x17 +#define JZ4780_DMA_SSI1_TX 0x18 +#define JZ4780_DMA_SSI1_RX 0x19 +#define JZ4780_DMA_MSC0_TX 0x1a +#define JZ4780_DMA_MSC0_RX 0x1b +#define JZ4780_DMA_MSC1_TX 0x1c +#define JZ4780_DMA_MSC1_RX 0x1d +#define JZ4780_DMA_MSC2_TX 0x1e +#define JZ4780_DMA_MSC2_RX 0x1f +#define JZ4780_DMA_PCM0_TX 0x20 +#define JZ4780_DMA_PCM0_RX 0x21 +#define JZ4780_DMA_SMB0_TX 0x24 +#define JZ4780_DMA_SMB0_RX 0x25 +#define JZ4780_DMA_SMB1_TX 0x26 +#define JZ4780_DMA_SMB1_RX 0x27 +#define JZ4780_DMA_SMB2_TX 0x28 +#define JZ4780_DMA_SMB2_RX 0x29 +#define JZ4780_DMA_SMB3_TX 0x2a +#define JZ4780_DMA_SMB3_RX 0x2b +#define JZ4780_DMA_SMB4_TX 0x2c +#define JZ4780_DMA_SMB4_RX 0x2d +#define JZ4780_DMA_DES_TX 0x2e +#define JZ4780_DMA_DES_RX 0x2f + +#endif /* __DT_BINDINGS_DMA_JZ4780_DMA_H__ */ diff --git a/include/dt-bindings/firmware/imx/rsrc.h b/include/dt-bindings/firmware/imx/rsrc.h new file mode 100644 index 000000000000..4481f2d60d65 --- /dev/null +++ b/include/dt-bindings/firmware/imx/rsrc.h @@ -0,0 +1,559 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + */ + +#ifndef __DT_BINDINGS_RSCRC_IMX_H +#define __DT_BINDINGS_RSCRC_IMX_H + +/* + * These defines are used to indicate a resource. Resources include peripherals + * and bus masters (but not memory regions). Note items from list should + * never be changed or removed (only added to at the end of the list). + */ + +#define IMX_SC_R_A53 0 +#define IMX_SC_R_A53_0 1 +#define IMX_SC_R_A53_1 2 +#define IMX_SC_R_A53_2 3 +#define IMX_SC_R_A53_3 4 +#define IMX_SC_R_A72 5 +#define IMX_SC_R_A72_0 6 +#define IMX_SC_R_A72_1 7 +#define IMX_SC_R_A72_2 8 +#define IMX_SC_R_A72_3 9 +#define IMX_SC_R_CCI 10 +#define IMX_SC_R_DB 11 +#define IMX_SC_R_DRC_0 12 +#define IMX_SC_R_DRC_1 13 +#define IMX_SC_R_GIC_SMMU 14 +#define IMX_SC_R_IRQSTR_M4_0 15 +#define IMX_SC_R_IRQSTR_M4_1 16 +#define IMX_SC_R_SMMU 17 +#define IMX_SC_R_GIC 18 +#define IMX_SC_R_DC_0_BLIT0 19 +#define IMX_SC_R_DC_0_BLIT1 20 +#define IMX_SC_R_DC_0_BLIT2 21 +#define IMX_SC_R_DC_0_BLIT_OUT 22 +#define IMX_SC_R_DC_0_CAPTURE0 23 +#define IMX_SC_R_DC_0_CAPTURE1 24 +#define IMX_SC_R_DC_0_WARP 25 +#define IMX_SC_R_DC_0_INTEGRAL0 26 +#define IMX_SC_R_DC_0_INTEGRAL1 27 +#define IMX_SC_R_DC_0_VIDEO0 28 +#define IMX_SC_R_DC_0_VIDEO1 29 +#define IMX_SC_R_DC_0_FRAC0 30 +#define IMX_SC_R_DC_0_FRAC1 31 +#define IMX_SC_R_DC_0 32 +#define IMX_SC_R_GPU_2_PID0 33 +#define IMX_SC_R_DC_0_PLL_0 34 +#define IMX_SC_R_DC_0_PLL_1 35 +#define IMX_SC_R_DC_1_BLIT0 36 +#define IMX_SC_R_DC_1_BLIT1 37 +#define IMX_SC_R_DC_1_BLIT2 38 +#define IMX_SC_R_DC_1_BLIT_OUT 39 +#define IMX_SC_R_DC_1_CAPTURE0 40 +#define IMX_SC_R_DC_1_CAPTURE1 41 +#define IMX_SC_R_DC_1_WARP 42 +#define IMX_SC_R_DC_1_INTEGRAL0 43 +#define IMX_SC_R_DC_1_INTEGRAL1 44 +#define IMX_SC_R_DC_1_VIDEO0 45 +#define IMX_SC_R_DC_1_VIDEO1 46 +#define IMX_SC_R_DC_1_FRAC0 47 +#define IMX_SC_R_DC_1_FRAC1 48 +#define IMX_SC_R_DC_1 49 +#define IMX_SC_R_GPU_3_PID0 50 +#define IMX_SC_R_DC_1_PLL_0 51 +#define IMX_SC_R_DC_1_PLL_1 52 +#define IMX_SC_R_SPI_0 53 +#define IMX_SC_R_SPI_1 54 +#define IMX_SC_R_SPI_2 55 +#define IMX_SC_R_SPI_3 56 +#define IMX_SC_R_UART_0 57 +#define IMX_SC_R_UART_1 58 +#define IMX_SC_R_UART_2 59 +#define IMX_SC_R_UART_3 60 +#define IMX_SC_R_UART_4 61 +#define IMX_SC_R_EMVSIM_0 62 +#define IMX_SC_R_EMVSIM_1 63 +#define IMX_SC_R_DMA_0_CH0 64 +#define IMX_SC_R_DMA_0_CH1 65 +#define IMX_SC_R_DMA_0_CH2 66 +#define IMX_SC_R_DMA_0_CH3 67 +#define IMX_SC_R_DMA_0_CH4 68 +#define IMX_SC_R_DMA_0_CH5 69 +#define IMX_SC_R_DMA_0_CH6 70 +#define IMX_SC_R_DMA_0_CH7 71 +#define IMX_SC_R_DMA_0_CH8 72 +#define IMX_SC_R_DMA_0_CH9 73 +#define IMX_SC_R_DMA_0_CH10 74 +#define IMX_SC_R_DMA_0_CH11 75 +#define IMX_SC_R_DMA_0_CH12 76 +#define IMX_SC_R_DMA_0_CH13 77 +#define IMX_SC_R_DMA_0_CH14 78 +#define IMX_SC_R_DMA_0_CH15 79 +#define IMX_SC_R_DMA_0_CH16 80 +#define IMX_SC_R_DMA_0_CH17 81 +#define IMX_SC_R_DMA_0_CH18 82 +#define IMX_SC_R_DMA_0_CH19 83 +#define IMX_SC_R_DMA_0_CH20 84 +#define IMX_SC_R_DMA_0_CH21 85 +#define IMX_SC_R_DMA_0_CH22 86 +#define IMX_SC_R_DMA_0_CH23 87 +#define IMX_SC_R_DMA_0_CH24 88 +#define IMX_SC_R_DMA_0_CH25 89 +#define IMX_SC_R_DMA_0_CH26 90 +#define IMX_SC_R_DMA_0_CH27 91 +#define IMX_SC_R_DMA_0_CH28 92 +#define IMX_SC_R_DMA_0_CH29 93 +#define IMX_SC_R_DMA_0_CH30 94 +#define IMX_SC_R_DMA_0_CH31 95 +#define IMX_SC_R_I2C_0 96 +#define IMX_SC_R_I2C_1 97 +#define IMX_SC_R_I2C_2 98 +#define IMX_SC_R_I2C_3 99 +#define IMX_SC_R_I2C_4 100 +#define IMX_SC_R_ADC_0 101 +#define IMX_SC_R_ADC_1 102 +#define IMX_SC_R_FTM_0 103 +#define IMX_SC_R_FTM_1 104 +#define IMX_SC_R_CAN_0 105 +#define IMX_SC_R_CAN_1 106 +#define IMX_SC_R_CAN_2 107 +#define IMX_SC_R_DMA_1_CH0 108 +#define IMX_SC_R_DMA_1_CH1 109 +#define IMX_SC_R_DMA_1_CH2 110 +#define IMX_SC_R_DMA_1_CH3 111 +#define IMX_SC_R_DMA_1_CH4 112 +#define IMX_SC_R_DMA_1_CH5 113 +#define IMX_SC_R_DMA_1_CH6 114 +#define IMX_SC_R_DMA_1_CH7 115 +#define IMX_SC_R_DMA_1_CH8 116 +#define IMX_SC_R_DMA_1_CH9 117 +#define IMX_SC_R_DMA_1_CH10 118 +#define IMX_SC_R_DMA_1_CH11 119 +#define IMX_SC_R_DMA_1_CH12 120 +#define IMX_SC_R_DMA_1_CH13 121 +#define IMX_SC_R_DMA_1_CH14 122 +#define IMX_SC_R_DMA_1_CH15 123 +#define IMX_SC_R_DMA_1_CH16 124 +#define IMX_SC_R_DMA_1_CH17 125 +#define IMX_SC_R_DMA_1_CH18 126 +#define IMX_SC_R_DMA_1_CH19 127 +#define IMX_SC_R_DMA_1_CH20 128 +#define IMX_SC_R_DMA_1_CH21 129 +#define IMX_SC_R_DMA_1_CH22 130 +#define IMX_SC_R_DMA_1_CH23 131 +#define IMX_SC_R_DMA_1_CH24 132 +#define IMX_SC_R_DMA_1_CH25 133 +#define IMX_SC_R_DMA_1_CH26 134 +#define IMX_SC_R_DMA_1_CH27 135 +#define IMX_SC_R_DMA_1_CH28 136 +#define IMX_SC_R_DMA_1_CH29 137 +#define IMX_SC_R_DMA_1_CH30 138 +#define IMX_SC_R_DMA_1_CH31 139 +#define IMX_SC_R_UNUSED1 140 +#define IMX_SC_R_UNUSED2 141 +#define IMX_SC_R_UNUSED3 142 +#define IMX_SC_R_UNUSED4 143 +#define IMX_SC_R_GPU_0_PID0 144 +#define IMX_SC_R_GPU_0_PID1 145 +#define IMX_SC_R_GPU_0_PID2 146 +#define IMX_SC_R_GPU_0_PID3 147 +#define IMX_SC_R_GPU_1_PID0 148 +#define IMX_SC_R_GPU_1_PID1 149 +#define IMX_SC_R_GPU_1_PID2 150 +#define IMX_SC_R_GPU_1_PID3 151 +#define IMX_SC_R_PCIE_A 152 +#define IMX_SC_R_SERDES_0 153 +#define IMX_SC_R_MATCH_0 154 +#define IMX_SC_R_MATCH_1 155 +#define IMX_SC_R_MATCH_2 156 +#define IMX_SC_R_MATCH_3 157 +#define IMX_SC_R_MATCH_4 158 +#define IMX_SC_R_MATCH_5 159 +#define IMX_SC_R_MATCH_6 160 +#define IMX_SC_R_MATCH_7 161 +#define IMX_SC_R_MATCH_8 162 +#define IMX_SC_R_MATCH_9 163 +#define IMX_SC_R_MATCH_10 164 +#define IMX_SC_R_MATCH_11 165 +#define IMX_SC_R_MATCH_12 166 +#define IMX_SC_R_MATCH_13 167 +#define IMX_SC_R_MATCH_14 168 +#define IMX_SC_R_PCIE_B 169 +#define IMX_SC_R_SATA_0 170 +#define IMX_SC_R_SERDES_1 171 +#define IMX_SC_R_HSIO_GPIO 172 +#define IMX_SC_R_MATCH_15 173 +#define IMX_SC_R_MATCH_16 174 +#define IMX_SC_R_MATCH_17 175 +#define IMX_SC_R_MATCH_18 176 +#define IMX_SC_R_MATCH_19 177 +#define IMX_SC_R_MATCH_20 178 +#define IMX_SC_R_MATCH_21 179 +#define IMX_SC_R_MATCH_22 180 +#define IMX_SC_R_MATCH_23 181 +#define IMX_SC_R_MATCH_24 182 +#define IMX_SC_R_MATCH_25 183 +#define IMX_SC_R_MATCH_26 184 +#define IMX_SC_R_MATCH_27 185 +#define IMX_SC_R_MATCH_28 186 +#define IMX_SC_R_LCD_0 187 +#define IMX_SC_R_LCD_0_PWM_0 188 +#define IMX_SC_R_LCD_0_I2C_0 189 +#define IMX_SC_R_LCD_0_I2C_1 190 +#define IMX_SC_R_PWM_0 191 +#define IMX_SC_R_PWM_1 192 +#define IMX_SC_R_PWM_2 193 +#define IMX_SC_R_PWM_3 194 +#define IMX_SC_R_PWM_4 195 +#define IMX_SC_R_PWM_5 196 +#define IMX_SC_R_PWM_6 197 +#define IMX_SC_R_PWM_7 198 +#define IMX_SC_R_GPIO_0 199 +#define IMX_SC_R_GPIO_1 200 +#define IMX_SC_R_GPIO_2 201 +#define IMX_SC_R_GPIO_3 202 +#define IMX_SC_R_GPIO_4 203 +#define IMX_SC_R_GPIO_5 204 +#define IMX_SC_R_GPIO_6 205 +#define IMX_SC_R_GPIO_7 206 +#define IMX_SC_R_GPT_0 207 +#define IMX_SC_R_GPT_1 208 +#define IMX_SC_R_GPT_2 209 +#define IMX_SC_R_GPT_3 210 +#define IMX_SC_R_GPT_4 211 +#define IMX_SC_R_KPP 212 +#define IMX_SC_R_MU_0A 213 +#define IMX_SC_R_MU_1A 214 +#define IMX_SC_R_MU_2A 215 +#define IMX_SC_R_MU_3A 216 +#define IMX_SC_R_MU_4A 217 +#define IMX_SC_R_MU_5A 218 +#define IMX_SC_R_MU_6A 219 +#define IMX_SC_R_MU_7A 220 +#define IMX_SC_R_MU_8A 221 +#define IMX_SC_R_MU_9A 222 +#define IMX_SC_R_MU_10A 223 +#define IMX_SC_R_MU_11A 224 +#define IMX_SC_R_MU_12A 225 +#define IMX_SC_R_MU_13A 226 +#define IMX_SC_R_MU_5B 227 +#define IMX_SC_R_MU_6B 228 +#define IMX_SC_R_MU_7B 229 +#define IMX_SC_R_MU_8B 230 +#define IMX_SC_R_MU_9B 231 +#define IMX_SC_R_MU_10B 232 +#define IMX_SC_R_MU_11B 233 +#define IMX_SC_R_MU_12B 234 +#define IMX_SC_R_MU_13B 235 +#define IMX_SC_R_ROM_0 236 +#define IMX_SC_R_FSPI_0 237 +#define IMX_SC_R_FSPI_1 238 +#define IMX_SC_R_IEE 239 +#define IMX_SC_R_IEE_R0 240 +#define IMX_SC_R_IEE_R1 241 +#define IMX_SC_R_IEE_R2 242 +#define IMX_SC_R_IEE_R3 243 +#define IMX_SC_R_IEE_R4 244 +#define IMX_SC_R_IEE_R5 245 +#define IMX_SC_R_IEE_R6 246 +#define IMX_SC_R_IEE_R7 247 +#define IMX_SC_R_SDHC_0 248 +#define IMX_SC_R_SDHC_1 249 +#define IMX_SC_R_SDHC_2 250 +#define IMX_SC_R_ENET_0 251 +#define IMX_SC_R_ENET_1 252 +#define IMX_SC_R_MLB_0 253 +#define IMX_SC_R_DMA_2_CH0 254 +#define IMX_SC_R_DMA_2_CH1 255 +#define IMX_SC_R_DMA_2_CH2 256 +#define IMX_SC_R_DMA_2_CH3 257 +#define IMX_SC_R_DMA_2_CH4 258 +#define IMX_SC_R_USB_0 259 +#define IMX_SC_R_USB_1 260 +#define IMX_SC_R_USB_0_PHY 261 +#define IMX_SC_R_USB_2 262 +#define IMX_SC_R_USB_2_PHY 263 +#define IMX_SC_R_DTCP 264 +#define IMX_SC_R_NAND 265 +#define IMX_SC_R_LVDS_0 266 +#define IMX_SC_R_LVDS_0_PWM_0 267 +#define IMX_SC_R_LVDS_0_I2C_0 268 +#define IMX_SC_R_LVDS_0_I2C_1 269 +#define IMX_SC_R_LVDS_1 270 +#define IMX_SC_R_LVDS_1_PWM_0 271 +#define IMX_SC_R_LVDS_1_I2C_0 272 +#define IMX_SC_R_LVDS_1_I2C_1 273 +#define IMX_SC_R_LVDS_2 274 +#define IMX_SC_R_LVDS_2_PWM_0 275 +#define IMX_SC_R_LVDS_2_I2C_0 276 +#define IMX_SC_R_LVDS_2_I2C_1 277 +#define IMX_SC_R_M4_0_PID0 278 +#define IMX_SC_R_M4_0_PID1 279 +#define IMX_SC_R_M4_0_PID2 280 +#define IMX_SC_R_M4_0_PID3 281 +#define IMX_SC_R_M4_0_PID4 282 +#define IMX_SC_R_M4_0_RGPIO 283 +#define IMX_SC_R_M4_0_SEMA42 284 +#define IMX_SC_R_M4_0_TPM 285 +#define IMX_SC_R_M4_0_PIT 286 +#define IMX_SC_R_M4_0_UART 287 +#define IMX_SC_R_M4_0_I2C 288 +#define IMX_SC_R_M4_0_INTMUX 289 +#define IMX_SC_R_M4_0_SIM 290 +#define IMX_SC_R_M4_0_WDOG 291 +#define IMX_SC_R_M4_0_MU_0B 292 +#define IMX_SC_R_M4_0_MU_0A0 293 +#define IMX_SC_R_M4_0_MU_0A1 294 +#define IMX_SC_R_M4_0_MU_0A2 295 +#define IMX_SC_R_M4_0_MU_0A3 296 +#define IMX_SC_R_M4_0_MU_1A 297 +#define IMX_SC_R_M4_1_PID0 298 +#define IMX_SC_R_M4_1_PID1 299 +#define IMX_SC_R_M4_1_PID2 300 +#define IMX_SC_R_M4_1_PID3 301 +#define IMX_SC_R_M4_1_PID4 302 +#define IMX_SC_R_M4_1_RGPIO 303 +#define IMX_SC_R_M4_1_SEMA42 304 +#define IMX_SC_R_M4_1_TPM 305 +#define IMX_SC_R_M4_1_PIT 306 +#define IMX_SC_R_M4_1_UART 307 +#define IMX_SC_R_M4_1_I2C 308 +#define IMX_SC_R_M4_1_INTMUX 309 +#define IMX_SC_R_M4_1_SIM 310 +#define IMX_SC_R_M4_1_WDOG 311 +#define IMX_SC_R_M4_1_MU_0B 312 +#define IMX_SC_R_M4_1_MU_0A0 313 +#define IMX_SC_R_M4_1_MU_0A1 314 +#define IMX_SC_R_M4_1_MU_0A2 315 +#define IMX_SC_R_M4_1_MU_0A3 316 +#define IMX_SC_R_M4_1_MU_1A 317 +#define IMX_SC_R_SAI_0 318 +#define IMX_SC_R_SAI_1 319 +#define IMX_SC_R_SAI_2 320 +#define IMX_SC_R_IRQSTR_SCU2 321 +#define IMX_SC_R_IRQSTR_DSP 322 +#define IMX_SC_R_ELCDIF_PLL 323 +#define IMX_SC_R_UNUSED6 324 +#define IMX_SC_R_AUDIO_PLL_0 325 +#define IMX_SC_R_PI_0 326 +#define IMX_SC_R_PI_0_PWM_0 327 +#define IMX_SC_R_PI_0_PWM_1 328 +#define IMX_SC_R_PI_0_I2C_0 329 +#define IMX_SC_R_PI_0_PLL 330 +#define IMX_SC_R_PI_1 331 +#define IMX_SC_R_PI_1_PWM_0 332 +#define IMX_SC_R_PI_1_PWM_1 333 +#define IMX_SC_R_PI_1_I2C_0 334 +#define IMX_SC_R_PI_1_PLL 335 +#define IMX_SC_R_SC_PID0 336 +#define IMX_SC_R_SC_PID1 337 +#define IMX_SC_R_SC_PID2 338 +#define IMX_SC_R_SC_PID3 339 +#define IMX_SC_R_SC_PID4 340 +#define IMX_SC_R_SC_SEMA42 341 +#define IMX_SC_R_SC_TPM 342 +#define IMX_SC_R_SC_PIT 343 +#define IMX_SC_R_SC_UART 344 +#define IMX_SC_R_SC_I2C 345 +#define IMX_SC_R_SC_MU_0B 346 +#define IMX_SC_R_SC_MU_0A0 347 +#define IMX_SC_R_SC_MU_0A1 348 +#define IMX_SC_R_SC_MU_0A2 349 +#define IMX_SC_R_SC_MU_0A3 350 +#define IMX_SC_R_SC_MU_1A 351 +#define IMX_SC_R_SYSCNT_RD 352 +#define IMX_SC_R_SYSCNT_CMP 353 +#define IMX_SC_R_DEBUG 354 +#define IMX_SC_R_SYSTEM 355 +#define IMX_SC_R_SNVS 356 +#define IMX_SC_R_OTP 357 +#define IMX_SC_R_VPU_PID0 358 +#define IMX_SC_R_VPU_PID1 359 +#define IMX_SC_R_VPU_PID2 360 +#define IMX_SC_R_VPU_PID3 361 +#define IMX_SC_R_VPU_PID4 362 +#define IMX_SC_R_VPU_PID5 363 +#define IMX_SC_R_VPU_PID6 364 +#define IMX_SC_R_VPU_PID7 365 +#define IMX_SC_R_VPU_UART 366 +#define IMX_SC_R_VPUCORE 367 +#define IMX_SC_R_VPUCORE_0 368 +#define IMX_SC_R_VPUCORE_1 369 +#define IMX_SC_R_VPUCORE_2 370 +#define IMX_SC_R_VPUCORE_3 371 +#define IMX_SC_R_DMA_4_CH0 372 +#define IMX_SC_R_DMA_4_CH1 373 +#define IMX_SC_R_DMA_4_CH2 374 +#define IMX_SC_R_DMA_4_CH3 375 +#define IMX_SC_R_DMA_4_CH4 376 +#define IMX_SC_R_ISI_CH0 377 +#define IMX_SC_R_ISI_CH1 378 +#define IMX_SC_R_ISI_CH2 379 +#define IMX_SC_R_ISI_CH3 380 +#define IMX_SC_R_ISI_CH4 381 +#define IMX_SC_R_ISI_CH5 382 +#define IMX_SC_R_ISI_CH6 383 +#define IMX_SC_R_ISI_CH7 384 +#define IMX_SC_R_MJPEG_DEC_S0 385 +#define IMX_SC_R_MJPEG_DEC_S1 386 +#define IMX_SC_R_MJPEG_DEC_S2 387 +#define IMX_SC_R_MJPEG_DEC_S3 388 +#define IMX_SC_R_MJPEG_ENC_S0 389 +#define IMX_SC_R_MJPEG_ENC_S1 390 +#define IMX_SC_R_MJPEG_ENC_S2 391 +#define IMX_SC_R_MJPEG_ENC_S3 392 +#define IMX_SC_R_MIPI_0 393 +#define IMX_SC_R_MIPI_0_PWM_0 394 +#define IMX_SC_R_MIPI_0_I2C_0 395 +#define IMX_SC_R_MIPI_0_I2C_1 396 +#define IMX_SC_R_MIPI_1 397 +#define IMX_SC_R_MIPI_1_PWM_0 398 +#define IMX_SC_R_MIPI_1_I2C_0 399 +#define IMX_SC_R_MIPI_1_I2C_1 400 +#define IMX_SC_R_CSI_0 401 +#define IMX_SC_R_CSI_0_PWM_0 402 +#define IMX_SC_R_CSI_0_I2C_0 403 +#define IMX_SC_R_CSI_1 404 +#define IMX_SC_R_CSI_1_PWM_0 405 +#define IMX_SC_R_CSI_1_I2C_0 406 +#define IMX_SC_R_HDMI 407 +#define IMX_SC_R_HDMI_I2S 408 +#define IMX_SC_R_HDMI_I2C_0 409 +#define IMX_SC_R_HDMI_PLL_0 410 +#define IMX_SC_R_HDMI_RX 411 +#define IMX_SC_R_HDMI_RX_BYPASS 412 +#define IMX_SC_R_HDMI_RX_I2C_0 413 +#define IMX_SC_R_ASRC_0 414 +#define IMX_SC_R_ESAI_0 415 +#define IMX_SC_R_SPDIF_0 416 +#define IMX_SC_R_SPDIF_1 417 +#define IMX_SC_R_SAI_3 418 +#define IMX_SC_R_SAI_4 419 +#define IMX_SC_R_SAI_5 420 +#define IMX_SC_R_GPT_5 421 +#define IMX_SC_R_GPT_6 422 +#define IMX_SC_R_GPT_7 423 +#define IMX_SC_R_GPT_8 424 +#define IMX_SC_R_GPT_9 425 +#define IMX_SC_R_GPT_10 426 +#define IMX_SC_R_DMA_2_CH5 427 +#define IMX_SC_R_DMA_2_CH6 428 +#define IMX_SC_R_DMA_2_CH7 429 +#define IMX_SC_R_DMA_2_CH8 430 +#define IMX_SC_R_DMA_2_CH9 431 +#define IMX_SC_R_DMA_2_CH10 432 +#define IMX_SC_R_DMA_2_CH11 433 +#define IMX_SC_R_DMA_2_CH12 434 +#define IMX_SC_R_DMA_2_CH13 435 +#define IMX_SC_R_DMA_2_CH14 436 +#define IMX_SC_R_DMA_2_CH15 437 +#define IMX_SC_R_DMA_2_CH16 438 +#define IMX_SC_R_DMA_2_CH17 439 +#define IMX_SC_R_DMA_2_CH18 440 +#define IMX_SC_R_DMA_2_CH19 441 +#define IMX_SC_R_DMA_2_CH20 442 +#define IMX_SC_R_DMA_2_CH21 443 +#define IMX_SC_R_DMA_2_CH22 444 +#define IMX_SC_R_DMA_2_CH23 445 +#define IMX_SC_R_DMA_2_CH24 446 +#define IMX_SC_R_DMA_2_CH25 447 +#define IMX_SC_R_DMA_2_CH26 448 +#define IMX_SC_R_DMA_2_CH27 449 +#define IMX_SC_R_DMA_2_CH28 450 +#define IMX_SC_R_DMA_2_CH29 451 +#define IMX_SC_R_DMA_2_CH30 452 +#define IMX_SC_R_DMA_2_CH31 453 +#define IMX_SC_R_ASRC_1 454 +#define IMX_SC_R_ESAI_1 455 +#define IMX_SC_R_SAI_6 456 +#define IMX_SC_R_SAI_7 457 +#define IMX_SC_R_AMIX 458 +#define IMX_SC_R_MQS_0 459 +#define IMX_SC_R_DMA_3_CH0 460 +#define IMX_SC_R_DMA_3_CH1 461 +#define IMX_SC_R_DMA_3_CH2 462 +#define IMX_SC_R_DMA_3_CH3 463 +#define IMX_SC_R_DMA_3_CH4 464 +#define IMX_SC_R_DMA_3_CH5 465 +#define IMX_SC_R_DMA_3_CH6 466 +#define IMX_SC_R_DMA_3_CH7 467 +#define IMX_SC_R_DMA_3_CH8 468 +#define IMX_SC_R_DMA_3_CH9 469 +#define IMX_SC_R_DMA_3_CH10 470 +#define IMX_SC_R_DMA_3_CH11 471 +#define IMX_SC_R_DMA_3_CH12 472 +#define IMX_SC_R_DMA_3_CH13 473 +#define IMX_SC_R_DMA_3_CH14 474 +#define IMX_SC_R_DMA_3_CH15 475 +#define IMX_SC_R_DMA_3_CH16 476 +#define IMX_SC_R_DMA_3_CH17 477 +#define IMX_SC_R_DMA_3_CH18 478 +#define IMX_SC_R_DMA_3_CH19 479 +#define IMX_SC_R_DMA_3_CH20 480 +#define IMX_SC_R_DMA_3_CH21 481 +#define IMX_SC_R_DMA_3_CH22 482 +#define IMX_SC_R_DMA_3_CH23 483 +#define IMX_SC_R_DMA_3_CH24 484 +#define IMX_SC_R_DMA_3_CH25 485 +#define IMX_SC_R_DMA_3_CH26 486 +#define IMX_SC_R_DMA_3_CH27 487 +#define IMX_SC_R_DMA_3_CH28 488 +#define IMX_SC_R_DMA_3_CH29 489 +#define IMX_SC_R_DMA_3_CH30 490 +#define IMX_SC_R_DMA_3_CH31 491 +#define IMX_SC_R_AUDIO_PLL_1 492 +#define IMX_SC_R_AUDIO_CLK_0 493 +#define IMX_SC_R_AUDIO_CLK_1 494 +#define IMX_SC_R_MCLK_OUT_0 495 +#define IMX_SC_R_MCLK_OUT_1 496 +#define IMX_SC_R_PMIC_0 497 +#define IMX_SC_R_PMIC_1 498 +#define IMX_SC_R_SECO 499 +#define IMX_SC_R_CAAM_JR1 500 +#define IMX_SC_R_CAAM_JR2 501 +#define IMX_SC_R_CAAM_JR3 502 +#define IMX_SC_R_SECO_MU_2 503 +#define IMX_SC_R_SECO_MU_3 504 +#define IMX_SC_R_SECO_MU_4 505 +#define IMX_SC_R_HDMI_RX_PWM_0 506 +#define IMX_SC_R_A35 507 +#define IMX_SC_R_A35_0 508 +#define IMX_SC_R_A35_1 509 +#define IMX_SC_R_A35_2 510 +#define IMX_SC_R_A35_3 511 +#define IMX_SC_R_DSP 512 +#define IMX_SC_R_DSP_RAM 513 +#define IMX_SC_R_CAAM_JR1_OUT 514 +#define IMX_SC_R_CAAM_JR2_OUT 515 +#define IMX_SC_R_CAAM_JR3_OUT 516 +#define IMX_SC_R_VPU_DEC_0 517 +#define IMX_SC_R_VPU_ENC_0 518 +#define IMX_SC_R_CAAM_JR0 519 +#define IMX_SC_R_CAAM_JR0_OUT 520 +#define IMX_SC_R_PMIC_2 521 +#define IMX_SC_R_DBLOGIC 522 +#define IMX_SC_R_HDMI_PLL_1 523 +#define IMX_SC_R_BOARD_R0 524 +#define IMX_SC_R_BOARD_R1 525 +#define IMX_SC_R_BOARD_R2 526 +#define IMX_SC_R_BOARD_R3 527 +#define IMX_SC_R_BOARD_R4 528 +#define IMX_SC_R_BOARD_R5 529 +#define IMX_SC_R_BOARD_R6 530 +#define IMX_SC_R_BOARD_R7 531 +#define IMX_SC_R_MJPEG_DEC_MP 532 +#define IMX_SC_R_MJPEG_ENC_MP 533 +#define IMX_SC_R_VPU_TS_0 534 +#define IMX_SC_R_VPU_MU_0 535 +#define IMX_SC_R_VPU_MU_1 536 +#define IMX_SC_R_VPU_MU_2 537 +#define IMX_SC_R_VPU_MU_3 538 +#define IMX_SC_R_VPU_ENC_1 539 +#define IMX_SC_R_VPU 540 +#define IMX_SC_R_LAST 541 + +#endif /* __DT_BINDINGS_RSCRC_IMX_H */ diff --git a/include/dt-bindings/gce/mt8173-gce.h b/include/dt-bindings/gce/mt8173-gce.h new file mode 100644 index 000000000000..ffcf94ba96c6 --- /dev/null +++ b/include/dt-bindings/gce/mt8173-gce.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018 MediaTek Inc. + * Author: Houlong Wei <houlong.wei@mediatek.com> + * + */ + +#ifndef _DT_BINDINGS_GCE_MT8173_H +#define _DT_BINDINGS_GCE_MT8173_H + +/* GCE HW thread priority */ +#define CMDQ_THR_PRIO_LOWEST 0 +#define CMDQ_THR_PRIO_HIGHEST 1 + +/* GCE SUBSYS */ +#define SUBSYS_1400XXXX 1 +#define SUBSYS_1401XXXX 2 +#define SUBSYS_1402XXXX 3 + +/* GCE HW EVENT */ +#define CMDQ_EVENT_DISP_OVL0_SOF 11 +#define CMDQ_EVENT_DISP_OVL1_SOF 12 +#define CMDQ_EVENT_DISP_RDMA0_SOF 13 +#define CMDQ_EVENT_DISP_RDMA1_SOF 14 +#define CMDQ_EVENT_DISP_RDMA2_SOF 15 +#define CMDQ_EVENT_DISP_WDMA0_SOF 16 +#define CMDQ_EVENT_DISP_WDMA1_SOF 17 +#define CMDQ_EVENT_DISP_OVL0_EOF 39 +#define CMDQ_EVENT_DISP_OVL1_EOF 40 +#define CMDQ_EVENT_DISP_RDMA0_EOF 41 +#define CMDQ_EVENT_DISP_RDMA1_EOF 42 +#define CMDQ_EVENT_DISP_RDMA2_EOF 43 +#define CMDQ_EVENT_DISP_WDMA0_EOF 44 +#define CMDQ_EVENT_DISP_WDMA1_EOF 45 +#define CMDQ_EVENT_MUTEX0_STREAM_EOF 53 +#define CMDQ_EVENT_MUTEX1_STREAM_EOF 54 +#define CMDQ_EVENT_MUTEX2_STREAM_EOF 55 +#define CMDQ_EVENT_MUTEX3_STREAM_EOF 56 +#define CMDQ_EVENT_MUTEX4_STREAM_EOF 57 +#define CMDQ_EVENT_DISP_RDMA0_UNDERRUN 63 +#define CMDQ_EVENT_DISP_RDMA1_UNDERRUN 64 +#define CMDQ_EVENT_DISP_RDMA2_UNDERRUN 65 + +#endif diff --git a/include/dt-bindings/gpio/meson-g12a-gpio.h b/include/dt-bindings/gpio/meson-g12a-gpio.h new file mode 100644 index 000000000000..f7bd69350d18 --- /dev/null +++ b/include/dt-bindings/gpio/meson-g12a-gpio.h @@ -0,0 +1,114 @@ +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* + * Copyright (c) 2018 Amlogic, Inc. All rights reserved. + * Author: Xingyu Chen <xingyu.chen@amlogic.com> + */ + +#ifndef _DT_BINDINGS_MESON_G12A_GPIO_H +#define _DT_BINDINGS_MESON_G12A_GPIO_H + +/* First GPIO chip */ +#define GPIOAO_0 0 +#define GPIOAO_1 1 +#define GPIOAO_2 2 +#define GPIOAO_3 3 +#define GPIOAO_4 4 +#define GPIOAO_5 5 +#define GPIOAO_6 6 +#define GPIOAO_7 7 +#define GPIOAO_8 8 +#define GPIOAO_9 9 +#define GPIOAO_10 10 +#define GPIOAO_11 11 +#define GPIOE_0 12 +#define GPIOE_1 13 +#define GPIOE_2 14 + +/* Second GPIO chip */ +#define GPIOZ_0 0 +#define GPIOZ_1 1 +#define GPIOZ_2 2 +#define GPIOZ_3 3 +#define GPIOZ_4 4 +#define GPIOZ_5 5 +#define GPIOZ_6 6 +#define GPIOZ_7 7 +#define GPIOZ_8 8 +#define GPIOZ_9 9 +#define GPIOZ_10 10 +#define GPIOZ_11 11 +#define GPIOZ_12 12 +#define GPIOZ_13 13 +#define GPIOZ_14 14 +#define GPIOZ_15 15 +#define GPIOH_0 16 +#define GPIOH_1 17 +#define GPIOH_2 18 +#define GPIOH_3 19 +#define GPIOH_4 20 +#define GPIOH_5 21 +#define GPIOH_6 22 +#define GPIOH_7 23 +#define GPIOH_8 24 +#define BOOT_0 25 +#define BOOT_1 26 +#define BOOT_2 27 +#define BOOT_3 28 +#define BOOT_4 29 +#define BOOT_5 30 +#define BOOT_6 31 +#define BOOT_7 32 +#define BOOT_8 33 +#define BOOT_9 34 +#define BOOT_10 35 +#define BOOT_11 36 +#define BOOT_12 37 +#define BOOT_13 38 +#define BOOT_14 39 +#define BOOT_15 40 +#define GPIOC_0 41 +#define GPIOC_1 42 +#define GPIOC_2 43 +#define GPIOC_3 44 +#define GPIOC_4 45 +#define GPIOC_5 46 +#define GPIOC_6 47 +#define GPIOC_7 48 +#define GPIOA_0 49 +#define GPIOA_1 50 +#define GPIOA_2 51 +#define GPIOA_3 52 +#define GPIOA_4 53 +#define GPIOA_5 54 +#define GPIOA_6 55 +#define GPIOA_7 56 +#define GPIOA_8 57 +#define GPIOA_9 58 +#define GPIOA_10 59 +#define GPIOA_11 60 +#define GPIOA_12 61 +#define GPIOA_13 62 +#define GPIOA_14 63 +#define GPIOA_15 64 +#define GPIOX_0 65 +#define GPIOX_1 66 +#define GPIOX_2 67 +#define GPIOX_3 68 +#define GPIOX_4 69 +#define GPIOX_5 70 +#define GPIOX_6 71 +#define GPIOX_7 72 +#define GPIOX_8 73 +#define GPIOX_9 74 +#define GPIOX_10 75 +#define GPIOX_11 76 +#define GPIOX_12 77 +#define GPIOX_13 78 +#define GPIOX_14 79 +#define GPIOX_15 80 +#define GPIOX_16 81 +#define GPIOX_17 82 +#define GPIOX_18 83 +#define GPIOX_19 84 + +#endif /* _DT_BINDINGS_MESON_G12A_GPIO_H */ diff --git a/include/dt-bindings/gpio/tegra186-gpio.h b/include/dt-bindings/gpio/tegra186-gpio.h index 463ad398fe3e..cabc5712e745 100644 --- a/include/dt-bindings/gpio/tegra186-gpio.h +++ b/include/dt-bindings/gpio/tegra186-gpio.h @@ -14,6 +14,34 @@ #include <dt-bindings/gpio/gpio.h> /* GPIOs implemented by main GPIO controller */ +#define TEGRA186_MAIN_GPIO_PORT_A 0 +#define TEGRA186_MAIN_GPIO_PORT_B 1 +#define TEGRA186_MAIN_GPIO_PORT_C 2 +#define TEGRA186_MAIN_GPIO_PORT_D 3 +#define TEGRA186_MAIN_GPIO_PORT_E 4 +#define TEGRA186_MAIN_GPIO_PORT_F 5 +#define TEGRA186_MAIN_GPIO_PORT_G 6 +#define TEGRA186_MAIN_GPIO_PORT_H 7 +#define TEGRA186_MAIN_GPIO_PORT_I 8 +#define TEGRA186_MAIN_GPIO_PORT_J 9 +#define TEGRA186_MAIN_GPIO_PORT_K 10 +#define TEGRA186_MAIN_GPIO_PORT_L 11 +#define TEGRA186_MAIN_GPIO_PORT_M 12 +#define TEGRA186_MAIN_GPIO_PORT_N 13 +#define TEGRA186_MAIN_GPIO_PORT_O 14 +#define TEGRA186_MAIN_GPIO_PORT_P 15 +#define TEGRA186_MAIN_GPIO_PORT_Q 16 +#define TEGRA186_MAIN_GPIO_PORT_R 17 +#define TEGRA186_MAIN_GPIO_PORT_T 18 +#define TEGRA186_MAIN_GPIO_PORT_X 19 +#define TEGRA186_MAIN_GPIO_PORT_Y 20 +#define TEGRA186_MAIN_GPIO_PORT_BB 21 +#define TEGRA186_MAIN_GPIO_PORT_CC 22 + +#define TEGRA186_MAIN_GPIO(port, offset) \ + ((TEGRA186_MAIN_GPIO_PORT_##port * 8) + offset) + +/* need to keep these for backwards-compatibility */ #define TEGRA_MAIN_GPIO_PORT_A 0 #define TEGRA_MAIN_GPIO_PORT_B 1 #define TEGRA_MAIN_GPIO_PORT_C 2 @@ -42,6 +70,19 @@ ((TEGRA_MAIN_GPIO_PORT_##port * 8) + offset) /* GPIOs implemented by AON GPIO controller */ +#define TEGRA186_AON_GPIO_PORT_S 0 +#define TEGRA186_AON_GPIO_PORT_U 1 +#define TEGRA186_AON_GPIO_PORT_V 2 +#define TEGRA186_AON_GPIO_PORT_W 3 +#define TEGRA186_AON_GPIO_PORT_Z 4 +#define TEGRA186_AON_GPIO_PORT_AA 5 +#define TEGRA186_AON_GPIO_PORT_EE 6 +#define TEGRA186_AON_GPIO_PORT_FF 7 + +#define TEGRA186_AON_GPIO(port, offset) \ + ((TEGRA186_AON_GPIO_PORT_##port * 8) + offset) + +/* need to keep these for backwards-compatibility */ #define TEGRA_AON_GPIO_PORT_S 0 #define TEGRA_AON_GPIO_PORT_U 1 #define TEGRA_AON_GPIO_PORT_V 2 diff --git a/include/dt-bindings/iio/adc/at91-sama5d2_adc.h b/include/dt-bindings/iio/adc/at91-sama5d2_adc.h new file mode 100644 index 000000000000..70f99dbdbb42 --- /dev/null +++ b/include/dt-bindings/iio/adc/at91-sama5d2_adc.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides constants for configuring the AT91 SAMA5D2 ADC + */ + +#ifndef _DT_BINDINGS_IIO_ADC_AT91_SAMA5D2_ADC_H +#define _DT_BINDINGS_IIO_ADC_AT91_SAMA5D2_ADC_H + +/* X relative position channel index */ +#define AT91_SAMA5D2_ADC_X_CHANNEL 24 +/* Y relative position channel index */ +#define AT91_SAMA5D2_ADC_Y_CHANNEL 25 +/* pressure channel index */ +#define AT91_SAMA5D2_ADC_P_CHANNEL 26 + +#endif diff --git a/include/dt-bindings/iio/qcom,spmi-vadc.h b/include/dt-bindings/iio/qcom,spmi-vadc.h index 42121fa238fa..61d556db1542 100644 --- a/include/dt-bindings/iio/qcom,spmi-vadc.h +++ b/include/dt-bindings/iio/qcom,spmi-vadc.h @@ -1,14 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (c) 2012-2014, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * Copyright (c) 2012-2014,2018 The Linux Foundation. All rights reserved. */ #ifndef _DT_BINDINGS_QCOM_SPMI_VADC_H @@ -116,4 +108,117 @@ #define VADC_LR_MUX10_PU1_PU2_AMUX_USB_ID 0xf9 #define VADC_LR_MUX3_BUF_PU1_PU2_XO_THERM 0xfc +/* ADC channels for SPMI PMIC5 */ + +#define ADC5_REF_GND 0x00 +#define ADC5_1P25VREF 0x01 +#define ADC5_VREF_VADC 0x02 +#define ADC5_VREF_VADC5_DIV_3 0x82 +#define ADC5_VPH_PWR 0x83 +#define ADC5_VBAT_SNS 0x84 +#define ADC5_VCOIN 0x85 +#define ADC5_DIE_TEMP 0x06 +#define ADC5_USB_IN_I 0x07 +#define ADC5_USB_IN_V_16 0x08 +#define ADC5_CHG_TEMP 0x09 +#define ADC5_BAT_THERM 0x0a +#define ADC5_BAT_ID 0x0b +#define ADC5_XO_THERM 0x0c +#define ADC5_AMUX_THM1 0x0d +#define ADC5_AMUX_THM2 0x0e +#define ADC5_AMUX_THM3 0x0f +#define ADC5_AMUX_THM4 0x10 +#define ADC5_AMUX_THM5 0x11 +#define ADC5_GPIO1 0x12 +#define ADC5_GPIO2 0x13 +#define ADC5_GPIO3 0x14 +#define ADC5_GPIO4 0x15 +#define ADC5_GPIO5 0x16 +#define ADC5_GPIO6 0x17 +#define ADC5_GPIO7 0x18 +#define ADC5_SBUx 0x99 +#define ADC5_MID_CHG_DIV6 0x1e +#define ADC5_OFF 0xff + +/* 30k pull-up1 */ +#define ADC5_BAT_THERM_30K_PU 0x2a +#define ADC5_BAT_ID_30K_PU 0x2b +#define ADC5_XO_THERM_30K_PU 0x2c +#define ADC5_AMUX_THM1_30K_PU 0x2d +#define ADC5_AMUX_THM2_30K_PU 0x2e +#define ADC5_AMUX_THM3_30K_PU 0x2f +#define ADC5_AMUX_THM4_30K_PU 0x30 +#define ADC5_AMUX_THM5_30K_PU 0x31 +#define ADC5_GPIO1_30K_PU 0x32 +#define ADC5_GPIO2_30K_PU 0x33 +#define ADC5_GPIO3_30K_PU 0x34 +#define ADC5_GPIO4_30K_PU 0x35 +#define ADC5_GPIO5_30K_PU 0x36 +#define ADC5_GPIO6_30K_PU 0x37 +#define ADC5_GPIO7_30K_PU 0x38 +#define ADC5_SBUx_30K_PU 0x39 + +/* 100k pull-up2 */ +#define ADC5_BAT_THERM_100K_PU 0x4a +#define ADC5_BAT_ID_100K_PU 0x4b +#define ADC5_XO_THERM_100K_PU 0x4c +#define ADC5_AMUX_THM1_100K_PU 0x4d +#define ADC5_AMUX_THM2_100K_PU 0x4e +#define ADC5_AMUX_THM3_100K_PU 0x4f +#define ADC5_AMUX_THM4_100K_PU 0x50 +#define ADC5_AMUX_THM5_100K_PU 0x51 +#define ADC5_GPIO1_100K_PU 0x52 +#define ADC5_GPIO2_100K_PU 0x53 +#define ADC5_GPIO3_100K_PU 0x54 +#define ADC5_GPIO4_100K_PU 0x55 +#define ADC5_GPIO5_100K_PU 0x56 +#define ADC5_GPIO6_100K_PU 0x57 +#define ADC5_GPIO7_100K_PU 0x58 +#define ADC5_SBUx_100K_PU 0x59 + +/* 400k pull-up3 */ +#define ADC5_BAT_THERM_400K_PU 0x6a +#define ADC5_BAT_ID_400K_PU 0x6b +#define ADC5_XO_THERM_400K_PU 0x6c +#define ADC5_AMUX_THM1_400K_PU 0x6d +#define ADC5_AMUX_THM2_400K_PU 0x6e +#define ADC5_AMUX_THM3_400K_PU 0x6f +#define ADC5_AMUX_THM4_400K_PU 0x70 +#define ADC5_AMUX_THM5_400K_PU 0x71 +#define ADC5_GPIO1_400K_PU 0x72 +#define ADC5_GPIO2_400K_PU 0x73 +#define ADC5_GPIO3_400K_PU 0x74 +#define ADC5_GPIO4_400K_PU 0x75 +#define ADC5_GPIO5_400K_PU 0x76 +#define ADC5_GPIO6_400K_PU 0x77 +#define ADC5_GPIO7_400K_PU 0x78 +#define ADC5_SBUx_400K_PU 0x79 + +/* 1/3 Divider */ +#define ADC5_GPIO1_DIV3 0x92 +#define ADC5_GPIO2_DIV3 0x93 +#define ADC5_GPIO3_DIV3 0x94 +#define ADC5_GPIO4_DIV3 0x95 +#define ADC5_GPIO5_DIV3 0x96 +#define ADC5_GPIO6_DIV3 0x97 +#define ADC5_GPIO7_DIV3 0x98 +#define ADC5_SBUx_DIV3 0x99 + +/* Current and combined current/voltage channels */ +#define ADC5_INT_EXT_ISENSE 0xa1 +#define ADC5_PARALLEL_ISENSE 0xa5 +#define ADC5_CUR_REPLICA_VDS 0xa7 +#define ADC5_CUR_SENS_BATFET_VDS_OFFSET 0xa9 +#define ADC5_CUR_SENS_REPLICA_VDS_OFFSET 0xab +#define ADC5_EXT_SENS_OFFSET 0xad + +#define ADC5_INT_EXT_ISENSE_VBAT_VDATA 0xb0 +#define ADC5_INT_EXT_ISENSE_VBAT_IDATA 0xb1 +#define ADC5_EXT_ISENSE_VBAT_VDATA 0xb2 +#define ADC5_EXT_ISENSE_VBAT_IDATA 0xb3 +#define ADC5_PARALLEL_ISENSE_VBAT_VDATA 0xb4 +#define ADC5_PARALLEL_ISENSE_VBAT_IDATA 0xb5 + +#define ADC5_MAX_CHANNEL 0xc0 + #endif /* _DT_BINDINGS_QCOM_SPMI_VADC_H */ diff --git a/include/dt-bindings/interrupt-controller/arm-gic.h b/include/dt-bindings/interrupt-controller/arm-gic.h index 0c85f65c81c7..35b6f69b7db6 100644 --- a/include/dt-bindings/interrupt-controller/arm-gic.h +++ b/include/dt-bindings/interrupt-controller/arm-gic.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ /* * This header provides constants for the ARM GIC. */ diff --git a/include/dt-bindings/interrupt-controller/irq.h b/include/dt-bindings/interrupt-controller/irq.h index a8b310555f14..9e3d183e1381 100644 --- a/include/dt-bindings/interrupt-controller/irq.h +++ b/include/dt-bindings/interrupt-controller/irq.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ /* * This header provides constants for most IRQ bindings. * diff --git a/include/dt-bindings/mailbox/tegra186-hsp.h b/include/dt-bindings/mailbox/tegra186-hsp.h index bcab5b7ca785..3bdec7a84d35 100644 --- a/include/dt-bindings/mailbox/tegra186-hsp.h +++ b/include/dt-bindings/mailbox/tegra186-hsp.h @@ -22,4 +22,15 @@ #define TEGRA_HSP_DB_MASTER_CCPLEX 17 #define TEGRA_HSP_DB_MASTER_BPMP 19 +/* + * Shared mailboxes are unidirectional, so the direction needs to be specified + * in the device tree. + */ +#define TEGRA_HSP_SM_MASK 0x00ffffff +#define TEGRA_HSP_SM_FLAG_RX (0 << 31) +#define TEGRA_HSP_SM_FLAG_TX (1 << 31) + +#define TEGRA_HSP_SM_RX(x) (TEGRA_HSP_SM_FLAG_RX | ((x) & TEGRA_HSP_SM_MASK)) +#define TEGRA_HSP_SM_TX(x) (TEGRA_HSP_SM_FLAG_TX | ((x) & TEGRA_HSP_SM_MASK)) + #endif diff --git a/include/dt-bindings/media/xilinx-vip.h b/include/dt-bindings/media/xilinx-vip.h index 6298fec00685..94ed3edfcc70 100644 --- a/include/dt-bindings/media/xilinx-vip.h +++ b/include/dt-bindings/media/xilinx-vip.h @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Xilinx Video IP Core * @@ -6,10 +7,6 @@ * * Contacts: Hyun Kwon <hyun.kwon@xilinx.com> * Laurent Pinchart <laurent.pinchart@ideasonboard.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #ifndef __DT_BINDINGS_MEDIA_XILINX_VIP_H__ diff --git a/include/dt-bindings/memory/mt2712-larb-port.h b/include/dt-bindings/memory/mt2712-larb-port.h new file mode 100644 index 000000000000..6f9aa7349cef --- /dev/null +++ b/include/dt-bindings/memory/mt2712-larb-port.h @@ -0,0 +1,95 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017 MediaTek Inc. + * Author: Yong Wu <yong.wu@mediatek.com> + */ +#ifndef __DTS_IOMMU_PORT_MT2712_H +#define __DTS_IOMMU_PORT_MT2712_H + +#define MTK_M4U_ID(larb, port) (((larb) << 5) | (port)) + +#define M4U_LARB0_ID 0 +#define M4U_LARB1_ID 1 +#define M4U_LARB2_ID 2 +#define M4U_LARB3_ID 3 +#define M4U_LARB4_ID 4 +#define M4U_LARB5_ID 5 +#define M4U_LARB6_ID 6 +#define M4U_LARB7_ID 7 +#define M4U_LARB8_ID 8 +#define M4U_LARB9_ID 9 + +/* larb0 */ +#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0) +#define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 1) +#define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 2) +#define M4U_PORT_DISP_OD_R MTK_M4U_ID(M4U_LARB0_ID, 3) +#define M4U_PORT_DISP_OD_W MTK_M4U_ID(M4U_LARB0_ID, 4) +#define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 5) +#define M4U_PORT_MDP_WDMA MTK_M4U_ID(M4U_LARB0_ID, 6) +#define M4U_PORT_DISP_RDMA2 MTK_M4U_ID(M4U_LARB0_ID, 7) + +/* larb1 */ +#define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(M4U_LARB1_ID, 0) +#define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(M4U_LARB1_ID, 1) +#define M4U_PORT_HW_VDEC_UFO_EXT MTK_M4U_ID(M4U_LARB1_ID, 2) +#define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB1_ID, 3) +#define M4U_PORT_HW_VDEC_VLD2_EXT MTK_M4U_ID(M4U_LARB1_ID, 4) +#define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB1_ID, 5) +#define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB1_ID, 6) +#define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB1_ID, 7) +#define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB1_ID, 8) +#define M4U_PORT_HW_VDEC_TILE MTK_M4U_ID(M4U_LARB1_ID, 9) +#define M4U_PORT_HW_IMG_RESZ_EXT MTK_M4U_ID(M4U_LARB1_ID, 10) + +/* larb2 */ +#define M4U_PORT_CAM_DMA0 MTK_M4U_ID(M4U_LARB2_ID, 0) +#define M4U_PORT_CAM_DMA1 MTK_M4U_ID(M4U_LARB2_ID, 1) +#define M4U_PORT_CAM_DMA2 MTK_M4U_ID(M4U_LARB2_ID, 2) + +/* larb3 */ +#define M4U_PORT_VENC_RCPU MTK_M4U_ID(M4U_LARB3_ID, 0) +#define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB3_ID, 1) +#define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 2) +#define M4U_PORT_VENC_SV_COMV MTK_M4U_ID(M4U_LARB3_ID, 3) +#define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB3_ID, 4) +#define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 5) +#define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 6) +#define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB3_ID, 7) +#define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB3_ID, 8) + +/* larb4 */ +#define M4U_PORT_DISP_OVL1 MTK_M4U_ID(M4U_LARB4_ID, 0) +#define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB4_ID, 1) +#define M4U_PORT_DISP_WDMA1 MTK_M4U_ID(M4U_LARB4_ID, 2) +#define M4U_PORT_DISP_OD1_R MTK_M4U_ID(M4U_LARB4_ID, 3) +#define M4U_PORT_DISP_OD1_W MTK_M4U_ID(M4U_LARB4_ID, 4) +#define M4U_PORT_MDP_RDMA1 MTK_M4U_ID(M4U_LARB4_ID, 5) +#define M4U_PORT_MDP_WROT1 MTK_M4U_ID(M4U_LARB4_ID, 6) + +/* larb5 */ +#define M4U_PORT_DISP_OVL2 MTK_M4U_ID(M4U_LARB5_ID, 0) +#define M4U_PORT_DISP_WDMA2 MTK_M4U_ID(M4U_LARB5_ID, 1) +#define M4U_PORT_MDP_RDMA2 MTK_M4U_ID(M4U_LARB5_ID, 2) +#define M4U_PORT_MDP_WROT0 MTK_M4U_ID(M4U_LARB5_ID, 3) + +/* larb6 */ +#define M4U_PORT_JPGDEC_WDMA_0 MTK_M4U_ID(M4U_LARB6_ID, 0) +#define M4U_PORT_JPGDEC_WDMA_1 MTK_M4U_ID(M4U_LARB6_ID, 1) +#define M4U_PORT_JPGDEC_BSDMA_0 MTK_M4U_ID(M4U_LARB6_ID, 2) +#define M4U_PORT_JPGDEC_BSDMA_1 MTK_M4U_ID(M4U_LARB6_ID, 3) + +/* larb7 */ +#define M4U_PORT_MDP_RDMA3 MTK_M4U_ID(M4U_LARB7_ID, 0) +#define M4U_PORT_MDP_WROT2 MTK_M4U_ID(M4U_LARB7_ID, 1) + +/* larb8 */ +#define M4U_PORT_VDO MTK_M4U_ID(M4U_LARB8_ID, 0) +#define M4U_PORT_NR MTK_M4U_ID(M4U_LARB8_ID, 1) +#define M4U_PORT_WR_CHANNEL0 MTK_M4U_ID(M4U_LARB8_ID, 2) + +/* larb9 */ +#define M4U_PORT_TVD MTK_M4U_ID(M4U_LARB9_ID, 0) +#define M4U_PORT_WR_CHANNEL1 MTK_M4U_ID(M4U_LARB9_ID, 1) + +#endif diff --git a/include/dt-bindings/memory/tegra114-mc.h b/include/dt-bindings/memory/tegra114-mc.h index 27c8386987ff..dfe99c8a5ba5 100644 --- a/include/dt-bindings/memory/tegra114-mc.h +++ b/include/dt-bindings/memory/tegra114-mc.h @@ -23,4 +23,21 @@ #define TEGRA_SWGROUP_EMUCIF 18 #define TEGRA_SWGROUP_TSEC 19 +#define TEGRA114_MC_RESET_AVPC 0 +#define TEGRA114_MC_RESET_DC 1 +#define TEGRA114_MC_RESET_DCB 2 +#define TEGRA114_MC_RESET_EPP 3 +#define TEGRA114_MC_RESET_2D 4 +#define TEGRA114_MC_RESET_HC 5 +#define TEGRA114_MC_RESET_HDA 6 +#define TEGRA114_MC_RESET_ISP 7 +#define TEGRA114_MC_RESET_MPCORE 8 +#define TEGRA114_MC_RESET_MPCORELP 9 +#define TEGRA114_MC_RESET_MPE 10 +#define TEGRA114_MC_RESET_3D 11 +#define TEGRA114_MC_RESET_3D2 12 +#define TEGRA114_MC_RESET_PPCS 13 +#define TEGRA114_MC_RESET_VDE 14 +#define TEGRA114_MC_RESET_VI 15 + #endif diff --git a/include/dt-bindings/memory/tegra124-mc.h b/include/dt-bindings/memory/tegra124-mc.h index f534d7c06019..186e6b7e9b35 100644 --- a/include/dt-bindings/memory/tegra124-mc.h +++ b/include/dt-bindings/memory/tegra124-mc.h @@ -29,4 +29,29 @@ #define TEGRA_SWGROUP_VIC 24 #define TEGRA_SWGROUP_VI 25 +#define TEGRA124_MC_RESET_AFI 0 +#define TEGRA124_MC_RESET_AVPC 1 +#define TEGRA124_MC_RESET_DC 2 +#define TEGRA124_MC_RESET_DCB 3 +#define TEGRA124_MC_RESET_HC 4 +#define TEGRA124_MC_RESET_HDA 5 +#define TEGRA124_MC_RESET_ISP2 6 +#define TEGRA124_MC_RESET_MPCORE 7 +#define TEGRA124_MC_RESET_MPCORELP 8 +#define TEGRA124_MC_RESET_MSENC 9 +#define TEGRA124_MC_RESET_PPCS 10 +#define TEGRA124_MC_RESET_SATA 11 +#define TEGRA124_MC_RESET_VDE 12 +#define TEGRA124_MC_RESET_VI 13 +#define TEGRA124_MC_RESET_VIC 14 +#define TEGRA124_MC_RESET_XUSB_HOST 15 +#define TEGRA124_MC_RESET_XUSB_DEV 16 +#define TEGRA124_MC_RESET_TSEC 17 +#define TEGRA124_MC_RESET_SDMMC1 18 +#define TEGRA124_MC_RESET_SDMMC2 19 +#define TEGRA124_MC_RESET_SDMMC3 20 +#define TEGRA124_MC_RESET_SDMMC4 21 +#define TEGRA124_MC_RESET_ISP2B 22 +#define TEGRA124_MC_RESET_GPU 23 + #endif diff --git a/include/dt-bindings/memory/tegra20-mc.h b/include/dt-bindings/memory/tegra20-mc.h new file mode 100644 index 000000000000..35e131eee198 --- /dev/null +++ b/include/dt-bindings/memory/tegra20-mc.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef DT_BINDINGS_MEMORY_TEGRA20_MC_H +#define DT_BINDINGS_MEMORY_TEGRA20_MC_H + +#define TEGRA20_MC_RESET_AVPC 0 +#define TEGRA20_MC_RESET_DC 1 +#define TEGRA20_MC_RESET_DCB 2 +#define TEGRA20_MC_RESET_EPP 3 +#define TEGRA20_MC_RESET_2D 4 +#define TEGRA20_MC_RESET_HC 5 +#define TEGRA20_MC_RESET_ISP 6 +#define TEGRA20_MC_RESET_MPCORE 7 +#define TEGRA20_MC_RESET_MPEA 8 +#define TEGRA20_MC_RESET_MPEB 9 +#define TEGRA20_MC_RESET_MPEC 10 +#define TEGRA20_MC_RESET_3D 11 +#define TEGRA20_MC_RESET_PPCS 12 +#define TEGRA20_MC_RESET_VDE 13 +#define TEGRA20_MC_RESET_VI 14 + +#endif diff --git a/include/dt-bindings/memory/tegra210-mc.h b/include/dt-bindings/memory/tegra210-mc.h index 4490f7cf4772..cacf05617e03 100644 --- a/include/dt-bindings/memory/tegra210-mc.h +++ b/include/dt-bindings/memory/tegra210-mc.h @@ -34,4 +34,35 @@ #define TEGRA_SWGROUP_ETR 29 #define TEGRA_SWGROUP_TSECB 30 +#define TEGRA210_MC_RESET_AFI 0 +#define TEGRA210_MC_RESET_AVPC 1 +#define TEGRA210_MC_RESET_DC 2 +#define TEGRA210_MC_RESET_DCB 3 +#define TEGRA210_MC_RESET_HC 4 +#define TEGRA210_MC_RESET_HDA 5 +#define TEGRA210_MC_RESET_ISP2 6 +#define TEGRA210_MC_RESET_MPCORE 7 +#define TEGRA210_MC_RESET_NVENC 8 +#define TEGRA210_MC_RESET_PPCS 9 +#define TEGRA210_MC_RESET_SATA 10 +#define TEGRA210_MC_RESET_VI 11 +#define TEGRA210_MC_RESET_VIC 12 +#define TEGRA210_MC_RESET_XUSB_HOST 13 +#define TEGRA210_MC_RESET_XUSB_DEV 14 +#define TEGRA210_MC_RESET_A9AVP 15 +#define TEGRA210_MC_RESET_TSEC 16 +#define TEGRA210_MC_RESET_SDMMC1 17 +#define TEGRA210_MC_RESET_SDMMC2 18 +#define TEGRA210_MC_RESET_SDMMC3 19 +#define TEGRA210_MC_RESET_SDMMC4 20 +#define TEGRA210_MC_RESET_ISP2B 21 +#define TEGRA210_MC_RESET_GPU 22 +#define TEGRA210_MC_RESET_NVDEC 23 +#define TEGRA210_MC_RESET_APE 24 +#define TEGRA210_MC_RESET_SE 25 +#define TEGRA210_MC_RESET_NVJPG 26 +#define TEGRA210_MC_RESET_AXIAP 27 +#define TEGRA210_MC_RESET_ETR 28 +#define TEGRA210_MC_RESET_TSECB 29 + #endif diff --git a/include/dt-bindings/memory/tegra30-mc.h b/include/dt-bindings/memory/tegra30-mc.h index 3cac81919023..169f005fbc78 100644 --- a/include/dt-bindings/memory/tegra30-mc.h +++ b/include/dt-bindings/memory/tegra30-mc.h @@ -22,4 +22,23 @@ #define TEGRA_SWGROUP_MPCORE 17 #define TEGRA_SWGROUP_ISP 18 +#define TEGRA30_MC_RESET_AFI 0 +#define TEGRA30_MC_RESET_AVPC 1 +#define TEGRA30_MC_RESET_DC 2 +#define TEGRA30_MC_RESET_DCB 3 +#define TEGRA30_MC_RESET_EPP 4 +#define TEGRA30_MC_RESET_2D 5 +#define TEGRA30_MC_RESET_HC 6 +#define TEGRA30_MC_RESET_HDA 7 +#define TEGRA30_MC_RESET_ISP 8 +#define TEGRA30_MC_RESET_MPCORE 9 +#define TEGRA30_MC_RESET_MPCORELP 10 +#define TEGRA30_MC_RESET_MPE 11 +#define TEGRA30_MC_RESET_3D 12 +#define TEGRA30_MC_RESET_3D2 13 +#define TEGRA30_MC_RESET_PPCS 14 +#define TEGRA30_MC_RESET_SATA 15 +#define TEGRA30_MC_RESET_VDE 16 +#define TEGRA30_MC_RESET_VI 17 + #endif diff --git a/include/dt-bindings/mfd/at91-usart.h b/include/dt-bindings/mfd/at91-usart.h new file mode 100644 index 000000000000..2de5bc312e1e --- /dev/null +++ b/include/dt-bindings/mfd/at91-usart.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides macros for AT91 USART DT bindings. + * + * Copyright (C) 2018 Microchip Technology + * + * Author: Radu Pirea <radu.pirea@microchip.com> + * + */ + +#ifndef __DT_BINDINGS_AT91_USART_H__ +#define __DT_BINDINGS_AT91_USART_H__ + +#define AT91_USART_MODE_SERIAL 0 +#define AT91_USART_MODE_SPI 1 + +#endif /* __DT_BINDINGS_AT91_USART_H__ */ diff --git a/include/dt-bindings/net/microchip-lan78xx.h b/include/dt-bindings/net/microchip-lan78xx.h new file mode 100644 index 000000000000..0742ff075307 --- /dev/null +++ b/include/dt-bindings/net/microchip-lan78xx.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _DT_BINDINGS_MICROCHIP_LAN78XX_H +#define _DT_BINDINGS_MICROCHIP_LAN78XX_H + +/* LED modes for LAN7800/LAN7850 embedded PHY */ + +#define LAN78XX_LINK_ACTIVITY 0 +#define LAN78XX_LINK_1000_ACTIVITY 1 +#define LAN78XX_LINK_100_ACTIVITY 2 +#define LAN78XX_LINK_10_ACTIVITY 3 +#define LAN78XX_LINK_100_1000_ACTIVITY 4 +#define LAN78XX_LINK_10_1000_ACTIVITY 5 +#define LAN78XX_LINK_10_100_ACTIVITY 6 +#define LAN78XX_DUPLEX_COLLISION 8 +#define LAN78XX_COLLISION 9 +#define LAN78XX_ACTIVITY 10 +#define LAN78XX_AUTONEG_FAULT 12 +#define LAN78XX_FORCE_LED_OFF 14 +#define LAN78XX_FORCE_LED_ON 15 + +#endif diff --git a/include/dt-bindings/net/mscc-phy-vsc8531.h b/include/dt-bindings/net/mscc-phy-vsc8531.h index 697161f80eb5..9eb2ec2b2ea9 100644 --- a/include/dt-bindings/net/mscc-phy-vsc8531.h +++ b/include/dt-bindings/net/mscc-phy-vsc8531.h @@ -18,9 +18,11 @@ #define VSC8531_LINK_100_1000_ACTIVITY 4 #define VSC8531_LINK_10_1000_ACTIVITY 5 #define VSC8531_LINK_10_100_ACTIVITY 6 +#define VSC8584_LINK_100FX_1000X_ACTIVITY 7 #define VSC8531_DUPLEX_COLLISION 8 #define VSC8531_COLLISION 9 #define VSC8531_ACTIVITY 10 +#define VSC8584_100FX_1000X_ACTIVITY 11 #define VSC8531_AUTONEG_FAULT 12 #define VSC8531_SERIAL_MODE 13 #define VSC8531_FORCE_LED_OFF 14 diff --git a/include/dt-bindings/phy/phy-ocelot-serdes.h b/include/dt-bindings/phy/phy-ocelot-serdes.h new file mode 100644 index 000000000000..fe70adaca68f --- /dev/null +++ b/include/dt-bindings/phy/phy-ocelot-serdes.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* Copyright (c) 2018 Microsemi Corporation */ +#ifndef __PHY_OCELOT_SERDES_H__ +#define __PHY_OCELOT_SERDES_H__ + +#define SERDES1G(x) (x) +#define SERDES1G_MAX SERDES1G(5) +#define SERDES6G(x) (SERDES1G_MAX + 1 + (x)) +#define SERDES6G_MAX SERDES6G(2) +#define SERDES_MAX (SERDES6G_MAX + 1) + +#endif diff --git a/include/dt-bindings/phy/phy-qcom-qusb2.h b/include/dt-bindings/phy/phy-qcom-qusb2.h new file mode 100644 index 000000000000..5c5e4d800cac --- /dev/null +++ b/include/dt-bindings/phy/phy-qcom-qusb2.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_QCOM_PHY_QUSB2_H_ +#define _DT_BINDINGS_QCOM_PHY_QUSB2_H_ + +/* PHY HSTX TRIM bit values (24mA to 15mA) */ +#define QUSB2_V2_HSTX_TRIM_24_0_MA 0x0 +#define QUSB2_V2_HSTX_TRIM_23_4_MA 0x1 +#define QUSB2_V2_HSTX_TRIM_22_8_MA 0x2 +#define QUSB2_V2_HSTX_TRIM_22_2_MA 0x3 +#define QUSB2_V2_HSTX_TRIM_21_6_MA 0x4 +#define QUSB2_V2_HSTX_TRIM_21_0_MA 0x5 +#define QUSB2_V2_HSTX_TRIM_20_4_MA 0x6 +#define QUSB2_V2_HSTX_TRIM_19_8_MA 0x7 +#define QUSB2_V2_HSTX_TRIM_19_2_MA 0x8 +#define QUSB2_V2_HSTX_TRIM_18_6_MA 0x9 +#define QUSB2_V2_HSTX_TRIM_18_0_MA 0xa +#define QUSB2_V2_HSTX_TRIM_17_4_MA 0xb +#define QUSB2_V2_HSTX_TRIM_16_8_MA 0xc +#define QUSB2_V2_HSTX_TRIM_16_2_MA 0xd +#define QUSB2_V2_HSTX_TRIM_15_6_MA 0xe +#define QUSB2_V2_HSTX_TRIM_15_0_MA 0xf + +/* PHY PREEMPHASIS bit values */ +#define QUSB2_V2_PREEMPHASIS_NONE 0 +#define QUSB2_V2_PREEMPHASIS_5_PERCENT 1 +#define QUSB2_V2_PREEMPHASIS_10_PERCENT 2 +#define QUSB2_V2_PREEMPHASIS_15_PERCENT 3 + +/* PHY PREEMPHASIS-WIDTH bit values */ +#define QUSB2_V2_PREEMPHASIS_WIDTH_FULL_BIT 0 +#define QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT 1 + +#endif diff --git a/include/dt-bindings/pinctrl/at91.h b/include/dt-bindings/pinctrl/at91.h index 2732d6c0fb39..eb81867eac77 100644 --- a/include/dt-bindings/pinctrl/at91.h +++ b/include/dt-bindings/pinctrl/at91.h @@ -39,4 +39,8 @@ #define AT91_PERIPH_C 3 #define AT91_PERIPH_D 4 +#define ATMEL_PIO_DRVSTR_LO 1 +#define ATMEL_PIO_DRVSTR_ME 2 +#define ATMEL_PIO_DRVSTR_HI 3 + #endif /* __DT_BINDINGS_AT91_PINCTRL_H__ */ diff --git a/include/dt-bindings/pinctrl/bcm2835.h b/include/dt-bindings/pinctrl/bcm2835.h index e4e4fdf5d38f..b5b2654a0e4d 100644 --- a/include/dt-bindings/pinctrl/bcm2835.h +++ b/include/dt-bindings/pinctrl/bcm2835.h @@ -1,14 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0 */ /* * Header providing constants for bcm2835 pinctrl bindings. * * Copyright (C) 2015 Stefan Wahren <stefan.wahren@i2se.com> - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html */ #ifndef __DT_BINDINGS_PINCTRL_BCM2835_H__ diff --git a/include/dt-bindings/pinctrl/k3.h b/include/dt-bindings/pinctrl/k3.h new file mode 100644 index 000000000000..45e11b6170ca --- /dev/null +++ b/include/dt-bindings/pinctrl/k3.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides constants for pinctrl bindings for TI's K3 SoC + * family. + * + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + */ +#ifndef _DT_BINDINGS_PINCTRL_TI_K3_H +#define _DT_BINDINGS_PINCTRL_TI_K3_H + +#define PULLUDEN_SHIFT (16) +#define PULLTYPESEL_SHIFT (17) +#define RXACTIVE_SHIFT (18) + +#define PULL_DISABLE (1 << PULLUDEN_SHIFT) +#define PULL_ENABLE (0 << PULLUDEN_SHIFT) + +#define PULL_UP (1 << PULLTYPESEL_SHIFT | PULL_ENABLE) +#define PULL_DOWN (0 << PULLTYPESEL_SHIFT | PULL_ENABLE) + +#define INPUT_EN (1 << RXACTIVE_SHIFT) +#define INPUT_DISABLE (0 << RXACTIVE_SHIFT) + +/* Only these macros are expected be used directly in device tree files */ +#define PIN_OUTPUT (INPUT_DISABLE | PULL_DISABLE) +#define PIN_OUTPUT_PULLUP (INPUT_DISABLE | PULL_UP) +#define PIN_OUTPUT_PULLDOWN (INPUT_DISABLE | PULL_DOWN) +#define PIN_INPUT (INPUT_EN | PULL_DISABLE) +#define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP) +#define PIN_INPUT_PULLDOWN (INPUT_EN | PULL_DOWN) + +#define AM65X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define AM65X_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) + +#endif diff --git a/include/dt-bindings/pinctrl/mt6797-pinfunc.h b/include/dt-bindings/pinctrl/mt6797-pinfunc.h new file mode 100644 index 000000000000..e9813361b27c --- /dev/null +++ b/include/dt-bindings/pinctrl/mt6797-pinfunc.h @@ -0,0 +1,1368 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DTS_MT6797_PINFUNC_H +#define __DTS_MT6797_PINFUNC_H + +#include <dt-bindings/pinctrl/mt65xx.h> + +#define MT6797_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) +#define MT6797_GPIO0__FUNC_CSI0A_L0P_T0A (MTK_PIN_NO(0) | 1) + +#define MT6797_GPIO1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) +#define MT6797_GPIO1__FUNC_CSI0A_L0N_T0B (MTK_PIN_NO(1) | 1) + +#define MT6797_GPIO2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) +#define MT6797_GPIO2__FUNC_CSI0A_L1P_T0C (MTK_PIN_NO(2) | 1) + +#define MT6797_GPIO3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) +#define MT6797_GPIO3__FUNC_CSI0A_L1N_T1A (MTK_PIN_NO(3) | 1) + +#define MT6797_GPIO4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) +#define MT6797_GPIO4__FUNC_CSI0A_L2P_T1B (MTK_PIN_NO(4) | 1) + +#define MT6797_GPIO5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) +#define MT6797_GPIO5__FUNC_CSI0A_L2N_T1C (MTK_PIN_NO(5) | 1) + +#define MT6797_GPIO6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) +#define MT6797_GPIO6__FUNC_CSI0B_L0P_T0A (MTK_PIN_NO(6) | 1) + +#define MT6797_GPIO7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) +#define MT6797_GPIO7__FUNC_CSI0B_L0N_T0B (MTK_PIN_NO(7) | 1) + +#define MT6797_GPIO8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) +#define MT6797_GPIO8__FUNC_CSI0B_L1P_T0C (MTK_PIN_NO(8) | 1) + +#define MT6797_GPIO9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) +#define MT6797_GPIO9__FUNC_CSI0B_L1N_T1A (MTK_PIN_NO(9) | 1) + +#define MT6797_GPIO10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) +#define MT6797_GPIO10__FUNC_CSI1A_L0P_T0A (MTK_PIN_NO(10) | 1) + +#define MT6797_GPIO11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) +#define MT6797_GPIO11__FUNC_CSI1A_L0N_T0B (MTK_PIN_NO(11) | 1) + +#define MT6797_GPIO12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) +#define MT6797_GPIO12__FUNC_CSI1A_L1P_T0C (MTK_PIN_NO(12) | 1) + +#define MT6797_GPIO13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) +#define MT6797_GPIO13__FUNC_CSI1A_L1N_T1A (MTK_PIN_NO(13) | 1) + +#define MT6797_GPIO14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) +#define MT6797_GPIO14__FUNC_CSI1A_L2P_T1B (MTK_PIN_NO(14) | 1) + +#define MT6797_GPIO15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) +#define MT6797_GPIO15__FUNC_CSI1A_L2N_T1C (MTK_PIN_NO(15) | 1) + +#define MT6797_GPIO16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0) +#define MT6797_GPIO16__FUNC_CSI1B_L0P_T0A (MTK_PIN_NO(16) | 1) + +#define MT6797_GPIO17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0) +#define MT6797_GPIO17__FUNC_CSI1B_L0N_T0B (MTK_PIN_NO(17) | 1) + +#define MT6797_GPIO18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) +#define MT6797_GPIO18__FUNC_CSI1B_L1P_T0C (MTK_PIN_NO(18) | 1) + +#define MT6797_GPIO19__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) +#define MT6797_GPIO19__FUNC_CSI1B_L1N_T1A (MTK_PIN_NO(19) | 1) + +#define MT6797_GPIO20__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) +#define MT6797_GPIO20__FUNC_CSI1B_L2P_T1B (MTK_PIN_NO(20) | 1) + +#define MT6797_GPIO21__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) +#define MT6797_GPIO21__FUNC_CSI1B_L2N_T1C (MTK_PIN_NO(21) | 1) + +#define MT6797_GPIO22__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) +#define MT6797_GPIO22__FUNC_CSI2_L0P_T0A (MTK_PIN_NO(22) | 1) + +#define MT6797_GPIO23__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) +#define MT6797_GPIO23__FUNC_CSI2_L0N_T0B (MTK_PIN_NO(23) | 1) + +#define MT6797_GPIO24__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) +#define MT6797_GPIO24__FUNC_CSI2_L1P_T0C (MTK_PIN_NO(24) | 1) + +#define MT6797_GPIO25__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) +#define MT6797_GPIO25__FUNC_CSI2_L1N_T1A (MTK_PIN_NO(25) | 1) + +#define MT6797_GPIO26__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) +#define MT6797_GPIO26__FUNC_CSI2_L2P_T1B (MTK_PIN_NO(26) | 1) + +#define MT6797_GPIO27__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) +#define MT6797_GPIO27__FUNC_CSI2_L2N_T1C (MTK_PIN_NO(27) | 1) + +#define MT6797_GPIO28__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) +#define MT6797_GPIO28__FUNC_SPI5_CLK_A (MTK_PIN_NO(28) | 1) +#define MT6797_GPIO28__FUNC_IRTX_OUT (MTK_PIN_NO(28) | 2) +#define MT6797_GPIO28__FUNC_UDI_TDO (MTK_PIN_NO(28) | 3) +#define MT6797_GPIO28__FUNC_SCP_JTAG_TDO (MTK_PIN_NO(28) | 4) +#define MT6797_GPIO28__FUNC_CONN_MCU_TDO (MTK_PIN_NO(28) | 5) +#define MT6797_GPIO28__FUNC_PWM_A (MTK_PIN_NO(28) | 6) +#define MT6797_GPIO28__FUNC_C2K_DM_OTDO (MTK_PIN_NO(28) | 7) + +#define MT6797_GPIO29__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) +#define MT6797_GPIO29__FUNC_SPI5_MI_A (MTK_PIN_NO(29) | 1) +#define MT6797_GPIO29__FUNC_DAP_SIB1_SWD (MTK_PIN_NO(29) | 2) +#define MT6797_GPIO29__FUNC_UDI_TMS (MTK_PIN_NO(29) | 3) +#define MT6797_GPIO29__FUNC_SCP_JTAG_TMS (MTK_PIN_NO(29) | 4) +#define MT6797_GPIO29__FUNC_CONN_MCU_TMS (MTK_PIN_NO(29) | 5) +#define MT6797_GPIO29__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(29) | 6) +#define MT6797_GPIO29__FUNC_C2K_DM_OTMS (MTK_PIN_NO(29) | 7) + +#define MT6797_GPIO30__FUNC_GPIO30 (MTK_PIN_NO(30) | 0) +#define MT6797_GPIO30__FUNC_CMMCLK0 (MTK_PIN_NO(30) | 1) +#define MT6797_GPIO30__FUNC_MD_CLKM0 (MTK_PIN_NO(30) | 7) + +#define MT6797_GPIO31__FUNC_GPIO31 (MTK_PIN_NO(31) | 0) +#define MT6797_GPIO31__FUNC_CMMCLK1 (MTK_PIN_NO(31) | 1) +#define MT6797_GPIO31__FUNC_MD_CLKM1 (MTK_PIN_NO(31) | 7) + +#define MT6797_GPIO32__FUNC_GPIO32 (MTK_PIN_NO(32) | 0) +#define MT6797_GPIO32__FUNC_SPI5_CS_A (MTK_PIN_NO(32) | 1) +#define MT6797_GPIO32__FUNC_DAP_SIB1_SWCK (MTK_PIN_NO(32) | 2) +#define MT6797_GPIO32__FUNC_UDI_TCK_XI (MTK_PIN_NO(32) | 3) +#define MT6797_GPIO32__FUNC_SCP_JTAG_TCK (MTK_PIN_NO(32) | 4) +#define MT6797_GPIO32__FUNC_CONN_MCU_TCK (MTK_PIN_NO(32) | 5) +#define MT6797_GPIO32__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(32) | 6) +#define MT6797_GPIO32__FUNC_C2K_DM_OTCK (MTK_PIN_NO(32) | 7) + +#define MT6797_GPIO33__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) +#define MT6797_GPIO33__FUNC_SPI5_MO_A (MTK_PIN_NO(33) | 1) +#define MT6797_GPIO33__FUNC_CMFLASH (MTK_PIN_NO(33) | 2) +#define MT6797_GPIO33__FUNC_UDI_TDI (MTK_PIN_NO(33) | 3) +#define MT6797_GPIO33__FUNC_SCP_JTAG_TDI (MTK_PIN_NO(33) | 4) +#define MT6797_GPIO33__FUNC_CONN_MCU_TDI (MTK_PIN_NO(33) | 5) +#define MT6797_GPIO33__FUNC_MD_URXD0 (MTK_PIN_NO(33) | 6) +#define MT6797_GPIO33__FUNC_C2K_DM_OTDI (MTK_PIN_NO(33) | 7) + +#define MT6797_GPIO34__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) +#define MT6797_GPIO34__FUNC_CMFLASH (MTK_PIN_NO(34) | 1) +#define MT6797_GPIO34__FUNC_CLKM0 (MTK_PIN_NO(34) | 2) +#define MT6797_GPIO34__FUNC_UDI_NTRST (MTK_PIN_NO(34) | 3) +#define MT6797_GPIO34__FUNC_SCP_JTAG_TRSTN (MTK_PIN_NO(34) | 4) +#define MT6797_GPIO34__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(34) | 5) +#define MT6797_GPIO34__FUNC_MD_UTXD0 (MTK_PIN_NO(34) | 6) +#define MT6797_GPIO34__FUNC_C2K_DM_JTINTP (MTK_PIN_NO(34) | 7) + +#define MT6797_GPIO35__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) +#define MT6797_GPIO35__FUNC_CMMCLK3 (MTK_PIN_NO(35) | 1) +#define MT6797_GPIO35__FUNC_CLKM1 (MTK_PIN_NO(35) | 2) +#define MT6797_GPIO35__FUNC_MD_URXD1 (MTK_PIN_NO(35) | 3) +#define MT6797_GPIO35__FUNC_PTA_RXD (MTK_PIN_NO(35) | 4) +#define MT6797_GPIO35__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(35) | 5) +#define MT6797_GPIO35__FUNC_PWM_B (MTK_PIN_NO(35) | 6) +#define MT6797_GPIO35__FUNC_PCC_PPC_IO (MTK_PIN_NO(35) | 7) + +#define MT6797_GPIO36__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) +#define MT6797_GPIO36__FUNC_CMMCLK2 (MTK_PIN_NO(36) | 1) +#define MT6797_GPIO36__FUNC_CLKM2 (MTK_PIN_NO(36) | 2) +#define MT6797_GPIO36__FUNC_MD_UTXD1 (MTK_PIN_NO(36) | 3) +#define MT6797_GPIO36__FUNC_PTA_TXD (MTK_PIN_NO(36) | 4) +#define MT6797_GPIO36__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(36) | 5) +#define MT6797_GPIO36__FUNC_PWM_C (MTK_PIN_NO(36) | 6) +#define MT6797_GPIO36__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(36) | 7) + +#define MT6797_GPIO37__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) +#define MT6797_GPIO37__FUNC_SCL0_0 (MTK_PIN_NO(37) | 1) + +#define MT6797_GPIO38__FUNC_GPIO38 (MTK_PIN_NO(38) | 0) +#define MT6797_GPIO38__FUNC_SDA0_0 (MTK_PIN_NO(38) | 1) + +#define MT6797_GPIO39__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) +#define MT6797_GPIO39__FUNC_DPI_D0 (MTK_PIN_NO(39) | 1) +#define MT6797_GPIO39__FUNC_SPI1_CLK_A (MTK_PIN_NO(39) | 2) +#define MT6797_GPIO39__FUNC_PCM0_SYNC (MTK_PIN_NO(39) | 3) +#define MT6797_GPIO39__FUNC_I2S0_LRCK (MTK_PIN_NO(39) | 4) +#define MT6797_GPIO39__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(39) | 5) +#define MT6797_GPIO39__FUNC_URXD3 (MTK_PIN_NO(39) | 6) +#define MT6797_GPIO39__FUNC_C2K_NTRST (MTK_PIN_NO(39) | 7) + +#define MT6797_GPIO40__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) +#define MT6797_GPIO40__FUNC_DPI_D1 (MTK_PIN_NO(40) | 1) +#define MT6797_GPIO40__FUNC_SPI1_MI_A (MTK_PIN_NO(40) | 2) +#define MT6797_GPIO40__FUNC_PCM0_CLK (MTK_PIN_NO(40) | 3) +#define MT6797_GPIO40__FUNC_I2S0_BCK (MTK_PIN_NO(40) | 4) +#define MT6797_GPIO40__FUNC_CONN_MCU_TDO (MTK_PIN_NO(40) | 5) +#define MT6797_GPIO40__FUNC_UTXD3 (MTK_PIN_NO(40) | 6) +#define MT6797_GPIO40__FUNC_C2K_TCK (MTK_PIN_NO(40) | 7) + +#define MT6797_GPIO41__FUNC_GPIO41 (MTK_PIN_NO(41) | 0) +#define MT6797_GPIO41__FUNC_DPI_D2 (MTK_PIN_NO(41) | 1) +#define MT6797_GPIO41__FUNC_SPI1_CS_A (MTK_PIN_NO(41) | 2) +#define MT6797_GPIO41__FUNC_PCM0_DO (MTK_PIN_NO(41) | 3) +#define MT6797_GPIO41__FUNC_I2S3_DO (MTK_PIN_NO(41) | 4) +#define MT6797_GPIO41__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(41) | 5) +#define MT6797_GPIO41__FUNC_URTS3 (MTK_PIN_NO(41) | 6) +#define MT6797_GPIO41__FUNC_C2K_TDI (MTK_PIN_NO(41) | 7) + +#define MT6797_GPIO42__FUNC_GPIO42 (MTK_PIN_NO(42) | 0) +#define MT6797_GPIO42__FUNC_DPI_D3 (MTK_PIN_NO(42) | 1) +#define MT6797_GPIO42__FUNC_SPI1_MO_A (MTK_PIN_NO(42) | 2) +#define MT6797_GPIO42__FUNC_PCM0_DI (MTK_PIN_NO(42) | 3) +#define MT6797_GPIO42__FUNC_I2S0_DI (MTK_PIN_NO(42) | 4) +#define MT6797_GPIO42__FUNC_CONN_MCU_TDI (MTK_PIN_NO(42) | 5) +#define MT6797_GPIO42__FUNC_UCTS3 (MTK_PIN_NO(42) | 6) +#define MT6797_GPIO42__FUNC_C2K_TMS (MTK_PIN_NO(42) | 7) + +#define MT6797_GPIO43__FUNC_GPIO43 (MTK_PIN_NO(43) | 0) +#define MT6797_GPIO43__FUNC_DPI_D4 (MTK_PIN_NO(43) | 1) +#define MT6797_GPIO43__FUNC_SPI2_CLK_A (MTK_PIN_NO(43) | 2) +#define MT6797_GPIO43__FUNC_PCM1_SYNC (MTK_PIN_NO(43) | 3) +#define MT6797_GPIO43__FUNC_I2S2_LRCK (MTK_PIN_NO(43) | 4) +#define MT6797_GPIO43__FUNC_CONN_MCU_TMS (MTK_PIN_NO(43) | 5) +#define MT6797_GPIO43__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(43) | 6) +#define MT6797_GPIO43__FUNC_C2K_TDO (MTK_PIN_NO(43) | 7) + +#define MT6797_GPIO44__FUNC_GPIO44 (MTK_PIN_NO(44) | 0) +#define MT6797_GPIO44__FUNC_DPI_D5 (MTK_PIN_NO(44) | 1) +#define MT6797_GPIO44__FUNC_SPI2_MI_A (MTK_PIN_NO(44) | 2) +#define MT6797_GPIO44__FUNC_PCM1_CLK (MTK_PIN_NO(44) | 3) +#define MT6797_GPIO44__FUNC_I2S2_BCK (MTK_PIN_NO(44) | 4) +#define MT6797_GPIO44__FUNC_CONN_MCU_TCK (MTK_PIN_NO(44) | 5) +#define MT6797_GPIO44__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(44) | 6) +#define MT6797_GPIO44__FUNC_C2K_RTCK (MTK_PIN_NO(44) | 7) + +#define MT6797_GPIO45__FUNC_GPIO45 (MTK_PIN_NO(45) | 0) +#define MT6797_GPIO45__FUNC_DPI_D6 (MTK_PIN_NO(45) | 1) +#define MT6797_GPIO45__FUNC_SPI2_CS_A (MTK_PIN_NO(45) | 2) +#define MT6797_GPIO45__FUNC_PCM1_DI (MTK_PIN_NO(45) | 3) +#define MT6797_GPIO45__FUNC_I2S2_DI (MTK_PIN_NO(45) | 4) +#define MT6797_GPIO45__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(45) | 5) +#define MT6797_GPIO45__FUNC_MD_URXD0 (MTK_PIN_NO(45) | 6) + +#define MT6797_GPIO46__FUNC_GPIO46 (MTK_PIN_NO(46) | 0) +#define MT6797_GPIO46__FUNC_DPI_D7 (MTK_PIN_NO(46) | 1) +#define MT6797_GPIO46__FUNC_SPI2_MO_A (MTK_PIN_NO(46) | 2) +#define MT6797_GPIO46__FUNC_PCM1_DO0 (MTK_PIN_NO(46) | 3) +#define MT6797_GPIO46__FUNC_I2S1_DO (MTK_PIN_NO(46) | 4) +#define MT6797_GPIO46__FUNC_ANT_SEL0 (MTK_PIN_NO(46) | 5) +#define MT6797_GPIO46__FUNC_MD_UTXD0 (MTK_PIN_NO(46) | 6) + +#define MT6797_GPIO47__FUNC_GPIO47 (MTK_PIN_NO(47) | 0) +#define MT6797_GPIO47__FUNC_DPI_D8 (MTK_PIN_NO(47) | 1) +#define MT6797_GPIO47__FUNC_CLKM0 (MTK_PIN_NO(47) | 2) +#define MT6797_GPIO47__FUNC_PCM1_DO1 (MTK_PIN_NO(47) | 3) +#define MT6797_GPIO47__FUNC_I2S0_MCK (MTK_PIN_NO(47) | 4) +#define MT6797_GPIO47__FUNC_ANT_SEL1 (MTK_PIN_NO(47) | 5) +#define MT6797_GPIO47__FUNC_PTA_RXD (MTK_PIN_NO(47) | 6) +#define MT6797_GPIO47__FUNC_C2K_URXD0 (MTK_PIN_NO(47) | 7) + +#define MT6797_GPIO48__FUNC_GPIO48 (MTK_PIN_NO(48) | 0) +#define MT6797_GPIO48__FUNC_DPI_D9 (MTK_PIN_NO(48) | 1) +#define MT6797_GPIO48__FUNC_CLKM1 (MTK_PIN_NO(48) | 2) +#define MT6797_GPIO48__FUNC_CMFLASH (MTK_PIN_NO(48) | 3) +#define MT6797_GPIO48__FUNC_I2S2_MCK (MTK_PIN_NO(48) | 4) +#define MT6797_GPIO48__FUNC_ANT_SEL2 (MTK_PIN_NO(48) | 5) +#define MT6797_GPIO48__FUNC_PTA_TXD (MTK_PIN_NO(48) | 6) +#define MT6797_GPIO48__FUNC_C2K_UTXD0 (MTK_PIN_NO(48) | 7) + +#define MT6797_GPIO49__FUNC_GPIO49 (MTK_PIN_NO(49) | 0) +#define MT6797_GPIO49__FUNC_DPI_D10 (MTK_PIN_NO(49) | 1) +#define MT6797_GPIO49__FUNC_MD_INT1_C2K_UIM1_HOT_PLUG_IN (MTK_PIN_NO(49) | 2) +#define MT6797_GPIO49__FUNC_PWM_C (MTK_PIN_NO(49) | 3) +#define MT6797_GPIO49__FUNC_IRTX_OUT (MTK_PIN_NO(49) | 4) +#define MT6797_GPIO49__FUNC_ANT_SEL3 (MTK_PIN_NO(49) | 5) +#define MT6797_GPIO49__FUNC_MD_URXD1 (MTK_PIN_NO(49) | 6) + +#define MT6797_GPIO50__FUNC_GPIO50 (MTK_PIN_NO(50) | 0) +#define MT6797_GPIO50__FUNC_DPI_D11 (MTK_PIN_NO(50) | 1) +#define MT6797_GPIO50__FUNC_MD_INT2 (MTK_PIN_NO(50) | 2) +#define MT6797_GPIO50__FUNC_PWM_D (MTK_PIN_NO(50) | 3) +#define MT6797_GPIO50__FUNC_CLKM2 (MTK_PIN_NO(50) | 4) +#define MT6797_GPIO50__FUNC_ANT_SEL4 (MTK_PIN_NO(50) | 5) +#define MT6797_GPIO50__FUNC_MD_UTXD1 (MTK_PIN_NO(50) | 6) + +#define MT6797_GPIO51__FUNC_GPIO51 (MTK_PIN_NO(51) | 0) +#define MT6797_GPIO51__FUNC_DPI_DE (MTK_PIN_NO(51) | 1) +#define MT6797_GPIO51__FUNC_SPI4_CLK_A (MTK_PIN_NO(51) | 2) +#define MT6797_GPIO51__FUNC_IRTX_OUT (MTK_PIN_NO(51) | 3) +#define MT6797_GPIO51__FUNC_SCL0_1 (MTK_PIN_NO(51) | 4) +#define MT6797_GPIO51__FUNC_ANT_SEL5 (MTK_PIN_NO(51) | 5) +#define MT6797_GPIO51__FUNC_C2K_UTXD1 (MTK_PIN_NO(51) | 7) + +#define MT6797_GPIO52__FUNC_GPIO52 (MTK_PIN_NO(52) | 0) +#define MT6797_GPIO52__FUNC_DPI_CK (MTK_PIN_NO(52) | 1) +#define MT6797_GPIO52__FUNC_SPI4_MI_A (MTK_PIN_NO(52) | 2) +#define MT6797_GPIO52__FUNC_SPI4_MO_A (MTK_PIN_NO(52) | 3) +#define MT6797_GPIO52__FUNC_SDA0_1 (MTK_PIN_NO(52) | 4) +#define MT6797_GPIO52__FUNC_ANT_SEL6 (MTK_PIN_NO(52) | 5) +#define MT6797_GPIO52__FUNC_C2K_URXD1 (MTK_PIN_NO(52) | 7) + +#define MT6797_GPIO53__FUNC_GPIO53 (MTK_PIN_NO(53) | 0) +#define MT6797_GPIO53__FUNC_DPI_HSYNC (MTK_PIN_NO(53) | 1) +#define MT6797_GPIO53__FUNC_SPI4_CS_A (MTK_PIN_NO(53) | 2) +#define MT6797_GPIO53__FUNC_CMFLASH (MTK_PIN_NO(53) | 3) +#define MT6797_GPIO53__FUNC_SCL1_1 (MTK_PIN_NO(53) | 4) +#define MT6797_GPIO53__FUNC_ANT_SEL7 (MTK_PIN_NO(53) | 5) +#define MT6797_GPIO53__FUNC_MD_URXD2 (MTK_PIN_NO(53) | 6) +#define MT6797_GPIO53__FUNC_PCC_PPC_IO (MTK_PIN_NO(53) | 7) + +#define MT6797_GPIO54__FUNC_GPIO54 (MTK_PIN_NO(54) | 0) +#define MT6797_GPIO54__FUNC_DPI_VSYNC (MTK_PIN_NO(54) | 1) +#define MT6797_GPIO54__FUNC_SPI4_MO_A (MTK_PIN_NO(54) | 2) +#define MT6797_GPIO54__FUNC_SPI4_MI_A (MTK_PIN_NO(54) | 3) +#define MT6797_GPIO54__FUNC_SDA1_1 (MTK_PIN_NO(54) | 4) +#define MT6797_GPIO54__FUNC_PWM_A (MTK_PIN_NO(54) | 5) +#define MT6797_GPIO54__FUNC_MD_UTXD2 (MTK_PIN_NO(54) | 6) +#define MT6797_GPIO54__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(54) | 7) + +#define MT6797_GPIO55__FUNC_GPIO55 (MTK_PIN_NO(55) | 0) +#define MT6797_GPIO55__FUNC_SCL1_0 (MTK_PIN_NO(55) | 1) + +#define MT6797_GPIO56__FUNC_GPIO56 (MTK_PIN_NO(56) | 0) +#define MT6797_GPIO56__FUNC_SDA1_0 (MTK_PIN_NO(56) | 1) + +#define MT6797_GPIO57__FUNC_GPIO57 (MTK_PIN_NO(57) | 0) +#define MT6797_GPIO57__FUNC_SPI0_CLK (MTK_PIN_NO(57) | 1) +#define MT6797_GPIO57__FUNC_SCL0_2 (MTK_PIN_NO(57) | 2) +#define MT6797_GPIO57__FUNC_PWM_B (MTK_PIN_NO(57) | 3) +#define MT6797_GPIO57__FUNC_UTXD3 (MTK_PIN_NO(57) | 4) +#define MT6797_GPIO57__FUNC_PCM0_SYNC (MTK_PIN_NO(57) | 5) + +#define MT6797_GPIO58__FUNC_GPIO58 (MTK_PIN_NO(58) | 0) +#define MT6797_GPIO58__FUNC_SPI0_MI (MTK_PIN_NO(58) | 1) +#define MT6797_GPIO58__FUNC_SPI0_MO (MTK_PIN_NO(58) | 2) +#define MT6797_GPIO58__FUNC_SDA1_2 (MTK_PIN_NO(58) | 3) +#define MT6797_GPIO58__FUNC_URXD3 (MTK_PIN_NO(58) | 4) +#define MT6797_GPIO58__FUNC_PCM0_CLK (MTK_PIN_NO(58) | 5) + +#define MT6797_GPIO59__FUNC_GPIO59 (MTK_PIN_NO(59) | 0) +#define MT6797_GPIO59__FUNC_SPI0_MO (MTK_PIN_NO(59) | 1) +#define MT6797_GPIO59__FUNC_SPI0_MI (MTK_PIN_NO(59) | 2) +#define MT6797_GPIO59__FUNC_PWM_C (MTK_PIN_NO(59) | 3) +#define MT6797_GPIO59__FUNC_URTS3 (MTK_PIN_NO(59) | 4) +#define MT6797_GPIO59__FUNC_PCM0_DO (MTK_PIN_NO(59) | 5) + +#define MT6797_GPIO60__FUNC_GPIO60 (MTK_PIN_NO(60) | 0) +#define MT6797_GPIO60__FUNC_SPI0_CS (MTK_PIN_NO(60) | 1) +#define MT6797_GPIO60__FUNC_SDA0_2 (MTK_PIN_NO(60) | 2) +#define MT6797_GPIO60__FUNC_SCL1_2 (MTK_PIN_NO(60) | 3) +#define MT6797_GPIO60__FUNC_UCTS3 (MTK_PIN_NO(60) | 4) +#define MT6797_GPIO60__FUNC_PCM0_DI (MTK_PIN_NO(60) | 5) + +#define MT6797_GPIO61__FUNC_GPIO61 (MTK_PIN_NO(61) | 0) +#define MT6797_GPIO61__FUNC_EINT0 (MTK_PIN_NO(61) | 1) +#define MT6797_GPIO61__FUNC_IDDIG (MTK_PIN_NO(61) | 2) +#define MT6797_GPIO61__FUNC_SPI4_CLK_B (MTK_PIN_NO(61) | 3) +#define MT6797_GPIO61__FUNC_I2S0_LRCK (MTK_PIN_NO(61) | 4) +#define MT6797_GPIO61__FUNC_PCM0_SYNC (MTK_PIN_NO(61) | 5) +#define MT6797_GPIO61__FUNC_C2K_EINT0 (MTK_PIN_NO(61) | 7) + +#define MT6797_GPIO62__FUNC_GPIO62 (MTK_PIN_NO(62) | 0) +#define MT6797_GPIO62__FUNC_EINT1 (MTK_PIN_NO(62) | 1) +#define MT6797_GPIO62__FUNC_USB_DRVVBUS (MTK_PIN_NO(62) | 2) +#define MT6797_GPIO62__FUNC_SPI4_MI_B (MTK_PIN_NO(62) | 3) +#define MT6797_GPIO62__FUNC_I2S0_BCK (MTK_PIN_NO(62) | 4) +#define MT6797_GPIO62__FUNC_PCM0_CLK (MTK_PIN_NO(62) | 5) +#define MT6797_GPIO62__FUNC_C2K_EINT1 (MTK_PIN_NO(62) | 7) + +#define MT6797_GPIO63__FUNC_GPIO63 (MTK_PIN_NO(63) | 0) +#define MT6797_GPIO63__FUNC_EINT2 (MTK_PIN_NO(63) | 1) +#define MT6797_GPIO63__FUNC_IRTX_OUT (MTK_PIN_NO(63) | 2) +#define MT6797_GPIO63__FUNC_SPI4_MO_B (MTK_PIN_NO(63) | 3) +#define MT6797_GPIO63__FUNC_I2S0_MCK (MTK_PIN_NO(63) | 4) +#define MT6797_GPIO63__FUNC_PCM0_DI (MTK_PIN_NO(63) | 5) +#define MT6797_GPIO63__FUNC_C2K_DM_EINT0 (MTK_PIN_NO(63) | 7) + +#define MT6797_GPIO64__FUNC_GPIO64 (MTK_PIN_NO(64) | 0) +#define MT6797_GPIO64__FUNC_EINT3 (MTK_PIN_NO(64) | 1) +#define MT6797_GPIO64__FUNC_CMFLASH (MTK_PIN_NO(64) | 2) +#define MT6797_GPIO64__FUNC_SPI4_CS_B (MTK_PIN_NO(64) | 3) +#define MT6797_GPIO64__FUNC_I2S0_DI (MTK_PIN_NO(64) | 4) +#define MT6797_GPIO64__FUNC_PCM0_DO (MTK_PIN_NO(64) | 5) +#define MT6797_GPIO64__FUNC_C2K_DM_EINT1 (MTK_PIN_NO(64) | 7) + +#define MT6797_GPIO65__FUNC_GPIO65 (MTK_PIN_NO(65) | 0) +#define MT6797_GPIO65__FUNC_EINT4 (MTK_PIN_NO(65) | 1) +#define MT6797_GPIO65__FUNC_CLKM0 (MTK_PIN_NO(65) | 2) +#define MT6797_GPIO65__FUNC_SPI5_CLK_B (MTK_PIN_NO(65) | 3) +#define MT6797_GPIO65__FUNC_I2S1_LRCK (MTK_PIN_NO(65) | 4) +#define MT6797_GPIO65__FUNC_PWM_A (MTK_PIN_NO(65) | 5) +#define MT6797_GPIO65__FUNC_C2K_DM_EINT2 (MTK_PIN_NO(65) | 7) + +#define MT6797_GPIO66__FUNC_GPIO66 (MTK_PIN_NO(66) | 0) +#define MT6797_GPIO66__FUNC_EINT5 (MTK_PIN_NO(66) | 1) +#define MT6797_GPIO66__FUNC_CLKM1 (MTK_PIN_NO(66) | 2) +#define MT6797_GPIO66__FUNC_SPI5_MI_B (MTK_PIN_NO(66) | 3) +#define MT6797_GPIO66__FUNC_I2S1_BCK (MTK_PIN_NO(66) | 4) +#define MT6797_GPIO66__FUNC_PWM_B (MTK_PIN_NO(66) | 5) +#define MT6797_GPIO66__FUNC_C2K_DM_EINT3 (MTK_PIN_NO(66) | 7) + +#define MT6797_GPIO67__FUNC_GPIO67 (MTK_PIN_NO(67) | 0) +#define MT6797_GPIO67__FUNC_EINT6 (MTK_PIN_NO(67) | 1) +#define MT6797_GPIO67__FUNC_CLKM2 (MTK_PIN_NO(67) | 2) +#define MT6797_GPIO67__FUNC_SPI5_MO_B (MTK_PIN_NO(67) | 3) +#define MT6797_GPIO67__FUNC_I2S1_MCK (MTK_PIN_NO(67) | 4) +#define MT6797_GPIO67__FUNC_PWM_C (MTK_PIN_NO(67) | 5) +#define MT6797_GPIO67__FUNC_DBG_MON_A0 (MTK_PIN_NO(67) | 7) + +#define MT6797_GPIO68__FUNC_GPIO68 (MTK_PIN_NO(68) | 0) +#define MT6797_GPIO68__FUNC_EINT7 (MTK_PIN_NO(68) | 1) +#define MT6797_GPIO68__FUNC_CLKM3 (MTK_PIN_NO(68) | 2) +#define MT6797_GPIO68__FUNC_SPI5_CS_B (MTK_PIN_NO(68) | 3) +#define MT6797_GPIO68__FUNC_I2S1_DO (MTK_PIN_NO(68) | 4) +#define MT6797_GPIO68__FUNC_PWM_D (MTK_PIN_NO(68) | 5) +#define MT6797_GPIO68__FUNC_DBG_MON_A1 (MTK_PIN_NO(68) | 7) + +#define MT6797_GPIO69__FUNC_GPIO69 (MTK_PIN_NO(69) | 0) +#define MT6797_GPIO69__FUNC_I2S0_LRCK (MTK_PIN_NO(69) | 1) +#define MT6797_GPIO69__FUNC_I2S3_LRCK (MTK_PIN_NO(69) | 2) +#define MT6797_GPIO69__FUNC_I2S1_LRCK (MTK_PIN_NO(69) | 3) +#define MT6797_GPIO69__FUNC_I2S2_LRCK (MTK_PIN_NO(69) | 4) +#define MT6797_GPIO69__FUNC_DBG_MON_A2 (MTK_PIN_NO(69) | 7) + +#define MT6797_GPIO70__FUNC_GPIO70 (MTK_PIN_NO(70) | 0) +#define MT6797_GPIO70__FUNC_I2S0_BCK (MTK_PIN_NO(70) | 1) +#define MT6797_GPIO70__FUNC_I2S3_BCK (MTK_PIN_NO(70) | 2) +#define MT6797_GPIO70__FUNC_I2S1_BCK (MTK_PIN_NO(70) | 3) +#define MT6797_GPIO70__FUNC_I2S2_BCK (MTK_PIN_NO(70) | 4) +#define MT6797_GPIO70__FUNC_DBG_MON_A3 (MTK_PIN_NO(70) | 7) + +#define MT6797_GPIO71__FUNC_GPIO71 (MTK_PIN_NO(71) | 0) +#define MT6797_GPIO71__FUNC_I2S0_MCK (MTK_PIN_NO(71) | 1) +#define MT6797_GPIO71__FUNC_I2S3_MCK (MTK_PIN_NO(71) | 2) +#define MT6797_GPIO71__FUNC_I2S1_MCK (MTK_PIN_NO(71) | 3) +#define MT6797_GPIO71__FUNC_I2S2_MCK (MTK_PIN_NO(71) | 4) +#define MT6797_GPIO71__FUNC_DBG_MON_A4 (MTK_PIN_NO(71) | 7) + +#define MT6797_GPIO72__FUNC_GPIO72 (MTK_PIN_NO(72) | 0) +/* #define MT6797_GPIO72__FUNC_I2S0_DI (MTK_PIN_NO(72) | 1) */ +#define MT6797_GPIO72__FUNC_I2S0_DI (MTK_PIN_NO(72) | 2) +/* #define MT6797_GPIO72__FUNC_I2S2_DI (MTK_PIN_NO(72) | 3) */ +#define MT6797_GPIO72__FUNC_I2S2_DI (MTK_PIN_NO(72) | 4) +#define MT6797_GPIO72__FUNC_DBG_MON_A5 (MTK_PIN_NO(72) | 7) + +#define MT6797_GPIO73__FUNC_GPIO73 (MTK_PIN_NO(73) | 0) +/* #define MT6797_GPIO73__FUNC_I2S3_DO (MTK_PIN_NO(73) | 1) */ +#define MT6797_GPIO73__FUNC_I2S3_DO (MTK_PIN_NO(73) | 2) +/* #define MT6797_GPIO73__FUNC_I2S1_DO (MTK_PIN_NO(73) | 3) */ +#define MT6797_GPIO73__FUNC_I2S1_DO (MTK_PIN_NO(73) | 4) +#define MT6797_GPIO73__FUNC_DBG_MON_A6 (MTK_PIN_NO(73) | 7) + +#define MT6797_GPIO74__FUNC_GPIO74 (MTK_PIN_NO(74) | 0) +#define MT6797_GPIO74__FUNC_SCL3_0 (MTK_PIN_NO(74) | 1) +#define MT6797_GPIO74__FUNC_AUXIF_CLK1 (MTK_PIN_NO(74) | 7) + +#define MT6797_GPIO75__FUNC_GPIO75 (MTK_PIN_NO(75) | 0) +#define MT6797_GPIO75__FUNC_SDA3_0 (MTK_PIN_NO(75) | 1) +#define MT6797_GPIO75__FUNC_AUXIF_ST1 (MTK_PIN_NO(75) | 7) + +#define MT6797_GPIO76__FUNC_GPIO76 (MTK_PIN_NO(76) | 0) +#define MT6797_GPIO76__FUNC_CONN_HRST_B (MTK_PIN_NO(76) | 1) +#define MT6797_GPIO76__FUNC_C2K_DM_EINT0 (MTK_PIN_NO(76) | 7) + +#define MT6797_GPIO77__FUNC_GPIO77 (MTK_PIN_NO(77) | 0) +#define MT6797_GPIO77__FUNC_CONN_TOP_CLK (MTK_PIN_NO(77) | 1) +#define MT6797_GPIO77__FUNC_C2K_DM_EINT1 (MTK_PIN_NO(77) | 7) + +#define MT6797_GPIO78__FUNC_GPIO78 (MTK_PIN_NO(78) | 0) +#define MT6797_GPIO78__FUNC_CONN_TOP_DATA (MTK_PIN_NO(78) | 1) +#define MT6797_GPIO78__FUNC_C2K_DM_EINT2 (MTK_PIN_NO(78) | 7) + +#define MT6797_GPIO79__FUNC_GPIO79 (MTK_PIN_NO(79) | 0) +#define MT6797_GPIO79__FUNC_CONN_WB_PTA (MTK_PIN_NO(79) | 1) +#define MT6797_GPIO79__FUNC_C2K_DM_EINT3 (MTK_PIN_NO(79) | 7) + +#define MT6797_GPIO80__FUNC_GPIO80 (MTK_PIN_NO(80) | 0) +#define MT6797_GPIO80__FUNC_CONN_WF_HB0 (MTK_PIN_NO(80) | 1) +#define MT6797_GPIO80__FUNC_C2K_EINT0 (MTK_PIN_NO(80) | 7) + +#define MT6797_GPIO81__FUNC_GPIO81 (MTK_PIN_NO(81) | 0) +#define MT6797_GPIO81__FUNC_CONN_WF_HB1 (MTK_PIN_NO(81) | 1) +#define MT6797_GPIO81__FUNC_C2K_EINT1 (MTK_PIN_NO(81) | 7) + +#define MT6797_GPIO82__FUNC_GPIO82 (MTK_PIN_NO(82) | 0) +#define MT6797_GPIO82__FUNC_CONN_WF_HB2 (MTK_PIN_NO(82) | 1) +#define MT6797_GPIO82__FUNC_MD_CLKM0 (MTK_PIN_NO(82) | 7) + +#define MT6797_GPIO83__FUNC_GPIO83 (MTK_PIN_NO(83) | 0) +#define MT6797_GPIO83__FUNC_CONN_BT_CLK (MTK_PIN_NO(83) | 1) +#define MT6797_GPIO83__FUNC_MD_CLKM1 (MTK_PIN_NO(83) | 7) + +#define MT6797_GPIO84__FUNC_GPIO84 (MTK_PIN_NO(84) | 0) +#define MT6797_GPIO84__FUNC_CONN_BT_DATA (MTK_PIN_NO(84) | 1) + +#define MT6797_GPIO85__FUNC_GPIO85 (MTK_PIN_NO(85) | 0) +#define MT6797_GPIO85__FUNC_EINT8 (MTK_PIN_NO(85) | 1) +#define MT6797_GPIO85__FUNC_I2S1_LRCK (MTK_PIN_NO(85) | 2) +#define MT6797_GPIO85__FUNC_I2S2_LRCK (MTK_PIN_NO(85) | 3) +#define MT6797_GPIO85__FUNC_URXD1 (MTK_PIN_NO(85) | 4) +#define MT6797_GPIO85__FUNC_MD_URXD0 (MTK_PIN_NO(85) | 5) +#define MT6797_GPIO85__FUNC_DBG_MON_A7 (MTK_PIN_NO(85) | 7) + +#define MT6797_GPIO86__FUNC_GPIO86 (MTK_PIN_NO(86) | 0) +#define MT6797_GPIO86__FUNC_EINT9 (MTK_PIN_NO(86) | 1) +#define MT6797_GPIO86__FUNC_I2S1_BCK (MTK_PIN_NO(86) | 2) +#define MT6797_GPIO86__FUNC_I2S2_BCK (MTK_PIN_NO(86) | 3) +#define MT6797_GPIO86__FUNC_UTXD1 (MTK_PIN_NO(86) | 4) +#define MT6797_GPIO86__FUNC_MD_UTXD0 (MTK_PIN_NO(86) | 5) +#define MT6797_GPIO86__FUNC_DBG_MON_A8 (MTK_PIN_NO(86) | 7) + +#define MT6797_GPIO87__FUNC_GPIO87 (MTK_PIN_NO(87) | 0) +#define MT6797_GPIO87__FUNC_EINT10 (MTK_PIN_NO(87) | 1) +#define MT6797_GPIO87__FUNC_I2S1_MCK (MTK_PIN_NO(87) | 2) +#define MT6797_GPIO87__FUNC_I2S2_MCK (MTK_PIN_NO(87) | 3) +#define MT6797_GPIO87__FUNC_URTS1 (MTK_PIN_NO(87) | 4) +#define MT6797_GPIO87__FUNC_MD_URXD1 (MTK_PIN_NO(87) | 5) +#define MT6797_GPIO87__FUNC_DBG_MON_A9 (MTK_PIN_NO(87) | 7) + +#define MT6797_GPIO88__FUNC_GPIO88 (MTK_PIN_NO(88) | 0) +#define MT6797_GPIO88__FUNC_EINT11 (MTK_PIN_NO(88) | 1) +#define MT6797_GPIO88__FUNC_I2S1_DO (MTK_PIN_NO(88) | 2) +#define MT6797_GPIO88__FUNC_I2S2_DI (MTK_PIN_NO(88) | 3) +#define MT6797_GPIO88__FUNC_UCTS1 (MTK_PIN_NO(88) | 4) +#define MT6797_GPIO88__FUNC_MD_UTXD1 (MTK_PIN_NO(88) | 5) +#define MT6797_GPIO88__FUNC_DBG_MON_A10 (MTK_PIN_NO(88) | 7) + +#define MT6797_GPIO89__FUNC_GPIO89 (MTK_PIN_NO(89) | 0) +#define MT6797_GPIO89__FUNC_EINT12 (MTK_PIN_NO(89) | 1) +#define MT6797_GPIO89__FUNC_IRTX_OUT (MTK_PIN_NO(89) | 2) +#define MT6797_GPIO89__FUNC_CLKM0 (MTK_PIN_NO(89) | 3) +#define MT6797_GPIO89__FUNC_PCM1_SYNC (MTK_PIN_NO(89) | 4) +#define MT6797_GPIO89__FUNC_URTS0 (MTK_PIN_NO(89) | 5) +#define MT6797_GPIO89__FUNC_DBG_MON_A11 (MTK_PIN_NO(89) | 7) + +#define MT6797_GPIO90__FUNC_GPIO90 (MTK_PIN_NO(90) | 0) +#define MT6797_GPIO90__FUNC_EINT13 (MTK_PIN_NO(90) | 1) +#define MT6797_GPIO90__FUNC_CMFLASH (MTK_PIN_NO(90) | 2) +#define MT6797_GPIO90__FUNC_CLKM1 (MTK_PIN_NO(90) | 3) +#define MT6797_GPIO90__FUNC_PCM1_CLK (MTK_PIN_NO(90) | 4) +#define MT6797_GPIO90__FUNC_UCTS0 (MTK_PIN_NO(90) | 5) +#define MT6797_GPIO90__FUNC_C2K_DM_EINT0 (MTK_PIN_NO(90) | 7) + +#define MT6797_GPIO91__FUNC_GPIO91 (MTK_PIN_NO(91) | 0) +#define MT6797_GPIO91__FUNC_EINT14 (MTK_PIN_NO(91) | 1) +#define MT6797_GPIO91__FUNC_PWM_A (MTK_PIN_NO(91) | 2) +#define MT6797_GPIO91__FUNC_CLKM2 (MTK_PIN_NO(91) | 3) +#define MT6797_GPIO91__FUNC_PCM1_DI (MTK_PIN_NO(91) | 4) +#define MT6797_GPIO91__FUNC_SDA0_3 (MTK_PIN_NO(91) | 5) +#define MT6797_GPIO91__FUNC_C2K_DM_EINT1 (MTK_PIN_NO(91) | 7) + +#define MT6797_GPIO92__FUNC_GPIO92 (MTK_PIN_NO(92) | 0) +#define MT6797_GPIO92__FUNC_EINT15 (MTK_PIN_NO(92) | 1) +#define MT6797_GPIO92__FUNC_PWM_B (MTK_PIN_NO(92) | 2) +#define MT6797_GPIO92__FUNC_CLKM3 (MTK_PIN_NO(92) | 3) +#define MT6797_GPIO92__FUNC_PCM1_DO0 (MTK_PIN_NO(92) | 4) +#define MT6797_GPIO92__FUNC_SCL0_3 (MTK_PIN_NO(92) | 5) + +#define MT6797_GPIO93__FUNC_GPIO93 (MTK_PIN_NO(93) | 0) +#define MT6797_GPIO93__FUNC_EINT16 (MTK_PIN_NO(93) | 1) +#define MT6797_GPIO93__FUNC_IDDIG (MTK_PIN_NO(93) | 2) +#define MT6797_GPIO93__FUNC_CLKM4 (MTK_PIN_NO(93) | 3) +#define MT6797_GPIO93__FUNC_PCM1_DO1 (MTK_PIN_NO(93) | 4) +#define MT6797_GPIO93__FUNC_MD_INT2 (MTK_PIN_NO(93) | 5) +#define MT6797_GPIO93__FUNC_DROP_ZONE (MTK_PIN_NO(93) | 7) + +#define MT6797_GPIO94__FUNC_GPIO94 (MTK_PIN_NO(94) | 0) +#define MT6797_GPIO94__FUNC_USB_DRVVBUS (MTK_PIN_NO(94) | 1) +#define MT6797_GPIO94__FUNC_PWM_C (MTK_PIN_NO(94) | 2) +#define MT6797_GPIO94__FUNC_CLKM5 (MTK_PIN_NO(94) | 3) + +#define MT6797_GPIO95__FUNC_GPIO95 (MTK_PIN_NO(95) | 0) +#define MT6797_GPIO95__FUNC_SDA2_0 (MTK_PIN_NO(95) | 1) +#define MT6797_GPIO95__FUNC_AUXIF_ST0 (MTK_PIN_NO(95) | 7) + +#define MT6797_GPIO96__FUNC_GPIO96 (MTK_PIN_NO(96) | 0) +#define MT6797_GPIO96__FUNC_SCL2_0 (MTK_PIN_NO(96) | 1) +#define MT6797_GPIO96__FUNC_AUXIF_CLK0 (MTK_PIN_NO(96) | 7) + +#define MT6797_GPIO97__FUNC_GPIO97 (MTK_PIN_NO(97) | 0) +#define MT6797_GPIO97__FUNC_URXD0 (MTK_PIN_NO(97) | 1) +#define MT6797_GPIO97__FUNC_UTXD0 (MTK_PIN_NO(97) | 2) +#define MT6797_GPIO97__FUNC_MD_URXD0 (MTK_PIN_NO(97) | 3) +#define MT6797_GPIO97__FUNC_MD_URXD1 (MTK_PIN_NO(97) | 4) +#define MT6797_GPIO97__FUNC_MD_URXD2 (MTK_PIN_NO(97) | 5) +#define MT6797_GPIO97__FUNC_C2K_URXD0 (MTK_PIN_NO(97) | 6) +#define MT6797_GPIO97__FUNC_C2K_URXD1 (MTK_PIN_NO(97) | 7) + +#define MT6797_GPIO98__FUNC_GPIO98 (MTK_PIN_NO(98) | 0) +#define MT6797_GPIO98__FUNC_UTXD0 (MTK_PIN_NO(98) | 1) +#define MT6797_GPIO98__FUNC_URXD0 (MTK_PIN_NO(98) | 2) +#define MT6797_GPIO98__FUNC_MD_UTXD0 (MTK_PIN_NO(98) | 3) +#define MT6797_GPIO98__FUNC_MD_UTXD1 (MTK_PIN_NO(98) | 4) +#define MT6797_GPIO98__FUNC_MD_UTXD2 (MTK_PIN_NO(98) | 5) +#define MT6797_GPIO98__FUNC_C2K_UTXD0 (MTK_PIN_NO(98) | 6) +#define MT6797_GPIO98__FUNC_C2K_UTXD1 (MTK_PIN_NO(98) | 7) + +#define MT6797_GPIO99__FUNC_GPIO99 (MTK_PIN_NO(99) | 0) +#define MT6797_GPIO99__FUNC_RTC32K_CK (MTK_PIN_NO(99) | 1) + +#define MT6797_GPIO100__FUNC_GPIO100 (MTK_PIN_NO(100) | 0) +#define MT6797_GPIO100__FUNC_SRCLKENAI0 (MTK_PIN_NO(100) | 1) + +#define MT6797_GPIO101__FUNC_GPIO101 (MTK_PIN_NO(101) | 0) +#define MT6797_GPIO101__FUNC_SRCLKENAI1 (MTK_PIN_NO(101) | 1) + +#define MT6797_GPIO102__FUNC_GPIO102 (MTK_PIN_NO(102) | 0) +#define MT6797_GPIO102__FUNC_SRCLKENA0 (MTK_PIN_NO(102) | 1) + +#define MT6797_GPIO103__FUNC_GPIO103 (MTK_PIN_NO(103) | 0) +#define MT6797_GPIO103__FUNC_SRCLKENA1 (MTK_PIN_NO(103) | 1) + +#define MT6797_GPIO104__FUNC_GPIO104 (MTK_PIN_NO(104) | 0) +#define MT6797_GPIO104__FUNC_SYSRSTB (MTK_PIN_NO(104) | 1) + +#define MT6797_GPIO105__FUNC_GPIO105 (MTK_PIN_NO(105) | 0) +#define MT6797_GPIO105__FUNC_WATCHDOG (MTK_PIN_NO(105) | 1) + +#define MT6797_GPIO106__FUNC_GPIO106 (MTK_PIN_NO(106) | 0) +#define MT6797_GPIO106__FUNC_KPROW0 (MTK_PIN_NO(106) | 1) +#define MT6797_GPIO106__FUNC_CMFLASH (MTK_PIN_NO(106) | 2) +#define MT6797_GPIO106__FUNC_CLKM4 (MTK_PIN_NO(106) | 3) +#define MT6797_GPIO106__FUNC_TP_GPIO0_AO (MTK_PIN_NO(106) | 4) +#define MT6797_GPIO106__FUNC_IRTX_OUT (MTK_PIN_NO(106) | 5) + +#define MT6797_GPIO107__FUNC_GPIO107 (MTK_PIN_NO(107) | 0) +#define MT6797_GPIO107__FUNC_KPROW1 (MTK_PIN_NO(107) | 1) +#define MT6797_GPIO107__FUNC_IDDIG (MTK_PIN_NO(107) | 2) +#define MT6797_GPIO107__FUNC_CLKM5 (MTK_PIN_NO(107) | 3) +#define MT6797_GPIO107__FUNC_TP_GPIO1_AO (MTK_PIN_NO(107) | 4) +#define MT6797_GPIO107__FUNC_I2S1_BCK (MTK_PIN_NO(107) | 5) +#define MT6797_GPIO107__FUNC_DAP_SIB1_SWD (MTK_PIN_NO(107) | 7) + +#define MT6797_GPIO108__FUNC_GPIO108 (MTK_PIN_NO(108) | 0) +#define MT6797_GPIO108__FUNC_KPROW2 (MTK_PIN_NO(108) | 1) +#define MT6797_GPIO108__FUNC_USB_DRVVBUS (MTK_PIN_NO(108) | 2) +#define MT6797_GPIO108__FUNC_PWM_A (MTK_PIN_NO(108) | 3) +#define MT6797_GPIO108__FUNC_CMFLASH (MTK_PIN_NO(108) | 4) +#define MT6797_GPIO108__FUNC_I2S1_LRCK (MTK_PIN_NO(108) | 5) +#define MT6797_GPIO108__FUNC_DAP_SIB1_SWCK (MTK_PIN_NO(108) | 7) + +#define MT6797_GPIO109__FUNC_GPIO109 (MTK_PIN_NO(109) | 0) +#define MT6797_GPIO109__FUNC_KPCOL0 (MTK_PIN_NO(109) | 1) + +#define MT6797_GPIO110__FUNC_GPIO110 (MTK_PIN_NO(110) | 0) +#define MT6797_GPIO110__FUNC_KPCOL1 (MTK_PIN_NO(110) | 1) +#define MT6797_GPIO110__FUNC_SDA1_3 (MTK_PIN_NO(110) | 2) +#define MT6797_GPIO110__FUNC_PWM_B (MTK_PIN_NO(110) | 3) +#define MT6797_GPIO110__FUNC_CLKM0 (MTK_PIN_NO(110) | 4) +#define MT6797_GPIO110__FUNC_I2S1_DO (MTK_PIN_NO(110) | 5) +#define MT6797_GPIO110__FUNC_C2K_DM_EINT3 (MTK_PIN_NO(110) | 7) + +#define MT6797_GPIO111__FUNC_GPIO111 (MTK_PIN_NO(111) | 0) +#define MT6797_GPIO111__FUNC_KPCOL2 (MTK_PIN_NO(111) | 1) +#define MT6797_GPIO111__FUNC_SCL1_3 (MTK_PIN_NO(111) | 2) +#define MT6797_GPIO111__FUNC_PWM_C (MTK_PIN_NO(111) | 3) +#define MT6797_GPIO111__FUNC_DISP_PWM (MTK_PIN_NO(111) | 4) +#define MT6797_GPIO111__FUNC_I2S1_MCK (MTK_PIN_NO(111) | 5) +#define MT6797_GPIO111__FUNC_C2K_DM_EINT2 (MTK_PIN_NO(111) | 7) + +#define MT6797_GPIO112__FUNC_GPIO112 (MTK_PIN_NO(112) | 0) +#define MT6797_GPIO112__FUNC_MD_INT1_C2K_UIM1_HOT_PLUG_IN (MTK_PIN_NO(112) | 1) +#define MT6797_GPIO112__FUNC_C2K_DM_EINT1 (MTK_PIN_NO(112) | 7) + +#define MT6797_GPIO113__FUNC_GPIO113 (MTK_PIN_NO(113) | 0) +#define MT6797_GPIO113__FUNC_MD_INT0_C2K_UIM0_HOT_PLUG_IN (MTK_PIN_NO(113) | 1) +#define MT6797_GPIO113__FUNC_C2K_DM_EINT0 (MTK_PIN_NO(113) | 7) + +#define MT6797_GPIO114__FUNC_GPIO114 (MTK_PIN_NO(114) | 0) +#define MT6797_GPIO114__FUNC_MSDC0_DAT0 (MTK_PIN_NO(114) | 1) + +#define MT6797_GPIO115__FUNC_GPIO115 (MTK_PIN_NO(115) | 0) +#define MT6797_GPIO115__FUNC_MSDC0_DAT1 (MTK_PIN_NO(115) | 1) + +#define MT6797_GPIO116__FUNC_GPIO116 (MTK_PIN_NO(116) | 0) +#define MT6797_GPIO116__FUNC_MSDC0_DAT2 (MTK_PIN_NO(116) | 1) + +#define MT6797_GPIO117__FUNC_GPIO117 (MTK_PIN_NO(117) | 0) +#define MT6797_GPIO117__FUNC_MSDC0_DAT3 (MTK_PIN_NO(117) | 1) + +#define MT6797_GPIO118__FUNC_GPIO118 (MTK_PIN_NO(118) | 0) +#define MT6797_GPIO118__FUNC_MSDC0_DAT4 (MTK_PIN_NO(118) | 1) + +#define MT6797_GPIO119__FUNC_GPIO119 (MTK_PIN_NO(119) | 0) +#define MT6797_GPIO119__FUNC_MSDC0_DAT5 (MTK_PIN_NO(119) | 1) + +#define MT6797_GPIO120__FUNC_GPIO120 (MTK_PIN_NO(120) | 0) +#define MT6797_GPIO120__FUNC_MSDC0_DAT6 (MTK_PIN_NO(120) | 1) + +#define MT6797_GPIO121__FUNC_GPIO121 (MTK_PIN_NO(121) | 0) +#define MT6797_GPIO121__FUNC_MSDC0_DAT7 (MTK_PIN_NO(121) | 1) + +#define MT6797_GPIO122__FUNC_GPIO122 (MTK_PIN_NO(122) | 0) +#define MT6797_GPIO122__FUNC_MSDC0_CMD (MTK_PIN_NO(122) | 1) + +#define MT6797_GPIO123__FUNC_GPIO123 (MTK_PIN_NO(123) | 0) +#define MT6797_GPIO123__FUNC_MSDC0_CLK (MTK_PIN_NO(123) | 1) + +#define MT6797_GPIO124__FUNC_GPIO124 (MTK_PIN_NO(124) | 0) +#define MT6797_GPIO124__FUNC_MSDC0_DSL (MTK_PIN_NO(124) | 1) + +#define MT6797_GPIO125__FUNC_GPIO125 (MTK_PIN_NO(125) | 0) +#define MT6797_GPIO125__FUNC_MSDC0_RSTB (MTK_PIN_NO(125) | 1) + +#define MT6797_GPIO126__FUNC_GPIO126 (MTK_PIN_NO(126) | 0) +#define MT6797_GPIO126__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(126) | 1) +#define MT6797_GPIO126__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(126) | 2) +#define MT6797_GPIO126__FUNC_C2K_UIM0_CLK (MTK_PIN_NO(126) | 3) +#define MT6797_GPIO126__FUNC_C2K_UIM1_CLK (MTK_PIN_NO(126) | 4) + +#define MT6797_GPIO127__FUNC_GPIO127 (MTK_PIN_NO(127) | 0) +#define MT6797_GPIO127__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(127) | 1) +#define MT6797_GPIO127__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(127) | 2) +#define MT6797_GPIO127__FUNC_C2K_UIM0_RST (MTK_PIN_NO(127) | 3) +#define MT6797_GPIO127__FUNC_C2K_UIM1_RST (MTK_PIN_NO(127) | 4) + +#define MT6797_GPIO128__FUNC_GPIO128 (MTK_PIN_NO(128) | 0) +#define MT6797_GPIO128__FUNC_MD1_SIM1_SIO (MTK_PIN_NO(128) | 1) +#define MT6797_GPIO128__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(128) | 2) +#define MT6797_GPIO128__FUNC_C2K_UIM0_IO (MTK_PIN_NO(128) | 3) +#define MT6797_GPIO128__FUNC_C2K_UIM1_IO (MTK_PIN_NO(128) | 4) + +#define MT6797_GPIO129__FUNC_GPIO129 (MTK_PIN_NO(129) | 0) +#define MT6797_GPIO129__FUNC_MSDC1_CMD (MTK_PIN_NO(129) | 1) +#define MT6797_GPIO129__FUNC_CONN_DSP_JMS (MTK_PIN_NO(129) | 2) +#define MT6797_GPIO129__FUNC_LTE_JTAG_TMS (MTK_PIN_NO(129) | 3) +#define MT6797_GPIO129__FUNC_UDI_TMS (MTK_PIN_NO(129) | 4) +#define MT6797_GPIO129__FUNC_C2K_TMS (MTK_PIN_NO(129) | 5) + +#define MT6797_GPIO130__FUNC_GPIO130 (MTK_PIN_NO(130) | 0) +#define MT6797_GPIO130__FUNC_MSDC1_DAT0 (MTK_PIN_NO(130) | 1) +#define MT6797_GPIO130__FUNC_CONN_DSP_JDI (MTK_PIN_NO(130) | 2) +#define MT6797_GPIO130__FUNC_LTE_JTAG_TDI (MTK_PIN_NO(130) | 3) +#define MT6797_GPIO130__FUNC_UDI_TDI (MTK_PIN_NO(130) | 4) +#define MT6797_GPIO130__FUNC_C2K_TDI (MTK_PIN_NO(130) | 5) + +#define MT6797_GPIO131__FUNC_GPIO131 (MTK_PIN_NO(131) | 0) +#define MT6797_GPIO131__FUNC_MSDC1_DAT1 (MTK_PIN_NO(131) | 1) +#define MT6797_GPIO131__FUNC_CONN_DSP_JDO (MTK_PIN_NO(131) | 2) +#define MT6797_GPIO131__FUNC_LTE_JTAG_TDO (MTK_PIN_NO(131) | 3) +#define MT6797_GPIO131__FUNC_UDI_TDO (MTK_PIN_NO(131) | 4) +#define MT6797_GPIO131__FUNC_C2K_TDO (MTK_PIN_NO(131) | 5) + +#define MT6797_GPIO132__FUNC_GPIO132 (MTK_PIN_NO(132) | 0) +#define MT6797_GPIO132__FUNC_MSDC1_DAT2 (MTK_PIN_NO(132) | 1) +#define MT6797_GPIO132__FUNC_C2K_RTCK (MTK_PIN_NO(132) | 5) + +#define MT6797_GPIO133__FUNC_GPIO133 (MTK_PIN_NO(133) | 0) +#define MT6797_GPIO133__FUNC_MSDC1_DAT3 (MTK_PIN_NO(133) | 1) +#define MT6797_GPIO133__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(133) | 2) +#define MT6797_GPIO133__FUNC_LTE_JTAG_TRSTN (MTK_PIN_NO(133) | 3) +#define MT6797_GPIO133__FUNC_UDI_NTRST (MTK_PIN_NO(133) | 4) +#define MT6797_GPIO133__FUNC_C2K_NTRST (MTK_PIN_NO(133) | 5) + +#define MT6797_GPIO134__FUNC_GPIO134 (MTK_PIN_NO(134) | 0) +#define MT6797_GPIO134__FUNC_MSDC1_CLK (MTK_PIN_NO(134) | 1) +#define MT6797_GPIO134__FUNC_CONN_DSP_JCK (MTK_PIN_NO(134) | 2) +#define MT6797_GPIO134__FUNC_LTE_JTAG_TCK (MTK_PIN_NO(134) | 3) +#define MT6797_GPIO134__FUNC_UDI_TCK_XI (MTK_PIN_NO(134) | 4) +#define MT6797_GPIO134__FUNC_C2K_TCK (MTK_PIN_NO(134) | 5) + +#define MT6797_GPIO135__FUNC_GPIO135 (MTK_PIN_NO(135) | 0) +#define MT6797_GPIO135__FUNC_TDM_LRCK (MTK_PIN_NO(135) | 1) +#define MT6797_GPIO135__FUNC_I2S0_LRCK (MTK_PIN_NO(135) | 2) +#define MT6797_GPIO135__FUNC_CLKM0 (MTK_PIN_NO(135) | 3) +#define MT6797_GPIO135__FUNC_PCM1_SYNC (MTK_PIN_NO(135) | 4) +#define MT6797_GPIO135__FUNC_PWM_A (MTK_PIN_NO(135) | 5) +#define MT6797_GPIO135__FUNC_DBG_MON_A12 (MTK_PIN_NO(135) | 7) + +#define MT6797_GPIO136__FUNC_GPIO136 (MTK_PIN_NO(136) | 0) +#define MT6797_GPIO136__FUNC_TDM_BCK (MTK_PIN_NO(136) | 1) +#define MT6797_GPIO136__FUNC_I2S0_BCK (MTK_PIN_NO(136) | 2) +#define MT6797_GPIO136__FUNC_CLKM1 (MTK_PIN_NO(136) | 3) +#define MT6797_GPIO136__FUNC_PCM1_CLK (MTK_PIN_NO(136) | 4) +#define MT6797_GPIO136__FUNC_PWM_B (MTK_PIN_NO(136) | 5) +#define MT6797_GPIO136__FUNC_DBG_MON_A13 (MTK_PIN_NO(136) | 7) + +#define MT6797_GPIO137__FUNC_GPIO137 (MTK_PIN_NO(137) | 0) +#define MT6797_GPIO137__FUNC_TDM_MCK (MTK_PIN_NO(137) | 1) +#define MT6797_GPIO137__FUNC_I2S0_MCK (MTK_PIN_NO(137) | 2) +#define MT6797_GPIO137__FUNC_CLKM2 (MTK_PIN_NO(137) | 3) +#define MT6797_GPIO137__FUNC_PCM1_DI (MTK_PIN_NO(137) | 4) +#define MT6797_GPIO137__FUNC_IRTX_OUT (MTK_PIN_NO(137) | 5) +#define MT6797_GPIO137__FUNC_DBG_MON_A14 (MTK_PIN_NO(137) | 7) + +#define MT6797_GPIO138__FUNC_GPIO138 (MTK_PIN_NO(138) | 0) +#define MT6797_GPIO138__FUNC_TDM_DATA0 (MTK_PIN_NO(138) | 1) +#define MT6797_GPIO138__FUNC_I2S0_DI (MTK_PIN_NO(138) | 2) +#define MT6797_GPIO138__FUNC_CLKM3 (MTK_PIN_NO(138) | 3) +#define MT6797_GPIO138__FUNC_PCM1_DO0 (MTK_PIN_NO(138) | 4) +#define MT6797_GPIO138__FUNC_PWM_C (MTK_PIN_NO(138) | 5) +#define MT6797_GPIO138__FUNC_SDA3_1 (MTK_PIN_NO(138) | 6) +#define MT6797_GPIO138__FUNC_DBG_MON_A15 (MTK_PIN_NO(138) | 7) + +#define MT6797_GPIO139__FUNC_GPIO139 (MTK_PIN_NO(139) | 0) +#define MT6797_GPIO139__FUNC_TDM_DATA1 (MTK_PIN_NO(139) | 1) +#define MT6797_GPIO139__FUNC_I2S3_DO (MTK_PIN_NO(139) | 2) +#define MT6797_GPIO139__FUNC_CLKM4 (MTK_PIN_NO(139) | 3) +#define MT6797_GPIO139__FUNC_PCM1_DO1 (MTK_PIN_NO(139) | 4) +#define MT6797_GPIO139__FUNC_ANT_SEL2 (MTK_PIN_NO(139) | 5) +#define MT6797_GPIO139__FUNC_SCL3_1 (MTK_PIN_NO(139) | 6) +#define MT6797_GPIO139__FUNC_DBG_MON_A16 (MTK_PIN_NO(139) | 7) + +#define MT6797_GPIO140__FUNC_GPIO140 (MTK_PIN_NO(140) | 0) +#define MT6797_GPIO140__FUNC_TDM_DATA2 (MTK_PIN_NO(140) | 1) +#define MT6797_GPIO140__FUNC_DISP_PWM (MTK_PIN_NO(140) | 2) +#define MT6797_GPIO140__FUNC_CLKM5 (MTK_PIN_NO(140) | 3) +#define MT6797_GPIO140__FUNC_SDA1_4 (MTK_PIN_NO(140) | 4) +#define MT6797_GPIO140__FUNC_ANT_SEL1 (MTK_PIN_NO(140) | 5) +#define MT6797_GPIO140__FUNC_URXD3 (MTK_PIN_NO(140) | 6) +#define MT6797_GPIO140__FUNC_DBG_MON_A17 (MTK_PIN_NO(140) | 7) + +#define MT6797_GPIO141__FUNC_GPIO141 (MTK_PIN_NO(141) | 0) +#define MT6797_GPIO141__FUNC_TDM_DATA3 (MTK_PIN_NO(141) | 1) +#define MT6797_GPIO141__FUNC_CMFLASH (MTK_PIN_NO(141) | 2) +#define MT6797_GPIO141__FUNC_IRTX_OUT (MTK_PIN_NO(141) | 3) +#define MT6797_GPIO141__FUNC_SCL1_4 (MTK_PIN_NO(141) | 4) +#define MT6797_GPIO141__FUNC_ANT_SEL0 (MTK_PIN_NO(141) | 5) +#define MT6797_GPIO141__FUNC_UTXD3 (MTK_PIN_NO(141) | 6) +#define MT6797_GPIO141__FUNC_DBG_MON_A18 (MTK_PIN_NO(141) | 7) + +#define MT6797_GPIO142__FUNC_GPIO142 (MTK_PIN_NO(142) | 0) +#define MT6797_GPIO142__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(142) | 1) +#define MT6797_GPIO142__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(142) | 2) + +#define MT6797_GPIO143__FUNC_GPIO143 (MTK_PIN_NO(143) | 0) +#define MT6797_GPIO143__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(143) | 1) +#define MT6797_GPIO143__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(143) | 2) + +#define MT6797_GPIO144__FUNC_GPIO144 (MTK_PIN_NO(144) | 0) +#define MT6797_GPIO144__FUNC_PWRAP_SPI0_CK (MTK_PIN_NO(144) | 1) + +#define MT6797_GPIO145__FUNC_GPIO145 (MTK_PIN_NO(145) | 0) +#define MT6797_GPIO145__FUNC_PWRAP_SPI0_CSN (MTK_PIN_NO(145) | 1) + +#define MT6797_GPIO146__FUNC_GPIO146 (MTK_PIN_NO(146) | 0) +#define MT6797_GPIO146__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(146) | 1) + +#define MT6797_GPIO147__FUNC_GPIO147 (MTK_PIN_NO(147) | 0) +#define MT6797_GPIO147__FUNC_AUD_DAT_MISO (MTK_PIN_NO(147) | 1) +#define MT6797_GPIO147__FUNC_AUD_DAT_MOSI (MTK_PIN_NO(147) | 2) +#define MT6797_GPIO147__FUNC_VOW_DAT_MISO (MTK_PIN_NO(147) | 3) + +#define MT6797_GPIO148__FUNC_GPIO148 (MTK_PIN_NO(148) | 0) +#define MT6797_GPIO148__FUNC_AUD_DAT_MOSI (MTK_PIN_NO(148) | 1) +#define MT6797_GPIO148__FUNC_AUD_DAT_MISO (MTK_PIN_NO(148) | 2) + +#define MT6797_GPIO149__FUNC_GPIO149 (MTK_PIN_NO(149) | 0) +#define MT6797_GPIO149__FUNC_VOW_CLK_MISO (MTK_PIN_NO(149) | 1) + +#define MT6797_GPIO150__FUNC_GPIO150 (MTK_PIN_NO(150) | 0) +#define MT6797_GPIO150__FUNC_ANC_DAT_MOSI (MTK_PIN_NO(150) | 1) + +#define MT6797_GPIO151__FUNC_GPIO151 (MTK_PIN_NO(151) | 0) +#define MT6797_GPIO151__FUNC_SCL6_0 (MTK_PIN_NO(151) | 1) + +#define MT6797_GPIO152__FUNC_GPIO152 (MTK_PIN_NO(152) | 0) +#define MT6797_GPIO152__FUNC_SDA6_0 (MTK_PIN_NO(152) | 1) + +#define MT6797_GPIO153__FUNC_GPIO153 (MTK_PIN_NO(153) | 0) +#define MT6797_GPIO153__FUNC_SCL7_0 (MTK_PIN_NO(153) | 1) + +#define MT6797_GPIO154__FUNC_GPIO154 (MTK_PIN_NO(154) | 0) +#define MT6797_GPIO154__FUNC_SDA7_0 (MTK_PIN_NO(154) | 1) + +#define MT6797_GPIO155__FUNC_GPIO155 (MTK_PIN_NO(155) | 0) +#define MT6797_GPIO155__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(155) | 1) +#define MT6797_GPIO155__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(155) | 2) +#define MT6797_GPIO155__FUNC_C2K_UIM0_CLK (MTK_PIN_NO(155) | 3) +#define MT6797_GPIO155__FUNC_C2K_UIM1_CLK (MTK_PIN_NO(155) | 4) + +#define MT6797_GPIO156__FUNC_GPIO156 (MTK_PIN_NO(156) | 0) +#define MT6797_GPIO156__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(156) | 1) +#define MT6797_GPIO156__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(156) | 2) +#define MT6797_GPIO156__FUNC_C2K_UIM0_RST (MTK_PIN_NO(156) | 3) +#define MT6797_GPIO156__FUNC_C2K_UIM1_RST (MTK_PIN_NO(156) | 4) + +#define MT6797_GPIO157__FUNC_GPIO157 (MTK_PIN_NO(157) | 0) +#define MT6797_GPIO157__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(157) | 1) +#define MT6797_GPIO157__FUNC_MD1_SIM1_SIO (MTK_PIN_NO(157) | 2) +#define MT6797_GPIO157__FUNC_C2K_UIM0_IO (MTK_PIN_NO(157) | 3) +#define MT6797_GPIO157__FUNC_C2K_UIM1_IO (MTK_PIN_NO(157) | 4) + +#define MT6797_GPIO158__FUNC_GPIO158 (MTK_PIN_NO(158) | 0) +#define MT6797_GPIO158__FUNC_MIPI_TDP0 (MTK_PIN_NO(158) | 1) + +#define MT6797_GPIO159__FUNC_GPIO159 (MTK_PIN_NO(159) | 0) +#define MT6797_GPIO159__FUNC_MIPI_TDN0 (MTK_PIN_NO(159) | 1) + +#define MT6797_GPIO160__FUNC_GPIO160 (MTK_PIN_NO(160) | 0) +#define MT6797_GPIO160__FUNC_MIPI_TDP1 (MTK_PIN_NO(160) | 1) + +#define MT6797_GPIO161__FUNC_GPIO161 (MTK_PIN_NO(161) | 0) +#define MT6797_GPIO161__FUNC_MIPI_TDN1 (MTK_PIN_NO(161) | 1) + +#define MT6797_GPIO162__FUNC_GPIO162 (MTK_PIN_NO(162) | 0) +#define MT6797_GPIO162__FUNC_MIPI_TCP (MTK_PIN_NO(162) | 1) + +#define MT6797_GPIO163__FUNC_GPIO163 (MTK_PIN_NO(163) | 0) +#define MT6797_GPIO163__FUNC_MIPI_TCN (MTK_PIN_NO(163) | 1) + +#define MT6797_GPIO164__FUNC_GPIO164 (MTK_PIN_NO(164) | 0) +#define MT6797_GPIO164__FUNC_MIPI_TDP2 (MTK_PIN_NO(164) | 1) + +#define MT6797_GPIO165__FUNC_GPIO165 (MTK_PIN_NO(165) | 0) +#define MT6797_GPIO165__FUNC_MIPI_TDN2 (MTK_PIN_NO(165) | 1) + +#define MT6797_GPIO166__FUNC_GPIO166 (MTK_PIN_NO(166) | 0) +#define MT6797_GPIO166__FUNC_MIPI_TDP3 (MTK_PIN_NO(166) | 1) + +#define MT6797_GPIO167__FUNC_GPIO167 (MTK_PIN_NO(167) | 0) +#define MT6797_GPIO167__FUNC_MIPI_TDN3 (MTK_PIN_NO(167) | 1) + +#define MT6797_GPIO168__FUNC_GPIO168 (MTK_PIN_NO(168) | 0) +#define MT6797_GPIO168__FUNC_MIPI_TDP0_A (MTK_PIN_NO(168) | 1) + +#define MT6797_GPIO169__FUNC_GPIO169 (MTK_PIN_NO(169) | 0) +#define MT6797_GPIO169__FUNC_MIPI_TDN0_A (MTK_PIN_NO(169) | 1) + +#define MT6797_GPIO170__FUNC_GPIO170 (MTK_PIN_NO(170) | 0) +#define MT6797_GPIO170__FUNC_MIPI_TDP1_A (MTK_PIN_NO(170) | 1) + +#define MT6797_GPIO171__FUNC_GPIO171 (MTK_PIN_NO(171) | 0) +#define MT6797_GPIO171__FUNC_MIPI_TDN1_A (MTK_PIN_NO(171) | 1) + +#define MT6797_GPIO172__FUNC_GPIO172 (MTK_PIN_NO(172) | 0) +#define MT6797_GPIO172__FUNC_MIPI_TCP_A (MTK_PIN_NO(172) | 1) + +#define MT6797_GPIO173__FUNC_GPIO173 (MTK_PIN_NO(173) | 0) +#define MT6797_GPIO173__FUNC_MIPI_TCN_A (MTK_PIN_NO(173) | 1) + +#define MT6797_GPIO174__FUNC_GPIO174 (MTK_PIN_NO(174) | 0) +#define MT6797_GPIO174__FUNC_MIPI_TDP2_A (MTK_PIN_NO(174) | 1) + +#define MT6797_GPIO175__FUNC_GPIO175 (MTK_PIN_NO(175) | 0) +#define MT6797_GPIO175__FUNC_MIPI_TDN2_A (MTK_PIN_NO(175) | 1) + +#define MT6797_GPIO176__FUNC_GPIO176 (MTK_PIN_NO(176) | 0) +#define MT6797_GPIO176__FUNC_MIPI_TDP3_A (MTK_PIN_NO(176) | 1) + +#define MT6797_GPIO177__FUNC_GPIO177 (MTK_PIN_NO(177) | 0) +#define MT6797_GPIO177__FUNC_MIPI_TDN3_A (MTK_PIN_NO(177) | 1) + +#define MT6797_GPIO178__FUNC_GPIO178 (MTK_PIN_NO(178) | 0) +#define MT6797_GPIO178__FUNC_DISP_PWM (MTK_PIN_NO(178) | 1) +#define MT6797_GPIO178__FUNC_PWM_D (MTK_PIN_NO(178) | 2) +#define MT6797_GPIO178__FUNC_CLKM5 (MTK_PIN_NO(178) | 3) +#define MT6797_GPIO178__FUNC_DBG_MON_A19 (MTK_PIN_NO(178) | 7) + +#define MT6797_GPIO179__FUNC_GPIO179 (MTK_PIN_NO(179) | 0) +#define MT6797_GPIO179__FUNC_DSI_TE0 (MTK_PIN_NO(179) | 1) +#define MT6797_GPIO179__FUNC_DBG_MON_A20 (MTK_PIN_NO(179) | 7) + +#define MT6797_GPIO180__FUNC_GPIO180 (MTK_PIN_NO(180) | 0) +#define MT6797_GPIO180__FUNC_LCM_RST (MTK_PIN_NO(180) | 1) +#define MT6797_GPIO180__FUNC_DSI_TE1 (MTK_PIN_NO(180) | 2) +#define MT6797_GPIO180__FUNC_DBG_MON_A21 (MTK_PIN_NO(180) | 7) + +#define MT6797_GPIO181__FUNC_GPIO181 (MTK_PIN_NO(181) | 0) +#define MT6797_GPIO181__FUNC_IDDIG (MTK_PIN_NO(181) | 1) +#define MT6797_GPIO181__FUNC_DSI_TE1 (MTK_PIN_NO(181) | 2) +#define MT6797_GPIO181__FUNC_DBG_MON_A22 (MTK_PIN_NO(181) | 7) + +#define MT6797_GPIO182__FUNC_GPIO182 (MTK_PIN_NO(182) | 0) +#define MT6797_GPIO182__FUNC_TESTMODE (MTK_PIN_NO(182) | 1) + +#define MT6797_GPIO183__FUNC_GPIO183 (MTK_PIN_NO(183) | 0) +#define MT6797_GPIO183__FUNC_RFIC0_BSI_CK (MTK_PIN_NO(183) | 1) +#define MT6797_GPIO183__FUNC_SPM_BSI_CK (MTK_PIN_NO(183) | 2) +#define MT6797_GPIO183__FUNC_DBG_MON_B27 (MTK_PIN_NO(183) | 7) + +#define MT6797_GPIO184__FUNC_GPIO184 (MTK_PIN_NO(184) | 0) +#define MT6797_GPIO184__FUNC_RFIC0_BSI_EN (MTK_PIN_NO(184) | 1) +#define MT6797_GPIO184__FUNC_SPM_BSI_EN (MTK_PIN_NO(184) | 2) +#define MT6797_GPIO184__FUNC_DBG_MON_B28 (MTK_PIN_NO(184) | 7) + +#define MT6797_GPIO185__FUNC_GPIO185 (MTK_PIN_NO(185) | 0) +#define MT6797_GPIO185__FUNC_RFIC0_BSI_D0 (MTK_PIN_NO(185) | 1) +#define MT6797_GPIO185__FUNC_SPM_BSI_D0 (MTK_PIN_NO(185) | 2) +#define MT6797_GPIO185__FUNC_DBG_MON_B29 (MTK_PIN_NO(185) | 7) + +#define MT6797_GPIO186__FUNC_GPIO186 (MTK_PIN_NO(186) | 0) +#define MT6797_GPIO186__FUNC_RFIC0_BSI_D1 (MTK_PIN_NO(186) | 1) +#define MT6797_GPIO186__FUNC_SPM_BSI_D1 (MTK_PIN_NO(186) | 2) +#define MT6797_GPIO186__FUNC_DBG_MON_B30 (MTK_PIN_NO(186) | 7) + +#define MT6797_GPIO187__FUNC_GPIO187 (MTK_PIN_NO(187) | 0) +#define MT6797_GPIO187__FUNC_RFIC0_BSI_D2 (MTK_PIN_NO(187) | 1) +#define MT6797_GPIO187__FUNC_SPM_BSI_D2 (MTK_PIN_NO(187) | 2) +#define MT6797_GPIO187__FUNC_DBG_MON_B31 (MTK_PIN_NO(187) | 7) + +#define MT6797_GPIO188__FUNC_GPIO188 (MTK_PIN_NO(188) | 0) +#define MT6797_GPIO188__FUNC_MIPI0_SCLK (MTK_PIN_NO(188) | 1) +#define MT6797_GPIO188__FUNC_DBG_MON_B32 (MTK_PIN_NO(188) | 7) + +#define MT6797_GPIO189__FUNC_GPIO189 (MTK_PIN_NO(189) | 0) +#define MT6797_GPIO189__FUNC_MIPI0_SDATA (MTK_PIN_NO(189) | 1) + +#define MT6797_GPIO190__FUNC_GPIO190 (MTK_PIN_NO(190) | 0) +#define MT6797_GPIO190__FUNC_MIPI1_SCLK (MTK_PIN_NO(190) | 1) + +#define MT6797_GPIO191__FUNC_GPIO191 (MTK_PIN_NO(191) | 0) +#define MT6797_GPIO191__FUNC_MIPI1_SDATA (MTK_PIN_NO(191) | 1) + +#define MT6797_GPIO192__FUNC_GPIO192 (MTK_PIN_NO(192) | 0) +#define MT6797_GPIO192__FUNC_BPI_BUS4 (MTK_PIN_NO(192) | 1) + +#define MT6797_GPIO193__FUNC_GPIO193 (MTK_PIN_NO(193) | 0) +#define MT6797_GPIO193__FUNC_BPI_BUS5 (MTK_PIN_NO(193) | 1) +#define MT6797_GPIO193__FUNC_DBG_MON_B0 (MTK_PIN_NO(193) | 7) + +#define MT6797_GPIO194__FUNC_GPIO194 (MTK_PIN_NO(194) | 0) +#define MT6797_GPIO194__FUNC_BPI_BUS6 (MTK_PIN_NO(194) | 1) +#define MT6797_GPIO194__FUNC_DBG_MON_B1 (MTK_PIN_NO(194) | 7) + +#define MT6797_GPIO195__FUNC_GPIO195 (MTK_PIN_NO(195) | 0) +#define MT6797_GPIO195__FUNC_BPI_BUS7 (MTK_PIN_NO(195) | 1) +#define MT6797_GPIO195__FUNC_DBG_MON_B2 (MTK_PIN_NO(195) | 7) + +#define MT6797_GPIO196__FUNC_GPIO196 (MTK_PIN_NO(196) | 0) +#define MT6797_GPIO196__FUNC_BPI_BUS8 (MTK_PIN_NO(196) | 1) +#define MT6797_GPIO196__FUNC_DBG_MON_B3 (MTK_PIN_NO(196) | 7) + +#define MT6797_GPIO197__FUNC_GPIO197 (MTK_PIN_NO(197) | 0) +#define MT6797_GPIO197__FUNC_BPI_BUS9 (MTK_PIN_NO(197) | 1) +#define MT6797_GPIO197__FUNC_DBG_MON_B4 (MTK_PIN_NO(197) | 7) + +#define MT6797_GPIO198__FUNC_GPIO198 (MTK_PIN_NO(198) | 0) +#define MT6797_GPIO198__FUNC_BPI_BUS10 (MTK_PIN_NO(198) | 1) +#define MT6797_GPIO198__FUNC_DBG_MON_B5 (MTK_PIN_NO(198) | 7) + +#define MT6797_GPIO199__FUNC_GPIO199 (MTK_PIN_NO(199) | 0) +#define MT6797_GPIO199__FUNC_BPI_BUS11 (MTK_PIN_NO(199) | 1) +#define MT6797_GPIO199__FUNC_DBG_MON_B6 (MTK_PIN_NO(199) | 7) + +#define MT6797_GPIO200__FUNC_GPIO200 (MTK_PIN_NO(200) | 0) +#define MT6797_GPIO200__FUNC_BPI_BUS12 (MTK_PIN_NO(200) | 1) +#define MT6797_GPIO200__FUNC_DBG_MON_B7 (MTK_PIN_NO(200) | 7) + +#define MT6797_GPIO201__FUNC_GPIO201 (MTK_PIN_NO(201) | 0) +#define MT6797_GPIO201__FUNC_BPI_BUS13 (MTK_PIN_NO(201) | 1) +#define MT6797_GPIO201__FUNC_DBG_MON_B8 (MTK_PIN_NO(201) | 7) + +#define MT6797_GPIO202__FUNC_GPIO202 (MTK_PIN_NO(202) | 0) +#define MT6797_GPIO202__FUNC_BPI_BUS14 (MTK_PIN_NO(202) | 1) +#define MT6797_GPIO202__FUNC_DBG_MON_B9 (MTK_PIN_NO(202) | 7) + +#define MT6797_GPIO203__FUNC_GPIO203 (MTK_PIN_NO(203) | 0) +#define MT6797_GPIO203__FUNC_BPI_BUS15 (MTK_PIN_NO(203) | 1) +#define MT6797_GPIO203__FUNC_DBG_MON_B10 (MTK_PIN_NO(203) | 7) + +#define MT6797_GPIO204__FUNC_GPIO204 (MTK_PIN_NO(204) | 0) +#define MT6797_GPIO204__FUNC_BPI_BUS16 (MTK_PIN_NO(204) | 1) +#define MT6797_GPIO204__FUNC_PA_VM0 (MTK_PIN_NO(204) | 2) +#define MT6797_GPIO204__FUNC_DBG_MON_B11 (MTK_PIN_NO(204) | 7) + +#define MT6797_GPIO205__FUNC_GPIO205 (MTK_PIN_NO(205) | 0) +#define MT6797_GPIO205__FUNC_BPI_BUS17 (MTK_PIN_NO(205) | 1) +#define MT6797_GPIO205__FUNC_PA_VM1 (MTK_PIN_NO(205) | 2) +#define MT6797_GPIO205__FUNC_DBG_MON_B12 (MTK_PIN_NO(205) | 7) + +#define MT6797_GPIO206__FUNC_GPIO206 (MTK_PIN_NO(206) | 0) +#define MT6797_GPIO206__FUNC_BPI_BUS18 (MTK_PIN_NO(206) | 1) +#define MT6797_GPIO206__FUNC_TX_SWAP0 (MTK_PIN_NO(206) | 2) +#define MT6797_GPIO206__FUNC_DBG_MON_B13 (MTK_PIN_NO(206) | 7) + +#define MT6797_GPIO207__FUNC_GPIO207 (MTK_PIN_NO(207) | 0) +#define MT6797_GPIO207__FUNC_BPI_BUS19 (MTK_PIN_NO(207) | 1) +#define MT6797_GPIO207__FUNC_TX_SWAP1 (MTK_PIN_NO(207) | 2) +#define MT6797_GPIO207__FUNC_DBG_MON_B14 (MTK_PIN_NO(207) | 7) + +#define MT6797_GPIO208__FUNC_GPIO208 (MTK_PIN_NO(208) | 0) +#define MT6797_GPIO208__FUNC_BPI_BUS20 (MTK_PIN_NO(208) | 1) +#define MT6797_GPIO208__FUNC_TX_SWAP2 (MTK_PIN_NO(208) | 2) +#define MT6797_GPIO208__FUNC_DBG_MON_B15 (MTK_PIN_NO(208) | 7) + +#define MT6797_GPIO209__FUNC_GPIO209 (MTK_PIN_NO(209) | 0) +#define MT6797_GPIO209__FUNC_BPI_BUS21 (MTK_PIN_NO(209) | 1) +#define MT6797_GPIO209__FUNC_TX_SWAP3 (MTK_PIN_NO(209) | 2) +#define MT6797_GPIO209__FUNC_DBG_MON_B16 (MTK_PIN_NO(209) | 7) + +#define MT6797_GPIO210__FUNC_GPIO210 (MTK_PIN_NO(210) | 0) +#define MT6797_GPIO210__FUNC_BPI_BUS22 (MTK_PIN_NO(210) | 1) +#define MT6797_GPIO210__FUNC_DET_BPI0 (MTK_PIN_NO(210) | 2) +#define MT6797_GPIO210__FUNC_DBG_MON_B17 (MTK_PIN_NO(210) | 7) + +#define MT6797_GPIO211__FUNC_GPIO211 (MTK_PIN_NO(211) | 0) +#define MT6797_GPIO211__FUNC_BPI_BUS23 (MTK_PIN_NO(211) | 1) +#define MT6797_GPIO211__FUNC_DET_BPI1 (MTK_PIN_NO(211) | 2) +#define MT6797_GPIO211__FUNC_DBG_MON_B18 (MTK_PIN_NO(211) | 7) + +#define MT6797_GPIO212__FUNC_GPIO212 (MTK_PIN_NO(212) | 0) +#define MT6797_GPIO212__FUNC_BPI_BUS0 (MTK_PIN_NO(212) | 1) +#define MT6797_GPIO212__FUNC_DBG_MON_B19 (MTK_PIN_NO(212) | 7) + +#define MT6797_GPIO213__FUNC_GPIO213 (MTK_PIN_NO(213) | 0) +#define MT6797_GPIO213__FUNC_BPI_BUS1 (MTK_PIN_NO(213) | 1) +#define MT6797_GPIO213__FUNC_DBG_MON_B20 (MTK_PIN_NO(213) | 7) + +#define MT6797_GPIO214__FUNC_GPIO214 (MTK_PIN_NO(214) | 0) +#define MT6797_GPIO214__FUNC_BPI_BUS2 (MTK_PIN_NO(214) | 1) +#define MT6797_GPIO214__FUNC_DBG_MON_B21 (MTK_PIN_NO(214) | 7) + +#define MT6797_GPIO215__FUNC_GPIO215 (MTK_PIN_NO(215) | 0) +#define MT6797_GPIO215__FUNC_BPI_BUS3 (MTK_PIN_NO(215) | 1) +#define MT6797_GPIO215__FUNC_DBG_MON_B22 (MTK_PIN_NO(215) | 7) + +#define MT6797_GPIO216__FUNC_GPIO216 (MTK_PIN_NO(216) | 0) +#define MT6797_GPIO216__FUNC_MIPI2_SCLK (MTK_PIN_NO(216) | 1) +#define MT6797_GPIO216__FUNC_DBG_MON_B23 (MTK_PIN_NO(216) | 7) + +#define MT6797_GPIO217__FUNC_GPIO217 (MTK_PIN_NO(217) | 0) +#define MT6797_GPIO217__FUNC_MIPI2_SDATA (MTK_PIN_NO(217) | 1) +#define MT6797_GPIO217__FUNC_DBG_MON_B24 (MTK_PIN_NO(217) | 7) + +#define MT6797_GPIO218__FUNC_GPIO218 (MTK_PIN_NO(218) | 0) +#define MT6797_GPIO218__FUNC_MIPI3_SCLK (MTK_PIN_NO(218) | 1) +#define MT6797_GPIO218__FUNC_DBG_MON_B25 (MTK_PIN_NO(218) | 7) + +#define MT6797_GPIO219__FUNC_GPIO219 (MTK_PIN_NO(219) | 0) +#define MT6797_GPIO219__FUNC_MIPI3_SDATA (MTK_PIN_NO(219) | 1) +#define MT6797_GPIO219__FUNC_DBG_MON_B26 (MTK_PIN_NO(219) | 7) + +#define MT6797_GPIO220__FUNC_GPIO220 (MTK_PIN_NO(220) | 0) +#define MT6797_GPIO220__FUNC_CONN_WF_IP (MTK_PIN_NO(220) | 1) + +#define MT6797_GPIO221__FUNC_GPIO221 (MTK_PIN_NO(221) | 0) +#define MT6797_GPIO221__FUNC_CONN_WF_IN (MTK_PIN_NO(221) | 1) + +#define MT6797_GPIO222__FUNC_GPIO222 (MTK_PIN_NO(222) | 0) +#define MT6797_GPIO222__FUNC_CONN_WF_QP (MTK_PIN_NO(222) | 1) + +#define MT6797_GPIO223__FUNC_GPIO223 (MTK_PIN_NO(223) | 0) +#define MT6797_GPIO223__FUNC_CONN_WF_QN (MTK_PIN_NO(223) | 1) + +#define MT6797_GPIO224__FUNC_GPIO224 (MTK_PIN_NO(224) | 0) +#define MT6797_GPIO224__FUNC_CONN_BT_IP (MTK_PIN_NO(224) | 1) + +#define MT6797_GPIO225__FUNC_GPIO225 (MTK_PIN_NO(225) | 0) +#define MT6797_GPIO225__FUNC_CONN_BT_IN (MTK_PIN_NO(225) | 1) + +#define MT6797_GPIO226__FUNC_GPIO226 (MTK_PIN_NO(226) | 0) +#define MT6797_GPIO226__FUNC_CONN_BT_QP (MTK_PIN_NO(226) | 1) + +#define MT6797_GPIO227__FUNC_GPIO227 (MTK_PIN_NO(227) | 0) +#define MT6797_GPIO227__FUNC_CONN_BT_QN (MTK_PIN_NO(227) | 1) + +#define MT6797_GPIO228__FUNC_GPIO228 (MTK_PIN_NO(228) | 0) +#define MT6797_GPIO228__FUNC_CONN_GPS_IP (MTK_PIN_NO(228) | 1) + +#define MT6797_GPIO229__FUNC_GPIO229 (MTK_PIN_NO(229) | 0) +#define MT6797_GPIO229__FUNC_CONN_GPS_IN (MTK_PIN_NO(229) | 1) + +#define MT6797_GPIO230__FUNC_GPIO230 (MTK_PIN_NO(230) | 0) +#define MT6797_GPIO230__FUNC_CONN_GPS_QP (MTK_PIN_NO(230) | 1) + +#define MT6797_GPIO231__FUNC_GPIO231 (MTK_PIN_NO(231) | 0) +#define MT6797_GPIO231__FUNC_CONN_GPS_QN (MTK_PIN_NO(231) | 1) + +#define MT6797_GPIO232__FUNC_GPIO232 (MTK_PIN_NO(232) | 0) +#define MT6797_GPIO232__FUNC_URXD1 (MTK_PIN_NO(232) | 1) +#define MT6797_GPIO232__FUNC_UTXD1 (MTK_PIN_NO(232) | 2) +#define MT6797_GPIO232__FUNC_MD_URXD0 (MTK_PIN_NO(232) | 3) +#define MT6797_GPIO232__FUNC_MD_URXD1 (MTK_PIN_NO(232) | 4) +#define MT6797_GPIO232__FUNC_MD_URXD2 (MTK_PIN_NO(232) | 5) +#define MT6797_GPIO232__FUNC_C2K_URXD0 (MTK_PIN_NO(232) | 6) +#define MT6797_GPIO232__FUNC_C2K_URXD1 (MTK_PIN_NO(232) | 7) + +#define MT6797_GPIO233__FUNC_GPIO233 (MTK_PIN_NO(233) | 0) +#define MT6797_GPIO233__FUNC_UTXD1 (MTK_PIN_NO(233) | 1) +#define MT6797_GPIO233__FUNC_URXD1 (MTK_PIN_NO(233) | 2) +#define MT6797_GPIO233__FUNC_MD_UTXD0 (MTK_PIN_NO(233) | 3) +#define MT6797_GPIO233__FUNC_MD_UTXD1 (MTK_PIN_NO(233) | 4) +#define MT6797_GPIO233__FUNC_MD_UTXD2 (MTK_PIN_NO(233) | 5) +#define MT6797_GPIO233__FUNC_C2K_UTXD0 (MTK_PIN_NO(233) | 6) +#define MT6797_GPIO233__FUNC_C2K_UTXD1 (MTK_PIN_NO(233) | 7) + +#define MT6797_GPIO234__FUNC_GPIO234 (MTK_PIN_NO(234) | 0) +#define MT6797_GPIO234__FUNC_SPI1_CLK_B (MTK_PIN_NO(234) | 1) +#define MT6797_GPIO234__FUNC_TP_UTXD1_AO (MTK_PIN_NO(234) | 2) +#define MT6797_GPIO234__FUNC_SCL4_1 (MTK_PIN_NO(234) | 3) +#define MT6797_GPIO234__FUNC_UTXD0 (MTK_PIN_NO(234) | 4) +#define MT6797_GPIO234__FUNC_PWM_A (MTK_PIN_NO(234) | 6) +#define MT6797_GPIO234__FUNC_DBG_MON_A23 (MTK_PIN_NO(234) | 7) + +#define MT6797_GPIO235__FUNC_GPIO235 (MTK_PIN_NO(235) | 0) +#define MT6797_GPIO235__FUNC_SPI1_MI_B (MTK_PIN_NO(235) | 1) +#define MT6797_GPIO235__FUNC_SPI1_MO_B (MTK_PIN_NO(235) | 2) +#define MT6797_GPIO235__FUNC_SDA4_1 (MTK_PIN_NO(235) | 3) +#define MT6797_GPIO235__FUNC_URXD0 (MTK_PIN_NO(235) | 4) +#define MT6797_GPIO235__FUNC_CLKM0 (MTK_PIN_NO(235) | 6) +#define MT6797_GPIO235__FUNC_DBG_MON_A24 (MTK_PIN_NO(235) | 7) + +#define MT6797_GPIO236__FUNC_GPIO236 (MTK_PIN_NO(236) | 0) +#define MT6797_GPIO236__FUNC_SPI1_MO_B (MTK_PIN_NO(236) | 1) +#define MT6797_GPIO236__FUNC_SPI1_MI_B (MTK_PIN_NO(236) | 2) +#define MT6797_GPIO236__FUNC_SCL5_1 (MTK_PIN_NO(236) | 3) +#define MT6797_GPIO236__FUNC_URTS0 (MTK_PIN_NO(236) | 4) +#define MT6797_GPIO236__FUNC_PWM_B (MTK_PIN_NO(236) | 6) +#define MT6797_GPIO236__FUNC_DBG_MON_A25 (MTK_PIN_NO(236) | 7) + +#define MT6797_GPIO237__FUNC_GPIO237 (MTK_PIN_NO(237) | 0) +#define MT6797_GPIO237__FUNC_SPI1_CS_B (MTK_PIN_NO(237) | 1) +#define MT6797_GPIO237__FUNC_TP_URXD1_AO (MTK_PIN_NO(237) | 2) +#define MT6797_GPIO237__FUNC_SDA5_1 (MTK_PIN_NO(237) | 3) +#define MT6797_GPIO237__FUNC_UCTS0 (MTK_PIN_NO(237) | 4) +#define MT6797_GPIO237__FUNC_CLKM1 (MTK_PIN_NO(237) | 6) +#define MT6797_GPIO237__FUNC_DBG_MON_A26 (MTK_PIN_NO(237) | 7) + +#define MT6797_GPIO238__FUNC_GPIO238 (MTK_PIN_NO(238) | 0) +#define MT6797_GPIO238__FUNC_SDA4_0 (MTK_PIN_NO(238) | 1) + +#define MT6797_GPIO239__FUNC_GPIO239 (MTK_PIN_NO(239) | 0) +#define MT6797_GPIO239__FUNC_SCL4_0 (MTK_PIN_NO(239) | 1) + +#define MT6797_GPIO240__FUNC_GPIO240 (MTK_PIN_NO(240) | 0) +#define MT6797_GPIO240__FUNC_SDA5_0 (MTK_PIN_NO(240) | 1) + +#define MT6797_GPIO241__FUNC_GPIO241 (MTK_PIN_NO(241) | 0) +#define MT6797_GPIO241__FUNC_SCL5_0 (MTK_PIN_NO(241) | 1) + +#define MT6797_GPIO242__FUNC_GPIO242 (MTK_PIN_NO(242) | 0) +#define MT6797_GPIO242__FUNC_SPI2_CLK_B (MTK_PIN_NO(242) | 1) +#define MT6797_GPIO242__FUNC_TP_UTXD2_AO (MTK_PIN_NO(242) | 2) +#define MT6797_GPIO242__FUNC_SCL4_2 (MTK_PIN_NO(242) | 3) +#define MT6797_GPIO242__FUNC_UTXD1 (MTK_PIN_NO(242) | 4) +#define MT6797_GPIO242__FUNC_URTS3 (MTK_PIN_NO(242) | 5) +#define MT6797_GPIO242__FUNC_PWM_C (MTK_PIN_NO(242) | 6) +#define MT6797_GPIO242__FUNC_DBG_MON_A27 (MTK_PIN_NO(242) | 7) + +#define MT6797_GPIO243__FUNC_GPIO243 (MTK_PIN_NO(243) | 0) +#define MT6797_GPIO243__FUNC_SPI2_MI_B (MTK_PIN_NO(243) | 1) +#define MT6797_GPIO243__FUNC_SPI2_MO_B (MTK_PIN_NO(243) | 2) +#define MT6797_GPIO243__FUNC_SDA4_2 (MTK_PIN_NO(243) | 3) +#define MT6797_GPIO243__FUNC_URXD1 (MTK_PIN_NO(243) | 4) +#define MT6797_GPIO243__FUNC_UCTS3 (MTK_PIN_NO(243) | 5) +#define MT6797_GPIO243__FUNC_CLKM2 (MTK_PIN_NO(243) | 6) +#define MT6797_GPIO243__FUNC_DBG_MON_A28 (MTK_PIN_NO(243) | 7) + +#define MT6797_GPIO244__FUNC_GPIO244 (MTK_PIN_NO(244) | 0) +#define MT6797_GPIO244__FUNC_SPI2_MO_B (MTK_PIN_NO(244) | 1) +#define MT6797_GPIO244__FUNC_SPI2_MI_B (MTK_PIN_NO(244) | 2) +#define MT6797_GPIO244__FUNC_SCL5_2 (MTK_PIN_NO(244) | 3) +#define MT6797_GPIO244__FUNC_URTS1 (MTK_PIN_NO(244) | 4) +#define MT6797_GPIO244__FUNC_UTXD3 (MTK_PIN_NO(244) | 5) +#define MT6797_GPIO244__FUNC_PWM_D (MTK_PIN_NO(244) | 6) +#define MT6797_GPIO244__FUNC_DBG_MON_A29 (MTK_PIN_NO(244) | 7) + +#define MT6797_GPIO245__FUNC_GPIO245 (MTK_PIN_NO(245) | 0) +#define MT6797_GPIO245__FUNC_SPI2_CS_B (MTK_PIN_NO(245) | 1) +#define MT6797_GPIO245__FUNC_TP_URXD2_AO (MTK_PIN_NO(245) | 2) +#define MT6797_GPIO245__FUNC_SDA5_2 (MTK_PIN_NO(245) | 3) +#define MT6797_GPIO245__FUNC_UCTS1 (MTK_PIN_NO(245) | 4) +#define MT6797_GPIO245__FUNC_URXD3 (MTK_PIN_NO(245) | 5) +#define MT6797_GPIO245__FUNC_CLKM3 (MTK_PIN_NO(245) | 6) +#define MT6797_GPIO245__FUNC_DBG_MON_A30 (MTK_PIN_NO(245) | 7) + +#define MT6797_GPIO246__FUNC_GPIO246 (MTK_PIN_NO(246) | 0) +#define MT6797_GPIO246__FUNC_I2S1_LRCK (MTK_PIN_NO(246) | 1) +#define MT6797_GPIO246__FUNC_I2S2_LRCK (MTK_PIN_NO(246) | 2) +#define MT6797_GPIO246__FUNC_I2S0_LRCK (MTK_PIN_NO(246) | 3) +#define MT6797_GPIO246__FUNC_I2S3_LRCK (MTK_PIN_NO(246) | 4) +#define MT6797_GPIO246__FUNC_PCM0_SYNC (MTK_PIN_NO(246) | 5) +#define MT6797_GPIO246__FUNC_SPI5_CLK_C (MTK_PIN_NO(246) | 6) +#define MT6797_GPIO246__FUNC_DBG_MON_A31 (MTK_PIN_NO(246) | 7) + +#define MT6797_GPIO247__FUNC_GPIO247 (MTK_PIN_NO(247) | 0) +#define MT6797_GPIO247__FUNC_I2S1_BCK (MTK_PIN_NO(247) | 1) +#define MT6797_GPIO247__FUNC_I2S2_BCK (MTK_PIN_NO(247) | 2) +#define MT6797_GPIO247__FUNC_I2S0_BCK (MTK_PIN_NO(247) | 3) +#define MT6797_GPIO247__FUNC_I2S3_BCK (MTK_PIN_NO(247) | 4) +#define MT6797_GPIO247__FUNC_PCM0_CLK (MTK_PIN_NO(247) | 5) +#define MT6797_GPIO247__FUNC_SPI5_MI_C (MTK_PIN_NO(247) | 6) +#define MT6797_GPIO247__FUNC_DBG_MON_A32 (MTK_PIN_NO(247) | 7) + +#define MT6797_GPIO248__FUNC_GPIO248 (MTK_PIN_NO(248) | 0) +/* #define MT6797_GPIO248__FUNC_I2S2_DI (MTK_PIN_NO(248) | 1) */ +#define MT6797_GPIO248__FUNC_I2S2_DI (MTK_PIN_NO(248) | 2) +/* #define MT6797_GPIO248__FUNC_I2S0_DI (MTK_PIN_NO(248) | 3) */ +#define MT6797_GPIO248__FUNC_I2S0_DI (MTK_PIN_NO(248) | 4) +#define MT6797_GPIO248__FUNC_PCM0_DI (MTK_PIN_NO(248) | 5) +#define MT6797_GPIO248__FUNC_SPI5_CS_C (MTK_PIN_NO(248) | 6) + +#define MT6797_GPIO249__FUNC_GPIO249 (MTK_PIN_NO(249) | 0) +/* #define MT6797_GPIO249__FUNC_I2S1_DO (MTK_PIN_NO(249) | 1) */ +#define MT6797_GPIO249__FUNC_I2S1_DO (MTK_PIN_NO(249) | 2) +/* #define MT6797_GPIO249__FUNC_I2S3_DO (MTK_PIN_NO(249) | 3) */ +#define MT6797_GPIO249__FUNC_I2S3_DO (MTK_PIN_NO(249) | 4) +#define MT6797_GPIO249__FUNC_PCM0_DO (MTK_PIN_NO(249) | 5) +#define MT6797_GPIO249__FUNC_SPI5_MO_C (MTK_PIN_NO(249) | 6) +#define MT6797_GPIO249__FUNC_TRAP_SRAM_PWR_BYPASS (MTK_PIN_NO(249) | 7) + +#define MT6797_GPIO250__FUNC_GPIO250 (MTK_PIN_NO(250) | 0) +#define MT6797_GPIO250__FUNC_SPI3_MI (MTK_PIN_NO(250) | 1) +#define MT6797_GPIO250__FUNC_SPI3_MO (MTK_PIN_NO(250) | 2) +#define MT6797_GPIO250__FUNC_IRTX_OUT (MTK_PIN_NO(250) | 3) +#define MT6797_GPIO250__FUNC_TP_URXD1_AO (MTK_PIN_NO(250) | 6) +#define MT6797_GPIO250__FUNC_DROP_ZONE (MTK_PIN_NO(250) | 7) + +#define MT6797_GPIO251__FUNC_GPIO251 (MTK_PIN_NO(251) | 0) +#define MT6797_GPIO251__FUNC_SPI3_MO (MTK_PIN_NO(251) | 1) +#define MT6797_GPIO251__FUNC_SPI3_MI (MTK_PIN_NO(251) | 2) +#define MT6797_GPIO251__FUNC_CMFLASH (MTK_PIN_NO(251) | 3) +#define MT6797_GPIO251__FUNC_TP_UTXD1_AO (MTK_PIN_NO(251) | 6) +#define MT6797_GPIO251__FUNC_C2K_RTCK (MTK_PIN_NO(251) | 7) + +#define MT6797_GPIO252__FUNC_GPIO252 (MTK_PIN_NO(252) | 0) +#define MT6797_GPIO252__FUNC_SPI3_CLK (MTK_PIN_NO(252) | 1) +#define MT6797_GPIO252__FUNC_SCL0_4 (MTK_PIN_NO(252) | 2) +#define MT6797_GPIO252__FUNC_PWM_D (MTK_PIN_NO(252) | 3) +#define MT6797_GPIO252__FUNC_C2K_TMS (MTK_PIN_NO(252) | 7) + +#define MT6797_GPIO253__FUNC_GPIO253 (MTK_PIN_NO(253) | 0) +#define MT6797_GPIO253__FUNC_SPI3_CS (MTK_PIN_NO(253) | 1) +#define MT6797_GPIO253__FUNC_SDA0_4 (MTK_PIN_NO(253) | 2) +#define MT6797_GPIO253__FUNC_PWM_A (MTK_PIN_NO(253) | 3) +#define MT6797_GPIO253__FUNC_C2K_TCK (MTK_PIN_NO(253) | 7) + +#define MT6797_GPIO254__FUNC_GPIO254 (MTK_PIN_NO(254) | 0) +#define MT6797_GPIO254__FUNC_I2S1_MCK (MTK_PIN_NO(254) | 1) +#define MT6797_GPIO254__FUNC_I2S2_MCK (MTK_PIN_NO(254) | 2) +#define MT6797_GPIO254__FUNC_I2S0_MCK (MTK_PIN_NO(254) | 3) +#define MT6797_GPIO254__FUNC_I2S3_MCK (MTK_PIN_NO(254) | 4) +#define MT6797_GPIO254__FUNC_CLKM0 (MTK_PIN_NO(254) | 5) +#define MT6797_GPIO254__FUNC_C2K_TDI (MTK_PIN_NO(254) | 7) + +#define MT6797_GPIO255__FUNC_GPIO255 (MTK_PIN_NO(255) | 0) +#define MT6797_GPIO255__FUNC_CLKM1 (MTK_PIN_NO(255) | 1) +#define MT6797_GPIO255__FUNC_DISP_PWM (MTK_PIN_NO(255) | 2) +#define MT6797_GPIO255__FUNC_PWM_B (MTK_PIN_NO(255) | 3) +#define MT6797_GPIO255__FUNC_TP_GPIO1_AO (MTK_PIN_NO(255) | 6) +#define MT6797_GPIO255__FUNC_C2K_TDO (MTK_PIN_NO(255) | 7) + +#define MT6797_GPIO256__FUNC_GPIO256 (MTK_PIN_NO(256) | 0) +#define MT6797_GPIO256__FUNC_CLKM2 (MTK_PIN_NO(256) | 1) +#define MT6797_GPIO256__FUNC_IRTX_OUT (MTK_PIN_NO(256) | 2) +#define MT6797_GPIO256__FUNC_PWM_C (MTK_PIN_NO(256) | 3) +#define MT6797_GPIO256__FUNC_TP_GPIO0_AO (MTK_PIN_NO(256) | 6) +#define MT6797_GPIO256__FUNC_C2K_NTRST (MTK_PIN_NO(256) | 7) + +#define MT6797_GPIO257__FUNC_GPIO257 (MTK_PIN_NO(257) | 0) +#define MT6797_GPIO257__FUNC_IO_JTAG_TMS (MTK_PIN_NO(257) | 1) +#define MT6797_GPIO257__FUNC_LTE_JTAG_TMS (MTK_PIN_NO(257) | 2) +#define MT6797_GPIO257__FUNC_DFD_TMS (MTK_PIN_NO(257) | 3) +#define MT6797_GPIO257__FUNC_DAP_SIB1_SWD (MTK_PIN_NO(257) | 4) +#define MT6797_GPIO257__FUNC_ANC_JTAG_TMS (MTK_PIN_NO(257) | 5) +#define MT6797_GPIO257__FUNC_SCP_JTAG_TMS (MTK_PIN_NO(257) | 6) +#define MT6797_GPIO257__FUNC_C2K_DM_OTMS (MTK_PIN_NO(257) | 7) + +#define MT6797_GPIO258__FUNC_GPIO258 (MTK_PIN_NO(258) | 0) +#define MT6797_GPIO258__FUNC_IO_JTAG_TCK (MTK_PIN_NO(258) | 1) +#define MT6797_GPIO258__FUNC_LTE_JTAG_TCK (MTK_PIN_NO(258) | 2) +#define MT6797_GPIO258__FUNC_DFD_TCK_XI (MTK_PIN_NO(258) | 3) +#define MT6797_GPIO258__FUNC_DAP_SIB1_SWCK (MTK_PIN_NO(258) | 4) +#define MT6797_GPIO258__FUNC_ANC_JTAG_TCK (MTK_PIN_NO(258) | 5) +#define MT6797_GPIO258__FUNC_SCP_JTAG_TCK (MTK_PIN_NO(258) | 6) +#define MT6797_GPIO258__FUNC_C2K_DM_OTCK (MTK_PIN_NO(258) | 7) + +#define MT6797_GPIO259__FUNC_GPIO259 (MTK_PIN_NO(259) | 0) +#define MT6797_GPIO259__FUNC_IO_JTAG_TDI (MTK_PIN_NO(259) | 1) +#define MT6797_GPIO259__FUNC_LTE_JTAG_TDI (MTK_PIN_NO(259) | 2) +#define MT6797_GPIO259__FUNC_DFD_TDI (MTK_PIN_NO(259) | 3) +#define MT6797_GPIO259__FUNC_ANC_JTAG_TDI (MTK_PIN_NO(259) | 5) +#define MT6797_GPIO259__FUNC_SCP_JTAG_TDI (MTK_PIN_NO(259) | 6) +#define MT6797_GPIO259__FUNC_C2K_DM_OTDI (MTK_PIN_NO(259) | 7) + +#define MT6797_GPIO260__FUNC_GPIO260 (MTK_PIN_NO(260) | 0) +#define MT6797_GPIO260__FUNC_IO_JTAG_TDO (MTK_PIN_NO(260) | 1) +#define MT6797_GPIO260__FUNC_LTE_JTAG_TDO (MTK_PIN_NO(260) | 2) +#define MT6797_GPIO260__FUNC_DFD_TDO (MTK_PIN_NO(260) | 3) +#define MT6797_GPIO260__FUNC_ANC_JTAG_TDO (MTK_PIN_NO(260) | 5) +#define MT6797_GPIO260__FUNC_SCP_JTAG_TDO (MTK_PIN_NO(260) | 6) +#define MT6797_GPIO260__FUNC_C2K_DM_OTDO (MTK_PIN_NO(260) | 7) + +#define MT6797_GPIO261__FUNC_GPIO261 (MTK_PIN_NO(261) | 0) +#define MT6797_GPIO261__FUNC_LTE_JTAG_TRSTN (MTK_PIN_NO(261) | 2) +#define MT6797_GPIO261__FUNC_DFD_NTRST (MTK_PIN_NO(261) | 3) +#define MT6797_GPIO261__FUNC_ANC_JTAG_TRSTN (MTK_PIN_NO(261) | 5) +#define MT6797_GPIO261__FUNC_SCP_JTAG_TRSTN (MTK_PIN_NO(261) | 6) +#define MT6797_GPIO261__FUNC_C2K_DM_JTINTP (MTK_PIN_NO(261) | 7) + +#endif /* __DTS_MT6797_PINFUNC_H */ diff --git a/include/dt-bindings/pinctrl/mt7623-pinfunc.h b/include/dt-bindings/pinctrl/mt7623-pinfunc.h index 4878a67a844c..604fe781c465 100644 --- a/include/dt-bindings/pinctrl/mt7623-pinfunc.h +++ b/include/dt-bindings/pinctrl/mt7623-pinfunc.h @@ -23,20 +23,26 @@ #define MT7623_PIN_5_PWRAP_SPI0_CK2_FUNC_GPIO5 (MTK_PIN_NO(5) | 0) #define MT7623_PIN_5_PWRAP_SPI0_CK2_FUNC_PWRAP_SPICK2_I (MTK_PIN_NO(5) | 1) +#define MT7623_PIN_5_PWRAP_SPI0_CK2_FUNC_ANT_SEL1 (MTK_PIN_NO(5) | 5) #define MT7623_PIN_6_PWRAP_SPI0_CSN2_FUNC_GPIO6 (MTK_PIN_NO(6) | 0) #define MT7623_PIN_6_PWRAP_SPI0_CSN2_FUNC_PWRAP_SPICS2_B_I (MTK_PIN_NO(6) | 1) +#define MT7623_PIN_6_PWRAP_SPI0_CSN2_FUNC_ANT_SEL0 (MTK_PIN_NO(6) | 5) #define MT7623_PIN_7_SPI1_CSN_FUNC_GPIO7 (MTK_PIN_NO(7) | 0) #define MT7623_PIN_7_SPI1_CSN_FUNC_SPI1_CS (MTK_PIN_NO(7) | 1) +#define MT7623_PIN_7_SPI1_CSN_FUNC_KCOL0 (MTK_PIN_NO(7) | 4) #define MT7623_PIN_8_SPI1_MI_FUNC_GPIO8 (MTK_PIN_NO(8) | 0) #define MT7623_PIN_8_SPI1_MI_FUNC_SPI1_MI (MTK_PIN_NO(8) | 1) #define MT7623_PIN_8_SPI1_MI_FUNC_SPI1_MO (MTK_PIN_NO(8) | 2) +#define MT7623_PIN_8_SPI1_MI_FUNC_KCOL1 (MTK_PIN_NO(8) | 4) #define MT7623_PIN_9_SPI1_MO_FUNC_GPIO9 (MTK_PIN_NO(9) | 0) #define MT7623_PIN_9_SPI1_MO_FUNC_SPI1_MO (MTK_PIN_NO(9) | 1) #define MT7623_PIN_9_SPI1_MO_FUNC_SPI1_MI (MTK_PIN_NO(9) | 2) +#define MT7623_PIN_9_SPI1_MO_FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(9) | 3) +#define MT7623_PIN_9_SPI1_MO_FUNC_KCOL2 (MTK_PIN_NO(9) | 4) #define MT7623_PIN_10_RTC32K_CK_FUNC_GPIO10 (MTK_PIN_NO(10) | 0) #define MT7623_PIN_10_RTC32K_CK_FUNC_RTC32K_CK (MTK_PIN_NO(10) | 1) @@ -53,6 +59,7 @@ #define MT7623_PIN_14_GPIO14_FUNC_GPIO14 (MTK_PIN_NO(14) | 0) #define MT7623_PIN_14_GPIO14_FUNC_URXD2 (MTK_PIN_NO(14) | 1) #define MT7623_PIN_14_GPIO14_FUNC_UTXD2 (MTK_PIN_NO(14) | 2) +#define MT7623_PIN_14_GPIO14_FUNC_SRCCLKENAI2 (MTK_PIN_NO(14) | 5) #define MT7623_PIN_15_GPIO15_FUNC_GPIO15 (MTK_PIN_NO(15) | 0) #define MT7623_PIN_15_GPIO15_FUNC_UTXD2 (MTK_PIN_NO(15) | 1) @@ -60,88 +67,139 @@ #define MT7623_PIN_18_PCM_CLK_FUNC_GPIO18 (MTK_PIN_NO(18) | 0) #define MT7623_PIN_18_PCM_CLK_FUNC_PCM_CLK0 (MTK_PIN_NO(18) | 1) +#define MT7623_PIN_18_PCM_CLK_FUNC_MRG_CLK (MTK_PIN_NO(18) | 2) +#define MT7623_PIN_18_PCM_CLK_FUNC_MM_TEST_CK (MTK_PIN_NO(18) | 4) +#define MT7623_PIN_18_PCM_CLK_FUNC_CONN_DSP_JCK (MTK_PIN_NO(18) | 5) #define MT7623_PIN_18_PCM_CLK_FUNC_AP_PCM_CLKO (MTK_PIN_NO(18) | 6) #define MT7623_PIN_19_PCM_SYNC_FUNC_GPIO19 (MTK_PIN_NO(19) | 0) #define MT7623_PIN_19_PCM_SYNC_FUNC_PCM_SYNC (MTK_PIN_NO(19) | 1) +#define MT7623_PIN_19_PCM_SYNC_FUNC_MRG_SYNC (MTK_PIN_NO(19) | 2) +#define MT7623_PIN_19_PCM_SYNC_FUNC_CONN_DSP_JINTP (MTK_PIN_NO(19) | 5) #define MT7623_PIN_19_PCM_SYNC_FUNC_AP_PCM_SYNC (MTK_PIN_NO(19) | 6) #define MT7623_PIN_20_PCM_RX_FUNC_GPIO20 (MTK_PIN_NO(20) | 0) #define MT7623_PIN_20_PCM_RX_FUNC_PCM_RX (MTK_PIN_NO(20) | 1) +#define MT7623_PIN_20_PCM_RX_FUNC_MRG_RX (MTK_PIN_NO(20) | 2) +#define MT7623_PIN_20_PCM_RX_FUNC_MRG_TX (MTK_PIN_NO(20) | 3) #define MT7623_PIN_20_PCM_RX_FUNC_PCM_TX (MTK_PIN_NO(20) | 4) +#define MT7623_PIN_20_PCM_RX_FUNC_CONN_DSP_JDI (MTK_PIN_NO(20) | 5) #define MT7623_PIN_20_PCM_RX_FUNC_AP_PCM_RX (MTK_PIN_NO(20) | 6) #define MT7623_PIN_21_PCM_TX_FUNC_GPIO21 (MTK_PIN_NO(21) | 0) #define MT7623_PIN_21_PCM_TX_FUNC_PCM_TX (MTK_PIN_NO(21) | 1) +#define MT7623_PIN_21_PCM_TX_FUNC_MRG_TX (MTK_PIN_NO(21) | 2) +#define MT7623_PIN_21_PCM_TX_FUNC_MRG_RX (MTK_PIN_NO(21) | 3) #define MT7623_PIN_21_PCM_TX_FUNC_PCM_RX (MTK_PIN_NO(21) | 4) +#define MT7623_PIN_21_PCM_TX_FUNC_CONN_DSP_JMS (MTK_PIN_NO(21) | 5) #define MT7623_PIN_21_PCM_TX_FUNC_AP_PCM_TX (MTK_PIN_NO(21) | 6) #define MT7623_PIN_22_EINT0_FUNC_GPIO22 (MTK_PIN_NO(22) | 0) #define MT7623_PIN_22_EINT0_FUNC_UCTS0 (MTK_PIN_NO(22) | 1) #define MT7623_PIN_22_EINT0_FUNC_PCIE0_PERST_N (MTK_PIN_NO(22) | 2) +#define MT7623_PIN_22_EINT0_FUNC_KCOL3 (MTK_PIN_NO(22) | 3) +#define MT7623_PIN_22_EINT0_FUNC_CONN_DSP_JDO (MTK_PIN_NO(22) | 4) +#define MT7623_PIN_22_EINT0_FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(22) | 5) #define MT7623_PIN_23_EINT1_FUNC_GPIO23 (MTK_PIN_NO(23) | 0) #define MT7623_PIN_23_EINT1_FUNC_URTS0 (MTK_PIN_NO(23) | 1) #define MT7623_PIN_23_EINT1_FUNC_PCIE1_PERST_N (MTK_PIN_NO(23) | 2) +#define MT7623_PIN_23_EINT1_FUNC_KCOL2 (MTK_PIN_NO(23) | 3) +#define MT7623_PIN_23_EINT1_FUNC_CONN_MCU_TDO (MTK_PIN_NO(23) | 4) +#define MT7623_PIN_23_EINT1_FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(23) | 5) #define MT7623_PIN_24_EINT2_FUNC_GPIO24 (MTK_PIN_NO(24) | 0) #define MT7623_PIN_24_EINT2_FUNC_UCTS1 (MTK_PIN_NO(24) | 1) #define MT7623_PIN_24_EINT2_FUNC_PCIE2_PERST_N (MTK_PIN_NO(24) | 2) +#define MT7623_PIN_24_EINT2_FUNC_KCOL1 (MTK_PIN_NO(24) | 3) +#define MT7623_PIN_24_EINT2_FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(24) | 4) #define MT7623_PIN_25_EINT3_FUNC_GPIO25 (MTK_PIN_NO(25) | 0) #define MT7623_PIN_25_EINT3_FUNC_URTS1 (MTK_PIN_NO(25) | 1) +#define MT7623_PIN_25_EINT3_FUNC_KCOL0 (MTK_PIN_NO(25) | 3) +#define MT7623_PIN_25_EINT3_FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(25) | 4) #define MT7623_PIN_26_EINT4_FUNC_GPIO26 (MTK_PIN_NO(26) | 0) #define MT7623_PIN_26_EINT4_FUNC_UCTS3 (MTK_PIN_NO(26) | 1) +#define MT7623_PIN_26_EINT4_FUNC_DRV_VBUS_P1 (MTK_PIN_NO(26) | 2) +#define MT7623_PIN_26_EINT4_FUNC_KROW3 (MTK_PIN_NO(26) | 3) +#define MT7623_PIN_26_EINT4_FUNC_CONN_MCU_TCK0 (MTK_PIN_NO(26) | 4) +#define MT7623_PIN_26_EINT4_FUNC_CONN_MCU_AICE_JCKC (MTK_PIN_NO(26) | 5) #define MT7623_PIN_26_EINT4_FUNC_PCIE2_WAKE_N (MTK_PIN_NO(26) | 6) #define MT7623_PIN_27_EINT5_FUNC_GPIO27 (MTK_PIN_NO(27) | 0) #define MT7623_PIN_27_EINT5_FUNC_URTS3 (MTK_PIN_NO(27) | 1) +#define MT7623_PIN_27_EINT5_FUNC_IDDIG_P1 (MTK_PIN_NO(27) | 2) +#define MT7623_PIN_27_EINT5_FUNC_KROW2 (MTK_PIN_NO(27) | 3) +#define MT7623_PIN_27_EINT5_FUNC_CONN_MCU_TDI (MTK_PIN_NO(27) | 4) #define MT7623_PIN_27_EINT5_FUNC_PCIE1_WAKE_N (MTK_PIN_NO(27) | 6) #define MT7623_PIN_28_EINT6_FUNC_GPIO28 (MTK_PIN_NO(28) | 0) #define MT7623_PIN_28_EINT6_FUNC_DRV_VBUS (MTK_PIN_NO(28) | 1) +#define MT7623_PIN_28_EINT6_FUNC_KROW1 (MTK_PIN_NO(28) | 3) +#define MT7623_PIN_28_EINT6_FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(28) | 4) #define MT7623_PIN_28_EINT6_FUNC_PCIE0_WAKE_N (MTK_PIN_NO(28) | 6) #define MT7623_PIN_29_EINT7_FUNC_GPIO29 (MTK_PIN_NO(29) | 0) #define MT7623_PIN_29_EINT7_FUNC_IDDIG (MTK_PIN_NO(29) | 1) #define MT7623_PIN_29_EINT7_FUNC_MSDC1_WP (MTK_PIN_NO(29) | 2) +#define MT7623_PIN_29_EINT7_FUNC_KROW0 (MTK_PIN_NO(29) | 3) +#define MT7623_PIN_29_EINT7_FUNC_CONN_MCU_TMS (MTK_PIN_NO(29) | 4) +#define MT7623_PIN_29_EINT7_FUNC_CONN_MCU_AICE_JMSC (MTK_PIN_NO(29) | 5) #define MT7623_PIN_29_EINT7_FUNC_PCIE2_PERST_N (MTK_PIN_NO(29) | 6) #define MT7623_PIN_33_I2S1_DATA_FUNC_GPIO33 (MTK_PIN_NO(33) | 0) #define MT7623_PIN_33_I2S1_DATA_FUNC_I2S1_DATA (MTK_PIN_NO(33) | 1) +#define MT7623_PIN_33_I2S1_DATA_FUNC_I2S1_DATA_BYPS (MTK_PIN_NO(33) | 2) #define MT7623_PIN_33_I2S1_DATA_FUNC_PCM_TX (MTK_PIN_NO(33) | 3) +#define MT7623_PIN_33_I2S1_DATA_FUNC_IMG_TEST_CK (MTK_PIN_NO(33) | 4) +#define MT7623_PIN_33_I2S1_DATA_FUNC_G1_RXD0 (MTK_PIN_NO(33) | 5) #define MT7623_PIN_33_I2S1_DATA_FUNC_AP_PCM_TX (MTK_PIN_NO(33) | 6) #define MT7623_PIN_34_I2S1_DATA_IN_FUNC_GPIO34 (MTK_PIN_NO(34) | 0) #define MT7623_PIN_34_I2S1_DATA_IN_FUNC_I2S1_DATA_IN (MTK_PIN_NO(34) | 1) #define MT7623_PIN_34_I2S1_DATA_IN_FUNC_PCM_RX (MTK_PIN_NO(34) | 3) +#define MT7623_PIN_34_I2S1_DATA_IN_FUNC_VDEC_TEST_CK (MTK_PIN_NO(34) | 4) +#define MT7623_PIN_34_I2S1_DATA_IN_FUNC_G1_RXD1 (MTK_PIN_NO(34) | 5) #define MT7623_PIN_34_I2S1_DATA_IN_FUNC_AP_PCM_RX (MTK_PIN_NO(34) | 6) #define MT7623_PIN_35_I2S1_BCK_FUNC_GPIO35 (MTK_PIN_NO(35) | 0) #define MT7623_PIN_35_I2S1_BCK_FUNC_I2S1_BCK (MTK_PIN_NO(35) | 1) #define MT7623_PIN_35_I2S1_BCK_FUNC_PCM_CLK0 (MTK_PIN_NO(35) | 3) +#define MT7623_PIN_35_I2S1_BCK_FUNC_G1_RXD2 (MTK_PIN_NO(35) | 5) #define MT7623_PIN_35_I2S1_BCK_FUNC_AP_PCM_CLKO (MTK_PIN_NO(35) | 6) #define MT7623_PIN_36_I2S1_LRCK_FUNC_GPIO36 (MTK_PIN_NO(36) | 0) #define MT7623_PIN_36_I2S1_LRCK_FUNC_I2S1_LRCK (MTK_PIN_NO(36) | 1) #define MT7623_PIN_36_I2S1_LRCK_FUNC_PCM_SYNC (MTK_PIN_NO(36) | 3) +#define MT7623_PIN_36_I2S1_LRCK_FUNC_G1_RXD3 (MTK_PIN_NO(36) | 5) #define MT7623_PIN_36_I2S1_LRCK_FUNC_AP_PCM_SYNC (MTK_PIN_NO(36) | 6) #define MT7623_PIN_37_I2S1_MCLK_FUNC_GPIO37 (MTK_PIN_NO(37) | 0) #define MT7623_PIN_37_I2S1_MCLK_FUNC_I2S1_MCLK (MTK_PIN_NO(37) | 1) +#define MT7623_PIN_37_I2S1_MCLK_FUNC_G1_RXDV (MTK_PIN_NO(37) | 5) #define MT7623_PIN_39_JTMS_FUNC_GPIO39 (MTK_PIN_NO(39) | 0) #define MT7623_PIN_39_JTMS_FUNC_JTMS (MTK_PIN_NO(39) | 1) +#define MT7623_PIN_39_JTMS_FUNC_CONN_MCU_TMS (MTK_PIN_NO(39) | 2) +#define MT7623_PIN_39_JTMS_FUNC_CONN_MCU_AICE_JMSC (MTK_PIN_NO(39) | 3) +#define MT7623_PIN_39_JTMS_FUNC_DFD_TMS_XI (MTK_PIN_NO(39) | 4) #define MT7623_PIN_40_JTCK_FUNC_GPIO40 (MTK_PIN_NO(40) | 0) #define MT7623_PIN_40_JTCK_FUNC_JTCK (MTK_PIN_NO(40) | 1) +#define MT7623_PIN_40_JTCK_FUNC_CONN_MCU_TCK1 (MTK_PIN_NO(40) | 2) +#define MT7623_PIN_40_JTCK_FUNC_CONN_MCU_AICE_JCKC (MTK_PIN_NO(40) | 3) +#define MT7623_PIN_40_JTCK_FUNC_DFD_TCK_XI (MTK_PIN_NO(40) | 4) #define MT7623_PIN_41_JTDI_FUNC_GPIO41 (MTK_PIN_NO(41) | 0) #define MT7623_PIN_41_JTDI_FUNC_JTDI (MTK_PIN_NO(41) | 1) +#define MT7623_PIN_41_JTDI_FUNC_CONN_MCU_TDI (MTK_PIN_NO(41) | 2) +#define MT7623_PIN_41_JTDI_FUNC_DFD_TDI_XI (MTK_PIN_NO(41) | 4) #define MT7623_PIN_42_JTDO_FUNC_GPIO42 (MTK_PIN_NO(42) | 0) #define MT7623_PIN_42_JTDO_FUNC_JTDO (MTK_PIN_NO(42) | 1) +#define MT7623_PIN_42_JTDO_FUNC_CONN_MCU_TDO (MTK_PIN_NO(42) | 2) +#define MT7623_PIN_42_JTDO_FUNC_DFD_TDO (MTK_PIN_NO(42) | 4) #define MT7623_PIN_43_NCLE_FUNC_GPIO43 (MTK_PIN_NO(43) | 0) #define MT7623_PIN_43_NCLE_FUNC_NCLE (MTK_PIN_NO(43) | 1) @@ -160,31 +218,40 @@ #define MT7623_PIN_47_NREB_FUNC_GPIO47 (MTK_PIN_NO(47) | 0) #define MT7623_PIN_47_NREB_FUNC_NREB (MTK_PIN_NO(47) | 1) +#define MT7623_PIN_47_NREB_FUNC_IDDIG_P1 (MTK_PIN_NO(47) | 2) #define MT7623_PIN_48_NRNB_FUNC_GPIO48 (MTK_PIN_NO(48) | 0) #define MT7623_PIN_48_NRNB_FUNC_NRNB (MTK_PIN_NO(48) | 1) +#define MT7623_PIN_48_NRNB_FUNC_DRV_VBUS_P1 (MTK_PIN_NO(48) | 2) #define MT7623_PIN_49_I2S0_DATA_FUNC_GPIO49 (MTK_PIN_NO(49) | 0) #define MT7623_PIN_49_I2S0_DATA_FUNC_I2S0_DATA (MTK_PIN_NO(49) | 1) +#define MT7623_PIN_49_I2S0_DATA_FUNC_I2S0_DATA_BYPS (MTK_PIN_NO(49) | 2) #define MT7623_PIN_49_I2S0_DATA_FUNC_PCM_TX (MTK_PIN_NO(49) | 3) #define MT7623_PIN_49_I2S0_DATA_FUNC_AP_I2S_DO (MTK_PIN_NO(49) | 6) #define MT7623_PIN_53_SPI0_CSN_FUNC_GPIO53 (MTK_PIN_NO(53) | 0) #define MT7623_PIN_53_SPI0_CSN_FUNC_SPI0_CS (MTK_PIN_NO(53) | 1) +#define MT7623_PIN_53_SPI0_CSN_FUNC_SPDIF (MTK_PIN_NO(53) | 3) +#define MT7623_PIN_53_SPI0_CSN_FUNC_ADC_CK (MTK_PIN_NO(53) | 4) #define MT7623_PIN_53_SPI0_CSN_FUNC_PWM1 (MTK_PIN_NO(53) | 5) #define MT7623_PIN_54_SPI0_CK_FUNC_GPIO54 (MTK_PIN_NO(54) | 0) #define MT7623_PIN_54_SPI0_CK_FUNC_SPI0_CK (MTK_PIN_NO(54) | 1) +#define MT7623_PIN_54_SPI0_CK_FUNC_SPDIF_IN1 (MTK_PIN_NO(54) | 3) +#define MT7623_PIN_54_SPI0_CK_FUNC_ADC_DAT_IN (MTK_PIN_NO(54) | 4) #define MT7623_PIN_55_SPI0_MI_FUNC_GPIO55 (MTK_PIN_NO(55) | 0) #define MT7623_PIN_55_SPI0_MI_FUNC_SPI0_MI (MTK_PIN_NO(55) | 1) #define MT7623_PIN_55_SPI0_MI_FUNC_SPI0_MO (MTK_PIN_NO(55) | 2) #define MT7623_PIN_55_SPI0_MI_FUNC_MSDC1_WP (MTK_PIN_NO(55) | 3) +#define MT7623_PIN_55_SPI0_MI_FUNC_ADC_WS (MTK_PIN_NO(55) | 4) #define MT7623_PIN_55_SPI0_MI_FUNC_PWM2 (MTK_PIN_NO(55) | 5) #define MT7623_PIN_56_SPI0_MO_FUNC_GPIO56 (MTK_PIN_NO(56) | 0) #define MT7623_PIN_56_SPI0_MO_FUNC_SPI0_MO (MTK_PIN_NO(56) | 1) #define MT7623_PIN_56_SPI0_MO_FUNC_SPI0_MI (MTK_PIN_NO(56) | 2) +#define MT7623_PIN_56_SPI0_MO_FUNC_SPDIF_IN0 (MTK_PIN_NO(56) | 3) #define MT7623_PIN_57_SDA1_FUNC_GPIO57 (MTK_PIN_NO(57) | 0) #define MT7623_PIN_57_SDA1_FUNC_SDA1 (MTK_PIN_NO(57) | 1) @@ -275,10 +342,23 @@ #define MT7623_PIN_83_LCM_RST_FUNC_GPIO83 (MTK_PIN_NO(83) | 0) #define MT7623_PIN_83_LCM_RST_FUNC_LCM_RST (MTK_PIN_NO(83) | 1) +#define MT7623_PIN_83_LCM_RST_FUNC_VDAC_CK_XI (MTK_PIN_NO(83) | 2) #define MT7623_PIN_84_DSI_TE_FUNC_GPIO84 (MTK_PIN_NO(84) | 0) #define MT7623_PIN_84_DSI_TE_FUNC_DSI_TE (MTK_PIN_NO(84) | 1) +#define MT7623_PIN_91_MIPI_TDN3_FUNC_GPIO91 (MTK_PIN_NO(91) | 0) +#define MT7623_PIN_91_MIPI_TDN3_FUNC_TDN3 (MTK_PIN_NO(91) | 1) + +#define MT7623_PIN_92_MIPI_TDP3_FUNC_GPIO92 (MTK_PIN_NO(92) | 0) +#define MT7623_PIN_92_MIPI_TDP3_FUNC_TDP3 (MTK_PIN_NO(92) | 1) + +#define MT7623_PIN_93_MIPI_TDN2_FUNC_GPIO93 (MTK_PIN_NO(93) | 0) +#define MT7623_PIN_93_MIPI_TDN2_FUNC_TDN2 (MTK_PIN_NO(93) | 1) + +#define MT7623_PIN_94_MIPI_TDP2_FUNC_GPIO94 (MTK_PIN_NO(94) | 0) +#define MT7623_PIN_94_MIPI_TDP2_FUNC_TDP2 (MTK_PIN_NO(94) | 1) + #define MT7623_PIN_95_MIPI_TCN_FUNC_GPIO95 (MTK_PIN_NO(95) | 0) #define MT7623_PIN_95_MIPI_TCN_FUNC_TCN (MTK_PIN_NO(95) | 1) @@ -300,20 +380,24 @@ #define MT7623_PIN_101_SPI2_CSN_FUNC_GPIO101 (MTK_PIN_NO(101) | 0) #define MT7623_PIN_101_SPI2_CSN_FUNC_SPI2_CS (MTK_PIN_NO(101) | 1) #define MT7623_PIN_101_SPI2_CSN_FUNC_SCL3 (MTK_PIN_NO(101) | 3) +#define MT7623_PIN_101_SPI2_CSN_FUNC_KROW0 (MTK_PIN_NO(101) | 4) #define MT7623_PIN_102_SPI2_MI_FUNC_GPIO102 (MTK_PIN_NO(102) | 0) #define MT7623_PIN_102_SPI2_MI_FUNC_SPI2_MI (MTK_PIN_NO(102) | 1) #define MT7623_PIN_102_SPI2_MI_FUNC_SPI2_MO (MTK_PIN_NO(102) | 2) #define MT7623_PIN_102_SPI2_MI_FUNC_SDA3 (MTK_PIN_NO(102) | 3) +#define MT7623_PIN_102_SPI2_MI_FUNC_KROW1 (MTK_PIN_NO(102) | 4) #define MT7623_PIN_103_SPI2_MO_FUNC_GPIO103 (MTK_PIN_NO(103) | 0) #define MT7623_PIN_103_SPI2_MO_FUNC_SPI2_MO (MTK_PIN_NO(103) | 1) #define MT7623_PIN_103_SPI2_MO_FUNC_SPI2_MI (MTK_PIN_NO(103) | 2) #define MT7623_PIN_103_SPI2_MO_FUNC_SCL3 (MTK_PIN_NO(103) | 3) +#define MT7623_PIN_103_SPI2_MO_FUNC_KROW2 (MTK_PIN_NO(103) | 4) #define MT7623_PIN_104_SPI2_CK_FUNC_GPIO104 (MTK_PIN_NO(104) | 0) #define MT7623_PIN_104_SPI2_CK_FUNC_SPI2_CK (MTK_PIN_NO(104) | 1) #define MT7623_PIN_104_SPI2_CK_FUNC_SDA3 (MTK_PIN_NO(104) | 3) +#define MT7623_PIN_104_SPI2_CK_FUNC_KROW3 (MTK_PIN_NO(104) | 4) #define MT7623_PIN_105_MSDC1_CMD_FUNC_GPIO105 (MTK_PIN_NO(105) | 0) #define MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD (MTK_PIN_NO(105) | 1) @@ -394,7 +478,7 @@ #define MT7623_PIN_121_MSDC0_DAT0_FUNC_WATCHDOG (MTK_PIN_NO(121) | 5) #define MT7623_PIN_122_GPIO122_FUNC_GPIO122 (MTK_PIN_NO(122) | 0) -#define MT7623_PIN_122_GPIO122_FUNC_TEST (MTK_PIN_NO(122) | 1) +#define MT7623_PIN_122_GPIO122_FUNC_CEC (MTK_PIN_NO(122) | 1) #define MT7623_PIN_122_GPIO122_FUNC_SDA2 (MTK_PIN_NO(122) | 4) #define MT7623_PIN_122_GPIO122_FUNC_URXD0 (MTK_PIN_NO(122) | 5) @@ -404,12 +488,12 @@ #define MT7623_PIN_123_HTPLG_FUNC_UTXD0 (MTK_PIN_NO(123) | 5) #define MT7623_PIN_124_GPIO124_FUNC_GPIO124 (MTK_PIN_NO(124) | 0) -#define MT7623_PIN_124_GPIO124_FUNC_TEST (MTK_PIN_NO(124) | 1) +#define MT7623_PIN_124_GPIO124_FUNC_HDMISCK (MTK_PIN_NO(124) | 1) #define MT7623_PIN_124_GPIO124_FUNC_SDA1 (MTK_PIN_NO(124) | 4) #define MT7623_PIN_124_GPIO124_FUNC_PWM3 (MTK_PIN_NO(124) | 5) #define MT7623_PIN_125_GPIO125_FUNC_GPIO125 (MTK_PIN_NO(125) | 0) -#define MT7623_PIN_125_GPIO125_FUNC_TEST (MTK_PIN_NO(125) | 1) +#define MT7623_PIN_125_GPIO125_FUNC_HDMISD (MTK_PIN_NO(125) | 1) #define MT7623_PIN_125_GPIO125_FUNC_SCL1 (MTK_PIN_NO(125) | 4) #define MT7623_PIN_125_GPIO125_FUNC_PWM4 (MTK_PIN_NO(125) | 5) diff --git a/include/dt-bindings/pinctrl/pads-imx8qm.h b/include/dt-bindings/pinctrl/pads-imx8qm.h new file mode 100644 index 000000000000..ae7b2942da69 --- /dev/null +++ b/include/dt-bindings/pinctrl/pads-imx8qm.h @@ -0,0 +1,960 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017~2018 NXP + */ + +#ifndef _IMX8QM_PADS_H +#define _IMX8QM_PADS_H + +/* pin id */ +#define IMX8QM_SIM0_CLK 0 +#define IMX8QM_SIM0_RST 1 +#define IMX8QM_SIM0_IO 2 +#define IMX8QM_SIM0_PD 3 +#define IMX8QM_SIM0_POWER_EN 4 +#define IMX8QM_SIM0_GPIO0_00 5 +#define IMX8QM_COMP_CTL_GPIO_1V8_3V3_SIM 6 +#define IMX8QM_M40_I2C0_SCL 7 +#define IMX8QM_M40_I2C0_SDA 8 +#define IMX8QM_M40_GPIO0_00 9 +#define IMX8QM_M40_GPIO0_01 10 +#define IMX8QM_M41_I2C0_SCL 11 +#define IMX8QM_M41_I2C0_SDA 12 +#define IMX8QM_M41_GPIO0_00 13 +#define IMX8QM_M41_GPIO0_01 14 +#define IMX8QM_GPT0_CLK 15 +#define IMX8QM_GPT0_CAPTURE 16 +#define IMX8QM_GPT0_COMPARE 17 +#define IMX8QM_GPT1_CLK 18 +#define IMX8QM_GPT1_CAPTURE 19 +#define IMX8QM_GPT1_COMPARE 20 +#define IMX8QM_UART0_RX 21 +#define IMX8QM_UART0_TX 22 +#define IMX8QM_UART0_RTS_B 23 +#define IMX8QM_UART0_CTS_B 24 +#define IMX8QM_UART1_TX 25 +#define IMX8QM_UART1_RX 26 +#define IMX8QM_UART1_RTS_B 27 +#define IMX8QM_UART1_CTS_B 28 +#define IMX8QM_COMP_CTL_GPIO_1V8_3V3_GPIOLH 29 +#define IMX8QM_SCU_PMIC_MEMC_ON 30 +#define IMX8QM_SCU_WDOG_OUT 31 +#define IMX8QM_PMIC_I2C_SDA 32 +#define IMX8QM_PMIC_I2C_SCL 33 +#define IMX8QM_PMIC_EARLY_WARNING 34 +#define IMX8QM_PMIC_INT_B 35 +#define IMX8QM_SCU_GPIO0_00 36 +#define IMX8QM_SCU_GPIO0_01 37 +#define IMX8QM_SCU_GPIO0_02 38 +#define IMX8QM_SCU_GPIO0_03 39 +#define IMX8QM_SCU_GPIO0_04 40 +#define IMX8QM_SCU_GPIO0_05 41 +#define IMX8QM_SCU_GPIO0_06 42 +#define IMX8QM_SCU_GPIO0_07 43 +#define IMX8QM_SCU_BOOT_MODE0 44 +#define IMX8QM_SCU_BOOT_MODE1 45 +#define IMX8QM_SCU_BOOT_MODE2 46 +#define IMX8QM_SCU_BOOT_MODE3 47 +#define IMX8QM_SCU_BOOT_MODE4 48 +#define IMX8QM_SCU_BOOT_MODE5 49 +#define IMX8QM_LVDS0_GPIO00 50 +#define IMX8QM_LVDS0_GPIO01 51 +#define IMX8QM_LVDS0_I2C0_SCL 52 +#define IMX8QM_LVDS0_I2C0_SDA 53 +#define IMX8QM_LVDS0_I2C1_SCL 54 +#define IMX8QM_LVDS0_I2C1_SDA 55 +#define IMX8QM_LVDS1_GPIO00 56 +#define IMX8QM_LVDS1_GPIO01 57 +#define IMX8QM_LVDS1_I2C0_SCL 58 +#define IMX8QM_LVDS1_I2C0_SDA 59 +#define IMX8QM_LVDS1_I2C1_SCL 60 +#define IMX8QM_LVDS1_I2C1_SDA 61 +#define IMX8QM_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO 62 +#define IMX8QM_MIPI_DSI0_I2C0_SCL 63 +#define IMX8QM_MIPI_DSI0_I2C0_SDA 64 +#define IMX8QM_MIPI_DSI0_GPIO0_00 65 +#define IMX8QM_MIPI_DSI0_GPIO0_01 66 +#define IMX8QM_MIPI_DSI1_I2C0_SCL 67 +#define IMX8QM_MIPI_DSI1_I2C0_SDA 68 +#define IMX8QM_MIPI_DSI1_GPIO0_00 69 +#define IMX8QM_MIPI_DSI1_GPIO0_01 70 +#define IMX8QM_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO 71 +#define IMX8QM_MIPI_CSI0_MCLK_OUT 72 +#define IMX8QM_MIPI_CSI0_I2C0_SCL 73 +#define IMX8QM_MIPI_CSI0_I2C0_SDA 74 +#define IMX8QM_MIPI_CSI0_GPIO0_00 75 +#define IMX8QM_MIPI_CSI0_GPIO0_01 76 +#define IMX8QM_MIPI_CSI1_MCLK_OUT 77 +#define IMX8QM_MIPI_CSI1_GPIO0_00 78 +#define IMX8QM_MIPI_CSI1_GPIO0_01 79 +#define IMX8QM_MIPI_CSI1_I2C0_SCL 80 +#define IMX8QM_MIPI_CSI1_I2C0_SDA 81 +#define IMX8QM_HDMI_TX0_TS_SCL 82 +#define IMX8QM_HDMI_TX0_TS_SDA 83 +#define IMX8QM_COMP_CTL_GPIO_3V3_HDMIGPIO 84 +#define IMX8QM_ESAI1_FSR 85 +#define IMX8QM_ESAI1_FST 86 +#define IMX8QM_ESAI1_SCKR 87 +#define IMX8QM_ESAI1_SCKT 88 +#define IMX8QM_ESAI1_TX0 89 +#define IMX8QM_ESAI1_TX1 90 +#define IMX8QM_ESAI1_TX2_RX3 91 +#define IMX8QM_ESAI1_TX3_RX2 92 +#define IMX8QM_ESAI1_TX4_RX1 93 +#define IMX8QM_ESAI1_TX5_RX0 94 +#define IMX8QM_SPDIF0_RX 95 +#define IMX8QM_SPDIF0_TX 96 +#define IMX8QM_SPDIF0_EXT_CLK 97 +#define IMX8QM_SPI3_SCK 98 +#define IMX8QM_SPI3_SDO 99 +#define IMX8QM_SPI3_SDI 100 +#define IMX8QM_SPI3_CS0 101 +#define IMX8QM_SPI3_CS1 102 +#define IMX8QM_COMP_CTL_GPIO_1V8_3V3_GPIORHB 103 +#define IMX8QM_ESAI0_FSR 104 +#define IMX8QM_ESAI0_FST 105 +#define IMX8QM_ESAI0_SCKR 106 +#define IMX8QM_ESAI0_SCKT 107 +#define IMX8QM_ESAI0_TX0 108 +#define IMX8QM_ESAI0_TX1 109 +#define IMX8QM_ESAI0_TX2_RX3 110 +#define IMX8QM_ESAI0_TX3_RX2 111 +#define IMX8QM_ESAI0_TX4_RX1 112 +#define IMX8QM_ESAI0_TX5_RX0 113 +#define IMX8QM_MCLK_IN0 114 +#define IMX8QM_MCLK_OUT0 115 +#define IMX8QM_COMP_CTL_GPIO_1V8_3V3_GPIORHC 116 +#define IMX8QM_SPI0_SCK 117 +#define IMX8QM_SPI0_SDO 118 +#define IMX8QM_SPI0_SDI 119 +#define IMX8QM_SPI0_CS0 120 +#define IMX8QM_SPI0_CS1 121 +#define IMX8QM_SPI2_SCK 122 +#define IMX8QM_SPI2_SDO 123 +#define IMX8QM_SPI2_SDI 124 +#define IMX8QM_SPI2_CS0 125 +#define IMX8QM_SPI2_CS1 126 +#define IMX8QM_SAI1_RXC 127 +#define IMX8QM_SAI1_RXD 128 +#define IMX8QM_SAI1_RXFS 129 +#define IMX8QM_SAI1_TXC 130 +#define IMX8QM_SAI1_TXD 131 +#define IMX8QM_SAI1_TXFS 132 +#define IMX8QM_COMP_CTL_GPIO_1V8_3V3_GPIORHT 133 +#define IMX8QM_ADC_IN7 134 +#define IMX8QM_ADC_IN6 135 +#define IMX8QM_ADC_IN5 136 +#define IMX8QM_ADC_IN4 137 +#define IMX8QM_ADC_IN3 138 +#define IMX8QM_ADC_IN2 139 +#define IMX8QM_ADC_IN1 140 +#define IMX8QM_ADC_IN0 141 +#define IMX8QM_MLB_SIG 142 +#define IMX8QM_MLB_CLK 143 +#define IMX8QM_MLB_DATA 144 +#define IMX8QM_COMP_CTL_GPIO_1V8_3V3_GPIOLHT 145 +#define IMX8QM_FLEXCAN0_RX 146 +#define IMX8QM_FLEXCAN0_TX 147 +#define IMX8QM_FLEXCAN1_RX 148 +#define IMX8QM_FLEXCAN1_TX 149 +#define IMX8QM_FLEXCAN2_RX 150 +#define IMX8QM_FLEXCAN2_TX 151 +#define IMX8QM_COMP_CTL_GPIO_1V8_3V3_GPIOTHR 152 +#define IMX8QM_USB_SS3_TC0 153 +#define IMX8QM_USB_SS3_TC1 154 +#define IMX8QM_USB_SS3_TC2 155 +#define IMX8QM_USB_SS3_TC3 156 +#define IMX8QM_COMP_CTL_GPIO_3V3_USB3IO 157 +#define IMX8QM_USDHC1_RESET_B 158 +#define IMX8QM_USDHC1_VSELECT 159 +#define IMX8QM_USDHC2_RESET_B 160 +#define IMX8QM_USDHC2_VSELECT 161 +#define IMX8QM_USDHC2_WP 162 +#define IMX8QM_USDHC2_CD_B 163 +#define IMX8QM_COMP_CTL_GPIO_1V8_3V3_VSELSEP 164 +#define IMX8QM_ENET0_MDIO 165 +#define IMX8QM_ENET0_MDC 166 +#define IMX8QM_ENET0_REFCLK_125M_25M 167 +#define IMX8QM_ENET1_REFCLK_125M_25M 168 +#define IMX8QM_ENET1_MDIO 169 +#define IMX8QM_ENET1_MDC 170 +#define IMX8QM_COMP_CTL_GPIO_1V8_3V3_GPIOCT 171 +#define IMX8QM_QSPI1A_SS0_B 172 +#define IMX8QM_QSPI1A_SS1_B 173 +#define IMX8QM_QSPI1A_SCLK 174 +#define IMX8QM_QSPI1A_DQS 175 +#define IMX8QM_QSPI1A_DATA3 176 +#define IMX8QM_QSPI1A_DATA2 177 +#define IMX8QM_QSPI1A_DATA1 178 +#define IMX8QM_QSPI1A_DATA0 179 +#define IMX8QM_COMP_CTL_GPIO_1V8_3V3_QSPI1 180 +#define IMX8QM_QSPI0A_DATA0 181 +#define IMX8QM_QSPI0A_DATA1 182 +#define IMX8QM_QSPI0A_DATA2 183 +#define IMX8QM_QSPI0A_DATA3 184 +#define IMX8QM_QSPI0A_DQS 185 +#define IMX8QM_QSPI0A_SS0_B 186 +#define IMX8QM_QSPI0A_SS1_B 187 +#define IMX8QM_QSPI0A_SCLK 188 +#define IMX8QM_QSPI0B_SCLK 189 +#define IMX8QM_QSPI0B_DATA0 190 +#define IMX8QM_QSPI0B_DATA1 191 +#define IMX8QM_QSPI0B_DATA2 192 +#define IMX8QM_QSPI0B_DATA3 193 +#define IMX8QM_QSPI0B_DQS 194 +#define IMX8QM_QSPI0B_SS0_B 195 +#define IMX8QM_QSPI0B_SS1_B 196 +#define IMX8QM_COMP_CTL_GPIO_1V8_3V3_QSPI0 197 +#define IMX8QM_PCIE_CTRL0_CLKREQ_B 198 +#define IMX8QM_PCIE_CTRL0_WAKE_B 199 +#define IMX8QM_PCIE_CTRL0_PERST_B 200 +#define IMX8QM_PCIE_CTRL1_CLKREQ_B 201 +#define IMX8QM_PCIE_CTRL1_WAKE_B 202 +#define IMX8QM_PCIE_CTRL1_PERST_B 203 +#define IMX8QM_COMP_CTL_GPIO_1V8_3V3_PCIESEP 204 +#define IMX8QM_USB_HSIC0_DATA 205 +#define IMX8QM_USB_HSIC0_STROBE 206 +#define IMX8QM_CALIBRATION_0_HSIC 207 +#define IMX8QM_CALIBRATION_1_HSIC 208 +#define IMX8QM_EMMC0_CLK 209 +#define IMX8QM_EMMC0_CMD 210 +#define IMX8QM_EMMC0_DATA0 211 +#define IMX8QM_EMMC0_DATA1 212 +#define IMX8QM_EMMC0_DATA2 213 +#define IMX8QM_EMMC0_DATA3 214 +#define IMX8QM_EMMC0_DATA4 215 +#define IMX8QM_EMMC0_DATA5 216 +#define IMX8QM_EMMC0_DATA6 217 +#define IMX8QM_EMMC0_DATA7 218 +#define IMX8QM_EMMC0_STROBE 219 +#define IMX8QM_EMMC0_RESET_B 220 +#define IMX8QM_COMP_CTL_GPIO_1V8_3V3_SD1FIX 221 +#define IMX8QM_USDHC1_CLK 222 +#define IMX8QM_USDHC1_CMD 223 +#define IMX8QM_USDHC1_DATA0 224 +#define IMX8QM_USDHC1_DATA1 225 +#define IMX8QM_CTL_NAND_RE_P_N 226 +#define IMX8QM_USDHC1_DATA2 227 +#define IMX8QM_USDHC1_DATA3 228 +#define IMX8QM_CTL_NAND_DQS_P_N 229 +#define IMX8QM_USDHC1_DATA4 230 +#define IMX8QM_USDHC1_DATA5 231 +#define IMX8QM_USDHC1_DATA6 232 +#define IMX8QM_USDHC1_DATA7 233 +#define IMX8QM_USDHC1_STROBE 234 +#define IMX8QM_COMP_CTL_GPIO_1V8_3V3_VSEL2 235 +#define IMX8QM_USDHC2_CLK 236 +#define IMX8QM_USDHC2_CMD 237 +#define IMX8QM_USDHC2_DATA0 238 +#define IMX8QM_USDHC2_DATA1 239 +#define IMX8QM_USDHC2_DATA2 240 +#define IMX8QM_USDHC2_DATA3 241 +#define IMX8QM_COMP_CTL_GPIO_1V8_3V3_VSEL3 242 +#define IMX8QM_ENET0_RGMII_TXC 243 +#define IMX8QM_ENET0_RGMII_TX_CTL 244 +#define IMX8QM_ENET0_RGMII_TXD0 245 +#define IMX8QM_ENET0_RGMII_TXD1 246 +#define IMX8QM_ENET0_RGMII_TXD2 247 +#define IMX8QM_ENET0_RGMII_TXD3 248 +#define IMX8QM_ENET0_RGMII_RXC 249 +#define IMX8QM_ENET0_RGMII_RX_CTL 250 +#define IMX8QM_ENET0_RGMII_RXD0 251 +#define IMX8QM_ENET0_RGMII_RXD1 252 +#define IMX8QM_ENET0_RGMII_RXD2 253 +#define IMX8QM_ENET0_RGMII_RXD3 254 +#define IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB 255 +#define IMX8QM_ENET1_RGMII_TXC 256 +#define IMX8QM_ENET1_RGMII_TX_CTL 257 +#define IMX8QM_ENET1_RGMII_TXD0 258 +#define IMX8QM_ENET1_RGMII_TXD1 259 +#define IMX8QM_ENET1_RGMII_TXD2 260 +#define IMX8QM_ENET1_RGMII_TXD3 261 +#define IMX8QM_ENET1_RGMII_RXC 262 +#define IMX8QM_ENET1_RGMII_RX_CTL 263 +#define IMX8QM_ENET1_RGMII_RXD0 264 +#define IMX8QM_ENET1_RGMII_RXD1 265 +#define IMX8QM_ENET1_RGMII_RXD2 266 +#define IMX8QM_ENET1_RGMII_RXD3 267 +#define IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA 268 + +/* + * format: <pin_id mux_mode> + */ +#define IMX8QM_SIM0_CLK_DMA_SIM0_CLK IMX8QM_SIM0_CLK 0 +#define IMX8QM_SIM0_CLK_LSIO_GPIO0_IO00 IMX8QM_SIM0_CLK 3 +#define IMX8QM_SIM0_RST_DMA_SIM0_RST IMX8QM_SIM0_RST 0 +#define IMX8QM_SIM0_RST_LSIO_GPIO0_IO01 IMX8QM_SIM0_RST 3 +#define IMX8QM_SIM0_IO_DMA_SIM0_IO IMX8QM_SIM0_IO 0 +#define IMX8QM_SIM0_IO_LSIO_GPIO0_IO02 IMX8QM_SIM0_IO 3 +#define IMX8QM_SIM0_PD_DMA_SIM0_PD IMX8QM_SIM0_PD 0 +#define IMX8QM_SIM0_PD_DMA_I2C3_SCL IMX8QM_SIM0_PD 1 +#define IMX8QM_SIM0_PD_LSIO_GPIO0_IO03 IMX8QM_SIM0_PD 3 +#define IMX8QM_SIM0_POWER_EN_DMA_SIM0_POWER_EN IMX8QM_SIM0_POWER_EN 0 +#define IMX8QM_SIM0_POWER_EN_DMA_I2C3_SDA IMX8QM_SIM0_POWER_EN 1 +#define IMX8QM_SIM0_POWER_EN_LSIO_GPIO0_IO04 IMX8QM_SIM0_POWER_EN 3 +#define IMX8QM_SIM0_GPIO0_00_DMA_SIM0_POWER_EN IMX8QM_SIM0_GPIO0_00 0 +#define IMX8QM_SIM0_GPIO0_00_LSIO_GPIO0_IO05 IMX8QM_SIM0_GPIO0_00 3 +#define IMX8QM_M40_I2C0_SCL_M40_I2C0_SCL IMX8QM_M40_I2C0_SCL 0 +#define IMX8QM_M40_I2C0_SCL_M40_UART0_RX IMX8QM_M40_I2C0_SCL 1 +#define IMX8QM_M40_I2C0_SCL_M40_GPIO0_IO02 IMX8QM_M40_I2C0_SCL 2 +#define IMX8QM_M40_I2C0_SCL_LSIO_GPIO0_IO06 IMX8QM_M40_I2C0_SCL 3 +#define IMX8QM_M40_I2C0_SDA_M40_I2C0_SDA IMX8QM_M40_I2C0_SDA 0 +#define IMX8QM_M40_I2C0_SDA_M40_UART0_TX IMX8QM_M40_I2C0_SDA 1 +#define IMX8QM_M40_I2C0_SDA_M40_GPIO0_IO03 IMX8QM_M40_I2C0_SDA 2 +#define IMX8QM_M40_I2C0_SDA_LSIO_GPIO0_IO07 IMX8QM_M40_I2C0_SDA 3 +#define IMX8QM_M40_GPIO0_00_M40_GPIO0_IO00 IMX8QM_M40_GPIO0_00 0 +#define IMX8QM_M40_GPIO0_00_M40_TPM0_CH0 IMX8QM_M40_GPIO0_00 1 +#define IMX8QM_M40_GPIO0_00_DMA_UART4_RX IMX8QM_M40_GPIO0_00 2 +#define IMX8QM_M40_GPIO0_00_LSIO_GPIO0_IO08 IMX8QM_M40_GPIO0_00 3 +#define IMX8QM_M40_GPIO0_01_M40_GPIO0_IO01 IMX8QM_M40_GPIO0_01 0 +#define IMX8QM_M40_GPIO0_01_M40_TPM0_CH1 IMX8QM_M40_GPIO0_01 1 +#define IMX8QM_M40_GPIO0_01_DMA_UART4_TX IMX8QM_M40_GPIO0_01 2 +#define IMX8QM_M40_GPIO0_01_LSIO_GPIO0_IO09 IMX8QM_M40_GPIO0_01 3 +#define IMX8QM_M41_I2C0_SCL_M41_I2C0_SCL IMX8QM_M41_I2C0_SCL 0 +#define IMX8QM_M41_I2C0_SCL_M41_UART0_RX IMX8QM_M41_I2C0_SCL 1 +#define IMX8QM_M41_I2C0_SCL_M41_GPIO0_IO02 IMX8QM_M41_I2C0_SCL 2 +#define IMX8QM_M41_I2C0_SCL_LSIO_GPIO0_IO10 IMX8QM_M41_I2C0_SCL 3 +#define IMX8QM_M41_I2C0_SDA_M41_I2C0_SDA IMX8QM_M41_I2C0_SDA 0 +#define IMX8QM_M41_I2C0_SDA_M41_UART0_TX IMX8QM_M41_I2C0_SDA 1 +#define IMX8QM_M41_I2C0_SDA_M41_GPIO0_IO03 IMX8QM_M41_I2C0_SDA 2 +#define IMX8QM_M41_I2C0_SDA_LSIO_GPIO0_IO11 IMX8QM_M41_I2C0_SDA 3 +#define IMX8QM_M41_GPIO0_00_M41_GPIO0_IO00 IMX8QM_M41_GPIO0_00 0 +#define IMX8QM_M41_GPIO0_00_M41_TPM0_CH0 IMX8QM_M41_GPIO0_00 1 +#define IMX8QM_M41_GPIO0_00_DMA_UART3_RX IMX8QM_M41_GPIO0_00 2 +#define IMX8QM_M41_GPIO0_00_LSIO_GPIO0_IO12 IMX8QM_M41_GPIO0_00 3 +#define IMX8QM_M41_GPIO0_01_M41_GPIO0_IO01 IMX8QM_M41_GPIO0_01 0 +#define IMX8QM_M41_GPIO0_01_M41_TPM0_CH1 IMX8QM_M41_GPIO0_01 1 +#define IMX8QM_M41_GPIO0_01_DMA_UART3_TX IMX8QM_M41_GPIO0_01 2 +#define IMX8QM_M41_GPIO0_01_LSIO_GPIO0_IO13 IMX8QM_M41_GPIO0_01 3 +#define IMX8QM_GPT0_CLK_LSIO_GPT0_CLK IMX8QM_GPT0_CLK 0 +#define IMX8QM_GPT0_CLK_DMA_I2C1_SCL IMX8QM_GPT0_CLK 1 +#define IMX8QM_GPT0_CLK_LSIO_KPP0_COL4 IMX8QM_GPT0_CLK 2 +#define IMX8QM_GPT0_CLK_LSIO_GPIO0_IO14 IMX8QM_GPT0_CLK 3 +#define IMX8QM_GPT0_CAPTURE_LSIO_GPT0_CAPTURE IMX8QM_GPT0_CAPTURE 0 +#define IMX8QM_GPT0_CAPTURE_DMA_I2C1_SDA IMX8QM_GPT0_CAPTURE 1 +#define IMX8QM_GPT0_CAPTURE_LSIO_KPP0_COL5 IMX8QM_GPT0_CAPTURE 2 +#define IMX8QM_GPT0_CAPTURE_LSIO_GPIO0_IO15 IMX8QM_GPT0_CAPTURE 3 +#define IMX8QM_GPT0_COMPARE_LSIO_GPT0_COMPARE IMX8QM_GPT0_COMPARE 0 +#define IMX8QM_GPT0_COMPARE_LSIO_PWM3_OUT IMX8QM_GPT0_COMPARE 1 +#define IMX8QM_GPT0_COMPARE_LSIO_KPP0_COL6 IMX8QM_GPT0_COMPARE 2 +#define IMX8QM_GPT0_COMPARE_LSIO_GPIO0_IO16 IMX8QM_GPT0_COMPARE 3 +#define IMX8QM_GPT1_CLK_LSIO_GPT1_CLK IMX8QM_GPT1_CLK 0 +#define IMX8QM_GPT1_CLK_DMA_I2C2_SCL IMX8QM_GPT1_CLK 1 +#define IMX8QM_GPT1_CLK_LSIO_KPP0_COL7 IMX8QM_GPT1_CLK 2 +#define IMX8QM_GPT1_CLK_LSIO_GPIO0_IO17 IMX8QM_GPT1_CLK 3 +#define IMX8QM_GPT1_CAPTURE_LSIO_GPT1_CAPTURE IMX8QM_GPT1_CAPTURE 0 +#define IMX8QM_GPT1_CAPTURE_DMA_I2C2_SDA IMX8QM_GPT1_CAPTURE 1 +#define IMX8QM_GPT1_CAPTURE_LSIO_KPP0_ROW4 IMX8QM_GPT1_CAPTURE 2 +#define IMX8QM_GPT1_CAPTURE_LSIO_GPIO0_IO18 IMX8QM_GPT1_CAPTURE 3 +#define IMX8QM_GPT1_COMPARE_LSIO_GPT1_COMPARE IMX8QM_GPT1_COMPARE 0 +#define IMX8QM_GPT1_COMPARE_LSIO_PWM2_OUT IMX8QM_GPT1_COMPARE 1 +#define IMX8QM_GPT1_COMPARE_LSIO_KPP0_ROW5 IMX8QM_GPT1_COMPARE 2 +#define IMX8QM_GPT1_COMPARE_LSIO_GPIO0_IO19 IMX8QM_GPT1_COMPARE 3 +#define IMX8QM_UART0_RX_DMA_UART0_RX IMX8QM_UART0_RX 0 +#define IMX8QM_UART0_RX_SCU_UART0_RX IMX8QM_UART0_RX 1 +#define IMX8QM_UART0_RX_LSIO_GPIO0_IO20 IMX8QM_UART0_RX 3 +#define IMX8QM_UART0_TX_DMA_UART0_TX IMX8QM_UART0_TX 0 +#define IMX8QM_UART0_TX_SCU_UART0_TX IMX8QM_UART0_TX 1 +#define IMX8QM_UART0_TX_LSIO_GPIO0_IO21 IMX8QM_UART0_TX 3 +#define IMX8QM_UART0_RTS_B_DMA_UART0_RTS_B IMX8QM_UART0_RTS_B 0 +#define IMX8QM_UART0_RTS_B_LSIO_PWM0_OUT IMX8QM_UART0_RTS_B 1 +#define IMX8QM_UART0_RTS_B_DMA_UART2_RX IMX8QM_UART0_RTS_B 2 +#define IMX8QM_UART0_RTS_B_LSIO_GPIO0_IO22 IMX8QM_UART0_RTS_B 3 +#define IMX8QM_UART0_CTS_B_DMA_UART0_CTS_B IMX8QM_UART0_CTS_B 0 +#define IMX8QM_UART0_CTS_B_LSIO_PWM1_OUT IMX8QM_UART0_CTS_B 1 +#define IMX8QM_UART0_CTS_B_DMA_UART2_TX IMX8QM_UART0_CTS_B 2 +#define IMX8QM_UART0_CTS_B_LSIO_GPIO0_IO23 IMX8QM_UART0_CTS_B 3 +#define IMX8QM_UART1_TX_DMA_UART1_TX IMX8QM_UART1_TX 0 +#define IMX8QM_UART1_TX_DMA_SPI3_SCK IMX8QM_UART1_TX 1 +#define IMX8QM_UART1_TX_LSIO_GPIO0_IO24 IMX8QM_UART1_TX 3 +#define IMX8QM_UART1_RX_DMA_UART1_RX IMX8QM_UART1_RX 0 +#define IMX8QM_UART1_RX_DMA_SPI3_SDO IMX8QM_UART1_RX 1 +#define IMX8QM_UART1_RX_LSIO_GPIO0_IO25 IMX8QM_UART1_RX 3 +#define IMX8QM_UART1_RTS_B_DMA_UART1_RTS_B IMX8QM_UART1_RTS_B 0 +#define IMX8QM_UART1_RTS_B_DMA_SPI3_SDI IMX8QM_UART1_RTS_B 1 +#define IMX8QM_UART1_RTS_B_DMA_UART1_CTS_B IMX8QM_UART1_RTS_B 2 +#define IMX8QM_UART1_RTS_B_LSIO_GPIO0_IO26 IMX8QM_UART1_RTS_B 3 +#define IMX8QM_UART1_CTS_B_DMA_UART1_CTS_B IMX8QM_UART1_CTS_B 0 +#define IMX8QM_UART1_CTS_B_DMA_SPI3_CS0 IMX8QM_UART1_CTS_B 1 +#define IMX8QM_UART1_CTS_B_DMA_UART1_RTS_B IMX8QM_UART1_CTS_B 2 +#define IMX8QM_UART1_CTS_B_LSIO_GPIO0_IO27 IMX8QM_UART1_CTS_B 3 +#define IMX8QM_SCU_PMIC_MEMC_ON_SCU_GPIO0_IOXX_PMIC_MEMC_ON IMX8QM_SCU_PMIC_MEMC_ON 0 +#define IMX8QM_SCU_WDOG_OUT_SCU_WDOG0_WDOG_OUT IMX8QM_SCU_WDOG_OUT 0 +#define IMX8QM_PMIC_I2C_SDA_SCU_PMIC_I2C_SDA IMX8QM_PMIC_I2C_SDA 0 +#define IMX8QM_PMIC_I2C_SCL_SCU_PMIC_I2C_SCL IMX8QM_PMIC_I2C_SCL 0 +#define IMX8QM_PMIC_EARLY_WARNING_SCU_PMIC_EARLY_WARNING IMX8QM_PMIC_EARLY_WARNING 0 +#define IMX8QM_PMIC_INT_B_SCU_DIMX8QMMIC_INT_B IMX8QM_PMIC_INT_B 0 +#define IMX8QM_SCU_GPIO0_00_SCU_GPIO0_IO00 IMX8QM_SCU_GPIO0_00 0 +#define IMX8QM_SCU_GPIO0_00_SCU_UART0_RX IMX8QM_SCU_GPIO0_00 1 +#define IMX8QM_SCU_GPIO0_00_LSIO_GPIO0_IO28 IMX8QM_SCU_GPIO0_00 3 +#define IMX8QM_SCU_GPIO0_01_SCU_GPIO0_IO01 IMX8QM_SCU_GPIO0_01 0 +#define IMX8QM_SCU_GPIO0_01_SCU_UART0_TX IMX8QM_SCU_GPIO0_01 1 +#define IMX8QM_SCU_GPIO0_01_LSIO_GPIO0_IO29 IMX8QM_SCU_GPIO0_01 3 +#define IMX8QM_SCU_GPIO0_02_SCU_GPIO0_IO02 IMX8QM_SCU_GPIO0_02 0 +#define IMX8QM_SCU_GPIO0_02_SCU_GPIO0_IOXX_PMIC_GPU0_ON IMX8QM_SCU_GPIO0_02 1 +#define IMX8QM_SCU_GPIO0_02_LSIO_GPIO0_IO30 IMX8QM_SCU_GPIO0_02 3 +#define IMX8QM_SCU_GPIO0_03_SCU_GPIO0_IO03 IMX8QM_SCU_GPIO0_03 0 +#define IMX8QM_SCU_GPIO0_03_SCU_GPIO0_IOXX_PMIC_GPU1_ON IMX8QM_SCU_GPIO0_03 1 +#define IMX8QM_SCU_GPIO0_03_LSIO_GPIO0_IO31 IMX8QM_SCU_GPIO0_03 3 +#define IMX8QM_SCU_GPIO0_04_SCU_GPIO0_IO04 IMX8QM_SCU_GPIO0_04 0 +#define IMX8QM_SCU_GPIO0_04_SCU_GPIO0_IOXX_PMIC_A72_ON IMX8QM_SCU_GPIO0_04 1 +#define IMX8QM_SCU_GPIO0_04_LSIO_GPIO1_IO00 IMX8QM_SCU_GPIO0_04 3 +#define IMX8QM_SCU_GPIO0_05_SCU_GPIO0_IO05 IMX8QM_SCU_GPIO0_05 0 +#define IMX8QM_SCU_GPIO0_05_SCU_GPIO0_IOXX_PMIC_A53_ON IMX8QM_SCU_GPIO0_05 1 +#define IMX8QM_SCU_GPIO0_05_LSIO_GPIO1_IO01 IMX8QM_SCU_GPIO0_05 3 +#define IMX8QM_SCU_GPIO0_06_SCU_GPIO0_IO06 IMX8QM_SCU_GPIO0_06 0 +#define IMX8QM_SCU_GPIO0_06_SCU_TPM0_CH0 IMX8QM_SCU_GPIO0_06 1 +#define IMX8QM_SCU_GPIO0_06_LSIO_GPIO1_IO02 IMX8QM_SCU_GPIO0_06 3 +#define IMX8QM_SCU_GPIO0_07_SCU_GPIO0_IO07 IMX8QM_SCU_GPIO0_07 0 +#define IMX8QM_SCU_GPIO0_07_SCU_TPM0_CH1 IMX8QM_SCU_GPIO0_07 1 +#define IMX8QM_SCU_GPIO0_07_SCU_DSC_RTC_CLOCK_OUTPUT_32K IMX8QM_SCU_GPIO0_07 2 +#define IMX8QM_SCU_GPIO0_07_LSIO_GPIO1_IO03 IMX8QM_SCU_GPIO0_07 3 +#define IMX8QM_SCU_BOOT_MODE0_SCU_DSC_BOOT_MODE0 IMX8QM_SCU_BOOT_MODE0 0 +#define IMX8QM_SCU_BOOT_MODE1_SCU_DSC_BOOT_MODE1 IMX8QM_SCU_BOOT_MODE1 0 +#define IMX8QM_SCU_BOOT_MODE2_SCU_DSC_BOOT_MODE2 IMX8QM_SCU_BOOT_MODE2 0 +#define IMX8QM_SCU_BOOT_MODE3_SCU_DSC_BOOT_MODE3 IMX8QM_SCU_BOOT_MODE3 0 +#define IMX8QM_SCU_BOOT_MODE4_SCU_DSC_BOOT_MODE4 IMX8QM_SCU_BOOT_MODE4 0 +#define IMX8QM_SCU_BOOT_MODE4_SCU_PMIC_I2C_SCL IMX8QM_SCU_BOOT_MODE4 1 +#define IMX8QM_SCU_BOOT_MODE5_SCU_DSC_BOOT_MODE5 IMX8QM_SCU_BOOT_MODE5 0 +#define IMX8QM_SCU_BOOT_MODE5_SCU_PMIC_I2C_SDA IMX8QM_SCU_BOOT_MODE5 1 +#define IMX8QM_LVDS0_GPIO00_LVDS0_GPIO0_IO00 IMX8QM_LVDS0_GPIO00 0 +#define IMX8QM_LVDS0_GPIO00_LVDS0_PWM0_OUT IMX8QM_LVDS0_GPIO00 1 +#define IMX8QM_LVDS0_GPIO00_LSIO_GPIO1_IO04 IMX8QM_LVDS0_GPIO00 3 +#define IMX8QM_LVDS0_GPIO01_LVDS0_GPIO0_IO01 IMX8QM_LVDS0_GPIO01 0 +#define IMX8QM_LVDS0_GPIO01_LSIO_GPIO1_IO05 IMX8QM_LVDS0_GPIO01 3 +#define IMX8QM_LVDS0_I2C0_SCL_LVDS0_I2C0_SCL IMX8QM_LVDS0_I2C0_SCL 0 +#define IMX8QM_LVDS0_I2C0_SCL_LVDS0_GPIO0_IO02 IMX8QM_LVDS0_I2C0_SCL 1 +#define IMX8QM_LVDS0_I2C0_SCL_LSIO_GPIO1_IO06 IMX8QM_LVDS0_I2C0_SCL 3 +#define IMX8QM_LVDS0_I2C0_SDA_LVDS0_I2C0_SDA IMX8QM_LVDS0_I2C0_SDA 0 +#define IMX8QM_LVDS0_I2C0_SDA_LVDS0_GPIO0_IO03 IMX8QM_LVDS0_I2C0_SDA 1 +#define IMX8QM_LVDS0_I2C0_SDA_LSIO_GPIO1_IO07 IMX8QM_LVDS0_I2C0_SDA 3 +#define IMX8QM_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL IMX8QM_LVDS0_I2C1_SCL 0 +#define IMX8QM_LVDS0_I2C1_SCL_DMA_UART2_TX IMX8QM_LVDS0_I2C1_SCL 1 +#define IMX8QM_LVDS0_I2C1_SCL_LSIO_GPIO1_IO08 IMX8QM_LVDS0_I2C1_SCL 3 +#define IMX8QM_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA IMX8QM_LVDS0_I2C1_SDA 0 +#define IMX8QM_LVDS0_I2C1_SDA_DMA_UART2_RX IMX8QM_LVDS0_I2C1_SDA 1 +#define IMX8QM_LVDS0_I2C1_SDA_LSIO_GPIO1_IO09 IMX8QM_LVDS0_I2C1_SDA 3 +#define IMX8QM_LVDS1_GPIO00_LVDS1_GPIO0_IO00 IMX8QM_LVDS1_GPIO00 0 +#define IMX8QM_LVDS1_GPIO00_LVDS1_PWM0_OUT IMX8QM_LVDS1_GPIO00 1 +#define IMX8QM_LVDS1_GPIO00_LSIO_GPIO1_IO10 IMX8QM_LVDS1_GPIO00 3 +#define IMX8QM_LVDS1_GPIO01_LVDS1_GPIO0_IO01 IMX8QM_LVDS1_GPIO01 0 +#define IMX8QM_LVDS1_GPIO01_LSIO_GPIO1_IO11 IMX8QM_LVDS1_GPIO01 3 +#define IMX8QM_LVDS1_I2C0_SCL_LVDS1_I2C0_SCL IMX8QM_LVDS1_I2C0_SCL 0 +#define IMX8QM_LVDS1_I2C0_SCL_LVDS1_GPIO0_IO02 IMX8QM_LVDS1_I2C0_SCL 1 +#define IMX8QM_LVDS1_I2C0_SCL_LSIO_GPIO1_IO12 IMX8QM_LVDS1_I2C0_SCL 3 +#define IMX8QM_LVDS1_I2C0_SDA_LVDS1_I2C0_SDA IMX8QM_LVDS1_I2C0_SDA 0 +#define IMX8QM_LVDS1_I2C0_SDA_LVDS1_GPIO0_IO03 IMX8QM_LVDS1_I2C0_SDA 1 +#define IMX8QM_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 IMX8QM_LVDS1_I2C0_SDA 3 +#define IMX8QM_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL IMX8QM_LVDS1_I2C1_SCL 0 +#define IMX8QM_LVDS1_I2C1_SCL_DMA_UART3_TX IMX8QM_LVDS1_I2C1_SCL 1 +#define IMX8QM_LVDS1_I2C1_SCL_LSIO_GPIO1_IO14 IMX8QM_LVDS1_I2C1_SCL 3 +#define IMX8QM_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA IMX8QM_LVDS1_I2C1_SDA 0 +#define IMX8QM_LVDS1_I2C1_SDA_DMA_UART3_RX IMX8QM_LVDS1_I2C1_SDA 1 +#define IMX8QM_LVDS1_I2C1_SDA_LSIO_GPIO1_IO15 IMX8QM_LVDS1_I2C1_SDA 3 +#define IMX8QM_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL IMX8QM_MIPI_DSI0_I2C0_SCL 0 +#define IMX8QM_MIPI_DSI0_I2C0_SCL_LSIO_GPIO1_IO16 IMX8QM_MIPI_DSI0_I2C0_SCL 3 +#define IMX8QM_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA IMX8QM_MIPI_DSI0_I2C0_SDA 0 +#define IMX8QM_MIPI_DSI0_I2C0_SDA_LSIO_GPIO1_IO17 IMX8QM_MIPI_DSI0_I2C0_SDA 3 +#define IMX8QM_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_IO00 IMX8QM_MIPI_DSI0_GPIO0_00 0 +#define IMX8QM_MIPI_DSI0_GPIO0_00_MIPI_DSI0_PWM0_OUT IMX8QM_MIPI_DSI0_GPIO0_00 1 +#define IMX8QM_MIPI_DSI0_GPIO0_00_LSIO_GPIO1_IO18 IMX8QM_MIPI_DSI0_GPIO0_00 3 +#define IMX8QM_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_IO01 IMX8QM_MIPI_DSI0_GPIO0_01 0 +#define IMX8QM_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO19 IMX8QM_MIPI_DSI0_GPIO0_01 3 +#define IMX8QM_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL IMX8QM_MIPI_DSI1_I2C0_SCL 0 +#define IMX8QM_MIPI_DSI1_I2C0_SCL_LSIO_GPIO1_IO20 IMX8QM_MIPI_DSI1_I2C0_SCL 3 +#define IMX8QM_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA IMX8QM_MIPI_DSI1_I2C0_SDA 0 +#define IMX8QM_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO21 IMX8QM_MIPI_DSI1_I2C0_SDA 3 +#define IMX8QM_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_IO00 IMX8QM_MIPI_DSI1_GPIO0_00 0 +#define IMX8QM_MIPI_DSI1_GPIO0_00_MIPI_DSI1_PWM0_OUT IMX8QM_MIPI_DSI1_GPIO0_00 1 +#define IMX8QM_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO22 IMX8QM_MIPI_DSI1_GPIO0_00 3 +#define IMX8QM_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_IO01 IMX8QM_MIPI_DSI1_GPIO0_01 0 +#define IMX8QM_MIPI_DSI1_GPIO0_01_LSIO_GPIO1_IO23 IMX8QM_MIPI_DSI1_GPIO0_01 3 +#define IMX8QM_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT IMX8QM_MIPI_CSI0_MCLK_OUT 0 +#define IMX8QM_MIPI_CSI0_MCLK_OUT_LSIO_GPIO1_IO24 IMX8QM_MIPI_CSI0_MCLK_OUT 3 +#define IMX8QM_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL IMX8QM_MIPI_CSI0_I2C0_SCL 0 +#define IMX8QM_MIPI_CSI0_I2C0_SCL_LSIO_GPIO1_IO25 IMX8QM_MIPI_CSI0_I2C0_SCL 3 +#define IMX8QM_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA IMX8QM_MIPI_CSI0_I2C0_SDA 0 +#define IMX8QM_MIPI_CSI0_I2C0_SDA_LSIO_GPIO1_IO26 IMX8QM_MIPI_CSI0_I2C0_SDA 3 +#define IMX8QM_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_IO00 IMX8QM_MIPI_CSI0_GPIO0_00 0 +#define IMX8QM_MIPI_CSI0_GPIO0_00_DMA_I2C0_SCL IMX8QM_MIPI_CSI0_GPIO0_00 1 +#define IMX8QM_MIPI_CSI0_GPIO0_00_MIPI_CSI1_I2C0_SCL IMX8QM_MIPI_CSI0_GPIO0_00 2 +#define IMX8QM_MIPI_CSI0_GPIO0_00_LSIO_GPIO1_IO27 IMX8QM_MIPI_CSI0_GPIO0_00 3 +#define IMX8QM_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_IO01 IMX8QM_MIPI_CSI0_GPIO0_01 0 +#define IMX8QM_MIPI_CSI0_GPIO0_01_DMA_I2C0_SDA IMX8QM_MIPI_CSI0_GPIO0_01 1 +#define IMX8QM_MIPI_CSI0_GPIO0_01_MIPI_CSI1_I2C0_SDA IMX8QM_MIPI_CSI0_GPIO0_01 2 +#define IMX8QM_MIPI_CSI0_GPIO0_01_LSIO_GPIO1_IO28 IMX8QM_MIPI_CSI0_GPIO0_01 3 +#define IMX8QM_MIPI_CSI1_MCLK_OUT_MIPI_CSI1_ACM_MCLK_OUT IMX8QM_MIPI_CSI1_MCLK_OUT 0 +#define IMX8QM_MIPI_CSI1_MCLK_OUT_LSIO_GPIO1_IO29 IMX8QM_MIPI_CSI1_MCLK_OUT 3 +#define IMX8QM_MIPI_CSI1_GPIO0_00_MIPI_CSI1_GPIO0_IO00 IMX8QM_MIPI_CSI1_GPIO0_00 0 +#define IMX8QM_MIPI_CSI1_GPIO0_00_DMA_UART4_RX IMX8QM_MIPI_CSI1_GPIO0_00 1 +#define IMX8QM_MIPI_CSI1_GPIO0_00_LSIO_GPIO1_IO30 IMX8QM_MIPI_CSI1_GPIO0_00 3 +#define IMX8QM_MIPI_CSI1_GPIO0_01_MIPI_CSI1_GPIO0_IO01 IMX8QM_MIPI_CSI1_GPIO0_01 0 +#define IMX8QM_MIPI_CSI1_GPIO0_01_DMA_UART4_TX IMX8QM_MIPI_CSI1_GPIO0_01 1 +#define IMX8QM_MIPI_CSI1_GPIO0_01_LSIO_GPIO1_IO31 IMX8QM_MIPI_CSI1_GPIO0_01 3 +#define IMX8QM_MIPI_CSI1_I2C0_SCL_MIPI_CSI1_I2C0_SCL IMX8QM_MIPI_CSI1_I2C0_SCL 0 +#define IMX8QM_MIPI_CSI1_I2C0_SCL_LSIO_GPIO2_IO00 IMX8QM_MIPI_CSI1_I2C0_SCL 3 +#define IMX8QM_MIPI_CSI1_I2C0_SDA_MIPI_CSI1_I2C0_SDA IMX8QM_MIPI_CSI1_I2C0_SDA 0 +#define IMX8QM_MIPI_CSI1_I2C0_SDA_LSIO_GPIO2_IO01 IMX8QM_MIPI_CSI1_I2C0_SDA 3 +#define IMX8QM_HDMI_TX0_TS_SCL_HDMI_TX0_I2C0_SCL IMX8QM_HDMI_TX0_TS_SCL 0 +#define IMX8QM_HDMI_TX0_TS_SCL_DMA_I2C0_SCL IMX8QM_HDMI_TX0_TS_SCL 1 +#define IMX8QM_HDMI_TX0_TS_SCL_LSIO_GPIO2_IO02 IMX8QM_HDMI_TX0_TS_SCL 3 +#define IMX8QM_HDMI_TX0_TS_SDA_HDMI_TX0_I2C0_SDA IMX8QM_HDMI_TX0_TS_SDA 0 +#define IMX8QM_HDMI_TX0_TS_SDA_DMA_I2C0_SDA IMX8QM_HDMI_TX0_TS_SDA 1 +#define IMX8QM_HDMI_TX0_TS_SDA_LSIO_GPIO2_IO03 IMX8QM_HDMI_TX0_TS_SDA 3 +#define IMX8QM_ESAI1_FSR_AUD_ESAI1_FSR IMX8QM_ESAI1_FSR 0 +#define IMX8QM_ESAI1_FSR_LSIO_GPIO2_IO04 IMX8QM_ESAI1_FSR 3 +#define IMX8QM_ESAI1_FST_AUD_ESAI1_FST IMX8QM_ESAI1_FST 0 +#define IMX8QM_ESAI1_FST_AUD_SPDIF0_EXT_CLK IMX8QM_ESAI1_FST 1 +#define IMX8QM_ESAI1_FST_LSIO_GPIO2_IO05 IMX8QM_ESAI1_FST 3 +#define IMX8QM_ESAI1_SCKR_AUD_ESAI1_SCKR IMX8QM_ESAI1_SCKR 0 +#define IMX8QM_ESAI1_SCKR_LSIO_GPIO2_IO06 IMX8QM_ESAI1_SCKR 3 +#define IMX8QM_ESAI1_SCKT_AUD_ESAI1_SCKT IMX8QM_ESAI1_SCKT 0 +#define IMX8QM_ESAI1_SCKT_AUD_SAI2_RXC IMX8QM_ESAI1_SCKT 1 +#define IMX8QM_ESAI1_SCKT_AUD_SPDIF0_EXT_CLK IMX8QM_ESAI1_SCKT 2 +#define IMX8QM_ESAI1_SCKT_LSIO_GPIO2_IO07 IMX8QM_ESAI1_SCKT 3 +#define IMX8QM_ESAI1_TX0_AUD_ESAI1_TX0 IMX8QM_ESAI1_TX0 0 +#define IMX8QM_ESAI1_TX0_AUD_SAI2_RXD IMX8QM_ESAI1_TX0 1 +#define IMX8QM_ESAI1_TX0_AUD_SPDIF0_RX IMX8QM_ESAI1_TX0 2 +#define IMX8QM_ESAI1_TX0_LSIO_GPIO2_IO08 IMX8QM_ESAI1_TX0 3 +#define IMX8QM_ESAI1_TX1_AUD_ESAI1_TX1 IMX8QM_ESAI1_TX1 0 +#define IMX8QM_ESAI1_TX1_AUD_SAI2_RXFS IMX8QM_ESAI1_TX1 1 +#define IMX8QM_ESAI1_TX1_AUD_SPDIF0_TX IMX8QM_ESAI1_TX1 2 +#define IMX8QM_ESAI1_TX1_LSIO_GPIO2_IO09 IMX8QM_ESAI1_TX1 3 +#define IMX8QM_ESAI1_TX2_RX3_AUD_ESAI1_TX2_RX3 IMX8QM_ESAI1_TX2_RX3 0 +#define IMX8QM_ESAI1_TX2_RX3_AUD_SPDIF0_RX IMX8QM_ESAI1_TX2_RX3 1 +#define IMX8QM_ESAI1_TX2_RX3_LSIO_GPIO2_IO10 IMX8QM_ESAI1_TX2_RX3 3 +#define IMX8QM_ESAI1_TX3_RX2_AUD_ESAI1_TX3_RX2 IMX8QM_ESAI1_TX3_RX2 0 +#define IMX8QM_ESAI1_TX3_RX2_AUD_SPDIF0_TX IMX8QM_ESAI1_TX3_RX2 1 +#define IMX8QM_ESAI1_TX3_RX2_LSIO_GPIO2_IO11 IMX8QM_ESAI1_TX3_RX2 3 +#define IMX8QM_ESAI1_TX4_RX1_AUD_ESAI1_TX4_RX1 IMX8QM_ESAI1_TX4_RX1 0 +#define IMX8QM_ESAI1_TX4_RX1_LSIO_GPIO2_IO12 IMX8QM_ESAI1_TX4_RX1 3 +#define IMX8QM_ESAI1_TX5_RX0_AUD_ESAI1_TX5_RX0 IMX8QM_ESAI1_TX5_RX0 0 +#define IMX8QM_ESAI1_TX5_RX0_LSIO_GPIO2_IO13 IMX8QM_ESAI1_TX5_RX0 3 +#define IMX8QM_SPDIF0_RX_AUD_SPDIF0_RX IMX8QM_SPDIF0_RX 0 +#define IMX8QM_SPDIF0_RX_AUD_MQS_R IMX8QM_SPDIF0_RX 1 +#define IMX8QM_SPDIF0_RX_AUD_ACM_MCLK_IN1 IMX8QM_SPDIF0_RX 2 +#define IMX8QM_SPDIF0_RX_LSIO_GPIO2_IO14 IMX8QM_SPDIF0_RX 3 +#define IMX8QM_SPDIF0_TX_AUD_SPDIF0_TX IMX8QM_SPDIF0_TX 0 +#define IMX8QM_SPDIF0_TX_AUD_MQS_L IMX8QM_SPDIF0_TX 1 +#define IMX8QM_SPDIF0_TX_AUD_ACM_MCLK_OUT1 IMX8QM_SPDIF0_TX 2 +#define IMX8QM_SPDIF0_TX_LSIO_GPIO2_IO15 IMX8QM_SPDIF0_TX 3 +#define IMX8QM_SPDIF0_EXT_CLK_AUD_SPDIF0_EXT_CLK IMX8QM_SPDIF0_EXT_CLK 0 +#define IMX8QM_SPDIF0_EXT_CLK_DMA_DMA0_REQ_IN0 IMX8QM_SPDIF0_EXT_CLK 1 +#define IMX8QM_SPDIF0_EXT_CLK_LSIO_GPIO2_IO16 IMX8QM_SPDIF0_EXT_CLK 3 +#define IMX8QM_SPI3_SCK_DMA_SPI3_SCK IMX8QM_SPI3_SCK 0 +#define IMX8QM_SPI3_SCK_LSIO_GPIO2_IO17 IMX8QM_SPI3_SCK 3 +#define IMX8QM_SPI3_SDO_DMA_SPI3_SDO IMX8QM_SPI3_SDO 0 +#define IMX8QM_SPI3_SDO_DMA_FTM_CH0 IMX8QM_SPI3_SDO 1 +#define IMX8QM_SPI3_SDO_LSIO_GPIO2_IO18 IMX8QM_SPI3_SDO 3 +#define IMX8QM_SPI3_SDI_DMA_SPI3_SDI IMX8QM_SPI3_SDI 0 +#define IMX8QM_SPI3_SDI_DMA_FTM_CH1 IMX8QM_SPI3_SDI 1 +#define IMX8QM_SPI3_SDI_LSIO_GPIO2_IO19 IMX8QM_SPI3_SDI 3 +#define IMX8QM_SPI3_CS0_DMA_SPI3_CS0 IMX8QM_SPI3_CS0 0 +#define IMX8QM_SPI3_CS0_DMA_FTM_CH2 IMX8QM_SPI3_CS0 1 +#define IMX8QM_SPI3_CS0_LSIO_GPIO2_IO20 IMX8QM_SPI3_CS0 3 +#define IMX8QM_SPI3_CS1_DMA_SPI3_CS1 IMX8QM_SPI3_CS1 0 +#define IMX8QM_SPI3_CS1_LSIO_GPIO2_IO21 IMX8QM_SPI3_CS1 3 +#define IMX8QM_ESAI0_FSR_AUD_ESAI0_FSR IMX8QM_ESAI0_FSR 0 +#define IMX8QM_ESAI0_FSR_LSIO_GPIO2_IO22 IMX8QM_ESAI0_FSR 3 +#define IMX8QM_ESAI0_FST_AUD_ESAI0_FST IMX8QM_ESAI0_FST 0 +#define IMX8QM_ESAI0_FST_LSIO_GPIO2_IO23 IMX8QM_ESAI0_FST 3 +#define IMX8QM_ESAI0_SCKR_AUD_ESAI0_SCKR IMX8QM_ESAI0_SCKR 0 +#define IMX8QM_ESAI0_SCKR_LSIO_GPIO2_IO24 IMX8QM_ESAI0_SCKR 3 +#define IMX8QM_ESAI0_SCKT_AUD_ESAI0_SCKT IMX8QM_ESAI0_SCKT 0 +#define IMX8QM_ESAI0_SCKT_LSIO_GPIO2_IO25 IMX8QM_ESAI0_SCKT 3 +#define IMX8QM_ESAI0_TX0_AUD_ESAI0_TX0 IMX8QM_ESAI0_TX0 0 +#define IMX8QM_ESAI0_TX0_LSIO_GPIO2_IO26 IMX8QM_ESAI0_TX0 3 +#define IMX8QM_ESAI0_TX1_AUD_ESAI0_TX1 IMX8QM_ESAI0_TX1 0 +#define IMX8QM_ESAI0_TX1_LSIO_GPIO2_IO27 IMX8QM_ESAI0_TX1 3 +#define IMX8QM_ESAI0_TX2_RX3_AUD_ESAI0_TX2_RX3 IMX8QM_ESAI0_TX2_RX3 0 +#define IMX8QM_ESAI0_TX2_RX3_LSIO_GPIO2_IO28 IMX8QM_ESAI0_TX2_RX3 3 +#define IMX8QM_ESAI0_TX3_RX2_AUD_ESAI0_TX3_RX2 IMX8QM_ESAI0_TX3_RX2 0 +#define IMX8QM_ESAI0_TX3_RX2_LSIO_GPIO2_IO29 IMX8QM_ESAI0_TX3_RX2 3 +#define IMX8QM_ESAI0_TX4_RX1_AUD_ESAI0_TX4_RX1 IMX8QM_ESAI0_TX4_RX1 0 +#define IMX8QM_ESAI0_TX4_RX1_LSIO_GPIO2_IO30 IMX8QM_ESAI0_TX4_RX1 3 +#define IMX8QM_ESAI0_TX5_RX0_AUD_ESAI0_TX5_RX0 IMX8QM_ESAI0_TX5_RX0 0 +#define IMX8QM_ESAI0_TX5_RX0_LSIO_GPIO2_IO31 IMX8QM_ESAI0_TX5_RX0 3 +#define IMX8QM_MCLK_IN0_AUD_ACM_MCLK_IN0 IMX8QM_MCLK_IN0 0 +#define IMX8QM_MCLK_IN0_AUD_ESAI0_RX_HF_CLK IMX8QM_MCLK_IN0 1 +#define IMX8QM_MCLK_IN0_AUD_ESAI1_RX_HF_CLK IMX8QM_MCLK_IN0 2 +#define IMX8QM_MCLK_IN0_LSIO_GPIO3_IO00 IMX8QM_MCLK_IN0 3 +#define IMX8QM_MCLK_OUT0_AUD_ACM_MCLK_OUT0 IMX8QM_MCLK_OUT0 0 +#define IMX8QM_MCLK_OUT0_AUD_ESAI0_TX_HF_CLK IMX8QM_MCLK_OUT0 1 +#define IMX8QM_MCLK_OUT0_AUD_ESAI1_TX_HF_CLK IMX8QM_MCLK_OUT0 2 +#define IMX8QM_MCLK_OUT0_LSIO_GPIO3_IO01 IMX8QM_MCLK_OUT0 3 +#define IMX8QM_SPI0_SCK_DMA_SPI0_SCK IMX8QM_SPI0_SCK 0 +#define IMX8QM_SPI0_SCK_AUD_SAI0_RXC IMX8QM_SPI0_SCK 1 +#define IMX8QM_SPI0_SCK_LSIO_GPIO3_IO02 IMX8QM_SPI0_SCK 3 +#define IMX8QM_SPI0_SDO_DMA_SPI0_SDO IMX8QM_SPI0_SDO 0 +#define IMX8QM_SPI0_SDO_AUD_SAI0_TXD IMX8QM_SPI0_SDO 1 +#define IMX8QM_SPI0_SDO_LSIO_GPIO3_IO03 IMX8QM_SPI0_SDO 3 +#define IMX8QM_SPI0_SDI_DMA_SPI0_SDI IMX8QM_SPI0_SDI 0 +#define IMX8QM_SPI0_SDI_AUD_SAI0_RXD IMX8QM_SPI0_SDI 1 +#define IMX8QM_SPI0_SDI_LSIO_GPIO3_IO04 IMX8QM_SPI0_SDI 3 +#define IMX8QM_SPI0_CS0_DMA_SPI0_CS0 IMX8QM_SPI0_CS0 0 +#define IMX8QM_SPI0_CS0_AUD_SAI0_RXFS IMX8QM_SPI0_CS0 1 +#define IMX8QM_SPI0_CS0_LSIO_GPIO3_IO05 IMX8QM_SPI0_CS0 3 +#define IMX8QM_SPI0_CS1_DMA_SPI0_CS1 IMX8QM_SPI0_CS1 0 +#define IMX8QM_SPI0_CS1_AUD_SAI0_TXC IMX8QM_SPI0_CS1 1 +#define IMX8QM_SPI0_CS1_LSIO_GPIO3_IO06 IMX8QM_SPI0_CS1 3 +#define IMX8QM_SPI2_SCK_DMA_SPI2_SCK IMX8QM_SPI2_SCK 0 +#define IMX8QM_SPI2_SCK_LSIO_GPIO3_IO07 IMX8QM_SPI2_SCK 3 +#define IMX8QM_SPI2_SDO_DMA_SPI2_SDO IMX8QM_SPI2_SDO 0 +#define IMX8QM_SPI2_SDO_LSIO_GPIO3_IO08 IMX8QM_SPI2_SDO 3 +#define IMX8QM_SPI2_SDI_DMA_SPI2_SDI IMX8QM_SPI2_SDI 0 +#define IMX8QM_SPI2_SDI_LSIO_GPIO3_IO09 IMX8QM_SPI2_SDI 3 +#define IMX8QM_SPI2_CS0_DMA_SPI2_CS0 IMX8QM_SPI2_CS0 0 +#define IMX8QM_SPI2_CS0_LSIO_GPIO3_IO10 IMX8QM_SPI2_CS0 3 +#define IMX8QM_SPI2_CS1_DMA_SPI2_CS1 IMX8QM_SPI2_CS1 0 +#define IMX8QM_SPI2_CS1_AUD_SAI0_TXFS IMX8QM_SPI2_CS1 1 +#define IMX8QM_SPI2_CS1_LSIO_GPIO3_IO11 IMX8QM_SPI2_CS1 3 +#define IMX8QM_SAI1_RXC_AUD_SAI1_RXC IMX8QM_SAI1_RXC 0 +#define IMX8QM_SAI1_RXC_AUD_SAI0_TXD IMX8QM_SAI1_RXC 1 +#define IMX8QM_SAI1_RXC_LSIO_GPIO3_IO12 IMX8QM_SAI1_RXC 3 +#define IMX8QM_SAI1_RXD_AUD_SAI1_RXD IMX8QM_SAI1_RXD 0 +#define IMX8QM_SAI1_RXD_AUD_SAI0_TXFS IMX8QM_SAI1_RXD 1 +#define IMX8QM_SAI1_RXD_LSIO_GPIO3_IO13 IMX8QM_SAI1_RXD 3 +#define IMX8QM_SAI1_RXFS_AUD_SAI1_RXFS IMX8QM_SAI1_RXFS 0 +#define IMX8QM_SAI1_RXFS_AUD_SAI0_RXD IMX8QM_SAI1_RXFS 1 +#define IMX8QM_SAI1_RXFS_LSIO_GPIO3_IO14 IMX8QM_SAI1_RXFS 3 +#define IMX8QM_SAI1_TXC_AUD_SAI1_TXC IMX8QM_SAI1_TXC 0 +#define IMX8QM_SAI1_TXC_AUD_SAI0_TXC IMX8QM_SAI1_TXC 1 +#define IMX8QM_SAI1_TXC_LSIO_GPIO3_IO15 IMX8QM_SAI1_TXC 3 +#define IMX8QM_SAI1_TXD_AUD_SAI1_TXD IMX8QM_SAI1_TXD 0 +#define IMX8QM_SAI1_TXD_AUD_SAI1_RXC IMX8QM_SAI1_TXD 1 +#define IMX8QM_SAI1_TXD_LSIO_GPIO3_IO16 IMX8QM_SAI1_TXD 3 +#define IMX8QM_SAI1_TXFS_AUD_SAI1_TXFS IMX8QM_SAI1_TXFS 0 +#define IMX8QM_SAI1_TXFS_AUD_SAI1_RXFS IMX8QM_SAI1_TXFS 1 +#define IMX8QM_SAI1_TXFS_LSIO_GPIO3_IO17 IMX8QM_SAI1_TXFS 3 +#define IMX8QM_ADC_IN7_DMA_ADC1_IN3 IMX8QM_ADC_IN7 0 +#define IMX8QM_ADC_IN7_DMA_SPI1_CS1 IMX8QM_ADC_IN7 1 +#define IMX8QM_ADC_IN7_LSIO_KPP0_ROW3 IMX8QM_ADC_IN7 2 +#define IMX8QM_ADC_IN7_LSIO_GPIO3_IO25 IMX8QM_ADC_IN7 3 +#define IMX8QM_ADC_IN6_DMA_ADC1_IN2 IMX8QM_ADC_IN6 0 +#define IMX8QM_ADC_IN6_DMA_SPI1_CS0 IMX8QM_ADC_IN6 1 +#define IMX8QM_ADC_IN6_LSIO_KPP0_ROW2 IMX8QM_ADC_IN6 2 +#define IMX8QM_ADC_IN6_LSIO_GPIO3_IO24 IMX8QM_ADC_IN6 3 +#define IMX8QM_ADC_IN5_DMA_ADC1_IN1 IMX8QM_ADC_IN5 0 +#define IMX8QM_ADC_IN5_DMA_SPI1_SDI IMX8QM_ADC_IN5 1 +#define IMX8QM_ADC_IN5_LSIO_KPP0_ROW1 IMX8QM_ADC_IN5 2 +#define IMX8QM_ADC_IN5_LSIO_GPIO3_IO23 IMX8QM_ADC_IN5 3 +#define IMX8QM_ADC_IN4_DMA_ADC1_IN0 IMX8QM_ADC_IN4 0 +#define IMX8QM_ADC_IN4_DMA_SPI1_SDO IMX8QM_ADC_IN4 1 +#define IMX8QM_ADC_IN4_LSIO_KPP0_ROW0 IMX8QM_ADC_IN4 2 +#define IMX8QM_ADC_IN4_LSIO_GPIO3_IO22 IMX8QM_ADC_IN4 3 +#define IMX8QM_ADC_IN3_DMA_ADC0_IN3 IMX8QM_ADC_IN3 0 +#define IMX8QM_ADC_IN3_DMA_SPI1_SCK IMX8QM_ADC_IN3 1 +#define IMX8QM_ADC_IN3_LSIO_KPP0_COL3 IMX8QM_ADC_IN3 2 +#define IMX8QM_ADC_IN3_LSIO_GPIO3_IO21 IMX8QM_ADC_IN3 3 +#define IMX8QM_ADC_IN2_DMA_ADC0_IN2 IMX8QM_ADC_IN2 0 +#define IMX8QM_ADC_IN2_LSIO_KPP0_COL2 IMX8QM_ADC_IN2 2 +#define IMX8QM_ADC_IN2_LSIO_GPIO3_IO20 IMX8QM_ADC_IN2 3 +#define IMX8QM_ADC_IN1_DMA_ADC0_IN1 IMX8QM_ADC_IN1 0 +#define IMX8QM_ADC_IN1_LSIO_KPP0_COL1 IMX8QM_ADC_IN1 2 +#define IMX8QM_ADC_IN1_LSIO_GPIO3_IO19 IMX8QM_ADC_IN1 3 +#define IMX8QM_ADC_IN0_DMA_ADC0_IN0 IMX8QM_ADC_IN0 0 +#define IMX8QM_ADC_IN0_LSIO_KPP0_COL0 IMX8QM_ADC_IN0 2 +#define IMX8QM_ADC_IN0_LSIO_GPIO3_IO18 IMX8QM_ADC_IN0 3 +#define IMX8QM_MLB_SIG_CONN_MLB_SIG IMX8QM_MLB_SIG 0 +#define IMX8QM_MLB_SIG_AUD_SAI3_RXC IMX8QM_MLB_SIG 1 +#define IMX8QM_MLB_SIG_LSIO_GPIO3_IO26 IMX8QM_MLB_SIG 3 +#define IMX8QM_MLB_CLK_CONN_MLB_CLK IMX8QM_MLB_CLK 0 +#define IMX8QM_MLB_CLK_AUD_SAI3_RXFS IMX8QM_MLB_CLK 1 +#define IMX8QM_MLB_CLK_LSIO_GPIO3_IO27 IMX8QM_MLB_CLK 3 +#define IMX8QM_MLB_DATA_CONN_MLB_DATA IMX8QM_MLB_DATA 0 +#define IMX8QM_MLB_DATA_AUD_SAI3_RXD IMX8QM_MLB_DATA 1 +#define IMX8QM_MLB_DATA_LSIO_GPIO3_IO28 IMX8QM_MLB_DATA 3 +#define IMX8QM_FLEXCAN0_RX_DMA_FLEXCAN0_RX IMX8QM_FLEXCAN0_RX 0 +#define IMX8QM_FLEXCAN0_RX_LSIO_GPIO3_IO29 IMX8QM_FLEXCAN0_RX 3 +#define IMX8QM_FLEXCAN0_TX_DMA_FLEXCAN0_TX IMX8QM_FLEXCAN0_TX 0 +#define IMX8QM_FLEXCAN0_TX_LSIO_GPIO3_IO30 IMX8QM_FLEXCAN0_TX 3 +#define IMX8QM_FLEXCAN1_RX_DMA_FLEXCAN1_RX IMX8QM_FLEXCAN1_RX 0 +#define IMX8QM_FLEXCAN1_RX_LSIO_GPIO3_IO31 IMX8QM_FLEXCAN1_RX 3 +#define IMX8QM_FLEXCAN1_TX_DMA_FLEXCAN1_TX IMX8QM_FLEXCAN1_TX 0 +#define IMX8QM_FLEXCAN1_TX_LSIO_GPIO4_IO00 IMX8QM_FLEXCAN1_TX 3 +#define IMX8QM_FLEXCAN2_RX_DMA_FLEXCAN2_RX IMX8QM_FLEXCAN2_RX 0 +#define IMX8QM_FLEXCAN2_RX_LSIO_GPIO4_IO01 IMX8QM_FLEXCAN2_RX 3 +#define IMX8QM_FLEXCAN2_TX_DMA_FLEXCAN2_TX IMX8QM_FLEXCAN2_TX 0 +#define IMX8QM_FLEXCAN2_TX_LSIO_GPIO4_IO02 IMX8QM_FLEXCAN2_TX 3 +#define IMX8QM_USB_SS3_TC0_DMA_I2C1_SCL IMX8QM_USB_SS3_TC0 0 +#define IMX8QM_USB_SS3_TC0_CONN_USB_OTG1_PWR IMX8QM_USB_SS3_TC0 1 +#define IMX8QM_USB_SS3_TC0_LSIO_GPIO4_IO03 IMX8QM_USB_SS3_TC0 3 +#define IMX8QM_USB_SS3_TC1_DMA_I2C1_SCL IMX8QM_USB_SS3_TC1 0 +#define IMX8QM_USB_SS3_TC1_CONN_USB_OTG2_PWR IMX8QM_USB_SS3_TC1 1 +#define IMX8QM_USB_SS3_TC1_LSIO_GPIO4_IO04 IMX8QM_USB_SS3_TC1 3 +#define IMX8QM_USB_SS3_TC2_DMA_I2C1_SDA IMX8QM_USB_SS3_TC2 0 +#define IMX8QM_USB_SS3_TC2_CONN_USB_OTG1_OC IMX8QM_USB_SS3_TC2 1 +#define IMX8QM_USB_SS3_TC2_LSIO_GPIO4_IO05 IMX8QM_USB_SS3_TC2 3 +#define IMX8QM_USB_SS3_TC3_DMA_I2C1_SDA IMX8QM_USB_SS3_TC3 0 +#define IMX8QM_USB_SS3_TC3_CONN_USB_OTG2_OC IMX8QM_USB_SS3_TC3 1 +#define IMX8QM_USB_SS3_TC3_LSIO_GPIO4_IO06 IMX8QM_USB_SS3_TC3 3 +#define IMX8QM_USDHC1_RESET_B_CONN_USDHC1_RESET_B IMX8QM_USDHC1_RESET_B 0 +#define IMX8QM_USDHC1_RESET_B_LSIO_GPIO4_IO07 IMX8QM_USDHC1_RESET_B 3 +#define IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT IMX8QM_USDHC1_VSELECT 0 +#define IMX8QM_USDHC1_VSELECT_LSIO_GPIO4_IO08 IMX8QM_USDHC1_VSELECT 3 +#define IMX8QM_USDHC2_RESET_B_CONN_USDHC2_RESET_B IMX8QM_USDHC2_RESET_B 0 +#define IMX8QM_USDHC2_RESET_B_LSIO_GPIO4_IO09 IMX8QM_USDHC2_RESET_B 3 +#define IMX8QM_USDHC2_VSELECT_CONN_USDHC2_VSELECT IMX8QM_USDHC2_VSELECT 0 +#define IMX8QM_USDHC2_VSELECT_LSIO_GPIO4_IO10 IMX8QM_USDHC2_VSELECT 3 +#define IMX8QM_USDHC2_WP_CONN_USDHC2_WP IMX8QM_USDHC2_WP 0 +#define IMX8QM_USDHC2_WP_LSIO_GPIO4_IO11 IMX8QM_USDHC2_WP 3 +#define IMX8QM_USDHC2_CD_B_CONN_USDHC2_CD_B IMX8QM_USDHC2_CD_B 0 +#define IMX8QM_USDHC2_CD_B_LSIO_GPIO4_IO12 IMX8QM_USDHC2_CD_B 3 +#define IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO IMX8QM_ENET0_MDIO 0 +#define IMX8QM_ENET0_MDIO_DMA_I2C4_SDA IMX8QM_ENET0_MDIO 1 +#define IMX8QM_ENET0_MDIO_LSIO_GPIO4_IO13 IMX8QM_ENET0_MDIO 3 +#define IMX8QM_ENET0_MDC_CONN_ENET0_MDC IMX8QM_ENET0_MDC 0 +#define IMX8QM_ENET0_MDC_DMA_I2C4_SCL IMX8QM_ENET0_MDC 1 +#define IMX8QM_ENET0_MDC_LSIO_GPIO4_IO14 IMX8QM_ENET0_MDC 3 +#define IMX8QM_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M IMX8QM_ENET0_REFCLK_125M_25M 0 +#define IMX8QM_ENET0_REFCLK_125M_25M_CONN_ENET0_PPS IMX8QM_ENET0_REFCLK_125M_25M 1 +#define IMX8QM_ENET0_REFCLK_125M_25M_LSIO_GPIO4_IO15 IMX8QM_ENET0_REFCLK_125M_25M 3 +#define IMX8QM_ENET1_REFCLK_125M_25M_CONN_ENET1_REFCLK_125M_25M IMX8QM_ENET1_REFCLK_125M_25M 0 +#define IMX8QM_ENET1_REFCLK_125M_25M_CONN_ENET1_PPS IMX8QM_ENET1_REFCLK_125M_25M 1 +#define IMX8QM_ENET1_REFCLK_125M_25M_LSIO_GPIO4_IO16 IMX8QM_ENET1_REFCLK_125M_25M 3 +#define IMX8QM_ENET1_MDIO_CONN_ENET1_MDIO IMX8QM_ENET1_MDIO 0 +#define IMX8QM_ENET1_MDIO_DMA_I2C4_SDA IMX8QM_ENET1_MDIO 1 +#define IMX8QM_ENET1_MDIO_LSIO_GPIO4_IO17 IMX8QM_ENET1_MDIO 3 +#define IMX8QM_ENET1_MDC_CONN_ENET1_MDC IMX8QM_ENET1_MDC 0 +#define IMX8QM_ENET1_MDC_DMA_I2C4_SCL IMX8QM_ENET1_MDC 1 +#define IMX8QM_ENET1_MDC_LSIO_GPIO4_IO18 IMX8QM_ENET1_MDC 3 +#define IMX8QM_QSPI1A_SS0_B_LSIO_QSPI1A_SS0_B IMX8QM_QSPI1A_SS0_B 0 +#define IMX8QM_QSPI1A_SS0_B_LSIO_GPIO4_IO19 IMX8QM_QSPI1A_SS0_B 3 +#define IMX8QM_QSPI1A_SS1_B_LSIO_QSPI1A_SS1_B IMX8QM_QSPI1A_SS1_B 0 +#define IMX8QM_QSPI1A_SS1_B_LSIO_QSPI1A_SCLK2 IMX8QM_QSPI1A_SS1_B 1 +#define IMX8QM_QSPI1A_SS1_B_LSIO_GPIO4_IO20 IMX8QM_QSPI1A_SS1_B 3 +#define IMX8QM_QSPI1A_SCLK_LSIO_QSPI1A_SCLK IMX8QM_QSPI1A_SCLK 0 +#define IMX8QM_QSPI1A_SCLK_LSIO_GPIO4_IO21 IMX8QM_QSPI1A_SCLK 3 +#define IMX8QM_QSPI1A_DQS_LSIO_QSPI1A_DQS IMX8QM_QSPI1A_DQS 0 +#define IMX8QM_QSPI1A_DQS_LSIO_GPIO4_IO22 IMX8QM_QSPI1A_DQS 3 +#define IMX8QM_QSPI1A_DATA3_LSIO_QSPI1A_DATA3 IMX8QM_QSPI1A_DATA3 0 +#define IMX8QM_QSPI1A_DATA3_DMA_I2C1_SDA IMX8QM_QSPI1A_DATA3 1 +#define IMX8QM_QSPI1A_DATA3_CONN_USB_OTG1_OC IMX8QM_QSPI1A_DATA3 2 +#define IMX8QM_QSPI1A_DATA3_LSIO_GPIO4_IO23 IMX8QM_QSPI1A_DATA3 3 +#define IMX8QM_QSPI1A_DATA2_LSIO_QSPI1A_DATA2 IMX8QM_QSPI1A_DATA2 0 +#define IMX8QM_QSPI1A_DATA2_DMA_I2C1_SCL IMX8QM_QSPI1A_DATA2 1 +#define IMX8QM_QSPI1A_DATA2_CONN_USB_OTG2_PWR IMX8QM_QSPI1A_DATA2 2 +#define IMX8QM_QSPI1A_DATA2_LSIO_GPIO4_IO24 IMX8QM_QSPI1A_DATA2 3 +#define IMX8QM_QSPI1A_DATA1_LSIO_QSPI1A_DATA1 IMX8QM_QSPI1A_DATA1 0 +#define IMX8QM_QSPI1A_DATA1_DMA_I2C1_SDA IMX8QM_QSPI1A_DATA1 1 +#define IMX8QM_QSPI1A_DATA1_CONN_USB_OTG2_OC IMX8QM_QSPI1A_DATA1 2 +#define IMX8QM_QSPI1A_DATA1_LSIO_GPIO4_IO25 IMX8QM_QSPI1A_DATA1 3 +#define IMX8QM_QSPI1A_DATA0_LSIO_QSPI1A_DATA0 IMX8QM_QSPI1A_DATA0 0 +#define IMX8QM_QSPI1A_DATA0_LSIO_GPIO4_IO26 IMX8QM_QSPI1A_DATA0 3 +#define IMX8QM_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 IMX8QM_QSPI0A_DATA0 0 +#define IMX8QM_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 IMX8QM_QSPI0A_DATA1 0 +#define IMX8QM_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 IMX8QM_QSPI0A_DATA2 0 +#define IMX8QM_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 IMX8QM_QSPI0A_DATA3 0 +#define IMX8QM_QSPI0A_DQS_LSIO_QSPI0A_DQS IMX8QM_QSPI0A_DQS 0 +#define IMX8QM_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B IMX8QM_QSPI0A_SS0_B 0 +#define IMX8QM_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B IMX8QM_QSPI0A_SS1_B 0 +#define IMX8QM_QSPI0A_SS1_B_LSIO_QSPI0A_SCLK2 IMX8QM_QSPI0A_SS1_B 1 +#define IMX8QM_QSPI0A_SCLK_LSIO_QSPI0A_SCLK IMX8QM_QSPI0A_SCLK 0 +#define IMX8QM_QSPI0B_SCLK_LSIO_QSPI0B_SCLK IMX8QM_QSPI0B_SCLK 0 +#define IMX8QM_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 IMX8QM_QSPI0B_DATA0 0 +#define IMX8QM_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 IMX8QM_QSPI0B_DATA1 0 +#define IMX8QM_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 IMX8QM_QSPI0B_DATA2 0 +#define IMX8QM_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 IMX8QM_QSPI0B_DATA3 0 +#define IMX8QM_QSPI0B_DQS_LSIO_QSPI0B_DQS IMX8QM_QSPI0B_DQS 0 +#define IMX8QM_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B IMX8QM_QSPI0B_SS0_B 0 +#define IMX8QM_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B IMX8QM_QSPI0B_SS1_B 0 +#define IMX8QM_QSPI0B_SS1_B_LSIO_QSPI0B_SCLK2 IMX8QM_QSPI0B_SS1_B 1 +#define IMX8QM_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B IMX8QM_PCIE_CTRL0_CLKREQ_B 0 +#define IMX8QM_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27 IMX8QM_PCIE_CTRL0_CLKREQ_B 3 +#define IMX8QM_PCIE_CTRL0_WAKE_B_HSIO_PCIE0_WAKE_B IMX8QM_PCIE_CTRL0_WAKE_B 0 +#define IMX8QM_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 IMX8QM_PCIE_CTRL0_WAKE_B 3 +#define IMX8QM_PCIE_CTRL0_PERST_B_HSIO_PCIE0_PERST_B IMX8QM_PCIE_CTRL0_PERST_B 0 +#define IMX8QM_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 IMX8QM_PCIE_CTRL0_PERST_B 3 +#define IMX8QM_PCIE_CTRL1_CLKREQ_B_HSIO_PCIE1_CLKREQ_B IMX8QM_PCIE_CTRL1_CLKREQ_B 0 +#define IMX8QM_PCIE_CTRL1_CLKREQ_B_DMA_I2C1_SDA IMX8QM_PCIE_CTRL1_CLKREQ_B 1 +#define IMX8QM_PCIE_CTRL1_CLKREQ_B_CONN_USB_OTG2_OC IMX8QM_PCIE_CTRL1_CLKREQ_B 2 +#define IMX8QM_PCIE_CTRL1_CLKREQ_B_LSIO_GPIO4_IO30 IMX8QM_PCIE_CTRL1_CLKREQ_B 3 +#define IMX8QM_PCIE_CTRL1_WAKE_B_HSIO_PCIE1_WAKE_B IMX8QM_PCIE_CTRL1_WAKE_B 0 +#define IMX8QM_PCIE_CTRL1_WAKE_B_DMA_I2C1_SCL IMX8QM_PCIE_CTRL1_WAKE_B 1 +#define IMX8QM_PCIE_CTRL1_WAKE_B_CONN_USB_OTG2_PWR IMX8QM_PCIE_CTRL1_WAKE_B 2 +#define IMX8QM_PCIE_CTRL1_WAKE_B_LSIO_GPIO4_IO31 IMX8QM_PCIE_CTRL1_WAKE_B 3 +#define IMX8QM_PCIE_CTRL1_PERST_B_HSIO_PCIE1_PERST_B IMX8QM_PCIE_CTRL1_PERST_B 0 +#define IMX8QM_PCIE_CTRL1_PERST_B_DMA_I2C1_SCL IMX8QM_PCIE_CTRL1_PERST_B 1 +#define IMX8QM_PCIE_CTRL1_PERST_B_CONN_USB_OTG1_PWR IMX8QM_PCIE_CTRL1_PERST_B 2 +#define IMX8QM_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00 IMX8QM_PCIE_CTRL1_PERST_B 3 +#define IMX8QM_USB_HSIC0_DATA_CONN_USB_HSIC0_DATA IMX8QM_USB_HSIC0_DATA 0 +#define IMX8QM_USB_HSIC0_DATA_DMA_I2C1_SDA IMX8QM_USB_HSIC0_DATA 1 +#define IMX8QM_USB_HSIC0_DATA_LSIO_GPIO5_IO01 IMX8QM_USB_HSIC0_DATA 3 +#define IMX8QM_USB_HSIC0_STROBE_CONN_USB_HSIC0_STROBE IMX8QM_USB_HSIC0_STROBE 0 +#define IMX8QM_USB_HSIC0_STROBE_DMA_I2C1_SCL IMX8QM_USB_HSIC0_STROBE 1 +#define IMX8QM_USB_HSIC0_STROBE_LSIO_GPIO5_IO02 IMX8QM_USB_HSIC0_STROBE 3 +#define IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK IMX8QM_EMMC0_CLK 0 +#define IMX8QM_EMMC0_CLK_CONN_NAND_READY_B IMX8QM_EMMC0_CLK 1 +#define IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD IMX8QM_EMMC0_CMD 0 +#define IMX8QM_EMMC0_CMD_CONN_NAND_DQS IMX8QM_EMMC0_CMD 1 +#define IMX8QM_EMMC0_CMD_AUD_MQS_R IMX8QM_EMMC0_CMD 2 +#define IMX8QM_EMMC0_CMD_LSIO_GPIO5_IO03 IMX8QM_EMMC0_CMD 3 +#define IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 IMX8QM_EMMC0_DATA0 0 +#define IMX8QM_EMMC0_DATA0_CONN_NAND_DATA00 IMX8QM_EMMC0_DATA0 1 +#define IMX8QM_EMMC0_DATA0_LSIO_GPIO5_IO04 IMX8QM_EMMC0_DATA0 3 +#define IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 IMX8QM_EMMC0_DATA1 0 +#define IMX8QM_EMMC0_DATA1_CONN_NAND_DATA01 IMX8QM_EMMC0_DATA1 1 +#define IMX8QM_EMMC0_DATA1_LSIO_GPIO5_IO05 IMX8QM_EMMC0_DATA1 3 +#define IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 IMX8QM_EMMC0_DATA2 0 +#define IMX8QM_EMMC0_DATA2_CONN_NAND_DATA02 IMX8QM_EMMC0_DATA2 1 +#define IMX8QM_EMMC0_DATA2_LSIO_GPIO5_IO06 IMX8QM_EMMC0_DATA2 3 +#define IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 IMX8QM_EMMC0_DATA3 0 +#define IMX8QM_EMMC0_DATA3_CONN_NAND_DATA03 IMX8QM_EMMC0_DATA3 1 +#define IMX8QM_EMMC0_DATA3_LSIO_GPIO5_IO07 IMX8QM_EMMC0_DATA3 3 +#define IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 IMX8QM_EMMC0_DATA4 0 +#define IMX8QM_EMMC0_DATA4_CONN_NAND_DATA04 IMX8QM_EMMC0_DATA4 1 +#define IMX8QM_EMMC0_DATA4_LSIO_GPIO5_IO08 IMX8QM_EMMC0_DATA4 3 +#define IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 IMX8QM_EMMC0_DATA5 0 +#define IMX8QM_EMMC0_DATA5_CONN_NAND_DATA05 IMX8QM_EMMC0_DATA5 1 +#define IMX8QM_EMMC0_DATA5_LSIO_GPIO5_IO09 IMX8QM_EMMC0_DATA5 3 +#define IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 IMX8QM_EMMC0_DATA6 0 +#define IMX8QM_EMMC0_DATA6_CONN_NAND_DATA06 IMX8QM_EMMC0_DATA6 1 +#define IMX8QM_EMMC0_DATA6_LSIO_GPIO5_IO10 IMX8QM_EMMC0_DATA6 3 +#define IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 IMX8QM_EMMC0_DATA7 0 +#define IMX8QM_EMMC0_DATA7_CONN_NAND_DATA07 IMX8QM_EMMC0_DATA7 1 +#define IMX8QM_EMMC0_DATA7_LSIO_GPIO5_IO11 IMX8QM_EMMC0_DATA7 3 +#define IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE IMX8QM_EMMC0_STROBE 0 +#define IMX8QM_EMMC0_STROBE_CONN_NAND_CLE IMX8QM_EMMC0_STROBE 1 +#define IMX8QM_EMMC0_STROBE_LSIO_GPIO5_IO12 IMX8QM_EMMC0_STROBE 3 +#define IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B IMX8QM_EMMC0_RESET_B 0 +#define IMX8QM_EMMC0_RESET_B_CONN_NAND_WP_B IMX8QM_EMMC0_RESET_B 1 +#define IMX8QM_EMMC0_RESET_B_CONN_USDHC1_VSELECT IMX8QM_EMMC0_RESET_B 2 +#define IMX8QM_EMMC0_RESET_B_LSIO_GPIO5_IO13 IMX8QM_EMMC0_RESET_B 3 +#define IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK IMX8QM_USDHC1_CLK 0 +#define IMX8QM_USDHC1_CLK_AUD_MQS_R IMX8QM_USDHC1_CLK 1 +#define IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD IMX8QM_USDHC1_CMD 0 +#define IMX8QM_USDHC1_CMD_AUD_MQS_L IMX8QM_USDHC1_CMD 1 +#define IMX8QM_USDHC1_CMD_LSIO_GPIO5_IO14 IMX8QM_USDHC1_CMD 3 +#define IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 IMX8QM_USDHC1_DATA0 0 +#define IMX8QM_USDHC1_DATA0_CONN_NAND_RE_N IMX8QM_USDHC1_DATA0 1 +#define IMX8QM_USDHC1_DATA0_LSIO_GPIO5_IO15 IMX8QM_USDHC1_DATA0 3 +#define IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 IMX8QM_USDHC1_DATA1 0 +#define IMX8QM_USDHC1_DATA1_CONN_NAND_RE_P IMX8QM_USDHC1_DATA1 1 +#define IMX8QM_USDHC1_DATA1_LSIO_GPIO5_IO16 IMX8QM_USDHC1_DATA1 3 +#define IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 IMX8QM_USDHC1_DATA2 0 +#define IMX8QM_USDHC1_DATA2_CONN_NAND_DQS_N IMX8QM_USDHC1_DATA2 1 +#define IMX8QM_USDHC1_DATA2_LSIO_GPIO5_IO17 IMX8QM_USDHC1_DATA2 3 +#define IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 IMX8QM_USDHC1_DATA3 0 +#define IMX8QM_USDHC1_DATA3_CONN_NAND_DQS_P IMX8QM_USDHC1_DATA3 1 +#define IMX8QM_USDHC1_DATA3_LSIO_GPIO5_IO18 IMX8QM_USDHC1_DATA3 3 +#define IMX8QM_USDHC1_DATA4_CONN_USDHC1_DATA4 IMX8QM_USDHC1_DATA4 0 +#define IMX8QM_USDHC1_DATA4_CONN_NAND_CE0_B IMX8QM_USDHC1_DATA4 1 +#define IMX8QM_USDHC1_DATA4_AUD_MQS_R IMX8QM_USDHC1_DATA4 2 +#define IMX8QM_USDHC1_DATA4_LSIO_GPIO5_IO19 IMX8QM_USDHC1_DATA4 3 +#define IMX8QM_USDHC1_DATA5_CONN_USDHC1_DATA5 IMX8QM_USDHC1_DATA5 0 +#define IMX8QM_USDHC1_DATA5_CONN_NAND_RE_B IMX8QM_USDHC1_DATA5 1 +#define IMX8QM_USDHC1_DATA5_AUD_MQS_L IMX8QM_USDHC1_DATA5 2 +#define IMX8QM_USDHC1_DATA5_LSIO_GPIO5_IO20 IMX8QM_USDHC1_DATA5 3 +#define IMX8QM_USDHC1_DATA6_CONN_USDHC1_DATA6 IMX8QM_USDHC1_DATA6 0 +#define IMX8QM_USDHC1_DATA6_CONN_NAND_WE_B IMX8QM_USDHC1_DATA6 1 +#define IMX8QM_USDHC1_DATA6_CONN_USDHC1_WP IMX8QM_USDHC1_DATA6 2 +#define IMX8QM_USDHC1_DATA6_LSIO_GPIO5_IO21 IMX8QM_USDHC1_DATA6 3 +#define IMX8QM_USDHC1_DATA7_CONN_USDHC1_DATA7 IMX8QM_USDHC1_DATA7 0 +#define IMX8QM_USDHC1_DATA7_CONN_NAND_ALE IMX8QM_USDHC1_DATA7 1 +#define IMX8QM_USDHC1_DATA7_CONN_USDHC1_CD_B IMX8QM_USDHC1_DATA7 2 +#define IMX8QM_USDHC1_DATA7_LSIO_GPIO5_IO22 IMX8QM_USDHC1_DATA7 3 +#define IMX8QM_USDHC1_STROBE_CONN_USDHC1_STROBE IMX8QM_USDHC1_STROBE 0 +#define IMX8QM_USDHC1_STROBE_CONN_NAND_CE1_B IMX8QM_USDHC1_STROBE 1 +#define IMX8QM_USDHC1_STROBE_CONN_USDHC1_RESET_B IMX8QM_USDHC1_STROBE 2 +#define IMX8QM_USDHC1_STROBE_LSIO_GPIO5_IO23 IMX8QM_USDHC1_STROBE 3 +#define IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK IMX8QM_USDHC2_CLK 0 +#define IMX8QM_USDHC2_CLK_AUD_MQS_R IMX8QM_USDHC2_CLK 1 +#define IMX8QM_USDHC2_CLK_LSIO_GPIO5_IO24 IMX8QM_USDHC2_CLK 3 +#define IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD IMX8QM_USDHC2_CMD 0 +#define IMX8QM_USDHC2_CMD_AUD_MQS_L IMX8QM_USDHC2_CMD 1 +#define IMX8QM_USDHC2_CMD_LSIO_GPIO5_IO25 IMX8QM_USDHC2_CMD 3 +#define IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0 IMX8QM_USDHC2_DATA0 0 +#define IMX8QM_USDHC2_DATA0_DMA_UART4_RX IMX8QM_USDHC2_DATA0 1 +#define IMX8QM_USDHC2_DATA0_LSIO_GPIO5_IO26 IMX8QM_USDHC2_DATA0 3 +#define IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1 IMX8QM_USDHC2_DATA1 0 +#define IMX8QM_USDHC2_DATA1_DMA_UART4_TX IMX8QM_USDHC2_DATA1 1 +#define IMX8QM_USDHC2_DATA1_LSIO_GPIO5_IO27 IMX8QM_USDHC2_DATA1 3 +#define IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2 IMX8QM_USDHC2_DATA2 0 +#define IMX8QM_USDHC2_DATA2_DMA_UART4_CTS_B IMX8QM_USDHC2_DATA2 1 +#define IMX8QM_USDHC2_DATA2_LSIO_GPIO5_IO28 IMX8QM_USDHC2_DATA2 3 +#define IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3 IMX8QM_USDHC2_DATA3 0 +#define IMX8QM_USDHC2_DATA3_DMA_UART4_RTS_B IMX8QM_USDHC2_DATA3 1 +#define IMX8QM_USDHC2_DATA3_LSIO_GPIO5_IO29 IMX8QM_USDHC2_DATA3 3 +#define IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC IMX8QM_ENET0_RGMII_TXC 0 +#define IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT IMX8QM_ENET0_RGMII_TXC 1 +#define IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_IN IMX8QM_ENET0_RGMII_TXC 2 +#define IMX8QM_ENET0_RGMII_TXC_LSIO_GPIO5_IO30 IMX8QM_ENET0_RGMII_TXC 3 +#define IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL IMX8QM_ENET0_RGMII_TX_CTL 0 +#define IMX8QM_ENET0_RGMII_TX_CTL_LSIO_GPIO5_IO31 IMX8QM_ENET0_RGMII_TX_CTL 3 +#define IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 IMX8QM_ENET0_RGMII_TXD0 0 +#define IMX8QM_ENET0_RGMII_TXD0_LSIO_GPIO6_IO00 IMX8QM_ENET0_RGMII_TXD0 3 +#define IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 IMX8QM_ENET0_RGMII_TXD1 0 +#define IMX8QM_ENET0_RGMII_TXD1_LSIO_GPIO6_IO01 IMX8QM_ENET0_RGMII_TXD1 3 +#define IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 IMX8QM_ENET0_RGMII_TXD2 0 +#define IMX8QM_ENET0_RGMII_TXD2_DMA_UART3_TX IMX8QM_ENET0_RGMII_TXD2 1 +#define IMX8QM_ENET0_RGMII_TXD2_VPU_TSI_S1_VID IMX8QM_ENET0_RGMII_TXD2 2 +#define IMX8QM_ENET0_RGMII_TXD2_LSIO_GPIO6_IO02 IMX8QM_ENET0_RGMII_TXD2 3 +#define IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 IMX8QM_ENET0_RGMII_TXD3 0 +#define IMX8QM_ENET0_RGMII_TXD3_DMA_UART3_RTS_B IMX8QM_ENET0_RGMII_TXD3 1 +#define IMX8QM_ENET0_RGMII_TXD3_VPU_TSI_S1_SYNC IMX8QM_ENET0_RGMII_TXD3 2 +#define IMX8QM_ENET0_RGMII_TXD3_LSIO_GPIO6_IO03 IMX8QM_ENET0_RGMII_TXD3 3 +#define IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC IMX8QM_ENET0_RGMII_RXC 0 +#define IMX8QM_ENET0_RGMII_RXC_DMA_UART3_CTS_B IMX8QM_ENET0_RGMII_RXC 1 +#define IMX8QM_ENET0_RGMII_RXC_VPU_TSI_S1_DATA IMX8QM_ENET0_RGMII_RXC 2 +#define IMX8QM_ENET0_RGMII_RXC_LSIO_GPIO6_IO04 IMX8QM_ENET0_RGMII_RXC 3 +#define IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL IMX8QM_ENET0_RGMII_RX_CTL 0 +#define IMX8QM_ENET0_RGMII_RX_CTL_VPU_TSI_S0_VID IMX8QM_ENET0_RGMII_RX_CTL 2 +#define IMX8QM_ENET0_RGMII_RX_CTL_LSIO_GPIO6_IO05 IMX8QM_ENET0_RGMII_RX_CTL 3 +#define IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 IMX8QM_ENET0_RGMII_RXD0 0 +#define IMX8QM_ENET0_RGMII_RXD0_VPU_TSI_S0_SYNC IMX8QM_ENET0_RGMII_RXD0 2 +#define IMX8QM_ENET0_RGMII_RXD0_LSIO_GPIO6_IO06 IMX8QM_ENET0_RGMII_RXD0 3 +#define IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 IMX8QM_ENET0_RGMII_RXD1 0 +#define IMX8QM_ENET0_RGMII_RXD1_VPU_TSI_S0_DATA IMX8QM_ENET0_RGMII_RXD1 2 +#define IMX8QM_ENET0_RGMII_RXD1_LSIO_GPIO6_IO07 IMX8QM_ENET0_RGMII_RXD1 3 +#define IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 IMX8QM_ENET0_RGMII_RXD2 0 +#define IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER IMX8QM_ENET0_RGMII_RXD2 1 +#define IMX8QM_ENET0_RGMII_RXD2_VPU_TSI_S0_CLK IMX8QM_ENET0_RGMII_RXD2 2 +#define IMX8QM_ENET0_RGMII_RXD2_LSIO_GPIO6_IO08 IMX8QM_ENET0_RGMII_RXD2 3 +#define IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 IMX8QM_ENET0_RGMII_RXD3 0 +#define IMX8QM_ENET0_RGMII_RXD3_DMA_UART3_RX IMX8QM_ENET0_RGMII_RXD3 1 +#define IMX8QM_ENET0_RGMII_RXD3_VPU_TSI_S1_CLK IMX8QM_ENET0_RGMII_RXD3 2 +#define IMX8QM_ENET0_RGMII_RXD3_LSIO_GPIO6_IO09 IMX8QM_ENET0_RGMII_RXD3 3 +#define IMX8QM_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC IMX8QM_ENET1_RGMII_TXC 0 +#define IMX8QM_ENET1_RGMII_TXC_CONN_ENET1_RCLK50M_OUT IMX8QM_ENET1_RGMII_TXC 1 +#define IMX8QM_ENET1_RGMII_TXC_CONN_ENET1_RCLK50M_IN IMX8QM_ENET1_RGMII_TXC 2 +#define IMX8QM_ENET1_RGMII_TXC_LSIO_GPIO6_IO10 IMX8QM_ENET1_RGMII_TXC 3 +#define IMX8QM_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL IMX8QM_ENET1_RGMII_TX_CTL 0 +#define IMX8QM_ENET1_RGMII_TX_CTL_LSIO_GPIO6_IO11 IMX8QM_ENET1_RGMII_TX_CTL 3 +#define IMX8QM_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 IMX8QM_ENET1_RGMII_TXD0 0 +#define IMX8QM_ENET1_RGMII_TXD0_LSIO_GPIO6_IO12 IMX8QM_ENET1_RGMII_TXD0 3 +#define IMX8QM_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 IMX8QM_ENET1_RGMII_TXD1 0 +#define IMX8QM_ENET1_RGMII_TXD1_LSIO_GPIO6_IO13 IMX8QM_ENET1_RGMII_TXD1 3 +#define IMX8QM_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 IMX8QM_ENET1_RGMII_TXD2 0 +#define IMX8QM_ENET1_RGMII_TXD2_DMA_UART3_TX IMX8QM_ENET1_RGMII_TXD2 1 +#define IMX8QM_ENET1_RGMII_TXD2_VPU_TSI_S1_VID IMX8QM_ENET1_RGMII_TXD2 2 +#define IMX8QM_ENET1_RGMII_TXD2_LSIO_GPIO6_IO14 IMX8QM_ENET1_RGMII_TXD2 3 +#define IMX8QM_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 IMX8QM_ENET1_RGMII_TXD3 0 +#define IMX8QM_ENET1_RGMII_TXD3_DMA_UART3_RTS_B IMX8QM_ENET1_RGMII_TXD3 1 +#define IMX8QM_ENET1_RGMII_TXD3_VPU_TSI_S1_SYNC IMX8QM_ENET1_RGMII_TXD3 2 +#define IMX8QM_ENET1_RGMII_TXD3_LSIO_GPIO6_IO15 IMX8QM_ENET1_RGMII_TXD3 3 +#define IMX8QM_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC IMX8QM_ENET1_RGMII_RXC 0 +#define IMX8QM_ENET1_RGMII_RXC_DMA_UART3_CTS_B IMX8QM_ENET1_RGMII_RXC 1 +#define IMX8QM_ENET1_RGMII_RXC_VPU_TSI_S1_DATA IMX8QM_ENET1_RGMII_RXC 2 +#define IMX8QM_ENET1_RGMII_RXC_LSIO_GPIO6_IO16 IMX8QM_ENET1_RGMII_RXC 3 +#define IMX8QM_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL IMX8QM_ENET1_RGMII_RX_CTL 0 +#define IMX8QM_ENET1_RGMII_RX_CTL_VPU_TSI_S0_VID IMX8QM_ENET1_RGMII_RX_CTL 2 +#define IMX8QM_ENET1_RGMII_RX_CTL_LSIO_GPIO6_IO17 IMX8QM_ENET1_RGMII_RX_CTL 3 +#define IMX8QM_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 IMX8QM_ENET1_RGMII_RXD0 0 +#define IMX8QM_ENET1_RGMII_RXD0_VPU_TSI_S0_SYNC IMX8QM_ENET1_RGMII_RXD0 2 +#define IMX8QM_ENET1_RGMII_RXD0_LSIO_GPIO6_IO18 IMX8QM_ENET1_RGMII_RXD0 3 +#define IMX8QM_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 IMX8QM_ENET1_RGMII_RXD1 0 +#define IMX8QM_ENET1_RGMII_RXD1_VPU_TSI_S0_DATA IMX8QM_ENET1_RGMII_RXD1 2 +#define IMX8QM_ENET1_RGMII_RXD1_LSIO_GPIO6_IO19 IMX8QM_ENET1_RGMII_RXD1 3 +#define IMX8QM_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 IMX8QM_ENET1_RGMII_RXD2 0 +#define IMX8QM_ENET1_RGMII_RXD2_CONN_ENET1_RMII_RX_ER IMX8QM_ENET1_RGMII_RXD2 1 +#define IMX8QM_ENET1_RGMII_RXD2_VPU_TSI_S0_CLK IMX8QM_ENET1_RGMII_RXD2 2 +#define IMX8QM_ENET1_RGMII_RXD2_LSIO_GPIO6_IO20 IMX8QM_ENET1_RGMII_RXD2 3 +#define IMX8QM_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 IMX8QM_ENET1_RGMII_RXD3 0 +#define IMX8QM_ENET1_RGMII_RXD3_DMA_UART3_RX IMX8QM_ENET1_RGMII_RXD3 1 +#define IMX8QM_ENET1_RGMII_RXD3_VPU_TSI_S1_CLK IMX8QM_ENET1_RGMII_RXD3 2 +#define IMX8QM_ENET1_RGMII_RXD3_LSIO_GPIO6_IO21 IMX8QM_ENET1_RGMII_RXD3 3 +#define IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB 0 +#define IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA 0 + +#endif /* _IMX8QM_PADS_H */ diff --git a/include/dt-bindings/pinctrl/pads-imx8qxp.h b/include/dt-bindings/pinctrl/pads-imx8qxp.h new file mode 100644 index 000000000000..fbfee7ecf844 --- /dev/null +++ b/include/dt-bindings/pinctrl/pads-imx8qxp.h @@ -0,0 +1,751 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017~2018 NXP + */ + +#ifndef _IMX8QXP_PADS_H +#define _IMX8QXP_PADS_H + +/* pin id */ +#define IMX8QXP_PCIE_CTRL0_PERST_B 0 +#define IMX8QXP_PCIE_CTRL0_CLKREQ_B 1 +#define IMX8QXP_PCIE_CTRL0_WAKE_B 2 +#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_PCIESEP 3 +#define IMX8QXP_USB_SS3_TC0 4 +#define IMX8QXP_USB_SS3_TC1 5 +#define IMX8QXP_USB_SS3_TC2 6 +#define IMX8QXP_USB_SS3_TC3 7 +#define IMX8QXP_COMP_CTL_GPIO_3V3_USB3IO 8 +#define IMX8QXP_EMMC0_CLK 9 +#define IMX8QXP_EMMC0_CMD 10 +#define IMX8QXP_EMMC0_DATA0 11 +#define IMX8QXP_EMMC0_DATA1 12 +#define IMX8QXP_EMMC0_DATA2 13 +#define IMX8QXP_EMMC0_DATA3 14 +#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_SD1FIX0 15 +#define IMX8QXP_EMMC0_DATA4 16 +#define IMX8QXP_EMMC0_DATA5 17 +#define IMX8QXP_EMMC0_DATA6 18 +#define IMX8QXP_EMMC0_DATA7 19 +#define IMX8QXP_EMMC0_STROBE 20 +#define IMX8QXP_EMMC0_RESET_B 21 +#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_SD1FIX1 22 +#define IMX8QXP_USDHC1_RESET_B 23 +#define IMX8QXP_USDHC1_VSELECT 24 +#define IMX8QXP_CTL_NAND_RE_P_N 25 +#define IMX8QXP_USDHC1_WP 26 +#define IMX8QXP_USDHC1_CD_B 27 +#define IMX8QXP_CTL_NAND_DQS_P_N 28 +#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_VSELSEP 29 +#define IMX8QXP_USDHC1_CLK 30 +#define IMX8QXP_USDHC1_CMD 31 +#define IMX8QXP_USDHC1_DATA0 32 +#define IMX8QXP_USDHC1_DATA1 33 +#define IMX8QXP_USDHC1_DATA2 34 +#define IMX8QXP_USDHC1_DATA3 35 +#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_VSEL3 36 +#define IMX8QXP_ENET0_RGMII_TXC 37 +#define IMX8QXP_ENET0_RGMII_TX_CTL 38 +#define IMX8QXP_ENET0_RGMII_TXD0 39 +#define IMX8QXP_ENET0_RGMII_TXD1 40 +#define IMX8QXP_ENET0_RGMII_TXD2 41 +#define IMX8QXP_ENET0_RGMII_TXD3 42 +#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 43 +#define IMX8QXP_ENET0_RGMII_RXC 44 +#define IMX8QXP_ENET0_RGMII_RX_CTL 45 +#define IMX8QXP_ENET0_RGMII_RXD0 46 +#define IMX8QXP_ENET0_RGMII_RXD1 47 +#define IMX8QXP_ENET0_RGMII_RXD2 48 +#define IMX8QXP_ENET0_RGMII_RXD3 49 +#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 50 +#define IMX8QXP_ENET0_REFCLK_125M_25M 51 +#define IMX8QXP_ENET0_MDIO 52 +#define IMX8QXP_ENET0_MDC 53 +#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIOCT 54 +#define IMX8QXP_ESAI0_FSR 55 +#define IMX8QXP_ESAI0_FST 56 +#define IMX8QXP_ESAI0_SCKR 57 +#define IMX8QXP_ESAI0_SCKT 58 +#define IMX8QXP_ESAI0_TX0 59 +#define IMX8QXP_ESAI0_TX1 60 +#define IMX8QXP_ESAI0_TX2_RX3 61 +#define IMX8QXP_ESAI0_TX3_RX2 62 +#define IMX8QXP_ESAI0_TX4_RX1 63 +#define IMX8QXP_ESAI0_TX5_RX0 64 +#define IMX8QXP_SPDIF0_RX 65 +#define IMX8QXP_SPDIF0_TX 66 +#define IMX8QXP_SPDIF0_EXT_CLK 67 +#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHB 68 +#define IMX8QXP_SPI3_SCK 69 +#define IMX8QXP_SPI3_SDO 70 +#define IMX8QXP_SPI3_SDI 71 +#define IMX8QXP_SPI3_CS0 72 +#define IMX8QXP_SPI3_CS1 73 +#define IMX8QXP_MCLK_IN1 74 +#define IMX8QXP_MCLK_IN0 75 +#define IMX8QXP_MCLK_OUT0 76 +#define IMX8QXP_UART1_TX 77 +#define IMX8QXP_UART1_RX 78 +#define IMX8QXP_UART1_RTS_B 79 +#define IMX8QXP_UART1_CTS_B 80 +#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHK 81 +#define IMX8QXP_SAI0_TXD 82 +#define IMX8QXP_SAI0_TXC 83 +#define IMX8QXP_SAI0_RXD 84 +#define IMX8QXP_SAI0_TXFS 85 +#define IMX8QXP_SAI1_RXD 86 +#define IMX8QXP_SAI1_RXC 87 +#define IMX8QXP_SAI1_RXFS 88 +#define IMX8QXP_SPI2_CS0 89 +#define IMX8QXP_SPI2_SDO 90 +#define IMX8QXP_SPI2_SDI 91 +#define IMX8QXP_SPI2_SCK 92 +#define IMX8QXP_SPI0_SCK 93 +#define IMX8QXP_SPI0_SDI 94 +#define IMX8QXP_SPI0_SDO 95 +#define IMX8QXP_SPI0_CS1 96 +#define IMX8QXP_SPI0_CS0 97 +#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHT 98 +#define IMX8QXP_ADC_IN1 99 +#define IMX8QXP_ADC_IN0 100 +#define IMX8QXP_ADC_IN3 101 +#define IMX8QXP_ADC_IN2 102 +#define IMX8QXP_ADC_IN5 103 +#define IMX8QXP_ADC_IN4 104 +#define IMX8QXP_FLEXCAN0_RX 105 +#define IMX8QXP_FLEXCAN0_TX 106 +#define IMX8QXP_FLEXCAN1_RX 107 +#define IMX8QXP_FLEXCAN1_TX 108 +#define IMX8QXP_FLEXCAN2_RX 109 +#define IMX8QXP_FLEXCAN2_TX 110 +#define IMX8QXP_UART0_RX 111 +#define IMX8QXP_UART0_TX 112 +#define IMX8QXP_UART2_TX 113 +#define IMX8QXP_UART2_RX 114 +#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIOLH 115 +#define IMX8QXP_MIPI_DSI0_I2C0_SCL 116 +#define IMX8QXP_MIPI_DSI0_I2C0_SDA 117 +#define IMX8QXP_MIPI_DSI0_GPIO0_00 118 +#define IMX8QXP_MIPI_DSI0_GPIO0_01 119 +#define IMX8QXP_MIPI_DSI1_I2C0_SCL 120 +#define IMX8QXP_MIPI_DSI1_I2C0_SDA 121 +#define IMX8QXP_MIPI_DSI1_GPIO0_00 122 +#define IMX8QXP_MIPI_DSI1_GPIO0_01 123 +#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO 124 +#define IMX8QXP_JTAG_TRST_B 125 +#define IMX8QXP_PMIC_I2C_SCL 126 +#define IMX8QXP_PMIC_I2C_SDA 127 +#define IMX8QXP_PMIC_INT_B 128 +#define IMX8QXP_SCU_GPIO0_00 129 +#define IMX8QXP_SCU_GPIO0_01 130 +#define IMX8QXP_SCU_PMIC_STANDBY 131 +#define IMX8QXP_SCU_BOOT_MODE0 132 +#define IMX8QXP_SCU_BOOT_MODE1 133 +#define IMX8QXP_SCU_BOOT_MODE2 134 +#define IMX8QXP_SCU_BOOT_MODE3 135 +#define IMX8QXP_CSI_D00 136 +#define IMX8QXP_CSI_D01 137 +#define IMX8QXP_CSI_D02 138 +#define IMX8QXP_CSI_D03 139 +#define IMX8QXP_CSI_D04 140 +#define IMX8QXP_CSI_D05 141 +#define IMX8QXP_CSI_D06 142 +#define IMX8QXP_CSI_D07 143 +#define IMX8QXP_CSI_HSYNC 144 +#define IMX8QXP_CSI_VSYNC 145 +#define IMX8QXP_CSI_PCLK 146 +#define IMX8QXP_CSI_MCLK 147 +#define IMX8QXP_CSI_EN 148 +#define IMX8QXP_CSI_RESET 149 +#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHD 150 +#define IMX8QXP_MIPI_CSI0_MCLK_OUT 151 +#define IMX8QXP_MIPI_CSI0_I2C0_SCL 152 +#define IMX8QXP_MIPI_CSI0_I2C0_SDA 153 +#define IMX8QXP_MIPI_CSI0_GPIO0_01 154 +#define IMX8QXP_MIPI_CSI0_GPIO0_00 155 +#define IMX8QXP_QSPI0A_DATA0 156 +#define IMX8QXP_QSPI0A_DATA1 157 +#define IMX8QXP_QSPI0A_DATA2 158 +#define IMX8QXP_QSPI0A_DATA3 159 +#define IMX8QXP_QSPI0A_DQS 160 +#define IMX8QXP_QSPI0A_SS0_B 161 +#define IMX8QXP_QSPI0A_SS1_B 162 +#define IMX8QXP_QSPI0A_SCLK 163 +#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_QSPI0A 164 +#define IMX8QXP_QSPI0B_SCLK 165 +#define IMX8QXP_QSPI0B_DATA0 166 +#define IMX8QXP_QSPI0B_DATA1 167 +#define IMX8QXP_QSPI0B_DATA2 168 +#define IMX8QXP_QSPI0B_DATA3 169 +#define IMX8QXP_QSPI0B_DQS 170 +#define IMX8QXP_QSPI0B_SS0_B 171 +#define IMX8QXP_QSPI0B_SS1_B 172 +#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_QSPI0B 173 + +/* + * format: <pin_id mux_mode> + */ +#define IMX8QXP_PCIE_CTRL0_PERST_B_HSIO_PCIE0_PERST_B IMX8QXP_PCIE_CTRL0_PERST_B 0 +#define IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 IMX8QXP_PCIE_CTRL0_PERST_B 4 +#define IMX8QXP_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B IMX8QXP_PCIE_CTRL0_CLKREQ_B 0 +#define IMX8QXP_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 IMX8QXP_PCIE_CTRL0_CLKREQ_B 4 +#define IMX8QXP_PCIE_CTRL0_WAKE_B_HSIO_PCIE0_WAKE_B IMX8QXP_PCIE_CTRL0_WAKE_B 0 +#define IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 IMX8QXP_PCIE_CTRL0_WAKE_B 4 +#define IMX8QXP_USB_SS3_TC0_ADMA_I2C1_SCL IMX8QXP_USB_SS3_TC0 0 +#define IMX8QXP_USB_SS3_TC0_CONN_USB_OTG1_PWR IMX8QXP_USB_SS3_TC0 1 +#define IMX8QXP_USB_SS3_TC0_CONN_USB_OTG2_PWR IMX8QXP_USB_SS3_TC0 2 +#define IMX8QXP_USB_SS3_TC0_LSIO_GPIO4_IO03 IMX8QXP_USB_SS3_TC0 4 +#define IMX8QXP_USB_SS3_TC1_ADMA_I2C1_SCL IMX8QXP_USB_SS3_TC1 0 +#define IMX8QXP_USB_SS3_TC1_CONN_USB_OTG2_PWR IMX8QXP_USB_SS3_TC1 1 +#define IMX8QXP_USB_SS3_TC1_LSIO_GPIO4_IO04 IMX8QXP_USB_SS3_TC1 4 +#define IMX8QXP_USB_SS3_TC2_ADMA_I2C1_SDA IMX8QXP_USB_SS3_TC2 0 +#define IMX8QXP_USB_SS3_TC2_CONN_USB_OTG1_OC IMX8QXP_USB_SS3_TC2 1 +#define IMX8QXP_USB_SS3_TC2_CONN_USB_OTG2_OC IMX8QXP_USB_SS3_TC2 2 +#define IMX8QXP_USB_SS3_TC2_LSIO_GPIO4_IO05 IMX8QXP_USB_SS3_TC2 4 +#define IMX8QXP_USB_SS3_TC3_ADMA_I2C1_SDA IMX8QXP_USB_SS3_TC3 0 +#define IMX8QXP_USB_SS3_TC3_CONN_USB_OTG2_OC IMX8QXP_USB_SS3_TC3 1 +#define IMX8QXP_USB_SS3_TC3_LSIO_GPIO4_IO06 IMX8QXP_USB_SS3_TC3 4 +#define IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK IMX8QXP_EMMC0_CLK 0 +#define IMX8QXP_EMMC0_CLK_CONN_NAND_READY_B IMX8QXP_EMMC0_CLK 1 +#define IMX8QXP_EMMC0_CLK_LSIO_GPIO4_IO07 IMX8QXP_EMMC0_CLK 4 +#define IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD IMX8QXP_EMMC0_CMD 0 +#define IMX8QXP_EMMC0_CMD_CONN_NAND_DQS IMX8QXP_EMMC0_CMD 1 +#define IMX8QXP_EMMC0_CMD_LSIO_GPIO4_IO08 IMX8QXP_EMMC0_CMD 4 +#define IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 IMX8QXP_EMMC0_DATA0 0 +#define IMX8QXP_EMMC0_DATA0_CONN_NAND_DATA00 IMX8QXP_EMMC0_DATA0 1 +#define IMX8QXP_EMMC0_DATA0_LSIO_GPIO4_IO09 IMX8QXP_EMMC0_DATA0 4 +#define IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 IMX8QXP_EMMC0_DATA1 0 +#define IMX8QXP_EMMC0_DATA1_CONN_NAND_DATA01 IMX8QXP_EMMC0_DATA1 1 +#define IMX8QXP_EMMC0_DATA1_LSIO_GPIO4_IO10 IMX8QXP_EMMC0_DATA1 4 +#define IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 IMX8QXP_EMMC0_DATA2 0 +#define IMX8QXP_EMMC0_DATA2_CONN_NAND_DATA02 IMX8QXP_EMMC0_DATA2 1 +#define IMX8QXP_EMMC0_DATA2_LSIO_GPIO4_IO11 IMX8QXP_EMMC0_DATA2 4 +#define IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 IMX8QXP_EMMC0_DATA3 0 +#define IMX8QXP_EMMC0_DATA3_CONN_NAND_DATA03 IMX8QXP_EMMC0_DATA3 1 +#define IMX8QXP_EMMC0_DATA3_LSIO_GPIO4_IO12 IMX8QXP_EMMC0_DATA3 4 +#define IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 IMX8QXP_EMMC0_DATA4 0 +#define IMX8QXP_EMMC0_DATA4_CONN_NAND_DATA04 IMX8QXP_EMMC0_DATA4 1 +#define IMX8QXP_EMMC0_DATA4_CONN_EMMC0_WP IMX8QXP_EMMC0_DATA4 3 +#define IMX8QXP_EMMC0_DATA4_LSIO_GPIO4_IO13 IMX8QXP_EMMC0_DATA4 4 +#define IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 IMX8QXP_EMMC0_DATA5 0 +#define IMX8QXP_EMMC0_DATA5_CONN_NAND_DATA05 IMX8QXP_EMMC0_DATA5 1 +#define IMX8QXP_EMMC0_DATA5_CONN_EMMC0_VSELECT IMX8QXP_EMMC0_DATA5 3 +#define IMX8QXP_EMMC0_DATA5_LSIO_GPIO4_IO14 IMX8QXP_EMMC0_DATA5 4 +#define IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 IMX8QXP_EMMC0_DATA6 0 +#define IMX8QXP_EMMC0_DATA6_CONN_NAND_DATA06 IMX8QXP_EMMC0_DATA6 1 +#define IMX8QXP_EMMC0_DATA6_CONN_MLB_CLK IMX8QXP_EMMC0_DATA6 3 +#define IMX8QXP_EMMC0_DATA6_LSIO_GPIO4_IO15 IMX8QXP_EMMC0_DATA6 4 +#define IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 IMX8QXP_EMMC0_DATA7 0 +#define IMX8QXP_EMMC0_DATA7_CONN_NAND_DATA07 IMX8QXP_EMMC0_DATA7 1 +#define IMX8QXP_EMMC0_DATA7_CONN_MLB_SIG IMX8QXP_EMMC0_DATA7 3 +#define IMX8QXP_EMMC0_DATA7_LSIO_GPIO4_IO16 IMX8QXP_EMMC0_DATA7 4 +#define IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE IMX8QXP_EMMC0_STROBE 0 +#define IMX8QXP_EMMC0_STROBE_CONN_NAND_CLE IMX8QXP_EMMC0_STROBE 1 +#define IMX8QXP_EMMC0_STROBE_CONN_MLB_DATA IMX8QXP_EMMC0_STROBE 3 +#define IMX8QXP_EMMC0_STROBE_LSIO_GPIO4_IO17 IMX8QXP_EMMC0_STROBE 4 +#define IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B IMX8QXP_EMMC0_RESET_B 0 +#define IMX8QXP_EMMC0_RESET_B_CONN_NAND_WP_B IMX8QXP_EMMC0_RESET_B 1 +#define IMX8QXP_EMMC0_RESET_B_LSIO_GPIO4_IO18 IMX8QXP_EMMC0_RESET_B 4 +#define IMX8QXP_USDHC1_RESET_B_CONN_USDHC1_RESET_B IMX8QXP_USDHC1_RESET_B 0 +#define IMX8QXP_USDHC1_RESET_B_CONN_NAND_RE_N IMX8QXP_USDHC1_RESET_B 1 +#define IMX8QXP_USDHC1_RESET_B_ADMA_SPI2_SCK IMX8QXP_USDHC1_RESET_B 2 +#define IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19 IMX8QXP_USDHC1_RESET_B 4 +#define IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT IMX8QXP_USDHC1_VSELECT 0 +#define IMX8QXP_USDHC1_VSELECT_CONN_NAND_RE_P IMX8QXP_USDHC1_VSELECT 1 +#define IMX8QXP_USDHC1_VSELECT_ADMA_SPI2_SDO IMX8QXP_USDHC1_VSELECT 2 +#define IMX8QXP_USDHC1_VSELECT_CONN_NAND_RE_B IMX8QXP_USDHC1_VSELECT 3 +#define IMX8QXP_USDHC1_VSELECT_LSIO_GPIO4_IO20 IMX8QXP_USDHC1_VSELECT 4 +#define IMX8QXP_USDHC1_WP_CONN_USDHC1_WP IMX8QXP_USDHC1_WP 0 +#define IMX8QXP_USDHC1_WP_CONN_NAND_DQS_N IMX8QXP_USDHC1_WP 1 +#define IMX8QXP_USDHC1_WP_ADMA_SPI2_SDI IMX8QXP_USDHC1_WP 2 +#define IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21 IMX8QXP_USDHC1_WP 4 +#define IMX8QXP_USDHC1_CD_B_CONN_USDHC1_CD_B IMX8QXP_USDHC1_CD_B 0 +#define IMX8QXP_USDHC1_CD_B_CONN_NAND_DQS_P IMX8QXP_USDHC1_CD_B 1 +#define IMX8QXP_USDHC1_CD_B_ADMA_SPI2_CS0 IMX8QXP_USDHC1_CD_B 2 +#define IMX8QXP_USDHC1_CD_B_CONN_NAND_DQS IMX8QXP_USDHC1_CD_B 3 +#define IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22 IMX8QXP_USDHC1_CD_B 4 +#define IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK IMX8QXP_USDHC1_CLK 0 +#define IMX8QXP_USDHC1_CLK_ADMA_UART3_RX IMX8QXP_USDHC1_CLK 2 +#define IMX8QXP_USDHC1_CLK_LSIO_GPIO4_IO23 IMX8QXP_USDHC1_CLK 4 +#define IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD IMX8QXP_USDHC1_CMD 0 +#define IMX8QXP_USDHC1_CMD_CONN_NAND_CE0_B IMX8QXP_USDHC1_CMD 1 +#define IMX8QXP_USDHC1_CMD_ADMA_MQS_R IMX8QXP_USDHC1_CMD 2 +#define IMX8QXP_USDHC1_CMD_LSIO_GPIO4_IO24 IMX8QXP_USDHC1_CMD 4 +#define IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 IMX8QXP_USDHC1_DATA0 0 +#define IMX8QXP_USDHC1_DATA0_CONN_NAND_CE1_B IMX8QXP_USDHC1_DATA0 1 +#define IMX8QXP_USDHC1_DATA0_ADMA_MQS_L IMX8QXP_USDHC1_DATA0 2 +#define IMX8QXP_USDHC1_DATA0_LSIO_GPIO4_IO25 IMX8QXP_USDHC1_DATA0 4 +#define IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 IMX8QXP_USDHC1_DATA1 0 +#define IMX8QXP_USDHC1_DATA1_CONN_NAND_RE_B IMX8QXP_USDHC1_DATA1 1 +#define IMX8QXP_USDHC1_DATA1_ADMA_UART3_TX IMX8QXP_USDHC1_DATA1 2 +#define IMX8QXP_USDHC1_DATA1_LSIO_GPIO4_IO26 IMX8QXP_USDHC1_DATA1 4 +#define IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 IMX8QXP_USDHC1_DATA2 0 +#define IMX8QXP_USDHC1_DATA2_CONN_NAND_WE_B IMX8QXP_USDHC1_DATA2 1 +#define IMX8QXP_USDHC1_DATA2_ADMA_UART3_CTS_B IMX8QXP_USDHC1_DATA2 2 +#define IMX8QXP_USDHC1_DATA2_LSIO_GPIO4_IO27 IMX8QXP_USDHC1_DATA2 4 +#define IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 IMX8QXP_USDHC1_DATA3 0 +#define IMX8QXP_USDHC1_DATA3_CONN_NAND_ALE IMX8QXP_USDHC1_DATA3 1 +#define IMX8QXP_USDHC1_DATA3_ADMA_UART3_RTS_B IMX8QXP_USDHC1_DATA3 2 +#define IMX8QXP_USDHC1_DATA3_LSIO_GPIO4_IO28 IMX8QXP_USDHC1_DATA3 4 +#define IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC IMX8QXP_ENET0_RGMII_TXC 0 +#define IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT IMX8QXP_ENET0_RGMII_TXC 1 +#define IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_IN IMX8QXP_ENET0_RGMII_TXC 2 +#define IMX8QXP_ENET0_RGMII_TXC_CONN_NAND_CE1_B IMX8QXP_ENET0_RGMII_TXC 3 +#define IMX8QXP_ENET0_RGMII_TXC_LSIO_GPIO4_IO29 IMX8QXP_ENET0_RGMII_TXC 4 +#define IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL IMX8QXP_ENET0_RGMII_TX_CTL 0 +#define IMX8QXP_ENET0_RGMII_TX_CTL_CONN_USDHC1_RESET_B IMX8QXP_ENET0_RGMII_TX_CTL 3 +#define IMX8QXP_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 IMX8QXP_ENET0_RGMII_TX_CTL 4 +#define IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 IMX8QXP_ENET0_RGMII_TXD0 0 +#define IMX8QXP_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT IMX8QXP_ENET0_RGMII_TXD0 3 +#define IMX8QXP_ENET0_RGMII_TXD0_LSIO_GPIO4_IO31 IMX8QXP_ENET0_RGMII_TXD0 4 +#define IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 IMX8QXP_ENET0_RGMII_TXD1 0 +#define IMX8QXP_ENET0_RGMII_TXD1_CONN_USDHC1_WP IMX8QXP_ENET0_RGMII_TXD1 3 +#define IMX8QXP_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 IMX8QXP_ENET0_RGMII_TXD1 4 +#define IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 IMX8QXP_ENET0_RGMII_TXD2 0 +#define IMX8QXP_ENET0_RGMII_TXD2_CONN_MLB_CLK IMX8QXP_ENET0_RGMII_TXD2 1 +#define IMX8QXP_ENET0_RGMII_TXD2_CONN_NAND_CE0_B IMX8QXP_ENET0_RGMII_TXD2 2 +#define IMX8QXP_ENET0_RGMII_TXD2_CONN_USDHC1_CD_B IMX8QXP_ENET0_RGMII_TXD2 3 +#define IMX8QXP_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 IMX8QXP_ENET0_RGMII_TXD2 4 +#define IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 IMX8QXP_ENET0_RGMII_TXD3 0 +#define IMX8QXP_ENET0_RGMII_TXD3_CONN_MLB_SIG IMX8QXP_ENET0_RGMII_TXD3 1 +#define IMX8QXP_ENET0_RGMII_TXD3_CONN_NAND_RE_B IMX8QXP_ENET0_RGMII_TXD3 2 +#define IMX8QXP_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02 IMX8QXP_ENET0_RGMII_TXD3 4 +#define IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC IMX8QXP_ENET0_RGMII_RXC 0 +#define IMX8QXP_ENET0_RGMII_RXC_CONN_MLB_DATA IMX8QXP_ENET0_RGMII_RXC 1 +#define IMX8QXP_ENET0_RGMII_RXC_CONN_NAND_WE_B IMX8QXP_ENET0_RGMII_RXC 2 +#define IMX8QXP_ENET0_RGMII_RXC_CONN_USDHC1_CLK IMX8QXP_ENET0_RGMII_RXC 3 +#define IMX8QXP_ENET0_RGMII_RXC_LSIO_GPIO5_IO03 IMX8QXP_ENET0_RGMII_RXC 4 +#define IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL IMX8QXP_ENET0_RGMII_RX_CTL 0 +#define IMX8QXP_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD IMX8QXP_ENET0_RGMII_RX_CTL 3 +#define IMX8QXP_ENET0_RGMII_RX_CTL_LSIO_GPIO5_IO04 IMX8QXP_ENET0_RGMII_RX_CTL 4 +#define IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 IMX8QXP_ENET0_RGMII_RXD0 0 +#define IMX8QXP_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 IMX8QXP_ENET0_RGMII_RXD0 3 +#define IMX8QXP_ENET0_RGMII_RXD0_LSIO_GPIO5_IO05 IMX8QXP_ENET0_RGMII_RXD0 4 +#define IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 IMX8QXP_ENET0_RGMII_RXD1 0 +#define IMX8QXP_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 IMX8QXP_ENET0_RGMII_RXD1 3 +#define IMX8QXP_ENET0_RGMII_RXD1_LSIO_GPIO5_IO06 IMX8QXP_ENET0_RGMII_RXD1 4 +#define IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 IMX8QXP_ENET0_RGMII_RXD2 0 +#define IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER IMX8QXP_ENET0_RGMII_RXD2 1 +#define IMX8QXP_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 IMX8QXP_ENET0_RGMII_RXD2 3 +#define IMX8QXP_ENET0_RGMII_RXD2_LSIO_GPIO5_IO07 IMX8QXP_ENET0_RGMII_RXD2 4 +#define IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 IMX8QXP_ENET0_RGMII_RXD3 0 +#define IMX8QXP_ENET0_RGMII_RXD3_CONN_NAND_ALE IMX8QXP_ENET0_RGMII_RXD3 2 +#define IMX8QXP_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 IMX8QXP_ENET0_RGMII_RXD3 3 +#define IMX8QXP_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08 IMX8QXP_ENET0_RGMII_RXD3 4 +#define IMX8QXP_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M IMX8QXP_ENET0_REFCLK_125M_25M 0 +#define IMX8QXP_ENET0_REFCLK_125M_25M_CONN_ENET0_PPS IMX8QXP_ENET0_REFCLK_125M_25M 1 +#define IMX8QXP_ENET0_REFCLK_125M_25M_CONN_ENET1_PPS IMX8QXP_ENET0_REFCLK_125M_25M 2 +#define IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 IMX8QXP_ENET0_REFCLK_125M_25M 4 +#define IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO IMX8QXP_ENET0_MDIO 0 +#define IMX8QXP_ENET0_MDIO_ADMA_I2C3_SDA IMX8QXP_ENET0_MDIO 1 +#define IMX8QXP_ENET0_MDIO_CONN_ENET1_MDIO IMX8QXP_ENET0_MDIO 2 +#define IMX8QXP_ENET0_MDIO_LSIO_GPIO5_IO10 IMX8QXP_ENET0_MDIO 4 +#define IMX8QXP_ENET0_MDC_CONN_ENET0_MDC IMX8QXP_ENET0_MDC 0 +#define IMX8QXP_ENET0_MDC_ADMA_I2C3_SCL IMX8QXP_ENET0_MDC 1 +#define IMX8QXP_ENET0_MDC_CONN_ENET1_MDC IMX8QXP_ENET0_MDC 2 +#define IMX8QXP_ENET0_MDC_LSIO_GPIO5_IO11 IMX8QXP_ENET0_MDC 4 +#define IMX8QXP_ESAI0_FSR_ADMA_ESAI0_FSR IMX8QXP_ESAI0_FSR 0 +#define IMX8QXP_ESAI0_FSR_CONN_ENET1_RCLK50M_OUT IMX8QXP_ESAI0_FSR 1 +#define IMX8QXP_ESAI0_FSR_ADMA_LCDIF_D00 IMX8QXP_ESAI0_FSR 2 +#define IMX8QXP_ESAI0_FSR_CONN_ENET1_RGMII_TXC IMX8QXP_ESAI0_FSR 3 +#define IMX8QXP_ESAI0_FSR_CONN_ENET1_RCLK50M_IN IMX8QXP_ESAI0_FSR 4 +#define IMX8QXP_ESAI0_FST_ADMA_ESAI0_FST IMX8QXP_ESAI0_FST 0 +#define IMX8QXP_ESAI0_FST_CONN_MLB_CLK IMX8QXP_ESAI0_FST 1 +#define IMX8QXP_ESAI0_FST_ADMA_LCDIF_D01 IMX8QXP_ESAI0_FST 2 +#define IMX8QXP_ESAI0_FST_CONN_ENET1_RGMII_TXD2 IMX8QXP_ESAI0_FST 3 +#define IMX8QXP_ESAI0_FST_LSIO_GPIO0_IO01 IMX8QXP_ESAI0_FST 4 +#define IMX8QXP_ESAI0_SCKR_ADMA_ESAI0_SCKR IMX8QXP_ESAI0_SCKR 0 +#define IMX8QXP_ESAI0_SCKR_ADMA_LCDIF_D02 IMX8QXP_ESAI0_SCKR 2 +#define IMX8QXP_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL IMX8QXP_ESAI0_SCKR 3 +#define IMX8QXP_ESAI0_SCKR_LSIO_GPIO0_IO02 IMX8QXP_ESAI0_SCKR 4 +#define IMX8QXP_ESAI0_SCKT_ADMA_ESAI0_SCKT IMX8QXP_ESAI0_SCKT 0 +#define IMX8QXP_ESAI0_SCKT_CONN_MLB_SIG IMX8QXP_ESAI0_SCKT 1 +#define IMX8QXP_ESAI0_SCKT_ADMA_LCDIF_D03 IMX8QXP_ESAI0_SCKT 2 +#define IMX8QXP_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 IMX8QXP_ESAI0_SCKT 3 +#define IMX8QXP_ESAI0_SCKT_LSIO_GPIO0_IO03 IMX8QXP_ESAI0_SCKT 4 +#define IMX8QXP_ESAI0_TX0_ADMA_ESAI0_TX0 IMX8QXP_ESAI0_TX0 0 +#define IMX8QXP_ESAI0_TX0_CONN_MLB_DATA IMX8QXP_ESAI0_TX0 1 +#define IMX8QXP_ESAI0_TX0_ADMA_LCDIF_D04 IMX8QXP_ESAI0_TX0 2 +#define IMX8QXP_ESAI0_TX0_CONN_ENET1_RGMII_RXC IMX8QXP_ESAI0_TX0 3 +#define IMX8QXP_ESAI0_TX0_LSIO_GPIO0_IO04 IMX8QXP_ESAI0_TX0 4 +#define IMX8QXP_ESAI0_TX1_ADMA_ESAI0_TX1 IMX8QXP_ESAI0_TX1 0 +#define IMX8QXP_ESAI0_TX1_ADMA_LCDIF_D05 IMX8QXP_ESAI0_TX1 2 +#define IMX8QXP_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 IMX8QXP_ESAI0_TX1 3 +#define IMX8QXP_ESAI0_TX1_LSIO_GPIO0_IO05 IMX8QXP_ESAI0_TX1 4 +#define IMX8QXP_ESAI0_TX2_RX3_ADMA_ESAI0_TX2_RX3 IMX8QXP_ESAI0_TX2_RX3 0 +#define IMX8QXP_ESAI0_TX2_RX3_CONN_ENET1_RMII_RX_ER IMX8QXP_ESAI0_TX2_RX3 1 +#define IMX8QXP_ESAI0_TX2_RX3_ADMA_LCDIF_D06 IMX8QXP_ESAI0_TX2_RX3 2 +#define IMX8QXP_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 IMX8QXP_ESAI0_TX2_RX3 3 +#define IMX8QXP_ESAI0_TX2_RX3_LSIO_GPIO0_IO06 IMX8QXP_ESAI0_TX2_RX3 4 +#define IMX8QXP_ESAI0_TX3_RX2_ADMA_ESAI0_TX3_RX2 IMX8QXP_ESAI0_TX3_RX2 0 +#define IMX8QXP_ESAI0_TX3_RX2_ADMA_LCDIF_D07 IMX8QXP_ESAI0_TX3_RX2 2 +#define IMX8QXP_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 IMX8QXP_ESAI0_TX3_RX2 3 +#define IMX8QXP_ESAI0_TX3_RX2_LSIO_GPIO0_IO07 IMX8QXP_ESAI0_TX3_RX2 4 +#define IMX8QXP_ESAI0_TX4_RX1_ADMA_ESAI0_TX4_RX1 IMX8QXP_ESAI0_TX4_RX1 0 +#define IMX8QXP_ESAI0_TX4_RX1_ADMA_LCDIF_D08 IMX8QXP_ESAI0_TX4_RX1 2 +#define IMX8QXP_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 IMX8QXP_ESAI0_TX4_RX1 3 +#define IMX8QXP_ESAI0_TX4_RX1_LSIO_GPIO0_IO08 IMX8QXP_ESAI0_TX4_RX1 4 +#define IMX8QXP_ESAI0_TX5_RX0_ADMA_ESAI0_TX5_RX0 IMX8QXP_ESAI0_TX5_RX0 0 +#define IMX8QXP_ESAI0_TX5_RX0_ADMA_LCDIF_D09 IMX8QXP_ESAI0_TX5_RX0 2 +#define IMX8QXP_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 IMX8QXP_ESAI0_TX5_RX0 3 +#define IMX8QXP_ESAI0_TX5_RX0_LSIO_GPIO0_IO09 IMX8QXP_ESAI0_TX5_RX0 4 +#define IMX8QXP_SPDIF0_RX_ADMA_SPDIF0_RX IMX8QXP_SPDIF0_RX 0 +#define IMX8QXP_SPDIF0_RX_ADMA_MQS_R IMX8QXP_SPDIF0_RX 1 +#define IMX8QXP_SPDIF0_RX_ADMA_LCDIF_D10 IMX8QXP_SPDIF0_RX 2 +#define IMX8QXP_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 IMX8QXP_SPDIF0_RX 3 +#define IMX8QXP_SPDIF0_RX_LSIO_GPIO0_IO10 IMX8QXP_SPDIF0_RX 4 +#define IMX8QXP_SPDIF0_TX_ADMA_SPDIF0_TX IMX8QXP_SPDIF0_TX 0 +#define IMX8QXP_SPDIF0_TX_ADMA_MQS_L IMX8QXP_SPDIF0_TX 1 +#define IMX8QXP_SPDIF0_TX_ADMA_LCDIF_D11 IMX8QXP_SPDIF0_TX 2 +#define IMX8QXP_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL IMX8QXP_SPDIF0_TX 3 +#define IMX8QXP_SPDIF0_TX_LSIO_GPIO0_IO11 IMX8QXP_SPDIF0_TX 4 +#define IMX8QXP_SPDIF0_EXT_CLK_ADMA_SPDIF0_EXT_CLK IMX8QXP_SPDIF0_EXT_CLK 0 +#define IMX8QXP_SPDIF0_EXT_CLK_ADMA_LCDIF_D12 IMX8QXP_SPDIF0_EXT_CLK 2 +#define IMX8QXP_SPDIF0_EXT_CLK_CONN_ENET1_REFCLK_125M_25M IMX8QXP_SPDIF0_EXT_CLK 3 +#define IMX8QXP_SPDIF0_EXT_CLK_LSIO_GPIO0_IO12 IMX8QXP_SPDIF0_EXT_CLK 4 +#define IMX8QXP_SPI3_SCK_ADMA_SPI3_SCK IMX8QXP_SPI3_SCK 0 +#define IMX8QXP_SPI3_SCK_ADMA_LCDIF_D13 IMX8QXP_SPI3_SCK 2 +#define IMX8QXP_SPI3_SCK_LSIO_GPIO0_IO13 IMX8QXP_SPI3_SCK 4 +#define IMX8QXP_SPI3_SDO_ADMA_SPI3_SDO IMX8QXP_SPI3_SDO 0 +#define IMX8QXP_SPI3_SDO_ADMA_LCDIF_D14 IMX8QXP_SPI3_SDO 2 +#define IMX8QXP_SPI3_SDO_LSIO_GPIO0_IO14 IMX8QXP_SPI3_SDO 4 +#define IMX8QXP_SPI3_SDI_ADMA_SPI3_SDI IMX8QXP_SPI3_SDI 0 +#define IMX8QXP_SPI3_SDI_ADMA_LCDIF_D15 IMX8QXP_SPI3_SDI 2 +#define IMX8QXP_SPI3_SDI_LSIO_GPIO0_IO15 IMX8QXP_SPI3_SDI 4 +#define IMX8QXP_SPI3_CS0_ADMA_SPI3_CS0 IMX8QXP_SPI3_CS0 0 +#define IMX8QXP_SPI3_CS0_ADMA_ACM_MCLK_OUT1 IMX8QXP_SPI3_CS0 1 +#define IMX8QXP_SPI3_CS0_ADMA_LCDIF_HSYNC IMX8QXP_SPI3_CS0 2 +#define IMX8QXP_SPI3_CS0_LSIO_GPIO0_IO16 IMX8QXP_SPI3_CS0 4 +#define IMX8QXP_SPI3_CS1_ADMA_SPI3_CS1 IMX8QXP_SPI3_CS1 0 +#define IMX8QXP_SPI3_CS1_ADMA_I2C3_SCL IMX8QXP_SPI3_CS1 1 +#define IMX8QXP_SPI3_CS1_ADMA_LCDIF_RESET IMX8QXP_SPI3_CS1 2 +#define IMX8QXP_SPI3_CS1_ADMA_SPI2_CS0 IMX8QXP_SPI3_CS1 3 +#define IMX8QXP_SPI3_CS1_ADMA_LCDIF_D16 IMX8QXP_SPI3_CS1 4 +#define IMX8QXP_MCLK_IN1_ADMA_ACM_MCLK_IN1 IMX8QXP_MCLK_IN1 0 +#define IMX8QXP_MCLK_IN1_ADMA_I2C3_SDA IMX8QXP_MCLK_IN1 1 +#define IMX8QXP_MCLK_IN1_ADMA_LCDIF_EN IMX8QXP_MCLK_IN1 2 +#define IMX8QXP_MCLK_IN1_ADMA_SPI2_SCK IMX8QXP_MCLK_IN1 3 +#define IMX8QXP_MCLK_IN1_ADMA_LCDIF_D17 IMX8QXP_MCLK_IN1 4 +#define IMX8QXP_MCLK_IN0_ADMA_ACM_MCLK_IN0 IMX8QXP_MCLK_IN0 0 +#define IMX8QXP_MCLK_IN0_ADMA_ESAI0_RX_HF_CLK IMX8QXP_MCLK_IN0 1 +#define IMX8QXP_MCLK_IN0_ADMA_LCDIF_VSYNC IMX8QXP_MCLK_IN0 2 +#define IMX8QXP_MCLK_IN0_ADMA_SPI2_SDI IMX8QXP_MCLK_IN0 3 +#define IMX8QXP_MCLK_IN0_LSIO_GPIO0_IO19 IMX8QXP_MCLK_IN0 4 +#define IMX8QXP_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 IMX8QXP_MCLK_OUT0 0 +#define IMX8QXP_MCLK_OUT0_ADMA_ESAI0_TX_HF_CLK IMX8QXP_MCLK_OUT0 1 +#define IMX8QXP_MCLK_OUT0_ADMA_LCDIF_CLK IMX8QXP_MCLK_OUT0 2 +#define IMX8QXP_MCLK_OUT0_ADMA_SPI2_SDO IMX8QXP_MCLK_OUT0 3 +#define IMX8QXP_MCLK_OUT0_LSIO_GPIO0_IO20 IMX8QXP_MCLK_OUT0 4 +#define IMX8QXP_UART1_TX_ADMA_UART1_TX IMX8QXP_UART1_TX 0 +#define IMX8QXP_UART1_TX_LSIO_PWM0_OUT IMX8QXP_UART1_TX 1 +#define IMX8QXP_UART1_TX_LSIO_GPT0_CAPTURE IMX8QXP_UART1_TX 2 +#define IMX8QXP_UART1_TX_LSIO_GPIO0_IO21 IMX8QXP_UART1_TX 4 +#define IMX8QXP_UART1_RX_ADMA_UART1_RX IMX8QXP_UART1_RX 0 +#define IMX8QXP_UART1_RX_LSIO_PWM1_OUT IMX8QXP_UART1_RX 1 +#define IMX8QXP_UART1_RX_LSIO_GPT0_COMPARE IMX8QXP_UART1_RX 2 +#define IMX8QXP_UART1_RX_LSIO_GPT1_CLK IMX8QXP_UART1_RX 3 +#define IMX8QXP_UART1_RX_LSIO_GPIO0_IO22 IMX8QXP_UART1_RX 4 +#define IMX8QXP_UART1_RTS_B_ADMA_UART1_RTS_B IMX8QXP_UART1_RTS_B 0 +#define IMX8QXP_UART1_RTS_B_LSIO_PWM2_OUT IMX8QXP_UART1_RTS_B 1 +#define IMX8QXP_UART1_RTS_B_ADMA_LCDIF_D16 IMX8QXP_UART1_RTS_B 2 +#define IMX8QXP_UART1_RTS_B_LSIO_GPT1_CAPTURE IMX8QXP_UART1_RTS_B 3 +#define IMX8QXP_UART1_RTS_B_LSIO_GPT0_CLK IMX8QXP_UART1_RTS_B 4 +#define IMX8QXP_UART1_CTS_B_ADMA_UART1_CTS_B IMX8QXP_UART1_CTS_B 0 +#define IMX8QXP_UART1_CTS_B_LSIO_PWM3_OUT IMX8QXP_UART1_CTS_B 1 +#define IMX8QXP_UART1_CTS_B_ADMA_LCDIF_D17 IMX8QXP_UART1_CTS_B 2 +#define IMX8QXP_UART1_CTS_B_LSIO_GPT1_COMPARE IMX8QXP_UART1_CTS_B 3 +#define IMX8QXP_UART1_CTS_B_LSIO_GPIO0_IO24 IMX8QXP_UART1_CTS_B 4 +#define IMX8QXP_SAI0_TXD_ADMA_SAI0_TXD IMX8QXP_SAI0_TXD 0 +#define IMX8QXP_SAI0_TXD_ADMA_SAI1_RXC IMX8QXP_SAI0_TXD 1 +#define IMX8QXP_SAI0_TXD_ADMA_SPI1_SDO IMX8QXP_SAI0_TXD 2 +#define IMX8QXP_SAI0_TXD_ADMA_LCDIF_D18 IMX8QXP_SAI0_TXD 3 +#define IMX8QXP_SAI0_TXD_LSIO_GPIO0_IO25 IMX8QXP_SAI0_TXD 4 +#define IMX8QXP_SAI0_TXC_ADMA_SAI0_TXC IMX8QXP_SAI0_TXC 0 +#define IMX8QXP_SAI0_TXC_ADMA_SAI1_TXD IMX8QXP_SAI0_TXC 1 +#define IMX8QXP_SAI0_TXC_ADMA_SPI1_SDI IMX8QXP_SAI0_TXC 2 +#define IMX8QXP_SAI0_TXC_ADMA_LCDIF_D19 IMX8QXP_SAI0_TXC 3 +#define IMX8QXP_SAI0_TXC_LSIO_GPIO0_IO26 IMX8QXP_SAI0_TXC 4 +#define IMX8QXP_SAI0_RXD_ADMA_SAI0_RXD IMX8QXP_SAI0_RXD 0 +#define IMX8QXP_SAI0_RXD_ADMA_SAI1_RXFS IMX8QXP_SAI0_RXD 1 +#define IMX8QXP_SAI0_RXD_ADMA_SPI1_CS0 IMX8QXP_SAI0_RXD 2 +#define IMX8QXP_SAI0_RXD_ADMA_LCDIF_D20 IMX8QXP_SAI0_RXD 3 +#define IMX8QXP_SAI0_RXD_LSIO_GPIO0_IO27 IMX8QXP_SAI0_RXD 4 +#define IMX8QXP_SAI0_TXFS_ADMA_SAI0_TXFS IMX8QXP_SAI0_TXFS 0 +#define IMX8QXP_SAI0_TXFS_ADMA_SPI2_CS1 IMX8QXP_SAI0_TXFS 1 +#define IMX8QXP_SAI0_TXFS_ADMA_SPI1_SCK IMX8QXP_SAI0_TXFS 2 +#define IMX8QXP_SAI0_TXFS_LSIO_GPIO0_IO28 IMX8QXP_SAI0_TXFS 4 +#define IMX8QXP_SAI1_RXD_ADMA_SAI1_RXD IMX8QXP_SAI1_RXD 0 +#define IMX8QXP_SAI1_RXD_ADMA_SAI0_RXFS IMX8QXP_SAI1_RXD 1 +#define IMX8QXP_SAI1_RXD_ADMA_SPI1_CS1 IMX8QXP_SAI1_RXD 2 +#define IMX8QXP_SAI1_RXD_ADMA_LCDIF_D21 IMX8QXP_SAI1_RXD 3 +#define IMX8QXP_SAI1_RXD_LSIO_GPIO0_IO29 IMX8QXP_SAI1_RXD 4 +#define IMX8QXP_SAI1_RXC_ADMA_SAI1_RXC IMX8QXP_SAI1_RXC 0 +#define IMX8QXP_SAI1_RXC_ADMA_SAI1_TXC IMX8QXP_SAI1_RXC 1 +#define IMX8QXP_SAI1_RXC_ADMA_LCDIF_D22 IMX8QXP_SAI1_RXC 3 +#define IMX8QXP_SAI1_RXC_LSIO_GPIO0_IO30 IMX8QXP_SAI1_RXC 4 +#define IMX8QXP_SAI1_RXFS_ADMA_SAI1_RXFS IMX8QXP_SAI1_RXFS 0 +#define IMX8QXP_SAI1_RXFS_ADMA_SAI1_TXFS IMX8QXP_SAI1_RXFS 1 +#define IMX8QXP_SAI1_RXFS_ADMA_LCDIF_D23 IMX8QXP_SAI1_RXFS 3 +#define IMX8QXP_SAI1_RXFS_LSIO_GPIO0_IO31 IMX8QXP_SAI1_RXFS 4 +#define IMX8QXP_SPI2_CS0_ADMA_SPI2_CS0 IMX8QXP_SPI2_CS0 0 +#define IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00 IMX8QXP_SPI2_CS0 4 +#define IMX8QXP_SPI2_SDO_ADMA_SPI2_SDO IMX8QXP_SPI2_SDO 0 +#define IMX8QXP_SPI2_SDO_LSIO_GPIO1_IO01 IMX8QXP_SPI2_SDO 4 +#define IMX8QXP_SPI2_SDI_ADMA_SPI2_SDI IMX8QXP_SPI2_SDI 0 +#define IMX8QXP_SPI2_SDI_LSIO_GPIO1_IO02 IMX8QXP_SPI2_SDI 4 +#define IMX8QXP_SPI2_SCK_ADMA_SPI2_SCK IMX8QXP_SPI2_SCK 0 +#define IMX8QXP_SPI2_SCK_LSIO_GPIO1_IO03 IMX8QXP_SPI2_SCK 4 +#define IMX8QXP_SPI0_SCK_ADMA_SPI0_SCK IMX8QXP_SPI0_SCK 0 +#define IMX8QXP_SPI0_SCK_ADMA_SAI0_TXC IMX8QXP_SPI0_SCK 1 +#define IMX8QXP_SPI0_SCK_M40_I2C0_SCL IMX8QXP_SPI0_SCK 2 +#define IMX8QXP_SPI0_SCK_M40_GPIO0_IO00 IMX8QXP_SPI0_SCK 3 +#define IMX8QXP_SPI0_SCK_LSIO_GPIO1_IO04 IMX8QXP_SPI0_SCK 4 +#define IMX8QXP_SPI0_SDI_ADMA_SPI0_SDI IMX8QXP_SPI0_SDI 0 +#define IMX8QXP_SPI0_SDI_ADMA_SAI0_TXD IMX8QXP_SPI0_SDI 1 +#define IMX8QXP_SPI0_SDI_M40_TPM0_CH0 IMX8QXP_SPI0_SDI 2 +#define IMX8QXP_SPI0_SDI_M40_GPIO0_IO02 IMX8QXP_SPI0_SDI 3 +#define IMX8QXP_SPI0_SDI_LSIO_GPIO1_IO05 IMX8QXP_SPI0_SDI 4 +#define IMX8QXP_SPI0_SDO_ADMA_SPI0_SDO IMX8QXP_SPI0_SDO 0 +#define IMX8QXP_SPI0_SDO_ADMA_SAI0_TXFS IMX8QXP_SPI0_SDO 1 +#define IMX8QXP_SPI0_SDO_M40_I2C0_SDA IMX8QXP_SPI0_SDO 2 +#define IMX8QXP_SPI0_SDO_M40_GPIO0_IO01 IMX8QXP_SPI0_SDO 3 +#define IMX8QXP_SPI0_SDO_LSIO_GPIO1_IO06 IMX8QXP_SPI0_SDO 4 +#define IMX8QXP_SPI0_CS1_ADMA_SPI0_CS1 IMX8QXP_SPI0_CS1 0 +#define IMX8QXP_SPI0_CS1_ADMA_SAI0_RXC IMX8QXP_SPI0_CS1 1 +#define IMX8QXP_SPI0_CS1_ADMA_SAI1_TXD IMX8QXP_SPI0_CS1 2 +#define IMX8QXP_SPI0_CS1_ADMA_LCD_PWM0_OUT IMX8QXP_SPI0_CS1 3 +#define IMX8QXP_SPI0_CS1_LSIO_GPIO1_IO07 IMX8QXP_SPI0_CS1 4 +#define IMX8QXP_SPI0_CS0_ADMA_SPI0_CS0 IMX8QXP_SPI0_CS0 0 +#define IMX8QXP_SPI0_CS0_ADMA_SAI0_RXD IMX8QXP_SPI0_CS0 1 +#define IMX8QXP_SPI0_CS0_M40_TPM0_CH1 IMX8QXP_SPI0_CS0 2 +#define IMX8QXP_SPI0_CS0_M40_GPIO0_IO03 IMX8QXP_SPI0_CS0 3 +#define IMX8QXP_SPI0_CS0_LSIO_GPIO1_IO08 IMX8QXP_SPI0_CS0 4 +#define IMX8QXP_ADC_IN1_ADMA_ADC_IN1 IMX8QXP_ADC_IN1 0 +#define IMX8QXP_ADC_IN1_M40_I2C0_SDA IMX8QXP_ADC_IN1 1 +#define IMX8QXP_ADC_IN1_M40_GPIO0_IO01 IMX8QXP_ADC_IN1 2 +#define IMX8QXP_ADC_IN1_LSIO_GPIO1_IO09 IMX8QXP_ADC_IN1 4 +#define IMX8QXP_ADC_IN0_ADMA_ADC_IN0 IMX8QXP_ADC_IN0 0 +#define IMX8QXP_ADC_IN0_M40_I2C0_SCL IMX8QXP_ADC_IN0 1 +#define IMX8QXP_ADC_IN0_M40_GPIO0_IO00 IMX8QXP_ADC_IN0 2 +#define IMX8QXP_ADC_IN0_LSIO_GPIO1_IO10 IMX8QXP_ADC_IN0 4 +#define IMX8QXP_ADC_IN3_ADMA_ADC_IN3 IMX8QXP_ADC_IN3 0 +#define IMX8QXP_ADC_IN3_M40_UART0_TX IMX8QXP_ADC_IN3 1 +#define IMX8QXP_ADC_IN3_M40_GPIO0_IO03 IMX8QXP_ADC_IN3 2 +#define IMX8QXP_ADC_IN3_ADMA_ACM_MCLK_OUT0 IMX8QXP_ADC_IN3 3 +#define IMX8QXP_ADC_IN3_LSIO_GPIO1_IO11 IMX8QXP_ADC_IN3 4 +#define IMX8QXP_ADC_IN2_ADMA_ADC_IN2 IMX8QXP_ADC_IN2 0 +#define IMX8QXP_ADC_IN2_M40_UART0_RX IMX8QXP_ADC_IN2 1 +#define IMX8QXP_ADC_IN2_M40_GPIO0_IO02 IMX8QXP_ADC_IN2 2 +#define IMX8QXP_ADC_IN2_ADMA_ACM_MCLK_IN0 IMX8QXP_ADC_IN2 3 +#define IMX8QXP_ADC_IN2_LSIO_GPIO1_IO12 IMX8QXP_ADC_IN2 4 +#define IMX8QXP_ADC_IN5_ADMA_ADC_IN5 IMX8QXP_ADC_IN5 0 +#define IMX8QXP_ADC_IN5_M40_TPM0_CH1 IMX8QXP_ADC_IN5 1 +#define IMX8QXP_ADC_IN5_M40_GPIO0_IO05 IMX8QXP_ADC_IN5 2 +#define IMX8QXP_ADC_IN5_LSIO_GPIO1_IO13 IMX8QXP_ADC_IN5 4 +#define IMX8QXP_ADC_IN4_ADMA_ADC_IN4 IMX8QXP_ADC_IN4 0 +#define IMX8QXP_ADC_IN4_M40_TPM0_CH0 IMX8QXP_ADC_IN4 1 +#define IMX8QXP_ADC_IN4_M40_GPIO0_IO04 IMX8QXP_ADC_IN4 2 +#define IMX8QXP_ADC_IN4_LSIO_GPIO1_IO14 IMX8QXP_ADC_IN4 4 +#define IMX8QXP_FLEXCAN0_RX_ADMA_FLEXCAN0_RX IMX8QXP_FLEXCAN0_RX 0 +#define IMX8QXP_FLEXCAN0_RX_ADMA_SAI2_RXC IMX8QXP_FLEXCAN0_RX 1 +#define IMX8QXP_FLEXCAN0_RX_ADMA_UART0_RTS_B IMX8QXP_FLEXCAN0_RX 2 +#define IMX8QXP_FLEXCAN0_RX_ADMA_SAI1_TXC IMX8QXP_FLEXCAN0_RX 3 +#define IMX8QXP_FLEXCAN0_RX_LSIO_GPIO1_IO15 IMX8QXP_FLEXCAN0_RX 4 +#define IMX8QXP_FLEXCAN0_TX_ADMA_FLEXCAN0_TX IMX8QXP_FLEXCAN0_TX 0 +#define IMX8QXP_FLEXCAN0_TX_ADMA_SAI2_RXD IMX8QXP_FLEXCAN0_TX 1 +#define IMX8QXP_FLEXCAN0_TX_ADMA_UART0_CTS_B IMX8QXP_FLEXCAN0_TX 2 +#define IMX8QXP_FLEXCAN0_TX_ADMA_SAI1_TXFS IMX8QXP_FLEXCAN0_TX 3 +#define IMX8QXP_FLEXCAN0_TX_LSIO_GPIO1_IO16 IMX8QXP_FLEXCAN0_TX 4 +#define IMX8QXP_FLEXCAN1_RX_ADMA_FLEXCAN1_RX IMX8QXP_FLEXCAN1_RX 0 +#define IMX8QXP_FLEXCAN1_RX_ADMA_SAI2_RXFS IMX8QXP_FLEXCAN1_RX 1 +#define IMX8QXP_FLEXCAN1_RX_ADMA_FTM_CH2 IMX8QXP_FLEXCAN1_RX 2 +#define IMX8QXP_FLEXCAN1_RX_ADMA_SAI1_TXD IMX8QXP_FLEXCAN1_RX 3 +#define IMX8QXP_FLEXCAN1_RX_LSIO_GPIO1_IO17 IMX8QXP_FLEXCAN1_RX 4 +#define IMX8QXP_FLEXCAN1_TX_ADMA_FLEXCAN1_TX IMX8QXP_FLEXCAN1_TX 0 +#define IMX8QXP_FLEXCAN1_TX_ADMA_SAI3_RXC IMX8QXP_FLEXCAN1_TX 1 +#define IMX8QXP_FLEXCAN1_TX_ADMA_DMA0_REQ_IN0 IMX8QXP_FLEXCAN1_TX 2 +#define IMX8QXP_FLEXCAN1_TX_ADMA_SAI1_RXD IMX8QXP_FLEXCAN1_TX 3 +#define IMX8QXP_FLEXCAN1_TX_LSIO_GPIO1_IO18 IMX8QXP_FLEXCAN1_TX 4 +#define IMX8QXP_FLEXCAN2_RX_ADMA_FLEXCAN2_RX IMX8QXP_FLEXCAN2_RX 0 +#define IMX8QXP_FLEXCAN2_RX_ADMA_SAI3_RXD IMX8QXP_FLEXCAN2_RX 1 +#define IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX IMX8QXP_FLEXCAN2_RX 2 +#define IMX8QXP_FLEXCAN2_RX_ADMA_SAI1_RXFS IMX8QXP_FLEXCAN2_RX 3 +#define IMX8QXP_FLEXCAN2_RX_LSIO_GPIO1_IO19 IMX8QXP_FLEXCAN2_RX 4 +#define IMX8QXP_FLEXCAN2_TX_ADMA_FLEXCAN2_TX IMX8QXP_FLEXCAN2_TX 0 +#define IMX8QXP_FLEXCAN2_TX_ADMA_SAI3_RXFS IMX8QXP_FLEXCAN2_TX 1 +#define IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX IMX8QXP_FLEXCAN2_TX 2 +#define IMX8QXP_FLEXCAN2_TX_ADMA_SAI1_RXC IMX8QXP_FLEXCAN2_TX 3 +#define IMX8QXP_FLEXCAN2_TX_LSIO_GPIO1_IO20 IMX8QXP_FLEXCAN2_TX 4 +#define IMX8QXP_UART0_RX_ADMA_UART0_RX IMX8QXP_UART0_RX 0 +#define IMX8QXP_UART0_RX_ADMA_MQS_R IMX8QXP_UART0_RX 1 +#define IMX8QXP_UART0_RX_ADMA_FLEXCAN0_RX IMX8QXP_UART0_RX 2 +#define IMX8QXP_UART0_RX_LSIO_GPIO1_IO21 IMX8QXP_UART0_RX 4 +#define IMX8QXP_UART0_TX_ADMA_UART0_TX IMX8QXP_UART0_TX 0 +#define IMX8QXP_UART0_TX_ADMA_MQS_L IMX8QXP_UART0_TX 1 +#define IMX8QXP_UART0_TX_ADMA_FLEXCAN0_TX IMX8QXP_UART0_TX 2 +#define IMX8QXP_UART0_TX_LSIO_GPIO1_IO22 IMX8QXP_UART0_TX 4 +#define IMX8QXP_UART2_TX_ADMA_UART2_TX IMX8QXP_UART2_TX 0 +#define IMX8QXP_UART2_TX_ADMA_FTM_CH1 IMX8QXP_UART2_TX 1 +#define IMX8QXP_UART2_TX_ADMA_FLEXCAN1_TX IMX8QXP_UART2_TX 2 +#define IMX8QXP_UART2_TX_LSIO_GPIO1_IO23 IMX8QXP_UART2_TX 4 +#define IMX8QXP_UART2_RX_ADMA_UART2_RX IMX8QXP_UART2_RX 0 +#define IMX8QXP_UART2_RX_ADMA_FTM_CH0 IMX8QXP_UART2_RX 1 +#define IMX8QXP_UART2_RX_ADMA_FLEXCAN1_RX IMX8QXP_UART2_RX 2 +#define IMX8QXP_UART2_RX_LSIO_GPIO1_IO24 IMX8QXP_UART2_RX 4 +#define IMX8QXP_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL IMX8QXP_MIPI_DSI0_I2C0_SCL 0 +#define IMX8QXP_MIPI_DSI0_I2C0_SCL_MIPI_DSI1_GPIO0_IO02 IMX8QXP_MIPI_DSI0_I2C0_SCL 1 +#define IMX8QXP_MIPI_DSI0_I2C0_SCL_LSIO_GPIO1_IO25 IMX8QXP_MIPI_DSI0_I2C0_SCL 4 +#define IMX8QXP_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA IMX8QXP_MIPI_DSI0_I2C0_SDA 0 +#define IMX8QXP_MIPI_DSI0_I2C0_SDA_MIPI_DSI1_GPIO0_IO03 IMX8QXP_MIPI_DSI0_I2C0_SDA 1 +#define IMX8QXP_MIPI_DSI0_I2C0_SDA_LSIO_GPIO1_IO26 IMX8QXP_MIPI_DSI0_I2C0_SDA 4 +#define IMX8QXP_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_IO00 IMX8QXP_MIPI_DSI0_GPIO0_00 0 +#define IMX8QXP_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL IMX8QXP_MIPI_DSI0_GPIO0_00 1 +#define IMX8QXP_MIPI_DSI0_GPIO0_00_MIPI_DSI0_PWM0_OUT IMX8QXP_MIPI_DSI0_GPIO0_00 2 +#define IMX8QXP_MIPI_DSI0_GPIO0_00_LSIO_GPIO1_IO27 IMX8QXP_MIPI_DSI0_GPIO0_00 4 +#define IMX8QXP_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_IO01 IMX8QXP_MIPI_DSI0_GPIO0_01 0 +#define IMX8QXP_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA IMX8QXP_MIPI_DSI0_GPIO0_01 1 +#define IMX8QXP_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO28 IMX8QXP_MIPI_DSI0_GPIO0_01 4 +#define IMX8QXP_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL IMX8QXP_MIPI_DSI1_I2C0_SCL 0 +#define IMX8QXP_MIPI_DSI1_I2C0_SCL_MIPI_DSI0_GPIO0_IO02 IMX8QXP_MIPI_DSI1_I2C0_SCL 1 +#define IMX8QXP_MIPI_DSI1_I2C0_SCL_LSIO_GPIO1_IO29 IMX8QXP_MIPI_DSI1_I2C0_SCL 4 +#define IMX8QXP_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA IMX8QXP_MIPI_DSI1_I2C0_SDA 0 +#define IMX8QXP_MIPI_DSI1_I2C0_SDA_MIPI_DSI0_GPIO0_IO03 IMX8QXP_MIPI_DSI1_I2C0_SDA 1 +#define IMX8QXP_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO30 IMX8QXP_MIPI_DSI1_I2C0_SDA 4 +#define IMX8QXP_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_IO00 IMX8QXP_MIPI_DSI1_GPIO0_00 0 +#define IMX8QXP_MIPI_DSI1_GPIO0_00_ADMA_I2C2_SCL IMX8QXP_MIPI_DSI1_GPIO0_00 1 +#define IMX8QXP_MIPI_DSI1_GPIO0_00_MIPI_DSI1_PWM0_OUT IMX8QXP_MIPI_DSI1_GPIO0_00 2 +#define IMX8QXP_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO31 IMX8QXP_MIPI_DSI1_GPIO0_00 4 +#define IMX8QXP_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_IO01 IMX8QXP_MIPI_DSI1_GPIO0_01 0 +#define IMX8QXP_MIPI_DSI1_GPIO0_01_ADMA_I2C2_SDA IMX8QXP_MIPI_DSI1_GPIO0_01 1 +#define IMX8QXP_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 IMX8QXP_MIPI_DSI1_GPIO0_01 4 +#define IMX8QXP_JTAG_TRST_B_SCU_JTAG_TRST_B IMX8QXP_JTAG_TRST_B 0 +#define IMX8QXP_JTAG_TRST_B_SCU_WDOG0_WDOG_OUT IMX8QXP_JTAG_TRST_B 1 +#define IMX8QXP_PMIC_I2C_SCL_SCU_PMIC_I2C_SCL IMX8QXP_PMIC_I2C_SCL 0 +#define IMX8QXP_PMIC_I2C_SCL_SCU_GPIO0_IOXX_PMIC_A35_ON IMX8QXP_PMIC_I2C_SCL 1 +#define IMX8QXP_PMIC_I2C_SCL_LSIO_GPIO2_IO01 IMX8QXP_PMIC_I2C_SCL 4 +#define IMX8QXP_PMIC_I2C_SDA_SCU_PMIC_I2C_SDA IMX8QXP_PMIC_I2C_SDA 0 +#define IMX8QXP_PMIC_I2C_SDA_SCU_GPIO0_IOXX_PMIC_GPU_ON IMX8QXP_PMIC_I2C_SDA 1 +#define IMX8QXP_PMIC_I2C_SDA_LSIO_GPIO2_IO02 IMX8QXP_PMIC_I2C_SDA 4 +#define IMX8QXP_PMIC_INT_B_SCU_DIMX8QXPMIC_INT_B IMX8QXP_PMIC_INT_B 0 +#define IMX8QXP_SCU_GPIO0_00_SCU_GPIO0_IO00 IMX8QXP_SCU_GPIO0_00 0 +#define IMX8QXP_SCU_GPIO0_00_SCU_UART0_RX IMX8QXP_SCU_GPIO0_00 1 +#define IMX8QXP_SCU_GPIO0_00_M40_UART0_RX IMX8QXP_SCU_GPIO0_00 2 +#define IMX8QXP_SCU_GPIO0_00_ADMA_UART3_RX IMX8QXP_SCU_GPIO0_00 3 +#define IMX8QXP_SCU_GPIO0_00_LSIO_GPIO2_IO03 IMX8QXP_SCU_GPIO0_00 4 +#define IMX8QXP_SCU_GPIO0_01_SCU_GPIO0_IO01 IMX8QXP_SCU_GPIO0_01 0 +#define IMX8QXP_SCU_GPIO0_01_SCU_UART0_TX IMX8QXP_SCU_GPIO0_01 1 +#define IMX8QXP_SCU_GPIO0_01_M40_UART0_TX IMX8QXP_SCU_GPIO0_01 2 +#define IMX8QXP_SCU_GPIO0_01_ADMA_UART3_TX IMX8QXP_SCU_GPIO0_01 3 +#define IMX8QXP_SCU_GPIO0_01_SCU_WDOG0_WDOG_OUT IMX8QXP_SCU_GPIO0_01 4 +#define IMX8QXP_SCU_PMIC_STANDBY_SCU_DIMX8QXPMIC_STANDBY IMX8QXP_SCU_PMIC_STANDBY 0 +#define IMX8QXP_SCU_BOOT_MODE0_SCU_DSC_BOOT_MODE0 IMX8QXP_SCU_BOOT_MODE0 0 +#define IMX8QXP_SCU_BOOT_MODE1_SCU_DSC_BOOT_MODE1 IMX8QXP_SCU_BOOT_MODE1 0 +#define IMX8QXP_SCU_BOOT_MODE2_SCU_DSC_BOOT_MODE2 IMX8QXP_SCU_BOOT_MODE2 0 +#define IMX8QXP_SCU_BOOT_MODE2_SCU_PMIC_I2C_SDA IMX8QXP_SCU_BOOT_MODE2 1 +#define IMX8QXP_SCU_BOOT_MODE3_SCU_DSC_BOOT_MODE3 IMX8QXP_SCU_BOOT_MODE3 0 +#define IMX8QXP_SCU_BOOT_MODE3_SCU_PMIC_I2C_SCL IMX8QXP_SCU_BOOT_MODE3 1 +#define IMX8QXP_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K IMX8QXP_SCU_BOOT_MODE3 3 +#define IMX8QXP_CSI_D00_CI_PI_D02 IMX8QXP_CSI_D00 0 +#define IMX8QXP_CSI_D00_ADMA_SAI0_RXC IMX8QXP_CSI_D00 2 +#define IMX8QXP_CSI_D01_CI_PI_D03 IMX8QXP_CSI_D01 0 +#define IMX8QXP_CSI_D01_ADMA_SAI0_RXD IMX8QXP_CSI_D01 2 +#define IMX8QXP_CSI_D02_CI_PI_D04 IMX8QXP_CSI_D02 0 +#define IMX8QXP_CSI_D02_ADMA_SAI0_RXFS IMX8QXP_CSI_D02 2 +#define IMX8QXP_CSI_D03_CI_PI_D05 IMX8QXP_CSI_D03 0 +#define IMX8QXP_CSI_D03_ADMA_SAI2_RXC IMX8QXP_CSI_D03 2 +#define IMX8QXP_CSI_D04_CI_PI_D06 IMX8QXP_CSI_D04 0 +#define IMX8QXP_CSI_D04_ADMA_SAI2_RXD IMX8QXP_CSI_D04 2 +#define IMX8QXP_CSI_D05_CI_PI_D07 IMX8QXP_CSI_D05 0 +#define IMX8QXP_CSI_D05_ADMA_SAI2_RXFS IMX8QXP_CSI_D05 2 +#define IMX8QXP_CSI_D06_CI_PI_D08 IMX8QXP_CSI_D06 0 +#define IMX8QXP_CSI_D06_ADMA_SAI3_RXC IMX8QXP_CSI_D06 2 +#define IMX8QXP_CSI_D07_CI_PI_D09 IMX8QXP_CSI_D07 0 +#define IMX8QXP_CSI_D07_ADMA_SAI3_RXD IMX8QXP_CSI_D07 2 +#define IMX8QXP_CSI_HSYNC_CI_PI_HSYNC IMX8QXP_CSI_HSYNC 0 +#define IMX8QXP_CSI_HSYNC_CI_PI_D00 IMX8QXP_CSI_HSYNC 1 +#define IMX8QXP_CSI_HSYNC_ADMA_SAI3_RXFS IMX8QXP_CSI_HSYNC 2 +#define IMX8QXP_CSI_VSYNC_CI_PI_VSYNC IMX8QXP_CSI_VSYNC 0 +#define IMX8QXP_CSI_VSYNC_CI_PI_D01 IMX8QXP_CSI_VSYNC 1 +#define IMX8QXP_CSI_PCLK_CI_PI_PCLK IMX8QXP_CSI_PCLK 0 +#define IMX8QXP_CSI_PCLK_MIPI_CSI0_I2C0_SCL IMX8QXP_CSI_PCLK 1 +#define IMX8QXP_CSI_PCLK_ADMA_SPI1_SCK IMX8QXP_CSI_PCLK 3 +#define IMX8QXP_CSI_PCLK_LSIO_GPIO3_IO00 IMX8QXP_CSI_PCLK 4 +#define IMX8QXP_CSI_MCLK_CI_PI_MCLK IMX8QXP_CSI_MCLK 0 +#define IMX8QXP_CSI_MCLK_MIPI_CSI0_I2C0_SDA IMX8QXP_CSI_MCLK 1 +#define IMX8QXP_CSI_MCLK_ADMA_SPI1_SDO IMX8QXP_CSI_MCLK 3 +#define IMX8QXP_CSI_MCLK_LSIO_GPIO3_IO01 IMX8QXP_CSI_MCLK 4 +#define IMX8QXP_CSI_EN_CI_PI_EN IMX8QXP_CSI_EN 0 +#define IMX8QXP_CSI_EN_CI_PI_I2C_SCL IMX8QXP_CSI_EN 1 +#define IMX8QXP_CSI_EN_ADMA_I2C3_SCL IMX8QXP_CSI_EN 2 +#define IMX8QXP_CSI_EN_ADMA_SPI1_SDI IMX8QXP_CSI_EN 3 +#define IMX8QXP_CSI_EN_LSIO_GPIO3_IO02 IMX8QXP_CSI_EN 4 +#define IMX8QXP_CSI_RESET_CI_PI_RESET IMX8QXP_CSI_RESET 0 +#define IMX8QXP_CSI_RESET_CI_PI_I2C_SDA IMX8QXP_CSI_RESET 1 +#define IMX8QXP_CSI_RESET_ADMA_I2C3_SDA IMX8QXP_CSI_RESET 2 +#define IMX8QXP_CSI_RESET_ADMA_SPI1_CS0 IMX8QXP_CSI_RESET 3 +#define IMX8QXP_CSI_RESET_LSIO_GPIO3_IO03 IMX8QXP_CSI_RESET 4 +#define IMX8QXP_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT IMX8QXP_MIPI_CSI0_MCLK_OUT 0 +#define IMX8QXP_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04 IMX8QXP_MIPI_CSI0_MCLK_OUT 4 +#define IMX8QXP_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL IMX8QXP_MIPI_CSI0_I2C0_SCL 0 +#define IMX8QXP_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_GPIO0_IO02 IMX8QXP_MIPI_CSI0_I2C0_SCL 1 +#define IMX8QXP_MIPI_CSI0_I2C0_SCL_LSIO_GPIO3_IO05 IMX8QXP_MIPI_CSI0_I2C0_SCL 4 +#define IMX8QXP_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA IMX8QXP_MIPI_CSI0_I2C0_SDA 0 +#define IMX8QXP_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_GPIO0_IO03 IMX8QXP_MIPI_CSI0_I2C0_SDA 1 +#define IMX8QXP_MIPI_CSI0_I2C0_SDA_LSIO_GPIO3_IO06 IMX8QXP_MIPI_CSI0_I2C0_SDA 4 +#define IMX8QXP_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_IO01 IMX8QXP_MIPI_CSI0_GPIO0_01 0 +#define IMX8QXP_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA IMX8QXP_MIPI_CSI0_GPIO0_01 1 +#define IMX8QXP_MIPI_CSI0_GPIO0_01_LSIO_GPIO3_IO07 IMX8QXP_MIPI_CSI0_GPIO0_01 4 +#define IMX8QXP_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_IO00 IMX8QXP_MIPI_CSI0_GPIO0_00 0 +#define IMX8QXP_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL IMX8QXP_MIPI_CSI0_GPIO0_00 1 +#define IMX8QXP_MIPI_CSI0_GPIO0_00_LSIO_GPIO3_IO08 IMX8QXP_MIPI_CSI0_GPIO0_00 4 +#define IMX8QXP_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 IMX8QXP_QSPI0A_DATA0 0 +#define IMX8QXP_QSPI0A_DATA0_LSIO_GPIO3_IO09 IMX8QXP_QSPI0A_DATA0 4 +#define IMX8QXP_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 IMX8QXP_QSPI0A_DATA1 0 +#define IMX8QXP_QSPI0A_DATA1_LSIO_GPIO3_IO10 IMX8QXP_QSPI0A_DATA1 4 +#define IMX8QXP_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 IMX8QXP_QSPI0A_DATA2 0 +#define IMX8QXP_QSPI0A_DATA2_LSIO_GPIO3_IO11 IMX8QXP_QSPI0A_DATA2 4 +#define IMX8QXP_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 IMX8QXP_QSPI0A_DATA3 0 +#define IMX8QXP_QSPI0A_DATA3_LSIO_GPIO3_IO12 IMX8QXP_QSPI0A_DATA3 4 +#define IMX8QXP_QSPI0A_DQS_LSIO_QSPI0A_DQS IMX8QXP_QSPI0A_DQS 0 +#define IMX8QXP_QSPI0A_DQS_LSIO_GPIO3_IO13 IMX8QXP_QSPI0A_DQS 4 +#define IMX8QXP_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B IMX8QXP_QSPI0A_SS0_B 0 +#define IMX8QXP_QSPI0A_SS0_B_LSIO_GPIO3_IO14 IMX8QXP_QSPI0A_SS0_B 4 +#define IMX8QXP_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B IMX8QXP_QSPI0A_SS1_B 0 +#define IMX8QXP_QSPI0A_SS1_B_LSIO_GPIO3_IO15 IMX8QXP_QSPI0A_SS1_B 4 +#define IMX8QXP_QSPI0A_SCLK_LSIO_QSPI0A_SCLK IMX8QXP_QSPI0A_SCLK 0 +#define IMX8QXP_QSPI0A_SCLK_LSIO_GPIO3_IO16 IMX8QXP_QSPI0A_SCLK 4 +#define IMX8QXP_QSPI0B_SCLK_LSIO_QSPI0B_SCLK IMX8QXP_QSPI0B_SCLK 0 +#define IMX8QXP_QSPI0B_SCLK_LSIO_QSPI1A_SCLK IMX8QXP_QSPI0B_SCLK 1 +#define IMX8QXP_QSPI0B_SCLK_LSIO_KPP0_COL0 IMX8QXP_QSPI0B_SCLK 2 +#define IMX8QXP_QSPI0B_SCLK_LSIO_GPIO3_IO17 IMX8QXP_QSPI0B_SCLK 4 +#define IMX8QXP_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 IMX8QXP_QSPI0B_DATA0 0 +#define IMX8QXP_QSPI0B_DATA0_LSIO_QSPI1A_DATA0 IMX8QXP_QSPI0B_DATA0 1 +#define IMX8QXP_QSPI0B_DATA0_LSIO_KPP0_COL1 IMX8QXP_QSPI0B_DATA0 2 +#define IMX8QXP_QSPI0B_DATA0_LSIO_GPIO3_IO18 IMX8QXP_QSPI0B_DATA0 4 +#define IMX8QXP_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 IMX8QXP_QSPI0B_DATA1 0 +#define IMX8QXP_QSPI0B_DATA1_LSIO_QSPI1A_DATA1 IMX8QXP_QSPI0B_DATA1 1 +#define IMX8QXP_QSPI0B_DATA1_LSIO_KPP0_COL2 IMX8QXP_QSPI0B_DATA1 2 +#define IMX8QXP_QSPI0B_DATA1_LSIO_GPIO3_IO19 IMX8QXP_QSPI0B_DATA1 4 +#define IMX8QXP_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 IMX8QXP_QSPI0B_DATA2 0 +#define IMX8QXP_QSPI0B_DATA2_LSIO_QSPI1A_DATA2 IMX8QXP_QSPI0B_DATA2 1 +#define IMX8QXP_QSPI0B_DATA2_LSIO_KPP0_COL3 IMX8QXP_QSPI0B_DATA2 2 +#define IMX8QXP_QSPI0B_DATA2_LSIO_GPIO3_IO20 IMX8QXP_QSPI0B_DATA2 4 +#define IMX8QXP_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 IMX8QXP_QSPI0B_DATA3 0 +#define IMX8QXP_QSPI0B_DATA3_LSIO_QSPI1A_DATA3 IMX8QXP_QSPI0B_DATA3 1 +#define IMX8QXP_QSPI0B_DATA3_LSIO_KPP0_ROW0 IMX8QXP_QSPI0B_DATA3 2 +#define IMX8QXP_QSPI0B_DATA3_LSIO_GPIO3_IO21 IMX8QXP_QSPI0B_DATA3 4 +#define IMX8QXP_QSPI0B_DQS_LSIO_QSPI0B_DQS IMX8QXP_QSPI0B_DQS 0 +#define IMX8QXP_QSPI0B_DQS_LSIO_QSPI1A_DQS IMX8QXP_QSPI0B_DQS 1 +#define IMX8QXP_QSPI0B_DQS_LSIO_KPP0_ROW1 IMX8QXP_QSPI0B_DQS 2 +#define IMX8QXP_QSPI0B_DQS_LSIO_GPIO3_IO22 IMX8QXP_QSPI0B_DQS 4 +#define IMX8QXP_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B IMX8QXP_QSPI0B_SS0_B 0 +#define IMX8QXP_QSPI0B_SS0_B_LSIO_QSPI1A_SS0_B IMX8QXP_QSPI0B_SS0_B 1 +#define IMX8QXP_QSPI0B_SS0_B_LSIO_KPP0_ROW2 IMX8QXP_QSPI0B_SS0_B 2 +#define IMX8QXP_QSPI0B_SS0_B_LSIO_GPIO3_IO23 IMX8QXP_QSPI0B_SS0_B 4 +#define IMX8QXP_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B IMX8QXP_QSPI0B_SS1_B 0 +#define IMX8QXP_QSPI0B_SS1_B_LSIO_QSPI1A_SS1_B IMX8QXP_QSPI0B_SS1_B 1 +#define IMX8QXP_QSPI0B_SS1_B_LSIO_KPP0_ROW3 IMX8QXP_QSPI0B_SS1_B 2 +#define IMX8QXP_QSPI0B_SS1_B_LSIO_GPIO3_IO24 IMX8QXP_QSPI0B_SS1_B 4 + +#endif /* _IMX8QXP_PADS_H */ diff --git a/include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h b/include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h new file mode 100644 index 000000000000..20f43404cac0 --- /dev/null +++ b/include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * pinctrl-tegra-io-pad.h: Tegra I/O pad source voltage configuration constants + * pinctrl bindings. + * + * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. + * + * Author: Aapo Vienamo <avienamo@nvidia.com> + */ + +#ifndef _DT_BINDINGS_PINCTRL_TEGRA_IO_PAD_H +#define _DT_BINDINGS_PINCTRL_TEGRA_IO_PAD_H + +/* Voltage levels of the I/O pad's source rail */ +#define TEGRA_IO_PAD_VOLTAGE_1V8 0 +#define TEGRA_IO_PAD_VOLTAGE_3V3 1 + +#endif diff --git a/include/dt-bindings/pinctrl/r7s9210-pinctrl.h b/include/dt-bindings/pinctrl/r7s9210-pinctrl.h new file mode 100644 index 000000000000..2d0c23e5d3a7 --- /dev/null +++ b/include/dt-bindings/pinctrl/r7s9210-pinctrl.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Defines macros and constants for Renesas RZ/A2 pin controller pin + * muxing functions. + */ +#ifndef __DT_BINDINGS_PINCTRL_RENESAS_RZA2_H +#define __DT_BINDINGS_PINCTRL_RENESAS_RZA2_H + +#define RZA2_PINS_PER_PORT 8 + +/* Port names as labeled in the Hardware Manual */ +#define PORT0 0 +#define PORT1 1 +#define PORT2 2 +#define PORT3 3 +#define PORT4 4 +#define PORT5 5 +#define PORT6 6 +#define PORT7 7 +#define PORT8 8 +#define PORT9 9 +#define PORTA 10 +#define PORTB 11 +#define PORTC 12 +#define PORTD 13 +#define PORTE 14 +#define PORTF 15 +#define PORTG 16 +#define PORTH 17 +/* No I */ +#define PORTJ 18 +#define PORTK 19 +#define PORTL 20 +#define PORTM 21 /* Pins PM_0/1 are labeled JP_0/1 in HW manual */ + +/* + * Create the pin index from its bank and position numbers and store in + * the upper 16 bits the alternate function identifier + */ +#define RZA2_PINMUX(b, p, f) ((b) * RZA2_PINS_PER_PORT + (p) | (f << 16)) + +/* + * Convert a port and pin label to its global pin index + */ + #define RZA2_PIN(port, pin) ((port) * RZA2_PINS_PER_PORT + (pin)) + +#endif /* __DT_BINDINGS_PINCTRL_RENESAS_RZA2_H */ diff --git a/include/dt-bindings/pinctrl/rzn1-pinctrl.h b/include/dt-bindings/pinctrl/rzn1-pinctrl.h new file mode 100644 index 000000000000..21d6cc4d59f5 --- /dev/null +++ b/include/dt-bindings/pinctrl/rzn1-pinctrl.h @@ -0,0 +1,141 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Defines macros and constants for Renesas RZ/N1 pin controller pin + * muxing functions. + */ +#ifndef __DT_BINDINGS_RZN1_PINCTRL_H +#define __DT_BINDINGS_RZN1_PINCTRL_H + +#define RZN1_PINMUX(_gpio, _func) \ + (((_func) << 8) | (_gpio)) + +/* + * Given the different levels of muxing on the SoC, it was decided to + * 'linearize' them into one numerical space. So mux level 1, 2 and the MDIO + * muxes are all represented by one single value. + * + * You can derive the hardware value pretty easily too, as + * 0...9 are Level 1 + * 10...71 are Level 2. The Level 2 mux will be set to this + * value - RZN1_FUNC_L2_OFFSET, and the Level 1 mux will be + * set accordingly. + * 72...103 are for the 2 MDIO muxes. + */ +#define RZN1_FUNC_HIGHZ 0 +#define RZN1_FUNC_0L 1 +#define RZN1_FUNC_CLK_ETH_MII_RGMII_RMII 2 +#define RZN1_FUNC_CLK_ETH_NAND 3 +#define RZN1_FUNC_QSPI 4 +#define RZN1_FUNC_SDIO 5 +#define RZN1_FUNC_LCD 6 +#define RZN1_FUNC_LCD_E 7 +#define RZN1_FUNC_MSEBIM 8 +#define RZN1_FUNC_MSEBIS 9 +#define RZN1_FUNC_L2_OFFSET 10 /* I'm Special */ + +#define RZN1_FUNC_HIGHZ1 (RZN1_FUNC_L2_OFFSET + 0) +#define RZN1_FUNC_ETHERCAT (RZN1_FUNC_L2_OFFSET + 1) +#define RZN1_FUNC_SERCOS3 (RZN1_FUNC_L2_OFFSET + 2) +#define RZN1_FUNC_SDIO_E (RZN1_FUNC_L2_OFFSET + 3) +#define RZN1_FUNC_ETH_MDIO (RZN1_FUNC_L2_OFFSET + 4) +#define RZN1_FUNC_ETH_MDIO_E1 (RZN1_FUNC_L2_OFFSET + 5) +#define RZN1_FUNC_USB (RZN1_FUNC_L2_OFFSET + 6) +#define RZN1_FUNC_MSEBIM_E (RZN1_FUNC_L2_OFFSET + 7) +#define RZN1_FUNC_MSEBIS_E (RZN1_FUNC_L2_OFFSET + 8) +#define RZN1_FUNC_RSV (RZN1_FUNC_L2_OFFSET + 9) +#define RZN1_FUNC_RSV_E (RZN1_FUNC_L2_OFFSET + 10) +#define RZN1_FUNC_RSV_E1 (RZN1_FUNC_L2_OFFSET + 11) +#define RZN1_FUNC_UART0_I (RZN1_FUNC_L2_OFFSET + 12) +#define RZN1_FUNC_UART0_I_E (RZN1_FUNC_L2_OFFSET + 13) +#define RZN1_FUNC_UART1_I (RZN1_FUNC_L2_OFFSET + 14) +#define RZN1_FUNC_UART1_I_E (RZN1_FUNC_L2_OFFSET + 15) +#define RZN1_FUNC_UART2_I (RZN1_FUNC_L2_OFFSET + 16) +#define RZN1_FUNC_UART2_I_E (RZN1_FUNC_L2_OFFSET + 17) +#define RZN1_FUNC_UART0 (RZN1_FUNC_L2_OFFSET + 18) +#define RZN1_FUNC_UART0_E (RZN1_FUNC_L2_OFFSET + 19) +#define RZN1_FUNC_UART1 (RZN1_FUNC_L2_OFFSET + 20) +#define RZN1_FUNC_UART1_E (RZN1_FUNC_L2_OFFSET + 21) +#define RZN1_FUNC_UART2 (RZN1_FUNC_L2_OFFSET + 22) +#define RZN1_FUNC_UART2_E (RZN1_FUNC_L2_OFFSET + 23) +#define RZN1_FUNC_UART3 (RZN1_FUNC_L2_OFFSET + 24) +#define RZN1_FUNC_UART3_E (RZN1_FUNC_L2_OFFSET + 25) +#define RZN1_FUNC_UART4 (RZN1_FUNC_L2_OFFSET + 26) +#define RZN1_FUNC_UART4_E (RZN1_FUNC_L2_OFFSET + 27) +#define RZN1_FUNC_UART5 (RZN1_FUNC_L2_OFFSET + 28) +#define RZN1_FUNC_UART5_E (RZN1_FUNC_L2_OFFSET + 29) +#define RZN1_FUNC_UART6 (RZN1_FUNC_L2_OFFSET + 30) +#define RZN1_FUNC_UART6_E (RZN1_FUNC_L2_OFFSET + 31) +#define RZN1_FUNC_UART7 (RZN1_FUNC_L2_OFFSET + 32) +#define RZN1_FUNC_UART7_E (RZN1_FUNC_L2_OFFSET + 33) +#define RZN1_FUNC_SPI0_M (RZN1_FUNC_L2_OFFSET + 34) +#define RZN1_FUNC_SPI0_M_E (RZN1_FUNC_L2_OFFSET + 35) +#define RZN1_FUNC_SPI1_M (RZN1_FUNC_L2_OFFSET + 36) +#define RZN1_FUNC_SPI1_M_E (RZN1_FUNC_L2_OFFSET + 37) +#define RZN1_FUNC_SPI2_M (RZN1_FUNC_L2_OFFSET + 38) +#define RZN1_FUNC_SPI2_M_E (RZN1_FUNC_L2_OFFSET + 39) +#define RZN1_FUNC_SPI3_M (RZN1_FUNC_L2_OFFSET + 40) +#define RZN1_FUNC_SPI3_M_E (RZN1_FUNC_L2_OFFSET + 41) +#define RZN1_FUNC_SPI4_S (RZN1_FUNC_L2_OFFSET + 42) +#define RZN1_FUNC_SPI4_S_E (RZN1_FUNC_L2_OFFSET + 43) +#define RZN1_FUNC_SPI5_S (RZN1_FUNC_L2_OFFSET + 44) +#define RZN1_FUNC_SPI5_S_E (RZN1_FUNC_L2_OFFSET + 45) +#define RZN1_FUNC_SGPIO0_M (RZN1_FUNC_L2_OFFSET + 46) +#define RZN1_FUNC_SGPIO1_M (RZN1_FUNC_L2_OFFSET + 47) +#define RZN1_FUNC_GPIO (RZN1_FUNC_L2_OFFSET + 48) +#define RZN1_FUNC_CAN (RZN1_FUNC_L2_OFFSET + 49) +#define RZN1_FUNC_I2C (RZN1_FUNC_L2_OFFSET + 50) +#define RZN1_FUNC_SAFE (RZN1_FUNC_L2_OFFSET + 51) +#define RZN1_FUNC_PTO_PWM (RZN1_FUNC_L2_OFFSET + 52) +#define RZN1_FUNC_PTO_PWM1 (RZN1_FUNC_L2_OFFSET + 53) +#define RZN1_FUNC_PTO_PWM2 (RZN1_FUNC_L2_OFFSET + 54) +#define RZN1_FUNC_PTO_PWM3 (RZN1_FUNC_L2_OFFSET + 55) +#define RZN1_FUNC_PTO_PWM4 (RZN1_FUNC_L2_OFFSET + 56) +#define RZN1_FUNC_DELTA_SIGMA (RZN1_FUNC_L2_OFFSET + 57) +#define RZN1_FUNC_SGPIO2_M (RZN1_FUNC_L2_OFFSET + 58) +#define RZN1_FUNC_SGPIO3_M (RZN1_FUNC_L2_OFFSET + 59) +#define RZN1_FUNC_SGPIO4_S (RZN1_FUNC_L2_OFFSET + 60) +#define RZN1_FUNC_MAC_MTIP_SWITCH (RZN1_FUNC_L2_OFFSET + 61) + +#define RZN1_FUNC_MDIO_OFFSET (RZN1_FUNC_L2_OFFSET + 62) + +/* These are MDIO0 peripherals for the RZN1_FUNC_ETH_MDIO function */ +#define RZN1_FUNC_MDIO0_HIGHZ (RZN1_FUNC_MDIO_OFFSET + 0) +#define RZN1_FUNC_MDIO0_GMAC0 (RZN1_FUNC_MDIO_OFFSET + 1) +#define RZN1_FUNC_MDIO0_GMAC1 (RZN1_FUNC_MDIO_OFFSET + 2) +#define RZN1_FUNC_MDIO0_ECAT (RZN1_FUNC_MDIO_OFFSET + 3) +#define RZN1_FUNC_MDIO0_S3_MDIO0 (RZN1_FUNC_MDIO_OFFSET + 4) +#define RZN1_FUNC_MDIO0_S3_MDIO1 (RZN1_FUNC_MDIO_OFFSET + 5) +#define RZN1_FUNC_MDIO0_HWRTOS (RZN1_FUNC_MDIO_OFFSET + 6) +#define RZN1_FUNC_MDIO0_SWITCH (RZN1_FUNC_MDIO_OFFSET + 7) +/* These are MDIO0 peripherals for the RZN1_FUNC_ETH_MDIO_E1 function */ +#define RZN1_FUNC_MDIO0_E1_HIGHZ (RZN1_FUNC_MDIO_OFFSET + 8) +#define RZN1_FUNC_MDIO0_E1_GMAC0 (RZN1_FUNC_MDIO_OFFSET + 9) +#define RZN1_FUNC_MDIO0_E1_GMAC1 (RZN1_FUNC_MDIO_OFFSET + 10) +#define RZN1_FUNC_MDIO0_E1_ECAT (RZN1_FUNC_MDIO_OFFSET + 11) +#define RZN1_FUNC_MDIO0_E1_S3_MDIO0 (RZN1_FUNC_MDIO_OFFSET + 12) +#define RZN1_FUNC_MDIO0_E1_S3_MDIO1 (RZN1_FUNC_MDIO_OFFSET + 13) +#define RZN1_FUNC_MDIO0_E1_HWRTOS (RZN1_FUNC_MDIO_OFFSET + 14) +#define RZN1_FUNC_MDIO0_E1_SWITCH (RZN1_FUNC_MDIO_OFFSET + 15) + +/* These are MDIO1 peripherals for the RZN1_FUNC_ETH_MDIO function */ +#define RZN1_FUNC_MDIO1_HIGHZ (RZN1_FUNC_MDIO_OFFSET + 16) +#define RZN1_FUNC_MDIO1_GMAC0 (RZN1_FUNC_MDIO_OFFSET + 17) +#define RZN1_FUNC_MDIO1_GMAC1 (RZN1_FUNC_MDIO_OFFSET + 18) +#define RZN1_FUNC_MDIO1_ECAT (RZN1_FUNC_MDIO_OFFSET + 19) +#define RZN1_FUNC_MDIO1_S3_MDIO0 (RZN1_FUNC_MDIO_OFFSET + 20) +#define RZN1_FUNC_MDIO1_S3_MDIO1 (RZN1_FUNC_MDIO_OFFSET + 21) +#define RZN1_FUNC_MDIO1_HWRTOS (RZN1_FUNC_MDIO_OFFSET + 22) +#define RZN1_FUNC_MDIO1_SWITCH (RZN1_FUNC_MDIO_OFFSET + 23) +/* These are MDIO1 peripherals for the RZN1_FUNC_ETH_MDIO_E1 function */ +#define RZN1_FUNC_MDIO1_E1_HIGHZ (RZN1_FUNC_MDIO_OFFSET + 24) +#define RZN1_FUNC_MDIO1_E1_GMAC0 (RZN1_FUNC_MDIO_OFFSET + 25) +#define RZN1_FUNC_MDIO1_E1_GMAC1 (RZN1_FUNC_MDIO_OFFSET + 26) +#define RZN1_FUNC_MDIO1_E1_ECAT (RZN1_FUNC_MDIO_OFFSET + 27) +#define RZN1_FUNC_MDIO1_E1_S3_MDIO0 (RZN1_FUNC_MDIO_OFFSET + 28) +#define RZN1_FUNC_MDIO1_E1_S3_MDIO1 (RZN1_FUNC_MDIO_OFFSET + 29) +#define RZN1_FUNC_MDIO1_E1_HWRTOS (RZN1_FUNC_MDIO_OFFSET + 30) +#define RZN1_FUNC_MDIO1_E1_SWITCH (RZN1_FUNC_MDIO_OFFSET + 31) + +#define RZN1_FUNC_MAX (RZN1_FUNC_MDIO_OFFSET + 32) + +#endif /* __DT_BINDINGS_RZN1_PINCTRL_H */ diff --git a/include/dt-bindings/pinctrl/samsung.h b/include/dt-bindings/pinctrl/samsung.h index ceb672305f59..b1832506b923 100644 --- a/include/dt-bindings/pinctrl/samsung.h +++ b/include/dt-bindings/pinctrl/samsung.h @@ -1,14 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0 */ /* * Samsung's Exynos pinctrl bindings * * Copyright (c) 2016 Samsung Electronics Co., Ltd. * http://www.samsung.com * Author: Krzysztof Kozlowski <krzk@kernel.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ + */ #ifndef __DT_BINDINGS_PINCTRL_SAMSUNG_H__ #define __DT_BINDINGS_PINCTRL_SAMSUNG_H__ diff --git a/include/dt-bindings/power/imx8mq-power.h b/include/dt-bindings/power/imx8mq-power.h new file mode 100644 index 000000000000..8a513bd9166e --- /dev/null +++ b/include/dt-bindings/power/imx8mq-power.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright (C) 2018 Pengutronix, Lucas Stach <kernel@pengutronix.de> + */ + +#ifndef __DT_BINDINGS_IMX8MQ_POWER_H__ +#define __DT_BINDINGS_IMX8MQ_POWER_H__ + +#define IMX8M_POWER_DOMAIN_MIPI 0 +#define IMX8M_POWER_DOMAIN_PCIE1 1 +#define IMX8M_POWER_DOMAIN_USB_OTG1 2 +#define IMX8M_POWER_DOMAIN_USB_OTG2 3 +#define IMX8M_POWER_DOMAIN_DDR1 4 +#define IMX8M_POWER_DOMAIN_GPU 5 +#define IMX8M_POWER_DOMAIN_VPU 6 +#define IMX8M_POWER_DOMAIN_DISP 7 +#define IMX8M_POWER_DOMAIN_MIPI_CSI1 8 +#define IMX8M_POWER_DOMAIN_MIPI_CSI2 9 +#define IMX8M_POWER_DOMAIN_PCIE2 10 + +#endif diff --git a/include/dt-bindings/power/owl-s900-powergate.h b/include/dt-bindings/power/owl-s900-powergate.h new file mode 100644 index 000000000000..d939bd964657 --- /dev/null +++ b/include/dt-bindings/power/owl-s900-powergate.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) */ +/* + * Actions Semi S900 SPS + * + * Copyright (c) 2018 Linaro Ltd. + */ +#ifndef DT_BINDINGS_POWER_OWL_S900_POWERGATE_H +#define DT_BINDINGS_POWER_OWL_S900_POWERGATE_H + +#define S900_PD_GPU_B 0 +#define S900_PD_VCE 1 +#define S900_PD_SENSOR 2 +#define S900_PD_VDE 3 +#define S900_PD_HDE 4 +#define S900_PD_USB3 5 +#define S900_PD_DDR0 6 +#define S900_PD_DDR1 7 +#define S900_PD_DE 8 +#define S900_PD_NAND 9 +#define S900_PD_USB2_H0 10 +#define S900_PD_USB2_H1 11 + +#endif diff --git a/include/dt-bindings/power/px30-power.h b/include/dt-bindings/power/px30-power.h new file mode 100644 index 000000000000..30917a99ad20 --- /dev/null +++ b/include/dt-bindings/power/px30-power.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_POWER_PX30_POWER_H__ +#define __DT_BINDINGS_POWER_PX30_POWER_H__ + +/* VD_CORE */ +#define PX30_PD_A35_0 0 +#define PX30_PD_A35_1 1 +#define PX30_PD_A35_2 2 +#define PX30_PD_A35_3 3 +#define PX30_PD_SCU 4 + +/* VD_LOGIC */ +#define PX30_PD_USB 5 +#define PX30_PD_DDR 6 +#define PX30_PD_SDCARD 7 +#define PX30_PD_CRYPTO 8 +#define PX30_PD_GMAC 9 +#define PX30_PD_MMC_NAND 10 +#define PX30_PD_VPU 11 +#define PX30_PD_VO 12 +#define PX30_PD_VI 13 +#define PX30_PD_GPU 14 + +/* VD_PMU */ +#define PX30_PD_PMU 15 + +#endif diff --git a/include/dt-bindings/power/r8a7744-sysc.h b/include/dt-bindings/power/r8a7744-sysc.h new file mode 100644 index 000000000000..8b6529778f98 --- /dev/null +++ b/include/dt-bindings/power/r8a7744-sysc.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2018 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_POWER_R8A7744_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A7744_SYSC_H__ + +/* + * These power domain indices match the numbers of the interrupt bits + * representing the power areas in the various Interrupt Registers + * (e.g. SYSCISR, Interrupt Status Register) + * + * Note that RZ/G1N is identical to RZ/G2M w.r.t. power domains. + */ + +#define R8A7744_PD_CA15_CPU0 0 +#define R8A7744_PD_CA15_CPU1 1 +#define R8A7744_PD_CA15_SCU 12 +#define R8A7744_PD_SGX 20 + +/* Always-on power area */ +#define R8A7744_PD_ALWAYS_ON 32 + +#endif /* __DT_BINDINGS_POWER_R8A7744_SYSC_H__ */ diff --git a/include/dt-bindings/power/r8a77470-sysc.h b/include/dt-bindings/power/r8a77470-sysc.h new file mode 100644 index 000000000000..8bf4db187c31 --- /dev/null +++ b/include/dt-bindings/power/r8a77470-sysc.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2018 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_POWER_R8A77470_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A77470_SYSC_H__ + +/* + * These power domain indices match the numbers of the interrupt bits + * representing the power areas in the various Interrupt Registers + * (e.g. SYSCISR, Interrupt Status Register) + */ + +#define R8A77470_PD_CA7_CPU0 5 +#define R8A77470_PD_CA7_CPU1 6 +#define R8A77470_PD_SGX 20 +#define R8A77470_PD_CA7_SCU 21 + +/* Always-on power area */ +#define R8A77470_PD_ALWAYS_ON 32 + +#endif /* __DT_BINDINGS_POWER_R8A77470_SYSC_H__ */ diff --git a/include/dt-bindings/power/r8a774a1-sysc.h b/include/dt-bindings/power/r8a774a1-sysc.h new file mode 100644 index 000000000000..580f431cd32e --- /dev/null +++ b/include/dt-bindings/power/r8a774a1-sysc.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2018 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_POWER_R8A774A1_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A774A1_SYSC_H__ + +/* + * These power domain indices match the numbers of the interrupt bits + * representing the power areas in the various Interrupt Registers + * (e.g. SYSCISR, Interrupt Status Register) + */ + +#define R8A774A1_PD_CA57_CPU0 0 +#define R8A774A1_PD_CA57_CPU1 1 +#define R8A774A1_PD_CA53_CPU0 5 +#define R8A774A1_PD_CA53_CPU1 6 +#define R8A774A1_PD_CA53_CPU2 7 +#define R8A774A1_PD_CA53_CPU3 8 +#define R8A774A1_PD_CA57_SCU 12 +#define R8A774A1_PD_A3VC 14 +#define R8A774A1_PD_3DG_A 17 +#define R8A774A1_PD_3DG_B 18 +#define R8A774A1_PD_CA53_SCU 21 +#define R8A774A1_PD_A2VC0 25 +#define R8A774A1_PD_A2VC1 26 + +/* Always-on power area */ +#define R8A774A1_PD_ALWAYS_ON 32 + +#endif /* __DT_BINDINGS_POWER_R8A774A1_SYSC_H__ */ diff --git a/include/dt-bindings/power/r8a774c0-sysc.h b/include/dt-bindings/power/r8a774c0-sysc.h new file mode 100644 index 000000000000..9922d4c6f87d --- /dev/null +++ b/include/dt-bindings/power/r8a774c0-sysc.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2018 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_POWER_R8A774C0_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A774C0_SYSC_H__ + +/* + * These power domain indices match the numbers of the interrupt bits + * representing the power areas in the various Interrupt Registers + * (e.g. SYSCISR, Interrupt Status Register) + */ + +#define R8A774C0_PD_CA53_CPU0 5 +#define R8A774C0_PD_CA53_CPU1 6 +#define R8A774C0_PD_A3VC 14 +#define R8A774C0_PD_3DG_A 17 +#define R8A774C0_PD_3DG_B 18 +#define R8A774C0_PD_CA53_SCU 21 +#define R8A774C0_PD_A2VC1 26 + +/* Always-on power area */ +#define R8A774C0_PD_ALWAYS_ON 32 + +#endif /* __DT_BINDINGS_POWER_R8A774C0_SYSC_H__ */ diff --git a/include/dt-bindings/power/r8a77970-sysc.h b/include/dt-bindings/power/r8a77970-sysc.h index bf54779d1625..85cc5f23cf9f 100644 --- a/include/dt-bindings/power/r8a77970-sysc.h +++ b/include/dt-bindings/power/r8a77970-sysc.h @@ -16,13 +16,12 @@ #define R8A77970_PD_CA53_CPU0 5 #define R8A77970_PD_CA53_CPU1 6 -#define R8A77970_PD_CR7 13 #define R8A77970_PD_CA53_SCU 21 #define R8A77970_PD_A2IR0 23 -#define R8A77970_PD_A3IR 24 +#define R8A77970_PD_A3IR 24 #define R8A77970_PD_A2IR1 27 -#define R8A77970_PD_A2IR2 28 -#define R8A77970_PD_A2IR3 29 +#define R8A77970_PD_A2DP 28 +#define R8A77970_PD_A2CN 29 #define R8A77970_PD_A2SC0 30 #define R8A77970_PD_A2SC1 31 diff --git a/include/dt-bindings/power/r8a77980-sysc.h b/include/dt-bindings/power/r8a77980-sysc.h index 2c90c1237725..e12c8587b87e 100644 --- a/include/dt-bindings/power/r8a77980-sysc.h +++ b/include/dt-bindings/power/r8a77980-sysc.h @@ -15,14 +15,14 @@ #define R8A77980_PD_A2SC2 0 #define R8A77980_PD_A2SC3 1 #define R8A77980_PD_A2SC4 2 -#define R8A77980_PD_A2PD0 3 -#define R8A77980_PD_A2PD1 4 +#define R8A77980_PD_A2DP0 3 +#define R8A77980_PD_A2DP1 4 #define R8A77980_PD_CA53_CPU0 5 #define R8A77980_PD_CA53_CPU1 6 #define R8A77980_PD_CA53_CPU2 7 #define R8A77980_PD_CA53_CPU3 8 #define R8A77980_PD_A2CN 10 -#define R8A77980_PD_A3VIP 11 +#define R8A77980_PD_A3VIP0 11 #define R8A77980_PD_A2IR5 12 #define R8A77980_PD_CR7 13 #define R8A77980_PD_A2IR4 15 diff --git a/include/dt-bindings/power/r8a77990-sysc.h b/include/dt-bindings/power/r8a77990-sysc.h new file mode 100644 index 000000000000..944d85beec15 --- /dev/null +++ b/include/dt-bindings/power/r8a77990-sysc.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_POWER_R8A77990_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A77990_SYSC_H__ + +/* + * These power domain indices match the numbers of the interrupt bits + * representing the power areas in the various Interrupt Registers + * (e.g. SYSCISR, Interrupt Status Register) + */ + +#define R8A77990_PD_CA53_CPU0 5 +#define R8A77990_PD_CA53_CPU1 6 +#define R8A77990_PD_CR7 13 +#define R8A77990_PD_A3VC 14 +#define R8A77990_PD_3DG_A 17 +#define R8A77990_PD_3DG_B 18 +#define R8A77990_PD_CA53_SCU 21 +#define R8A77990_PD_A2VC1 26 + +/* Always-on power area */ +#define R8A77990_PD_ALWAYS_ON 32 + +#endif /* __DT_BINDINGS_POWER_R8A77990_SYSC_H__ */ diff --git a/include/dt-bindings/power/raspberrypi-power.h b/include/dt-bindings/power/raspberrypi-power.h index b3ff8e09a78f..3575f9f4b0bd 100644 --- a/include/dt-bindings/power/raspberrypi-power.h +++ b/include/dt-bindings/power/raspberrypi-power.h @@ -1,9 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright © 2015 Broadcom - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #ifndef _DT_BINDINGS_ARM_BCM2835_RPI_POWER_H diff --git a/include/dt-bindings/power/rk3036-power.h b/include/dt-bindings/power/rk3036-power.h new file mode 100644 index 000000000000..0bc6b5d5075e --- /dev/null +++ b/include/dt-bindings/power/rk3036-power.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_POWER_RK3036_POWER_H__ +#define __DT_BINDINGS_POWER_RK3036_POWER_H__ + +#define RK3036_PD_MSCH 0 +#define RK3036_PD_CORE 1 +#define RK3036_PD_PERI 2 +#define RK3036_PD_VIO 3 +#define RK3036_PD_VPU 4 +#define RK3036_PD_GPU 5 +#define RK3036_PD_SYS 6 + +#endif diff --git a/include/dt-bindings/power/rk3066-power.h b/include/dt-bindings/power/rk3066-power.h new file mode 100644 index 000000000000..acf9f310ac53 --- /dev/null +++ b/include/dt-bindings/power/rk3066-power.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_POWER_RK3066_POWER_H__ +#define __DT_BINDINGS_POWER_RK3066_POWER_H__ + +/* VD_CORE */ +#define RK3066_PD_A9_0 0 +#define RK3066_PD_A9_1 1 +#define RK3066_PD_DBG 4 +#define RK3066_PD_SCU 5 + +/* VD_LOGIC */ +#define RK3066_PD_VIDEO 6 +#define RK3066_PD_VIO 7 +#define RK3066_PD_GPU 8 +#define RK3066_PD_PERI 9 +#define RK3066_PD_CPU 10 +#define RK3066_PD_ALIVE 11 + +/* VD_PMU */ +#define RK3066_PD_RTC 12 + +#endif diff --git a/include/dt-bindings/power/rk3128-power.h b/include/dt-bindings/power/rk3128-power.h new file mode 100644 index 000000000000..c051dc3108db --- /dev/null +++ b/include/dt-bindings/power/rk3128-power.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_POWER_RK3128_POWER_H__ +#define __DT_BINDINGS_POWER_RK3128_POWER_H__ + +/* VD_CORE */ +#define RK3128_PD_CORE 0 + +/* VD_LOGIC */ +#define RK3128_PD_VIO 1 +#define RK3128_PD_VIDEO 2 +#define RK3128_PD_GPU 3 +#define RK3128_PD_MSCH 4 + +#endif diff --git a/include/dt-bindings/power/rk3188-power.h b/include/dt-bindings/power/rk3188-power.h new file mode 100644 index 000000000000..93d23dfba33f --- /dev/null +++ b/include/dt-bindings/power/rk3188-power.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_POWER_RK3188_POWER_H__ +#define __DT_BINDINGS_POWER_RK3188_POWER_H__ + +/* VD_CORE */ +#define RK3188_PD_A9_0 0 +#define RK3188_PD_A9_1 1 +#define RK3188_PD_A9_2 2 +#define RK3188_PD_A9_3 3 +#define RK3188_PD_DBG 4 +#define RK3188_PD_SCU 5 + +/* VD_LOGIC */ +#define RK3188_PD_VIDEO 6 +#define RK3188_PD_VIO 7 +#define RK3188_PD_GPU 8 +#define RK3188_PD_PERI 9 +#define RK3188_PD_CPU 10 +#define RK3188_PD_ALIVE 11 + +/* VD_PMU */ +#define RK3188_PD_RTC 12 + +#endif diff --git a/include/dt-bindings/power/rk3228-power.h b/include/dt-bindings/power/rk3228-power.h new file mode 100644 index 000000000000..6a8dc1bf76ce --- /dev/null +++ b/include/dt-bindings/power/rk3228-power.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_POWER_RK3228_POWER_H__ +#define __DT_BINDINGS_POWER_RK3228_POWER_H__ + +/** + * RK3228 idle id Summary. + */ + +#define RK3228_PD_CORE 0 +#define RK3228_PD_MSCH 1 +#define RK3228_PD_BUS 2 +#define RK3228_PD_SYS 3 +#define RK3228_PD_VIO 4 +#define RK3228_PD_VOP 5 +#define RK3228_PD_VPU 6 +#define RK3228_PD_RKVDEC 7 +#define RK3228_PD_GPU 8 +#define RK3228_PD_PERI 9 +#define RK3228_PD_GMAC 10 + +#endif diff --git a/include/dt-bindings/regulator/active-semi,8945a-regulator.h b/include/dt-bindings/regulator/active-semi,8945a-regulator.h new file mode 100644 index 000000000000..9bdba5e3141a --- /dev/null +++ b/include/dt-bindings/regulator/active-semi,8945a-regulator.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018 Microchip Technology, Inc. All rights reserved. + * + * Device Tree binding constants for the ACT8945A PMIC regulators + */ + +#ifndef _DT_BINDINGS_REGULATOR_ACT8945A_H +#define _DT_BINDINGS_REGULATOR_ACT8945A_H + +/* + * These constants should be used to specify regulator modes in device tree for + * ACT8945A regulators as follows: + * ACT8945A_REGULATOR_MODE_FIXED: It is specific to DCDC regulators and it + * specifies the usage of fixed-frequency + * PWM. + * + * ACT8945A_REGULATOR_MODE_NORMAL: It is specific to LDO regulators and it + * specifies the usage of normal mode. + * + * ACT8945A_REGULATOR_MODE_LOWPOWER: For DCDC and LDO regulators; it specify + * the usage of proprietary power-saving + * mode. + */ + +#define ACT8945A_REGULATOR_MODE_FIXED 1 +#define ACT8945A_REGULATOR_MODE_NORMAL 2 +#define ACT8945A_REGULATOR_MODE_LOWPOWER 3 + +#endif diff --git a/include/dt-bindings/regulator/maxim,max77802.h b/include/dt-bindings/regulator/maxim,max77802.h index cf28631d7109..d0baba1973d4 100644 --- a/include/dt-bindings/regulator/maxim,max77802.h +++ b/include/dt-bindings/regulator/maxim,max77802.h @@ -1,10 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2014 Google, Inc * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * * Device Tree binding constants for the Maxim 77802 PMIC regulators */ diff --git a/include/dt-bindings/regulator/qcom,rpmh-regulator.h b/include/dt-bindings/regulator/qcom,rpmh-regulator.h new file mode 100644 index 000000000000..86713dcf9e02 --- /dev/null +++ b/include/dt-bindings/regulator/qcom,rpmh-regulator.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. */ + +#ifndef __QCOM_RPMH_REGULATOR_H +#define __QCOM_RPMH_REGULATOR_H + +/* + * These mode constants may be used to specify modes for various RPMh regulator + * device tree properties (e.g. regulator-initial-mode). Each type of regulator + * supports a subset of the possible modes. + * + * %RPMH_REGULATOR_MODE_RET: Retention mode in which only an extremely small + * load current is allowed. This mode is supported + * by LDO and SMPS type regulators. + * %RPMH_REGULATOR_MODE_LPM: Low power mode in which a small load current is + * allowed. This mode corresponds to PFM for SMPS + * and BOB type regulators. This mode is supported + * by LDO, HFSMPS, BOB, and PMIC4 FTSMPS type + * regulators. + * %RPMH_REGULATOR_MODE_AUTO: Auto mode in which the regulator hardware + * automatically switches between LPM and HPM based + * upon the real-time load current. This mode is + * supported by HFSMPS, BOB, and PMIC4 FTSMPS type + * regulators. + * %RPMH_REGULATOR_MODE_HPM: High power mode in which the full rated current + * of the regulator is allowed. This mode + * corresponds to PWM for SMPS and BOB type + * regulators. This mode is supported by all types + * of regulators. + */ +#define RPMH_REGULATOR_MODE_RET 0 +#define RPMH_REGULATOR_MODE_LPM 1 +#define RPMH_REGULATOR_MODE_AUTO 2 +#define RPMH_REGULATOR_MODE_HPM 3 + +#endif diff --git a/include/dt-bindings/reset/actions,s700-reset.h b/include/dt-bindings/reset/actions,s700-reset.h new file mode 100644 index 000000000000..5e3b16b8ef53 --- /dev/null +++ b/include/dt-bindings/reset/actions,s700-reset.h @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +// +// Device Tree binding constants for Actions Semi S700 Reset Management Unit +// +// Copyright (c) 2018 Linaro Ltd. + +#ifndef __DT_BINDINGS_ACTIONS_S700_RESET_H +#define __DT_BINDINGS_ACTIONS_S700_RESET_H + +#define RESET_AUDIO 0 +#define RESET_CSI 1 +#define RESET_DE 2 +#define RESET_DSI 3 +#define RESET_GPIO 4 +#define RESET_I2C0 5 +#define RESET_I2C1 6 +#define RESET_I2C2 7 +#define RESET_I2C3 8 +#define RESET_KEY 9 +#define RESET_LCD0 10 +#define RESET_SI 11 +#define RESET_SPI0 12 +#define RESET_SPI1 13 +#define RESET_SPI2 14 +#define RESET_SPI3 15 +#define RESET_UART0 16 +#define RESET_UART1 17 +#define RESET_UART2 18 +#define RESET_UART3 19 +#define RESET_UART4 20 +#define RESET_UART5 21 +#define RESET_UART6 22 + +#endif /* __DT_BINDINGS_ACTIONS_S700_RESET_H */ diff --git a/include/dt-bindings/reset/actions,s900-reset.h b/include/dt-bindings/reset/actions,s900-reset.h new file mode 100644 index 000000000000..42c19d02e43b --- /dev/null +++ b/include/dt-bindings/reset/actions,s900-reset.h @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +// +// Device Tree binding constants for Actions Semi S900 Reset Management Unit +// +// Copyright (c) 2018 Linaro Ltd. + +#ifndef __DT_BINDINGS_ACTIONS_S900_RESET_H +#define __DT_BINDINGS_ACTIONS_S900_RESET_H + +#define RESET_CHIPID 0 +#define RESET_CPU_SCNT 1 +#define RESET_SRAMI 2 +#define RESET_DDR_CTL_PHY 3 +#define RESET_DMAC 4 +#define RESET_GPIO 5 +#define RESET_BISP_AXI 6 +#define RESET_CSI0 7 +#define RESET_CSI1 8 +#define RESET_DE 9 +#define RESET_DSI 10 +#define RESET_GPU3D_PA 11 +#define RESET_GPU3D_PB 12 +#define RESET_HDE 13 +#define RESET_I2C0 14 +#define RESET_I2C1 15 +#define RESET_I2C2 16 +#define RESET_I2C3 17 +#define RESET_I2C4 18 +#define RESET_I2C5 19 +#define RESET_IMX 20 +#define RESET_NANDC0 21 +#define RESET_NANDC1 22 +#define RESET_SD0 23 +#define RESET_SD1 24 +#define RESET_SD2 25 +#define RESET_SD3 26 +#define RESET_SPI0 27 +#define RESET_SPI1 28 +#define RESET_SPI2 29 +#define RESET_SPI3 30 +#define RESET_UART0 31 +#define RESET_UART1 32 +#define RESET_UART2 33 +#define RESET_UART3 34 +#define RESET_UART4 35 +#define RESET_UART5 36 +#define RESET_UART6 37 +#define RESET_HDMI 38 +#define RESET_LVDS 39 +#define RESET_EDP 40 +#define RESET_USB2HUB 41 +#define RESET_USB2HSIC 42 +#define RESET_USB3 43 +#define RESET_PCM1 44 +#define RESET_AUDIO 45 +#define RESET_PCM0 46 +#define RESET_SE 47 +#define RESET_GIC 48 +#define RESET_DDR_CTL_PHY_AXI 49 +#define RESET_CMU_DDR 50 +#define RESET_DMM 51 +#define RESET_HDCP2TX 52 +#define RESET_ETHERNET 53 + +#endif /* __DT_BINDINGS_ACTIONS_S900_RESET_H */ diff --git a/include/dt-bindings/reset/amlogic,meson-axg-audio-arb.h b/include/dt-bindings/reset/amlogic,meson-axg-audio-arb.h new file mode 100644 index 000000000000..05c36367875c --- /dev/null +++ b/include/dt-bindings/reset/amlogic,meson-axg-audio-arb.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) + * + * Copyright (c) 2018 Baylibre SAS. + * Author: Jerome Brunet <jbrunet@baylibre.com> + */ + +#ifndef _DT_BINDINGS_AMLOGIC_MESON_AXG_AUDIO_ARB_H +#define _DT_BINDINGS_AMLOGIC_MESON_AXG_AUDIO_ARB_H + +#define AXG_ARB_TODDR_A 0 +#define AXG_ARB_TODDR_B 1 +#define AXG_ARB_TODDR_C 2 +#define AXG_ARB_FRDDR_A 3 +#define AXG_ARB_FRDDR_B 4 +#define AXG_ARB_FRDDR_C 5 + +#endif /* _DT_BINDINGS_AMLOGIC_MESON_AXG_AUDIO_ARB_H */ diff --git a/include/dt-bindings/reset/axg-aoclkc.h b/include/dt-bindings/reset/axg-aoclkc.h new file mode 100644 index 000000000000..d342c0b6b2a7 --- /dev/null +++ b/include/dt-bindings/reset/axg-aoclkc.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ +/* + * Copyright (c) 2016 BayLibre, SAS + * Author: Neil Armstrong <narmstrong@baylibre.com> + * + * Copyright (c) 2018 Amlogic, inc. + * Author: Qiufang Dai <qiufang.dai@amlogic.com> + */ + +#ifndef DT_BINDINGS_RESET_AMLOGIC_MESON_AXG_AOCLK +#define DT_BINDINGS_RESET_AMLOGIC_MESON_AXG_AOCLK + +#define RESET_AO_REMOTE 0 +#define RESET_AO_I2C_MASTER 1 +#define RESET_AO_I2C_SLAVE 2 +#define RESET_AO_UART1 3 +#define RESET_AO_UART2 4 +#define RESET_AO_IR_BLASTER 5 + +#endif diff --git a/include/dt-bindings/reset/imx7-reset.h b/include/dt-bindings/reset/imx7-reset.h index 63948170c7b2..31b3f87dde9a 100644 --- a/include/dt-bindings/reset/imx7-reset.h +++ b/include/dt-bindings/reset/imx7-reset.h @@ -56,7 +56,9 @@ #define IMX7_RESET_DDRC_PRST 23 #define IMX7_RESET_DDRC_CORE_RST 24 -#define IMX7_RESET_NUM 25 +#define IMX7_RESET_PCIE_CTRL_APPS_TURNOFF 25 + +#define IMX7_RESET_NUM 26 #endif diff --git a/include/dt-bindings/reset/mt2701-resets.h b/include/dt-bindings/reset/mt2701-resets.h index 21deb547cfa4..50b7f066da9a 100644 --- a/include/dt-bindings/reset/mt2701-resets.h +++ b/include/dt-bindings/reset/mt2701-resets.h @@ -87,4 +87,7 @@ #define MT2701_ETHSYS_GMAC_RST 23 #define MT2701_ETHSYS_PPE_RST 31 +/* G3DSYS resets */ +#define MT2701_G3DSYS_CORE_RST 0 + #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT2701 */ diff --git a/include/dt-bindings/reset/qcom,sdm845-aoss.h b/include/dt-bindings/reset/qcom,sdm845-aoss.h new file mode 100644 index 000000000000..476c5fc873b6 --- /dev/null +++ b/include/dt-bindings/reset/qcom,sdm845-aoss.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_RESET_AOSS_SDM_845_H +#define _DT_BINDINGS_RESET_AOSS_SDM_845_H + +#define AOSS_CC_MSS_RESTART 0 +#define AOSS_CC_CAMSS_RESTART 1 +#define AOSS_CC_VENUS_RESTART 2 +#define AOSS_CC_GPU_RESTART 3 +#define AOSS_CC_DISPSS_RESTART 4 +#define AOSS_CC_WCSS_RESTART 5 +#define AOSS_CC_LPASS_RESTART 6 + +#endif diff --git a/include/dt-bindings/reset/qcom,sdm845-pdc.h b/include/dt-bindings/reset/qcom,sdm845-pdc.h new file mode 100644 index 000000000000..53c37f9c319a --- /dev/null +++ b/include/dt-bindings/reset/qcom,sdm845-pdc.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_RESET_PDC_SDM_845_H +#define _DT_BINDINGS_RESET_PDC_SDM_845_H + +#define PDC_APPS_SYNC_RESET 0 +#define PDC_SP_SYNC_RESET 1 +#define PDC_AUDIO_SYNC_RESET 2 +#define PDC_SENSORS_SYNC_RESET 3 +#define PDC_AOP_SYNC_RESET 4 +#define PDC_DEBUG_SYNC_RESET 5 +#define PDC_GPU_SYNC_RESET 6 +#define PDC_DISPLAY_SYNC_RESET 7 +#define PDC_COMPUTE_SYNC_RESET 8 +#define PDC_MODEM_SYNC_RESET 9 + +#endif diff --git a/include/dt-bindings/reset/sun50i-h6-r-ccu.h b/include/dt-bindings/reset/sun50i-h6-r-ccu.h new file mode 100644 index 000000000000..01c84dba49a4 --- /dev/null +++ b/include/dt-bindings/reset/sun50i-h6-r-ccu.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* + * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz> + */ + +#ifndef _DT_BINDINGS_RST_SUN50I_H6_R_CCU_H_ +#define _DT_BINDINGS_RST_SUN50I_H6_R_CCU_H_ + +#define RST_R_APB1_TIMER 0 +#define RST_R_APB1_TWD 1 +#define RST_R_APB1_PWM 2 +#define RST_R_APB2_UART 3 +#define RST_R_APB2_I2C 4 +#define RST_R_APB1_IR 5 +#define RST_R_APB1_W1 6 + +#endif /* _DT_BINDINGS_RST_SUN50I_H6_R_CCU_H_ */ diff --git a/include/dt-bindings/reset/sun8i-de2.h b/include/dt-bindings/reset/sun8i-de2.h index 9526017432f0..1c36a6ac86d6 100644 --- a/include/dt-bindings/reset/sun8i-de2.h +++ b/include/dt-bindings/reset/sun8i-de2.h @@ -10,5 +10,6 @@ #define RST_MIXER0 0 #define RST_MIXER1 1 #define RST_WB 2 +#define RST_ROT 3 #endif /* _DT_BINDINGS_RESET_SUN8I_DE2_H_ */ diff --git a/include/dt-bindings/reset/suniv-ccu-f1c100s.h b/include/dt-bindings/reset/suniv-ccu-f1c100s.h new file mode 100644 index 000000000000..6a4b4385fe5a --- /dev/null +++ b/include/dt-bindings/reset/suniv-ccu-f1c100s.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) + * + * Copyright (C) 2018 Icenowy Zheng <icenowy@aosc.xyz> + * + */ + +#ifndef _DT_BINDINGS_RST_SUNIV_F1C100S_H_ +#define _DT_BINDINGS_RST_SUNIV_F1C100S_H_ + +#define RST_USB_PHY0 0 +#define RST_BUS_DMA 1 +#define RST_BUS_MMC0 2 +#define RST_BUS_MMC1 3 +#define RST_BUS_DRAM 4 +#define RST_BUS_SPI0 5 +#define RST_BUS_SPI1 6 +#define RST_BUS_OTG 7 +#define RST_BUS_VE 8 +#define RST_BUS_LCD 9 +#define RST_BUS_DEINTERLACE 10 +#define RST_BUS_CSI 11 +#define RST_BUS_TVD 12 +#define RST_BUS_TVE 13 +#define RST_BUS_DE_BE 14 +#define RST_BUS_DE_FE 15 +#define RST_BUS_CODEC 16 +#define RST_BUS_SPDIF 17 +#define RST_BUS_IR 18 +#define RST_BUS_RSB 19 +#define RST_BUS_I2S0 20 +#define RST_BUS_I2C0 21 +#define RST_BUS_I2C1 22 +#define RST_BUS_I2C2 23 +#define RST_BUS_UART0 24 +#define RST_BUS_UART1 25 +#define RST_BUS_UART2 26 + +#endif /* _DT_BINDINGS_RST_SUNIV_F1C100S_H_ */ diff --git a/include/dt-bindings/soc/qcom,apr.h b/include/dt-bindings/soc/qcom,apr.h new file mode 100644 index 000000000000..006362400c0f --- /dev/null +++ b/include/dt-bindings/soc/qcom,apr.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_QCOM_APR_H +#define __DT_BINDINGS_QCOM_APR_H + +/* Domain IDs */ +#define APR_DOMAIN_SIM 0x1 +#define APR_DOMAIN_PC 0x2 +#define APR_DOMAIN_MODEM 0x3 +#define APR_DOMAIN_ADSP 0x4 +#define APR_DOMAIN_APPS 0x5 +#define APR_DOMAIN_MAX 0x6 + +/* ADSP service IDs */ +#define APR_SVC_ADSP_CORE 0x3 +#define APR_SVC_AFE 0x4 +#define APR_SVC_VSM 0x5 +#define APR_SVC_VPM 0x6 +#define APR_SVC_ASM 0x7 +#define APR_SVC_ADM 0x8 +#define APR_SVC_ADSP_MVM 0x09 +#define APR_SVC_ADSP_CVS 0x0A +#define APR_SVC_ADSP_CVP 0x0B +#define APR_SVC_USM 0x0C +#define APR_SVC_LSM 0x0D +#define APR_SVC_VIDC 0x16 +#define APR_SVC_MAX 0x17 + +#endif /* __DT_BINDINGS_QCOM_APR_H */ diff --git a/include/dt-bindings/soc/qcom,rpmh-rsc.h b/include/dt-bindings/soc/qcom,rpmh-rsc.h new file mode 100644 index 000000000000..868f998ea998 --- /dev/null +++ b/include/dt-bindings/soc/qcom,rpmh-rsc.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. + */ + +#ifndef __DT_QCOM_RPMH_RSC_H__ +#define __DT_QCOM_RPMH_RSC_H__ + +#define SLEEP_TCS 0 +#define WAKE_TCS 1 +#define ACTIVE_TCS 2 +#define CONTROL_TCS 3 + +#endif /* __DT_QCOM_RPMH_RSC_H__ */ diff --git a/include/dt-bindings/sound/fsl-imx-audmux.h b/include/dt-bindings/sound/fsl-imx-audmux.h index 751fe1416f95..15f138bebe16 100644 --- a/include/dt-bindings/sound/fsl-imx-audmux.h +++ b/include/dt-bindings/sound/fsl-imx-audmux.h @@ -25,6 +25,13 @@ #define MX51_AUDMUX_PORT6 5 #define MX51_AUDMUX_PORT7 6 +/* + * TFCSEL/RFCSEL (i.MX27) or TFSEL/TCSEL/RFSEL/RCSEL (i.MX31/51/53/6Q) + * can be sourced from Rx/Tx. + */ +#define IMX_AUDMUX_RXFS 0x8 +#define IMX_AUDMUX_RXCLK 0x8 + /* Register definitions for the i.MX21/27 Digital Audio Multiplexer */ #define IMX_AUDMUX_V1_PCR_INMMASK(x) ((x) & 0xff) #define IMX_AUDMUX_V1_PCR_INMEN (1 << 8) diff --git a/include/dt-bindings/sound/qcom,q6afe.h b/include/dt-bindings/sound/qcom,q6afe.h new file mode 100644 index 000000000000..1df06f8ad5c3 --- /dev/null +++ b/include/dt-bindings/sound/qcom,q6afe.h @@ -0,0 +1,112 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_Q6_AFE_H__ +#define __DT_BINDINGS_Q6_AFE_H__ + +/* Audio Front End (AFE) virtual ports IDs */ +#define HDMI_RX 1 +#define SLIMBUS_0_RX 2 +#define SLIMBUS_0_TX 3 +#define SLIMBUS_1_RX 4 +#define SLIMBUS_1_TX 5 +#define SLIMBUS_2_RX 6 +#define SLIMBUS_2_TX 7 +#define SLIMBUS_3_RX 8 +#define SLIMBUS_3_TX 9 +#define SLIMBUS_4_RX 10 +#define SLIMBUS_4_TX 11 +#define SLIMBUS_5_RX 12 +#define SLIMBUS_5_TX 13 +#define SLIMBUS_6_RX 14 +#define SLIMBUS_6_TX 15 +#define PRIMARY_MI2S_RX 16 +#define PRIMARY_MI2S_TX 17 +#define SECONDARY_MI2S_RX 18 +#define SECONDARY_MI2S_TX 19 +#define TERTIARY_MI2S_RX 20 +#define TERTIARY_MI2S_TX 21 +#define QUATERNARY_MI2S_RX 22 +#define QUATERNARY_MI2S_TX 23 +#define PRIMARY_TDM_RX_0 24 +#define PRIMARY_TDM_TX_0 25 +#define PRIMARY_TDM_RX_1 26 +#define PRIMARY_TDM_TX_1 27 +#define PRIMARY_TDM_RX_2 28 +#define PRIMARY_TDM_TX_2 29 +#define PRIMARY_TDM_RX_3 30 +#define PRIMARY_TDM_TX_3 31 +#define PRIMARY_TDM_RX_4 32 +#define PRIMARY_TDM_TX_4 33 +#define PRIMARY_TDM_RX_5 34 +#define PRIMARY_TDM_TX_5 35 +#define PRIMARY_TDM_RX_6 36 +#define PRIMARY_TDM_TX_6 37 +#define PRIMARY_TDM_RX_7 38 +#define PRIMARY_TDM_TX_7 39 +#define SECONDARY_TDM_RX_0 40 +#define SECONDARY_TDM_TX_0 41 +#define SECONDARY_TDM_RX_1 42 +#define SECONDARY_TDM_TX_1 43 +#define SECONDARY_TDM_RX_2 44 +#define SECONDARY_TDM_TX_2 45 +#define SECONDARY_TDM_RX_3 46 +#define SECONDARY_TDM_TX_3 47 +#define SECONDARY_TDM_RX_4 48 +#define SECONDARY_TDM_TX_4 49 +#define SECONDARY_TDM_RX_5 50 +#define SECONDARY_TDM_TX_5 51 +#define SECONDARY_TDM_RX_6 52 +#define SECONDARY_TDM_TX_6 53 +#define SECONDARY_TDM_RX_7 54 +#define SECONDARY_TDM_TX_7 55 +#define TERTIARY_TDM_RX_0 56 +#define TERTIARY_TDM_TX_0 57 +#define TERTIARY_TDM_RX_1 58 +#define TERTIARY_TDM_TX_1 59 +#define TERTIARY_TDM_RX_2 60 +#define TERTIARY_TDM_TX_2 61 +#define TERTIARY_TDM_RX_3 62 +#define TERTIARY_TDM_TX_3 63 +#define TERTIARY_TDM_RX_4 64 +#define TERTIARY_TDM_TX_4 65 +#define TERTIARY_TDM_RX_5 66 +#define TERTIARY_TDM_TX_5 67 +#define TERTIARY_TDM_RX_6 68 +#define TERTIARY_TDM_TX_6 69 +#define TERTIARY_TDM_RX_7 70 +#define TERTIARY_TDM_TX_7 71 +#define QUATERNARY_TDM_RX_0 72 +#define QUATERNARY_TDM_TX_0 73 +#define QUATERNARY_TDM_RX_1 74 +#define QUATERNARY_TDM_TX_1 75 +#define QUATERNARY_TDM_RX_2 76 +#define QUATERNARY_TDM_TX_2 77 +#define QUATERNARY_TDM_RX_3 78 +#define QUATERNARY_TDM_TX_3 79 +#define QUATERNARY_TDM_RX_4 80 +#define QUATERNARY_TDM_TX_4 81 +#define QUATERNARY_TDM_RX_5 82 +#define QUATERNARY_TDM_TX_5 83 +#define QUATERNARY_TDM_RX_6 84 +#define QUATERNARY_TDM_TX_6 85 +#define QUATERNARY_TDM_RX_7 86 +#define QUATERNARY_TDM_TX_7 87 +#define QUINARY_TDM_RX_0 88 +#define QUINARY_TDM_TX_0 89 +#define QUINARY_TDM_RX_1 90 +#define QUINARY_TDM_TX_1 91 +#define QUINARY_TDM_RX_2 92 +#define QUINARY_TDM_TX_2 93 +#define QUINARY_TDM_RX_3 94 +#define QUINARY_TDM_TX_3 95 +#define QUINARY_TDM_RX_4 96 +#define QUINARY_TDM_TX_4 97 +#define QUINARY_TDM_RX_5 98 +#define QUINARY_TDM_TX_5 99 +#define QUINARY_TDM_RX_6 100 +#define QUINARY_TDM_TX_6 101 +#define QUINARY_TDM_RX_7 102 +#define QUINARY_TDM_TX_7 103 +#define DISPLAY_PORT_RX 104 + +#endif /* __DT_BINDINGS_Q6_AFE_H__ */ + diff --git a/include/dt-bindings/sound/qcom,q6asm.h b/include/dt-bindings/sound/qcom,q6asm.h new file mode 100644 index 000000000000..1eb77d87c2e8 --- /dev/null +++ b/include/dt-bindings/sound/qcom,q6asm.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_Q6_ASM_H__ +#define __DT_BINDINGS_Q6_ASM_H__ + +#define MSM_FRONTEND_DAI_MULTIMEDIA1 0 +#define MSM_FRONTEND_DAI_MULTIMEDIA2 1 +#define MSM_FRONTEND_DAI_MULTIMEDIA3 2 +#define MSM_FRONTEND_DAI_MULTIMEDIA4 3 +#define MSM_FRONTEND_DAI_MULTIMEDIA5 4 +#define MSM_FRONTEND_DAI_MULTIMEDIA6 5 +#define MSM_FRONTEND_DAI_MULTIMEDIA7 6 +#define MSM_FRONTEND_DAI_MULTIMEDIA8 7 +#define MSM_FRONTEND_DAI_MULTIMEDIA9 8 +#define MSM_FRONTEND_DAI_MULTIMEDIA10 9 +#define MSM_FRONTEND_DAI_MULTIMEDIA11 10 +#define MSM_FRONTEND_DAI_MULTIMEDIA12 11 +#define MSM_FRONTEND_DAI_MULTIMEDIA13 12 +#define MSM_FRONTEND_DAI_MULTIMEDIA14 13 +#define MSM_FRONTEND_DAI_MULTIMEDIA15 14 +#define MSM_FRONTEND_DAI_MULTIMEDIA16 15 + +#endif /* __DT_BINDINGS_Q6_ASM_H__ */ diff --git a/include/dt-bindings/sound/rt5640.h b/include/dt-bindings/sound/rt5640.h new file mode 100644 index 000000000000..154c9b4414f2 --- /dev/null +++ b/include/dt-bindings/sound/rt5640.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_RT5640_H +#define __DT_RT5640_H + +#define RT5640_DMIC1_DATA_PIN_NONE 0 +#define RT5640_DMIC1_DATA_PIN_IN1P 1 +#define RT5640_DMIC1_DATA_PIN_GPIO3 2 + +#define RT5640_DMIC2_DATA_PIN_NONE 0 +#define RT5640_DMIC2_DATA_PIN_IN1N 1 +#define RT5640_DMIC2_DATA_PIN_GPIO4 2 + +#define RT5640_JD_SRC_GPIO1 1 +#define RT5640_JD_SRC_JD1_IN4P 2 +#define RT5640_JD_SRC_JD2_IN4N 3 +#define RT5640_JD_SRC_GPIO2 4 +#define RT5640_JD_SRC_GPIO3 5 +#define RT5640_JD_SRC_GPIO4 6 + +#define RT5640_OVCD_SF_0P5 0 +#define RT5640_OVCD_SF_0P75 1 +#define RT5640_OVCD_SF_1P0 2 +#define RT5640_OVCD_SF_1P5 3 + +#endif /* __DT_RT5640_H */ diff --git a/include/dt-bindings/thermal/tegra194-bpmp-thermal.h b/include/dt-bindings/thermal/tegra194-bpmp-thermal.h new file mode 100644 index 000000000000..aa7fb08135ca --- /dev/null +++ b/include/dt-bindings/thermal/tegra194-bpmp-thermal.h @@ -0,0 +1,15 @@ +/* + * This header provides constants for binding nvidia,tegra194-bpmp-thermal. + */ + +#ifndef _DT_BINDINGS_THERMAL_TEGRA194_BPMP_THERMAL_H +#define _DT_BINDINGS_THERMAL_TEGRA194_BPMP_THERMAL_H + +#define TEGRA194_BPMP_THERMAL_ZONE_CPU 2 +#define TEGRA194_BPMP_THERMAL_ZONE_GPU 3 +#define TEGRA194_BPMP_THERMAL_ZONE_AUX 4 +#define TEGRA194_BPMP_THERMAL_ZONE_PLLX 5 +#define TEGRA194_BPMP_THERMAL_ZONE_AO 6 +#define TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX 7 + +#endif diff --git a/include/dt-bindings/thermal/thermal_exynos.h b/include/dt-bindings/thermal/thermal_exynos.h index 0646500bca69..642e4e7f4084 100644 --- a/include/dt-bindings/thermal/thermal_exynos.h +++ b/include/dt-bindings/thermal/thermal_exynos.h @@ -1,19 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ /* * thermal_exynos.h - Samsung EXYNOS TMU device tree definitions * * Copyright (C) 2014 Samsung Electronics * Lukasz Majewski <l.majewski@samsung.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * */ #ifndef _EXYNOS_THERMAL_TMU_DT_H diff --git a/include/dt-bindings/usb/pd.h b/include/dt-bindings/usb/pd.h new file mode 100644 index 000000000000..985f2bbd4d24 --- /dev/null +++ b/include/dt-bindings/usb/pd.h @@ -0,0 +1,88 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_POWER_DELIVERY_H +#define __DT_POWER_DELIVERY_H + +/* Power delivery Power Data Object definitions */ +#define PDO_TYPE_FIXED 0 +#define PDO_TYPE_BATT 1 +#define PDO_TYPE_VAR 2 +#define PDO_TYPE_APDO 3 + +#define PDO_TYPE_SHIFT 30 +#define PDO_TYPE_MASK 0x3 + +#define PDO_TYPE(t) ((t) << PDO_TYPE_SHIFT) + +#define PDO_VOLT_MASK 0x3ff +#define PDO_CURR_MASK 0x3ff +#define PDO_PWR_MASK 0x3ff + +#define PDO_FIXED_DUAL_ROLE (1 << 29) /* Power role swap supported */ +#define PDO_FIXED_SUSPEND (1 << 28) /* USB Suspend supported (Source) */ +#define PDO_FIXED_HIGHER_CAP (1 << 28) /* Requires more than vSafe5V (Sink) */ +#define PDO_FIXED_EXTPOWER (1 << 27) /* Externally powered */ +#define PDO_FIXED_USB_COMM (1 << 26) /* USB communications capable */ +#define PDO_FIXED_DATA_SWAP (1 << 25) /* Data role swap supported */ +#define PDO_FIXED_VOLT_SHIFT 10 /* 50mV units */ +#define PDO_FIXED_CURR_SHIFT 0 /* 10mA units */ + +#define PDO_FIXED_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_FIXED_VOLT_SHIFT) +#define PDO_FIXED_CURR(ma) ((((ma) / 10) & PDO_CURR_MASK) << PDO_FIXED_CURR_SHIFT) + +#define PDO_FIXED(mv, ma, flags) \ + (PDO_TYPE(PDO_TYPE_FIXED) | (flags) | \ + PDO_FIXED_VOLT(mv) | PDO_FIXED_CURR(ma)) + +#define VSAFE5V 5000 /* mv units */ + +#define PDO_BATT_MAX_VOLT_SHIFT 20 /* 50mV units */ +#define PDO_BATT_MIN_VOLT_SHIFT 10 /* 50mV units */ +#define PDO_BATT_MAX_PWR_SHIFT 0 /* 250mW units */ + +#define PDO_BATT_MIN_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_BATT_MIN_VOLT_SHIFT) +#define PDO_BATT_MAX_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_BATT_MAX_VOLT_SHIFT) +#define PDO_BATT_MAX_POWER(mw) ((((mw) / 250) & PDO_PWR_MASK) << PDO_BATT_MAX_PWR_SHIFT) + +#define PDO_BATT(min_mv, max_mv, max_mw) \ + (PDO_TYPE(PDO_TYPE_BATT) | PDO_BATT_MIN_VOLT(min_mv) | \ + PDO_BATT_MAX_VOLT(max_mv) | PDO_BATT_MAX_POWER(max_mw)) + +#define PDO_VAR_MAX_VOLT_SHIFT 20 /* 50mV units */ +#define PDO_VAR_MIN_VOLT_SHIFT 10 /* 50mV units */ +#define PDO_VAR_MAX_CURR_SHIFT 0 /* 10mA units */ + +#define PDO_VAR_MIN_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_VAR_MIN_VOLT_SHIFT) +#define PDO_VAR_MAX_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_VAR_MAX_VOLT_SHIFT) +#define PDO_VAR_MAX_CURR(ma) ((((ma) / 10) & PDO_CURR_MASK) << PDO_VAR_MAX_CURR_SHIFT) + +#define PDO_VAR(min_mv, max_mv, max_ma) \ + (PDO_TYPE(PDO_TYPE_VAR) | PDO_VAR_MIN_VOLT(min_mv) | \ + PDO_VAR_MAX_VOLT(max_mv) | PDO_VAR_MAX_CURR(max_ma)) + +#define APDO_TYPE_PPS 0 + +#define PDO_APDO_TYPE_SHIFT 28 /* Only valid value currently is 0x0 - PPS */ +#define PDO_APDO_TYPE_MASK 0x3 + +#define PDO_APDO_TYPE(t) ((t) << PDO_APDO_TYPE_SHIFT) + +#define PDO_PPS_APDO_MAX_VOLT_SHIFT 17 /* 100mV units */ +#define PDO_PPS_APDO_MIN_VOLT_SHIFT 8 /* 100mV units */ +#define PDO_PPS_APDO_MAX_CURR_SHIFT 0 /* 50mA units */ + +#define PDO_PPS_APDO_VOLT_MASK 0xff +#define PDO_PPS_APDO_CURR_MASK 0x7f + +#define PDO_PPS_APDO_MIN_VOLT(mv) \ + ((((mv) / 100) & PDO_PPS_APDO_VOLT_MASK) << PDO_PPS_APDO_MIN_VOLT_SHIFT) +#define PDO_PPS_APDO_MAX_VOLT(mv) \ + ((((mv) / 100) & PDO_PPS_APDO_VOLT_MASK) << PDO_PPS_APDO_MAX_VOLT_SHIFT) +#define PDO_PPS_APDO_MAX_CURR(ma) \ + ((((ma) / 50) & PDO_PPS_APDO_CURR_MASK) << PDO_PPS_APDO_MAX_CURR_SHIFT) + +#define PDO_PPS_APDO(min_mv, max_mv, max_ma) \ + (PDO_TYPE(PDO_TYPE_APDO) | PDO_APDO_TYPE(APDO_TYPE_PPS) | \ + PDO_PPS_APDO_MIN_VOLT(min_mv) | PDO_PPS_APDO_MAX_VOLT(max_mv) | \ + PDO_PPS_APDO_MAX_CURR(max_ma)) + + #endif /* __DT_POWER_DELIVERY_H */ |