diff options
Diffstat (limited to 'include/dt-bindings/clock/starfive-jh7100.h')
| -rw-r--r-- | include/dt-bindings/clock/starfive-jh7100.h | 203 |
1 files changed, 203 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/starfive-jh7100.h b/include/dt-bindings/clock/starfive-jh7100.h new file mode 100644 index 000000000000..35857c3254c6 --- /dev/null +++ b/include/dt-bindings/clock/starfive-jh7100.h @@ -0,0 +1,203 @@ +/* SPDX-License-Identifier: GPL-2.0 OR X11 */ +/* + * Copyright (C) 2021 Ahmad Fatoum, Pengutronix + */ + +#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7100_H__ +#define __DT_BINDINGS_CLOCK_STARFIVE_JH7100_H__ + +#define JH7100_CLK_OSC_SYS 0 +#define JH7100_CLK_OSC_AUD 1 +#define JH7100_CLK_PLL0_OUT 2 +#define JH7100_CLK_PLL1_OUT 3 +#define JH7100_CLK_PLL2_OUT 4 +#define JH7100_CLK_CPUNDBUS_ROOT 5 +#define JH7100_CLK_DLA_ROOT 6 +#define JH7100_CLK_DSP_ROOT 7 +#define JH7100_CLK_GMACUSB_ROOT 8 +#define JH7100_CLK_PERH0_ROOT 9 +#define JH7100_CLK_PERH1_ROOT 10 +#define JH7100_CLK_VIN_ROOT 11 +#define JH7100_CLK_VOUT_ROOT 12 +#define JH7100_CLK_AUDIO_ROOT 13 +#define JH7100_CLK_CDECHIFI4_ROOT 14 +#define JH7100_CLK_CDEC_ROOT 15 +#define JH7100_CLK_VOUTBUS_ROOT 16 +#define JH7100_CLK_CPUNBUS_ROOT_DIV 17 +#define JH7100_CLK_DSP_ROOT_DIV 18 +#define JH7100_CLK_PERH0_SRC 19 +#define JH7100_CLK_PERH1_SRC 20 +#define JH7100_CLK_PLL0_TESTOUT 21 +#define JH7100_CLK_PLL1_TESTOUT 22 +#define JH7100_CLK_PLL2_TESTOUT 23 +#define JH7100_CLK_PLL2_REF 24 +#define JH7100_CLK_CPU_CORE 25 +#define JH7100_CLK_CPU_AXI 26 +#define JH7100_CLK_AHB_BUS 27 +#define JH7100_CLK_APB1_BUS 28 +#define JH7100_CLK_APB2_BUS 29 +#define JH7100_CLK_DOM3AHB_BUS 30 +#define JH7100_CLK_DOM7AHB_BUS 31 +#define JH7100_CLK_U74_CORE0 32 +#define JH7100_CLK_U74_CORE1 33 +#define JH7100_CLK_U74_AXI 34 +#define JH7100_CLK_U74RTC_TOGGLE 35 +#define JH7100_CLK_SGDMA2P_AXI 36 +#define JH7100_CLK_DMA2PNOC_AXI 37 +#define JH7100_CLK_SGDMA2P_AHB 38 +#define JH7100_CLK_DLA_BUS 39 +#define JH7100_CLK_DLA_AXI 40 +#define JH7100_CLK_DLANOC_AXI 41 +#define JH7100_CLK_DLA_APB 42 +#define JH7100_CLK_VP6_CORE 43 +#define JH7100_CLK_VP6BUS_SRC 44 +#define JH7100_CLK_VP6_AXI 45 +#define JH7100_CLK_VCDECBUS_SRC 46 +#define JH7100_CLK_VDEC_BUS 47 +#define JH7100_CLK_VDEC_AXI 48 +#define JH7100_CLK_VDECBRG_MAIN 49 +#define JH7100_CLK_VDEC_BCLK 50 +#define JH7100_CLK_VDEC_CCLK 51 +#define JH7100_CLK_VDEC_APB 52 +#define JH7100_CLK_JPEG_AXI 53 +#define JH7100_CLK_JPEG_CCLK 54 +#define JH7100_CLK_JPEG_APB 55 +#define JH7100_CLK_GC300_2X 56 +#define JH7100_CLK_GC300_AHB 57 +#define JH7100_CLK_JPCGC300_AXIBUS 58 +#define JH7100_CLK_GC300_AXI 59 +#define JH7100_CLK_JPCGC300_MAIN 60 +#define JH7100_CLK_VENC_BUS 61 +#define JH7100_CLK_VENC_AXI 62 +#define JH7100_CLK_VENCBRG_MAIN 63 +#define JH7100_CLK_VENC_BCLK 64 +#define JH7100_CLK_VENC_CCLK 65 +#define JH7100_CLK_VENC_APB 66 +#define JH7100_CLK_DDRPLL_DIV2 67 +#define JH7100_CLK_DDRPLL_DIV4 68 +#define JH7100_CLK_DDRPLL_DIV8 69 +#define JH7100_CLK_DDROSC_DIV2 70 +#define JH7100_CLK_DDRC0 71 +#define JH7100_CLK_DDRC1 72 +#define JH7100_CLK_DDRPHY_APB 73 +#define JH7100_CLK_NOC_ROB 74 +#define JH7100_CLK_NOC_COG 75 +#define JH7100_CLK_NNE_AHB 76 +#define JH7100_CLK_NNEBUS_SRC1 77 +#define JH7100_CLK_NNE_BUS 78 +#define JH7100_CLK_NNE_AXI 79 +#define JH7100_CLK_NNENOC_AXI 80 +#define JH7100_CLK_DLASLV_AXI 81 +#define JH7100_CLK_DSPX2C_AXI 82 +#define JH7100_CLK_HIFI4_SRC 83 +#define JH7100_CLK_HIFI4_COREFREE 84 +#define JH7100_CLK_HIFI4_CORE 85 +#define JH7100_CLK_HIFI4_BUS 86 +#define JH7100_CLK_HIFI4_AXI 87 +#define JH7100_CLK_HIFI4NOC_AXI 88 +#define JH7100_CLK_SGDMA1P_BUS 89 +#define JH7100_CLK_SGDMA1P_AXI 90 +#define JH7100_CLK_DMA1P_AXI 91 +#define JH7100_CLK_X2C_AXI 92 +#define JH7100_CLK_USB_BUS 93 +#define JH7100_CLK_USB_AXI 94 +#define JH7100_CLK_USBNOC_AXI 95 +#define JH7100_CLK_USBPHY_ROOTDIV 96 +#define JH7100_CLK_USBPHY_125M 97 +#define JH7100_CLK_USBPHY_PLLDIV25M 98 +#define JH7100_CLK_USBPHY_25M 99 +#define JH7100_CLK_AUDIO_DIV 100 +#define JH7100_CLK_AUDIO_SRC 101 +#define JH7100_CLK_AUDIO_12288 102 +#define JH7100_CLK_VIN_SRC 103 +#define JH7100_CLK_ISP0_BUS 104 +#define JH7100_CLK_ISP0_AXI 105 +#define JH7100_CLK_ISP0NOC_AXI 106 +#define JH7100_CLK_ISPSLV_AXI 107 +#define JH7100_CLK_ISP1_BUS 108 +#define JH7100_CLK_ISP1_AXI 109 +#define JH7100_CLK_ISP1NOC_AXI 110 +#define JH7100_CLK_VIN_BUS 111 +#define JH7100_CLK_VIN_AXI 112 +#define JH7100_CLK_VINNOC_AXI 113 +#define JH7100_CLK_VOUT_SRC 114 +#define JH7100_CLK_DISPBUS_SRC 115 +#define JH7100_CLK_DISP_BUS 116 +#define JH7100_CLK_DISP_AXI 117 +#define JH7100_CLK_DISPNOC_AXI 118 +#define JH7100_CLK_SDIO0_AHB 119 +#define JH7100_CLK_SDIO0_CCLKINT 120 +#define JH7100_CLK_SDIO0_CCLKINT_INV 121 +#define JH7100_CLK_SDIO1_AHB 122 +#define JH7100_CLK_SDIO1_CCLKINT 123 +#define JH7100_CLK_SDIO1_CCLKINT_INV 124 +#define JH7100_CLK_GMAC_AHB 125 +#define JH7100_CLK_GMAC_ROOT_DIV 126 +#define JH7100_CLK_GMAC_PTP_REF 127 +#define JH7100_CLK_GMAC_GTX 128 +#define JH7100_CLK_GMAC_RMII_TX 129 +#define JH7100_CLK_GMAC_RMII_RX 130 +#define JH7100_CLK_GMAC_TX 131 +#define JH7100_CLK_GMAC_TX_INV 132 +#define JH7100_CLK_GMAC_RX_PRE 133 +#define JH7100_CLK_GMAC_RX_INV 134 +#define JH7100_CLK_GMAC_RMII 135 +#define JH7100_CLK_GMAC_TOPHYREF 136 +#define JH7100_CLK_SPI2AHB_AHB 137 +#define JH7100_CLK_SPI2AHB_CORE 138 +#define JH7100_CLK_EZMASTER_AHB 139 +#define JH7100_CLK_E24_AHB 140 +#define JH7100_CLK_E24RTC_TOGGLE 141 +#define JH7100_CLK_QSPI_AHB 142 +#define JH7100_CLK_QSPI_APB 143 +#define JH7100_CLK_QSPI_REF 144 +#define JH7100_CLK_SEC_AHB 145 +#define JH7100_CLK_AES 146 +#define JH7100_CLK_SHA 147 +#define JH7100_CLK_PKA 148 +#define JH7100_CLK_TRNG_APB 149 +#define JH7100_CLK_OTP_APB 150 +#define JH7100_CLK_UART0_APB 151 +#define JH7100_CLK_UART0_CORE 152 +#define JH7100_CLK_UART1_APB 153 +#define JH7100_CLK_UART1_CORE 154 +#define JH7100_CLK_SPI0_APB 155 +#define JH7100_CLK_SPI0_CORE 156 +#define JH7100_CLK_SPI1_APB 157 +#define JH7100_CLK_SPI1_CORE 158 +#define JH7100_CLK_I2C0_APB 159 +#define JH7100_CLK_I2C0_CORE 160 +#define JH7100_CLK_I2C1_APB 161 +#define JH7100_CLK_I2C1_CORE 162 +#define JH7100_CLK_GPIO_APB 163 +#define JH7100_CLK_UART2_APB 164 +#define JH7100_CLK_UART2_CORE 165 +#define JH7100_CLK_UART3_APB 166 +#define JH7100_CLK_UART3_CORE 167 +#define JH7100_CLK_SPI2_APB 168 +#define JH7100_CLK_SPI2_CORE 169 +#define JH7100_CLK_SPI3_APB 170 +#define JH7100_CLK_SPI3_CORE 171 +#define JH7100_CLK_I2C2_APB 172 +#define JH7100_CLK_I2C2_CORE 173 +#define JH7100_CLK_I2C3_APB 174 +#define JH7100_CLK_I2C3_CORE 175 +#define JH7100_CLK_WDTIMER_APB 176 +#define JH7100_CLK_WDT_CORE 177 +#define JH7100_CLK_TIMER0_CORE 178 +#define JH7100_CLK_TIMER1_CORE 179 +#define JH7100_CLK_TIMER2_CORE 180 +#define JH7100_CLK_TIMER3_CORE 181 +#define JH7100_CLK_TIMER4_CORE 182 +#define JH7100_CLK_TIMER5_CORE 183 +#define JH7100_CLK_TIMER6_CORE 184 +#define JH7100_CLK_VP6INTC_APB 185 +#define JH7100_CLK_PWM_APB 186 +#define JH7100_CLK_MSI_APB 187 +#define JH7100_CLK_TEMP_APB 188 +#define JH7100_CLK_TEMP_SENSE 189 +#define JH7100_CLK_SYSERR_APB 190 + +#define JH7100_CLK_END 191 + +#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7100_H__ */ |