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-rw-r--r--drivers/clk/Kconfig24
-rw-r--r--drivers/clk/Makefile1
-rw-r--r--drivers/clk/actions/owl-s500.c92
-rw-r--r--drivers/clk/clk-bd718x7.c11
-rw-r--r--drivers/clk/clk-lmk04832.c1599
-rw-r--r--drivers/clk/clk-stm32mp1.c500
-rw-r--r--drivers/clk/ingenic/Kconfig10
-rw-r--r--drivers/clk/ingenic/Makefile1
-rw-r--r--drivers/clk/ingenic/cgu.c92
-rw-r--r--drivers/clk/ingenic/cgu.h12
-rw-r--r--drivers/clk/ingenic/jz4725b-cgu.c12
-rw-r--r--drivers/clk/ingenic/jz4740-cgu.c12
-rw-r--r--drivers/clk/ingenic/jz4760-cgu.c428
-rw-r--r--drivers/clk/ingenic/jz4770-cgu.c15
-rw-r--r--drivers/clk/ingenic/tcu.c2
-rw-r--r--drivers/reset/Kconfig6
-rw-r--r--drivers/reset/Makefile1
-rw-r--r--drivers/reset/reset-stm32mp1.c115
18 files changed, 2625 insertions, 308 deletions
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index ed1364ac376b..e873f9ea2e65 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -51,6 +51,14 @@ config CLK_HSDK
This driver supports the HSDK core, system, ddr, tunnel and hdmi PLLs
control.
+config LMK04832
+ tristate "Ti LMK04832 JESD204B Compliant Clock Jitter Cleaner"
+ depends on SPI
+ select REGMAP_SPI
+ help
+ Say yes here to build support for Texas Instruments' LMK04832 Ultra
+ Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs
+
config COMMON_CLK_MAX77686
tristate "Clock driver for Maxim 77620/77686/77802 MFD"
depends on MFD_MAX77686 || MFD_MAX77620 || COMPILE_TEST
@@ -331,6 +339,16 @@ config COMMON_CLK_STM32MP157
help
Support for stm32mp157 SoC family clocks
+config COMMON_CLK_STM32MP157_SCMI
+ bool "stm32mp157 Clock driver with Trusted Firmware"
+ depends on COMMON_CLK_STM32MP157
+ select COMMON_CLK_SCMI
+ select ARM_SCMI_PROTOCOL
+ default y
+ help
+ Support for stm32mp157 SoC family clocks with Trusted Firmware using
+ SCMI protocol.
+
config COMMON_CLK_STM32F
def_bool COMMON_CLK && (MACH_STM32F429 || MACH_STM32F469 || MACH_STM32F746)
help
@@ -354,10 +372,10 @@ config COMMON_CLK_MMP2_AUDIO
config COMMON_CLK_BD718XX
tristate "Clock driver for 32K clk gates on ROHM PMICs"
- depends on MFD_ROHM_BD718XX || MFD_ROHM_BD70528 || MFD_ROHM_BD71828
+ depends on MFD_ROHM_BD718XX || MFD_ROHM_BD71828
help
- This driver supports ROHM BD71837, ROHM BD71847, ROHM BD71828 and
- ROHM BD70528 PMICs clock gates.
+ This driver supports ROHM BD71837, BD71847, BD71850, BD71815
+ and BD71828 PMICs clock gates.
config COMMON_CLK_FIXED_MMIO
bool "Clock driver for Memory Mapped Fixed values"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 5341c37b62dc..2b91d34c582b 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -36,6 +36,7 @@ obj-$(CONFIG_MACH_ASPEED_G6) += clk-ast2600.o
obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o
obj-$(CONFIG_CLK_HSDK) += clk-hsdk-pll.o
obj-$(CONFIG_COMMON_CLK_K210) += clk-k210.o
+obj-$(CONFIG_LMK04832) += clk-lmk04832.o
obj-$(CONFIG_COMMON_CLK_LOCHNAGAR) += clk-lochnagar.o
obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o
obj-$(CONFIG_COMMON_CLK_MAX9485) += clk-max9485.o
diff --git a/drivers/clk/actions/owl-s500.c b/drivers/clk/actions/owl-s500.c
index 61bb224f6330..57d06e183dff 100644
--- a/drivers/clk/actions/owl-s500.c
+++ b/drivers/clk/actions/owl-s500.c
@@ -113,6 +113,7 @@ static const char * const sensor_clk_mux_p[] = { "hosc", "bisp_clk" };
static const char * const sd_clk_mux_p[] = { "dev_clk", "nand_pll_clk" };
static const char * const pwm_clk_mux_p[] = { "losc", "hosc" };
static const char * const ahbprediv_clk_mux_p[] = { "dev_clk", "display_pll_clk", "nand_pll_clk", "ddr_pll_clk" };
+static const char * const nic_clk_mux_p[] = { "dev_clk", "display_pll_clk", "nand_pll_clk", "ddr_pll_clk" };
static const char * const uart_clk_mux_p[] = { "hosc", "dev_pll_clk" };
static const char * const de_clk_mux_p[] = { "display_pll_clk", "dev_clk" };
static const char * const i2s_clk_mux_p[] = { "audio_pll_clk" };
@@ -127,8 +128,7 @@ static struct clk_factor_table sd_factor_table[] = {
{ 12, 1, 13 }, { 13, 1, 14 }, { 14, 1, 15 }, { 15, 1, 16 },
{ 16, 1, 17 }, { 17, 1, 18 }, { 18, 1, 19 }, { 19, 1, 20 },
{ 20, 1, 21 }, { 21, 1, 22 }, { 22, 1, 23 }, { 23, 1, 24 },
- { 24, 1, 25 }, { 25, 1, 26 }, { 26, 1, 27 }, { 27, 1, 28 },
- { 28, 1, 29 }, { 29, 1, 30 }, { 30, 1, 31 }, { 31, 1, 32 },
+ { 24, 1, 25 },
/* bit8: /128 */
{ 256, 1, 1 * 128 }, { 257, 1, 2 * 128 }, { 258, 1, 3 * 128 }, { 259, 1, 4 * 128 },
@@ -137,19 +137,20 @@ static struct clk_factor_table sd_factor_table[] = {
{ 268, 1, 13 * 128 }, { 269, 1, 14 * 128 }, { 270, 1, 15 * 128 }, { 271, 1, 16 * 128 },
{ 272, 1, 17 * 128 }, { 273, 1, 18 * 128 }, { 274, 1, 19 * 128 }, { 275, 1, 20 * 128 },
{ 276, 1, 21 * 128 }, { 277, 1, 22 * 128 }, { 278, 1, 23 * 128 }, { 279, 1, 24 * 128 },
- { 280, 1, 25 * 128 }, { 281, 1, 26 * 128 }, { 282, 1, 27 * 128 }, { 283, 1, 28 * 128 },
- { 284, 1, 29 * 128 }, { 285, 1, 30 * 128 }, { 286, 1, 31 * 128 }, { 287, 1, 32 * 128 },
+ { 280, 1, 25 * 128 },
{ 0, 0, 0 },
};
-static struct clk_factor_table bisp_factor_table[] = {
- { 0, 1, 1 }, { 1, 1, 2 }, { 2, 1, 3 }, { 3, 1, 4 },
- { 4, 1, 5 }, { 5, 1, 6 }, { 6, 1, 7 }, { 7, 1, 8 },
+static struct clk_factor_table de_factor_table[] = {
+ { 0, 1, 1 }, { 1, 2, 3 }, { 2, 1, 2 }, { 3, 2, 5 },
+ { 4, 1, 3 }, { 5, 1, 4 }, { 6, 1, 6 }, { 7, 1, 8 },
+ { 8, 1, 12 },
{ 0, 0, 0 },
};
-static struct clk_factor_table ahb_factor_table[] = {
- { 1, 1, 2 }, { 2, 1, 3 },
+static struct clk_factor_table hde_factor_table[] = {
+ { 0, 1, 1 }, { 1, 2, 3 }, { 2, 1, 2 }, { 3, 2, 5 },
+ { 4, 1, 3 }, { 5, 1, 4 }, { 6, 1, 6 }, { 7, 1, 8 },
{ 0, 0, 0 },
};
@@ -158,6 +159,13 @@ static struct clk_div_table rmii_ref_div_table[] = {
{ 0, 0 },
};
+static struct clk_div_table std12rate_div_table[] = {
+ { 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 },
+ { 4, 5 }, { 5, 6 }, { 6, 7 }, { 7, 8 },
+ { 8, 9 }, { 9, 10 }, { 10, 11 }, { 11, 12 },
+ { 0, 0 },
+};
+
static struct clk_div_table i2s_div_table[] = {
{ 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 },
{ 4, 6 }, { 5, 8 }, { 6, 12 }, { 7, 16 },
@@ -174,7 +182,6 @@ static struct clk_div_table nand_div_table[] = {
/* mux clock */
static OWL_MUX(dev_clk, "dev_clk", dev_clk_mux_p, CMU_DEVPLL, 12, 1, CLK_SET_RATE_PARENT);
-static OWL_MUX(ahbprediv_clk, "ahbprediv_clk", ahbprediv_clk_mux_p, CMU_BUSCLK1, 8, 3, CLK_SET_RATE_PARENT);
/* gate clocks */
static OWL_GATE(gpio_clk, "gpio_clk", "apb_clk", CMU_DEVCLKEN0, 18, 0, 0);
@@ -187,45 +194,60 @@ static OWL_GATE(timer_clk, "timer_clk", "hosc", CMU_DEVCLKEN1, 27, 0, 0);
static OWL_GATE(hdmi_clk, "hdmi_clk", "hosc", CMU_DEVCLKEN1, 3, 0, 0);
/* divider clocks */
-static OWL_DIVIDER(h_clk, "h_clk", "ahbprediv_clk", CMU_BUSCLK1, 12, 2, NULL, 0, 0);
-static OWL_DIVIDER(apb_clk, "apb_clk", "ahb_clk", CMU_BUSCLK1, 14, 2, NULL, 0, 0);
+static OWL_DIVIDER(h_clk, "h_clk", "ahbprediv_clk", CMU_BUSCLK1, 2, 2, NULL, 0, 0);
+static OWL_DIVIDER(apb_clk, "apb_clk", "nic_clk", CMU_BUSCLK1, 14, 2, NULL, 0, 0);
static OWL_DIVIDER(rmii_ref_clk, "rmii_ref_clk", "ethernet_pll_clk", CMU_ETHERNETPLL, 1, 1, rmii_ref_div_table, 0, 0);
/* factor clocks */
-static OWL_FACTOR(ahb_clk, "ahb_clk", "h_clk", CMU_BUSCLK1, 2, 2, ahb_factor_table, 0, 0);
-static OWL_FACTOR(de1_clk, "de_clk1", "de_clk", CMU_DECLK, 0, 3, bisp_factor_table, 0, 0);
-static OWL_FACTOR(de2_clk, "de_clk2", "de_clk", CMU_DECLK, 4, 3, bisp_factor_table, 0, 0);
+static OWL_FACTOR(de1_clk, "de_clk1", "de_clk", CMU_DECLK, 0, 4, de_factor_table, 0, 0);
+static OWL_FACTOR(de2_clk, "de_clk2", "de_clk", CMU_DECLK, 4, 4, de_factor_table, 0, 0);
/* composite clocks */
+static OWL_COMP_DIV(nic_clk, "nic_clk", nic_clk_mux_p,
+ OWL_MUX_HW(CMU_BUSCLK1, 4, 3),
+ { 0 },
+ OWL_DIVIDER_HW(CMU_BUSCLK1, 16, 2, 0, NULL),
+ 0);
+
+static OWL_COMP_DIV(ahbprediv_clk, "ahbprediv_clk", ahbprediv_clk_mux_p,
+ OWL_MUX_HW(CMU_BUSCLK1, 8, 3),
+ { 0 },
+ OWL_DIVIDER_HW(CMU_BUSCLK1, 12, 2, 0, NULL),
+ CLK_SET_RATE_PARENT);
+
+static OWL_COMP_FIXED_FACTOR(ahb_clk, "ahb_clk", "h_clk",
+ { 0 },
+ 1, 1, 0);
+
static OWL_COMP_FACTOR(vce_clk, "vce_clk", hde_clk_mux_p,
OWL_MUX_HW(CMU_VCECLK, 4, 2),
OWL_GATE_HW(CMU_DEVCLKEN0, 26, 0),
- OWL_FACTOR_HW(CMU_VCECLK, 0, 3, 0, bisp_factor_table),
+ OWL_FACTOR_HW(CMU_VCECLK, 0, 3, 0, hde_factor_table),
0);
static OWL_COMP_FACTOR(vde_clk, "vde_clk", hde_clk_mux_p,
OWL_MUX_HW(CMU_VDECLK, 4, 2),
OWL_GATE_HW(CMU_DEVCLKEN0, 25, 0),
- OWL_FACTOR_HW(CMU_VDECLK, 0, 3, 0, bisp_factor_table),
+ OWL_FACTOR_HW(CMU_VDECLK, 0, 3, 0, hde_factor_table),
0);
-static OWL_COMP_FACTOR(bisp_clk, "bisp_clk", bisp_clk_mux_p,
+static OWL_COMP_DIV(bisp_clk, "bisp_clk", bisp_clk_mux_p,
OWL_MUX_HW(CMU_BISPCLK, 4, 1),
OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0),
- OWL_FACTOR_HW(CMU_BISPCLK, 0, 3, 0, bisp_factor_table),
+ OWL_DIVIDER_HW(CMU_BISPCLK, 0, 4, 0, std12rate_div_table),
0);
-static OWL_COMP_FACTOR(sensor0_clk, "sensor0_clk", sensor_clk_mux_p,
+static OWL_COMP_DIV(sensor0_clk, "sensor0_clk", sensor_clk_mux_p,
OWL_MUX_HW(CMU_SENSORCLK, 4, 1),
OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0),
- OWL_FACTOR_HW(CMU_SENSORCLK, 0, 3, 0, bisp_factor_table),
- CLK_IGNORE_UNUSED);
+ OWL_DIVIDER_HW(CMU_SENSORCLK, 0, 4, 0, std12rate_div_table),
+ 0);
-static OWL_COMP_FACTOR(sensor1_clk, "sensor1_clk", sensor_clk_mux_p,
+static OWL_COMP_DIV(sensor1_clk, "sensor1_clk", sensor_clk_mux_p,
OWL_MUX_HW(CMU_SENSORCLK, 4, 1),
OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0),
- OWL_FACTOR_HW(CMU_SENSORCLK, 8, 3, 0, bisp_factor_table),
- CLK_IGNORE_UNUSED);
+ OWL_DIVIDER_HW(CMU_SENSORCLK, 8, 4, 0, std12rate_div_table),
+ 0);
static OWL_COMP_FACTOR(sd0_clk, "sd0_clk", sd_clk_mux_p,
OWL_MUX_HW(CMU_SD0CLK, 9, 1),
@@ -302,10 +324,14 @@ static OWL_COMP_FIXED_FACTOR(i2c3_clk, "i2c3_clk", "ethernet_pll_clk",
OWL_GATE_HW(CMU_DEVCLKEN1, 31, 0),
1, 5, 0);
+static OWL_COMP_FIXED_FACTOR(ethernet_clk, "ethernet_clk", "ethernet_pll_clk",
+ OWL_GATE_HW(CMU_DEVCLKEN1, 22, 0),
+ 1, 20, 0);
+
static OWL_COMP_DIV(uart0_clk, "uart0_clk", uart_clk_mux_p,
OWL_MUX_HW(CMU_UART0CLK, 16, 1),
OWL_GATE_HW(CMU_DEVCLKEN1, 6, 0),
- OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
+ OWL_DIVIDER_HW(CMU_UART0CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
CLK_IGNORE_UNUSED);
static OWL_COMP_DIV(uart1_clk, "uart1_clk", uart_clk_mux_p,
@@ -317,31 +343,31 @@ static OWL_COMP_DIV(uart1_clk, "uart1_clk", uart_clk_mux_p,
static OWL_COMP_DIV(uart2_clk, "uart2_clk", uart_clk_mux_p,
OWL_MUX_HW(CMU_UART2CLK, 16, 1),
OWL_GATE_HW(CMU_DEVCLKEN1, 8, 0),
- OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
+ OWL_DIVIDER_HW(CMU_UART2CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
CLK_IGNORE_UNUSED);
static OWL_COMP_DIV(uart3_clk, "uart3_clk", uart_clk_mux_p,
OWL_MUX_HW(CMU_UART3CLK, 16, 1),
OWL_GATE_HW(CMU_DEVCLKEN1, 19, 0),
- OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
+ OWL_DIVIDER_HW(CMU_UART3CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
CLK_IGNORE_UNUSED);
static OWL_COMP_DIV(uart4_clk, "uart4_clk", uart_clk_mux_p,
OWL_MUX_HW(CMU_UART4CLK, 16, 1),
OWL_GATE_HW(CMU_DEVCLKEN1, 20, 0),
- OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
+ OWL_DIVIDER_HW(CMU_UART4CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
CLK_IGNORE_UNUSED);
static OWL_COMP_DIV(uart5_clk, "uart5_clk", uart_clk_mux_p,
OWL_MUX_HW(CMU_UART5CLK, 16, 1),
OWL_GATE_HW(CMU_DEVCLKEN1, 21, 0),
- OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
+ OWL_DIVIDER_HW(CMU_UART5CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
CLK_IGNORE_UNUSED);
static OWL_COMP_DIV(uart6_clk, "uart6_clk", uart_clk_mux_p,
OWL_MUX_HW(CMU_UART6CLK, 16, 1),
OWL_GATE_HW(CMU_DEVCLKEN1, 18, 0),
- OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
+ OWL_DIVIDER_HW(CMU_UART6CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
CLK_IGNORE_UNUSED);
static OWL_COMP_DIV(i2srx_clk, "i2srx_clk", i2s_clk_mux_p,
@@ -436,6 +462,8 @@ static struct owl_clk_common *s500_clks[] = {
&apb_clk.common,
&dmac_clk.common,
&gpio_clk.common,
+ &nic_clk.common,
+ &ethernet_clk.common,
};
static struct clk_hw_onecell_data s500_hw_clks = {
@@ -495,6 +523,8 @@ static struct clk_hw_onecell_data s500_hw_clks = {
[CLK_APB] = &apb_clk.common.hw,
[CLK_DMAC] = &dmac_clk.common.hw,
[CLK_GPIO] = &gpio_clk.common.hw,
+ [CLK_NIC] = &nic_clk.common.hw,
+ [CLK_ETHERNET] = &ethernet_clk.common.hw,
},
.num = CLK_NR_CLKS,
};
diff --git a/drivers/clk/clk-bd718x7.c b/drivers/clk/clk-bd718x7.c
index d9e70e506d18..ac40b669d60b 100644
--- a/drivers/clk/clk-bd718x7.c
+++ b/drivers/clk/clk-bd718x7.c
@@ -15,15 +15,13 @@
/* clk control registers */
/* BD71815 */
#define BD71815_REG_OUT32K 0x1d
-/* BD70528 */
-#define BD70528_REG_OUT32K 0x2c
/* BD71828 */
#define BD71828_REG_OUT32K 0x4B
/* BD71837 and BD71847 */
#define BD718XX_REG_OUT32K 0x2E
/*
- * BD71837, BD71847, BD70528 and BD71828 all use bit [0] to clk output control
+ * BD71837, BD71847, and BD71828 all use bit [0] to clk output control
*/
#define CLK_OUT_EN_MASK BIT(0)
@@ -116,10 +114,6 @@ static int bd71837_clk_probe(struct platform_device *pdev)
c->reg = BD71828_REG_OUT32K;
c->mask = CLK_OUT_EN_MASK;
break;
- case ROHM_CHIP_TYPE_BD70528:
- c->reg = BD70528_REG_OUT32K;
- c->mask = CLK_OUT_EN_MASK;
- break;
case ROHM_CHIP_TYPE_BD71815:
c->reg = BD71815_REG_OUT32K;
c->mask = CLK_OUT_EN_MASK;
@@ -150,7 +144,6 @@ static int bd71837_clk_probe(struct platform_device *pdev)
static const struct platform_device_id bd718x7_clk_id[] = {
{ "bd71837-clk", ROHM_CHIP_TYPE_BD71837 },
{ "bd71847-clk", ROHM_CHIP_TYPE_BD71847 },
- { "bd70528-clk", ROHM_CHIP_TYPE_BD70528 },
{ "bd71828-clk", ROHM_CHIP_TYPE_BD71828 },
{ "bd71815-clk", ROHM_CHIP_TYPE_BD71815 },
{ },
@@ -168,6 +161,6 @@ static struct platform_driver bd71837_clk = {
module_platform_driver(bd71837_clk);
MODULE_AUTHOR("Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>");
-MODULE_DESCRIPTION("BD718(15/18/28/37/47/50) and BD70528 chip clk driver");
+MODULE_DESCRIPTION("BD718(15/18/28/37/47/50) and chip clk driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:bd718xx-clk");
diff --git a/drivers/clk/clk-lmk04832.c b/drivers/clk/clk-lmk04832.c
new file mode 100644
index 000000000000..c1095e733220
--- /dev/null
+++ b/drivers/clk/clk-lmk04832.c
@@ -0,0 +1,1599 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * LMK04832 Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner
+ * Pin compatible with the LMK0482x family
+ *
+ * Datasheet: https://www.ti.com/lit/ds/symlink/lmk04832.pdf
+ *
+ * Copyright (c) 2020, Xiphos Systems Corp.
+ *
+ */
+
+#include <linux/bitfield.h>
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/debugfs.h>
+#include <linux/device.h>
+#include <linux/gcd.h>
+#include <linux/gpio/consumer.h>
+#include <linux/module.h>
+#include <linux/uaccess.h>
+#include <linux/regmap.h>
+#include <linux/spi/spi.h>
+
+/* 0x000 - 0x00d System Functions */
+#define LMK04832_REG_RST3W 0x000
+#define LMK04832_BIT_RESET BIT(7)
+#define LMK04832_BIT_SPI_3WIRE_DIS BIT(4)
+#define LMK04832_REG_POWERDOWN 0x002
+#define LMK04832_REG_ID_DEV_TYPE 0x003
+#define LMK04832_REG_ID_PROD_MSB 0x004
+#define LMK04832_REG_ID_PROD_LSB 0x005
+#define LMK04832_REG_ID_MASKREV 0x006
+#define LMK04832_REG_ID_VNDR_MSB 0x00c
+#define LMK04832_REG_ID_VNDR_LSB 0x00d
+
+/* 0x100 - 0x137 Device Clock and SYSREF Clock Output Control */
+#define LMK04832_REG_CLKOUT_CTRL0(ch) (0x100 + (ch >> 1) * 8)
+#define LMK04832_BIT_DCLK_DIV_LSB GENMASK(7, 0)
+#define LMK04832_REG_CLKOUT_CTRL1(ch) (0x101 + (ch >> 1) * 8)
+#define LMK04832_BIT_DCLKX_Y_DDLY_LSB GENMASK(7, 0)
+#define LMK04832_REG_CLKOUT_CTRL2(ch) (0x102 + (ch >> 1) * 8)
+#define LMK04832_BIT_CLKOUTX_Y_PD BIT(7)
+#define LMK04832_BIT_DCLKX_Y_DDLY_PD BIT(4)
+#define LMK04832_BIT_DCLKX_Y_DDLY_MSB GENMASK(3, 2)
+#define LMK04832_BIT_DCLK_DIV_MSB GENMASK(1, 0)
+#define LMK04832_REG_CLKOUT_SRC_MUX(ch) (0x103 + (ch % 2) + (ch >> 1) * 8)
+#define LMK04832_BIT_CLKOUT_SRC_MUX BIT(5)
+#define LMK04832_REG_CLKOUT_CTRL3(ch) (0x103 + (ch >> 1) * 8)
+#define LMK04832_BIT_DCLKX_Y_PD BIT(4)
+#define LMK04832_BIT_DCLKX_Y_DCC BIT(2)
+#define LMK04832_BIT_DCLKX_Y_HS BIT(0)
+#define LMK04832_REG_CLKOUT_CTRL4(ch) (0x104 + (ch >> 1) * 8)
+#define LMK04832_BIT_SCLK_PD BIT(4)
+#define LMK04832_BIT_SCLKX_Y_DIS_MODE GENMASK(3, 2)
+#define LMK04832_REG_SCLKX_Y_ADLY(ch) (0x105 + (ch >> 1) * 8)
+#define LMK04832_REG_SCLKX_Y_DDLY(ch) (0x106 + (ch >> 1) * 8)
+#define LMK04832_BIT_SCLKX_Y_DDLY GENMASK(3, 0)
+#define LMK04832_REG_CLKOUT_FMT(ch) (0x107 + (ch >> 1) * 8)
+#define LMK04832_BIT_CLKOUT_FMT(ch) (ch % 2 ? 0xf0 : 0x0f)
+#define LMK04832_VAL_CLKOUT_FMT_POWERDOWN 0x00
+#define LMK04832_VAL_CLKOUT_FMT_LVDS 0x01
+#define LMK04832_VAL_CLKOUT_FMT_HSDS6 0x02
+#define LMK04832_VAL_CLKOUT_FMT_HSDS8 0x03
+#define LMK04832_VAL_CLKOUT_FMT_LVPECL1600 0x04
+#define LMK04832_VAL_CLKOUT_FMT_LVPECL2000 0x05
+#define LMK04832_VAL_CLKOUT_FMT_LCPECL 0x06
+#define LMK04832_VAL_CLKOUT_FMT_CML16 0x07
+#define LMK04832_VAL_CLKOUT_FMT_CML24 0x08
+#define LMK04832_VAL_CLKOUT_FMT_CML32 0x09
+#define LMK04832_VAL_CLKOUT_FMT_CMOS_OFF_INV 0x0a
+#define LMK04832_VAL_CLKOUT_FMT_CMOS_NOR_OFF 0x0b
+#define LMK04832_VAL_CLKOUT_FMT_CMOS_INV_INV 0x0c
+#define LMK04832_VAL_CLKOUT_FMT_CMOS_INV_NOR 0x0d
+#define LMK04832_VAL_CLKOUT_FMT_CMOS_NOR_INV 0x0e
+#define LMK04832_VAL_CLKOUT_FMT_CMOS_NOR_NOR 0x0f
+
+/* 0x138 - 0x145 SYSREF, SYNC, and Device Config */
+#define LMK04832_REG_VCO_OSCOUT 0x138
+#define LMK04832_BIT_VCO_MUX GENMASK(6, 5)
+#define LMK04832_VAL_VCO_MUX_VCO0 0x00
+#define LMK04832_VAL_VCO_MUX_VCO1 0x01
+#define LMK04832_VAL_VCO_MUX_EXT 0x02
+#define LMK04832_REG_SYSREF_OUT 0x139
+#define LMK04832_BIT_SYSREF_REQ_EN BIT(6)
+#define LMK04832_BIT_SYSREF_MUX GENMASK(1, 0)
+#define LMK04832_VAL_SYSREF_MUX_NORMAL_SYNC 0x00
+#define LMK04832_VAL_SYSREF_MUX_RECLK 0x01
+#define LMK04832_VAL_SYSREF_MUX_PULSER 0x02
+#define LMK04832_VAL_SYSREF_MUX_CONTINUOUS 0x03
+#define LMK04832_REG_SYSREF_DIV_MSB 0x13a
+#define LMK04832_BIT_SYSREF_DIV_MSB GENMASK(4, 0)
+#define LMK04832_REG_SYSREF_DIV_LSB 0x13b
+#define LMK04832_REG_SYSREF_DDLY_MSB 0x13c
+#define LMK04832_BIT_SYSREF_DDLY_MSB GENMASK(4, 0)
+#define LMK04832_REG_SYSREF_DDLY_LSB 0x13d
+#define LMK04832_REG_SYSREF_PULSE_CNT 0x13e
+#define LMK04832_REG_FB_CTRL 0x13f
+#define LMK04832_BIT_PLL2_RCLK_MUX BIT(7)
+#define LMK04832_VAL_PLL2_RCLK_MUX_OSCIN 0x00
+#define LMK04832_VAL_PLL2_RCLK_MUX_CLKIN 0x01
+#define LMK04832_BIT_PLL2_NCLK_MUX BIT(5)
+#define LMK04832_VAL_PLL2_NCLK_MUX_PLL2_P 0x00
+#define LMK04832_VAL_PLL2_NCLK_MUX_FB_MUX 0x01
+#define LMK04832_BIT_FB_MUX_EN BIT(0)
+#define LMK04832_REG_MAIN_PD 0x140
+#define LMK04832_BIT_PLL1_PD BIT(7)
+#define LMK04832_BIT_VCO_LDO_PD BIT(6)
+#define LMK04832_BIT_VCO_PD BIT(5)
+#define LMK04832_BIT_OSCIN_PD BIT(4)
+#define LMK04832_BIT_SYSREF_GBL_PD BIT(3)
+#define LMK04832_BIT_SYSREF_PD BIT(2)
+#define LMK04832_BIT_SYSREF_DDLY_PD BIT(1)
+#define LMK04832_BIT_SYSREF_PLSR_PD BIT(0)
+#define LMK04832_REG_SYNC 0x143
+#define LMK04832_BIT_SYNC_CLR BIT(7)
+#define LMK04832_BIT_SYNC_1SHOT_EN BIT(6)
+#define LMK04832_BIT_SYNC_POL BIT(5)
+#define LMK04832_BIT_SYNC_EN BIT(4)
+#define LMK04832_BIT_SYNC_MODE GENMASK(1, 0)
+#define LMK04832_VAL_SYNC_MODE_OFF 0x00
+#define LMK04832_VAL_SYNC_MODE_ON 0x01
+#define LMK04832_VAL_SYNC_MODE_PULSER_PIN 0x02
+#define LMK04832_VAL_SYNC_MODE_PULSER_SPI 0x03
+#define LMK04832_REG_SYNC_DIS 0x144
+
+/* 0x146 - 0x14a CLKin Control */
+#define LMK04832_REG_CLKIN_SEL0 0x148
+#define LMK04832_REG_CLKIN_SEL1 0x149
+#define LMK04832_REG_CLKIN_RST 0x14a
+#define LMK04832_BIT_SDIO_RDBK_TYPE BIT(6)
+#define LMK04832_BIT_CLKIN_SEL_MUX GENMASK(5, 3)
+#define LMK04832_VAL_CLKIN_SEL_MUX_SPI_RDBK 0x06
+#define LMK04832_BIT_CLKIN_SEL_TYPE GENMASK(2, 0)
+#define LMK04832_VAL_CLKIN_SEL_TYPE_OUT 0x03
+
+/* 0x14b - 0x152 Holdover */
+
+/* 0x153 - 0x15f PLL1 Configuration */
+
+/* 0x160 - 0x16e PLL2 Configuration */
+#define LMK04832_REG_PLL2_R_MSB 0x160
+#define LMK04832_BIT_PLL2_R_MSB GENMASK(3, 0)
+#define LMK04832_REG_PLL2_R_LSB 0x161
+#define LMK04832_REG_PLL2_MISC 0x162
+#define LMK04832_BIT_PLL2_MISC_P GENMASK(7, 5)
+#define LMK04832_BIT_PLL2_MISC_REF_2X_EN BIT(0)
+#define LMK04832_REG_PLL2_N_CAL_0 0x163
+#define LMK04832_BIT_PLL2_N_CAL_0 GENMASK(1, 0)
+#define LMK04832_REG_PLL2_N_CAL_1 0x164
+#define LMK04832_REG_PLL2_N_CAL_2 0x165
+#define LMK04832_REG_PLL2_N_0 0x166
+#define LMK04832_BIT_PLL2_N_0 GENMASK(1, 0)
+#define LMK04832_REG_PLL2_N_1 0x167
+#define LMK04832_REG_PLL2_N_2 0x168
+#define LMK04832_REG_PLL2_DLD_CNT_MSB 0x16a
+#define LMK04832_REG_PLL2_DLD_CNT_LSB 0x16b
+#define LMK04832_REG_PLL2_LD 0x16e
+#define LMK04832_BIT_PLL2_LD_MUX GENMASK(7, 3)
+#define LMK04832_VAL_PLL2_LD_MUX_PLL2_DLD 0x02
+#define LMK04832_BIT_PLL2_LD_TYPE GENMASK(2, 0)
+#define LMK04832_VAL_PLL2_LD_TYPE_OUT_PP 0x03
+
+/* 0x16F - 0x555 Misc Registers */
+#define LMK04832_REG_PLL2_PD 0x173
+#define LMK04832_BIT_PLL2_PRE_PD BIT(6)
+#define LMK04832_BIT_PLL2_PD BIT(5)
+#define LMK04832_REG_PLL1R_RST 0x177
+#define LMK04832_REG_CLR_PLL_LOST 0x182
+#define LMK04832_REG_RB_PLL_LD 0x183
+#define LMK04832_REG_RB_CLK_DAC_VAL_MSB 0x184
+#define LMK04832_REG_RB_DAC_VAL_LSB 0x185
+#define LMK04832_REG_RB_HOLDOVER 0x188
+#define LMK04832_REG_SPI_LOCK 0x555
+
+enum lmk04832_device_types {
+ LMK04832,
+};
+
+/**
+ * lmk04832_device_info - Holds static device information that is specific to
+ * the chip revision
+ *
+ * pid: Product Identifier
+ * maskrev: IC version identifier
+ * num_channels: Number of available output channels (clkout count)
+ * vco0_range: {min, max} of the VCO0 operating range (in MHz)
+ * vco1_range: {min, max} of the VCO1 operating range (in MHz)
+ */
+struct lmk04832_device_info {
+ u16 pid;
+ u8 maskrev;
+ size_t num_channels;
+ unsigned int vco0_range[2];
+ unsigned int vco1_range[2];
+};
+
+static const struct lmk04832_device_info lmk04832_device_info[] = {
+ [LMK04832] = {
+ .pid = 0x63d1, /* WARNING PROD_ID is inverted in the datasheet */
+ .maskrev = 0x70,
+ .num_channels = 14,
+ .vco0_range = { 2440, 2580 },
+ .vco1_range = { 2945, 3255 },
+ },
+};
+
+enum lmk04832_rdbk_type {
+ RDBK_CLKIN_SEL0,
+ RDBK_CLKIN_SEL1,
+ RDBK_RESET,
+};
+
+struct lmk_dclk {
+ struct lmk04832 *lmk;
+ struct clk_hw hw;
+ u8 id;
+};
+
+struct lmk_clkout {
+ struct lmk04832 *lmk;
+ struct clk_hw hw;
+ bool sysref;
+ u32 format;
+ u8 id;
+};
+
+/**
+ * struct lmk04832 - The LMK04832 device structure
+ *
+ * @dev: reference to a struct device, linked to the spi_device
+ * @regmap: struct regmap instance use to access the chip
+ * @sync_mode: operational mode for SYNC signal
+ * @sysref_mux: select SYSREF source
+ * @sysref_pulse_cnt: number of SYSREF pulses generated while not in continuous
+ * mode.
+ * @sysref_ddly: SYSREF digital delay value
+ * @oscin: PLL2 input clock
+ * @vco: reference to the internal VCO clock
+ * @sclk: reference to the internal sysref clock (SCLK)
+ * @vco_rate: user provided VCO rate
+ * @reset_gpio: reference to the reset GPIO
+ * @dclk: list of internal device clock references.
+ * Each pair of clkout clocks share a single device clock (DCLKX_Y)
+ * @clkout: list of output clock references
+ * @clk_data: holds clkout related data like clk_hw* and number of clocks
+ */
+struct lmk04832 {
+ struct device *dev;
+ struct regmap *regmap;
+
+ unsigned int sync_mode;
+ unsigned int sysref_mux;
+ unsigned int sysref_pulse_cnt;
+ unsigned int sysref_ddly;
+
+ struct clk *oscin;
+ struct clk_hw vco;
+ struct clk_hw sclk;
+ unsigned int vco_rate;
+
+ struct gpio_desc *reset_gpio;
+
+ struct lmk_dclk *dclk;
+ struct lmk_clkout *clkout;
+ struct clk_hw_onecell_data *clk_data;
+};
+
+static bool lmk04832_regmap_rd_regs(struct device *dev, unsigned int reg)
+{
+ switch (reg) {
+ case LMK04832_REG_RST3W ... LMK04832_REG_ID_MASKREV:
+ fallthrough;
+ case LMK04832_REG_ID_VNDR_MSB:
+ fallthrough;
+ case LMK04832_REG_ID_VNDR_LSB:
+ fallthrough;
+ case LMK04832_REG_CLKOUT_CTRL0(0) ... LMK04832_REG_PLL2_DLD_CNT_LSB:
+ fallthrough;
+ case LMK04832_REG_PLL2_LD:
+ fallthrough;
+ case LMK04832_REG_PLL2_PD:
+ fallthrough;
+ case LMK04832_REG_PLL1R_RST:
+ fallthrough;
+ case LMK04832_REG_CLR_PLL_LOST ... LMK04832_REG_RB_DAC_VAL_LSB:
+ fallthrough;
+ case LMK04832_REG_RB_HOLDOVER:
+ fallthrough;
+ case LMK04832_REG_SPI_LOCK:
+ return true;
+ default:
+ return false;
+ };
+};
+
+static bool lmk04832_regmap_wr_regs(struct device *dev, unsigned int reg)
+{
+ switch (reg) {
+ case LMK04832_REG_RST3W:
+ fallthrough;
+ case LMK04832_REG_POWERDOWN:
+ return true;
+ case LMK04832_REG_ID_DEV_TYPE ... LMK04832_REG_ID_MASKREV:
+ fallthrough;
+ case LMK04832_REG_ID_VNDR_MSB:
+ fallthrough;
+ case LMK04832_REG_ID_VNDR_LSB:
+ return false;
+ case LMK04832_REG_CLKOUT_CTRL0(0) ... LMK04832_REG_PLL2_DLD_CNT_LSB:
+ fallthrough;
+ case LMK04832_REG_PLL2_LD:
+ fallthrough;
+ case LMK04832_REG_PLL2_PD:
+ fallthrough;
+ case LMK04832_REG_PLL1R_RST:
+ fallthrough;
+ case LMK04832_REG_CLR_PLL_LOST ... LMK04832_REG_RB_DAC_VAL_LSB:
+ fallthrough;
+ case LMK04832_REG_RB_HOLDOVER:
+ fallthrough;
+ case LMK04832_REG_SPI_LOCK:
+ return true;
+ default:
+ return false;
+ };
+};
+
+static const struct regmap_config regmap_config = {
+ .name = "lmk04832",
+ .reg_bits = 16,
+ .val_bits = 8,
+ .use_single_read = 1,
+ .use_single_write = 1,
+ .read_flag_mask = 0x80,
+ .write_flag_mask = 0x00,
+ .readable_reg = lmk04832_regmap_rd_regs,
+ .writeable_reg = lmk04832_regmap_wr_regs,
+ .cache_type = REGCACHE_NONE,
+ .max_register = LMK04832_REG_SPI_LOCK,
+};
+
+static int lmk04832_vco_is_enabled(struct clk_hw *hw)
+{
+ struct lmk04832 *lmk = container_of(hw, struct lmk04832, vco);
+ unsigned int tmp;
+ int ret;
+
+ ret = regmap_read(lmk->regmap, LMK04832_REG_MAIN_PD, &tmp);
+ if (ret)
+ return ret;
+
+ return !(FIELD_GET(LMK04832_BIT_OSCIN_PD, tmp) |
+ FIELD_GET(LMK04832_BIT_VCO_PD, tmp) |
+ FIELD_GET(LMK04832_BIT_VCO_LDO_PD, tmp));
+}
+
+static int lmk04832_vco_prepare(struct clk_hw *hw)
+{
+ struct lmk04832 *lmk = container_of(hw, struct lmk04832, vco);
+ int ret;
+
+ ret = regmap_update_bits(lmk->regmap, LMK04832_REG_PLL2_PD,
+ LMK04832_BIT_PLL2_PRE_PD |
+ LMK04832_BIT_PLL2_PD,
+ 0x00);
+ if (ret)
+ return ret;
+
+ return regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD,
+ LMK04832_BIT_VCO_LDO_PD |
+ LMK04832_BIT_VCO_PD |
+ LMK04832_BIT_OSCIN_PD, 0x00);
+}
+
+static void lmk04832_vco_unprepare(struct clk_hw *hw)
+{
+ struct lmk04832 *lmk = container_of(hw, struct lmk04832, vco);
+
+ regmap_update_bits(lmk->regmap, LMK04832_REG_PLL2_PD,
+ LMK04832_BIT_PLL2_PRE_PD | LMK04832_BIT_PLL2_PD,
+ 0xff);
+
+ /* Don't set LMK04832_BIT_OSCIN_PD since other clocks depend on it */
+ regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD,
+ LMK04832_BIT_VCO_LDO_PD | LMK04832_BIT_VCO_PD, 0xff);
+}
+
+static unsigned long lmk04832_vco_recalc_rate(struct clk_hw *hw,
+ unsigned long prate)
+{
+ struct lmk04832 *lmk = container_of(hw, struct lmk04832, vco);
+ unsigned int pll2_p[] = {8, 2, 2, 3, 4, 5, 6, 7};
+ unsigned int pll2_n, p, pll2_r;
+ unsigned int pll2_misc;
+ unsigned long vco_rate;
+ u8 tmp[3];
+ int ret;
+
+ ret = regmap_read(lmk->regmap, LMK04832_REG_PLL2_MISC, &pll2_misc);
+ if (ret)
+ return ret;
+
+ p = FIELD_GET(LMK04832_BIT_PLL2_MISC_P, pll2_misc);
+
+ ret = regmap_bulk_read(lmk->regmap, LMK04832_REG_PLL2_N_0, &tmp, 3);
+ if (ret)
+ return ret;
+
+ pll2_n = FIELD_PREP(0x030000, tmp[0]) |
+ FIELD_PREP(0x00ff00, tmp[1]) |
+ FIELD_PREP(0x0000ff, tmp[2]);
+
+ ret = regmap_bulk_read(lmk->regmap, LMK04832_REG_PLL2_R_MSB, &tmp, 2);
+ if (ret)
+ return ret;
+
+ pll2_r = FIELD_PREP(0x0f00, tmp[0]) |
+ FIELD_PREP(0x00ff, tmp[1]);
+
+ vco_rate = (prate << FIELD_GET(LMK04832_BIT_PLL2_MISC_REF_2X_EN,
+ pll2_misc)) * pll2_n * pll2_p[p] / pll2_r;
+
+ return vco_rate;
+};
+
+/**
+ * lmk04832_check_vco_ranges - Check requested VCO frequency against VCO ranges
+ *
+ * @lmk: Reference to the lmk device
+ * @rate: Desired output rate for the VCO
+ *
+ * The LMK04832 has 2 internal VCO, each with independent operating ranges.
+ * Use the device_info structure to determine which VCO to use based on rate.
+ *
+ * Returns VCO_MUX value or negative errno.
+ */
+static int lmk04832_check_vco_ranges(struct lmk04832 *lmk, unsigned long rate)
+{
+ struct spi_device *spi = to_spi_device(lmk->dev);
+ const struct lmk04832_device_info *info;
+ unsigned long mhz = rate / 1000000;
+
+ info = &lmk04832_device_info[spi_get_device_id(spi)->driver_data];
+
+ if (mhz >= info->vco0_range[0] && mhz <= info->vco0_range[1])
+ return LMK04832_VAL_VCO_MUX_VCO0;
+
+ if (mhz >= info->vco1_range[0] && mhz <= info->vco1_range[1])
+ return LMK04832_VAL_VCO_MUX_VCO1;
+
+ dev_err(lmk->dev, "%lu Hz is out of VCO ranges\n", rate);
+ return -ERANGE;
+}
+
+/**
+ * lmk04832_calc_pll2_params - Get PLL2 parameters used to set the VCO frequency
+ *
+ * @prate: parent rate to the PLL2, usually OSCin
+ * @rate: Desired output rate for the VCO
+ * @n: reference to PLL2_N
+ * @p: reference to PLL2_P
+ * @r: reference to PLL2_R
+ *
+ * This functions assumes LMK04832_BIT_PLL2_MISC_REF_2X_EN is set since it is
+ * recommended in the datasheet because a higher phase detector frequencies
+ * makes the design of wider loop bandwidth filters possible.
+ *
+ * the VCO rate can be calculated using the following expression:
+ *
+ * VCO = OSCin * 2 * PLL2_N * PLL2_P / PLL2_R
+ *
+ * Returns vco rate or negative errno.
+ */
+static long lmk04832_calc_pll2_params(unsigned long prate, unsigned long rate,
+ unsigned int *n, unsigned int *p,
+ unsigned int *r)
+{
+ unsigned int pll2_n, pll2_p, pll2_r;
+ unsigned long num, div;
+
+ /* Set PLL2_P to a fixed value to simplify optimizations */
+ pll2_p = 2;
+
+ div = gcd(rate, prate);
+
+ num = DIV_ROUND_CLOSEST(rate, div);
+ pll2_r = DIV_ROUND_CLOSEST(prate, div);
+
+ if (num > 4) {
+ pll2_n = num >> 2;
+ } else {
+ pll2_r = pll2_r << 2;
+ pll2_n = num;
+ }
+
+ if (pll2_n < 1 || pll2_n > 0x03ffff)
+ return -EINVAL;
+ if (pll2_r < 1 || pll2_r > 0xfff)
+ return -EINVAL;
+
+ *n = pll2_n;
+ *p = pll2_p;
+ *r = pll2_r;
+
+ return DIV_ROUND_CLOSEST(prate * 2 * pll2_p * pll2_n, pll2_r);
+}
+
+static long lmk04832_vco_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+ struct lmk04832 *lmk = container_of(hw, struct lmk04832, vco);
+ unsigned int n, p, r;
+ long vco_rate;
+ int ret;
+
+ ret = lmk04832_check_vco_ranges(lmk, rate);
+ if (ret < 0)
+ return ret;
+
+ vco_rate = lmk04832_calc_pll2_params(*prate, rate, &n, &p, &r);
+ if (vco_rate < 0) {
+ dev_err(lmk->dev, "PLL2 parmeters out of range\n");
+ return vco_rate;
+ }
+
+ if (rate != vco_rate)
+ return -EINVAL;
+
+ return vco_rate;
+};
+
+static int lmk04832_vco_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long prate)
+{
+ struct lmk04832 *lmk = container_of(hw, struct lmk04832, vco);
+ unsigned int n, p, r;
+ long vco_rate;
+ int vco_mux;
+ int ret;
+
+ vco_mux = lmk04832_check_vco_ranges(lmk, rate);
+ if (vco_mux < 0)
+ return vco_mux;
+
+ ret = regmap_update_bits(lmk->regmap, LMK04832_REG_VCO_OSCOUT,
+ LMK04832_BIT_VCO_MUX,
+ FIELD_PREP(LMK04832_BIT_VCO_MUX, vco_mux));
+ if (ret)
+ return ret;
+
+ vco_rate = lmk04832_calc_pll2_params(prate, rate, &n, &p, &r);
+ if (vco_rate < 0) {
+ dev_err(lmk->dev, "failed to determine PLL2 parmeters\n");
+ return vco_rate;
+ }
+
+ ret = regmap_update_bits(lmk->regmap, LMK04832_REG_PLL2_R_MSB,
+ LMK04832_BIT_PLL2_R_MSB,
+ FIELD_GET(0x000700, r));
+ if (ret)
+ return ret;
+
+ ret = regmap_write(lmk->regmap, LMK04832_REG_PLL2_R_LSB,
+ FIELD_GET(0x0000ff, r));
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(lmk->regmap, LMK04832_REG_PLL2_MISC,
+ LMK04832_BIT_PLL2_MISC_P,
+ FIELD_PREP(LMK04832_BIT_PLL2_MISC_P, p));
+ if (ret)
+ return ret;
+
+ /*
+ * PLL2_N registers must be programmed after other PLL2 dividers are
+ * programed to ensure proper VCO frequency calibration
+ */
+ ret = regmap_write(lmk->regmap, LMK04832_REG_PLL2_N_0,
+ FIELD_GET(0x030000, n));
+ if (ret)
+ return ret;
+ ret = regmap_write(lmk->regmap, LMK04832_REG_PLL2_N_1,
+ FIELD_GET(0x00ff00, n));
+ if (ret)
+ return ret;
+
+ return regmap_write(lmk->regmap, LMK04832_REG_PLL2_N_2,
+ FIELD_GET(0x0000ff, n));
+};
+
+static const struct clk_ops lmk04832_vco_ops = {
+ .is_enabled = lmk04832_vco_is_enabled,
+ .prepare = lmk04832_vco_prepare,
+ .unprepare = lmk04832_vco_unprepare,
+ .recalc_rate = lmk04832_vco_recalc_rate,
+ .round_rate = lmk04832_vco_round_rate,
+ .set_rate = lmk04832_vco_set_rate,
+};
+
+/*
+ * lmk04832_register_vco - Initialize the internal VCO and clock distribution
+ * path in PLL2 single loop mode.
+ */
+static int lmk04832_register_vco(struct lmk04832 *lmk)
+{
+ const char *parent_names[1];
+ struct clk_init_data init;
+ int ret;
+
+ init.name = "lmk-vco";
+ parent_names[0] = __clk_get_name(lmk->oscin);
+ init.parent_names = parent_names;
+
+ init.ops = &lmk04832_vco_ops;
+ init.num_parents = 1;
+
+ ret = regmap_update_bits(lmk->regmap, LMK04832_REG_VCO_OSCOUT,
+ LMK04832_BIT_VCO_MUX,
+ FIELD_PREP(LMK04832_BIT_VCO_MUX,
+ LMK04832_VAL_VCO_MUX_VCO1));
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(lmk->regmap, LMK04832_REG_FB_CTRL,
+ LMK04832_BIT_PLL2_RCLK_MUX |
+ LMK04832_BIT_PLL2_NCLK_MUX,
+ FIELD_PREP(LMK04832_BIT_PLL2_RCLK_MUX,
+ LMK04832_VAL_PLL2_RCLK_MUX_OSCIN)|
+ FIELD_PREP(LMK04832_BIT_PLL2_NCLK_MUX,
+ LMK04832_VAL_PLL2_NCLK_MUX_PLL2_P));
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(lmk->regmap, LMK04832_REG_PLL2_MISC,
+ LMK04832_BIT_PLL2_MISC_REF_2X_EN,
+ LMK04832_BIT_PLL2_MISC_REF_2X_EN);
+ if (ret)
+ return ret;
+
+ ret = regmap_write(lmk->regmap, LMK04832_REG_PLL2_LD,
+ FIELD_PREP(LMK04832_BIT_PLL2_LD_MUX,
+ LMK04832_VAL_PLL2_LD_MUX_PLL2_DLD) |
+ FIELD_PREP(LMK04832_BIT_PLL2_LD_TYPE,
+ LMK04832_VAL_PLL2_LD_TYPE_OUT_PP));
+ if (ret)
+ return ret;
+
+ lmk->vco.init = &init;
+ return devm_clk_hw_register(lmk->dev, &lmk->vco);
+}
+
+static int lmk04832_clkout_set_ddly(struct lmk04832 *lmk, int id)
+{
+ int dclk_div_adj[] = {0, 0, -2, -2, 0, 3, -1, 0};
+ unsigned int sclkx_y_ddly = 10;
+ unsigned int dclkx_y_ddly;
+ unsigned int dclkx_y_div;
+ unsigned int sysref_ddly;
+ unsigned int dclkx_y_hs;
+ unsigned int lsb, msb;
+ int ret;
+
+ ret = regmap_update_bits(lmk->regmap,
+ LMK04832_REG_CLKOUT_CTRL2(id),
+ LMK04832_BIT_DCLKX_Y_DDLY_PD,
+ FIELD_PREP(LMK04832_BIT_DCLKX_Y_DDLY_PD, 0));
+ if (ret)
+ return ret;
+
+ ret = regmap_read(lmk->regmap, LMK04832_REG_SYSREF_DDLY_LSB, &lsb);
+ if (ret)
+ return ret;
+
+ ret = regmap_read(lmk->regmap, LMK04832_REG_SYSREF_DDLY_MSB, &msb);
+ if (ret)
+ return ret;
+
+ sysref_ddly = FIELD_GET(LMK04832_BIT_SYSREF_DDLY_MSB, msb) << 8 | lsb;
+
+ ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL0(id), &lsb);
+ if (ret)
+ return ret;
+
+ ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL2(id), &msb);
+ if (ret)
+ return ret;
+
+ dclkx_y_div = FIELD_GET(LMK04832_BIT_DCLK_DIV_MSB, msb) << 8 | lsb;
+
+ ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL3(id), &lsb);
+ if (ret)
+ return ret;
+
+ dclkx_y_hs = FIELD_GET(LMK04832_BIT_DCLKX_Y_HS, lsb);
+
+ dclkx_y_ddly = sysref_ddly + 1 -
+ dclk_div_adj[dclkx_y_div < 6 ? dclkx_y_div : 7] -
+ dclkx_y_hs + sclkx_y_ddly;
+
+ if (dclkx_y_ddly < 7 || dclkx_y_ddly > 0x3fff) {
+ dev_err(lmk->dev, "DCLKX_Y_DDLY out of range (%d)\n",
+ dclkx_y_ddly);
+ return -EINVAL;
+ }
+
+ ret = regmap_write(lmk->regmap,
+ LMK04832_REG_SCLKX_Y_DDLY(id),
+ FIELD_GET(LMK04832_BIT_SCLKX_Y_DDLY, sclkx_y_ddly));
+ if (ret)
+ return ret;
+
+ ret = regmap_write(lmk->regmap, LMK04832_REG_CLKOUT_CTRL1(id),
+ FIELD_GET(0x00ff, dclkx_y_ddly));
+ if (ret)
+ return ret;
+
+ dev_dbg(lmk->dev, "clkout%02u: sysref_ddly=%u, dclkx_y_ddly=%u, "
+ "dclk_div_adj=%+d, dclkx_y_hs=%u, sclkx_y_ddly=%u\n",
+ id, sysref_ddly, dclkx_y_ddly,
+ dclk_div_adj[dclkx_y_div < 6 ? dclkx_y_div : 7],
+ dclkx_y_hs, sclkx_y_ddly);
+
+ return regmap_update_bits(lmk->regmap, LMK04832_REG_CLKOUT_CTRL2(id),
+ LMK04832_BIT_DCLKX_Y_DDLY_MSB,
+ FIELD_GET(0x0300, dclkx_y_ddly));
+}
+
+/** lmk04832_sclk_sync - Establish deterministic phase relationship between sclk
+ * and dclk
+ *
+ * @lmk: Reference to the lmk device
+ *
+ * The synchronization sequence:
+ * - in the datasheet https://www.ti.com/lit/ds/symlink/lmk04832.pdf, p.31
+ * (8.3.3.1 How to enable SYSREF)
+ * - Ti forum: https://e2e.ti.com/support/clock-and-timing/f/48/t/970972
+ *
+ * Returns 0 or negative errno.
+ */
+static int lmk04832_sclk_sync_sequence(struct lmk04832 *lmk)
+{
+ int ret;
+ int i;
+
+ /* 1. (optional) mute all sysref_outputs during synchronization */
+ /* 2. Enable and write device clock digital delay to applicable clocks */
+ ret = regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD,
+ LMK04832_BIT_SYSREF_DDLY_PD,
+ FIELD_PREP(LMK04832_BIT_SYSREF_DDLY_PD, 0));
+ if (ret)
+ return ret;
+
+ for (i = 0; i < lmk->clk_data->num; i += 2) {
+ ret = lmk04832_clkout_set_ddly(lmk, i);
+ if (ret)
+ return ret;
+ }
+
+ /*
+ * 3. Configure SYNC_MODE to SYNC_PIN and SYSREF_MUX to Normal SYNC,
+ * and clear SYSREF_REQ_EN (see 6.)
+ */
+ ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYSREF_OUT,
+ LMK04832_BIT_SYSREF_REQ_EN |
+ LMK04832_BIT_SYSREF_MUX,
+ FIELD_PREP(LMK04832_BIT_SYSREF_REQ_EN, 0) |
+ FIELD_PREP(LMK04832_BIT_SYSREF_MUX,
+ LMK04832_VAL_SYSREF_MUX_NORMAL_SYNC));
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC,
+ LMK04832_BIT_SYNC_MODE,
+ FIELD_PREP(LMK04832_BIT_SYNC_MODE,
+ LMK04832_VAL_SYNC_MODE_ON));
+ if (ret)
+ return ret;
+
+ /* 4. Clear SYNXC_DISx or applicable clocks and clear SYNC_DISSYSREF */
+ ret = regmap_write(lmk->regmap, LMK04832_REG_SYNC_DIS, 0x00);
+ if (ret)
+ return ret;
+
+ /*
+ * 5. If SCLKX_Y_DDLY != 0, Set SYSREF_CLR=1 for at least 15 clock
+ * distribution path cycles (VCO cycles), then back to 0. In
+ * PLL2-only use case, this will be complete in less than one SPI
+ * transaction. If SYSREF local digital delay is not used, this step
+ * can be skipped.
+ */
+ ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC,
+ LMK04832_BIT_SYNC_CLR,
+ FIELD_PREP(LMK04832_BIT_SYNC_CLR, 0x01));
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC,
+ LMK04832_BIT_SYNC_CLR,
+ FIELD_PREP(LMK04832_BIT_SYNC_CLR, 0x00));
+ if (ret)
+ return ret;
+
+ /*
+ * 6. Toggle SYNC_POL state between inverted and not inverted.
+ * If you use an external signal on the SYNC pin instead of toggling
+ * SYNC_POL, make sure that SYSREF_REQ_EN=0 so that the SYSREF_MUX
+ * does not shift into continuous SYSREF mode.
+ */
+ ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC,
+ LMK04832_BIT_SYNC_POL,
+ FIELD_PREP(LMK04832_BIT_SYNC_POL, 0x01));
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC,
+ LMK04832_BIT_SYNC_POL,
+ FIELD_PREP(LMK04832_BIT_SYNC_POL, 0x00));
+ if (ret)
+ return ret;
+
+ /* 7. Set all SYNC_DISx=1, including SYNC_DISSYSREF */
+ ret = regmap_write(lmk->regmap, LMK04832_REG_SYNC_DIS, 0xff);
+ if (ret)
+ return ret;
+
+ /* 8. Restore state of SYNC_MODE and SYSREF_MUX to desired values */
+ ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYSREF_OUT,
+ LMK04832_BIT_SYSREF_MUX,
+ FIELD_PREP(LMK04832_BIT_SYSREF_MUX,
+ lmk->sysref_mux));
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC,
+ LMK04832_BIT_SYNC_MODE,
+ FIELD_PREP(LMK04832_BIT_SYNC_MODE,
+ lmk->sync_mode));
+ if (ret)
+ return ret;
+
+ /*
+ * 9. (optional) if SCLKx_y_DIS_MODE was used to mute SYSREF outputs
+ * during the SYNC event, restore SCLKx_y_DIS_MODE=0 for active state,
+ * or set SYSREF_GBL_PD=0 if SCLKx_y_DIS_MODE is set to a conditional
+ * option.
+ */
+
+ /*
+ * 10. (optional) To reduce power consumption, after the synchronization
+ * event is complete, DCLKx_y_DDLY_PD=1 and SYSREF_DDLY_PD=1 disable the
+ * digital delay counters (which are only used immediately after the
+ * SYNC pulse to delay the output by some number of VCO counts).
+ */
+
+ return ret;
+}
+
+static int lmk04832_sclk_is_enabled(struct clk_hw *hw)
+{
+ struct lmk04832 *lmk = container_of(hw, struct lmk04832, sclk);
+ unsigned int tmp;
+ int ret;
+
+ ret = regmap_read(lmk->regmap, LMK04832_REG_MAIN_PD, &tmp);
+ if (ret)
+ return ret;
+
+ return FIELD_GET(LMK04832_BIT_SYSREF_PD, tmp);
+}
+
+static int lmk04832_sclk_prepare(struct clk_hw *hw)
+{
+ struct lmk04832 *lmk = container_of(hw, struct lmk04832, sclk);
+
+ return regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD,
+ LMK04832_BIT_SYSREF_PD, 0x00);
+}
+
+static void lmk04832_sclk_unprepare(struct clk_hw *hw)
+{
+ struct lmk04832 *lmk = container_of(hw, struct lmk04832, sclk);
+
+ regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD,
+ LMK04832_BIT_SYSREF_PD, LMK04832_BIT_SYSREF_PD);
+}
+
+static unsigned long lmk04832_sclk_recalc_rate(struct clk_hw *hw,
+ unsigned long prate)
+{
+ struct lmk04832 *lmk = container_of(hw, struct lmk04832, sclk);
+ unsigned int sysref_div;
+ u8 tmp[2];
+ int ret;
+
+ ret = regmap_bulk_read(lmk->regmap, LMK04832_REG_SYSREF_DIV_MSB, &tmp, 2);
+ if (ret)
+ return ret;
+
+ sysref_div = FIELD_GET(LMK04832_BIT_SYSREF_DIV_MSB, tmp[0]) << 8 |
+ tmp[1];
+
+ return DIV_ROUND_CLOSEST(prate, sysref_div);
+}
+
+static long lmk04832_sclk_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+ struct lmk04832 *lmk = container_of(hw, struct lmk04832, sclk);
+ unsigned long sclk_rate;
+ unsigned int sysref_div;
+
+ sysref_div = DIV_ROUND_CLOSEST(*prate, rate);
+ sclk_rate = DIV_ROUND_CLOSEST(*prate, sysref_div);
+
+ if (sysref_div < 0x07 || sysref_div > 0x1fff) {
+ dev_err(lmk->dev, "SYSREF divider out of range\n");
+ return -EINVAL;
+ }
+
+ if (rate != sclk_rate)
+ return -EINVAL;
+
+ return sclk_rate;
+}
+
+static int lmk04832_sclk_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long prate)
+{
+ struct lmk04832 *lmk = container_of(hw, struct lmk04832, sclk);
+ unsigned int sysref_div;
+ int ret;
+
+ sysref_div = DIV_ROUND_CLOSEST(prate, rate);
+
+ if (sysref_div < 0x07 || sysref_div > 0x1fff) {
+ dev_err(lmk->dev, "SYSREF divider out of range\n");
+ return -EINVAL;
+ }
+
+ ret = regmap_write(lmk->regmap, LMK04832_REG_SYSREF_DIV_MSB,
+ FIELD_GET(0x1f00, sysref_div));
+ if (ret)
+ return ret;
+
+ ret = regmap_write(lmk->regmap, LMK04832_REG_SYSREF_DIV_LSB,
+ FIELD_GET(0x00ff, sysref_div));
+ if (ret)
+ return ret;
+
+ ret = lmk04832_sclk_sync_sequence(lmk);
+ if (ret)
+ dev_err(lmk->dev, "SYNC sequence failed\n");
+
+ return ret;
+}
+
+static const struct clk_ops lmk04832_sclk_ops = {
+ .is_enabled = lmk04832_sclk_is_enabled,
+ .prepare = lmk04832_sclk_prepare,
+ .unprepare = lmk04832_sclk_unprepare,
+ .recalc_rate = lmk04832_sclk_recalc_rate,
+ .round_rate = lmk04832_sclk_round_rate,
+ .set_rate = lmk04832_sclk_set_rate,
+};
+
+static int lmk04832_register_sclk(struct lmk04832 *lmk)
+{
+ const char *parent_names[1];
+ struct clk_init_data init;
+ int ret;
+
+ init.name = "lmk-sclk";
+ parent_names[0] = clk_hw_get_name(&lmk->vco);
+ init.parent_names = parent_names;
+
+ init.ops = &lmk04832_sclk_ops;
+ init.flags = CLK_SET_RATE_PARENT;
+ init.num_parents = 1;
+
+ ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYSREF_OUT,
+ LMK04832_BIT_SYSREF_MUX,
+ FIELD_PREP(LMK04832_BIT_SYSREF_MUX,
+ lmk->sysref_mux));
+ if (ret)
+ return ret;
+
+ ret = regmap_write(lmk->regmap, LMK04832_REG_SYSREF_DDLY_LSB,
+ FIELD_GET(0x00ff, lmk->sysref_ddly));
+ if (ret)
+ return ret;
+
+ ret = regmap_write(lmk->regmap, LMK04832_REG_SYSREF_DDLY_MSB,
+ FIELD_GET(0x1f00, lmk->sysref_ddly));
+ if (ret)
+ return ret;
+
+ ret = regmap_write(lmk->regmap, LMK04832_REG_SYSREF_PULSE_CNT,
+ ilog2(lmk->sysref_pulse_cnt));
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD,
+ LMK04832_BIT_SYSREF_DDLY_PD |
+ LMK04832_BIT_SYSREF_PLSR_PD,
+ FIELD_PREP(LMK04832_BIT_SYSREF_DDLY_PD, 0) |
+ FIELD_PREP(LMK04832_BIT_SYSREF_PLSR_PD, 0));
+ if (ret)
+ return ret;
+
+ ret = regmap_write(lmk->regmap, LMK04832_REG_SYNC,
+ FIELD_PREP(LMK04832_BIT_SYNC_POL, 0) |
+ FIELD_PREP(LMK04832_BIT_SYNC_EN, 1) |
+ FIELD_PREP(LMK04832_BIT_SYNC_MODE, lmk->sync_mode));
+ if (ret)
+ return ret;
+
+ ret = regmap_write(lmk->regmap, LMK04832_REG_SYNC_DIS, 0xff);
+ if (ret)
+ return ret;
+
+ lmk->sclk.init = &init;
+ return devm_clk_hw_register(lmk->dev, &lmk->sclk);
+}
+
+static int lmk04832_dclk_is_enabled(struct clk_hw *hw)
+{
+ struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw);
+ struct lmk04832 *lmk = dclk->lmk;
+ unsigned int tmp;
+ int ret;
+
+ ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL3(dclk->id),
+ &tmp);
+ if (ret)
+ return ret;
+
+ return !FIELD_GET(LMK04832_BIT_DCLKX_Y_PD, tmp);
+}
+
+static int lmk04832_dclk_prepare(struct clk_hw *hw)
+{
+ struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw);
+ struct lmk04832 *lmk = dclk->lmk;
+
+ return regmap_update_bits(lmk->regmap,
+ LMK04832_REG_CLKOUT_CTRL3(dclk->id),
+ LMK04832_BIT_DCLKX_Y_PD, 0x00);
+}
+
+static void lmk04832_dclk_unprepare(struct clk_hw *hw)
+{
+ struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw);
+ struct lmk04832 *lmk = dclk->lmk;
+
+ regmap_update_bits(lmk->regmap,
+ LMK04832_REG_CLKOUT_CTRL3(dclk->id),
+ LMK04832_BIT_DCLKX_Y_PD, 0xff);
+}
+
+static unsigned long lmk04832_dclk_recalc_rate(struct clk_hw *hw,
+ unsigned long prate)
+{
+ struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw);
+ struct lmk04832 *lmk = dclk->lmk;
+ unsigned int dclk_div;
+ unsigned int lsb, msb;
+ unsigned long rate;
+ int ret;
+
+ ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL0(dclk->id),
+ &lsb);
+ if (ret)
+ return ret;
+
+ ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL2(dclk->id),
+ &msb);
+ if (ret)
+ return ret;
+
+ dclk_div = FIELD_GET(LMK04832_BIT_DCLK_DIV_MSB, msb) << 8 | lsb;
+ rate = DIV_ROUND_CLOSEST(prate, dclk_div);
+
+ return rate;
+};
+
+static long lmk04832_dclk_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+ struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw);
+ struct lmk04832 *lmk = dclk->lmk;
+ unsigned long dclk_rate;
+ unsigned int dclk_div;
+
+ dclk_div = DIV_ROUND_CLOSEST(*prate, rate);
+ dclk_rate = DIV_ROUND_CLOSEST(*prate, dclk_div);
+
+ if (dclk_div < 1 || dclk_div > 0x3ff) {
+ dev_err(lmk->dev, "%s_div out of range\n", clk_hw_get_name(hw));
+ return -EINVAL;
+ }
+
+ if (rate != dclk_rate)
+ return -EINVAL;
+
+ return dclk_rate;
+};
+
+static int lmk04832_dclk_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long prate)
+{
+ struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw);
+ struct lmk04832 *lmk = dclk->lmk;
+ unsigned int dclk_div;
+ int ret;
+
+ dclk_div = DIV_ROUND_CLOSEST(prate, rate);
+
+ if (dclk_div > 0x3ff) {
+ dev_err(lmk->dev, "%s_div out of range\n", clk_hw_get_name(hw));
+ return -EINVAL;
+ }
+
+ /* Enable Duty Cycle Corretion */
+ if (dclk_div == 1) {
+ ret = regmap_update_bits(lmk->regmap,
+ LMK04832_REG_CLKOUT_CTRL3(dclk->id),
+ LMK04832_BIT_DCLKX_Y_DCC,
+ FIELD_PREP(LMK04832_BIT_DCLKX_Y_DCC, 1));
+ if (ret)
+ return ret;
+ }
+
+ /*
+ * While using Divide-by-2 or Divide-by-3 for DCLK_X_Y_DIV, SYNC
+ * procedure requires to first program Divide-by-4 and then back to
+ * Divide-by-2 or Divide-by-3 before doing SYNC.
+ */
+ if (dclk_div == 2 || dclk_div == 3) {
+ ret = regmap_update_bits(lmk->regmap,
+ LMK04832_REG_CLKOUT_CTRL2(dclk->id),
+ LMK04832_BIT_DCLK_DIV_MSB, 0x00);
+ if (ret)
+ return ret;
+
+ ret = regmap_write(lmk->regmap,
+ LMK04832_REG_CLKOUT_CTRL0(dclk->id), 0x04);
+ if (ret)
+ return ret;
+ }
+
+ ret = regmap_write(lmk->regmap, LMK04832_REG_CLKOUT_CTRL0(dclk->id),
+ FIELD_GET(0x0ff, dclk_div));
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(lmk->regmap,
+ LMK04832_REG_CLKOUT_CTRL2(dclk->id),
+ LMK04832_BIT_DCLK_DIV_MSB,
+ FIELD_GET(0x300, dclk_div));
+ if (ret)
+ return ret;
+
+ ret = lmk04832_sclk_sync_sequence(lmk);
+ if (ret)
+ dev_err(lmk->dev, "SYNC sequence failed\n");
+
+ return ret;
+};
+
+static const struct clk_ops lmk04832_dclk_ops = {
+ .is_enabled = lmk04832_dclk_is_enabled,
+ .prepare = lmk04832_dclk_prepare,
+ .unprepare = lmk04832_dclk_unprepare,
+ .recalc_rate = lmk04832_dclk_recalc_rate,
+ .round_rate = lmk04832_dclk_round_rate,
+ .set_rate = lmk04832_dclk_set_rate,
+};
+
+static int lmk04832_clkout_is_enabled(struct clk_hw *hw)
+{
+ struct lmk_clkout *clkout = container_of(hw, struct lmk_clkout, hw);
+ struct lmk04832 *lmk = clkout->lmk;
+ unsigned int clkoutx_y_pd;
+ unsigned int sclkx_y_pd;
+ unsigned int tmp;
+ u32 enabled;
+ int ret;
+ u8 fmt;
+
+ ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL2(clkout->id),
+ &clkoutx_y_pd);
+ if (ret)
+ return ret;
+
+ enabled = !FIELD_GET(LMK04832_BIT_CLKOUTX_Y_PD, clkoutx_y_pd);
+
+ ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_SRC_MUX(clkout->id),
+ &tmp);
+ if (ret)
+ return ret;
+
+ if (FIELD_GET(LMK04832_BIT_CLKOUT_SRC_MUX, tmp)) {
+ ret = regmap_read(lmk->regmap,
+ LMK04832_REG_CLKOUT_CTRL4(clkout->id),
+ &sclkx_y_pd);
+ if (ret)
+ return ret;
+
+ enabled = enabled && !FIELD_GET(LMK04832_BIT_SCLK_PD, sclkx_y_pd);
+ }
+
+ ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_FMT(clkout->id),
+ &tmp);
+ if (ret)
+ return ret;
+
+ if (clkout->id % 2)
+ fmt = FIELD_GET(0xf0, tmp);
+ else
+ fmt = FIELD_GET(0x0f, tmp);
+
+ return enabled && !fmt;
+}
+
+static int lmk04832_clkout_prepare(struct clk_hw *hw)
+{
+ struct lmk_clkout *clkout = container_of(hw, struct lmk_clkout, hw);
+ struct lmk04832 *lmk = clkout->lmk;
+ unsigned int tmp;
+ int ret;
+
+ if (clkout->format == LMK04832_VAL_CLKOUT_FMT_POWERDOWN)
+ dev_err(lmk->dev, "prepared %s but format is powerdown\n",
+ clk_hw_get_name(hw));
+
+ ret = regmap_update_bits(lmk->regmap,
+ LMK04832_REG_CLKOUT_CTRL2(clkout->id),
+ LMK04832_BIT_CLKOUTX_Y_PD, 0x00);
+ if (ret)
+ return ret;
+
+ ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_SRC_MUX(clkout->id),
+ &tmp);
+ if (ret)
+ return ret;
+
+ if (FIELD_GET(LMK04832_BIT_CLKOUT_SRC_MUX, tmp)) {
+ ret = regmap_update_bits(lmk->regmap,
+ LMK04832_REG_CLKOUT_CTRL4(clkout->id),
+ LMK04832_BIT_SCLK_PD, 0x00);
+ if (ret)
+ return ret;
+ }
+
+ return regmap_update_bits(lmk->regmap,
+ LMK04832_REG_CLKOUT_FMT(clkout->id),
+ LMK04832_BIT_CLKOUT_FMT(clkout->id),
+ clkout->format << 4 * (clkout->id % 2));
+}
+
+static void lmk04832_clkout_unprepare(struct clk_hw *hw)
+{
+ struct lmk_clkout *clkout = container_of(hw, struct lmk_clkout, hw);
+ struct lmk04832 *lmk = clkout->lmk;
+
+ regmap_update_bits(lmk->regmap, LMK04832_REG_CLKOUT_FMT(clkout->id),
+ LMK04832_BIT_CLKOUT_FMT(clkout->id),
+ 0x00);
+}
+
+static int lmk04832_clkout_set_parent(struct clk_hw *hw, uint8_t index)
+{
+ struct lmk_clkout *clkout = container_of(hw, struct lmk_clkout, hw);
+ struct lmk04832 *lmk = clkout->lmk;
+
+ return regmap_update_bits(lmk->regmap,
+ LMK04832_REG_CLKOUT_SRC_MUX(clkout->id),
+ LMK04832_BIT_CLKOUT_SRC_MUX,
+ FIELD_PREP(LMK04832_BIT_CLKOUT_SRC_MUX,
+ index));
+}
+
+static uint8_t lmk04832_clkout_get_parent(struct clk_hw *hw)
+{
+ struct lmk_clkout *clkout = container_of(hw, struct lmk_clkout, hw);
+ struct lmk04832 *lmk = clkout->lmk;
+ unsigned int tmp;
+ int ret;
+
+ ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_SRC_MUX(clkout->id),
+ &tmp);
+ if (ret)
+ return ret;
+
+ return FIELD_GET(LMK04832_BIT_CLKOUT_SRC_MUX, tmp);
+}
+
+static const struct clk_ops lmk04832_clkout_ops = {
+ .is_enabled = lmk04832_clkout_is_enabled,
+ .prepare = lmk04832_clkout_prepare,
+ .unprepare = lmk04832_clkout_unprepare,
+ .set_parent = lmk04832_clkout_set_parent,
+ .get_parent = lmk04832_clkout_get_parent,
+};
+
+static int lmk04832_register_clkout(struct lmk04832 *lmk, const int num)
+{
+ char name[] = "lmk-clkoutXX";
+ char dclk_name[] = "lmk-dclkXX_YY";
+ const char *parent_names[2];
+ struct clk_init_data init;
+ int dclk_num = num / 2;
+ int ret;
+
+ if (num % 2 == 0) {
+ sprintf(dclk_name, "lmk-dclk%02d_%02d", num, num + 1);
+ init.name = dclk_name;
+ parent_names[0] = clk_hw_get_name(&lmk->vco);
+ init.ops = &lmk04832_dclk_ops;
+ init.flags = CLK_SET_RATE_PARENT;
+ init.num_parents = 1;
+
+ lmk->dclk[dclk_num].id = num;
+ lmk->dclk[dclk_num].lmk = lmk;
+ lmk->dclk[dclk_num].hw.init = &init;
+
+ ret = devm_clk_hw_register(lmk->dev, &lmk->dclk[dclk_num].hw);
+ if (ret)
+ return ret;
+ } else {
+ sprintf(dclk_name, "lmk-dclk%02d_%02d", num - 1, num);
+ }
+
+ if (of_property_read_string_index(lmk->dev->of_node,
+ "clock-output-names",
+ num, &init.name)) {
+ sprintf(name, "lmk-clkout%02d", num);
+ init.name = name;
+ }
+
+ parent_names[0] = dclk_name;
+ parent_names[1] = clk_hw_get_name(&lmk->sclk);
+ init.parent_names = parent_names;
+ init.ops = &lmk04832_clkout_ops;
+ init.flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT;
+ init.num_parents = ARRAY_SIZE(parent_names);
+
+ lmk->clkout[num].id = num;
+ lmk->clkout[num].lmk = lmk;
+ lmk->clkout[num].hw.init = &init;
+ lmk->clk_data->hws[num] = &lmk->clkout[num].hw;
+
+ /* Set initial parent */
+ regmap_update_bits(lmk->regmap,
+ LMK04832_REG_CLKOUT_SRC_MUX(num),
+ LMK04832_BIT_CLKOUT_SRC_MUX,
+ FIELD_PREP(LMK04832_BIT_CLKOUT_SRC_MUX,
+ lmk->clkout[num].sysref));
+
+ return devm_clk_hw_register(lmk->dev, &lmk->clkout[num].hw);
+}
+
+static int lmk04832_set_spi_rdbk(const struct lmk04832 *lmk, const int rdbk_pin)
+{
+ int reg;
+ int ret;
+
+ dev_info(lmk->dev, "setting up 4-wire mode\n");
+ ret = regmap_write(lmk->regmap, LMK04832_REG_RST3W,
+ LMK04832_BIT_SPI_3WIRE_DIS);
+ if (ret)
+ return ret;
+
+ switch (rdbk_pin) {
+ case RDBK_CLKIN_SEL0:
+ reg = LMK04832_REG_CLKIN_SEL0;
+ break;
+ case RDBK_CLKIN_SEL1:
+ reg = LMK04832_REG_CLKIN_SEL1;
+ break;
+ case RDBK_RESET:
+ reg = LMK04832_REG_CLKIN_RST;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return regmap_write(lmk->regmap, reg,
+ FIELD_PREP(LMK04832_BIT_CLKIN_SEL_MUX,
+ LMK04832_VAL_CLKIN_SEL_MUX_SPI_RDBK) |
+ FIELD_PREP(LMK04832_BIT_CLKIN_SEL_TYPE,
+ LMK04832_VAL_CLKIN_SEL_TYPE_OUT));
+}
+
+static int lmk04832_probe(struct spi_device *spi)
+{
+ const struct lmk04832_device_info *info;
+ int rdbk_pin = RDBK_CLKIN_SEL1;
+ struct device_node *child;
+ struct lmk04832 *lmk;
+ u8 tmp[3];
+ int ret;
+ int i;
+
+ info = &lmk04832_device_info[spi_get_device_id(spi)->driver_data];
+
+ lmk = devm_kzalloc(&spi->dev, sizeof(struct lmk04832), GFP_KERNEL);
+ if (!lmk)
+ return -ENOMEM;
+
+ lmk->dev = &spi->dev;
+
+ lmk->oscin = devm_clk_get(lmk->dev, "oscin");
+ if (IS_ERR(lmk->oscin)) {
+ dev_err(lmk->dev, "failed to get oscin clock\n");
+ return PTR_ERR(lmk->oscin);
+ }
+
+ ret = clk_prepare_enable(lmk->oscin);
+ if (ret)
+ return ret;
+
+ lmk->reset_gpio = devm_gpiod_get_optional(&spi->dev, "reset",
+ GPIOD_OUT_LOW);
+
+ lmk->dclk = devm_kcalloc(lmk->dev, info->num_channels >> 1,
+ sizeof(struct lmk_dclk), GFP_KERNEL);
+ if (IS_ERR(lmk->dclk)) {
+ ret = PTR_ERR(lmk->dclk);
+ goto err_disable_oscin;
+ }
+
+ lmk->clkout = devm_kcalloc(lmk->dev, info->num_channels,
+ sizeof(*lmk->clkout), GFP_KERNEL);
+ if (IS_ERR(lmk->clkout)) {
+ ret = PTR_ERR(lmk->clkout);
+ goto err_disable_oscin;
+ }
+
+ lmk->clk_data = devm_kzalloc(lmk->dev, struct_size(lmk->clk_data, hws,
+ info->num_channels),
+ GFP_KERNEL);
+ if (IS_ERR(lmk->clk_data)) {
+ ret = PTR_ERR(lmk->clk_data);
+ goto err_disable_oscin;
+ }
+
+ device_property_read_u32(lmk->dev, "ti,vco-hz", &lmk->vco_rate);
+
+ lmk->sysref_ddly = 8;
+ device_property_read_u32(lmk->dev, "ti,sysref-ddly", &lmk->sysref_ddly);
+
+ lmk->sysref_mux = LMK04832_VAL_SYSREF_MUX_CONTINUOUS;
+ device_property_read_u32(lmk->dev, "ti,sysref-mux",
+ &lmk->sysref_mux);
+
+ lmk->sync_mode = LMK04832_VAL_SYNC_MODE_OFF;
+ device_property_read_u32(lmk->dev, "ti,sync-mode",
+ &lmk->sync_mode);
+
+ lmk->sysref_pulse_cnt = 4;
+ device_property_read_u32(lmk->dev, "ti,sysref-pulse-count",
+ &lmk->sysref_pulse_cnt);
+
+ for_each_child_of_node(lmk->dev->of_node, child) {
+ int reg;
+
+ ret = of_property_read_u32(child, "reg", &reg);
+ if (ret) {
+ dev_err(lmk->dev, "missing reg property in child: %s\n",
+ child->full_name);
+ of_node_put(child);
+ goto err_disable_oscin;
+ }
+
+ of_property_read_u32(child, "ti,clkout-fmt",
+ &lmk->clkout[reg].format);
+
+ if (lmk->clkout[reg].format >= 0x0a && reg % 2 == 0
+ && reg != 8 && reg != 10)
+ dev_err(lmk->dev, "invalid format for clkout%02d\n",
+ reg);
+
+ lmk->clkout[reg].sysref =
+ of_property_read_bool(child, "ti,clkout-sysref");
+ }
+
+ lmk->regmap = devm_regmap_init_spi(spi, &regmap_config);
+ if (IS_ERR(lmk->regmap)) {
+ dev_err(lmk->dev, "%s: regmap allocation failed: %ld\n",
+
+ __func__, PTR_ERR(lmk->regmap));
+ ret = PTR_ERR(lmk->regmap);
+ goto err_disable_oscin;
+ }
+
+ regmap_write(lmk->regmap, LMK04832_REG_RST3W, LMK04832_BIT_RESET);
+
+ if (!(spi->mode & SPI_3WIRE)) {
+ device_property_read_u32(lmk->dev, "ti,spi-4wire-rdbk",
+ &rdbk_pin);
+ ret = lmk04832_set_spi_rdbk(lmk, rdbk_pin);
+ if (ret)
+ goto err_disable_oscin;
+ }
+
+ regmap_bulk_read(lmk->regmap, LMK04832_REG_ID_PROD_MSB, &tmp, 3);
+ if ((tmp[0] << 8 | tmp[1]) != info->pid || tmp[2] != info->maskrev) {
+ dev_err(lmk->dev, "unsupported device type: pid 0x%04x, maskrev 0x%02x\n",
+ tmp[0] << 8 | tmp[1], tmp[2]);
+ ret = -EINVAL;
+ goto err_disable_oscin;
+ }
+
+ ret = lmk04832_register_vco(lmk);
+ if (ret) {
+ dev_err(lmk->dev, "failed to init device clock path\n");
+ goto err_disable_oscin;
+ }
+
+ if (lmk->vco_rate) {
+ dev_info(lmk->dev, "setting VCO rate to %u Hz\n", lmk->vco_rate);
+ ret = clk_set_rate(lmk->vco.clk, lmk->vco_rate);
+ if (ret) {
+ dev_err(lmk->dev, "failed to set VCO rate\n");
+ goto err_disable_vco;
+ }
+ }
+
+ ret = lmk04832_register_sclk(lmk);
+ if (ret) {
+ dev_err(lmk->dev, "failed to init SYNC/SYSREF clock path\n");
+ goto err_disable_vco;
+ }
+
+ for (i = 0; i < info->num_channels; i++) {
+ ret = lmk04832_register_clkout(lmk, i);
+ if (ret) {
+ dev_err(lmk->dev, "failed to register clk %d\n", i);
+ goto err_disable_vco;
+ }
+ }
+
+ lmk->clk_data->num = info->num_channels;
+ ret = of_clk_add_hw_provider(lmk->dev->of_node, of_clk_hw_onecell_get,
+ lmk->clk_data);
+ if (ret) {
+ dev_err(lmk->dev, "failed to add provider (%d)\n", ret);
+ goto err_disable_vco;
+ }
+
+ spi_set_drvdata(spi, lmk);
+
+ return 0;
+
+err_disable_vco:
+ clk_disable_unprepare(lmk->vco.clk);
+
+err_disable_oscin:
+ clk_disable_unprepare(lmk->oscin);
+
+ return ret;
+}
+
+static int lmk04832_remove(struct spi_device *spi)
+{
+ struct lmk04832 *lmk = spi_get_drvdata(spi);
+
+ clk_disable_unprepare(lmk->oscin);
+ of_clk_del_provider(spi->dev.of_node);
+
+ return 0;
+}
+static const struct spi_device_id lmk04832_id[] = {
+ { "lmk04832", LMK04832 },
+ {}
+};
+MODULE_DEVICE_TABLE(spi, lmk04832_id);
+
+static const struct of_device_id lmk04832_of_id[] = {
+ { .compatible = "ti,lmk04832" },
+ {}
+};
+MODULE_DEVICE_TABLE(of, lmk04832_of_id);
+
+static struct spi_driver lmk04832_driver = {
+ .driver = {
+ .name = "lmk04832",
+ .of_match_table = lmk04832_of_id,
+ },
+ .probe = lmk04832_probe,
+ .remove = lmk04832_remove,
+ .id_table = lmk04832_id,
+};
+module_spi_driver(lmk04832_driver);
+
+MODULE_AUTHOR("Liam Beguin <lvb@xiphos.com>");
+MODULE_DESCRIPTION("Texas Instruments LMK04832");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c
index a875649df8b8..6adc625e79cb 100644
--- a/drivers/clk/clk-stm32mp1.c
+++ b/drivers/clk/clk-stm32mp1.c
@@ -10,8 +10,11 @@
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/io.h>
+#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/reset-controller.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
@@ -245,7 +248,7 @@ static const char * const dsi_src[] = {
};
static const char * const rtc_src[] = {
- "off", "ck_lse", "ck_lsi", "ck_hse_rtc"
+ "off", "ck_lse", "ck_lsi", "ck_hse"
};
static const char * const mco1_src[] = {
@@ -469,7 +472,7 @@ static const struct clk_ops mp1_gate_clk_ops = {
.is_enabled = clk_gate_is_enabled,
};
-static struct clk_hw *_get_stm32_mux(void __iomem *base,
+static struct clk_hw *_get_stm32_mux(struct device *dev, void __iomem *base,
const struct stm32_mux_cfg *cfg,
spinlock_t *lock)
{
@@ -478,7 +481,7 @@ static struct clk_hw *_get_stm32_mux(void __iomem *base,
struct clk_hw *mux_hw;
if (cfg->mmux) {
- mmux = kzalloc(sizeof(*mmux), GFP_KERNEL);
+ mmux = devm_kzalloc(dev, sizeof(*mmux), GFP_KERNEL);
if (!mmux)
return ERR_PTR(-ENOMEM);
@@ -493,7 +496,7 @@ static struct clk_hw *_get_stm32_mux(void __iomem *base,
cfg->mmux->hws[cfg->mmux->nbr_clk++] = mux_hw;
} else {
- mux = kzalloc(sizeof(*mux), GFP_KERNEL);
+ mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
if (!mux)
return ERR_PTR(-ENOMEM);
@@ -509,13 +512,13 @@ static struct clk_hw *_get_stm32_mux(void __iomem *base,
return mux_hw;
}
-static struct clk_hw *_get_stm32_div(void __iomem *base,
+static struct clk_hw *_get_stm32_div(struct device *dev, void __iomem *base,
const struct stm32_div_cfg *cfg,
spinlock_t *lock)
{
struct clk_divider *div;
- div = kzalloc(sizeof(*div), GFP_KERNEL);
+ div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);
if (!div)
return ERR_PTR(-ENOMEM);
@@ -530,16 +533,16 @@ static struct clk_hw *_get_stm32_div(void __iomem *base,
return &div->hw;
}
-static struct clk_hw *
-_get_stm32_gate(void __iomem *base,
- const struct stm32_gate_cfg *cfg, spinlock_t *lock)
+static struct clk_hw *_get_stm32_gate(struct device *dev, void __iomem *base,
+ const struct stm32_gate_cfg *cfg,
+ spinlock_t *lock)
{
struct stm32_clk_mgate *mgate;
struct clk_gate *gate;
struct clk_hw *gate_hw;
if (cfg->mgate) {
- mgate = kzalloc(sizeof(*mgate), GFP_KERNEL);
+ mgate = devm_kzalloc(dev, sizeof(*mgate), GFP_KERNEL);
if (!mgate)
return ERR_PTR(-ENOMEM);
@@ -554,7 +557,7 @@ _get_stm32_gate(void __iomem *base,
gate_hw = &mgate->gate.hw;
} else {
- gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+ gate = devm_kzalloc(dev, sizeof(*gate), GFP_KERNEL);
if (!gate)
return ERR_PTR(-ENOMEM);
@@ -592,7 +595,7 @@ clk_stm32_register_gate_ops(struct device *dev,
if (cfg->ops)
init.ops = cfg->ops;
- hw = _get_stm32_gate(base, cfg, lock);
+ hw = _get_stm32_gate(dev, base, cfg, lock);
if (IS_ERR(hw))
return ERR_PTR(-ENOMEM);
@@ -623,7 +626,7 @@ clk_stm32_register_composite(struct device *dev,
gate_ops = NULL;
if (cfg->mux) {
- mux_hw = _get_stm32_mux(base, cfg->mux, lock);
+ mux_hw = _get_stm32_mux(dev, base, cfg->mux, lock);
if (!IS_ERR(mux_hw)) {
mux_ops = &clk_mux_ops;
@@ -634,7 +637,7 @@ clk_stm32_register_composite(struct device *dev,
}
if (cfg->div) {
- div_hw = _get_stm32_div(base, cfg->div, lock);
+ div_hw = _get_stm32_div(dev, base, cfg->div, lock);
if (!IS_ERR(div_hw)) {
div_ops = &clk_divider_ops;
@@ -645,7 +648,7 @@ clk_stm32_register_composite(struct device *dev,
}
if (cfg->gate) {
- gate_hw = _get_stm32_gate(base, cfg->gate, lock);
+ gate_hw = _get_stm32_gate(dev, base, cfg->gate, lock);
if (!IS_ERR(gate_hw)) {
gate_ops = &clk_gate_ops;
@@ -731,6 +734,7 @@ struct stm32_pll_obj {
spinlock_t *lock;
void __iomem *reg;
struct clk_hw hw;
+ struct clk_mux mux;
};
#define to_pll(_hw) container_of(_hw, struct stm32_pll_obj, hw)
@@ -745,6 +749,8 @@ struct stm32_pll_obj {
#define FRAC_MASK 0x1FFF
#define FRAC_SHIFT 3
#define FRACLE BIT(16)
+#define PLL_MUX_SHIFT 0
+#define PLL_MUX_MASK 3
static int __pll_is_enabled(struct clk_hw *hw)
{
@@ -856,16 +862,29 @@ static int pll_is_enabled(struct clk_hw *hw)
return ret;
}
+static u8 pll_get_parent(struct clk_hw *hw)
+{
+ struct stm32_pll_obj *clk_elem = to_pll(hw);
+ struct clk_hw *mux_hw = &clk_elem->mux.hw;
+
+ __clk_hw_set_clk(mux_hw, hw);
+
+ return clk_mux_ops.get_parent(mux_hw);
+}
+
static const struct clk_ops pll_ops = {
.enable = pll_enable,
.disable = pll_disable,
.recalc_rate = pll_recalc_rate,
.is_enabled = pll_is_enabled,
+ .get_parent = pll_get_parent,
};
static struct clk_hw *clk_register_pll(struct device *dev, const char *name,
- const char *parent_name,
+ const char * const *parent_names,
+ int num_parents,
void __iomem *reg,
+ void __iomem *mux_reg,
unsigned long flags,
spinlock_t *lock)
{
@@ -874,15 +893,22 @@ static struct clk_hw *clk_register_pll(struct device *dev, const char *name,
struct clk_hw *hw;
int err;
- element = kzalloc(sizeof(*element), GFP_KERNEL);
+ element = devm_kzalloc(dev, sizeof(*element), GFP_KERNEL);
if (!element)
return ERR_PTR(-ENOMEM);
init.name = name;
init.ops = &pll_ops;
init.flags = flags;
- init.parent_names = &parent_name;
- init.num_parents = 1;
+ init.parent_names = parent_names;
+ init.num_parents = num_parents;
+
+ element->mux.lock = lock;
+ element->mux.reg = mux_reg;
+ element->mux.shift = PLL_MUX_SHIFT;
+ element->mux.mask = PLL_MUX_MASK;
+ element->mux.flags = CLK_MUX_READ_ONLY;
+ element->mux.reg = mux_reg;
element->hw.init = &init;
element->reg = reg;
@@ -891,10 +917,8 @@ static struct clk_hw *clk_register_pll(struct device *dev, const char *name,
hw = &element->hw;
err = clk_hw_register(dev, hw);
- if (err) {
- kfree(element);
+ if (err)
return ERR_PTR(err);
- }
return hw;
}
@@ -1005,7 +1029,7 @@ static struct clk_hw *clk_register_cktim(struct device *dev, const char *name,
struct clk_hw *hw;
int err;
- tim_ker = kzalloc(sizeof(*tim_ker), GFP_KERNEL);
+ tim_ker = devm_kzalloc(dev, sizeof(*tim_ker), GFP_KERNEL);
if (!tim_ker)
return ERR_PTR(-ENOMEM);
@@ -1023,16 +1047,56 @@ static struct clk_hw *clk_register_cktim(struct device *dev, const char *name,
hw = &tim_ker->hw;
err = clk_hw_register(dev, hw);
- if (err) {
- kfree(tim_ker);
+ if (err)
return ERR_PTR(err);
- }
return hw;
}
+/* The divider of RTC clock concerns only ck_hse clock */
+#define HSE_RTC 3
+
+static unsigned long clk_divider_rtc_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ if (clk_hw_get_parent(hw) == clk_hw_get_parent_by_index(hw, HSE_RTC))
+ return clk_divider_ops.recalc_rate(hw, parent_rate);
+
+ return parent_rate;
+}
+
+static int clk_divider_rtc_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ if (clk_hw_get_parent(hw) == clk_hw_get_parent_by_index(hw, HSE_RTC))
+ return clk_divider_ops.set_rate(hw, rate, parent_rate);
+
+ return parent_rate;
+}
+
+static int clk_divider_rtc_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
+{
+ unsigned long best_parent_rate = req->best_parent_rate;
+
+ if (req->best_parent_hw == clk_hw_get_parent_by_index(hw, HSE_RTC)) {
+ req->rate = clk_divider_ops.round_rate(hw, req->rate, &best_parent_rate);
+ req->best_parent_rate = best_parent_rate;
+ } else {
+ req->rate = best_parent_rate;
+ }
+
+ return 0;
+}
+
+static const struct clk_ops rtc_div_clk_ops = {
+ .recalc_rate = clk_divider_rtc_recalc_rate,
+ .set_rate = clk_divider_rtc_set_rate,
+ .determine_rate = clk_divider_rtc_determine_rate
+};
+
struct stm32_pll_cfg {
u32 offset;
+ u32 muxoff;
};
static struct clk_hw *_clk_register_pll(struct device *dev,
@@ -1042,8 +1106,11 @@ static struct clk_hw *_clk_register_pll(struct device *dev,
{
struct stm32_pll_cfg *stm_pll_cfg = cfg->cfg;
- return clk_register_pll(dev, cfg->name, cfg->parent_name,
- base + stm_pll_cfg->offset, cfg->flags, lock);
+ return clk_register_pll(dev, cfg->name, cfg->parent_names,
+ cfg->num_parents,
+ base + stm_pll_cfg->offset,
+ base + stm_pll_cfg->muxoff,
+ cfg->flags, lock);
}
struct stm32_cktim_cfg {
@@ -1153,14 +1220,16 @@ _clk_stm32_register_composite(struct device *dev,
.func = _clk_hw_register_mux,\
}
-#define PLL(_id, _name, _parent, _flags, _offset)\
+#define PLL(_id, _name, _parents, _flags, _offset_p, _offset_mux)\
{\
.id = _id,\
.name = _name,\
- .parent_name = _parent,\
- .flags = _flags,\
+ .parent_names = _parents,\
+ .num_parents = ARRAY_SIZE(_parents),\
+ .flags = CLK_IGNORE_UNUSED | (_flags),\
.cfg = &(struct stm32_pll_cfg) {\
- .offset = _offset,\
+ .offset = _offset_p,\
+ .muxoff = _offset_mux,\
},\
.func = _clk_register_pll,\
}
@@ -1243,6 +1312,10 @@ _clk_stm32_register_composite(struct device *dev,
_STM32_DIV(_div_offset, _div_shift, _div_width,\
_div_flags, _div_table, NULL)\
+#define _DIV_RTC(_div_offset, _div_shift, _div_width, _div_flags, _div_table)\
+ _STM32_DIV(_div_offset, _div_shift, _div_width,\
+ _div_flags, _div_table, &rtc_div_clk_ops)
+
#define _STM32_MUX(_offset, _shift, _width, _mux_flags, _mmux, _ops)\
.mux = &(struct stm32_mux_cfg) {\
&(struct mux_cfg) {\
@@ -1657,36 +1730,26 @@ static const struct stm32_mux_cfg ker_mux_cfg[M_LAST] = {
};
static const struct clock_config stm32mp1_clock_cfg[] = {
- /* Oscillator divider */
- DIV(NO_ID, "clk-hsi-div", "clk-hsi", CLK_DIVIDER_POWER_OF_TWO,
- RCC_HSICFGR, 0, 2, CLK_DIVIDER_READ_ONLY),
-
/* External / Internal Oscillators */
GATE_MP1(CK_HSE, "ck_hse", "clk-hse", 0, RCC_OCENSETR, 8, 0),
/* ck_csi is used by IO compensation and should be critical */
GATE_MP1(CK_CSI, "ck_csi", "clk-csi", CLK_IS_CRITICAL,
RCC_OCENSETR, 4, 0),
- GATE_MP1(CK_HSI, "ck_hsi", "clk-hsi-div", 0, RCC_OCENSETR, 0, 0),
+ COMPOSITE(CK_HSI, "ck_hsi", PARENT("clk-hsi"), 0,
+ _GATE_MP1(RCC_OCENSETR, 0, 0),
+ _NO_MUX,
+ _DIV(RCC_HSICFGR, 0, 2, CLK_DIVIDER_POWER_OF_TWO |
+ CLK_DIVIDER_READ_ONLY, NULL)),
GATE(CK_LSI, "ck_lsi", "clk-lsi", 0, RCC_RDLSICR, 0, 0),
GATE(CK_LSE, "ck_lse", "clk-lse", 0, RCC_BDCR, 0, 0),
FIXED_FACTOR(CK_HSE_DIV2, "clk-hse-div2", "ck_hse", 0, 1, 2),
- /* ref clock pll */
- MUX(NO_ID, "ref1", ref12_parents, CLK_OPS_PARENT_ENABLE, RCC_RCK12SELR,
- 0, 2, CLK_MUX_READ_ONLY),
-
- MUX(NO_ID, "ref3", ref3_parents, CLK_OPS_PARENT_ENABLE, RCC_RCK3SELR,
- 0, 2, CLK_MUX_READ_ONLY),
-
- MUX(NO_ID, "ref4", ref4_parents, CLK_OPS_PARENT_ENABLE, RCC_RCK4SELR,
- 0, 2, CLK_MUX_READ_ONLY),
-
/* PLLs */
- PLL(PLL1, "pll1", "ref1", CLK_IGNORE_UNUSED, RCC_PLL1CR),
- PLL(PLL2, "pll2", "ref1", CLK_IGNORE_UNUSED, RCC_PLL2CR),
- PLL(PLL3, "pll3", "ref3", CLK_IGNORE_UNUSED, RCC_PLL3CR),
- PLL(PLL4, "pll4", "ref4", CLK_IGNORE_UNUSED, RCC_PLL4CR),
+ PLL(PLL1, "pll1", ref12_parents, 0, RCC_PLL1CR, RCC_RCK12SELR),
+ PLL(PLL2, "pll2", ref12_parents, 0, RCC_PLL2CR, RCC_RCK12SELR),
+ PLL(PLL3, "pll3", ref3_parents, 0, RCC_PLL3CR, RCC_RCK3SELR),
+ PLL(PLL4, "pll4", ref4_parents, 0, RCC_PLL4CR, RCC_RCK4SELR),
/* ODF */
COMPOSITE(PLL1_P, "pll1_p", PARENT("pll1"), 0,
@@ -1965,13 +2028,10 @@ static const struct clock_config stm32mp1_clock_cfg[] = {
_DIV(RCC_ETHCKSELR, 4, 4, 0, NULL)),
/* RTC clock */
- DIV(NO_ID, "ck_hse_rtc", "ck_hse", 0, RCC_RTCDIVR, 0, 6, 0),
-
- COMPOSITE(RTC, "ck_rtc", rtc_src, CLK_OPS_PARENT_ENABLE |
- CLK_SET_RATE_PARENT,
+ COMPOSITE(RTC, "ck_rtc", rtc_src, CLK_OPS_PARENT_ENABLE,
_GATE(RCC_BDCR, 20, 0),
_MUX(RCC_BDCR, 16, 2, 0),
- _NO_DIV),
+ _DIV_RTC(RCC_RTCDIVR, 0, 6, 0, NULL)),
/* MCO clocks */
COMPOSITE(CK_MCO1, "ck_mco1", mco1_src, CLK_OPS_PARENT_ENABLE |
@@ -1996,16 +2056,76 @@ static const struct clock_config stm32mp1_clock_cfg[] = {
_DIV(RCC_DBGCFGR, 0, 3, 0, ck_trace_div_table)),
};
-struct stm32_clock_match_data {
+static const u32 stm32mp1_clock_secured[] = {
+ CK_HSE,
+ CK_HSI,
+ CK_CSI,
+ CK_LSI,
+ CK_LSE,
+ PLL1,
+ PLL2,
+ PLL1_P,
+ PLL2_P,
+ PLL2_Q,
+ PLL2_R,
+ CK_MPU,
+ CK_AXI,
+ SPI6,
+ I2C4,
+ I2C6,
+ USART1,
+ RTCAPB,
+ TZC1,
+ TZC2,
+ TZPC,
+ IWDG1,
+ BSEC,
+ STGEN,
+ GPIOZ,
+ CRYP1,
+ HASH1,
+ RNG1,
+ BKPSRAM,
+ RNG1_K,
+ STGEN_K,
+ SPI6_K,
+ I2C4_K,
+ I2C6_K,
+ USART1_K,
+ RTC,
+};
+
+static bool stm32_check_security(const struct clock_config *cfg)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(stm32mp1_clock_secured); i++)
+ if (cfg->id == stm32mp1_clock_secured[i])
+ return true;
+ return false;
+}
+
+struct stm32_rcc_match_data {
const struct clock_config *cfg;
unsigned int num;
unsigned int maxbinding;
+ u32 clear_offset;
+ bool (*check_security)(const struct clock_config *cfg);
};
-static struct stm32_clock_match_data stm32mp1_data = {
+static struct stm32_rcc_match_data stm32mp1_data = {
.cfg = stm32mp1_clock_cfg,
.num = ARRAY_SIZE(stm32mp1_clock_cfg),
.maxbinding = STM32MP1_LAST_CLK,
+ .clear_offset = RCC_CLR,
+};
+
+static struct stm32_rcc_match_data stm32mp1_data_secure = {
+ .cfg = stm32mp1_clock_cfg,
+ .num = ARRAY_SIZE(stm32mp1_clock_cfg),
+ .maxbinding = STM32MP1_LAST_CLK,
+ .clear_offset = RCC_CLR,
+ .check_security = &stm32_check_security
};
static const struct of_device_id stm32mp1_match_data[] = {
@@ -2013,8 +2133,13 @@ static const struct of_device_id stm32mp1_match_data[] = {
.compatible = "st,stm32mp1-rcc",
.data = &stm32mp1_data,
},
+ {
+ .compatible = "st,stm32mp1-rcc-secure",
+ .data = &stm32mp1_data_secure,
+ },
{ }
};
+MODULE_DEVICE_TABLE(of, stm32mp1_match_data);
static int stm32_register_hw_clk(struct device *dev,
struct clk_hw_onecell_data *clk_data,
@@ -2040,28 +2165,126 @@ static int stm32_register_hw_clk(struct device *dev,
return 0;
}
-static int stm32_rcc_init(struct device_node *np,
- void __iomem *base,
- const struct of_device_id *match_data)
+#define STM32_RESET_ID_MASK GENMASK(15, 0)
+
+struct stm32_reset_data {
+ /* reset lock */
+ spinlock_t lock;
+ struct reset_controller_dev rcdev;
+ void __iomem *membase;
+ u32 clear_offset;
+};
+
+static inline struct stm32_reset_data *
+to_stm32_reset_data(struct reset_controller_dev *rcdev)
{
- struct clk_hw_onecell_data *clk_data;
- struct clk_hw **hws;
- const struct of_device_id *match;
- const struct stm32_clock_match_data *data;
- int err, n, max_binding;
+ return container_of(rcdev, struct stm32_reset_data, rcdev);
+}
- match = of_match_node(match_data, np);
- if (!match) {
- pr_err("%s: match data not found\n", __func__);
- return -ENODEV;
+static int stm32_reset_update(struct reset_controller_dev *rcdev,
+ unsigned long id, bool assert)
+{
+ struct stm32_reset_data *data = to_stm32_reset_data(rcdev);
+ int reg_width = sizeof(u32);
+ int bank = id / (reg_width * BITS_PER_BYTE);
+ int offset = id % (reg_width * BITS_PER_BYTE);
+
+ if (data->clear_offset) {
+ void __iomem *addr;
+
+ addr = data->membase + (bank * reg_width);
+ if (!assert)
+ addr += data->clear_offset;
+
+ writel(BIT(offset), addr);
+
+ } else {
+ unsigned long flags;
+ u32 reg;
+
+ spin_lock_irqsave(&data->lock, flags);
+
+ reg = readl(data->membase + (bank * reg_width));
+
+ if (assert)
+ reg |= BIT(offset);
+ else
+ reg &= ~BIT(offset);
+
+ writel(reg, data->membase + (bank * reg_width));
+
+ spin_unlock_irqrestore(&data->lock, flags);
}
+ return 0;
+}
+
+static int stm32_reset_assert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ return stm32_reset_update(rcdev, id, true);
+}
+
+static int stm32_reset_deassert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ return stm32_reset_update(rcdev, id, false);
+}
+
+static int stm32_reset_status(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct stm32_reset_data *data = to_stm32_reset_data(rcdev);
+ int reg_width = sizeof(u32);
+ int bank = id / (reg_width * BITS_PER_BYTE);
+ int offset = id % (reg_width * BITS_PER_BYTE);
+ u32 reg;
+
+ reg = readl(data->membase + (bank * reg_width));
+
+ return !!(reg & BIT(offset));
+}
+
+static const struct reset_control_ops stm32_reset_ops = {
+ .assert = stm32_reset_assert,
+ .deassert = stm32_reset_deassert,
+ .status = stm32_reset_status,
+};
+
+static int stm32_rcc_reset_init(struct device *dev, void __iomem *base,
+ const struct of_device_id *match)
+{
+ const struct stm32_rcc_match_data *data = match->data;
+ struct stm32_reset_data *reset_data = NULL;
+
data = match->data;
+ reset_data = kzalloc(sizeof(*reset_data), GFP_KERNEL);
+ if (!reset_data)
+ return -ENOMEM;
+
+ reset_data->membase = base;
+ reset_data->rcdev.owner = THIS_MODULE;
+ reset_data->rcdev.ops = &stm32_reset_ops;
+ reset_data->rcdev.of_node = dev_of_node(dev);
+ reset_data->rcdev.nr_resets = STM32_RESET_ID_MASK;
+ reset_data->clear_offset = data->clear_offset;
+
+ return reset_controller_register(&reset_data->rcdev);
+}
+
+static int stm32_rcc_clock_init(struct device *dev, void __iomem *base,
+ const struct of_device_id *match)
+{
+ const struct stm32_rcc_match_data *data = match->data;
+ struct clk_hw_onecell_data *clk_data;
+ struct clk_hw **hws;
+ int err, n, max_binding;
+
max_binding = data->maxbinding;
- clk_data = kzalloc(struct_size(clk_data, hws, max_binding),
- GFP_KERNEL);
+ clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, max_binding),
+ GFP_KERNEL);
if (!clk_data)
return -ENOMEM;
@@ -2073,36 +2296,139 @@ static int stm32_rcc_init(struct device_node *np,
hws[n] = ERR_PTR(-ENOENT);
for (n = 0; n < data->num; n++) {
- err = stm32_register_hw_clk(NULL, clk_data, base, &rlock,
+ if (data->check_security && data->check_security(&data->cfg[n]))
+ continue;
+
+ err = stm32_register_hw_clk(dev, clk_data, base, &rlock,
&data->cfg[n]);
if (err) {
- pr_err("%s: can't register %s\n", __func__,
- data->cfg[n].name);
-
- kfree(clk_data);
+ dev_err(dev, "Can't register clk %s: %d\n",
+ data->cfg[n].name, err);
return err;
}
}
- return of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
+ return of_clk_add_hw_provider(dev_of_node(dev), of_clk_hw_onecell_get, clk_data);
}
-static void stm32mp1_rcc_init(struct device_node *np)
+static int stm32_rcc_init(struct device *dev, void __iomem *base,
+ const struct of_device_id *match_data)
+{
+ const struct of_device_id *match;
+ int err;
+
+ match = of_match_node(match_data, dev_of_node(dev));
+ if (!match) {
+ dev_err(dev, "match data not found\n");
+ return -ENODEV;
+ }
+
+ /* RCC Reset Configuration */
+ err = stm32_rcc_reset_init(dev, base, match);
+ if (err) {
+ pr_err("stm32mp1 reset failed to initialize\n");
+ return err;
+ }
+
+ /* RCC Clock Configuration */
+ err = stm32_rcc_clock_init(dev, base, match);
+ if (err) {
+ pr_err("stm32mp1 clock failed to initialize\n");
+ return err;
+ }
+
+ return 0;
+}
+
+static int stm32mp1_rcc_init(struct device *dev)
{
void __iomem *base;
+ int ret;
- base = of_iomap(np, 0);
+ base = of_iomap(dev_of_node(dev), 0);
if (!base) {
- pr_err("%pOFn: unable to map resource", np);
- of_node_put(np);
- return;
+ pr_err("%pOFn: unable to map resource", dev_of_node(dev));
+ ret = -ENOMEM;
+ goto out;
}
- if (stm32_rcc_init(np, base, stm32mp1_match_data)) {
- iounmap(base);
- of_node_put(np);
+ ret = stm32_rcc_init(dev, base, stm32mp1_match_data);
+
+out:
+ if (ret) {
+ if (base)
+ iounmap(base);
+
+ of_node_put(dev_of_node(dev));
}
+
+ return ret;
}
-CLK_OF_DECLARE_DRIVER(stm32mp1_rcc, "st,stm32mp1-rcc", stm32mp1_rcc_init);
+static int get_clock_deps(struct device *dev)
+{
+ static const char * const clock_deps_name[] = {
+ "hsi", "hse", "csi", "lsi", "lse",
+ };
+ size_t deps_size = sizeof(struct clk *) * ARRAY_SIZE(clock_deps_name);
+ struct clk **clk_deps;
+ int i;
+
+ clk_deps = devm_kzalloc(dev, deps_size, GFP_KERNEL);
+ if (!clk_deps)
+ return -ENOMEM;
+
+ for (i = 0; i < ARRAY_SIZE(clock_deps_name); i++) {
+ struct clk *clk = of_clk_get_by_name(dev_of_node(dev),
+ clock_deps_name[i]);
+
+ if (IS_ERR(clk)) {
+ if (PTR_ERR(clk) != -EINVAL && PTR_ERR(clk) != -ENOENT)
+ return PTR_ERR(clk);
+ } else {
+ /* Device gets a reference count on the clock */
+ clk_deps[i] = devm_clk_get(dev, __clk_get_name(clk));
+ clk_put(clk);
+ }
+ }
+
+ return 0;
+}
+
+static int stm32mp1_rcc_clocks_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ int ret = get_clock_deps(dev);
+
+ if (!ret)
+ ret = stm32mp1_rcc_init(dev);
+
+ return ret;
+}
+
+static int stm32mp1_rcc_clocks_remove(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *child, *np = dev_of_node(dev);
+
+ for_each_available_child_of_node(np, child)
+ of_clk_del_provider(child);
+
+ return 0;
+}
+
+static struct platform_driver stm32mp1_rcc_clocks_driver = {
+ .driver = {
+ .name = "stm32mp1_rcc",
+ .of_match_table = stm32mp1_match_data,
+ },
+ .probe = stm32mp1_rcc_clocks_probe,
+ .remove = stm32mp1_rcc_clocks_remove,
+};
+
+static int __init stm32mp1_clocks_init(void)
+{
+ return platform_driver_register(&stm32mp1_rcc_clocks_driver);
+}
+core_initcall(stm32mp1_clocks_init);
diff --git a/drivers/clk/ingenic/Kconfig b/drivers/clk/ingenic/Kconfig
index 580b0cf69ed5..898f1bc478c9 100644
--- a/drivers/clk/ingenic/Kconfig
+++ b/drivers/clk/ingenic/Kconfig
@@ -25,6 +25,16 @@ config INGENIC_CGU_JZ4725B
If building for a JZ4725B SoC, you want to say Y here.
+config INGENIC_CGU_JZ4760
+ bool "Ingenic JZ4760 CGU driver"
+ default MACH_JZ4760
+ select INGENIC_CGU_COMMON
+ help
+ Support the clocks provided by the CGU hardware on Ingenic JZ4760
+ and compatible SoCs.
+
+ If building for a JZ4760 SoC, you want to say Y here.
+
config INGENIC_CGU_JZ4770
bool "Ingenic JZ4770 CGU driver"
default MACH_JZ4770
diff --git a/drivers/clk/ingenic/Makefile b/drivers/clk/ingenic/Makefile
index aaa4bffe03c6..9edfaf4610b9 100644
--- a/drivers/clk/ingenic/Makefile
+++ b/drivers/clk/ingenic/Makefile
@@ -2,6 +2,7 @@
obj-$(CONFIG_INGENIC_CGU_COMMON) += cgu.o pm.o
obj-$(CONFIG_INGENIC_CGU_JZ4740) += jz4740-cgu.o
obj-$(CONFIG_INGENIC_CGU_JZ4725B) += jz4725b-cgu.o
+obj-$(CONFIG_INGENIC_CGU_JZ4760) += jz4760-cgu.o
obj-$(CONFIG_INGENIC_CGU_JZ4770) += jz4770-cgu.o
obj-$(CONFIG_INGENIC_CGU_JZ4780) += jz4780-cgu.o
obj-$(CONFIG_INGENIC_CGU_X1000) += x1000-cgu.o
diff --git a/drivers/clk/ingenic/cgu.c b/drivers/clk/ingenic/cgu.c
index c8e9cb6c8e39..266c7595d330 100644
--- a/drivers/clk/ingenic/cgu.c
+++ b/drivers/clk/ingenic/cgu.c
@@ -99,13 +99,14 @@ ingenic_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
od_enc = ctl >> pll_info->od_shift;
od_enc &= GENMASK(pll_info->od_bits - 1, 0);
- ctl = readl(cgu->base + pll_info->bypass_reg);
+ if (pll_info->bypass_bit >= 0) {
+ ctl = readl(cgu->base + pll_info->bypass_reg);
- bypass = !pll_info->no_bypass_bit &&
- !!(ctl & BIT(pll_info->bypass_bit));
+ bypass = !!(ctl & BIT(pll_info->bypass_bit));
- if (bypass)
- return parent_rate;
+ if (bypass)
+ return parent_rate;
+ }
for (od = 0; od < pll_info->od_max; od++) {
if (pll_info->od_encoding[od] == od_enc)
@@ -118,28 +119,42 @@ ingenic_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
n * od);
}
-static unsigned long
-ingenic_pll_calc(const struct ingenic_cgu_clk_info *clk_info,
- unsigned long rate, unsigned long parent_rate,
- unsigned *pm, unsigned *pn, unsigned *pod)
+static void
+ingenic_pll_calc_m_n_od(const struct ingenic_cgu_pll_info *pll_info,
+ unsigned long rate, unsigned long parent_rate,
+ unsigned int *pm, unsigned int *pn, unsigned int *pod)
{
- const struct ingenic_cgu_pll_info *pll_info;
- unsigned m, n, od;
-
- pll_info = &clk_info->pll;
- od = 1;
+ unsigned int m, n, od = 1;
/*
* The frequency after the input divider must be between 10 and 50 MHz.
* The highest divider yields the best resolution.
*/
n = parent_rate / (10 * MHZ);
- n = min_t(unsigned, n, 1 << clk_info->pll.n_bits);
- n = max_t(unsigned, n, pll_info->n_offset);
+ n = min_t(unsigned int, n, 1 << pll_info->n_bits);
+ n = max_t(unsigned int, n, pll_info->n_offset);
m = (rate / MHZ) * od * n / (parent_rate / MHZ);
- m = min_t(unsigned, m, 1 << clk_info->pll.m_bits);
- m = max_t(unsigned, m, pll_info->m_offset);
+ m = min_t(unsigned int, m, 1 << pll_info->m_bits);
+ m = max_t(unsigned int, m, pll_info->m_offset);
+
+ *pm = m;
+ *pn = n;
+ *pod = od;
+}
+
+static unsigned long
+ingenic_pll_calc(const struct ingenic_cgu_clk_info *clk_info,
+ unsigned long rate, unsigned long parent_rate,
+ unsigned int *pm, unsigned int *pn, unsigned int *pod)
+{
+ const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll;
+ unsigned int m, n, od;
+
+ if (pll_info->calc_m_n_od)
+ (*pll_info->calc_m_n_od)(pll_info, rate, parent_rate, &m, &n, &od);
+ else
+ ingenic_pll_calc_m_n_od(pll_info, rate, parent_rate, &m, &n, &od);
if (pm)
*pm = m;
@@ -225,11 +240,13 @@ static int ingenic_pll_enable(struct clk_hw *hw)
u32 ctl;
spin_lock_irqsave(&cgu->lock, flags);
- ctl = readl(cgu->base + pll_info->bypass_reg);
+ if (pll_info->bypass_bit >= 0) {
+ ctl = readl(cgu->base + pll_info->bypass_reg);
- ctl &= ~BIT(pll_info->bypass_bit);
+ ctl &= ~BIT(pll_info->bypass_bit);
- writel(ctl, cgu->base + pll_info->bypass_reg);
+ writel(ctl, cgu->base + pll_info->bypass_reg);
+ }
ctl = readl(cgu->base + pll_info->reg);
@@ -369,18 +386,23 @@ ingenic_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
struct ingenic_cgu *cgu = ingenic_clk->cgu;
unsigned long rate = parent_rate;
u32 div_reg, div;
+ u8 parent;
if (clk_info->type & CGU_CLK_DIV) {
- div_reg = readl(cgu->base + clk_info->div.reg);
- div = (div_reg >> clk_info->div.shift) &
- GENMASK(clk_info->div.bits - 1, 0);
+ parent = ingenic_clk_get_parent(hw);
- if (clk_info->div.div_table)
- div = clk_info->div.div_table[div];
- else
- div = (div + 1) * clk_info->div.div;
+ if (!(clk_info->div.bypass_mask & BIT(parent))) {
+ div_reg = readl(cgu->base + clk_info->div.reg);
+ div = (div_reg >> clk_info->div.shift) &
+ GENMASK(clk_info->div.bits - 1, 0);
- rate /= div;
+ if (clk_info->div.div_table)
+ div = clk_info->div.div_table[div];
+ else
+ div = (div + 1) * clk_info->div.div;
+
+ rate /= div;
+ }
} else if (clk_info->type & CGU_CLK_FIXDIV) {
rate /= clk_info->fixdiv.div;
}
@@ -410,10 +432,16 @@ ingenic_clk_calc_hw_div(const struct ingenic_cgu_clk_info *clk_info,
}
static unsigned
-ingenic_clk_calc_div(const struct ingenic_cgu_clk_info *clk_info,
+ingenic_clk_calc_div(struct clk_hw *hw,
+ const struct ingenic_cgu_clk_info *clk_info,
unsigned long parent_rate, unsigned long req_rate)
{
unsigned int div, hw_div;
+ u8 parent;
+
+ parent = ingenic_clk_get_parent(hw);
+ if (clk_info->div.bypass_mask & BIT(parent))
+ return 1;
/* calculate the divide */
div = DIV_ROUND_UP(parent_rate, req_rate);
@@ -448,7 +476,7 @@ ingenic_clk_round_rate(struct clk_hw *hw, unsigned long req_rate,
unsigned int div = 1;
if (clk_info->type & CGU_CLK_DIV)
- div = ingenic_clk_calc_div(clk_info, *parent_rate, req_rate);
+ div = ingenic_clk_calc_div(hw, clk_info, *parent_rate, req_rate);
else if (clk_info->type & CGU_CLK_FIXDIV)
div = clk_info->fixdiv.div;
else if (clk_hw_can_set_rate_parent(hw))
@@ -480,7 +508,7 @@ ingenic_clk_set_rate(struct clk_hw *hw, unsigned long req_rate,
int ret = 0;
if (clk_info->type & CGU_CLK_DIV) {
- div = ingenic_clk_calc_div(clk_info, parent_rate, req_rate);
+ div = ingenic_clk_calc_div(hw, clk_info, parent_rate, req_rate);
rate = DIV_ROUND_UP(parent_rate, div);
if (rate != req_rate)
diff --git a/drivers/clk/ingenic/cgu.h b/drivers/clk/ingenic/cgu.h
index 2c75ef4a36f5..bfc2b9c38a41 100644
--- a/drivers/clk/ingenic/cgu.h
+++ b/drivers/clk/ingenic/cgu.h
@@ -39,10 +39,10 @@
* their encoded values in the PLL control register, or -1 for
* unsupported values
* @bypass_reg: the offset of the bypass control register within the CGU
- * @bypass_bit: the index of the bypass bit in the PLL control register
+ * @bypass_bit: the index of the bypass bit in the PLL control register, or
+ * -1 if there is no bypass bit
* @enable_bit: the index of the enable bit in the PLL control register
* @stable_bit: the index of the stable bit in the PLL control register
- * @no_bypass_bit: if set, the PLL has no bypass functionality
*/
struct ingenic_cgu_pll_info {
unsigned reg;
@@ -52,10 +52,12 @@ struct ingenic_cgu_pll_info {
u8 n_shift, n_bits, n_offset;
u8 od_shift, od_bits, od_max;
unsigned bypass_reg;
- u8 bypass_bit;
+ s8 bypass_bit;
u8 enable_bit;
u8 stable_bit;
- bool no_bypass_bit;
+ void (*calc_m_n_od)(const struct ingenic_cgu_pll_info *pll_info,
+ unsigned long rate, unsigned long parent_rate,
+ unsigned int *m, unsigned int *n, unsigned int *od);
};
/**
@@ -84,6 +86,7 @@ struct ingenic_cgu_mux_info {
* isn't one
* @busy_bit: the index of the busy bit within reg, or -1 if there isn't one
* @stop_bit: the index of the stop bit within reg, or -1 if there isn't one
+ * @bypass_mask: mask of parent clocks for which the divider does not apply
* @div_table: optional table to map the value read from the register to the
* actual divider value
*/
@@ -95,6 +98,7 @@ struct ingenic_cgu_div_info {
s8 ce_bit;
s8 busy_bit;
s8 stop_bit;
+ u8 bypass_mask;
const u8 *div_table;
};
diff --git a/drivers/clk/ingenic/jz4725b-cgu.c b/drivers/clk/ingenic/jz4725b-cgu.c
index 8c38e72d14a7..5154b0cf8ad6 100644
--- a/drivers/clk/ingenic/jz4725b-cgu.c
+++ b/drivers/clk/ingenic/jz4725b-cgu.c
@@ -80,7 +80,7 @@ static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = {
"pll half", CGU_CLK_DIV,
.parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
.div = {
- CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1,
+ CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1, 0,
jz4725b_cgu_pll_half_div_table,
},
},
@@ -89,7 +89,7 @@ static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = {
"cclk", CGU_CLK_DIV,
.parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
.div = {
- CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1,
+ CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1, 0,
jz4725b_cgu_cpccr_div_table,
},
},
@@ -98,7 +98,7 @@ static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = {
"hclk", CGU_CLK_DIV,
.parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
.div = {
- CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1,
+ CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1, 0,
jz4725b_cgu_cpccr_div_table,
},
},
@@ -107,7 +107,7 @@ static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = {
"pclk", CGU_CLK_DIV,
.parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
.div = {
- CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1,
+ CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1, 0,
jz4725b_cgu_cpccr_div_table,
},
},
@@ -116,7 +116,7 @@ static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = {
"mclk", CGU_CLK_DIV,
.parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
.div = {
- CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1,
+ CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1, 0,
jz4725b_cgu_cpccr_div_table,
},
},
@@ -125,7 +125,7 @@ static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = {
"ipu", CGU_CLK_DIV | CGU_CLK_GATE,
.parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
.div = {
- CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1,
+ CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1, 0,
jz4725b_cgu_cpccr_div_table,
},
.gate = { CGU_REG_CLKGR, 13 },
diff --git a/drivers/clk/ingenic/jz4740-cgu.c b/drivers/clk/ingenic/jz4740-cgu.c
index c0ac9196a581..cd878f08aca3 100644
--- a/drivers/clk/ingenic/jz4740-cgu.c
+++ b/drivers/clk/ingenic/jz4740-cgu.c
@@ -95,7 +95,7 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = {
"pll half", CGU_CLK_DIV,
.parents = { JZ4740_CLK_PLL, -1, -1, -1 },
.div = {
- CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1,
+ CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1, 0,
jz4740_cgu_pll_half_div_table,
},
},
@@ -104,7 +104,7 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = {
"cclk", CGU_CLK_DIV,
.parents = { JZ4740_CLK_PLL, -1, -1, -1 },
.div = {
- CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1,
+ CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1, 0,
jz4740_cgu_cpccr_div_table,
},
},
@@ -113,7 +113,7 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = {
"hclk", CGU_CLK_DIV,
.parents = { JZ4740_CLK_PLL, -1, -1, -1 },
.div = {
- CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1,
+ CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1, 0,
jz4740_cgu_cpccr_div_table,
},
},
@@ -122,7 +122,7 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = {
"pclk", CGU_CLK_DIV,
.parents = { JZ4740_CLK_PLL, -1, -1, -1 },
.div = {
- CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1,
+ CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1, 0,
jz4740_cgu_cpccr_div_table,
},
},
@@ -131,7 +131,7 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = {
"mclk", CGU_CLK_DIV,
.parents = { JZ4740_CLK_PLL, -1, -1, -1 },
.div = {
- CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1,
+ CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1, 0,
jz4740_cgu_cpccr_div_table,
},
},
@@ -140,7 +140,7 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = {
"lcd", CGU_CLK_DIV | CGU_CLK_GATE,
.parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
.div = {
- CGU_REG_CPCCR, 16, 1, 5, 22, -1, -1,
+ CGU_REG_CPCCR, 16, 1, 5, 22, -1, -1, 0,
jz4740_cgu_cpccr_div_table,
},
.gate = { CGU_REG_CLKGR, 10 },
diff --git a/drivers/clk/ingenic/jz4760-cgu.c b/drivers/clk/ingenic/jz4760-cgu.c
new file mode 100644
index 000000000000..14483797a4db
--- /dev/null
+++ b/drivers/clk/ingenic/jz4760-cgu.c
@@ -0,0 +1,428 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * JZ4760 SoC CGU driver
+ * Copyright 2018, Paul Cercueil <paul@crapouillou.net>
+ */
+
+#include <linux/bitops.h>
+#include <linux/clk-provider.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/of.h>
+
+#include <linux/clk.h>
+
+#include <dt-bindings/clock/jz4760-cgu.h>
+
+#include "cgu.h"
+#include "pm.h"
+
+#define MHZ (1000 * 1000)
+
+/*
+ * CPM registers offset address definition
+ */
+#define CGU_REG_CPCCR 0x00
+#define CGU_REG_LCR 0x04
+#define CGU_REG_CPPCR0 0x10
+#define CGU_REG_CLKGR0 0x20
+#define CGU_REG_OPCR 0x24
+#define CGU_REG_CLKGR1 0x28
+#define CGU_REG_CPPCR1 0x30
+#define CGU_REG_USBPCR 0x3c
+#define CGU_REG_USBCDR 0x50
+#define CGU_REG_I2SCDR 0x60
+#define CGU_REG_LPCDR 0x64
+#define CGU_REG_MSCCDR 0x68
+#define CGU_REG_UHCCDR 0x6c
+#define CGU_REG_SSICDR 0x74
+#define CGU_REG_CIMCDR 0x7c
+#define CGU_REG_GPSCDR 0x80
+#define CGU_REG_PCMCDR 0x84
+#define CGU_REG_GPUCDR 0x88
+
+static const s8 pll_od_encoding[8] = {
+ 0x0, 0x1, -1, 0x2, -1, -1, -1, 0x3,
+};
+
+static const u8 jz4760_cgu_cpccr_div_table[] = {
+ 1, 2, 3, 4, 6, 8,
+};
+
+static const u8 jz4760_cgu_pll_half_div_table[] = {
+ 2, 1,
+};
+
+static void
+jz4760_cgu_calc_m_n_od(const struct ingenic_cgu_pll_info *pll_info,
+ unsigned long rate, unsigned long parent_rate,
+ unsigned int *pm, unsigned int *pn, unsigned int *pod)
+{
+ unsigned int m, n, od, m_max = (1 << pll_info->m_bits) - 2;
+
+ /* The frequency after the N divider must be between 1 and 50 MHz. */
+ n = parent_rate / (1 * MHZ);
+
+ /* The N divider must be >= 2. */
+ n = clamp_val(n, 2, 1 << pll_info->n_bits);
+
+ for (;; n >>= 1) {
+ od = (unsigned int)-1;
+
+ do {
+ m = (rate / MHZ) * (1 << ++od) * n / (parent_rate / MHZ);
+ } while ((m > m_max || m & 1) && (od < 4));
+
+ if (od < 4 && m >= 4 && m <= m_max)
+ break;
+ }
+
+ *pm = m;
+ *pn = n;
+ *pod = 1 << od;
+}
+
+static const struct ingenic_cgu_clk_info jz4760_cgu_clocks[] = {
+
+ /* External clocks */
+
+ [JZ4760_CLK_EXT] = { "ext", CGU_CLK_EXT },
+ [JZ4760_CLK_OSC32K] = { "osc32k", CGU_CLK_EXT },
+
+ /* PLLs */
+
+ [JZ4760_CLK_PLL0] = {
+ "pll0", CGU_CLK_PLL,
+ .parents = { JZ4760_CLK_EXT },
+ .pll = {
+ .reg = CGU_REG_CPPCR0,
+ .rate_multiplier = 1,
+ .m_shift = 23,
+ .m_bits = 8,
+ .m_offset = 0,
+ .n_shift = 18,
+ .n_bits = 4,
+ .n_offset = 0,
+ .od_shift = 16,
+ .od_bits = 2,
+ .od_max = 8,
+ .od_encoding = pll_od_encoding,
+ .bypass_reg = CGU_REG_CPPCR0,
+ .bypass_bit = 9,
+ .enable_bit = 8,
+ .stable_bit = 10,
+ .calc_m_n_od = jz4760_cgu_calc_m_n_od,
+ },
+ },
+
+ [JZ4760_CLK_PLL1] = {
+ /* TODO: PLL1 can depend on PLL0 */
+ "pll1", CGU_CLK_PLL,
+ .parents = { JZ4760_CLK_EXT },
+ .pll = {
+ .reg = CGU_REG_CPPCR1,
+ .rate_multiplier = 1,
+ .m_shift = 23,
+ .m_bits = 8,
+ .m_offset = 0,
+ .n_shift = 18,
+ .n_bits = 4,
+ .n_offset = 0,
+ .od_shift = 16,
+ .od_bits = 2,
+ .od_max = 8,
+ .od_encoding = pll_od_encoding,
+ .bypass_bit = -1,
+ .enable_bit = 7,
+ .stable_bit = 6,
+ .calc_m_n_od = jz4760_cgu_calc_m_n_od,
+ },
+ },
+
+ /* Main clocks */
+
+ [JZ4760_CLK_CCLK] = {
+ "cclk", CGU_CLK_DIV,
+ .parents = { JZ4760_CLK_PLL0, },
+ .div = {
+ CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1, 0,
+ jz4760_cgu_cpccr_div_table,
+ },
+ },
+ [JZ4760_CLK_HCLK] = {
+ "hclk", CGU_CLK_DIV,
+ .parents = { JZ4760_CLK_PLL0, },
+ .div = {
+ CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1, 0,
+ jz4760_cgu_cpccr_div_table,
+ },
+ },
+ [JZ4760_CLK_SCLK] = {
+ "sclk", CGU_CLK_DIV,
+ .parents = { JZ4760_CLK_PLL0, },
+ .div = {
+ CGU_REG_CPCCR, 24, 1, 4, 22, -1, -1, 0,
+ jz4760_cgu_cpccr_div_table,
+ },
+ },
+ [JZ4760_CLK_H2CLK] = {
+ "h2clk", CGU_CLK_DIV,
+ .parents = { JZ4760_CLK_PLL0, },
+ .div = {
+ CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1, 0,
+ jz4760_cgu_cpccr_div_table,
+ },
+ },
+ [JZ4760_CLK_MCLK] = {
+ "mclk", CGU_CLK_DIV,
+ .parents = { JZ4760_CLK_PLL0, },
+ .div = {
+ CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1, 0,
+ jz4760_cgu_cpccr_div_table,
+ },
+ },
+ [JZ4760_CLK_PCLK] = {
+ "pclk", CGU_CLK_DIV,
+ .parents = { JZ4760_CLK_PLL0, },
+ .div = {
+ CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1, 0,
+ jz4760_cgu_cpccr_div_table,
+ },
+ },
+
+ /* Divided clocks */
+
+ [JZ4760_CLK_PLL0_HALF] = {
+ "pll0_half", CGU_CLK_DIV,
+ .parents = { JZ4760_CLK_PLL0 },
+ .div = {
+ CGU_REG_CPCCR, 21, 1, 1, 22, -1, -1, 0,
+ jz4760_cgu_pll_half_div_table,
+ },
+ },
+
+ /* Those divided clocks can connect to PLL0 or PLL1 */
+
+ [JZ4760_CLK_UHC] = {
+ "uhc", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
+ .parents = { JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1, },
+ .mux = { CGU_REG_UHCCDR, 31, 1 },
+ .div = { CGU_REG_UHCCDR, 0, 1, 4, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR0, 24 },
+ },
+ [JZ4760_CLK_GPU] = {
+ "gpu", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
+ .parents = { JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1, },
+ .mux = { CGU_REG_GPUCDR, 31, 1 },
+ .div = { CGU_REG_GPUCDR, 0, 1, 3, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR1, 9 },
+ },
+ [JZ4760_CLK_LPCLK_DIV] = {
+ "lpclk_div", CGU_CLK_DIV | CGU_CLK_MUX,
+ .parents = { JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1, },
+ .mux = { CGU_REG_LPCDR, 29, 1 },
+ .div = { CGU_REG_LPCDR, 0, 1, 11, -1, -1, -1 },
+ },
+ [JZ4760_CLK_TVE] = {
+ "tve", CGU_CLK_GATE | CGU_CLK_MUX,
+ .parents = { JZ4760_CLK_LPCLK_DIV, JZ4760_CLK_EXT, },
+ .mux = { CGU_REG_LPCDR, 31, 1 },
+ .gate = { CGU_REG_CLKGR0, 27 },
+ },
+ [JZ4760_CLK_LPCLK] = {
+ "lpclk", CGU_CLK_GATE | CGU_CLK_MUX,
+ .parents = { JZ4760_CLK_LPCLK_DIV, JZ4760_CLK_TVE, },
+ .mux = { CGU_REG_LPCDR, 30, 1 },
+ .gate = { CGU_REG_CLKGR0, 28 },
+ },
+ [JZ4760_CLK_GPS] = {
+ "gps", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
+ .parents = { JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1, },
+ .mux = { CGU_REG_GPSCDR, 31, 1 },
+ .div = { CGU_REG_GPSCDR, 0, 1, 4, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR0, 22 },
+ },
+
+ /* Those divided clocks can connect to EXT, PLL0 or PLL1 */
+
+ [JZ4760_CLK_PCM] = {
+ "pcm", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
+ .parents = { JZ4760_CLK_EXT, -1,
+ JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1 },
+ .mux = { CGU_REG_PCMCDR, 30, 2 },
+ .div = { CGU_REG_PCMCDR, 0, 1, 9, -1, -1, -1, BIT(0) },
+ .gate = { CGU_REG_CLKGR1, 8 },
+ },
+ [JZ4760_CLK_I2S] = {
+ "i2s", CGU_CLK_DIV | CGU_CLK_MUX,
+ .parents = { JZ4760_CLK_EXT, -1,
+ JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1 },
+ .mux = { CGU_REG_I2SCDR, 30, 2 },
+ .div = { CGU_REG_I2SCDR, 0, 1, 9, -1, -1, -1, BIT(0) },
+ },
+ [JZ4760_CLK_OTG] = {
+ "usb", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
+ .parents = { JZ4760_CLK_EXT, -1,
+ JZ4760_CLK_PLL0_HALF, JZ4760_CLK_PLL1 },
+ .mux = { CGU_REG_USBCDR, 30, 2 },
+ .div = { CGU_REG_USBCDR, 0, 1, 8, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR0, 2 },
+ },
+
+ /* Those divided clocks can connect to EXT or PLL0 */
+ [JZ4760_CLK_MMC_MUX] = {
+ "mmc_mux", CGU_CLK_MUX | CGU_CLK_DIV,
+ .parents = { JZ4760_CLK_EXT, JZ4760_CLK_PLL0_HALF, },
+ .mux = { CGU_REG_MSCCDR, 31, 1 },
+ .div = { CGU_REG_MSCCDR, 0, 1, 6, -1, -1, -1, BIT(0) },
+ },
+ [JZ4760_CLK_SSI_MUX] = {
+ "ssi_mux", CGU_CLK_DIV | CGU_CLK_MUX,
+ .parents = { JZ4760_CLK_EXT, JZ4760_CLK_PLL0_HALF, },
+ .mux = { CGU_REG_SSICDR, 31, 1 },
+ .div = { CGU_REG_SSICDR, 0, 1, 6, -1, -1, -1, BIT(0) },
+ },
+
+ /* These divided clock can connect to PLL0 only */
+ [JZ4760_CLK_CIM] = {
+ "cim", CGU_CLK_DIV | CGU_CLK_GATE,
+ .parents = { JZ4760_CLK_PLL0_HALF },
+ .div = { CGU_REG_CIMCDR, 0, 1, 8, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR0, 26 },
+ },
+
+ /* Gate-only clocks */
+
+ [JZ4760_CLK_SSI0] = {
+ "ssi0", CGU_CLK_GATE,
+ .parents = { JZ4760_CLK_SSI_MUX, },
+ .gate = { CGU_REG_CLKGR0, 4 },
+ },
+ [JZ4760_CLK_SSI1] = {
+ "ssi1", CGU_CLK_GATE,
+ .parents = { JZ4760_CLK_SSI_MUX, },
+ .gate = { CGU_REG_CLKGR0, 19 },
+ },
+ [JZ4760_CLK_SSI2] = {
+ "ssi2", CGU_CLK_GATE,
+ .parents = { JZ4760_CLK_SSI_MUX, },
+ .gate = { CGU_REG_CLKGR0, 20 },
+ },
+ [JZ4760_CLK_DMA] = {
+ "dma", CGU_CLK_GATE,
+ .parents = { JZ4760_CLK_H2CLK, },
+ .gate = { CGU_REG_CLKGR0, 21 },
+ },
+ [JZ4760_CLK_I2C0] = {
+ "i2c0", CGU_CLK_GATE,
+ .parents = { JZ4760_CLK_EXT, },
+ .gate = { CGU_REG_CLKGR0, 5 },
+ },
+ [JZ4760_CLK_I2C1] = {
+ "i2c1", CGU_CLK_GATE,
+ .parents = { JZ4760_CLK_EXT, },
+ .gate = { CGU_REG_CLKGR0, 6 },
+ },
+ [JZ4760_CLK_UART0] = {
+ "uart0", CGU_CLK_GATE,
+ .parents = { JZ4760_CLK_EXT, },
+ .gate = { CGU_REG_CLKGR0, 15 },
+ },
+ [JZ4760_CLK_UART1] = {
+ "uart1", CGU_CLK_GATE,
+ .parents = { JZ4760_CLK_EXT, },
+ .gate = { CGU_REG_CLKGR0, 16 },
+ },
+ [JZ4760_CLK_UART2] = {
+ "uart2", CGU_CLK_GATE,
+ .parents = { JZ4760_CLK_EXT, },
+ .gate = { CGU_REG_CLKGR0, 17 },
+ },
+ [JZ4760_CLK_UART3] = {
+ "uart3", CGU_CLK_GATE,
+ .parents = { JZ4760_CLK_EXT, },
+ .gate = { CGU_REG_CLKGR0, 18 },
+ },
+ [JZ4760_CLK_IPU] = {
+ "ipu", CGU_CLK_GATE,
+ .parents = { JZ4760_CLK_HCLK, },
+ .gate = { CGU_REG_CLKGR0, 29 },
+ },
+ [JZ4760_CLK_ADC] = {
+ "adc", CGU_CLK_GATE,
+ .parents = { JZ4760_CLK_EXT, },
+ .gate = { CGU_REG_CLKGR0, 14 },
+ },
+ [JZ4760_CLK_AIC] = {
+ "aic", CGU_CLK_GATE,
+ .parents = { JZ4760_CLK_EXT, },
+ .gate = { CGU_REG_CLKGR0, 8 },
+ },
+ [JZ4760_CLK_VPU] = {
+ "vpu", CGU_CLK_GATE,
+ .parents = { JZ4760_CLK_HCLK, },
+ .gate = { CGU_REG_LCR, 30, false, 150 },
+ },
+ [JZ4760_CLK_MMC0] = {
+ "mmc0", CGU_CLK_GATE,
+ .parents = { JZ4760_CLK_MMC_MUX, },
+ .gate = { CGU_REG_CLKGR0, 3 },
+ },
+ [JZ4760_CLK_MMC1] = {
+ "mmc1", CGU_CLK_GATE,
+ .parents = { JZ4760_CLK_MMC_MUX, },
+ .gate = { CGU_REG_CLKGR0, 11 },
+ },
+ [JZ4760_CLK_MMC2] = {
+ "mmc2", CGU_CLK_GATE,
+ .parents = { JZ4760_CLK_MMC_MUX, },
+ .gate = { CGU_REG_CLKGR0, 12 },
+ },
+ [JZ4760_CLK_UHC_PHY] = {
+ "uhc_phy", CGU_CLK_GATE,
+ .parents = { JZ4760_CLK_UHC, },
+ .gate = { CGU_REG_OPCR, 5 },
+ },
+ [JZ4760_CLK_OTG_PHY] = {
+ "usb_phy", CGU_CLK_GATE,
+ .parents = { JZ4760_CLK_OTG },
+ .gate = { CGU_REG_OPCR, 7, true, 50 },
+ },
+
+ /* Custom clocks */
+ [JZ4760_CLK_EXT512] = {
+ "ext/512", CGU_CLK_FIXDIV,
+ .parents = { JZ4760_CLK_EXT },
+ .fixdiv = { 512 },
+ },
+ [JZ4760_CLK_RTC] = {
+ "rtc", CGU_CLK_MUX,
+ .parents = { JZ4760_CLK_EXT512, JZ4760_CLK_OSC32K, },
+ .mux = { CGU_REG_OPCR, 2, 1},
+ },
+};
+
+static void __init jz4760_cgu_init(struct device_node *np)
+{
+ struct ingenic_cgu *cgu;
+ int retval;
+
+ cgu = ingenic_cgu_new(jz4760_cgu_clocks,
+ ARRAY_SIZE(jz4760_cgu_clocks), np);
+ if (!cgu) {
+ pr_err("%s: failed to initialise CGU\n", __func__);
+ return;
+ }
+
+ retval = ingenic_cgu_register_clocks(cgu);
+ if (retval)
+ pr_err("%s: failed to register CGU Clocks\n", __func__);
+
+ ingenic_cgu_register_syscore_ops(cgu);
+}
+
+/* We only probe via devicetree, no need for a platform driver */
+CLK_OF_DECLARE_DRIVER(jz4760_cgu, "ingenic,jz4760-cgu", jz4760_cgu_init);
+
+/* JZ4760B has some small differences, but we don't implement them. */
+CLK_OF_DECLARE_DRIVER(jz4760b_cgu, "ingenic,jz4760b-cgu", jz4760_cgu_init);
diff --git a/drivers/clk/ingenic/jz4770-cgu.c b/drivers/clk/ingenic/jz4770-cgu.c
index 9ea4490ecb7f..2321742b3471 100644
--- a/drivers/clk/ingenic/jz4770-cgu.c
+++ b/drivers/clk/ingenic/jz4770-cgu.c
@@ -139,8 +139,7 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = {
.od_bits = 2,
.od_max = 8,
.od_encoding = pll_od_encoding,
- .bypass_reg = CGU_REG_CPPCR1,
- .no_bypass_bit = true,
+ .bypass_bit = -1,
.enable_bit = 7,
.stable_bit = 6,
},
@@ -152,7 +151,7 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = {
"cclk", CGU_CLK_DIV,
.parents = { JZ4770_CLK_PLL0, },
.div = {
- CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1,
+ CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1, 0,
jz4770_cgu_cpccr_div_table,
},
},
@@ -160,7 +159,7 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = {
"h0clk", CGU_CLK_DIV,
.parents = { JZ4770_CLK_PLL0, },
.div = {
- CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1,
+ CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1, 0,
jz4770_cgu_cpccr_div_table,
},
},
@@ -168,7 +167,7 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = {
"h1clk", CGU_CLK_DIV | CGU_CLK_GATE,
.parents = { JZ4770_CLK_PLL0, },
.div = {
- CGU_REG_CPCCR, 24, 1, 4, 22, -1, -1,
+ CGU_REG_CPCCR, 24, 1, 4, 22, -1, -1, 0,
jz4770_cgu_cpccr_div_table,
},
.gate = { CGU_REG_CLKGR1, 7 },
@@ -177,7 +176,7 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = {
"h2clk", CGU_CLK_DIV,
.parents = { JZ4770_CLK_PLL0, },
.div = {
- CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1,
+ CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1, 0,
jz4770_cgu_cpccr_div_table,
},
},
@@ -185,7 +184,7 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = {
"c1clk", CGU_CLK_DIV | CGU_CLK_GATE,
.parents = { JZ4770_CLK_PLL0, },
.div = {
- CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1,
+ CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1, 0,
jz4770_cgu_cpccr_div_table,
},
.gate = { CGU_REG_OPCR, 31, true }, // disable CCLK stop on idle
@@ -194,7 +193,7 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = {
"pclk", CGU_CLK_DIV,
.parents = { JZ4770_CLK_PLL0, },
.div = {
- CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1,
+ CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1, 0,
jz4770_cgu_cpccr_div_table,
},
},
diff --git a/drivers/clk/ingenic/tcu.c b/drivers/clk/ingenic/tcu.c
index 9382dc3aa27e..77acfbeb4830 100644
--- a/drivers/clk/ingenic/tcu.c
+++ b/drivers/clk/ingenic/tcu.c
@@ -326,6 +326,7 @@ static const struct ingenic_soc_info x1000_soc_info = {
static const struct of_device_id __maybe_unused ingenic_tcu_of_match[] __initconst = {
{ .compatible = "ingenic,jz4740-tcu", .data = &jz4740_soc_info, },
{ .compatible = "ingenic,jz4725b-tcu", .data = &jz4725b_soc_info, },
+ { .compatible = "ingenic,jz4760-tcu", .data = &jz4770_soc_info, },
{ .compatible = "ingenic,jz4770-tcu", .data = &jz4770_soc_info, },
{ .compatible = "ingenic,x1000-tcu", .data = &x1000_soc_info, },
{ /* sentinel */ }
@@ -477,5 +478,6 @@ static void __init ingenic_tcu_init(struct device_node *np)
CLK_OF_DECLARE_DRIVER(jz4740_cgu, "ingenic,jz4740-tcu", ingenic_tcu_init);
CLK_OF_DECLARE_DRIVER(jz4725b_cgu, "ingenic,jz4725b-tcu", ingenic_tcu_init);
+CLK_OF_DECLARE_DRIVER(jz4760_cgu, "ingenic,jz4760-tcu", ingenic_tcu_init);
CLK_OF_DECLARE_DRIVER(jz4770_cgu, "ingenic,jz4770-tcu", ingenic_tcu_init);
CLK_OF_DECLARE_DRIVER(x1000_cgu, "ingenic,x1000-tcu", ingenic_tcu_init);
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 3e7f55e44d84..29fb33c0e26d 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -199,12 +199,6 @@ config RESET_SIMPLE
- ZTE's zx2967 family
- SiFive FU740 SoCs
-config RESET_STM32MP157
- bool "STM32MP157 Reset Driver" if COMPILE_TEST
- default MACH_STM32MP157
- help
- This enables the RCC reset controller driver for STM32 MPUs.
-
config RESET_SOCFPGA
bool "SoCFPGA Reset Driver" if COMPILE_TEST && (!ARM || !ARCH_INTEL_SOCFPGA)
default ARM && ARCH_INTEL_SOCFPGA
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 65a118a91b27..ac3e612ad953 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -26,7 +26,6 @@ obj-$(CONFIG_RESET_QCOM_PDC) += reset-qcom-pdc.o
obj-$(CONFIG_RESET_RASPBERRYPI) += reset-raspberrypi.o
obj-$(CONFIG_RESET_SCMI) += reset-scmi.o
obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
-obj-$(CONFIG_RESET_STM32MP157) += reset-stm32mp1.o
obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o
diff --git a/drivers/reset/reset-stm32mp1.c b/drivers/reset/reset-stm32mp1.c
deleted file mode 100644
index b221a28041fa..000000000000
--- a/drivers/reset/reset-stm32mp1.c
+++ /dev/null
@@ -1,115 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
- * Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.
- */
-
-#include <linux/device.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/of.h>
-#include <linux/platform_device.h>
-#include <linux/reset-controller.h>
-
-#define CLR_OFFSET 0x4
-
-struct stm32_reset_data {
- struct reset_controller_dev rcdev;
- void __iomem *membase;
-};
-
-static inline struct stm32_reset_data *
-to_stm32_reset_data(struct reset_controller_dev *rcdev)
-{
- return container_of(rcdev, struct stm32_reset_data, rcdev);
-}
-
-static int stm32_reset_update(struct reset_controller_dev *rcdev,
- unsigned long id, bool assert)
-{
- struct stm32_reset_data *data = to_stm32_reset_data(rcdev);
- int reg_width = sizeof(u32);
- int bank = id / (reg_width * BITS_PER_BYTE);
- int offset = id % (reg_width * BITS_PER_BYTE);
- void __iomem *addr;
-
- addr = data->membase + (bank * reg_width);
- if (!assert)
- addr += CLR_OFFSET;
-
- writel(BIT(offset), addr);
-
- return 0;
-}
-
-static int stm32_reset_assert(struct reset_controller_dev *rcdev,
- unsigned long id)
-{
- return stm32_reset_update(rcdev, id, true);
-}
-
-static int stm32_reset_deassert(struct reset_controller_dev *rcdev,
- unsigned long id)
-{
- return stm32_reset_update(rcdev, id, false);
-}
-
-static int stm32_reset_status(struct reset_controller_dev *rcdev,
- unsigned long id)
-{
- struct stm32_reset_data *data = to_stm32_reset_data(rcdev);
- int reg_width = sizeof(u32);
- int bank = id / (reg_width * BITS_PER_BYTE);
- int offset = id % (reg_width * BITS_PER_BYTE);
- u32 reg;
-
- reg = readl(data->membase + (bank * reg_width));
-
- return !!(reg & BIT(offset));
-}
-
-static const struct reset_control_ops stm32_reset_ops = {
- .assert = stm32_reset_assert,
- .deassert = stm32_reset_deassert,
- .status = stm32_reset_status,
-};
-
-static const struct of_device_id stm32_reset_dt_ids[] = {
- { .compatible = "st,stm32mp1-rcc"},
- { /* sentinel */ },
-};
-
-static int stm32_reset_probe(struct platform_device *pdev)
-{
- struct device *dev = &pdev->dev;
- struct stm32_reset_data *data;
- void __iomem *membase;
- struct resource *res;
-
- data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
- if (!data)
- return -ENOMEM;
-
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- membase = devm_ioremap_resource(dev, res);
- if (IS_ERR(membase))
- return PTR_ERR(membase);
-
- data->membase = membase;
- data->rcdev.owner = THIS_MODULE;
- data->rcdev.nr_resets = resource_size(res) * BITS_PER_BYTE;
- data->rcdev.ops = &stm32_reset_ops;
- data->rcdev.of_node = dev->of_node;
-
- return devm_reset_controller_register(dev, &data->rcdev);
-}
-
-static struct platform_driver stm32_reset_driver = {
- .probe = stm32_reset_probe,
- .driver = {
- .name = "stm32mp1-reset",
- .of_match_table = stm32_reset_dt_ids,
- },
-};
-
-builtin_platform_driver(stm32_reset_driver);
generated by cgit v1.2.3 (git 2.39.0) at 2025-02-10 10:38:17 +0300