diff options
Diffstat (limited to 'drivers/spi')
| -rw-r--r-- | drivers/spi/spi-atmel.c | 44 | ||||
| -rw-r--r-- | drivers/spi/spi-bcm-qspi.c | 6 | ||||
| -rw-r--r-- | drivers/spi/spi-cadence.c | 65 | ||||
| -rw-r--r-- | drivers/spi/spi-davinci.c | 95 | ||||
| -rw-r--r-- | drivers/spi/spi-dw-mmio.c | 2 | ||||
| -rw-r--r-- | drivers/spi/spi-lantiq-ssc.c | 437 | ||||
| -rw-r--r-- | drivers/spi/spi-pl022.c | 2 | ||||
| -rw-r--r-- | drivers/spi/spi.c | 7 |
8 files changed, 367 insertions, 291 deletions
diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c index 0e7712bac3b6..1eb83c9613d5 100644 --- a/drivers/spi/spi-atmel.c +++ b/drivers/spi/spi-atmel.c @@ -1464,6 +1464,25 @@ static int atmel_spi_gpio_cs(struct platform_device *pdev) return 0; } +static void atmel_spi_init(struct atmel_spi *as) +{ + spi_writel(as, CR, SPI_BIT(SWRST)); + spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */ + if (as->caps.has_wdrbt) { + spi_writel(as, MR, SPI_BIT(WDRBT) | SPI_BIT(MODFDIS) + | SPI_BIT(MSTR)); + } else { + spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS)); + } + + if (as->use_pdc) + spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS)); + spi_writel(as, CR, SPI_BIT(SPIEN)); + + if (as->fifo_size) + spi_writel(as, CR, SPI_BIT(FIFOEN)); +} + static int atmel_spi_probe(struct platform_device *pdev) { struct resource *regs; @@ -1572,26 +1591,14 @@ static int atmel_spi_probe(struct platform_device *pdev) as->spi_clk = clk_get_rate(clk); - spi_writel(as, CR, SPI_BIT(SWRST)); - spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */ - if (as->caps.has_wdrbt) { - spi_writel(as, MR, SPI_BIT(WDRBT) | SPI_BIT(MODFDIS) - | SPI_BIT(MSTR)); - } else { - spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS)); - } - - if (as->use_pdc) - spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS)); - spi_writel(as, CR, SPI_BIT(SPIEN)); - as->fifo_size = 0; if (!of_property_read_u32(pdev->dev.of_node, "atmel,fifo-size", &as->fifo_size)) { dev_info(&pdev->dev, "Using FIFO (%u data)\n", as->fifo_size); - spi_writel(as, CR, SPI_BIT(FIFOEN)); } + atmel_spi_init(as); + pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT); pm_runtime_use_autosuspend(&pdev->dev); pm_runtime_set_active(&pdev->dev); @@ -1695,8 +1702,17 @@ static int atmel_spi_suspend(struct device *dev) static int atmel_spi_resume(struct device *dev) { struct spi_master *master = dev_get_drvdata(dev); + struct atmel_spi *as = spi_master_get_devdata(master); int ret; + ret = clk_prepare_enable(as->clk); + if (ret) + return ret; + + atmel_spi_init(as); + + clk_disable_unprepare(as->clk); + if (!pm_runtime_suspended(dev)) { ret = atmel_spi_runtime_resume(dev); if (ret) diff --git a/drivers/spi/spi-bcm-qspi.c b/drivers/spi/spi-bcm-qspi.c index 958fb4ee972d..b19722ba908c 100644 --- a/drivers/spi/spi-bcm-qspi.c +++ b/drivers/spi/spi-bcm-qspi.c @@ -373,7 +373,7 @@ static int bcm_qspi_bspi_set_flex_mode(struct bcm_qspi *qspi, int width, /* default mode, does not need flex_cmd */ flex_mode = 0; else - command = SPINOR_OP_READ4_FAST; + command = SPINOR_OP_READ_FAST_4B; break; case SPI_NBITS_DUAL: bpc = 0x00000001; @@ -386,7 +386,7 @@ static int bcm_qspi_bspi_set_flex_mode(struct bcm_qspi *qspi, int width, } else { command = SPINOR_OP_READ_1_1_2; if (spans_4byte) - command = SPINOR_OP_READ4_1_1_2; + command = SPINOR_OP_READ_1_1_2_4B; } break; case SPI_NBITS_QUAD: @@ -401,7 +401,7 @@ static int bcm_qspi_bspi_set_flex_mode(struct bcm_qspi *qspi, int width, } else { command = SPINOR_OP_READ_1_1_4; if (spans_4byte) - command = SPINOR_OP_READ4_1_1_4; + command = SPINOR_OP_READ_1_1_4_4B; } break; default: diff --git a/drivers/spi/spi-cadence.c b/drivers/spi/spi-cadence.c index 1c57ce64abba..f0b5c7b91f37 100644 --- a/drivers/spi/spi-cadence.c +++ b/drivers/spi/spi-cadence.c @@ -13,6 +13,7 @@ #include <linux/clk.h> #include <linux/delay.h> +#include <linux/gpio.h> #include <linux/interrupt.h> #include <linux/io.h> #include <linux/module.h> @@ -127,6 +128,10 @@ struct cdns_spi { u32 is_decoded_cs; }; +struct cdns_spi_device_data { + bool gpio_requested; +}; + /* Macros for the SPI controller read/write */ static inline u32 cdns_spi_read(struct cdns_spi *xspi, u32 offset) { @@ -456,6 +461,64 @@ static int cdns_unprepare_transfer_hardware(struct spi_master *master) return 0; } +static int cdns_spi_setup(struct spi_device *spi) +{ + + int ret = -EINVAL; + struct cdns_spi_device_data *cdns_spi_data = spi_get_ctldata(spi); + + /* this is a pin managed by the controller, leave it alone */ + if (spi->cs_gpio == -ENOENT) + return 0; + + /* this seems to be the first time we're here */ + if (!cdns_spi_data) { + cdns_spi_data = kzalloc(sizeof(*cdns_spi_data), GFP_KERNEL); + if (!cdns_spi_data) + return -ENOMEM; + cdns_spi_data->gpio_requested = false; + spi_set_ctldata(spi, cdns_spi_data); + } + + /* if we haven't done so, grab the gpio */ + if (!cdns_spi_data->gpio_requested && gpio_is_valid(spi->cs_gpio)) { + ret = gpio_request_one(spi->cs_gpio, + (spi->mode & SPI_CS_HIGH) ? + GPIOF_OUT_INIT_LOW : GPIOF_OUT_INIT_HIGH, + dev_name(&spi->dev)); + if (ret) + dev_err(&spi->dev, "can't request chipselect gpio %d\n", + spi->cs_gpio); + else + cdns_spi_data->gpio_requested = true; + } else { + if (gpio_is_valid(spi->cs_gpio)) { + int mode = ((spi->mode & SPI_CS_HIGH) ? + GPIOF_OUT_INIT_LOW : GPIOF_OUT_INIT_HIGH); + + ret = gpio_direction_output(spi->cs_gpio, mode); + if (ret) + dev_err(&spi->dev, "chipselect gpio %d setup failed (%d)\n", + spi->cs_gpio, ret); + } + } + + return ret; +} + +static void cdns_spi_cleanup(struct spi_device *spi) +{ + struct cdns_spi_device_data *cdns_spi_data = spi_get_ctldata(spi); + + if (cdns_spi_data) { + if (cdns_spi_data->gpio_requested) + gpio_free(spi->cs_gpio); + kfree(cdns_spi_data); + spi_set_ctldata(spi, NULL); + } + +} + /** * cdns_spi_probe - Probe method for the SPI driver * @pdev: Pointer to the platform_device structure @@ -555,6 +618,8 @@ static int cdns_spi_probe(struct platform_device *pdev) master->transfer_one = cdns_transfer_one; master->unprepare_transfer_hardware = cdns_unprepare_transfer_hardware; master->set_cs = cdns_spi_chipselect; + master->setup = cdns_spi_setup; + master->cleanup = cdns_spi_cleanup; master->auto_runtime_pm = true; master->mode_bits = SPI_CPOL | SPI_CPHA; diff --git a/drivers/spi/spi-davinci.c b/drivers/spi/spi-davinci.c index 02fb96797ac8..595acdcfc7d0 100644 --- a/drivers/spi/spi-davinci.c +++ b/drivers/spi/spi-davinci.c @@ -109,6 +109,8 @@ #define SPIDEF 0x4c #define SPIFMT0 0x50 +#define DMA_MIN_BYTES 16 + /* SPI Controller driver's private data. */ struct davinci_spi { struct spi_bitbang bitbang; @@ -389,6 +391,7 @@ static int davinci_spi_of_setup(struct spi_device *spi) { struct davinci_spi_config *spicfg = spi->controller_data; struct device_node *np = spi->dev.of_node; + struct davinci_spi *dspi = spi_master_get_devdata(spi->master); u32 prop; if (spicfg == NULL && np) { @@ -400,6 +403,9 @@ static int davinci_spi_of_setup(struct spi_device *spi) if (!of_property_read_u32(np, "ti,spi-wdelay", &prop)) spicfg->wdelay = (u8)prop; spi->controller_data = spicfg; + + if (dspi->dma_rx && dspi->dma_tx) + spicfg->io_type = SPI_IO_TYPE_DMA; } return 0; @@ -467,6 +473,22 @@ static void davinci_spi_cleanup(struct spi_device *spi) kfree(spicfg); } +static bool davinci_spi_can_dma(struct spi_master *master, + struct spi_device *spi, + struct spi_transfer *xfer) +{ + struct davinci_spi_config *spicfg = spi->controller_data; + bool can_dma = false; + + if (spicfg) + can_dma = (spicfg->io_type == SPI_IO_TYPE_DMA) && + (xfer->len >= DMA_MIN_BYTES) && + !is_vmalloc_addr(xfer->rx_buf) && + !is_vmalloc_addr(xfer->tx_buf); + + return can_dma; +} + static int davinci_spi_check_error(struct davinci_spi *dspi, int int_status) { struct device *sdev = dspi->bitbang.master->dev.parent; @@ -581,8 +603,6 @@ static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t) struct davinci_spi_config *spicfg; struct davinci_spi_platform_data *pdata; unsigned uninitialized_var(rx_buf_count); - void *dummy_buf = NULL; - struct scatterlist sg_rx, sg_tx; dspi = spi_master_get_devdata(spi->master); pdata = &dspi->pdata; @@ -605,10 +625,9 @@ static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t) reinit_completion(&dspi->done); - if (spicfg->io_type == SPI_IO_TYPE_INTR) - set_io_bits(dspi->base + SPIINT, SPIINT_MASKINT); - - if (spicfg->io_type != SPI_IO_TYPE_DMA) { + if (!davinci_spi_can_dma(spi->master, spi, t)) { + if (spicfg->io_type != SPI_IO_TYPE_POLL) + set_io_bits(dspi->base + SPIINT, SPIINT_MASKINT); /* start the transfer */ dspi->wcount--; tx_data = dspi->get_tx(dspi); @@ -630,51 +649,28 @@ static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t) }; struct dma_async_tx_descriptor *rxdesc; struct dma_async_tx_descriptor *txdesc; - void *buf; - - dummy_buf = kzalloc(t->len, GFP_KERNEL); - if (!dummy_buf) - goto err_alloc_dummy_buf; dmaengine_slave_config(dspi->dma_rx, &dma_rx_conf); dmaengine_slave_config(dspi->dma_tx, &dma_tx_conf); - sg_init_table(&sg_rx, 1); - if (!t->rx_buf) - buf = dummy_buf; - else - buf = t->rx_buf; - t->rx_dma = dma_map_single(&spi->dev, buf, - t->len, DMA_FROM_DEVICE); - if (dma_mapping_error(&spi->dev, !t->rx_dma)) { - ret = -EFAULT; - goto err_rx_map; - } - sg_dma_address(&sg_rx) = t->rx_dma; - sg_dma_len(&sg_rx) = t->len; - - sg_init_table(&sg_tx, 1); - if (!t->tx_buf) - buf = dummy_buf; - else - buf = (void *)t->tx_buf; - t->tx_dma = dma_map_single(&spi->dev, buf, - t->len, DMA_TO_DEVICE); - if (dma_mapping_error(&spi->dev, t->tx_dma)) { - ret = -EFAULT; - goto err_tx_map; - } - sg_dma_address(&sg_tx) = t->tx_dma; - sg_dma_len(&sg_tx) = t->len; - rxdesc = dmaengine_prep_slave_sg(dspi->dma_rx, - &sg_rx, 1, DMA_DEV_TO_MEM, + t->rx_sg.sgl, t->rx_sg.nents, DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); if (!rxdesc) goto err_desc; + if (!t->tx_buf) { + /* To avoid errors when doing rx-only transfers with + * many SG entries (> 20), use the rx buffer as the + * dummy tx buffer so that dma reloads are done at the + * same time for rx and tx. + */ + t->tx_sg.sgl = t->rx_sg.sgl; + t->tx_sg.nents = t->rx_sg.nents; + } + txdesc = dmaengine_prep_slave_sg(dspi->dma_tx, - &sg_tx, 1, DMA_MEM_TO_DEV, + t->tx_sg.sgl, t->tx_sg.nents, DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); if (!txdesc) goto err_desc; @@ -710,16 +706,9 @@ static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t) } clear_io_bits(dspi->base + SPIINT, SPIINT_MASKALL); - if (spicfg->io_type == SPI_IO_TYPE_DMA) { + if (davinci_spi_can_dma(spi->master, spi, t)) clear_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN); - dma_unmap_single(&spi->dev, t->rx_dma, - t->len, DMA_FROM_DEVICE); - dma_unmap_single(&spi->dev, t->tx_dma, - t->len, DMA_TO_DEVICE); - kfree(dummy_buf); - } - clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK); @@ -742,12 +731,6 @@ static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t) return t->len; err_desc: - dma_unmap_single(&spi->dev, t->tx_dma, t->len, DMA_TO_DEVICE); -err_tx_map: - dma_unmap_single(&spi->dev, t->rx_dma, t->len, DMA_FROM_DEVICE); -err_rx_map: - kfree(dummy_buf); -err_alloc_dummy_buf: return ret; } @@ -988,8 +971,10 @@ static int davinci_spi_probe(struct platform_device *pdev) master->bus_num = pdev->id; master->num_chipselect = pdata->num_chipselect; master->bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 16); + master->flags = SPI_MASTER_MUST_RX; master->setup = davinci_spi_setup; master->cleanup = davinci_spi_cleanup; + master->can_dma = davinci_spi_can_dma; dspi->bitbang.chipselect = davinci_spi_chipselect; dspi->bitbang.setup_transfer = davinci_spi_setup_transfer; diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c index 447497e9124c..d25cc4037e23 100644 --- a/drivers/spi/spi-dw-mmio.c +++ b/drivers/spi/spi-dw-mmio.c @@ -115,8 +115,8 @@ static int dw_spi_mmio_remove(struct platform_device *pdev) { struct dw_spi_mmio *dwsmmio = platform_get_drvdata(pdev); - clk_disable_unprepare(dwsmmio->clk); dw_spi_remove_host(&dwsmmio->dws); + clk_disable_unprepare(dwsmmio->clk); return 0; } diff --git a/drivers/spi/spi-lantiq-ssc.c b/drivers/spi/spi-lantiq-ssc.c index 8a626f7fccea..633c30b4d5a6 100644 --- a/drivers/spi/spi-lantiq-ssc.c +++ b/drivers/spi/spi-lantiq-ssc.c @@ -26,136 +26,140 @@ #include <lantiq_soc.h> #endif -#define SPI_RX_IRQ_NAME "spi_rx" -#define SPI_TX_IRQ_NAME "spi_tx" -#define SPI_ERR_IRQ_NAME "spi_err" -#define SPI_FRM_IRQ_NAME "spi_frm" - -#define SPI_CLC 0x00 -#define SPI_PISEL 0x04 -#define SPI_ID 0x08 -#define SPI_CON 0x10 -#define SPI_STAT 0x14 -#define SPI_WHBSTATE 0x18 -#define SPI_TB 0x20 -#define SPI_RB 0x24 -#define SPI_RXFCON 0x30 -#define SPI_TXFCON 0x34 -#define SPI_FSTAT 0x38 -#define SPI_BRT 0x40 -#define SPI_BRSTAT 0x44 -#define SPI_SFCON 0x60 -#define SPI_SFSTAT 0x64 -#define SPI_GPOCON 0x70 -#define SPI_GPOSTAT 0x74 -#define SPI_FPGO 0x78 -#define SPI_RXREQ 0x80 -#define SPI_RXCNT 0x84 -#define SPI_DMACON 0xec -#define SPI_IRNEN 0xf4 -#define SPI_IRNICR 0xf8 -#define SPI_IRNCR 0xfc - -#define SPI_CLC_SMC_S 16 /* Clock divider for sleep mode */ -#define SPI_CLC_SMC_M (0xFF << SPI_CLC_SMC_S) -#define SPI_CLC_RMC_S 8 /* Clock divider for normal run mode */ -#define SPI_CLC_RMC_M (0xFF << SPI_CLC_RMC_S) -#define SPI_CLC_DISS BIT(1) /* Disable status bit */ -#define SPI_CLC_DISR BIT(0) /* Disable request bit */ - -#define SPI_ID_TXFS_S 24 /* Implemented TX FIFO size */ -#define SPI_ID_TXFS_M (0x3F << SPI_ID_TXFS_S) -#define SPI_ID_RXFS_S 16 /* Implemented RX FIFO size */ -#define SPI_ID_RXFS_M (0x3F << SPI_ID_RXFS_S) -#define SPI_ID_MOD_S 8 /* Module ID */ -#define SPI_ID_MOD_M (0xff << SPI_ID_MOD_S) -#define SPI_ID_CFG_S 5 /* DMA interface support */ -#define SPI_ID_CFG_M (1 << SPI_ID_CFG_S) -#define SPI_ID_REV_M 0x1F /* Hardware revision number */ - -#define SPI_CON_BM_S 16 /* Data width selection */ -#define SPI_CON_BM_M (0x1F << SPI_CON_BM_S) -#define SPI_CON_EM BIT(24) /* Echo mode */ -#define SPI_CON_IDLE BIT(23) /* Idle bit value */ -#define SPI_CON_ENBV BIT(22) /* Enable byte valid control */ -#define SPI_CON_RUEN BIT(12) /* Receive underflow error enable */ -#define SPI_CON_TUEN BIT(11) /* Transmit underflow error enable */ -#define SPI_CON_AEN BIT(10) /* Abort error enable */ -#define SPI_CON_REN BIT(9) /* Receive overflow error enable */ -#define SPI_CON_TEN BIT(8) /* Transmit overflow error enable */ -#define SPI_CON_LB BIT(7) /* Loopback control */ -#define SPI_CON_PO BIT(6) /* Clock polarity control */ -#define SPI_CON_PH BIT(5) /* Clock phase control */ -#define SPI_CON_HB BIT(4) /* Heading control */ -#define SPI_CON_RXOFF BIT(1) /* Switch receiver off */ -#define SPI_CON_TXOFF BIT(0) /* Switch transmitter off */ - -#define SPI_STAT_RXBV_S 28 -#define SPI_STAT_RXBV_M (0x7 << SPI_STAT_RXBV_S) -#define SPI_STAT_BSY BIT(13) /* Busy flag */ -#define SPI_STAT_RUE BIT(12) /* Receive underflow error flag */ -#define SPI_STAT_TUE BIT(11) /* Transmit underflow error flag */ -#define SPI_STAT_AE BIT(10) /* Abort error flag */ -#define SPI_STAT_RE BIT(9) /* Receive error flag */ -#define SPI_STAT_TE BIT(8) /* Transmit error flag */ -#define SPI_STAT_ME BIT(7) /* Mode error flag */ -#define SPI_STAT_MS BIT(1) /* Master/slave select bit */ -#define SPI_STAT_EN BIT(0) /* Enable bit */ -#define SPI_STAT_ERRORS (SPI_STAT_ME | SPI_STAT_TE | SPI_STAT_RE | \ - SPI_STAT_AE | SPI_STAT_TUE | SPI_STAT_RUE) - -#define SPI_WHBSTATE_SETTUE BIT(15) /* Set transmit underflow error flag */ -#define SPI_WHBSTATE_SETAE BIT(14) /* Set abort error flag */ -#define SPI_WHBSTATE_SETRE BIT(13) /* Set receive error flag */ -#define SPI_WHBSTATE_SETTE BIT(12) /* Set transmit error flag */ -#define SPI_WHBSTATE_CLRTUE BIT(11) /* Clear transmit underflow error flag */ -#define SPI_WHBSTATE_CLRAE BIT(10) /* Clear abort error flag */ -#define SPI_WHBSTATE_CLRRE BIT(9) /* Clear receive error flag */ -#define SPI_WHBSTATE_CLRTE BIT(8) /* Clear transmit error flag */ -#define SPI_WHBSTATE_SETME BIT(7) /* Set mode error flag */ -#define SPI_WHBSTATE_CLRME BIT(6) /* Clear mode error flag */ -#define SPI_WHBSTATE_SETRUE BIT(5) /* Set receive underflow error flag */ -#define SPI_WHBSTATE_CLRRUE BIT(4) /* Clear receive underflow error flag */ -#define SPI_WHBSTATE_SETMS BIT(3) /* Set master select bit */ -#define SPI_WHBSTATE_CLRMS BIT(2) /* Clear master select bit */ -#define SPI_WHBSTATE_SETEN BIT(1) /* Set enable bit (operational mode) */ -#define SPI_WHBSTATE_CLREN BIT(0) /* Clear enable bit (config mode */ -#define SPI_WHBSTATE_CLR_ERRORS (SPI_WHBSTATE_CLRRUE | SPI_WHBSTATE_CLRME | \ - SPI_WHBSTATE_CLRTE | SPI_WHBSTATE_CLRRE | \ - SPI_WHBSTATE_CLRAE | SPI_WHBSTATE_CLRTUE) - -#define SPI_RXFCON_RXFITL_S 8 /* FIFO interrupt trigger level */ -#define SPI_RXFCON_RXFITL_M (0x3F << SPI_RXFCON_RXFITL_S) -#define SPI_RXFCON_RXFLU BIT(1) /* FIFO flush */ -#define SPI_RXFCON_RXFEN BIT(0) /* FIFO enable */ - -#define SPI_TXFCON_TXFITL_S 8 /* FIFO interrupt trigger level */ -#define SPI_TXFCON_TXFITL_M (0x3F << SPI_TXFCON_TXFITL_S) -#define SPI_TXFCON_TXFLU BIT(1) /* FIFO flush */ -#define SPI_TXFCON_TXFEN BIT(0) /* FIFO enable */ - -#define SPI_FSTAT_RXFFL_S 0 -#define SPI_FSTAT_RXFFL_M (0x3f << SPI_FSTAT_RXFFL_S) -#define SPI_FSTAT_TXFFL_S 8 -#define SPI_FSTAT_TXFFL_M (0x3f << SPI_FSTAT_TXFFL_S) - -#define SPI_GPOCON_ISCSBN_S 8 -#define SPI_GPOCON_INVOUTN_S 0 - -#define SPI_FGPO_SETOUTN_S 8 -#define SPI_FGPO_CLROUTN_S 0 - -#define SPI_RXREQ_RXCNT_M 0xFFFF /* Receive count value */ -#define SPI_RXCNT_TODO_M 0xFFFF /* Recevie to-do value */ - -#define SPI_IRNEN_TFI BIT(4) /* TX finished interrupt */ -#define SPI_IRNEN_F BIT(3) /* Frame end interrupt request */ -#define SPI_IRNEN_E BIT(2) /* Error end interrupt request */ -#define SPI_IRNEN_T_XWAY BIT(1) /* Transmit end interrupt request */ -#define SPI_IRNEN_R_XWAY BIT(0) /* Receive end interrupt request */ -#define SPI_IRNEN_R_XRX BIT(1) /* Transmit end interrupt request */ -#define SPI_IRNEN_T_XRX BIT(0) /* Receive end interrupt request */ -#define SPI_IRNEN_ALL 0x1F +#define LTQ_SPI_RX_IRQ_NAME "spi_rx" +#define LTQ_SPI_TX_IRQ_NAME "spi_tx" +#define LTQ_SPI_ERR_IRQ_NAME "spi_err" +#define LTQ_SPI_FRM_IRQ_NAME "spi_frm" + +#define LTQ_SPI_CLC 0x00 +#define LTQ_SPI_PISEL 0x04 +#define LTQ_SPI_ID 0x08 +#define LTQ_SPI_CON 0x10 +#define LTQ_SPI_STAT 0x14 +#define LTQ_SPI_WHBSTATE 0x18 +#define LTQ_SPI_TB 0x20 +#define LTQ_SPI_RB 0x24 +#define LTQ_SPI_RXFCON 0x30 +#define LTQ_SPI_TXFCON 0x34 +#define LTQ_SPI_FSTAT 0x38 +#define LTQ_SPI_BRT 0x40 +#define LTQ_SPI_BRSTAT 0x44 +#define LTQ_SPI_SFCON 0x60 +#define LTQ_SPI_SFSTAT 0x64 +#define LTQ_SPI_GPOCON 0x70 +#define LTQ_SPI_GPOSTAT 0x74 +#define LTQ_SPI_FPGO 0x78 +#define LTQ_SPI_RXREQ 0x80 +#define LTQ_SPI_RXCNT 0x84 +#define LTQ_SPI_DMACON 0xec +#define LTQ_SPI_IRNEN 0xf4 +#define LTQ_SPI_IRNICR 0xf8 +#define LTQ_SPI_IRNCR 0xfc + +#define LTQ_SPI_CLC_SMC_S 16 /* Clock divider for sleep mode */ +#define LTQ_SPI_CLC_SMC_M (0xFF << LTQ_SPI_CLC_SMC_S) +#define LTQ_SPI_CLC_RMC_S 8 /* Clock divider for normal run mode */ +#define LTQ_SPI_CLC_RMC_M (0xFF << LTQ_SPI_CLC_RMC_S) +#define LTQ_SPI_CLC_DISS BIT(1) /* Disable status bit */ +#define LTQ_SPI_CLC_DISR BIT(0) /* Disable request bit */ + +#define LTQ_SPI_ID_TXFS_S 24 /* Implemented TX FIFO size */ +#define LTQ_SPI_ID_TXFS_M (0x3F << LTQ_SPI_ID_TXFS_S) +#define LTQ_SPI_ID_RXFS_S 16 /* Implemented RX FIFO size */ +#define LTQ_SPI_ID_RXFS_M (0x3F << LTQ_SPI_ID_RXFS_S) +#define LTQ_SPI_ID_MOD_S 8 /* Module ID */ +#define LTQ_SPI_ID_MOD_M (0xff << LTQ_SPI_ID_MOD_S) +#define LTQ_SPI_ID_CFG_S 5 /* DMA interface support */ +#define LTQ_SPI_ID_CFG_M (1 << LTQ_SPI_ID_CFG_S) +#define LTQ_SPI_ID_REV_M 0x1F /* Hardware revision number */ + +#define LTQ_SPI_CON_BM_S 16 /* Data width selection */ +#define LTQ_SPI_CON_BM_M (0x1F << LTQ_SPI_CON_BM_S) +#define LTQ_SPI_CON_EM BIT(24) /* Echo mode */ +#define LTQ_SPI_CON_IDLE BIT(23) /* Idle bit value */ +#define LTQ_SPI_CON_ENBV BIT(22) /* Enable byte valid control */ +#define LTQ_SPI_CON_RUEN BIT(12) /* Receive underflow error enable */ +#define LTQ_SPI_CON_TUEN BIT(11) /* Transmit underflow error enable */ +#define LTQ_SPI_CON_AEN BIT(10) /* Abort error enable */ +#define LTQ_SPI_CON_REN BIT(9) /* Receive overflow error enable */ +#define LTQ_SPI_CON_TEN BIT(8) /* Transmit overflow error enable */ +#define LTQ_SPI_CON_LB BIT(7) /* Loopback control */ +#define LTQ_SPI_CON_PO BIT(6) /* Clock polarity control */ +#define LTQ_SPI_CON_PH BIT(5) /* Clock phase control */ +#define LTQ_SPI_CON_HB BIT(4) /* Heading control */ +#define LTQ_SPI_CON_RXOFF BIT(1) /* Switch receiver off */ +#define LTQ_SPI_CON_TXOFF BIT(0) /* Switch transmitter off */ + +#define LTQ_SPI_STAT_RXBV_S 28 +#define LTQ_SPI_STAT_RXBV_M (0x7 << LTQ_SPI_STAT_RXBV_S) +#define LTQ_SPI_STAT_BSY BIT(13) /* Busy flag */ +#define LTQ_SPI_STAT_RUE BIT(12) /* Receive underflow error flag */ +#define LTQ_SPI_STAT_TUE BIT(11) /* Transmit underflow error flag */ +#define LTQ_SPI_STAT_AE BIT(10) /* Abort error flag */ +#define LTQ_SPI_STAT_RE BIT(9) /* Receive error flag */ +#define LTQ_SPI_STAT_TE BIT(8) /* Transmit error flag */ +#define LTQ_SPI_STAT_ME BIT(7) /* Mode error flag */ +#define LTQ_SPI_STAT_MS BIT(1) /* Master/slave select bit */ +#define LTQ_SPI_STAT_EN BIT(0) /* Enable bit */ +#define LTQ_SPI_STAT_ERRORS (LTQ_SPI_STAT_ME | LTQ_SPI_STAT_TE | \ + LTQ_SPI_STAT_RE | LTQ_SPI_STAT_AE | \ + LTQ_SPI_STAT_TUE | LTQ_SPI_STAT_RUE) + +#define LTQ_SPI_WHBSTATE_SETTUE BIT(15) /* Set transmit underflow error flag */ +#define LTQ_SPI_WHBSTATE_SETAE BIT(14) /* Set abort error flag */ +#define LTQ_SPI_WHBSTATE_SETRE BIT(13) /* Set receive error flag */ +#define LTQ_SPI_WHBSTATE_SETTE BIT(12) /* Set transmit error flag */ +#define LTQ_SPI_WHBSTATE_CLRTUE BIT(11) /* Clear transmit underflow error flag */ +#define LTQ_SPI_WHBSTATE_CLRAE BIT(10) /* Clear abort error flag */ +#define LTQ_SPI_WHBSTATE_CLRRE BIT(9) /* Clear receive error flag */ +#define LTQ_SPI_WHBSTATE_CLRTE BIT(8) /* Clear transmit error flag */ +#define LTQ_SPI_WHBSTATE_SETME BIT(7) /* Set mode error flag */ +#define LTQ_SPI_WHBSTATE_CLRME BIT(6) /* Clear mode error flag */ +#define LTQ_SPI_WHBSTATE_SETRUE BIT(5) /* Set receive underflow error flag */ +#define LTQ_SPI_WHBSTATE_CLRRUE BIT(4) /* Clear receive underflow error flag */ +#define LTQ_SPI_WHBSTATE_SETMS BIT(3) /* Set master select bit */ +#define LTQ_SPI_WHBSTATE_CLRMS BIT(2) /* Clear master select bit */ +#define LTQ_SPI_WHBSTATE_SETEN BIT(1) /* Set enable bit (operational mode) */ +#define LTQ_SPI_WHBSTATE_CLREN BIT(0) /* Clear enable bit (config mode */ +#define LTQ_SPI_WHBSTATE_CLR_ERRORS (LTQ_SPI_WHBSTATE_CLRRUE | \ + LTQ_SPI_WHBSTATE_CLRME | \ + LTQ_SPI_WHBSTATE_CLRTE | \ + LTQ_SPI_WHBSTATE_CLRRE | \ + LTQ_SPI_WHBSTATE_CLRAE | \ + LTQ_SPI_WHBSTATE_CLRTUE) + +#define LTQ_SPI_RXFCON_RXFITL_S 8 /* FIFO interrupt trigger level */ +#define LTQ_SPI_RXFCON_RXFITL_M (0x3F << LTQ_SPI_RXFCON_RXFITL_S) +#define LTQ_SPI_RXFCON_RXFLU BIT(1) /* FIFO flush */ +#define LTQ_SPI_RXFCON_RXFEN BIT(0) /* FIFO enable */ + +#define LTQ_SPI_TXFCON_TXFITL_S 8 /* FIFO interrupt trigger level */ +#define LTQ_SPI_TXFCON_TXFITL_M (0x3F << LTQ_SPI_TXFCON_TXFITL_S) +#define LTQ_SPI_TXFCON_TXFLU BIT(1) /* FIFO flush */ +#define LTQ_SPI_TXFCON_TXFEN BIT(0) /* FIFO enable */ + +#define LTQ_SPI_FSTAT_RXFFL_S 0 +#define LTQ_SPI_FSTAT_RXFFL_M (0x3f << LTQ_SPI_FSTAT_RXFFL_S) +#define LTQ_SPI_FSTAT_TXFFL_S 8 +#define LTQ_SPI_FSTAT_TXFFL_M (0x3f << LTQ_SPI_FSTAT_TXFFL_S) + +#define LTQ_SPI_GPOCON_ISCSBN_S 8 +#define LTQ_SPI_GPOCON_INVOUTN_S 0 + +#define LTQ_SPI_FGPO_SETOUTN_S 8 +#define LTQ_SPI_FGPO_CLROUTN_S 0 + +#define LTQ_SPI_RXREQ_RXCNT_M 0xFFFF /* Receive count value */ +#define LTQ_SPI_RXCNT_TODO_M 0xFFFF /* Recevie to-do value */ + +#define LTQ_SPI_IRNEN_TFI BIT(4) /* TX finished interrupt */ +#define LTQ_SPI_IRNEN_F BIT(3) /* Frame end interrupt request */ +#define LTQ_SPI_IRNEN_E BIT(2) /* Error end interrupt request */ +#define LTQ_SPI_IRNEN_T_XWAY BIT(1) /* Transmit end interrupt request */ +#define LTQ_SPI_IRNEN_R_XWAY BIT(0) /* Receive end interrupt request */ +#define LTQ_SPI_IRNEN_R_XRX BIT(1) /* Transmit end interrupt request */ +#define LTQ_SPI_IRNEN_T_XRX BIT(0) /* Receive end interrupt request */ +#define LTQ_SPI_IRNEN_ALL 0x1F struct lantiq_ssc_hwcfg { unsigned int irnen_r; @@ -208,16 +212,16 @@ static void lantiq_ssc_maskl(const struct lantiq_ssc_spi *spi, u32 clr, static unsigned int tx_fifo_level(const struct lantiq_ssc_spi *spi) { - u32 fstat = lantiq_ssc_readl(spi, SPI_FSTAT); + u32 fstat = lantiq_ssc_readl(spi, LTQ_SPI_FSTAT); - return (fstat & SPI_FSTAT_TXFFL_M) >> SPI_FSTAT_TXFFL_S; + return (fstat & LTQ_SPI_FSTAT_TXFFL_M) >> LTQ_SPI_FSTAT_TXFFL_S; } static unsigned int rx_fifo_level(const struct lantiq_ssc_spi *spi) { - u32 fstat = lantiq_ssc_readl(spi, SPI_FSTAT); + u32 fstat = lantiq_ssc_readl(spi, LTQ_SPI_FSTAT); - return fstat & SPI_FSTAT_RXFFL_M; + return fstat & LTQ_SPI_FSTAT_RXFFL_M; } static unsigned int tx_fifo_free(const struct lantiq_ssc_spi *spi) @@ -227,38 +231,38 @@ static unsigned int tx_fifo_free(const struct lantiq_ssc_spi *spi) static void rx_fifo_reset(const struct lantiq_ssc_spi *spi) { - u32 val = spi->rx_fifo_size << SPI_RXFCON_RXFITL_S; + u32 val = spi->rx_fifo_size << LTQ_SPI_RXFCON_RXFITL_S; - val |= SPI_RXFCON_RXFEN | SPI_RXFCON_RXFLU; - lantiq_ssc_writel(spi, val, SPI_RXFCON); + val |= LTQ_SPI_RXFCON_RXFEN | LTQ_SPI_RXFCON_RXFLU; + lantiq_ssc_writel(spi, val, LTQ_SPI_RXFCON); } static void tx_fifo_reset(const struct lantiq_ssc_spi *spi) { - u32 val = 1 << SPI_TXFCON_TXFITL_S; + u32 val = 1 << LTQ_SPI_TXFCON_TXFITL_S; - val |= SPI_TXFCON_TXFEN | SPI_TXFCON_TXFLU; - lantiq_ssc_writel(spi, val, SPI_TXFCON); + val |= LTQ_SPI_TXFCON_TXFEN | LTQ_SPI_TXFCON_TXFLU; + lantiq_ssc_writel(spi, val, LTQ_SPI_TXFCON); } static void rx_fifo_flush(const struct lantiq_ssc_spi *spi) { - lantiq_ssc_maskl(spi, 0, SPI_RXFCON_RXFLU, SPI_RXFCON); + lantiq_ssc_maskl(spi, 0, LTQ_SPI_RXFCON_RXFLU, LTQ_SPI_RXFCON); } static void tx_fifo_flush(const struct lantiq_ssc_spi *spi) { - lantiq_ssc_maskl(spi, 0, SPI_TXFCON_TXFLU, SPI_TXFCON); + lantiq_ssc_maskl(spi, 0, LTQ_SPI_TXFCON_TXFLU, LTQ_SPI_TXFCON); } static void hw_enter_config_mode(const struct lantiq_ssc_spi *spi) { - lantiq_ssc_writel(spi, SPI_WHBSTATE_CLREN, SPI_WHBSTATE); + lantiq_ssc_writel(spi, LTQ_SPI_WHBSTATE_CLREN, LTQ_SPI_WHBSTATE); } static void hw_enter_active_mode(const struct lantiq_ssc_spi *spi) { - lantiq_ssc_writel(spi, SPI_WHBSTATE_SETEN, SPI_WHBSTATE); + lantiq_ssc_writel(spi, LTQ_SPI_WHBSTATE_SETEN, LTQ_SPI_WHBSTATE); } static void hw_setup_speed_hz(const struct lantiq_ssc_spi *spi, @@ -287,7 +291,7 @@ static void hw_setup_speed_hz(const struct lantiq_ssc_spi *spi, dev_dbg(spi->dev, "spi_clk %u, max_speed_hz %u, brt %u\n", spi_clk, max_speed_hz, brt); - lantiq_ssc_writel(spi, brt, SPI_BRT); + lantiq_ssc_writel(spi, brt, LTQ_SPI_BRT); } static void hw_setup_bits_per_word(const struct lantiq_ssc_spi *spi, @@ -296,9 +300,9 @@ static void hw_setup_bits_per_word(const struct lantiq_ssc_spi *spi, u32 bm; /* CON.BM value = bits_per_word - 1 */ - bm = (bits_per_word - 1) << SPI_CON_BM_S; + bm = (bits_per_word - 1) << LTQ_SPI_CON_BM_S; - lantiq_ssc_maskl(spi, SPI_CON_BM_M, bm, SPI_CON); + lantiq_ssc_maskl(spi, LTQ_SPI_CON_BM_M, bm, LTQ_SPI_CON); } static void hw_setup_clock_mode(const struct lantiq_ssc_spi *spi, @@ -315,28 +319,28 @@ static void hw_setup_clock_mode(const struct lantiq_ssc_spi *spi, * 3 1 1 1 0 */ if (mode & SPI_CPHA) - con_clr |= SPI_CON_PH; + con_clr |= LTQ_SPI_CON_PH; else - con_set |= SPI_CON_PH; + con_set |= LTQ_SPI_CON_PH; if (mode & SPI_CPOL) - con_set |= SPI_CON_PO | SPI_CON_IDLE; + con_set |= LTQ_SPI_CON_PO | LTQ_SPI_CON_IDLE; else - con_clr |= SPI_CON_PO | SPI_CON_IDLE; + con_clr |= LTQ_SPI_CON_PO | LTQ_SPI_CON_IDLE; /* Set heading control */ if (mode & SPI_LSB_FIRST) - con_clr |= SPI_CON_HB; + con_clr |= LTQ_SPI_CON_HB; else - con_set |= SPI_CON_HB; + con_set |= LTQ_SPI_CON_HB; /* Set loopback mode */ if (mode & SPI_LOOP) - con_set |= SPI_CON_LB; + con_set |= LTQ_SPI_CON_LB; else - con_clr |= SPI_CON_LB; + con_clr |= LTQ_SPI_CON_LB; - lantiq_ssc_maskl(spi, con_clr, con_set, SPI_CON); + lantiq_ssc_maskl(spi, con_clr, con_set, LTQ_SPI_CON); } static void lantiq_ssc_hw_init(const struct lantiq_ssc_spi *spi) @@ -347,37 +351,39 @@ static void lantiq_ssc_hw_init(const struct lantiq_ssc_spi *spi) * Set clock divider for run mode to 1 to * run at same frequency as FPI bus */ - lantiq_ssc_writel(spi, 1 << SPI_CLC_RMC_S, SPI_CLC); + lantiq_ssc_writel(spi, 1 << LTQ_SPI_CLC_RMC_S, LTQ_SPI_CLC); /* Put controller into config mode */ hw_enter_config_mode(spi); /* Clear error flags */ - lantiq_ssc_maskl(spi, 0, SPI_WHBSTATE_CLR_ERRORS, SPI_WHBSTATE); + lantiq_ssc_maskl(spi, 0, LTQ_SPI_WHBSTATE_CLR_ERRORS, LTQ_SPI_WHBSTATE); /* Enable error checking, disable TX/RX */ - lantiq_ssc_writel(spi, SPI_CON_RUEN | SPI_CON_AEN | SPI_CON_TEN | - SPI_CON_REN | SPI_CON_TXOFF | SPI_CON_RXOFF, SPI_CON); + lantiq_ssc_writel(spi, LTQ_SPI_CON_RUEN | LTQ_SPI_CON_AEN | + LTQ_SPI_CON_TEN | LTQ_SPI_CON_REN | LTQ_SPI_CON_TXOFF | + LTQ_SPI_CON_RXOFF, LTQ_SPI_CON); /* Setup default SPI mode */ hw_setup_bits_per_word(spi, spi->bits_per_word); hw_setup_clock_mode(spi, SPI_MODE_0); /* Enable master mode and clear error flags */ - lantiq_ssc_writel(spi, SPI_WHBSTATE_SETMS | SPI_WHBSTATE_CLR_ERRORS, - SPI_WHBSTATE); + lantiq_ssc_writel(spi, LTQ_SPI_WHBSTATE_SETMS | + LTQ_SPI_WHBSTATE_CLR_ERRORS, + LTQ_SPI_WHBSTATE); /* Reset GPIO/CS registers */ - lantiq_ssc_writel(spi, 0, SPI_GPOCON); - lantiq_ssc_writel(spi, 0xFF00, SPI_FPGO); + lantiq_ssc_writel(spi, 0, LTQ_SPI_GPOCON); + lantiq_ssc_writel(spi, 0xFF00, LTQ_SPI_FPGO); /* Enable and flush FIFOs */ rx_fifo_reset(spi); tx_fifo_reset(spi); /* Enable interrupts */ - lantiq_ssc_writel(spi, hwcfg->irnen_t | hwcfg->irnen_r | SPI_IRNEN_E, - SPI_IRNEN); + lantiq_ssc_writel(spi, hwcfg->irnen_t | hwcfg->irnen_r | + LTQ_SPI_IRNEN_E, LTQ_SPI_IRNEN); } static int lantiq_ssc_setup(struct spi_device *spidev) @@ -400,13 +406,13 @@ static int lantiq_ssc_setup(struct spi_device *spidev) } /* set GPO pin to CS mode */ - gpocon = 1 << ((cs - spi->base_cs) + SPI_GPOCON_ISCSBN_S); + gpocon = 1 << ((cs - spi->base_cs) + LTQ_SPI_GPOCON_ISCSBN_S); /* invert GPO pin */ if (spidev->mode & SPI_CS_HIGH) gpocon |= 1 << (cs - spi->base_cs); - lantiq_ssc_maskl(spi, 0, gpocon, SPI_GPOCON); + lantiq_ssc_maskl(spi, 0, gpocon, LTQ_SPI_GPOCON); return 0; } @@ -442,18 +448,18 @@ static void hw_setup_transfer(struct lantiq_ssc_spi *spi, } /* Configure transmitter and receiver */ - con = lantiq_ssc_readl(spi, SPI_CON); + con = lantiq_ssc_readl(spi, LTQ_SPI_CON); if (t->tx_buf) - con &= ~SPI_CON_TXOFF; + con &= ~LTQ_SPI_CON_TXOFF; else - con |= SPI_CON_TXOFF; + con |= LTQ_SPI_CON_TXOFF; if (t->rx_buf) - con &= ~SPI_CON_RXOFF; + con &= ~LTQ_SPI_CON_RXOFF; else - con |= SPI_CON_RXOFF; + con |= LTQ_SPI_CON_RXOFF; - lantiq_ssc_writel(spi, con, SPI_CON); + lantiq_ssc_writel(spi, con, LTQ_SPI_CON); } static int lantiq_ssc_unprepare_message(struct spi_master *master, @@ -464,7 +470,8 @@ static int lantiq_ssc_unprepare_message(struct spi_master *master, flush_workqueue(spi->wq); /* Disable transmitter and receiver while idle */ - lantiq_ssc_maskl(spi, 0, SPI_CON_TXOFF | SPI_CON_RXOFF, SPI_CON); + lantiq_ssc_maskl(spi, 0, LTQ_SPI_CON_TXOFF | LTQ_SPI_CON_RXOFF, + LTQ_SPI_CON); return 0; } @@ -503,7 +510,7 @@ static void tx_fifo_write(struct lantiq_ssc_spi *spi) break; } - lantiq_ssc_writel(spi, data, SPI_TB); + lantiq_ssc_writel(spi, data, LTQ_SPI_TB); tx_free--; } } @@ -517,7 +524,7 @@ static void rx_fifo_read_full_duplex(struct lantiq_ssc_spi *spi) unsigned int rx_fill = rx_fifo_level(spi); while (rx_fill) { - data = lantiq_ssc_readl(spi, SPI_RB); + data = lantiq_ssc_readl(spi, LTQ_SPI_RB); switch (spi->bits_per_word) { case 2 ... 8: @@ -563,9 +570,9 @@ static void rx_fifo_read_half_duplex(struct lantiq_ssc_spi *spi) */ while (rx_fill) { if (spi->rx_todo < 4) { - rxbv = (lantiq_ssc_readl(spi, SPI_STAT) & - SPI_STAT_RXBV_M) >> SPI_STAT_RXBV_S; - data = lantiq_ssc_readl(spi, SPI_RB); + rxbv = (lantiq_ssc_readl(spi, LTQ_SPI_STAT) & + LTQ_SPI_STAT_RXBV_M) >> LTQ_SPI_STAT_RXBV_S; + data = lantiq_ssc_readl(spi, LTQ_SPI_RB); shift = (rxbv - 1) * 8; rx8 = spi->rx; @@ -578,7 +585,7 @@ static void rx_fifo_read_half_duplex(struct lantiq_ssc_spi *spi) spi->rx++; } } else { - data = lantiq_ssc_readl(spi, SPI_RB); + data = lantiq_ssc_readl(spi, LTQ_SPI_RB); rx32 = (u32 *) spi->rx; *rx32++ = data; @@ -603,7 +610,7 @@ static void rx_request(struct lantiq_ssc_spi *spi) if (rxreq > rxreq_max) rxreq = rxreq_max; - lantiq_ssc_writel(spi, rxreq, SPI_RXREQ); + lantiq_ssc_writel(spi, rxreq, LTQ_SPI_RXREQ); } static irqreturn_t lantiq_ssc_xmit_interrupt(int irq, void *data) @@ -642,26 +649,26 @@ completed: static irqreturn_t lantiq_ssc_err_interrupt(int irq, void *data) { struct lantiq_ssc_spi *spi = data; - u32 stat = lantiq_ssc_readl(spi, SPI_STAT); + u32 stat = lantiq_ssc_readl(spi, LTQ_SPI_STAT); - if (!(stat & SPI_STAT_ERRORS)) + if (!(stat & LTQ_SPI_STAT_ERRORS)) return IRQ_NONE; - if (stat & SPI_STAT_RUE) + if (stat & LTQ_SPI_STAT_RUE) dev_err(spi->dev, "receive underflow error\n"); - if (stat & SPI_STAT_TUE) + if (stat & LTQ_SPI_STAT_TUE) dev_err(spi->dev, "transmit underflow error\n"); - if (stat & SPI_STAT_AE) + if (stat & LTQ_SPI_STAT_AE) dev_err(spi->dev, "abort error\n"); - if (stat & SPI_STAT_RE) + if (stat & LTQ_SPI_STAT_RE) dev_err(spi->dev, "receive overflow error\n"); - if (stat & SPI_STAT_TE) + if (stat & LTQ_SPI_STAT_TE) dev_err(spi->dev, "transmit overflow error\n"); - if (stat & SPI_STAT_ME) + if (stat & LTQ_SPI_STAT_ME) dev_err(spi->dev, "mode error\n"); /* Clear error flags */ - lantiq_ssc_maskl(spi, 0, SPI_WHBSTATE_CLR_ERRORS, SPI_WHBSTATE); + lantiq_ssc_maskl(spi, 0, LTQ_SPI_WHBSTATE_CLR_ERRORS, LTQ_SPI_WHBSTATE); /* set bad status so it can be retried */ if (spi->master->cur_msg) @@ -721,9 +728,9 @@ static void lantiq_ssc_bussy_work(struct work_struct *work) end = jiffies + msecs_to_jiffies(timeout); do { - u32 stat = lantiq_ssc_readl(spi, SPI_STAT); + u32 stat = lantiq_ssc_readl(spi, LTQ_SPI_STAT); - if (!(stat & SPI_STAT_BSY)) { + if (!(stat & LTQ_SPI_STAT_BSY)) { spi_finalize_current_transfer(spi->master); return; } @@ -755,9 +762,9 @@ static void lantiq_ssc_set_cs(struct spi_device *spidev, bool enable) if (!!(spidev->mode & SPI_CS_HIGH) == enable) fgpo = (1 << (cs - spi->base_cs)); else - fgpo = (1 << (cs - spi->base_cs + SPI_FGPO_SETOUTN_S)); + fgpo = (1 << (cs - spi->base_cs + LTQ_SPI_FGPO_SETOUTN_S)); - lantiq_ssc_writel(spi, fgpo, SPI_FPGO); + lantiq_ssc_writel(spi, fgpo, LTQ_SPI_FPGO); } static int lantiq_ssc_transfer_one(struct spi_master *master, @@ -772,13 +779,13 @@ static int lantiq_ssc_transfer_one(struct spi_master *master, } static const struct lantiq_ssc_hwcfg lantiq_ssc_xway = { - .irnen_r = SPI_IRNEN_R_XWAY, - .irnen_t = SPI_IRNEN_T_XWAY, + .irnen_r = LTQ_SPI_IRNEN_R_XWAY, + .irnen_t = LTQ_SPI_IRNEN_T_XWAY, }; static const struct lantiq_ssc_hwcfg lantiq_ssc_xrx = { - .irnen_r = SPI_IRNEN_R_XRX, - .irnen_t = SPI_IRNEN_T_XRX, + .irnen_r = LTQ_SPI_IRNEN_R_XRX, + .irnen_t = LTQ_SPI_IRNEN_T_XRX, }; static const struct of_device_id lantiq_ssc_match[] = { @@ -814,21 +821,21 @@ static int lantiq_ssc_probe(struct platform_device *pdev) return -ENXIO; } - rx_irq = platform_get_irq_byname(pdev, SPI_RX_IRQ_NAME); + rx_irq = platform_get_irq_byname(pdev, LTQ_SPI_RX_IRQ_NAME); if (rx_irq < 0) { - dev_err(dev, "failed to get %s\n", SPI_RX_IRQ_NAME); + dev_err(dev, "failed to get %s\n", LTQ_SPI_RX_IRQ_NAME); return -ENXIO; } - tx_irq = platform_get_irq_byname(pdev, SPI_TX_IRQ_NAME); + tx_irq = platform_get_irq_byname(pdev, LTQ_SPI_TX_IRQ_NAME); if (tx_irq < 0) { - dev_err(dev, "failed to get %s\n", SPI_TX_IRQ_NAME); + dev_err(dev, "failed to get %s\n", LTQ_SPI_TX_IRQ_NAME); return -ENXIO; } - err_irq = platform_get_irq_byname(pdev, SPI_ERR_IRQ_NAME); + err_irq = platform_get_irq_byname(pdev, LTQ_SPI_ERR_IRQ_NAME); if (err_irq < 0) { - dev_err(dev, "failed to get %s\n", SPI_ERR_IRQ_NAME); + dev_err(dev, "failed to get %s\n", LTQ_SPI_ERR_IRQ_NAME); return -ENXIO; } @@ -849,17 +856,17 @@ static int lantiq_ssc_probe(struct platform_device *pdev) } err = devm_request_irq(dev, rx_irq, lantiq_ssc_xmit_interrupt, - 0, SPI_RX_IRQ_NAME, spi); + 0, LTQ_SPI_RX_IRQ_NAME, spi); if (err) goto err_master_put; err = devm_request_irq(dev, tx_irq, lantiq_ssc_xmit_interrupt, - 0, SPI_TX_IRQ_NAME, spi); + 0, LTQ_SPI_TX_IRQ_NAME, spi); if (err) goto err_master_put; err = devm_request_irq(dev, err_irq, lantiq_ssc_err_interrupt, - 0, SPI_ERR_IRQ_NAME, spi); + 0, LTQ_SPI_ERR_IRQ_NAME, spi); if (err) goto err_master_put; @@ -916,11 +923,11 @@ static int lantiq_ssc_probe(struct platform_device *pdev) } INIT_WORK(&spi->work, lantiq_ssc_bussy_work); - id = lantiq_ssc_readl(spi, SPI_ID); - spi->tx_fifo_size = (id & SPI_ID_TXFS_M) >> SPI_ID_TXFS_S; - spi->rx_fifo_size = (id & SPI_ID_RXFS_M) >> SPI_ID_RXFS_S; - supports_dma = (id & SPI_ID_CFG_M) >> SPI_ID_CFG_S; - revision = id & SPI_ID_REV_M; + id = lantiq_ssc_readl(spi, LTQ_SPI_ID); + spi->tx_fifo_size = (id & LTQ_SPI_ID_TXFS_M) >> LTQ_SPI_ID_TXFS_S; + spi->rx_fifo_size = (id & LTQ_SPI_ID_RXFS_M) >> LTQ_SPI_ID_RXFS_S; + supports_dma = (id & LTQ_SPI_ID_CFG_M) >> LTQ_SPI_ID_CFG_S; + revision = id & LTQ_SPI_ID_REV_M; lantiq_ssc_hw_init(spi); @@ -952,8 +959,8 @@ static int lantiq_ssc_remove(struct platform_device *pdev) { struct lantiq_ssc_spi *spi = platform_get_drvdata(pdev); - lantiq_ssc_writel(spi, 0, SPI_IRNEN); - lantiq_ssc_writel(spi, 0, SPI_CLC); + lantiq_ssc_writel(spi, 0, LTQ_SPI_IRNEN); + lantiq_ssc_writel(spi, 0, LTQ_SPI_CLC); rx_fifo_flush(spi); tx_fifo_flush(spi); hw_enter_config_mode(spi); diff --git a/drivers/spi/spi-pl022.c b/drivers/spi/spi-pl022.c index f7f7ba17b40e..2f76e022cc59 100644 --- a/drivers/spi/spi-pl022.c +++ b/drivers/spi/spi-pl022.c @@ -2074,7 +2074,7 @@ pl022_platform_data_dt_get(struct device *dev) { struct device_node *np = dev->of_node; struct pl022_ssp_controller *pd; - u32 tmp; + u32 tmp = 0; if (!np) { dev_err(dev, "no dt node defined\n"); diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index f274df9e0e3e..b4a8bb7759b2 100644 --- a/drivers/spi/spi.c +++ b/drivers/spi/spi.c @@ -33,6 +33,7 @@ #include <linux/pm_domain.h> #include <linux/export.h> #include <linux/sched/rt.h> +#include <uapi/linux/sched/types.h> #include <linux/delay.h> #include <linux/kthread.h> #include <linux/ioport.h> @@ -1014,7 +1015,7 @@ static int spi_transfer_one_message(struct spi_master *master, ret = 0; ms = 8LL * 1000LL * xfer->len; do_div(ms, xfer->speed_hz); - ms += ms + 100; /* some tolerance */ + ms += ms + 200; /* some tolerance */ if (ms > UINT_MAX) ms = UINT_MAX; @@ -1738,13 +1739,15 @@ static acpi_status acpi_register_spi_device(struct spi_master *master, return AE_OK; } + acpi_set_modalias(adev, acpi_device_hid(adev), spi->modalias, + sizeof(spi->modalias)); + if (spi->irq < 0) spi->irq = acpi_dev_gpio_irq_get(adev, 0); acpi_device_set_enumerated(adev); adev->power.flags.ignore_parent = true; - strlcpy(spi->modalias, acpi_device_hid(adev), sizeof(spi->modalias)); if (spi_add_device(spi)) { adev->power.flags.ignore_parent = false; dev_err(&master->dev, "failed to add SPI device %s from ACPI\n", |