diff options
Diffstat (limited to 'drivers/spi/spi-s3c64xx.c')
| -rw-r--r-- | drivers/spi/spi-s3c64xx.c | 481 |
1 files changed, 409 insertions, 72 deletions
diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 3c36cfaa1b93..0dedbbdb153a 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -27,10 +27,15 @@ #include <linux/platform_device.h> #include <linux/pm_runtime.h> #include <linux/spi/spi.h> +#include <linux/gpio.h> +#include <linux/of.h> +#include <linux/of_gpio.h> #include <mach/dma.h> #include <plat/s3c64xx-spi.h> +#define MAX_SPI_PORTS 3 + /* Registers and bit-fields */ #define S3C64XX_SPI_CH_CFG 0x00 @@ -113,13 +118,12 @@ #define S3C64XX_SPI_FBCLK_MSK (3<<0) -#define S3C64XX_SPI_ST_TRLCNTZ(v, i) ((((v) >> (i)->rx_lvl_offset) & \ - (((i)->fifo_lvl_mask + 1))) \ - ? 1 : 0) - -#define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & (1 << (i)->tx_st_done)) ? 1 : 0) -#define TX_FIFO_LVL(v, i) (((v) >> 6) & (i)->fifo_lvl_mask) -#define RX_FIFO_LVL(v, i) (((v) >> (i)->rx_lvl_offset) & (i)->fifo_lvl_mask) +#define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id]) +#define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \ + (1 << (i)->port_conf->tx_st_done)) ? 1 : 0) +#define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i)) +#define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \ + FIFO_LVL_MASK(i)) #define S3C64XX_SPI_MAX_TRAILCNT 0x3ff #define S3C64XX_SPI_TRAILCNT_OFF 19 @@ -135,6 +139,29 @@ struct s3c64xx_spi_dma_data { unsigned ch; enum dma_data_direction direction; enum dma_ch dmach; + struct property *dma_prop; +}; + +/** + * struct s3c64xx_spi_info - SPI Controller hardware info + * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register. + * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter. + * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter. + * @high_speed: True, if the controller supports HIGH_SPEED_EN bit. + * @clk_from_cmu: True, if the controller does not include a clock mux and + * prescaler unit. + * + * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but + * differ in some aspects such as the size of the fifo and spi bus clock + * setup. Such differences are specified to the driver using this structure + * which is provided as driver data to the driver. + */ +struct s3c64xx_spi_port_config { + int fifo_lvl_mask[MAX_SPI_PORTS]; + int rx_lvl_offset; + int tx_st_done; + bool high_speed; + bool clk_from_cmu; }; /** @@ -175,6 +202,9 @@ struct s3c64xx_spi_driver_data { struct s3c64xx_spi_dma_data rx_dma; struct s3c64xx_spi_dma_data tx_dma; struct samsung_dma_ops *ops; + struct s3c64xx_spi_port_config *port_conf; + unsigned int port_id; + unsigned long gpios[4]; }; static struct s3c2410_dma_client s3c64xx_spi_dma_client = { @@ -183,7 +213,6 @@ static struct s3c2410_dma_client s3c64xx_spi_dma_client = { static void flush_fifo(struct s3c64xx_spi_driver_data *sdd) { - struct s3c64xx_spi_info *sci = sdd->cntrlr_info; void __iomem *regs = sdd->regs; unsigned long loops; u32 val; @@ -199,7 +228,7 @@ static void flush_fifo(struct s3c64xx_spi_driver_data *sdd) loops = msecs_to_loops(1); do { val = readl(regs + S3C64XX_SPI_STATUS); - } while (TX_FIFO_LVL(val, sci) && loops--); + } while (TX_FIFO_LVL(val, sdd) && loops--); if (loops == 0) dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n"); @@ -208,7 +237,7 @@ static void flush_fifo(struct s3c64xx_spi_driver_data *sdd) loops = msecs_to_loops(1); do { val = readl(regs + S3C64XX_SPI_STATUS); - if (RX_FIFO_LVL(val, sci)) + if (RX_FIFO_LVL(val, sdd)) readl(regs + S3C64XX_SPI_RX_DATA); else break; @@ -301,7 +330,9 @@ static int acquire_dma(struct s3c64xx_spi_driver_data *sdd) req.cap = DMA_SLAVE; req.client = &s3c64xx_spi_dma_client; + req.dt_dmach_prop = sdd->rx_dma.dma_prop; sdd->rx_dma.ch = sdd->ops->request(sdd->rx_dma.dmach, &req); + req.dt_dmach_prop = sdd->tx_dma.dma_prop; sdd->tx_dma.ch = sdd->ops->request(sdd->tx_dma.dmach, &req); return 1; @@ -311,7 +342,6 @@ static void enable_datapath(struct s3c64xx_spi_driver_data *sdd, struct spi_device *spi, struct spi_transfer *xfer, int dma_mode) { - struct s3c64xx_spi_info *sci = sdd->cntrlr_info; void __iomem *regs = sdd->regs; u32 modecfg, chcfg; @@ -361,7 +391,7 @@ static void enable_datapath(struct s3c64xx_spi_driver_data *sdd, if (xfer->rx_buf != NULL) { sdd->state |= RXBUSY; - if (sci->high_speed && sdd->cur_speed >= 30000000UL + if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL && !(sdd->cur_mode & SPI_CPHA)) chcfg |= S3C64XX_SPI_CH_HS_EN; @@ -388,20 +418,19 @@ static inline void enable_cs(struct s3c64xx_spi_driver_data *sdd, if (sdd->tgl_spi != spi) { /* if last mssg on diff device */ /* Deselect the last toggled device */ cs = sdd->tgl_spi->controller_data; - cs->set_level(cs->line, - spi->mode & SPI_CS_HIGH ? 0 : 1); + gpio_set_value(cs->line, + spi->mode & SPI_CS_HIGH ? 0 : 1); } sdd->tgl_spi = NULL; } cs = spi->controller_data; - cs->set_level(cs->line, spi->mode & SPI_CS_HIGH ? 1 : 0); + gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 1 : 0); } static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd, struct spi_transfer *xfer, int dma_mode) { - struct s3c64xx_spi_info *sci = sdd->cntrlr_info; void __iomem *regs = sdd->regs; unsigned long val; int ms; @@ -418,7 +447,7 @@ static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd, val = msecs_to_loops(ms); do { status = readl(regs + S3C64XX_SPI_STATUS); - } while (RX_FIFO_LVL(status, sci) < xfer->len && --val); + } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val); } if (!val) @@ -437,8 +466,8 @@ static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd, if (xfer->rx_buf == NULL) { val = msecs_to_loops(10); status = readl(regs + S3C64XX_SPI_STATUS); - while ((TX_FIFO_LVL(status, sci) - || !S3C64XX_SPI_ST_TX_DONE(status, sci)) + while ((TX_FIFO_LVL(status, sdd) + || !S3C64XX_SPI_ST_TX_DONE(status, sdd)) && --val) { cpu_relax(); status = readl(regs + S3C64XX_SPI_STATUS); @@ -482,17 +511,16 @@ static inline void disable_cs(struct s3c64xx_spi_driver_data *sdd, if (sdd->tgl_spi == spi) sdd->tgl_spi = NULL; - cs->set_level(cs->line, spi->mode & SPI_CS_HIGH ? 0 : 1); + gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 0 : 1); } static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd) { - struct s3c64xx_spi_info *sci = sdd->cntrlr_info; void __iomem *regs = sdd->regs; u32 val; /* Disable Clock */ - if (sci->clk_from_cmu) { + if (sdd->port_conf->clk_from_cmu) { clk_disable(sdd->src_clk); } else { val = readl(regs + S3C64XX_SPI_CLK_CFG); @@ -536,7 +564,7 @@ static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd) writel(val, regs + S3C64XX_SPI_MODE_CFG); - if (sci->clk_from_cmu) { + if (sdd->port_conf->clk_from_cmu) { /* Configure Clock */ /* There is half-multiplier before the SPI */ clk_set_rate(sdd->src_clk, sdd->cur_speed * 2); @@ -562,7 +590,6 @@ static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd) static int s3c64xx_spi_map_mssg(struct s3c64xx_spi_driver_data *sdd, struct spi_message *msg) { - struct s3c64xx_spi_info *sci = sdd->cntrlr_info; struct device *dev = &sdd->pdev->dev; struct spi_transfer *xfer; @@ -578,7 +605,7 @@ static int s3c64xx_spi_map_mssg(struct s3c64xx_spi_driver_data *sdd, /* Map until end or first fail */ list_for_each_entry(xfer, &msg->transfers, transfer_list) { - if (xfer->len <= ((sci->fifo_lvl_mask >> 1) + 1)) + if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1)) continue; if (xfer->tx_buf != NULL) { @@ -612,7 +639,6 @@ static int s3c64xx_spi_map_mssg(struct s3c64xx_spi_driver_data *sdd, static void s3c64xx_spi_unmap_mssg(struct s3c64xx_spi_driver_data *sdd, struct spi_message *msg) { - struct s3c64xx_spi_info *sci = sdd->cntrlr_info; struct device *dev = &sdd->pdev->dev; struct spi_transfer *xfer; @@ -621,7 +647,7 @@ static void s3c64xx_spi_unmap_mssg(struct s3c64xx_spi_driver_data *sdd, list_for_each_entry(xfer, &msg->transfers, transfer_list) { - if (xfer->len <= ((sci->fifo_lvl_mask >> 1) + 1)) + if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1)) continue; if (xfer->rx_buf != NULL @@ -640,7 +666,6 @@ static int s3c64xx_spi_transfer_one_message(struct spi_master *master, struct spi_message *msg) { struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); - struct s3c64xx_spi_info *sci = sdd->cntrlr_info; struct spi_device *spi = msg->spi; struct s3c64xx_spi_csinfo *cs = spi->controller_data; struct spi_transfer *xfer; @@ -695,7 +720,7 @@ static int s3c64xx_spi_transfer_one_message(struct spi_master *master, } /* Polling method for xfers not bigger than FIFO capacity */ - if (xfer->len <= ((sci->fifo_lvl_mask >> 1) + 1)) + if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1)) use_dma = 0; else use_dma = 1; @@ -800,6 +825,48 @@ static int s3c64xx_spi_unprepare_transfer(struct spi_master *spi) return 0; } +static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata( + struct s3c64xx_spi_driver_data *sdd, + struct spi_device *spi) +{ + struct s3c64xx_spi_csinfo *cs; + struct device_node *slave_np, *data_np; + u32 fb_delay = 0; + + slave_np = spi->dev.of_node; + if (!slave_np) { + dev_err(&spi->dev, "device node not found\n"); + return ERR_PTR(-EINVAL); + } + + for_each_child_of_node(slave_np, data_np) + if (!strcmp(data_np->name, "controller-data")) + break; + if (!data_np) { + dev_err(&spi->dev, "child node 'controller-data' not found\n"); + return ERR_PTR(-EINVAL); + } + + cs = kzalloc(sizeof(*cs), GFP_KERNEL); + if (!cs) { + dev_err(&spi->dev, "could not allocate memory for controller" + " data\n"); + return ERR_PTR(-ENOMEM); + } + + cs->line = of_get_named_gpio(data_np, "cs-gpio", 0); + if (!gpio_is_valid(cs->line)) { + dev_err(&spi->dev, "chip select gpio is not specified or " + "invalid\n"); + kfree(cs); + return ERR_PTR(-EINVAL); + } + + of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay); + cs->fb_delay = fb_delay; + return cs; +} + /* * Here we only check the validity of requested configuration * and save the configuration in a local data-structure. @@ -813,14 +880,30 @@ static int s3c64xx_spi_setup(struct spi_device *spi) struct s3c64xx_spi_info *sci; struct spi_message *msg; unsigned long flags; - int err = 0; + int err; - if (cs == NULL || cs->set_level == NULL) { + sdd = spi_master_get_devdata(spi->master); + if (!cs && spi->dev.of_node) { + cs = s3c64xx_get_slave_ctrldata(sdd, spi); + spi->controller_data = cs; + } + + if (IS_ERR_OR_NULL(cs)) { dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select); return -ENODEV; } - sdd = spi_master_get_devdata(spi->master); + if (!spi_get_ctldata(spi)) { + err = gpio_request(cs->line, dev_name(&spi->dev)); + if (err) { + dev_err(&spi->dev, "request for slave select gpio " + "line [%d] failed\n", cs->line); + err = -EBUSY; + goto err_gpio_req; + } + spi_set_ctldata(spi, cs); + } + sci = sdd->cntrlr_info; spin_lock_irqsave(&sdd->lock, flags); @@ -831,7 +914,8 @@ static int s3c64xx_spi_setup(struct spi_device *spi) dev_err(&spi->dev, "setup: attempt while mssg in queue!\n"); spin_unlock_irqrestore(&sdd->lock, flags); - return -EBUSY; + err = -EBUSY; + goto err_msgq; } } @@ -849,7 +933,7 @@ static int s3c64xx_spi_setup(struct spi_device *spi) pm_runtime_get_sync(&sdd->pdev->dev); /* Check if we can provide the requested rate */ - if (!sci->clk_from_cmu) { + if (!sdd->port_conf->clk_from_cmu) { u32 psr, speed; /* Max possible */ @@ -874,22 +958,44 @@ static int s3c64xx_spi_setup(struct spi_device *spi) } speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1); - if (spi->max_speed_hz >= speed) + if (spi->max_speed_hz >= speed) { spi->max_speed_hz = speed; - else + } else { err = -EINVAL; + goto setup_exit; + } } pm_runtime_put(&sdd->pdev->dev); + disable_cs(sdd, spi); + return 0; setup_exit: - /* setup() returns with device de-selected */ disable_cs(sdd, spi); +err_msgq: + gpio_free(cs->line); + spi_set_ctldata(spi, NULL); + +err_gpio_req: + kfree(cs); + return err; } +static void s3c64xx_spi_cleanup(struct spi_device *spi) +{ + struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi); + + if (cs) { + gpio_free(cs->line); + if (spi->dev.of_node) + kfree(cs); + } + spi_set_ctldata(spi, NULL); +} + static irqreturn_t s3c64xx_spi_irq(int irq, void *data) { struct s3c64xx_spi_driver_data *sdd = data; @@ -930,7 +1036,7 @@ static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel) /* Disable Interrupts - we use Polling if not DMA mode */ writel(0, regs + S3C64XX_SPI_INT_EN); - if (!sci->clk_from_cmu) + if (!sdd->port_conf->clk_from_cmu) writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT, regs + S3C64XX_SPI_CLK_CFG); writel(0, regs + S3C64XX_SPI_MODE_CFG); @@ -951,40 +1057,164 @@ static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel) flush_fifo(sdd); } -static int __init s3c64xx_spi_probe(struct platform_device *pdev) +static int __devinit s3c64xx_spi_get_dmares( + struct s3c64xx_spi_driver_data *sdd, bool tx) +{ + struct platform_device *pdev = sdd->pdev; + struct s3c64xx_spi_dma_data *dma_data; + struct property *prop; + struct resource *res; + char prop_name[15], *chan_str; + + if (tx) { + dma_data = &sdd->tx_dma; + dma_data->direction = DMA_TO_DEVICE; + chan_str = "tx"; + } else { + dma_data = &sdd->rx_dma; + dma_data->direction = DMA_FROM_DEVICE; + chan_str = "rx"; + } + + if (!sdd->pdev->dev.of_node) { + res = platform_get_resource(pdev, IORESOURCE_DMA, tx ? 0 : 1); + if (!res) { + dev_err(&pdev->dev, "Unable to get SPI-%s dma " + "resource\n", chan_str); + return -ENXIO; + } + dma_data->dmach = res->start; + return 0; + } + + sprintf(prop_name, "%s-dma-channel", chan_str); + prop = of_find_property(pdev->dev.of_node, prop_name, NULL); + if (!prop) { + dev_err(&pdev->dev, "%s dma channel property not specified\n", + chan_str); + return -ENXIO; + } + + dma_data->dmach = DMACH_DT_PROP; + dma_data->dma_prop = prop; + return 0; +} + +#ifdef CONFIG_OF +static int s3c64xx_spi_parse_dt_gpio(struct s3c64xx_spi_driver_data *sdd) +{ + struct device *dev = &sdd->pdev->dev; + int idx, gpio, ret; + + /* find gpios for mosi, miso and clock lines */ + for (idx = 0; idx < 3; idx++) { + gpio = of_get_gpio(dev->of_node, idx); + if (!gpio_is_valid(gpio)) { + dev_err(dev, "invalid gpio[%d]: %d\n", idx, gpio); + goto free_gpio; + } + + ret = gpio_request(gpio, "spi-bus"); + if (ret) { + dev_err(dev, "gpio [%d] request failed\n", gpio); + goto free_gpio; + } + } + return 0; + +free_gpio: + while (--idx >= 0) + gpio_free(sdd->gpios[idx]); + return -EINVAL; +} + +static void s3c64xx_spi_dt_gpio_free(struct s3c64xx_spi_driver_data *sdd) +{ + unsigned int idx; + for (idx = 0; idx < 3; idx++) + gpio_free(sdd->gpios[idx]); +} + +static struct __devinit s3c64xx_spi_info * s3c64xx_spi_parse_dt( + struct device *dev) { - struct resource *mem_res, *dmatx_res, *dmarx_res; - struct s3c64xx_spi_driver_data *sdd; struct s3c64xx_spi_info *sci; - struct spi_master *master; - int ret, irq; - char clk_name[16]; + u32 temp; - if (pdev->id < 0) { - dev_err(&pdev->dev, - "Invalid platform device id-%d\n", pdev->id); - return -ENODEV; + sci = devm_kzalloc(dev, sizeof(*sci), GFP_KERNEL); + if (!sci) { + dev_err(dev, "memory allocation for spi_info failed\n"); + return ERR_PTR(-ENOMEM); } - if (pdev->dev.platform_data == NULL) { - dev_err(&pdev->dev, "platform_data missing!\n"); - return -ENODEV; + if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) { + dev_warn(dev, "spi bus clock parent not specified, using " + "clock at index 0 as parent\n"); + sci->src_clk_nr = 0; + } else { + sci->src_clk_nr = temp; } - sci = pdev->dev.platform_data; + if (of_property_read_u32(dev->of_node, "num-cs", &temp)) { + dev_warn(dev, "number of chip select lines not specified, " + "assuming 1 chip select line\n"); + sci->num_cs = 1; + } else { + sci->num_cs = temp; + } + + return sci; +} +#else +static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev) +{ + return dev->platform_data; +} + +static int s3c64xx_spi_parse_dt_gpio(struct s3c64xx_spi_driver_data *sdd) +{ + return -EINVAL; +} - /* Check for availability of necessary resource */ +static void s3c64xx_spi_dt_gpio_free(struct s3c64xx_spi_driver_data *sdd) +{ +} +#endif - dmatx_res = platform_get_resource(pdev, IORESOURCE_DMA, 0); - if (dmatx_res == NULL) { - dev_err(&pdev->dev, "Unable to get SPI-Tx dma resource\n"); - return -ENXIO; +static const struct of_device_id s3c64xx_spi_dt_match[]; + +static inline struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config( + struct platform_device *pdev) +{ +#ifdef CONFIG_OF + if (pdev->dev.of_node) { + const struct of_device_id *match; + match = of_match_node(s3c64xx_spi_dt_match, pdev->dev.of_node); + return (struct s3c64xx_spi_port_config *)match->data; } +#endif + return (struct s3c64xx_spi_port_config *) + platform_get_device_id(pdev)->driver_data; +} - dmarx_res = platform_get_resource(pdev, IORESOURCE_DMA, 1); - if (dmarx_res == NULL) { - dev_err(&pdev->dev, "Unable to get SPI-Rx dma resource\n"); - return -ENXIO; +static int __init s3c64xx_spi_probe(struct platform_device *pdev) +{ + struct resource *mem_res; + struct s3c64xx_spi_driver_data *sdd; + struct s3c64xx_spi_info *sci = pdev->dev.platform_data; + struct spi_master *master; + int ret, irq; + char clk_name[16]; + + if (!sci && pdev->dev.of_node) { + sci = s3c64xx_spi_parse_dt(&pdev->dev); + if (IS_ERR(sci)) + return PTR_ERR(sci); + } + + if (!sci) { + dev_err(&pdev->dev, "platform_data missing!\n"); + return -ENODEV; } mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); @@ -1009,19 +1239,37 @@ static int __init s3c64xx_spi_probe(struct platform_device *pdev) platform_set_drvdata(pdev, master); sdd = spi_master_get_devdata(master); + sdd->port_conf = s3c64xx_spi_get_port_config(pdev); sdd->master = master; sdd->cntrlr_info = sci; sdd->pdev = pdev; sdd->sfr_start = mem_res->start; - sdd->tx_dma.dmach = dmatx_res->start; - sdd->tx_dma.direction = DMA_MEM_TO_DEV; - sdd->rx_dma.dmach = dmarx_res->start; - sdd->rx_dma.direction = DMA_DEV_TO_MEM; + if (pdev->dev.of_node) { + ret = of_alias_get_id(pdev->dev.of_node, "spi"); + if (ret < 0) { + dev_err(&pdev->dev, "failed to get alias id, " + "errno %d\n", ret); + goto err0; + } + sdd->port_id = ret; + } else { + sdd->port_id = pdev->id; + } sdd->cur_bpw = 8; - master->bus_num = pdev->id; + ret = s3c64xx_spi_get_dmares(sdd, true); + if (ret) + goto err0; + + ret = s3c64xx_spi_get_dmares(sdd, false); + if (ret) + goto err0; + + master->dev.of_node = pdev->dev.of_node; + master->bus_num = sdd->port_id; master->setup = s3c64xx_spi_setup; + master->cleanup = s3c64xx_spi_cleanup; master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer; master->transfer_one_message = s3c64xx_spi_transfer_one_message; master->unprepare_transfer_hardware = s3c64xx_spi_unprepare_transfer; @@ -1044,7 +1292,10 @@ static int __init s3c64xx_spi_probe(struct platform_device *pdev) goto err1; } - if (sci->cfg_gpio == NULL || sci->cfg_gpio(pdev)) { + if (!sci->cfg_gpio && pdev->dev.of_node) { + if (s3c64xx_spi_parse_dt_gpio(sdd)) + return -EBUSY; + } else if (sci->cfg_gpio == NULL || sci->cfg_gpio()) { dev_err(&pdev->dev, "Unable to config gpio\n"); ret = -EBUSY; goto err2; @@ -1080,7 +1331,7 @@ static int __init s3c64xx_spi_probe(struct platform_device *pdev) } /* Setup Deufult Mode */ - s3c64xx_spi_hwinit(sdd, pdev->id); + s3c64xx_spi_hwinit(sdd, sdd->port_id); spin_lock_init(&sdd->lock); init_completion(&sdd->xfer_completion); @@ -1105,7 +1356,7 @@ static int __init s3c64xx_spi_probe(struct platform_device *pdev) dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d " "with %d Slaves attached\n", - pdev->id, master->num_chipselect); + sdd->port_id, master->num_chipselect); dev_dbg(&pdev->dev, "\tIOmem=[0x%x-0x%x]\tDMA=[Rx-%d, Tx-%d]\n", mem_res->end, mem_res->start, sdd->rx_dma.dmach, sdd->tx_dma.dmach); @@ -1125,6 +1376,8 @@ err5: err4: clk_put(sdd->clk); err3: + if (!sdd->cntrlr_info->cfg_gpio && pdev->dev.of_node) + s3c64xx_spi_dt_gpio_free(sdd); err2: iounmap((void *) sdd->regs); err1: @@ -1156,6 +1409,9 @@ static int s3c64xx_spi_remove(struct platform_device *pdev) clk_disable(sdd->clk); clk_put(sdd->clk); + if (!sdd->cntrlr_info->cfg_gpio && pdev->dev.of_node) + s3c64xx_spi_dt_gpio_free(sdd); + iounmap((void *) sdd->regs); mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); @@ -1180,6 +1436,9 @@ static int s3c64xx_spi_suspend(struct device *dev) clk_disable(sdd->src_clk); clk_disable(sdd->clk); + if (!sdd->cntrlr_info->cfg_gpio && dev->of_node) + s3c64xx_spi_dt_gpio_free(sdd); + sdd->cur_speed = 0; /* Output Clock is stopped */ return 0; @@ -1187,18 +1446,20 @@ static int s3c64xx_spi_suspend(struct device *dev) static int s3c64xx_spi_resume(struct device *dev) { - struct platform_device *pdev = to_platform_device(dev); struct spi_master *master = spi_master_get(dev_get_drvdata(dev)); struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); struct s3c64xx_spi_info *sci = sdd->cntrlr_info; - sci->cfg_gpio(pdev); + if (!sci->cfg_gpio && dev->of_node) + s3c64xx_spi_parse_dt_gpio(sdd); + else + sci->cfg_gpio(); /* Enable the clock */ clk_enable(sdd->src_clk); clk_enable(sdd->clk); - s3c64xx_spi_hwinit(sdd, pdev->id); + s3c64xx_spi_hwinit(sdd, sdd->port_id); spi_master_resume(master); @@ -1236,13 +1497,89 @@ static const struct dev_pm_ops s3c64xx_spi_pm = { s3c64xx_spi_runtime_resume, NULL) }; +struct s3c64xx_spi_port_config s3c2443_spi_port_config = { + .fifo_lvl_mask = { 0x7f }, + .rx_lvl_offset = 13, + .tx_st_done = 21, + .high_speed = true, +}; + +struct s3c64xx_spi_port_config s3c6410_spi_port_config = { + .fifo_lvl_mask = { 0x7f, 0x7F }, + .rx_lvl_offset = 13, + .tx_st_done = 21, +}; + +struct s3c64xx_spi_port_config s5p64x0_spi_port_config = { + .fifo_lvl_mask = { 0x1ff, 0x7F }, + .rx_lvl_offset = 15, + .tx_st_done = 25, +}; + +struct s3c64xx_spi_port_config s5pc100_spi_port_config = { + .fifo_lvl_mask = { 0x7f, 0x7F }, + .rx_lvl_offset = 13, + .tx_st_done = 21, + .high_speed = true, +}; + +struct s3c64xx_spi_port_config s5pv210_spi_port_config = { + .fifo_lvl_mask = { 0x1ff, 0x7F }, + .rx_lvl_offset = 15, + .tx_st_done = 25, + .high_speed = true, +}; + +struct s3c64xx_spi_port_config exynos4_spi_port_config = { + .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F }, + .rx_lvl_offset = 15, + .tx_st_done = 25, + .high_speed = true, + .clk_from_cmu = true, +}; + +static struct platform_device_id s3c64xx_spi_driver_ids[] = { + { + .name = "s3c2443-spi", + .driver_data = (kernel_ulong_t)&s3c2443_spi_port_config, + }, { + .name = "s3c6410-spi", + .driver_data = (kernel_ulong_t)&s3c6410_spi_port_config, + }, { + .name = "s5p64x0-spi", + .driver_data = (kernel_ulong_t)&s5p64x0_spi_port_config, + }, { + .name = "s5pc100-spi", + .driver_data = (kernel_ulong_t)&s5pc100_spi_port_config, + }, { + .name = "s5pv210-spi", + .driver_data = (kernel_ulong_t)&s5pv210_spi_port_config, + }, { + .name = "exynos4210-spi", + .driver_data = (kernel_ulong_t)&exynos4_spi_port_config, + }, + { }, +}; + +#ifdef CONFIG_OF +static const struct of_device_id s3c64xx_spi_dt_match[] = { + { .compatible = "samsung,exynos4210-spi", + .data = (void *)&exynos4_spi_port_config, + }, + { }, +}; +MODULE_DEVICE_TABLE(of, s3c64xx_spi_dt_match); +#endif /* CONFIG_OF */ + static struct platform_driver s3c64xx_spi_driver = { .driver = { .name = "s3c64xx-spi", .owner = THIS_MODULE, .pm = &s3c64xx_spi_pm, + .of_match_table = of_match_ptr(s3c64xx_spi_dt_match), }, .remove = s3c64xx_spi_remove, + .id_table = s3c64xx_spi_driver_ids, }; MODULE_ALIAS("platform:s3c64xx-spi"); |