diff options
Diffstat (limited to 'drivers/pinctrl')
| -rw-r--r-- | drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 30 | ||||
| -rw-r--r-- | drivers/pinctrl/aspeed/pinmux-aspeed.c | 7 | ||||
| -rw-r--r-- | drivers/pinctrl/aspeed/pinmux-aspeed.h | 7 | ||||
| -rw-r--r-- | drivers/pinctrl/intel/pinctrl-baytrail.c | 16 | ||||
| -rw-r--r-- | drivers/pinctrl/intel/pinctrl-cherryview.c | 42 | ||||
| -rw-r--r-- | drivers/pinctrl/pinctrl-stmfx.c | 18 | ||||
| -rw-r--r-- | drivers/pinctrl/qcom/Kconfig | 1 | ||||
| -rw-r--r-- | drivers/pinctrl/qcom/pinctrl-msm.c | 23 | ||||
| -rw-r--r-- | drivers/pinctrl/qcom/pinctrl-spmi-gpio.c | 92 |
9 files changed, 131 insertions, 105 deletions
diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c index 09042fca62b8..d8a804b9f958 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c @@ -2659,7 +2659,7 @@ static struct regmap *aspeed_g5_acquire_regmap(struct aspeed_pinmux_data *ctx, if (IS_ERR(map)) return map; } else - map = ERR_PTR(-ENODEV); + return ERR_PTR(-ENODEV); ctx->maps[ASPEED_IP_LPC] = map; dev_dbg(ctx->dev, "Acquired LPC regmap"); @@ -2669,6 +2669,33 @@ static struct regmap *aspeed_g5_acquire_regmap(struct aspeed_pinmux_data *ctx, return ERR_PTR(-EINVAL); } +static int aspeed_g5_sig_expr_eval(struct aspeed_pinmux_data *ctx, + const struct aspeed_sig_expr *expr, + bool enabled) +{ + int ret; + int i; + + for (i = 0; i < expr->ndescs; i++) { + const struct aspeed_sig_desc *desc = &expr->descs[i]; + struct regmap *map; + + map = aspeed_g5_acquire_regmap(ctx, desc->ip); + if (IS_ERR(map)) { + dev_err(ctx->dev, + "Failed to acquire regmap for IP block %d\n", + desc->ip); + return PTR_ERR(map); + } + + ret = aspeed_sig_desc_eval(desc, enabled, ctx->maps[desc->ip]); + if (ret <= 0) + return ret; + } + + return 1; +} + /** * Configure a pin's signal by applying an expression's descriptor state for * all descriptors in the expression. @@ -2754,6 +2781,7 @@ static int aspeed_g5_sig_expr_set(struct aspeed_pinmux_data *ctx, } static const struct aspeed_pinmux_ops aspeed_g5_ops = { + .eval = aspeed_g5_sig_expr_eval, .set = aspeed_g5_sig_expr_set, }; diff --git a/drivers/pinctrl/aspeed/pinmux-aspeed.c b/drivers/pinctrl/aspeed/pinmux-aspeed.c index 839c01b7953f..57305ca838a7 100644 --- a/drivers/pinctrl/aspeed/pinmux-aspeed.c +++ b/drivers/pinctrl/aspeed/pinmux-aspeed.c @@ -78,11 +78,14 @@ int aspeed_sig_desc_eval(const struct aspeed_sig_desc *desc, * neither the enabled nor disabled state. Thus we must explicitly test for * either condition as required. */ -int aspeed_sig_expr_eval(const struct aspeed_pinmux_data *ctx, +int aspeed_sig_expr_eval(struct aspeed_pinmux_data *ctx, const struct aspeed_sig_expr *expr, bool enabled) { - int i; int ret; + int i; + + if (ctx->ops->eval) + return ctx->ops->eval(ctx, expr, enabled); for (i = 0; i < expr->ndescs; i++) { const struct aspeed_sig_desc *desc = &expr->descs[i]; diff --git a/drivers/pinctrl/aspeed/pinmux-aspeed.h b/drivers/pinctrl/aspeed/pinmux-aspeed.h index dfcc97ca1a8b..a2c0d52e4f7b 100644 --- a/drivers/pinctrl/aspeed/pinmux-aspeed.h +++ b/drivers/pinctrl/aspeed/pinmux-aspeed.h @@ -775,6 +775,8 @@ struct aspeed_pin_function { struct aspeed_pinmux_data; struct aspeed_pinmux_ops { + int (*eval)(struct aspeed_pinmux_data *ctx, + const struct aspeed_sig_expr *expr, bool enabled); int (*set)(struct aspeed_pinmux_data *ctx, const struct aspeed_sig_expr *expr, bool enabled); }; @@ -795,9 +797,8 @@ struct aspeed_pinmux_data { int aspeed_sig_desc_eval(const struct aspeed_sig_desc *desc, bool enabled, struct regmap *map); -int aspeed_sig_expr_eval(const struct aspeed_pinmux_data *ctx, - const struct aspeed_sig_expr *expr, - bool enabled); +int aspeed_sig_expr_eval(struct aspeed_pinmux_data *ctx, + const struct aspeed_sig_expr *expr, bool enabled); static inline int aspeed_sig_expr_set(struct aspeed_pinmux_data *ctx, const struct aspeed_sig_expr *expr, diff --git a/drivers/pinctrl/intel/pinctrl-baytrail.c b/drivers/pinctrl/intel/pinctrl-baytrail.c index db6c5ca9e2d6..9ffb22211d2b 100644 --- a/drivers/pinctrl/intel/pinctrl-baytrail.c +++ b/drivers/pinctrl/intel/pinctrl-baytrail.c @@ -1436,6 +1436,20 @@ static void byt_gpio_irq_handler(struct irq_desc *desc) chip->irq_eoi(data); } +static void byt_init_irq_valid_mask(struct gpio_chip *chip, + unsigned long *valid_mask, + unsigned int ngpios) +{ + /* + * FIXME: currently the valid_mask is filled in as part of + * initializing the irq_chip below in byt_gpio_irq_init_hw(). + * when converting this driver to the new way of passing the + * gpio_irq_chip along when adding the gpio_chip, move the + * mask initialization into this callback instead. Right now + * this callback is here to make sure the mask gets allocated. + */ +} + static void byt_gpio_irq_init_hw(struct byt_gpio *vg) { struct gpio_chip *gc = &vg->chip; @@ -1506,7 +1520,7 @@ static int byt_gpio_probe(struct byt_gpio *vg) gc->can_sleep = false; gc->parent = &vg->pdev->dev; gc->ngpio = vg->soc_data->npins; - gc->irq.need_valid_mask = true; + gc->irq.init_valid_mask = byt_init_irq_valid_mask; #ifdef CONFIG_PM_SLEEP vg->saved_context = devm_kcalloc(&vg->pdev->dev, gc->ngpio, diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c index cfb7168fe766..aae51c507f59 100644 --- a/drivers/pinctrl/intel/pinctrl-cherryview.c +++ b/drivers/pinctrl/intel/pinctrl-cherryview.c @@ -1543,6 +1543,30 @@ static const struct dmi_system_id chv_no_valid_mask[] = { {} }; +static void chv_init_irq_valid_mask(struct gpio_chip *chip, + unsigned long *valid_mask, + unsigned int ngpios) +{ + struct chv_pinctrl *pctrl = gpiochip_get_data(chip); + const struct chv_community *community = pctrl->community; + int i; + + /* Do not add GPIOs that can only generate GPEs to the IRQ domain */ + for (i = 0; i < community->npins; i++) { + const struct pinctrl_pin_desc *desc; + u32 intsel; + + desc = &community->pins[i]; + + intsel = readl(chv_padreg(pctrl, desc->number, CHV_PADCTRL0)); + intsel &= CHV_PADCTRL0_INTSEL_MASK; + intsel >>= CHV_PADCTRL0_INTSEL_SHIFT; + + if (intsel >= community->nirqs) + clear_bit(i, valid_mask); + } +} + static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq) { const struct chv_gpio_pinrange *range; @@ -1557,7 +1581,8 @@ static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq) chip->label = dev_name(pctrl->dev); chip->parent = pctrl->dev; chip->base = -1; - chip->irq.need_valid_mask = need_valid_mask; + if (need_valid_mask) + chip->irq.init_valid_mask = chv_init_irq_valid_mask; ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl); if (ret) { @@ -1576,21 +1601,6 @@ static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq) } } - /* Do not add GPIOs that can only generate GPEs to the IRQ domain */ - for (i = 0; i < community->npins; i++) { - const struct pinctrl_pin_desc *desc; - u32 intsel; - - desc = &community->pins[i]; - - intsel = readl(chv_padreg(pctrl, desc->number, CHV_PADCTRL0)); - intsel &= CHV_PADCTRL0_INTSEL_MASK; - intsel >>= CHV_PADCTRL0_INTSEL_SHIFT; - - if (need_valid_mask && intsel >= community->nirqs) - clear_bit(i, chip->irq.valid_mask); - } - /* * The same set of machines in chv_no_valid_mask[] have incorrectly * configured GPIOs that generate spurious interrupts so we use diff --git a/drivers/pinctrl/pinctrl-stmfx.c b/drivers/pinctrl/pinctrl-stmfx.c index d7e37b51984f..974973777395 100644 --- a/drivers/pinctrl/pinctrl-stmfx.c +++ b/drivers/pinctrl/pinctrl-stmfx.c @@ -585,12 +585,24 @@ static int stmfx_pinctrl_gpio_function_enable(struct stmfx_pinctrl *pctl) return stmfx_function_enable(pctl->stmfx, func); } +static int stmfx_pinctrl_gpio_init_valid_mask(struct gpio_chip *gc, + unsigned long *valid_mask, + unsigned int ngpios) +{ + struct stmfx_pinctrl *pctl = gpiochip_get_data(gc); + u32 n; + + for_each_clear_bit(n, &pctl->gpio_valid_mask, ngpios) + clear_bit(n, valid_mask); + + return 0; +} + static int stmfx_pinctrl_probe(struct platform_device *pdev) { struct stmfx *stmfx = dev_get_drvdata(pdev->dev.parent); struct device_node *np = pdev->dev.of_node; struct stmfx_pinctrl *pctl; - u32 n; int irq, ret; pctl = devm_kzalloc(stmfx->dev, sizeof(*pctl), GFP_KERNEL); @@ -648,7 +660,7 @@ static int stmfx_pinctrl_probe(struct platform_device *pdev) pctl->gpio_chip.ngpio = pctl->pctl_desc.npins; pctl->gpio_chip.can_sleep = true; pctl->gpio_chip.of_node = np; - pctl->gpio_chip.need_valid_mask = true; + pctl->gpio_chip.init_valid_mask = stmfx_pinctrl_gpio_init_valid_mask; ret = devm_gpiochip_add_data(pctl->dev, &pctl->gpio_chip, pctl); if (ret) { @@ -666,8 +678,6 @@ static int stmfx_pinctrl_probe(struct platform_device *pdev) pctl->irq_chip.irq_set_type = stmfx_pinctrl_irq_set_type; pctl->irq_chip.irq_bus_lock = stmfx_pinctrl_irq_bus_lock; pctl->irq_chip.irq_bus_sync_unlock = stmfx_pinctrl_irq_bus_sync_unlock; - for_each_clear_bit(n, &pctl->gpio_valid_mask, pctl->gpio_chip.ngpio) - clear_bit(n, pctl->gpio_chip.valid_mask); ret = gpiochip_irqchip_add_nested(&pctl->gpio_chip, &pctl->irq_chip, 0, handle_bad_irq, IRQ_TYPE_NONE); diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index af44dafc35e7..32fc2458b8eb 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -138,6 +138,7 @@ config PINCTRL_QCOM_SPMI_PMIC select PINMUX select PINCONF select GENERIC_PINCONF + select GPIOLIB_IRQCHIP select IRQ_DOMAIN_HIERARCHY help This is the pinctrl, pinmux, pinconf and gpiolib driver for the diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index edecd653daa9..763da0be10d6 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -593,24 +593,25 @@ static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) #define msm_gpio_dbg_show NULL #endif -static int msm_gpio_init_valid_mask(struct gpio_chip *chip) +static int msm_gpio_init_valid_mask(struct gpio_chip *gc, + unsigned long *valid_mask, + unsigned int ngpios) { - struct msm_pinctrl *pctrl = gpiochip_get_data(chip); + struct msm_pinctrl *pctrl = gpiochip_get_data(gc); int ret; unsigned int len, i; - unsigned int max_gpios = pctrl->soc->ngpios; const int *reserved = pctrl->soc->reserved_gpios; u16 *tmp; /* Driver provided reserved list overrides DT and ACPI */ if (reserved) { - bitmap_fill(chip->valid_mask, max_gpios); + bitmap_fill(valid_mask, ngpios); for (i = 0; reserved[i] >= 0; i++) { - if (i >= max_gpios || reserved[i] >= max_gpios) { + if (i >= ngpios || reserved[i] >= ngpios) { dev_err(pctrl->dev, "invalid list of reserved GPIOs\n"); return -EINVAL; } - clear_bit(reserved[i], chip->valid_mask); + clear_bit(reserved[i], valid_mask); } return 0; @@ -621,7 +622,7 @@ static int msm_gpio_init_valid_mask(struct gpio_chip *chip) if (ret < 0) return 0; - if (ret > max_gpios) + if (ret > ngpios) return -EINVAL; tmp = kmalloc_array(len, sizeof(*tmp), GFP_KERNEL); @@ -634,9 +635,9 @@ static int msm_gpio_init_valid_mask(struct gpio_chip *chip) goto out; } - bitmap_zero(chip->valid_mask, max_gpios); + bitmap_zero(valid_mask, ngpios); for (i = 0; i < len; i++) - set_bit(tmp[i], chip->valid_mask); + set_bit(tmp[i], valid_mask); out: kfree(tmp); @@ -652,7 +653,6 @@ static const struct gpio_chip msm_gpio_template = { .request = gpiochip_generic_request, .free = gpiochip_generic_free, .dbg_show = msm_gpio_dbg_show, - .init_valid_mask = msm_gpio_init_valid_mask, }; /* For dual-edge interrupts in software, since some hardware has no @@ -1015,7 +1015,8 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl) chip->parent = pctrl->dev; chip->owner = THIS_MODULE; chip->of_node = pctrl->dev->of_node; - chip->need_valid_mask = msm_gpio_needs_valid_mask(pctrl); + if (msm_gpio_needs_valid_mask(pctrl)) + chip->init_valid_mask = msm_gpio_init_valid_mask; pctrl->irq_chip.name = "msmgpio"; pctrl->irq_chip.irq_enable = msm_gpio_irq_enable; diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c index 6a6b41444234..f1fece5b9c06 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c @@ -170,8 +170,6 @@ struct pmic_gpio_state { struct regmap *map; struct pinctrl_dev *ctrl; struct gpio_chip chip; - struct fwnode_handle *fwnode; - struct irq_domain *domain; }; static const struct pinconf_generic_params pmic_gpio_bindings[] = { @@ -751,23 +749,6 @@ static int pmic_gpio_of_xlate(struct gpio_chip *chip, return gpio_desc->args[0] - PMIC_GPIO_PHYSICAL_OFFSET; } -static int pmic_gpio_to_irq(struct gpio_chip *chip, unsigned pin) -{ - struct pmic_gpio_state *state = gpiochip_get_data(chip); - struct irq_fwspec fwspec; - - fwspec.fwnode = state->fwnode; - fwspec.param_count = 2; - fwspec.param[0] = pin + PMIC_GPIO_PHYSICAL_OFFSET; - /* - * Set the type to a safe value temporarily. This will be overwritten - * later with the proper value by irq_set_type. - */ - fwspec.param[1] = IRQ_TYPE_EDGE_RISING; - - return irq_create_fwspec_mapping(&fwspec); -} - static void pmic_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) { struct pmic_gpio_state *state = gpiochip_get_data(chip); @@ -787,7 +768,6 @@ static const struct gpio_chip pmic_gpio_gpio_template = { .request = gpiochip_generic_request, .free = gpiochip_generic_free, .of_xlate = pmic_gpio_of_xlate, - .to_irq = pmic_gpio_to_irq, .dbg_show = pmic_gpio_dbg_show, }; @@ -966,46 +946,24 @@ static int pmic_gpio_domain_translate(struct irq_domain *domain, return 0; } -static int pmic_gpio_domain_alloc(struct irq_domain *domain, unsigned int virq, - unsigned int nr_irqs, void *data) +static unsigned int pmic_gpio_child_offset_to_irq(struct gpio_chip *chip, + unsigned int offset) { - struct pmic_gpio_state *state = container_of(domain->host_data, - struct pmic_gpio_state, - chip); - struct irq_fwspec *fwspec = data; - struct irq_fwspec parent_fwspec; - irq_hw_number_t hwirq; - unsigned int type; - int ret, i; - - ret = pmic_gpio_domain_translate(domain, fwspec, &hwirq, &type); - if (ret) - return ret; - - for (i = 0; i < nr_irqs; i++) - irq_domain_set_info(domain, virq + i, hwirq + i, - &pmic_gpio_irq_chip, state, - handle_level_irq, NULL, NULL); + return offset + PMIC_GPIO_PHYSICAL_OFFSET; +} - parent_fwspec.fwnode = domain->parent->fwnode; - parent_fwspec.param_count = 4; - parent_fwspec.param[0] = 0; - parent_fwspec.param[1] = hwirq + 0xc0; - parent_fwspec.param[2] = 0; - parent_fwspec.param[3] = fwspec->param[1]; +static int pmic_gpio_child_to_parent_hwirq(struct gpio_chip *chip, + unsigned int child_hwirq, + unsigned int child_type, + unsigned int *parent_hwirq, + unsigned int *parent_type) +{ + *parent_hwirq = child_hwirq + 0xc0; + *parent_type = child_type; - return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, - &parent_fwspec); + return 0; } -static const struct irq_domain_ops pmic_gpio_domain_ops = { - .activate = gpiochip_irq_domain_activate, - .alloc = pmic_gpio_domain_alloc, - .deactivate = gpiochip_irq_domain_deactivate, - .free = irq_domain_free_irqs_common, - .translate = pmic_gpio_domain_translate, -}; - static int pmic_gpio_probe(struct platform_device *pdev) { struct irq_domain *parent_domain; @@ -1015,6 +973,7 @@ static int pmic_gpio_probe(struct platform_device *pdev) struct pinctrl_desc *pctrldesc; struct pmic_gpio_pad *pad, *pads; struct pmic_gpio_state *state; + struct gpio_irq_chip *girq; int ret, npins, i; u32 reg; @@ -1094,19 +1053,21 @@ static int pmic_gpio_probe(struct platform_device *pdev) if (!parent_domain) return -ENXIO; - state->fwnode = of_node_to_fwnode(state->dev->of_node); - state->domain = irq_domain_create_hierarchy(parent_domain, 0, - state->chip.ngpio, - state->fwnode, - &pmic_gpio_domain_ops, - &state->chip); - if (!state->domain) - return -ENODEV; + girq = &state->chip.irq; + girq->chip = &pmic_gpio_irq_chip; + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_level_irq; + girq->fwnode = of_node_to_fwnode(state->dev->of_node); + girq->parent_domain = parent_domain; + girq->child_to_parent_hwirq = pmic_gpio_child_to_parent_hwirq; + girq->populate_parent_fwspec = gpiochip_populate_parent_fwspec_fourcell; + girq->child_offset_to_irq = pmic_gpio_child_offset_to_irq; + girq->child_irq_domain_ops.translate = pmic_gpio_domain_translate; ret = gpiochip_add_data(&state->chip, state); if (ret) { dev_err(state->dev, "can't add gpio chip\n"); - goto err_chip_add_data; + return ret; } /* @@ -1132,8 +1093,6 @@ static int pmic_gpio_probe(struct platform_device *pdev) err_range: gpiochip_remove(&state->chip); -err_chip_add_data: - irq_domain_remove(state->domain); return ret; } @@ -1142,7 +1101,6 @@ static int pmic_gpio_remove(struct platform_device *pdev) struct pmic_gpio_state *state = platform_get_drvdata(pdev); gpiochip_remove(&state->chip); - irq_domain_remove(state->domain); return 0; } |