diff options
Diffstat (limited to 'drivers/pinctrl')
| -rw-r--r-- | drivers/pinctrl/samsung/pinctrl-exynos-arm64.c | 140 | ||||
| -rw-r--r-- | drivers/pinctrl/samsung/pinctrl-samsung.c | 2 | ||||
| -rw-r--r-- | drivers/pinctrl/samsung/pinctrl-samsung.h | 1 |
3 files changed, 143 insertions, 0 deletions
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c index cb965cf93705..8d08b29a21f6 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c @@ -796,3 +796,143 @@ const struct samsung_pinctrl_of_match_data fsd_of_data __initconst = { .ctrl = fsd_pin_ctrl, .num_ctrl = ARRAY_SIZE(fsd_pin_ctrl), }; + +/* pin banks of gs101 pin-controller (ALIVE) */ +static const struct samsung_pin_bank_data gs101_pin_alive[] = { + EXYNOS850_PIN_BANK_EINTW(8, 0x0, "gpa0", 0x00), + EXYNOS850_PIN_BANK_EINTW(7, 0x20, "gpa1", 0x04), + EXYNOS850_PIN_BANK_EINTW(5, 0x40, "gpa2", 0x08), + EXYNOS850_PIN_BANK_EINTW(4, 0x60, "gpa3", 0x0c), + EXYNOS850_PIN_BANK_EINTW(4, 0x80, "gpa4", 0x10), + EXYNOS850_PIN_BANK_EINTW(7, 0xa0, "gpa5", 0x14), + EXYNOS850_PIN_BANK_EINTW(8, 0xc0, "gpa9", 0x18), + EXYNOS850_PIN_BANK_EINTW(2, 0xe0, "gpa10", 0x1c), +}; + +/* pin banks of gs101 pin-controller (FAR_ALIVE) */ +static const struct samsung_pin_bank_data gs101_pin_far_alive[] = { + EXYNOS850_PIN_BANK_EINTW(8, 0x0, "gpa6", 0x00), + EXYNOS850_PIN_BANK_EINTW(4, 0x20, "gpa7", 0x04), + EXYNOS850_PIN_BANK_EINTW(8, 0x40, "gpa8", 0x08), + EXYNOS850_PIN_BANK_EINTW(2, 0x60, "gpa11", 0x0c), +}; + +/* pin banks of gs101 pin-controller (GSACORE) */ +static const struct samsung_pin_bank_data gs101_pin_gsacore[] = { + EXYNOS850_PIN_BANK_EINTG(2, 0x0, "gps0", 0x00), + EXYNOS850_PIN_BANK_EINTG(8, 0x20, "gps1", 0x04), + EXYNOS850_PIN_BANK_EINTG(3, 0x40, "gps2", 0x08), +}; + +/* pin banks of gs101 pin-controller (GSACTRL) */ +static const struct samsung_pin_bank_data gs101_pin_gsactrl[] = { + EXYNOS850_PIN_BANK_EINTW(6, 0x0, "gps3", 0x00), +}; + +/* pin banks of gs101 pin-controller (PERIC0) */ +static const struct samsung_pin_bank_data gs101_pin_peric0[] = { + EXYNOS850_PIN_BANK_EINTG(5, 0x0, "gpp0", 0x00), + EXYNOS850_PIN_BANK_EINTG(4, 0x20, "gpp1", 0x04), + EXYNOS850_PIN_BANK_EINTG(4, 0x40, "gpp2", 0x08), + EXYNOS850_PIN_BANK_EINTG(2, 0x60, "gpp3", 0x0c), + EXYNOS850_PIN_BANK_EINTG(4, 0x80, "gpp4", 0x10), + EXYNOS850_PIN_BANK_EINTG(2, 0xa0, "gpp5", 0x14), + EXYNOS850_PIN_BANK_EINTG(4, 0xc0, "gpp6", 0x18), + EXYNOS850_PIN_BANK_EINTG(2, 0xe0, "gpp7", 0x1c), + EXYNOS850_PIN_BANK_EINTG(4, 0x100, "gpp8", 0x20), + EXYNOS850_PIN_BANK_EINTG(2, 0x120, "gpp9", 0x24), + EXYNOS850_PIN_BANK_EINTG(4, 0x140, "gpp10", 0x28), + EXYNOS850_PIN_BANK_EINTG(2, 0x160, "gpp11", 0x2c), + EXYNOS850_PIN_BANK_EINTG(4, 0x180, "gpp12", 0x30), + EXYNOS850_PIN_BANK_EINTG(2, 0x1a0, "gpp13", 0x34), + EXYNOS850_PIN_BANK_EINTG(4, 0x1c0, "gpp14", 0x38), + EXYNOS850_PIN_BANK_EINTG(2, 0x1e0, "gpp15", 0x3c), + EXYNOS850_PIN_BANK_EINTG(4, 0x200, "gpp16", 0x40), + EXYNOS850_PIN_BANK_EINTG(2, 0x220, "gpp17", 0x44), + EXYNOS850_PIN_BANK_EINTG(4, 0x240, "gpp18", 0x48), + EXYNOS850_PIN_BANK_EINTG(4, 0x260, "gpp19", 0x4c), +}; + +/* pin banks of gs101 pin-controller (PERIC1) */ +static const struct samsung_pin_bank_data gs101_pin_peric1[] = { + EXYNOS850_PIN_BANK_EINTG(8, 0x0, "gpp20", 0x00), + EXYNOS850_PIN_BANK_EINTG(4, 0x20, "gpp21", 0x04), + EXYNOS850_PIN_BANK_EINTG(2, 0x40, "gpp22", 0x08), + EXYNOS850_PIN_BANK_EINTG(8, 0x60, "gpp23", 0x0c), + EXYNOS850_PIN_BANK_EINTG(4, 0x80, "gpp24", 0x10), + EXYNOS850_PIN_BANK_EINTG(4, 0xa0, "gpp25", 0x14), + EXYNOS850_PIN_BANK_EINTG(5, 0xc0, "gpp26", 0x18), + EXYNOS850_PIN_BANK_EINTG(4, 0xe0, "gpp27", 0x1c), +}; + +/* pin banks of gs101 pin-controller (HSI1) */ +static const struct samsung_pin_bank_data gs101_pin_hsi1[] = { + EXYNOS850_PIN_BANK_EINTG(6, 0x0, "gph0", 0x00), + EXYNOS850_PIN_BANK_EINTG(7, 0x20, "gph1", 0x04), +}; + +/* pin banks of gs101 pin-controller (HSI2) */ +static const struct samsung_pin_bank_data gs101_pin_hsi2[] = { + EXYNOS850_PIN_BANK_EINTG(6, 0x0, "gph2", 0x00), + EXYNOS850_PIN_BANK_EINTG(2, 0x20, "gph3", 0x04), + EXYNOS850_PIN_BANK_EINTG(6, 0x40, "gph4", 0x08), +}; + +static const struct samsung_pin_ctrl gs101_pin_ctrl[] __initconst = { + { + /* pin banks of gs101 pin-controller (ALIVE) */ + .pin_banks = gs101_pin_alive, + .nr_banks = ARRAY_SIZE(gs101_pin_alive), + .eint_wkup_init = exynos_eint_wkup_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin banks of gs101 pin-controller (FAR_ALIVE) */ + .pin_banks = gs101_pin_far_alive, + .nr_banks = ARRAY_SIZE(gs101_pin_far_alive), + .eint_wkup_init = exynos_eint_wkup_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin banks of gs101 pin-controller (GSACORE) */ + .pin_banks = gs101_pin_gsacore, + .nr_banks = ARRAY_SIZE(gs101_pin_gsacore), + }, { + /* pin banks of gs101 pin-controller (GSACTRL) */ + .pin_banks = gs101_pin_gsactrl, + .nr_banks = ARRAY_SIZE(gs101_pin_gsactrl), + }, { + /* pin banks of gs101 pin-controller (PERIC0) */ + .pin_banks = gs101_pin_peric0, + .nr_banks = ARRAY_SIZE(gs101_pin_peric0), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin banks of gs101 pin-controller (PERIC1) */ + .pin_banks = gs101_pin_peric1, + .nr_banks = ARRAY_SIZE(gs101_pin_peric1), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin banks of gs101 pin-controller (HSI1) */ + .pin_banks = gs101_pin_hsi1, + .nr_banks = ARRAY_SIZE(gs101_pin_hsi1), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin banks of gs101 pin-controller (HSI2) */ + .pin_banks = gs101_pin_hsi2, + .nr_banks = ARRAY_SIZE(gs101_pin_hsi2), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, +}; + +const struct samsung_pinctrl_of_match_data gs101_of_data __initconst = { + .ctrl = gs101_pin_ctrl, + .num_ctrl = ARRAY_SIZE(gs101_pin_ctrl), +}; diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c index 79babbb39ced..5ad92600320e 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.c +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c @@ -1309,6 +1309,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = { .data = &s5pv210_of_data }, #endif #ifdef CONFIG_PINCTRL_EXYNOS_ARM64 + { .compatible = "google,gs101-pinctrl", + .data = &gs101_of_data }, { .compatible = "samsung,exynos5433-pinctrl", .data = &exynos5433_of_data }, { .compatible = "samsung,exynos7-pinctrl", diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h index 9b3db50adef3..0b459651bc4a 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.h +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h @@ -351,6 +351,7 @@ extern const struct samsung_pinctrl_of_match_data exynos7885_of_data; extern const struct samsung_pinctrl_of_match_data exynos850_of_data; extern const struct samsung_pinctrl_of_match_data exynosautov9_of_data; extern const struct samsung_pinctrl_of_match_data fsd_of_data; +extern const struct samsung_pinctrl_of_match_data gs101_of_data; extern const struct samsung_pinctrl_of_match_data s3c64xx_of_data; extern const struct samsung_pinctrl_of_match_data s3c2412_of_data; extern const struct samsung_pinctrl_of_match_data s3c2416_of_data; |