diff options
Diffstat (limited to 'drivers/pinctrl')
| -rw-r--r-- | drivers/pinctrl/Kconfig | 10 | ||||
| -rw-r--r-- | drivers/pinctrl/Makefile | 2 | ||||
| -rw-r--r-- | drivers/pinctrl/pinctrl-nomadik-db8500.c | 857 | ||||
| -rw-r--r-- | drivers/pinctrl/pinctrl-nomadik.c | 1780 | ||||
| -rw-r--r-- | drivers/pinctrl/pinctrl-nomadik.h | 77 |
5 files changed, 2726 insertions, 0 deletions
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index a54a93112cba..cc01c758bbfc 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -64,6 +64,16 @@ config PINCTRL_IMX28 select PINCONF select PINCTRL_MXS +config PINCTRL_NOMADIK + bool "Nomadik pin controller driver" + depends on ARCH_U8500 + select PINMUX + select PINCONF + +config PINCTRL_DB8500 + bool "DB8500 pin controller driver" + depends on PINCTRL_NOMADIK && ARCH_U8500 + config PINCTRL_PXA168 bool "PXA168 pin controller driver" depends on ARCH_MMP diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index c9b0be56ff49..8e764ade929a 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -16,6 +16,8 @@ obj-$(CONFIG_PINCTRL_MMP2) += pinctrl-mmp2.o obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o obj-$(CONFIG_PINCTRL_IMX28) += pinctrl-imx28.o +obj-$(CONFIG_PINCTRL_NOMADIK) += pinctrl-nomadik.o +obj-$(CONFIG_PINCTRL_DB8500) += pinctrl-nomadik-db8500.o obj-$(CONFIG_PINCTRL_PXA168) += pinctrl-pxa168.o obj-$(CONFIG_PINCTRL_PXA910) += pinctrl-pxa910.o obj-$(CONFIG_PINCTRL_SIRF) += pinctrl-sirf.o diff --git a/drivers/pinctrl/pinctrl-nomadik-db8500.c b/drivers/pinctrl/pinctrl-nomadik-db8500.c new file mode 100644 index 000000000000..8b2022276f71 --- /dev/null +++ b/drivers/pinctrl/pinctrl-nomadik-db8500.c @@ -0,0 +1,857 @@ +#include <linux/kernel.h> +#include <linux/pinctrl/pinctrl.h> +#include "pinctrl-nomadik.h" + +/* All the pins that can be used for GPIO and some other functions */ +#define _GPIO(offset) (offset) + +#define DB8500_PIN_AJ5 _GPIO(0) +#define DB8500_PIN_AJ3 _GPIO(1) +#define DB8500_PIN_AH4 _GPIO(2) +#define DB8500_PIN_AH3 _GPIO(3) +#define DB8500_PIN_AH6 _GPIO(4) +#define DB8500_PIN_AG6 _GPIO(5) +#define DB8500_PIN_AF6 _GPIO(6) +#define DB8500_PIN_AG5 _GPIO(7) +#define DB8500_PIN_AD5 _GPIO(8) +#define DB8500_PIN_AE4 _GPIO(9) +#define DB8500_PIN_AF5 _GPIO(10) +#define DB8500_PIN_AG4 _GPIO(11) +#define DB8500_PIN_AC4 _GPIO(12) +#define DB8500_PIN_AF3 _GPIO(13) +#define DB8500_PIN_AE3 _GPIO(14) +#define DB8500_PIN_AC3 _GPIO(15) +#define DB8500_PIN_AD3 _GPIO(16) +#define DB8500_PIN_AD4 _GPIO(17) +#define DB8500_PIN_AC2 _GPIO(18) +#define DB8500_PIN_AC1 _GPIO(19) +#define DB8500_PIN_AB4 _GPIO(20) +#define DB8500_PIN_AB3 _GPIO(21) +#define DB8500_PIN_AA3 _GPIO(22) +#define DB8500_PIN_AA4 _GPIO(23) +#define DB8500_PIN_AB2 _GPIO(24) +#define DB8500_PIN_Y4 _GPIO(25) +#define DB8500_PIN_Y2 _GPIO(26) +#define DB8500_PIN_AA2 _GPIO(27) +#define DB8500_PIN_AA1 _GPIO(28) +#define DB8500_PIN_W2 _GPIO(29) +#define DB8500_PIN_W3 _GPIO(30) +#define DB8500_PIN_V3 _GPIO(31) +#define DB8500_PIN_V2 _GPIO(32) +#define DB8500_PIN_AF2 _GPIO(33) +#define DB8500_PIN_AE1 _GPIO(34) +#define DB8500_PIN_AE2 _GPIO(35) +#define DB8500_PIN_AG2 _GPIO(36) +/* Hole */ +#define DB8500_PIN_F3 _GPIO(64) +#define DB8500_PIN_F1 _GPIO(65) +#define DB8500_PIN_G3 _GPIO(66) +#define DB8500_PIN_G2 _GPIO(67) +#define DB8500_PIN_E1 _GPIO(68) +#define DB8500_PIN_E2 _GPIO(69) +#define DB8500_PIN_G5 _GPIO(70) +#define DB8500_PIN_G4 _GPIO(71) +#define DB8500_PIN_H4 _GPIO(72) +#define DB8500_PIN_H3 _GPIO(73) +#define DB8500_PIN_J3 _GPIO(74) +#define DB8500_PIN_H2 _GPIO(75) +#define DB8500_PIN_J2 _GPIO(76) +#define DB8500_PIN_H1 _GPIO(77) +#define DB8500_PIN_F4 _GPIO(78) +#define DB8500_PIN_E3 _GPIO(79) +#define DB8500_PIN_E4 _GPIO(80) +#define DB8500_PIN_D2 _GPIO(81) +#define DB8500_PIN_C1 _GPIO(82) +#define DB8500_PIN_D3 _GPIO(83) +#define DB8500_PIN_C2 _GPIO(84) +#define DB8500_PIN_D5 _GPIO(85) +#define DB8500_PIN_C6 _GPIO(86) +#define DB8500_PIN_B3 _GPIO(87) +#define DB8500_PIN_C4 _GPIO(88) +#define DB8500_PIN_E6 _GPIO(89) +#define DB8500_PIN_A3 _GPIO(90) +#define DB8500_PIN_B6 _GPIO(91) +#define DB8500_PIN_D6 _GPIO(92) +#define DB8500_PIN_B7 _GPIO(93) +#define DB8500_PIN_D7 _GPIO(94) +#define DB8500_PIN_E8 _GPIO(95) +#define DB8500_PIN_D8 _GPIO(96) +#define DB8500_PIN_D9 _GPIO(97) +/* Hole */ +#define DB8500_PIN_A5 _GPIO(128) +#define DB8500_PIN_B4 _GPIO(129) +#define DB8500_PIN_C8 _GPIO(130) +#define DB8500_PIN_A12 _GPIO(131) +#define DB8500_PIN_C10 _GPIO(132) +#define DB8500_PIN_B10 _GPIO(133) +#define DB8500_PIN_B9 _GPIO(134) +#define DB8500_PIN_A9 _GPIO(135) +#define DB8500_PIN_C7 _GPIO(136) +#define DB8500_PIN_A7 _GPIO(137) +#define DB8500_PIN_C5 _GPIO(138) +#define DB8500_PIN_C9 _GPIO(139) +#define DB8500_PIN_B11 _GPIO(140) +#define DB8500_PIN_C12 _GPIO(141) +#define DB8500_PIN_C11 _GPIO(142) +#define DB8500_PIN_D12 _GPIO(143) +#define DB8500_PIN_B13 _GPIO(144) +#define DB8500_PIN_C13 _GPIO(145) +#define DB8500_PIN_D13 _GPIO(146) +#define DB8500_PIN_C15 _GPIO(147) +#define DB8500_PIN_B16 _GPIO(148) +#define DB8500_PIN_B14 _GPIO(149) +#define DB8500_PIN_C14 _GPIO(150) +#define DB8500_PIN_D17 _GPIO(151) +#define DB8500_PIN_D16 _GPIO(152) +#define DB8500_PIN_B17 _GPIO(153) +#define DB8500_PIN_C16 _GPIO(154) +#define DB8500_PIN_C19 _GPIO(155) +#define DB8500_PIN_C17 _GPIO(156) +#define DB8500_PIN_A18 _GPIO(157) +#define DB8500_PIN_C18 _GPIO(158) +#define DB8500_PIN_B19 _GPIO(159) +#define DB8500_PIN_B20 _GPIO(160) +#define DB8500_PIN_D21 _GPIO(161) +#define DB8500_PIN_D20 _GPIO(162) +#define DB8500_PIN_C20 _GPIO(163) +#define DB8500_PIN_B21 _GPIO(164) +#define DB8500_PIN_C21 _GPIO(165) +#define DB8500_PIN_A22 _GPIO(166) +#define DB8500_PIN_B24 _GPIO(167) +#define DB8500_PIN_C22 _GPIO(168) +#define DB8500_PIN_D22 _GPIO(169) +#define DB8500_PIN_C23 _GPIO(170) +#define DB8500_PIN_D23 _GPIO(171) +/* Hole */ +#define DB8500_PIN_AJ27 _GPIO(192) +#define DB8500_PIN_AH27 _GPIO(193) +#define DB8500_PIN_AF27 _GPIO(194) +#define DB8500_PIN_AG28 _GPIO(195) +#define DB8500_PIN_AG26 _GPIO(196) +#define DB8500_PIN_AH24 _GPIO(197) +#define DB8500_PIN_AG25 _GPIO(198) +#define DB8500_PIN_AH23 _GPIO(199) +#define DB8500_PIN_AH26 _GPIO(200) +#define DB8500_PIN_AF24 _GPIO(201) +#define DB8500_PIN_AF25 _GPIO(202) +#define DB8500_PIN_AE23 _GPIO(203) +#define DB8500_PIN_AF23 _GPIO(204) +#define DB8500_PIN_AG23 _GPIO(205) +#define DB8500_PIN_AG24 _GPIO(206) +#define DB8500_PIN_AJ23 _GPIO(207) +#define DB8500_PIN_AH16 _GPIO(208) +#define DB8500_PIN_AG15 _GPIO(209) +#define DB8500_PIN_AJ15 _GPIO(210) +#define DB8500_PIN_AG14 _GPIO(211) +#define DB8500_PIN_AF13 _GPIO(212) +#define DB8500_PIN_AG13 _GPIO(213) +#define DB8500_PIN_AH15 _GPIO(214) +#define DB8500_PIN_AH13 _GPIO(215) +#define DB8500_PIN_AG12 _GPIO(216) +#define DB8500_PIN_AH12 _GPIO(217) +#define DB8500_PIN_AH11 _GPIO(218) +#define DB8500_PIN_AG10 _GPIO(219) +#define DB8500_PIN_AH10 _GPIO(220) +#define DB8500_PIN_AJ11 _GPIO(221) +#define DB8500_PIN_AJ9 _GPIO(222) +#define DB8500_PIN_AH9 _GPIO(223) +#define DB8500_PIN_AG9 _GPIO(224) +#define DB8500_PIN_AG8 _GPIO(225) +#define DB8500_PIN_AF8 _GPIO(226) +#define DB8500_PIN_AH7 _GPIO(227) +#define DB8500_PIN_AJ6 _GPIO(228) +#define DB8500_PIN_AG7 _GPIO(229) +#define DB8500_PIN_AF7 _GPIO(230) +/* Hole */ +#define DB8500_PIN_AF28 _GPIO(256) +#define DB8500_PIN_AE29 _GPIO(257) +#define DB8500_PIN_AD29 _GPIO(258) +#define DB8500_PIN_AC29 _GPIO(259) +#define DB8500_PIN_AD28 _GPIO(260) +#define DB8500_PIN_AD26 _GPIO(261) +#define DB8500_PIN_AE26 _GPIO(262) +#define DB8500_PIN_AG29 _GPIO(263) +#define DB8500_PIN_AE27 _GPIO(264) +#define DB8500_PIN_AD27 _GPIO(265) +#define DB8500_PIN_AC28 _GPIO(266) +#define DB8500_PIN_AC27 _GPIO(267) + +/* + * The names of the pins are denoted by GPIO number and ball name, even + * though they can be used for other things than GPIO, this is the first + * column in the table of the data sheet and often used on schematics and + * such. + */ +static const struct pinctrl_pin_desc nmk_db8500_pins[] = { + PINCTRL_PIN(DB8500_PIN_AJ5, "GPIO0_AJ5"), + PINCTRL_PIN(DB8500_PIN_AJ3, "GPIO1_AJ3"), + PINCTRL_PIN(DB8500_PIN_AH4, "GPIO2_AH4"), + PINCTRL_PIN(DB8500_PIN_AH3, "GPIO3_AH3"), + PINCTRL_PIN(DB8500_PIN_AH6, "GPIO4_AH6"), + PINCTRL_PIN(DB8500_PIN_AG6, "GPIO5_AG6"), + PINCTRL_PIN(DB8500_PIN_AF6, "GPIO6_AF6"), + PINCTRL_PIN(DB8500_PIN_AG5, "GPIO7_AG5"), + PINCTRL_PIN(DB8500_PIN_AD5, "GPIO8_AD5"), + PINCTRL_PIN(DB8500_PIN_AE4, "GPIO9_AE4"), + PINCTRL_PIN(DB8500_PIN_AF5, "GPIO10_AF5"), + PINCTRL_PIN(DB8500_PIN_AG4, "GPIO11_AG4"), + PINCTRL_PIN(DB8500_PIN_AC4, "GPIO12_AC4"), + PINCTRL_PIN(DB8500_PIN_AF3, "GPIO13_AF3"), + PINCTRL_PIN(DB8500_PIN_AE3, "GPIO14_AE3"), + PINCTRL_PIN(DB8500_PIN_AC3, "GPIO15_AC3"), + PINCTRL_PIN(DB8500_PIN_AD3, "GPIO16_AD3"), + PINCTRL_PIN(DB8500_PIN_AD4, "GPIO17_AD4"), + PINCTRL_PIN(DB8500_PIN_AC2, "GPIO18_AC2"), + PINCTRL_PIN(DB8500_PIN_AC1, "GPIO19_AC1"), + PINCTRL_PIN(DB8500_PIN_AB4, "GPIO20_AB4"), + PINCTRL_PIN(DB8500_PIN_AB3, "GPIO21_AB3"), + PINCTRL_PIN(DB8500_PIN_AA3, "GPIO22_AA3"), + PINCTRL_PIN(DB8500_PIN_AA4, "GPIO23_AA4"), + PINCTRL_PIN(DB8500_PIN_AB2, "GPIO24_AB2"), + PINCTRL_PIN(DB8500_PIN_Y4, "GPIO25_Y4"), + PINCTRL_PIN(DB8500_PIN_Y2, "GPIO26_Y2"), + PINCTRL_PIN(DB8500_PIN_AA2, "GPIO27_AA2"), + PINCTRL_PIN(DB8500_PIN_AA1, "GPIO28_AA1"), + PINCTRL_PIN(DB8500_PIN_W2, "GPIO29_W2"), + PINCTRL_PIN(DB8500_PIN_W3, "GPIO30_W3"), + PINCTRL_PIN(DB8500_PIN_V3, "GPIO31_V3"), + PINCTRL_PIN(DB8500_PIN_V2, "GPIO32_V2"), + PINCTRL_PIN(DB8500_PIN_AF2, "GPIO33_AF2"), + PINCTRL_PIN(DB8500_PIN_AE1, "GPIO34_AE1"), + PINCTRL_PIN(DB8500_PIN_AE2, "GPIO35_AE2"), + PINCTRL_PIN(DB8500_PIN_AG2, "GPIO36_AG2"), + /* Hole */ + PINCTRL_PIN(DB8500_PIN_F3, "GPIO64_F3"), + PINCTRL_PIN(DB8500_PIN_F1, "GPIO65_F1"), + PINCTRL_PIN(DB8500_PIN_G3, "GPIO66_G3"), + PINCTRL_PIN(DB8500_PIN_G2, "GPIO67_G2"), + PINCTRL_PIN(DB8500_PIN_E1, "GPIO68_E1"), + PINCTRL_PIN(DB8500_PIN_E2, "GPIO69_E2"), + PINCTRL_PIN(DB8500_PIN_G5, "GPIO70_G5"), + PINCTRL_PIN(DB8500_PIN_G4, "GPIO71_G4"), + PINCTRL_PIN(DB8500_PIN_H4, "GPIO72_H4"), + PINCTRL_PIN(DB8500_PIN_H3, "GPIO73_H3"), + PINCTRL_PIN(DB8500_PIN_J3, "GPIO74_J3"), + PINCTRL_PIN(DB8500_PIN_H2, "GPIO75_H2"), + PINCTRL_PIN(DB8500_PIN_J2, "GPIO76_J2"), + PINCTRL_PIN(DB8500_PIN_H1, "GPIO77_H1"), + PINCTRL_PIN(DB8500_PIN_F4, "GPIO78_F4"), + PINCTRL_PIN(DB8500_PIN_E3, "GPIO79_E3"), + PINCTRL_PIN(DB8500_PIN_E4, "GPIO80_E4"), + PINCTRL_PIN(DB8500_PIN_D2, "GPIO81_D2"), + PINCTRL_PIN(DB8500_PIN_C1, "GPIO82_C1"), + PINCTRL_PIN(DB8500_PIN_D3, "GPIO83_D3"), + PINCTRL_PIN(DB8500_PIN_C2, "GPIO84_C2"), + PINCTRL_PIN(DB8500_PIN_D5, "GPIO85_D5"), + PINCTRL_PIN(DB8500_PIN_C6, "GPIO86_C6"), + PINCTRL_PIN(DB8500_PIN_B3, "GPIO87_B3"), + PINCTRL_PIN(DB8500_PIN_C4, "GPIO88_C4"), + PINCTRL_PIN(DB8500_PIN_E6, "GPIO89_E6"), + PINCTRL_PIN(DB8500_PIN_A3, "GPIO90_A3"), + PINCTRL_PIN(DB8500_PIN_B6, "GPIO91_B6"), + PINCTRL_PIN(DB8500_PIN_D6, "GPIO92_D6"), + PINCTRL_PIN(DB8500_PIN_B7, "GPIO93_B7"), + PINCTRL_PIN(DB8500_PIN_D7, "GPIO94_D7"), + PINCTRL_PIN(DB8500_PIN_E8, "GPIO95_E8"), + PINCTRL_PIN(DB8500_PIN_D8, "GPIO96_D8"), + PINCTRL_PIN(DB8500_PIN_D9, "GPIO97_D9"), + /* Hole */ + PINCTRL_PIN(DB8500_PIN_A5, "GPIO128_A5"), + PINCTRL_PIN(DB8500_PIN_B4, "GPIO129_B4"), + PINCTRL_PIN(DB8500_PIN_C8, "GPIO130_C8"), + PINCTRL_PIN(DB8500_PIN_A12, "GPIO131_A12"), + PINCTRL_PIN(DB8500_PIN_C10, "GPIO132_C10"), + PINCTRL_PIN(DB8500_PIN_B10, "GPIO133_B10"), + PINCTRL_PIN(DB8500_PIN_B9, "GPIO134_B9"), + PINCTRL_PIN(DB8500_PIN_A9, "GPIO135_A9"), + PINCTRL_PIN(DB8500_PIN_C7, "GPIO136_C7"), + PINCTRL_PIN(DB8500_PIN_A7, "GPIO137_A7"), + PINCTRL_PIN(DB8500_PIN_C5, "GPIO138_C5"), + PINCTRL_PIN(DB8500_PIN_C9, "GPIO139_C9"), + PINCTRL_PIN(DB8500_PIN_B11, "GPIO140_B11"), + PINCTRL_PIN(DB8500_PIN_C12, "GPIO141_C12"), + PINCTRL_PIN(DB8500_PIN_C11, "GPIO142_C11"), + PINCTRL_PIN(DB8500_PIN_D12, "GPIO143_D12"), + PINCTRL_PIN(DB8500_PIN_B13, "GPIO144_B13"), + PINCTRL_PIN(DB8500_PIN_C13, "GPIO145_C13"), + PINCTRL_PIN(DB8500_PIN_D13, "GPIO146_D13"), + PINCTRL_PIN(DB8500_PIN_C15, "GPIO147_C15"), + PINCTRL_PIN(DB8500_PIN_B16, "GPIO148_B16"), + PINCTRL_PIN(DB8500_PIN_B14, "GPIO149_B14"), + PINCTRL_PIN(DB8500_PIN_C14, "GPIO150_C14"), + PINCTRL_PIN(DB8500_PIN_D17, "GPIO151_D17"), + PINCTRL_PIN(DB8500_PIN_D16, "GPIO152_D16"), + PINCTRL_PIN(DB8500_PIN_B17, "GPIO153_B17"), + PINCTRL_PIN(DB8500_PIN_C16, "GPIO154_C16"), + PINCTRL_PIN(DB8500_PIN_C19, "GPIO155_C19"), + PINCTRL_PIN(DB8500_PIN_C17, "GPIO156_C17"), + PINCTRL_PIN(DB8500_PIN_A18, "GPIO157_A18"), + PINCTRL_PIN(DB8500_PIN_C18, "GPIO158_C18"), + PINCTRL_PIN(DB8500_PIN_B19, "GPIO159_B19"), + PINCTRL_PIN(DB8500_PIN_B20, "GPIO160_B20"), + PINCTRL_PIN(DB8500_PIN_D21, "GPIO161_D21"), + PINCTRL_PIN(DB8500_PIN_D20, "GPIO162_D20"), + PINCTRL_PIN(DB8500_PIN_C20, "GPIO163_C20"), + PINCTRL_PIN(DB8500_PIN_B21, "GPIO164_B21"), + PINCTRL_PIN(DB8500_PIN_C21, "GPIO165_C21"), + PINCTRL_PIN(DB8500_PIN_A22, "GPIO166_A22"), + PINCTRL_PIN(DB8500_PIN_B24, "GPIO167_B24"), + PINCTRL_PIN(DB8500_PIN_C22, "GPIO168_C22"), + PINCTRL_PIN(DB8500_PIN_D22, "GPIO169_D22"), + PINCTRL_PIN(DB8500_PIN_C23, "GPIO170_C23"), + PINCTRL_PIN(DB8500_PIN_D23, "GPIO171_D23"), + /* Hole */ + PINCTRL_PIN(DB8500_PIN_AJ27, "GPIO192_AJ27"), + PINCTRL_PIN(DB8500_PIN_AH27, "GPIO193_AH27"), + PINCTRL_PIN(DB8500_PIN_AF27, "GPIO194_AF27"), + PINCTRL_PIN(DB8500_PIN_AG28, "GPIO195_AG28"), + PINCTRL_PIN(DB8500_PIN_AG26, "GPIO196_AG26"), + PINCTRL_PIN(DB8500_PIN_AH24, "GPIO197_AH24"), + PINCTRL_PIN(DB8500_PIN_AG25, "GPIO198_AG25"), + PINCTRL_PIN(DB8500_PIN_AH23, "GPIO199_AH23"), + PINCTRL_PIN(DB8500_PIN_AH26, "GPIO200_AH26"), + PINCTRL_PIN(DB8500_PIN_AF24, "GPIO201_AF24"), + PINCTRL_PIN(DB8500_PIN_AF25, "GPIO202_AF25"), + PINCTRL_PIN(DB8500_PIN_AE23, "GPIO203_AE23"), + PINCTRL_PIN(DB8500_PIN_AF23, "GPIO204_AF23"), + PINCTRL_PIN(DB8500_PIN_AG23, "GPIO205_AG23"), + PINCTRL_PIN(DB8500_PIN_AG24, "GPIO206_AG24"), + PINCTRL_PIN(DB8500_PIN_AJ23, "GPIO207_AJ23"), + PINCTRL_PIN(DB8500_PIN_AH16, "GPIO208_AH16"), + PINCTRL_PIN(DB8500_PIN_AG15, "GPIO209_AG15"), + PINCTRL_PIN(DB8500_PIN_AJ15, "GPIO210_AJ15"), + PINCTRL_PIN(DB8500_PIN_AG14, "GPIO211_AG14"), + PINCTRL_PIN(DB8500_PIN_AF13, "GPIO212_AF13"), + PINCTRL_PIN(DB8500_PIN_AG13, "GPIO213_AG13"), + PINCTRL_PIN(DB8500_PIN_AH15, "GPIO214_AH15"), + PINCTRL_PIN(DB8500_PIN_AH13, "GPIO215_AH13"), + PINCTRL_PIN(DB8500_PIN_AG12, "GPIO216_AG12"), + PINCTRL_PIN(DB8500_PIN_AH12, "GPIO217_AH12"), + PINCTRL_PIN(DB8500_PIN_AH11, "GPIO218_AH11"), + PINCTRL_PIN(DB8500_PIN_AG10, "GPIO219_AG10"), + PINCTRL_PIN(DB8500_PIN_AH10, "GPIO220_AH10"), + PINCTRL_PIN(DB8500_PIN_AJ11, "GPIO221_AJ11"), + PINCTRL_PIN(DB8500_PIN_AJ9, "GPIO222_AJ9"), + PINCTRL_PIN(DB8500_PIN_AH9, "GPIO223_AH9"), + PINCTRL_PIN(DB8500_PIN_AG9, "GPIO224_AG9"), + PINCTRL_PIN(DB8500_PIN_AG8, "GPIO225_AG8"), + PINCTRL_PIN(DB8500_PIN_AF8, "GPIO226_AF8"), + PINCTRL_PIN(DB8500_PIN_AH7, "GPIO227_AH7"), + PINCTRL_PIN(DB8500_PIN_AJ6, "GPIO228_AJ6"), + PINCTRL_PIN(DB8500_PIN_AG7, "GPIO229_AG7"), + PINCTRL_PIN(DB8500_PIN_AF7, "GPIO230_AF7"), + /* Hole */ + PINCTRL_PIN(DB8500_PIN_AF28, "GPIO256_AF28"), + PINCTRL_PIN(DB8500_PIN_AE29, "GPIO257_AE29"), + PINCTRL_PIN(DB8500_PIN_AD29, "GPIO258_AD29"), + PINCTRL_PIN(DB8500_PIN_AC29, "GPIO259_AC29"), + PINCTRL_PIN(DB8500_PIN_AD28, "GPIO260_AD28"), + PINCTRL_PIN(DB8500_PIN_AD26, "GPIO261_AD26"), + PINCTRL_PIN(DB8500_PIN_AE26, "GPIO262_AE26"), + PINCTRL_PIN(DB8500_PIN_AG29, "GPIO263_AG29"), + PINCTRL_PIN(DB8500_PIN_AE27, "GPIO264_AE27"), + PINCTRL_PIN(DB8500_PIN_AD27, "GPIO265_AD27"), + PINCTRL_PIN(DB8500_PIN_AC28, "GPIO266_AC28"), + PINCTRL_PIN(DB8500_PIN_AC27, "GPIO267_AC27"), +}; + +#define DB8500_GPIO_RANGE(a, b, c) { .name = "DB8500", .id = a, .base = b, \ + .pin_base = b, .npins = c } + +/* + * This matches the 32-pin gpio chips registered by the GPIO portion. This + * cannot be const since we assign the struct gpio_chip * pointer at runtime. + */ +static struct pinctrl_gpio_range nmk_db8500_ranges[] = { + DB8500_GPIO_RANGE(0, 0, 32), + DB8500_GPIO_RANGE(1, 32, 5), + DB8500_GPIO_RANGE(2, 64, 32), + DB8500_GPIO_RANGE(3, 96, 2), + DB8500_GPIO_RANGE(4, 128, 32), + DB8500_GPIO_RANGE(5, 160, 12), + DB8500_GPIO_RANGE(6, 192, 32), + DB8500_GPIO_RANGE(7, 224, 7), + DB8500_GPIO_RANGE(8, 256, 12), +}; + +/* + * Read the pin group names like this: + * u0_a_1 = first groups of pins for uart0 on alt function a + * i2c2_b_2 = second group of pins for i2c2 on alt function b + * + * The groups are arranged as sets per altfunction column, so we can + * mux in one group at a time by selecting the same altfunction for them + * all. When functions require pins on different altfunctions, you need + * to combine several groups. + */ + +/* Altfunction A column */ +static const unsigned u0_a_1_pins[] = { DB8500_PIN_AJ5, DB8500_PIN_AJ3, + DB8500_PIN_AH4, DB8500_PIN_AH3 }; +static const unsigned u1rxtx_a_1_pins[] = { DB8500_PIN_AH6, DB8500_PIN_AG6 }; +static const unsigned u1ctsrts_a_1_pins[] = { DB8500_PIN_AF6, DB8500_PIN_AG5 }; +/* Image processor I2C line, this is driven by image processor firmware */ +static const unsigned ipi2c_a_1_pins[] = { DB8500_PIN_AD5, DB8500_PIN_AE4 }; +static const unsigned ipi2c_a_2_pins[] = { DB8500_PIN_AF5, DB8500_PIN_AG4 }; +/* MSP0 can only be on these pins, but TXD and RXD can be flipped */ +static const unsigned msp0txrx_a_1_pins[] = { DB8500_PIN_AC4, DB8500_PIN_AC3 }; +static const unsigned msp0tfstck_a_1_pins[] = { DB8500_PIN_AF3, DB8500_PIN_AE3 }; +static const unsigned msp0rfsrck_a_1_pins[] = { DB8500_PIN_AD3, DB8500_PIN_AD4 }; +/* Basic pins of the MMC/SD card 0 interface */ +static const unsigned mc0_a_1_pins[] = { DB8500_PIN_AC2, DB8500_PIN_AC1, + DB8500_PIN_AB4, DB8500_PIN_AA3, DB8500_PIN_AA4, DB8500_PIN_AB2, + DB8500_PIN_Y4, DB8500_PIN_Y2, DB8500_PIN_AA2, DB8500_PIN_AA1 }; +/* Often only 4 bits are used, then these are not needed (only used for MMC) */ +static const unsigned mc0_dat47_a_1_pins[] = { DB8500_PIN_W2, DB8500_PIN_W3, + DB8500_PIN_V3, DB8500_PIN_V2}; +static const unsigned mc0dat31dir_a_1_pins[] = { DB8500_PIN_AB3 }; +/* MSP1 can only be on these pins, but TXD and RXD can be flipped */ +static const unsigned msp1txrx_a_1_pins[] = { DB8500_PIN_AF2, DB8500_PIN_AG2 }; +static const unsigned msp1_a_1_pins[] = { DB8500_PIN_AE1, DB8500_PIN_AE2 }; +/* LCD interface */ +static const unsigned lcdb_a_1_pins[] = { DB8500_PIN_F3, DB8500_PIN_F1, + DB8500_PIN_G3, DB8500_PIN_G2 }; +static const unsigned lcdvsi0_a_1_pins[] = { DB8500_PIN_E1 }; +static const unsigned lcdvsi1_a_1_pins[] = { DB8500_PIN_E2 }; +static const unsigned lcd_d0_d7_a_1_pins[] = { + DB8500_PIN_G5, DB8500_PIN_G4, DB8500_PIN_H4, DB8500_PIN_H3, + DB8500_PIN_J3, DB8500_PIN_H2, DB8500_PIN_J2, DB8500_PIN_H1 }; +/* D8 thru D11 often used as TVOUT lines */ +static const unsigned lcd_d8_d11_a_1_pins[] = { DB8500_PIN_F4, + DB8500_PIN_E3, DB8500_PIN_E4, DB8500_PIN_D2 }; +static const unsigned lcd_d12_d23_a_1_pins[] = { + DB8500_PIN_C1, DB8500_PIN_D3, DB8500_PIN_C2, DB8500_PIN_D5, + DB8500_PIN_C6, DB8500_PIN_B3, DB8500_PIN_C4, DB8500_PIN_E6, + DB8500_PIN_A3, DB8500_PIN_B6, DB8500_PIN_D6, DB8500_PIN_B7 }; +static const unsigned kp_a_1_pins[] = { DB8500_PIN_D7, DB8500_PIN_E8, + DB8500_PIN_D8, DB8500_PIN_D9 }; +static const unsigned kpskaskb_a_1_pins[] = { DB8500_PIN_D17, DB8500_PIN_D16 }; +static const unsigned kp_a_2_pins[] = { + DB8500_PIN_B17, DB8500_PIN_C16, DB8500_PIN_C19, DB8500_PIN_C17, + DB8500_PIN_A18, DB8500_PIN_C18, DB8500_PIN_B19, DB8500_PIN_B20, + DB8500_PIN_D21, DB8500_PIN_D20, DB8500_PIN_C20, DB8500_PIN_B21, + DB8500_PIN_C21, DB8500_PIN_A22, DB8500_PIN_B24, DB8500_PIN_C22 }; +/* MC2 has 8 data lines and no direction control, so only for (e)MMC */ +static const unsigned mc2_a_1_pins[] = { DB8500_PIN_A5, DB8500_PIN_B4, + DB8500_PIN_C8, DB8500_PIN_A12, DB8500_PIN_C10, DB8500_PIN_B10, + DB8500_PIN_B9, DB8500_PIN_A9, DB8500_PIN_C7, DB8500_PIN_A7, + DB8500_PIN_C5 }; +static const unsigned ssp1_a_1_pins[] = { DB8500_PIN_C9, DB8500_PIN_B11, + DB8500_PIN_C12, DB8500_PIN_C11 }; +static const unsigned ssp0_a_1_pins[] = { DB8500_PIN_D12, DB8500_PIN_B13, + DB8500_PIN_C13, DB8500_PIN_D13 }; +static const unsigned i2c0_a_1_pins[] = { DB8500_PIN_C15, DB8500_PIN_B16 }; +/* + * Image processor GPIO pins are named "ipgpio" and have their own + * numberspace + */ +static const unsigned ipgpio0_a_1_pins[] = { DB8500_PIN_B14 }; +static const unsigned ipgpio1_a_1_pins[] = { DB8500_PIN_C14 }; +/* Three modem pins named RF_PURn, MODEM_STATE and MODEM_PWREN */ +static const unsigned modem_a_1_pins[] = { DB8500_PIN_D22, DB8500_PIN_C23, + DB8500_PIN_D23 }; +/* + * This MSP cannot switch RX and TX, SCK in a separate group since this + * seems to be optional. + */ +static const unsigned msp2sck_a_1_pins[] = { DB8500_PIN_AJ27 }; +static const unsigned msp2_a_1_pins[] = { DB8500_PIN_AH27, DB8500_PIN_AF27, + DB8500_PIN_AG28, DB8500_PIN_AG26 }; +static const unsigned mc4_a_1_pins[] = { DB8500_PIN_AH24, DB8500_PIN_AG25, + DB8500_PIN_AH23, DB8500_PIN_AH26, DB8500_PIN_AF24, DB8500_PIN_AF25, + DB8500_PIN_AE23, DB8500_PIN_AF23, DB8500_PIN_AG23, DB8500_PIN_AG24, + DB8500_PIN_AJ23 }; +/* MC1 has only 4 data pins, designed for SD or SDIO exclusively */ +static const unsigned mc1_a_1_pins[] = { DB8500_PIN_AH16, DB8500_PIN_AG15, + DB8500_PIN_AJ15, DB8500_PIN_AG14, DB8500_PIN_AF13, DB8500_PIN_AG13, + DB8500_PIN_AH15 }; +static const unsigned mc1dir_a_1_pins[] = { DB8500_PIN_AH13, DB8500_PIN_AG12, + DB8500_PIN_AH12, DB8500_PIN_AH11 }; +static const unsigned hsir_a_1_pins[] = { DB8500_PIN_AG10, DB8500_PIN_AH10 }; +static const unsigned hsit_a_1_pins[] = { DB8500_PIN_AJ11, DB8500_PIN_AJ9, + DB8500_PIN_AH9, DB8500_PIN_AG9, DB8500_PIN_AG8, DB8500_PIN_AF8 }; +static const unsigned clkout_a_1_pins[] = { DB8500_PIN_AH7, DB8500_PIN_AJ6 }; +static const unsigned clkout_a_2_pins[] = { DB8500_PIN_AG7, DB8500_PIN_AF7 }; +static const unsigned usb_a_1_pins[] = { DB8500_PIN_AF28, DB8500_PIN_AE29, + DB8500_PIN_AD29, DB8500_PIN_AC29, DB8500_PIN_AD28, DB8500_PIN_AD26, + DB8500_PIN_AE26, DB8500_PIN_AG29, DB8500_PIN_AE27, DB8500_PIN_AD27, + DB8500_PIN_AC28, DB8500_PIN_AC27 }; + +/* Altfunction B column */ +static const unsigned trig_b_1_pins[] = { DB8500_PIN_AJ5, DB8500_PIN_AJ3 }; +static const unsigned i2c4_b_1_pins[] = { DB8500_PIN_AH6, DB8500_PIN_AG6 }; +static const unsigned i2c1_b_1_pins[] = { DB8500_PIN_AF6, DB8500_PIN_AG5 }; +static const unsigned i2c2_b_1_pins[] = { DB8500_PIN_AD5, DB8500_PIN_AE4 }; +static const unsigned i2c2_b_2_pins[] = { DB8500_PIN_AF5, DB8500_PIN_AG4 }; +static const unsigned msp0txrx_b_1_pins[] = { DB8500_PIN_AC4, DB8500_PIN_AC3 }; +static const unsigned i2c1_b_2_pins[] = { DB8500_PIN_AD3, DB8500_PIN_AD4 }; +/* Just RX and TX for UART2 */ +static const unsigned u2rxtx_b_1_pins[] = { DB8500_PIN_AC2, DB8500_PIN_AC1 }; +static const unsigned uartmodtx_b_1_pins[] = { DB8500_PIN_AB4 }; +static const unsigned msp0sck_b_1_pins[] = { DB8500_PIN_AB3 }; +static const unsigned uartmodrx_b_1_pins[] = { DB8500_PIN_AA3 }; +static const unsigned stmmod_b_1_pins[] = { DB8500_PIN_AA4, DB8500_PIN_Y4, + DB8500_PIN_Y2, DB8500_PIN_AA2, DB8500_PIN_AA1 }; +static const unsigned uartmodrx_b_2_pins[] = { DB8500_PIN_AB2 }; +static const unsigned spi3_b_1_pins[] = { DB8500_PIN_W2, DB8500_PIN_W3, + DB8500_PIN_V3, DB8500_PIN_V2 }; +static const unsigned msp1txrx_b_1_pins[] = { DB8500_PIN_AF2, DB8500_PIN_AG2 }; +static const unsigned kp_b_1_pins[] = { DB8500_PIN_F3, DB8500_PIN_F1, + DB8500_PIN_G3, DB8500_PIN_G2, DB8500_PIN_E1, DB8500_PIN_E2, + DB8500_PIN_G5, DB8500_PIN_G4, DB8500_PIN_H4, DB8500_PIN_H3, + DB8500_PIN_J3, DB8500_PIN_H2, DB8500_PIN_J2, DB8500_PIN_H1, + DB8500_PIN_F4, DB8500_PIN_E3, DB8500_PIN_E4, DB8500_PIN_D2, + DB8500_PIN_C1, DB8500_PIN_D3, DB8500_PIN_C2, DB8500_PIN_D5 }; +static const unsigned sm_b_1_pins[] = { DB8500_PIN_C6, DB8500_PIN_B3, + DB8500_PIN_C4, DB8500_PIN_E6, DB8500_PIN_A3, DB8500_PIN_B6, + DB8500_PIN_D6, DB8500_PIN_B7, DB8500_PIN_D7, DB8500_PIN_D8, + DB8500_PIN_D9, DB8500_PIN_A5, DB8500_PIN_B4, DB8500_PIN_C8, + DB8500_PIN_A12, DB8500_PIN_C10, DB8500_PIN_B10, DB8500_PIN_B9, + DB8500_PIN_A9, DB8500_PIN_C7, DB8500_PIN_A7, DB8500_PIN_C5, + DB8500_PIN_C9, DB8500_PIN_B14 }; +/* This chip select pin can be "ps0" in alt B so have it separately */ +static const unsigned smcs0_b_1_pins[] = { DB8500_PIN_E8 }; +static const unsigned ipgpio7_b_1_pins[] = { DB8500_PIN_B11 }; +static const unsigned ipgpio2_b_1_pins[] = { DB8500_PIN_C12 }; +static const unsigned ipgpio3_b_1_pins[] = { DB8500_PIN_C11 }; +static const unsigned lcdaclk_b_1_pins[] = { DB8500_PIN_C14 }; +static const unsigned lcda_b_1_pins[] = { DB8500_PIN_D22, + DB8500_PIN_C23, DB8500_PIN_D23 }; +static const unsigned lcd_b_1_pins[] = { DB8500_PIN_D17, DB8500_PIN_D16, + DB8500_PIN_B17, DB8500_PIN_C16, DB8500_PIN_C19, DB8500_PIN_C17, + DB8500_PIN_A18, DB8500_PIN_C18, DB8500_PIN_B19, DB8500_PIN_B20, + DB8500_PIN_D21, DB8500_PIN_D20, DB8500_PIN_C20, DB8500_PIN_B21, + DB8500_PIN_C21, DB8500_PIN_A22, DB8500_PIN_B24, DB8500_PIN_C22 }; +static const unsigned ddrtrig_b_1_pins[] = { DB8500_PIN_AJ27 }; +static const unsigned pwl_b_1_pins[] = { DB8500_PIN_AF25 }; +static const unsigned spi1_b_1_pins[] = { DB8500_PIN_AG15, DB8500_PIN_AF13, + DB8500_PIN_AG13, DB8500_PIN_AH15 }; +static const unsigned mc3_b_1_pins[] = { DB8500_PIN_AH13, DB8500_PIN_AG12, + DB8500_PIN_AH12, DB8500_PIN_AH11, DB8500_PIN_AG10, DB8500_PIN_AH10, + DB8500_PIN_AJ11, DB8500_PIN_AJ9, DB8500_PIN_AH9, DB8500_PIN_AG9, + DB8500_PIN_AG8 }; +static const unsigned pwl_b_2_pins[] = { DB8500_PIN_AF8 }; +static const unsigned pwl_b_3_pins[] = { DB8500_PIN_AG7 }; +static const unsigned pwl_b_4_pins[] = { DB8500_PIN_AF7 }; + +/* Altfunction C column */ +static const unsigned ipjtag_c_1_pins[] = { DB8500_PIN_AJ5, DB8500_PIN_AJ3, + DB8500_PIN_AH4, DB8500_PIN_AH3, DB8500_PIN_AH6 }; +static const unsigned ipgpio6_c_1_pins[] = { DB8500_PIN_AG6 }; +static const unsigned ipgpio0_c_1_pins[] = { DB8500_PIN_AF6 }; +static const unsigned ipgpio1_c_1_pins[] = { DB8500_PIN_AG5 }; +static const unsigned ipgpio3_c_1_pins[] = { DB8500_PIN_AF5 }; +static const unsigned ipgpio2_c_1_pins[] = { DB8500_PIN_AG4 }; +static const unsigned slim0_c_1_pins[] = { DB8500_PIN_AD3, DB8500_PIN_AD4 }; +/* Optional 4-bit Memory Stick interface */ +static const unsigned ms_c_1_pins[] = { DB8500_PIN_AC2, DB8500_PIN_AC1, + DB8500_PIN_AB3, DB8500_PIN_AA3, DB8500_PIN_AA4, DB8500_PIN_AB2, + DB8500_PIN_Y4, DB8500_PIN_Y2, DB8500_PIN_AA2, DB8500_PIN_AA1 }; +static const unsigned iptrigout_c_1_pins[] = { DB8500_PIN_AB4 }; +static const unsigned u2rxtx_c_1_pins[] = { DB8500_PIN_W2, DB8500_PIN_W3 }; +static const unsigned u2ctsrts_c_1_pins[] = { DB8500_PIN_V3, DB8500_PIN_V2 }; +static const unsigned u0_c_1_pins[] = { DB8500_PIN_AF2, DB8500_PIN_AE1, + DB8500_PIN_AE2, DB8500_PIN_AG2 }; +static const unsigned ipgpio4_c_1_pins[] = { DB8500_PIN_F3 }; +static const unsigned ipgpio5_c_1_pins[] = { DB8500_PIN_F1 }; +static const unsigned ipgpio6_c_2_pins[] = { DB8500_PIN_G3 }; +static const unsigned ipgpio7_c_1_pins[] = { DB8500_PIN_G2 }; +static const unsigned smcleale_c_1_pins[] = { DB8500_PIN_E1, DB8500_PIN_E2 }; +static const unsigned stmape_c_1_pins[] = { DB8500_PIN_G5, DB8500_PIN_G4, + DB8500_PIN_H4, DB8500_PIN_H3, DB8500_PIN_J3 }; +static const unsigned u2rxtx_c_2_pins[] = { DB8500_PIN_H2, DB8500_PIN_J2 }; +static const unsigned ipgpio2_c_2_pins[] = { DB8500_PIN_F4 }; +static const unsigned ipgpio3_c_2_pins[] = { DB8500_PIN_E3 }; +static const unsigned ipgpio4_c_2_pins[] = { DB8500_PIN_E4 }; +static const unsigned ipgpio5_c_2_pins[] = { DB8500_PIN_D2 }; +static const unsigned mc5_c_1_pins[] = { DB8500_PIN_C6, DB8500_PIN_B3, + DB8500_PIN_C4, DB8500_PIN_E6, DB8500_PIN_A3, DB8500_PIN_B6, + DB8500_PIN_D6, DB8500_PIN_B7, DB8500_PIN_D7, DB8500_PIN_D8, + DB8500_PIN_D9 }; +static const unsigned mc2rstn_c_1_pins[] = { DB8500_PIN_C8 }; +static const unsigned kp_c_1_pins[] = { DB8500_PIN_C9, DB8500_PIN_B11, + DB8500_PIN_C12, DB8500_PIN_C11, DB8500_PIN_D17, DB8500_PIN_D16, + DB8500_PIN_C23, DB8500_PIN_D23 }; +static const unsigned smps1_c_1_pins[] = { DB8500_PIN_B14 }; +static const unsigned u2rxtx_c_3_pins[] = { DB8500_PIN_B17, DB8500_PIN_C16 }; +static const unsigned stmape_c_2_pins[] = { DB8500_PIN_C19, DB8500_PIN_C17, + DB8500_PIN_A18, DB8500_PIN_C18, DB8500_PIN_B19 }; +static const unsigned uartmodrx_c_1_pins[] = { DB8500_PIN_D21 }; +static const unsigned uartmodtx_c_1_pins[] = { DB8500_PIN_D20 }; +static const unsigned stmmod_c_1_pins[] = { DB8500_PIN_C20, DB8500_PIN_B21, + DB8500_PIN_C21, DB8500_PIN_A22, DB8500_PIN_B24 }; +static const unsigned usbsim_c_1_pins[] = { DB8500_PIN_D22 }; +static const unsigned mc4rstn_c_1_pins[] = { DB8500_PIN_AF25 }; +static const unsigned clkout_c_1_pins[] = { DB8500_PIN_AH13, DB8500_PIN_AH12 }; +static const unsigned i2c3_c_1_pins[] = { DB8500_PIN_AG12, DB8500_PIN_AH11 }; +static const unsigned spi0_c_1_pins[] = { DB8500_PIN_AH10, DB8500_PIN_AH9, + DB8500_PIN_AG9, DB8500_PIN_AG8 }; +static const unsigned usbsim_c_2_pins[] = { DB8500_PIN_AF8 }; +static const unsigned i2c3_c_2_pins[] = { DB8500_PIN_AG7, DB8500_PIN_AF7 }; + +/* Other C1 column */ +static const unsigned kp_oc1_1_pins[] = { DB8500_PIN_C6, DB8500_PIN_B3, + DB8500_PIN_C4, DB8500_PIN_E6, DB8500_PIN_A3, DB8500_PIN_B6, + DB8500_PIN_D6, DB8500_PIN_B7 }; +static const unsigned spi2_oc1_1_pins[] = { DB8500_PIN_AH13, DB8500_PIN_AG12, + DB8500_PIN_AH12, DB8500_PIN_AH11 }; + +#define DB8500_PIN_GROUP(a,b) { .name = #a, .pins = a##_pins, \ + .npins = ARRAY_SIZE(a##_pins), .altsetting = b } + +static const struct nmk_pingroup nmk_db8500_groups[] = { + /* Altfunction A column */ + DB8500_PIN_GROUP(u0_a_1, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(u1rxtx_a_1, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(u1ctsrts_a_1, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(ipi2c_a_1, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(ipi2c_a_2, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(msp0txrx_a_1, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(msp0tfstck_a_1, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(msp0rfsrck_a_1, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(mc0_a_1, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(msp1txrx_a_1, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(msp1_a_1, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(lcdb_a_1, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(lcdvsi0_a_1, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(lcdvsi1_a_1, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(lcd_d0_d7_a_1, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(lcd_d8_d11_a_1, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(lcd_d12_d23_a_1, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(kp_a_1, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(mc2_a_1, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(ssp1_a_1, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(ssp0_a_1, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(i2c0_a_1, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(ipgpio0_a_1, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(ipgpio1_a_1, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(msp2sck_a_1, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(msp2_a_1, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(mc4_a_1, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(mc1_a_1, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(hsir_a_1, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(hsit_a_1, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(clkout_a_1, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(clkout_a_2, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(usb_a_1, NMK_GPIO_ALT_A), + /* Altfunction B column */ + DB8500_PIN_GROUP(trig_b_1, NMK_GPIO_ALT_B), + DB8500_PIN_GROUP(i2c4_b_1, NMK_GPIO_ALT_B), + DB8500_PIN_GROUP(i2c1_b_1, NMK_GPIO_ALT_B), + DB8500_PIN_GROUP(i2c2_b_1, NMK_GPIO_ALT_B), + DB8500_PIN_GROUP(i2c2_b_2, NMK_GPIO_ALT_B), + DB8500_PIN_GROUP(msp0txrx_b_1, NMK_GPIO_ALT_B), + DB8500_PIN_GROUP(i2c1_b_2, NMK_GPIO_ALT_B), + DB8500_PIN_GROUP(u2rxtx_b_1, NMK_GPIO_ALT_B), + DB8500_PIN_GROUP(uartmodtx_b_1, NMK_GPIO_ALT_B), + DB8500_PIN_GROUP(msp0sck_b_1, NMK_GPIO_ALT_B), + DB8500_PIN_GROUP(uartmodrx_b_1, NMK_GPIO_ALT_B), + DB8500_PIN_GROUP(stmmod_b_1, NMK_GPIO_ALT_B), + DB8500_PIN_GROUP(uartmodrx_b_2, NMK_GPIO_ALT_B), + DB8500_PIN_GROUP(spi3_b_1, NMK_GPIO_ALT_B), + DB8500_PIN_GROUP(msp1txrx_b_1, NMK_GPIO_ALT_B), + DB8500_PIN_GROUP(kp_b_1, NMK_GPIO_ALT_B), + DB8500_PIN_GROUP(sm_b_1, NMK_GPIO_ALT_B), + DB8500_PIN_GROUP(smcs0_b_1, NMK_GPIO_ALT_B), + DB8500_PIN_GROUP(ipgpio7_b_1, NMK_GPIO_ALT_B), + DB8500_PIN_GROUP(ipgpio2_b_1, NMK_GPIO_ALT_B), + DB8500_PIN_GROUP(ipgpio3_b_1, NMK_GPIO_ALT_B), + DB8500_PIN_GROUP(lcdaclk_b_1, NMK_GPIO_ALT_B), + DB8500_PIN_GROUP(lcda_b_1, NMK_GPIO_ALT_B), + DB8500_PIN_GROUP(lcd_b_1, NMK_GPIO_ALT_B), + DB8500_PIN_GROUP(ddrtrig_b_1, NMK_GPIO_ALT_B), + DB8500_PIN_GROUP(pwl_b_1, NMK_GPIO_ALT_B), + DB8500_PIN_GROUP(spi1_b_1, NMK_GPIO_ALT_B), + DB8500_PIN_GROUP(mc3_b_1, NMK_GPIO_ALT_B), + DB8500_PIN_GROUP(pwl_b_2, NMK_GPIO_ALT_B), + DB8500_PIN_GROUP(pwl_b_3, NMK_GPIO_ALT_B), + DB8500_PIN_GROUP(pwl_b_4, NMK_GPIO_ALT_B), + /* Altfunction C column */ + DB8500_PIN_GROUP(ipjtag_c_1, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(ipgpio6_c_1, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(ipgpio0_c_1, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(ipgpio1_c_1, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(ipgpio3_c_1, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(ipgpio2_c_1, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(slim0_c_1, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(ms_c_1, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(iptrigout_c_1, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(u2rxtx_c_1, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(u2ctsrts_c_1, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(u0_c_1, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(ipgpio4_c_1, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(ipgpio5_c_1, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(ipgpio6_c_1, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(ipgpio7_c_1, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(smcleale_c_1, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(stmape_c_1, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(u2rxtx_c_2, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(ipgpio2_c_2, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(ipgpio3_c_2, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(ipgpio4_c_2, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(ipgpio5_c_2, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(mc5_c_1, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(mc2rstn_c_1, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(kp_c_1, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(smps1_c_1, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(u2rxtx_c_3, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(stmape_c_2, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(uartmodrx_c_1, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(uartmodtx_c_1, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(stmmod_c_1, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(usbsim_c_1, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(mc4rstn_c_1, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(clkout_c_1, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(i2c3_c_1, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(spi0_c_1, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(usbsim_c_2, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(i2c3_c_2, NMK_GPIO_ALT_C), + /* Other alt C1 column, these are still configured as alt C */ + DB8500_PIN_GROUP(kp_oc1_1, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(spi2_oc1_1, NMK_GPIO_ALT_C), +}; + +/* We use this macro to define the groups applicable to a function */ +#define DB8500_FUNC_GROUPS(a, b...) \ +static const char * const a##_groups[] = { b }; + +DB8500_FUNC_GROUPS(u0, "u0_a_1", "u0_c_1"); +DB8500_FUNC_GROUPS(u1, "u1rxtx_a_1", "u1ctsrts_a_1"); +/* + * UART2 can be muxed out with just RX/TX in four places, CTS+RTS is however + * only available on two pins in alternative function C + */ +DB8500_FUNC_GROUPS(u2, "u2rxtx_b_1", "u2rxtx_c_1", "u2ctsrts_c_1", + "u2rxtx_c_2", "u2rxtx_c_3"); +DB8500_FUNC_GROUPS(ipi2c, "ipi2c_a_1", "ipi2c_a_2"); +/* + * MSP0 can only be on a certain set of pins, but the TX/RX pins can be + * switched around by selecting the altfunction A or B. The SCK pin is + * only available on the altfunction B. + */ +DB8500_FUNC_GROUPS(msp0, "msp0txrx_a_1", "msp0tfstck_a_1", "msp0rfstck_a_1", + "msp0txrx_b_1", "msp0sck_b_1"); +DB8500_FUNC_GROUPS(mc0, "mc0_a_1"); +/* MSP0 can swap RX/TX like MSP0 but has no SCK pin available */ +DB8500_FUNC_GROUPS(msp1, "msp1txrx_a_1", "msp1_a_1", "msp1txrx_b_1"); +DB8500_FUNC_GROUPS(lcdb, "lcdb_a_1"); +DB8500_FUNC_GROUPS(lcd, "lcdvsi0_a_1", "lcdvsi1_a_1", "lcd_d0_d7_a_1", + "lcd_d8_d11_a_1", "lcd_d12_d23_a_1", "lcd_b_1"); +DB8500_FUNC_GROUPS(kp, "kp_a_1", "kp_b_1", "kp_c_1", "kp_oc1_1"); +DB8500_FUNC_GROUPS(mc2, "mc2_a_1", "mc2rstn_c_1"); +DB8500_FUNC_GROUPS(ssp1, "ssp1_a_1"); +DB8500_FUNC_GROUPS(ssp0, "ssp0_a_1"); +DB8500_FUNC_GROUPS(i2c0, "i2c0_a_1"); +/* The image processor has 8 GPIO pins that can be muxed out */ +DB8500_FUNC_GROUPS(ipgpio, "ipgpio0_a_1", "ipgpio1_a_1", "ipgpio7_b_1", + "ipgpio2_b_1", "ipgpio3_b_1", "ipgpio6_c_1", "ipgpio0_c_1", + "ipgpio1_c_1", "ipgpio3_c_1", "ipgpio2_c_1", "ipgpio4_c_1", + "ipgpio5_c_1", "ipgpio6_c_2", "ipgpio7_c_1", "ipgpio2_c_2", + "ipgpio3_c_2", "ipgpio4_c_2", "ipgpio5_c_2"); +/* MSP2 can not invert the RX/TX pins but has the optional SCK pin */ +DB8500_FUNC_GROUPS(msp2, "msp2sck_a_1", "msp2_a_1"); +DB8500_FUNC_GROUPS(mc4, "mc4_a_1", "mc4rstn_c_1"); +DB8500_FUNC_GROUPS(mc1, "mc1_a_1", "mc1dir_a_1"); +DB8500_FUNC_GROUPS(hsi, "hsir1_a_1", "hsit1_a_1"); +DB8500_FUNC_GROUPS(clkout, "clkout_a_1", "clkout_a_2", "clkout_c_1"); +DB8500_FUNC_GROUPS(usb, "usb_a_1"); +DB8500_FUNC_GROUPS(trig, "trig_b_1"); +DB8500_FUNC_GROUPS(i2c4, "i2c4_b_1"); +DB8500_FUNC_GROUPS(i2c1, "i2c1_b_1", "i2c1_b_2"); +DB8500_FUNC_GROUPS(i2c2, "i2c2_b_1", "i2c2_b_2"); +/* + * The modem UART can output its RX and TX pins in some different places, + * so select one of each. + */ +DB8500_FUNC_GROUPS(uartmod, "uartmodtx_b_1", "uartmodrx_b_1", "uartmodrx_b_2", + "uartmodrx_c_1", "uartmod_tx_c_1"); +DB8500_FUNC_GROUPS(stmmod, "stmmod_b_1", "stmmod_c_1"); +DB8500_FUNC_GROUPS(spi3, "spi3_b_1"); +/* Select between CS0 on alt B or PS1 on alt C */ +DB8500_FUNC_GROUPS(sm, "sm_b_1", "smcs0_b_1", "smcleale_c_1", "smps1_c_1"); +DB8500_FUNC_GROUPS(lcda, "lcdaclk_b_1", "lcda_b_1"); +DB8500_FUNC_GROUPS(ddrtrig, "ddrtrig_b_1"); +DB8500_FUNC_GROUPS(pwl, "pwl_b_1", "pwl_b_2", "pwl_b_3", "pwl_b_4"); +DB8500_FUNC_GROUPS(spi1, "spi1_b_1"); +DB8500_FUNC_GROUPS(mc3, "mc3_b_1"); +DB8500_FUNC_GROUPS(ipjtag, "ipjtag_c_1"); +DB8500_FUNC_GROUPS(slim0, "slim0_c_1"); +DB8500_FUNC_GROUPS(ms, "ms_c_1"); +DB8500_FUNC_GROUPS(iptrigout, "iptrigout_c_1"); +DB8500_FUNC_GROUPS(stmape, "stmape_c_1", "stmape_c_2"); +DB8500_FUNC_GROUPS(mc5, "mc5_c_1"); +DB8500_FUNC_GROUPS(usbsim, "usbsim_c_1", "usbsim_c_2"); +DB8500_FUNC_GROUPS(i2c3, "i2c3_c_1", "i2c3_c_2"); +DB8500_FUNC_GROUPS(spi0, "spi0_c_1"); +DB8500_FUNC_GROUPS(spi2, "spi2_oc1_1"); + +#define FUNCTION(fname) \ + { \ + .name = #fname, \ + .groups = fname##_groups, \ + .ngroups = ARRAY_SIZE(fname##_groups), \ + } + +static const struct nmk_function nmk_db8500_functions[] = { + FUNCTION(u0), + FUNCTION(u1), + FUNCTION(u2), + FUNCTION(ipi2c), + FUNCTION(msp0), + FUNCTION(mc0), + FUNCTION(msp1), + FUNCTION(lcdb), + FUNCTION(lcd), + FUNCTION(kp), + FUNCTION(mc2), + FUNCTION(ssp1), + FUNCTION(ssp0), + FUNCTION(i2c0), + FUNCTION(ipgpio), + FUNCTION(msp2), + FUNCTION(mc4), + FUNCTION(mc1), + FUNCTION(hsi), + FUNCTION(clkout), + FUNCTION(usb), + FUNCTION(trig), + FUNCTION(i2c4), + FUNCTION(i2c1), + FUNCTION(i2c2), + FUNCTION(uartmod), + FUNCTION(stmmod), + FUNCTION(spi3), + FUNCTION(sm), + FUNCTION(lcda), + FUNCTION(ddrtrig), + FUNCTION(pwl), + FUNCTION(spi1), + FUNCTION(mc3), + FUNCTION(ipjtag), + FUNCTION(slim0), + FUNCTION(ms), + FUNCTION(iptrigout), + FUNCTION(stmape), + FUNCTION(mc5), + FUNCTION(usbsim), + FUNCTION(i2c3), + FUNCTION(spi0), + FUNCTION(spi2), +}; + +static const struct nmk_pinctrl_soc_data nmk_db8500_soc = { + .gpio_ranges = nmk_db8500_ranges, + .gpio_num_ranges = ARRAY_SIZE(nmk_db8500_ranges), + .pins = nmk_db8500_pins, + .npins = ARRAY_SIZE(nmk_db8500_pins), + .functions = nmk_db8500_functions, + .nfunctions = ARRAY_SIZE(nmk_db8500_functions), + .groups = nmk_db8500_groups, + .ngroups = ARRAY_SIZE(nmk_db8500_groups), +}; + +void __devinit +nmk_pinctrl_db8500_init(const struct nmk_pinctrl_soc_data **soc) +{ + *soc = &nmk_db8500_soc; +} diff --git a/drivers/pinctrl/pinctrl-nomadik.c b/drivers/pinctrl/pinctrl-nomadik.c new file mode 100644 index 000000000000..b8e01c3eaa95 --- /dev/null +++ b/drivers/pinctrl/pinctrl-nomadik.c @@ -0,0 +1,1780 @@ +/* + * Generic GPIO driver for logic cells found in the Nomadik SoC + * + * Copyright (C) 2008,2009 STMicroelectronics + * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it> + * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com> + * Copyright (C) 2011 Linus Walleij <linus.walleij@linaro.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/init.h> +#include <linux/device.h> +#include <linux/platform_device.h> +#include <linux/io.h> +#include <linux/clk.h> +#include <linux/err.h> +#include <linux/gpio.h> +#include <linux/spinlock.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/irqdomain.h> +#include <linux/slab.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/pinctrl/pinconf.h> +/* Since we request GPIOs from ourself */ +#include <linux/pinctrl/consumer.h> + +#include <asm/mach/irq.h> + +#include <plat/pincfg.h> +#include <plat/gpio-nomadik.h> + +#include "pinctrl-nomadik.h" + +/* + * The GPIO module in the Nomadik family of Systems-on-Chip is an + * AMBA device, managing 32 pins and alternate functions. The logic block + * is currently used in the Nomadik and ux500. + * + * Symbols in this file are called "nmk_gpio" for "nomadik gpio" + */ + +#define NMK_GPIO_PER_CHIP 32 + +struct nmk_gpio_chip { + struct gpio_chip chip; + struct irq_domain *domain; + void __iomem *addr; + struct clk *clk; + unsigned int bank; + unsigned int parent_irq; + int secondary_parent_irq; + u32 (*get_secondary_status)(unsigned int bank); + void (*set_ioforce)(bool enable); + spinlock_t lock; + bool sleepmode; + /* Keep track of configured edges */ + u32 edge_rising; + u32 edge_falling; + u32 real_wake; + u32 rwimsc; + u32 fwimsc; + u32 rimsc; + u32 fimsc; + u32 pull_up; + u32 lowemi; +}; + +struct nmk_pinctrl { + struct device *dev; + struct pinctrl_dev *pctl; + const struct nmk_pinctrl_soc_data *soc; +}; + +static struct nmk_gpio_chip * +nmk_gpio_chips[DIV_ROUND_UP(ARCH_NR_GPIOS, NMK_GPIO_PER_CHIP)]; + +static DEFINE_SPINLOCK(nmk_gpio_slpm_lock); + +#define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips) + +static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip, + unsigned offset, int gpio_mode) +{ + u32 bit = 1 << offset; + u32 afunc, bfunc; + + afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~bit; + bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~bit; + if (gpio_mode & NMK_GPIO_ALT_A) + afunc |= bit; + if (gpio_mode & NMK_GPIO_ALT_B) + bfunc |= bit; + writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA); + writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB); +} + +static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip, + unsigned offset, enum nmk_gpio_slpm mode) +{ + u32 bit = 1 << offset; + u32 slpm; + + slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC); + if (mode == NMK_GPIO_SLPM_NOCHANGE) + slpm |= bit; + else + slpm &= ~bit; + writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC); +} + +static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip, + unsigned offset, enum nmk_gpio_pull pull) +{ + u32 bit = 1 << offset; + u32 pdis; + + pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS); + if (pull == NMK_GPIO_PULL_NONE) { + pdis |= bit; + nmk_chip->pull_up &= ~bit; + } else { + pdis &= ~bit; + } + + writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS); + + if (pull == NMK_GPIO_PULL_UP) { + nmk_chip->pull_up |= bit; + writel(bit, nmk_chip->addr + NMK_GPIO_DATS); + } else if (pull == NMK_GPIO_PULL_DOWN) { + nmk_chip->pull_up &= ~bit; + writel(bit, nmk_chip->addr + NMK_GPIO_DATC); + } +} + +static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip *nmk_chip, + unsigned offset, bool lowemi) +{ + u32 bit = BIT(offset); + bool enabled = nmk_chip->lowemi & bit; + + if (lowemi == enabled) + return; + + if (lowemi) + nmk_chip->lowemi |= bit; + else + nmk_chip->lowemi &= ~bit; + + writel_relaxed(nmk_chip->lowemi, + nmk_chip->addr + NMK_GPIO_LOWEMI); +} + +static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip, + unsigned offset) +{ + writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC); +} + +static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip, + unsigned offset, int val) +{ + if (val) + writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATS); + else + writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATC); +} + +static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip, + unsigned offset, int val) +{ + writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS); + __nmk_gpio_set_output(nmk_chip, offset, val); +} + +static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip, + unsigned offset, int gpio_mode, + bool glitch) +{ + u32 rwimsc = nmk_chip->rwimsc; + u32 fwimsc = nmk_chip->fwimsc; + + if (glitch && nmk_chip->set_ioforce) { + u32 bit = BIT(offset); + + /* Prevent spurious wakeups */ + writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC); + writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC); + + nmk_chip->set_ioforce(true); + } + + __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode); + + if (glitch && nmk_chip->set_ioforce) { + nmk_chip->set_ioforce(false); + + writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC); + writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC); + } +} + +static void +nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset) +{ + u32 falling = nmk_chip->fimsc & BIT(offset); + u32 rising = nmk_chip->rimsc & BIT(offset); + int gpio = nmk_chip->chip.base + offset; + int irq = NOMADIK_GPIO_TO_IRQ(gpio); + struct irq_data *d = irq_get_irq_data(irq); + + if (!rising && !falling) + return; + + if (!d || !irqd_irq_disabled(d)) + return; + + if (rising) { + nmk_chip->rimsc &= ~BIT(offset); + writel_relaxed(nmk_chip->rimsc, + nmk_chip->addr + NMK_GPIO_RIMSC); + } + + if (falling) { + nmk_chip->fimsc &= ~BIT(offset); + writel_relaxed(nmk_chip->fimsc, + nmk_chip->addr + NMK_GPIO_FIMSC); + } + + dev_dbg(nmk_chip->chip.dev, "%d: clearing interrupt mask\n", gpio); +} + +static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset, + pin_cfg_t cfg, bool sleep, unsigned int *slpmregs) +{ + static const char *afnames[] = { + [NMK_GPIO_ALT_GPIO] = "GPIO", + [NMK_GPIO_ALT_A] = "A", + [NMK_GPIO_ALT_B] = "B", + [NMK_GPIO_ALT_C] = "C" + }; + static const char *pullnames[] = { + [NMK_GPIO_PULL_NONE] = "none", + [NMK_GPIO_PULL_UP] = "up", + [NMK_GPIO_PULL_DOWN] = "down", + [3] /* illegal */ = "??" + }; + static const char *slpmnames[] = { + [NMK_GPIO_SLPM_INPUT] = "input/wakeup", + [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup", + }; + + int pin = PIN_NUM(cfg); + int pull = PIN_PULL(cfg); + int af = PIN_ALT(cfg); + int slpm = PIN_SLPM(cfg); + int output = PIN_DIR(cfg); + int val = PIN_VAL(cfg); + bool glitch = af == NMK_GPIO_ALT_C; + + dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: af %s, pull %s, slpm %s (%s%s)\n", + pin, cfg, afnames[af], pullnames[pull], slpmnames[slpm], + output ? "output " : "input", + output ? (val ? "high" : "low") : ""); + + if (sleep) { + int slpm_pull = PIN_SLPM_PULL(cfg); + int slpm_output = PIN_SLPM_DIR(cfg); + int slpm_val = PIN_SLPM_VAL(cfg); + + af = NMK_GPIO_ALT_GPIO; + + /* + * The SLPM_* values are normal values + 1 to allow zero to + * mean "same as normal". + */ + if (slpm_pull) + pull = slpm_pull - 1; + if (slpm_output) + output = slpm_output - 1; + if (slpm_val) + val = slpm_val - 1; + + dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n", + pin, + slpm_pull ? pullnames[pull] : "same", + slpm_output ? (output ? "output" : "input") : "same", + slpm_val ? (val ? "high" : "low") : "same"); + } + + if (output) + __nmk_gpio_make_output(nmk_chip, offset, val); + else { + __nmk_gpio_make_input(nmk_chip, offset); + __nmk_gpio_set_pull(nmk_chip, offset, pull); + } + + __nmk_gpio_set_lowemi(nmk_chip, offset, PIN_LOWEMI(cfg)); + + /* + * If the pin is switching to altfunc, and there was an interrupt + * installed on it which has been lazy disabled, actually mask the + * interrupt to prevent spurious interrupts that would occur while the + * pin is under control of the peripheral. Only SKE does this. + */ + if (af != NMK_GPIO_ALT_GPIO) + nmk_gpio_disable_lazy_irq(nmk_chip, offset); + + /* + * If we've backed up the SLPM registers (glitch workaround), modify + * the backups since they will be restored. + */ + if (slpmregs) { + if (slpm == NMK_GPIO_SLPM_NOCHANGE) + slpmregs[nmk_chip->bank] |= BIT(offset); + else + slpmregs[nmk_chip->bank] &= ~BIT(offset); + } else + __nmk_gpio_set_slpm(nmk_chip, offset, slpm); + + __nmk_gpio_set_mode_safe(nmk_chip, offset, af, glitch); +} + +/* + * Safe sequence used to switch IOs between GPIO and Alternate-C mode: + * - Save SLPM registers + * - Set SLPM=0 for the IOs you want to switch and others to 1 + * - Configure the GPIO registers for the IOs that are being switched + * - Set IOFORCE=1 + * - Modify the AFLSA/B registers for the IOs that are being switched + * - Set IOFORCE=0 + * - Restore SLPM registers + * - Any spurious wake up event during switch sequence to be ignored and + * cleared + */ +static void nmk_gpio_glitch_slpm_init(unsigned int *slpm) +{ + int i; + + for (i = 0; i < NUM_BANKS; i++) { + struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; + unsigned int temp = slpm[i]; + + if (!chip) + break; + + clk_enable(chip->clk); + + slpm[i] = readl(chip->addr + NMK_GPIO_SLPC); + writel(temp, chip->addr + NMK_GPIO_SLPC); + } +} + +static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm) +{ + int i; + + for (i = 0; i < NUM_BANKS; i++) { + struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; + + if (!chip) + break; + + writel(slpm[i], chip->addr + NMK_GPIO_SLPC); + + clk_disable(chip->clk); + } +} + +static int __nmk_config_pins(pin_cfg_t *cfgs, int num, bool sleep) +{ + static unsigned int slpm[NUM_BANKS]; + unsigned long flags; + bool glitch = false; + int ret = 0; + int i; + + for (i = 0; i < num; i++) { + if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C) { + glitch = true; + break; + } + } + + spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); + + if (glitch) { + memset(slpm, 0xff, sizeof(slpm)); + + for (i = 0; i < num; i++) { + int pin = PIN_NUM(cfgs[i]); + int offset = pin % NMK_GPIO_PER_CHIP; + + if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C) + slpm[pin / NMK_GPIO_PER_CHIP] &= ~BIT(offset); + } + + nmk_gpio_glitch_slpm_init(slpm); + } + + for (i = 0; i < num; i++) { + struct nmk_gpio_chip *nmk_chip; + int pin = PIN_NUM(cfgs[i]); + + nmk_chip = nmk_gpio_chips[pin / NMK_GPIO_PER_CHIP]; + if (!nmk_chip) { + ret = -EINVAL; + break; + } + + clk_enable(nmk_chip->clk); + spin_lock(&nmk_chip->lock); + __nmk_config_pin(nmk_chip, pin % NMK_GPIO_PER_CHIP, + cfgs[i], sleep, glitch ? slpm : NULL); + spin_unlock(&nmk_chip->lock); + clk_disable(nmk_chip->clk); + } + + if (glitch) + nmk_gpio_glitch_slpm_restore(slpm); + + spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); + + return ret; +} + +/** + * nmk_config_pin - configure a pin's mux attributes + * @cfg: pin confguration + * + * Configures a pin's mode (alternate function or GPIO), its pull up status, + * and its sleep mode based on the specified configuration. The @cfg is + * usually one of the SoC specific macros defined in mach/<soc>-pins.h. These + * are constructed using, and can be further enhanced with, the macros in + * plat/pincfg.h. + * + * If a pin's mode is set to GPIO, it is configured as an input to avoid + * side-effects. The gpio can be manipulated later using standard GPIO API + * calls. + */ +int nmk_config_pin(pin_cfg_t cfg, bool sleep) +{ + return __nmk_config_pins(&cfg, 1, sleep); +} +EXPORT_SYMBOL(nmk_config_pin); + +/** + * nmk_config_pins - configure several pins at once + * @cfgs: array of pin configurations + * @num: number of elments in the array + * + * Configures several pins using nmk_config_pin(). Refer to that function for + * further information. + */ +int nmk_config_pins(pin_cfg_t *cfgs, int num) +{ + return __nmk_config_pins(cfgs, num, false); +} +EXPORT_SYMBOL(nmk_config_pins); + +int nmk_config_pins_sleep(pin_cfg_t *cfgs, int num) +{ + return __nmk_config_pins(cfgs, num, true); +} +EXPORT_SYMBOL(nmk_config_pins_sleep); + +/** + * nmk_gpio_set_slpm() - configure the sleep mode of a pin + * @gpio: pin number + * @mode: NMK_GPIO_SLPM_INPUT or NMK_GPIO_SLPM_NOCHANGE, + * + * This register is actually in the pinmux layer, not the GPIO block itself. + * The GPIO1B_SLPM register defines the GPIO mode when SLEEP/DEEP-SLEEP + * mode is entered (i.e. when signal IOFORCE is HIGH by the platform code). + * Each GPIO can be configured to be forced into GPIO mode when IOFORCE is + * HIGH, overriding the normal setting defined by GPIO_AFSELx registers. + * When IOFORCE returns LOW (by software, after SLEEP/DEEP-SLEEP exit), + * the GPIOs return to the normal setting defined by GPIO_AFSELx registers. + * + * If @mode is NMK_GPIO_SLPM_INPUT, the corresponding GPIO is switched to GPIO + * mode when signal IOFORCE is HIGH (i.e. when SLEEP/DEEP-SLEEP mode is + * entered) regardless of the altfunction selected. Also wake-up detection is + * ENABLED. + * + * If @mode is NMK_GPIO_SLPM_NOCHANGE, the corresponding GPIO remains + * controlled by NMK_GPIO_DATC, NMK_GPIO_DATS, NMK_GPIO_DIR, NMK_GPIO_PDIS + * (for altfunction GPIO) or respective on-chip peripherals (for other + * altfuncs) when IOFORCE is HIGH. Also wake-up detection DISABLED. + * + * Note that enable_irq_wake() will automatically enable wakeup detection. + */ +int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode) +{ + struct nmk_gpio_chip *nmk_chip; + unsigned long flags; + + nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP]; + if (!nmk_chip) + return -EINVAL; + + clk_enable(nmk_chip->clk); + spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); + spin_lock(&nmk_chip->lock); + + __nmk_gpio_set_slpm(nmk_chip, gpio % NMK_GPIO_PER_CHIP, mode); + + spin_unlock(&nmk_chip->lock); + spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); + clk_disable(nmk_chip->clk); + + return 0; +} + +/** + * nmk_gpio_set_pull() - enable/disable pull up/down on a gpio + * @gpio: pin number + * @pull: one of NMK_GPIO_PULL_DOWN, NMK_GPIO_PULL_UP, and NMK_GPIO_PULL_NONE + * + * Enables/disables pull up/down on a specified pin. This only takes effect if + * the pin is configured as an input (either explicitly or by the alternate + * function). + * + * NOTE: If enabling the pull up/down, the caller must ensure that the GPIO is + * configured as an input. Otherwise, due to the way the controller registers + * work, this function will change the value output on the pin. + */ +int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull) +{ + struct nmk_gpio_chip *nmk_chip; + unsigned long flags; + + nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP]; + if (!nmk_chip) + return -EINVAL; + + clk_enable(nmk_chip->clk); + spin_lock_irqsave(&nmk_chip->lock, flags); + __nmk_gpio_set_pull(nmk_chip, gpio % NMK_GPIO_PER_CHIP, pull); + spin_unlock_irqrestore(&nmk_chip->lock, flags); + clk_disable(nmk_chip->clk); + + return 0; +} + +/* Mode functions */ +/** + * nmk_gpio_set_mode() - set the mux mode of a gpio pin + * @gpio: pin number + * @gpio_mode: one of NMK_GPIO_ALT_GPIO, NMK_GPIO_ALT_A, + * NMK_GPIO_ALT_B, and NMK_GPIO_ALT_C + * + * Sets the mode of the specified pin to one of the alternate functions or + * plain GPIO. + */ +int nmk_gpio_set_mode(int gpio, int gpio_mode) +{ + struct nmk_gpio_chip *nmk_chip; + unsigned long flags; + + nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP]; + if (!nmk_chip) + return -EINVAL; + + clk_enable(nmk_chip->clk); + spin_lock_irqsave(&nmk_chip->lock, flags); + __nmk_gpio_set_mode(nmk_chip, gpio % NMK_GPIO_PER_CHIP, gpio_mode); + spin_unlock_irqrestore(&nmk_chip->lock, flags); + clk_disable(nmk_chip->clk); + + return 0; +} +EXPORT_SYMBOL(nmk_gpio_set_mode); + +int nmk_gpio_get_mode(int gpio) +{ + struct nmk_gpio_chip *nmk_chip; + u32 afunc, bfunc, bit; + + nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP]; + if (!nmk_chip) + return -EINVAL; + + bit = 1 << (gpio % NMK_GPIO_PER_CHIP); + + clk_enable(nmk_chip->clk); + + afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & bit; + bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & bit; + + clk_disable(nmk_chip->clk); + + return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0); +} +EXPORT_SYMBOL(nmk_gpio_get_mode); + + +/* IRQ functions */ +static inline int nmk_gpio_get_bitmask(int gpio) +{ + return 1 << (gpio % NMK_GPIO_PER_CHIP); +} + +static void nmk_gpio_irq_ack(struct irq_data *d) +{ + struct nmk_gpio_chip *nmk_chip; + + nmk_chip = irq_data_get_irq_chip_data(d); + if (!nmk_chip) + return; + + clk_enable(nmk_chip->clk); + writel(nmk_gpio_get_bitmask(d->hwirq), nmk_chip->addr + NMK_GPIO_IC); + clk_disable(nmk_chip->clk); +} + +enum nmk_gpio_irq_type { + NORMAL, + WAKE, +}; + +static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip, + int gpio, enum nmk_gpio_irq_type which, + bool enable) +{ + u32 bitmask = nmk_gpio_get_bitmask(gpio); + u32 *rimscval; + u32 *fimscval; + u32 rimscreg; + u32 fimscreg; + + if (which == NORMAL) { + rimscreg = NMK_GPIO_RIMSC; + fimscreg = NMK_GPIO_FIMSC; + rimscval = &nmk_chip->rimsc; + fimscval = &nmk_chip->fimsc; + } else { + rimscreg = NMK_GPIO_RWIMSC; + fimscreg = NMK_GPIO_FWIMSC; + rimscval = &nmk_chip->rwimsc; + fimscval = &nmk_chip->fwimsc; + } + + /* we must individually set/clear the two edges */ + if (nmk_chip->edge_rising & bitmask) { + if (enable) + *rimscval |= bitmask; + else + *rimscval &= ~bitmask; + writel(*rimscval, nmk_chip->addr + rimscreg); + } + if (nmk_chip->edge_falling & bitmask) { + if (enable) + *fimscval |= bitmask; + else + *fimscval &= ~bitmask; + writel(*fimscval, nmk_chip->addr + fimscreg); + } +} + +static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip, + int gpio, bool on) +{ + /* + * Ensure WAKEUP_ENABLE is on. No need to disable it if wakeup is + * disabled, since setting SLPM to 1 increases power consumption, and + * wakeup is anyhow controlled by the RIMSC and FIMSC registers. + */ + if (nmk_chip->sleepmode && on) { + __nmk_gpio_set_slpm(nmk_chip, gpio % nmk_chip->chip.base, + NMK_GPIO_SLPM_WAKEUP_ENABLE); + } + + __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on); +} + +static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable) +{ + struct nmk_gpio_chip *nmk_chip; + unsigned long flags; + u32 bitmask; + + nmk_chip = irq_data_get_irq_chip_data(d); + bitmask = nmk_gpio_get_bitmask(d->hwirq); + if (!nmk_chip) + return -EINVAL; + + clk_enable(nmk_chip->clk); + spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); + spin_lock(&nmk_chip->lock); + + __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, enable); + + if (!(nmk_chip->real_wake & bitmask)) + __nmk_gpio_set_wake(nmk_chip, d->hwirq, enable); + + spin_unlock(&nmk_chip->lock); + spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); + clk_disable(nmk_chip->clk); + + return 0; +} + +static void nmk_gpio_irq_mask(struct irq_data *d) +{ + nmk_gpio_irq_maskunmask(d, false); +} + +static void nmk_gpio_irq_unmask(struct irq_data *d) +{ + nmk_gpio_irq_maskunmask(d, true); +} + +static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on) +{ + struct nmk_gpio_chip *nmk_chip; + unsigned long flags; + u32 bitmask; + + nmk_chip = irq_data_get_irq_chip_data(d); + if (!nmk_chip) + return -EINVAL; + bitmask = nmk_gpio_get_bitmask(d->hwirq); + + clk_enable(nmk_chip->clk); + spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); + spin_lock(&nmk_chip->lock); + + if (irqd_irq_disabled(d)) + __nmk_gpio_set_wake(nmk_chip, d->hwirq, on); + + if (on) + nmk_chip->real_wake |= bitmask; + else + nmk_chip->real_wake &= ~bitmask; + + spin_unlock(&nmk_chip->lock); + spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); + clk_disable(nmk_chip->clk); + + return 0; +} + +static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type) +{ + bool enabled = !irqd_irq_disabled(d); + bool wake = irqd_is_wakeup_set(d); + struct nmk_gpio_chip *nmk_chip; + unsigned long flags; + u32 bitmask; + + nmk_chip = irq_data_get_irq_chip_data(d); + bitmask = nmk_gpio_get_bitmask(d->hwirq); + if (!nmk_chip) + return -EINVAL; + if (type & IRQ_TYPE_LEVEL_HIGH) + return -EINVAL; + if (type & IRQ_TYPE_LEVEL_LOW) + return -EINVAL; + + clk_enable(nmk_chip->clk); + spin_lock_irqsave(&nmk_chip->lock, flags); + + if (enabled) + __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, false); + + if (enabled || wake) + __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, false); + + nmk_chip->edge_rising &= ~bitmask; + if (type & IRQ_TYPE_EDGE_RISING) + nmk_chip->edge_rising |= bitmask; + + nmk_chip->edge_falling &= ~bitmask; + if (type & IRQ_TYPE_EDGE_FALLING) + nmk_chip->edge_falling |= bitmask; + + if (enabled) + __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, true); + + if (enabled || wake) + __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, true); + + spin_unlock_irqrestore(&nmk_chip->lock, flags); + clk_disable(nmk_chip->clk); + + return 0; +} + +static unsigned int nmk_gpio_irq_startup(struct irq_data *d) +{ + struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d); + + clk_enable(nmk_chip->clk); + nmk_gpio_irq_unmask(d); + return 0; +} + +static void nmk_gpio_irq_shutdown(struct irq_data *d) +{ + struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d); + + nmk_gpio_irq_mask(d); + clk_disable(nmk_chip->clk); +} + +static struct irq_chip nmk_gpio_irq_chip = { + .name = "Nomadik-GPIO", + .irq_ack = nmk_gpio_irq_ack, + .irq_mask = nmk_gpio_irq_mask, + .irq_unmask = nmk_gpio_irq_unmask, + .irq_set_type = nmk_gpio_irq_set_type, + .irq_set_wake = nmk_gpio_irq_set_wake, + .irq_startup = nmk_gpio_irq_startup, + .irq_shutdown = nmk_gpio_irq_shutdown, +}; + +static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc, + u32 status) +{ + struct nmk_gpio_chip *nmk_chip; + struct irq_chip *host_chip = irq_get_chip(irq); + unsigned int first_irq; + + chained_irq_enter(host_chip, desc); + + nmk_chip = irq_get_handler_data(irq); + first_irq = nmk_chip->domain->revmap_data.legacy.first_irq; + while (status) { + int bit = __ffs(status); + + generic_handle_irq(first_irq + bit); + status &= ~BIT(bit); + } + + chained_irq_exit(host_chip, desc); +} + +static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) +{ + struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq); + u32 status; + + clk_enable(nmk_chip->clk); + status = readl(nmk_chip->addr + NMK_GPIO_IS); + clk_disable(nmk_chip->clk); + + __nmk_gpio_irq_handler(irq, desc, status); +} + +static void nmk_gpio_secondary_irq_handler(unsigned int irq, + struct irq_desc *desc) +{ + struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq); + u32 status = nmk_chip->get_secondary_status(nmk_chip->bank); + + __nmk_gpio_irq_handler(irq, desc, status); +} + +static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip) +{ + irq_set_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler); + irq_set_handler_data(nmk_chip->parent_irq, nmk_chip); + + if (nmk_chip->secondary_parent_irq >= 0) { + irq_set_chained_handler(nmk_chip->secondary_parent_irq, + nmk_gpio_secondary_irq_handler); + irq_set_handler_data(nmk_chip->secondary_parent_irq, nmk_chip); + } + + return 0; +} + +/* I/O Functions */ + +static int nmk_gpio_request(struct gpio_chip *chip, unsigned offset) +{ + /* + * Map back to global GPIO space and request muxing, the direction + * parameter does not matter for this controller. + */ + int gpio = chip->base + offset; + + return pinctrl_request_gpio(gpio); +} + +static void nmk_gpio_free(struct gpio_chip *chip, unsigned offset) +{ + int gpio = chip->base + offset; + + pinctrl_free_gpio(gpio); +} + +static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset) +{ + struct nmk_gpio_chip *nmk_chip = + container_of(chip, struct nmk_gpio_chip, chip); + + clk_enable(nmk_chip->clk); + + writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC); + + clk_disable(nmk_chip->clk); + + return 0; +} + +static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset) +{ + struct nmk_gpio_chip *nmk_chip = + container_of(chip, struct nmk_gpio_chip, chip); + u32 bit = 1 << offset; + int value; + + clk_enable(nmk_chip->clk); + + value = (readl(nmk_chip->addr + NMK_GPIO_DAT) & bit) != 0; + + clk_disable(nmk_chip->clk); + + return value; +} + +static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset, + int val) +{ + struct nmk_gpio_chip *nmk_chip = + container_of(chip, struct nmk_gpio_chip, chip); + + clk_enable(nmk_chip->clk); + + __nmk_gpio_set_output(nmk_chip, offset, val); + + clk_disable(nmk_chip->clk); +} + +static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset, + int val) +{ + struct nmk_gpio_chip *nmk_chip = + container_of(chip, struct nmk_gpio_chip, chip); + + clk_enable(nmk_chip->clk); + + __nmk_gpio_make_output(nmk_chip, offset, val); + + clk_disable(nmk_chip->clk); + + return 0; +} + +static int nmk_gpio_to_irq(struct gpio_chip *chip, unsigned offset) +{ + struct nmk_gpio_chip *nmk_chip = + container_of(chip, struct nmk_gpio_chip, chip); + + return irq_find_mapping(nmk_chip->domain, offset); +} + +#ifdef CONFIG_DEBUG_FS + +#include <linux/seq_file.h> + +static void nmk_gpio_dbg_show_one(struct seq_file *s, struct gpio_chip *chip, + unsigned offset, unsigned gpio) +{ + const char *label = gpiochip_is_requested(chip, offset); + struct nmk_gpio_chip *nmk_chip = + container_of(chip, struct nmk_gpio_chip, chip); + int mode; + bool is_out; + bool pull; + u32 bit = 1 << offset; + const char *modes[] = { + [NMK_GPIO_ALT_GPIO] = "gpio", + [NMK_GPIO_ALT_A] = "altA", + [NMK_GPIO_ALT_B] = "altB", + [NMK_GPIO_ALT_C] = "altC", + }; + + clk_enable(nmk_chip->clk); + is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & bit); + pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit); + mode = nmk_gpio_get_mode(gpio); + + seq_printf(s, " gpio-%-3d (%-20.20s) %s %s %s %s", + gpio, label ?: "(none)", + is_out ? "out" : "in ", + chip->get + ? (chip->get(chip, offset) ? "hi" : "lo") + : "? ", + (mode < 0) ? "unknown" : modes[mode], + pull ? "pull" : "none"); + + if (label && !is_out) { + int irq = gpio_to_irq(gpio); + struct irq_desc *desc = irq_to_desc(irq); + + /* This races with request_irq(), set_irq_type(), + * and set_irq_wake() ... but those are "rare". + */ + if (irq >= 0 && desc->action) { + char *trigger; + u32 bitmask = nmk_gpio_get_bitmask(gpio); + + if (nmk_chip->edge_rising & bitmask) + trigger = "edge-rising"; + else if (nmk_chip->edge_falling & bitmask) + trigger = "edge-falling"; + else + trigger = "edge-undefined"; + + seq_printf(s, " irq-%d %s%s", + irq, trigger, + irqd_is_wakeup_set(&desc->irq_data) + ? " wakeup" : ""); + } + } + clk_disable(nmk_chip->clk); +} + +static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) +{ + unsigned i; + unsigned gpio = chip->base; + + for (i = 0; i < chip->ngpio; i++, gpio++) { + nmk_gpio_dbg_show_one(s, chip, i, gpio); + seq_printf(s, "\n"); + } +} + +#else +static inline void nmk_gpio_dbg_show_one(struct seq_file *s, + struct gpio_chip *chip, + unsigned offset, unsigned gpio) +{ +} +#define nmk_gpio_dbg_show NULL +#endif + +/* This structure is replicated for each GPIO block allocated at probe time */ +static struct gpio_chip nmk_gpio_template = { + .request = nmk_gpio_request, + .free = nmk_gpio_free, + .direction_input = nmk_gpio_make_input, + .get = nmk_gpio_get_input, + .direction_output = nmk_gpio_make_output, + .set = nmk_gpio_set_output, + .to_irq = nmk_gpio_to_irq, + .dbg_show = nmk_gpio_dbg_show, + .can_sleep = 0, +}; + +void nmk_gpio_clocks_enable(void) +{ + int i; + + for (i = 0; i < NUM_BANKS; i++) { + struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; + + if (!chip) + continue; + + clk_enable(chip->clk); + } +} + +void nmk_gpio_clocks_disable(void) +{ + int i; + + for (i = 0; i < NUM_BANKS; i++) { + struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; + + if (!chip) + continue; + + clk_disable(chip->clk); + } +} + +/* + * Called from the suspend/resume path to only keep the real wakeup interrupts + * (those that have had set_irq_wake() called on them) as wakeup interrupts, + * and not the rest of the interrupts which we needed to have as wakeups for + * cpuidle. + * + * PM ops are not used since this needs to be done at the end, after all the + * other drivers are done with their suspend callbacks. + */ +void nmk_gpio_wakeups_suspend(void) +{ + int i; + + for (i = 0; i < NUM_BANKS; i++) { + struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; + + if (!chip) + break; + + clk_enable(chip->clk); + + writel(chip->rwimsc & chip->real_wake, + chip->addr + NMK_GPIO_RWIMSC); + writel(chip->fwimsc & chip->real_wake, + chip->addr + NMK_GPIO_FWIMSC); + + clk_disable(chip->clk); + } +} + +void nmk_gpio_wakeups_resume(void) +{ + int i; + + for (i = 0; i < NUM_BANKS; i++) { + struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; + + if (!chip) + break; + + clk_enable(chip->clk); + + writel(chip->rwimsc, chip->addr + NMK_GPIO_RWIMSC); + writel(chip->fwimsc, chip->addr + NMK_GPIO_FWIMSC); + + clk_disable(chip->clk); + } +} + +/* + * Read the pull up/pull down status. + * A bit set in 'pull_up' means that pull up + * is selected if pull is enabled in PDIS register. + * Note: only pull up/down set via this driver can + * be detected due to HW limitations. + */ +void nmk_gpio_read_pull(int gpio_bank, u32 *pull_up) +{ + if (gpio_bank < NUM_BANKS) { + struct nmk_gpio_chip *chip = nmk_gpio_chips[gpio_bank]; + + if (!chip) + return; + + *pull_up = chip->pull_up; + } +} + +int nmk_gpio_irq_map(struct irq_domain *d, unsigned int irq, + irq_hw_number_t hwirq) +{ + struct nmk_gpio_chip *nmk_chip = d->host_data; + + if (!nmk_chip) + return -EINVAL; + + irq_set_chip_and_handler(irq, &nmk_gpio_irq_chip, handle_edge_irq); + set_irq_flags(irq, IRQF_VALID); + irq_set_chip_data(irq, nmk_chip); + irq_set_irq_type(irq, IRQ_TYPE_EDGE_FALLING); + + return 0; +} + +const struct irq_domain_ops nmk_gpio_irq_simple_ops = { + .map = nmk_gpio_irq_map, + .xlate = irq_domain_xlate_twocell, +}; + +static int __devinit nmk_gpio_probe(struct platform_device *dev) +{ + struct nmk_gpio_platform_data *pdata = dev->dev.platform_data; + struct device_node *np = dev->dev.of_node; + struct nmk_gpio_chip *nmk_chip; + struct gpio_chip *chip; + struct resource *res; + struct clk *clk; + int secondary_irq; + void __iomem *base; + int irq; + int ret; + + if (!pdata && !np) { + dev_err(&dev->dev, "No platform data or device tree found\n"); + return -ENODEV; + } + + if (np) { + pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); + if (!pdata) + return -ENOMEM; + + if (of_get_property(np, "supports-sleepmode", NULL)) + pdata->supports_sleepmode = true; + + if (of_property_read_u32(np, "gpio-bank", &dev->id)) { + dev_err(&dev->dev, "gpio-bank property not found\n"); + ret = -EINVAL; + goto out; + } + + pdata->first_gpio = dev->id * NMK_GPIO_PER_CHIP; + pdata->num_gpio = NMK_GPIO_PER_CHIP; + } + + res = platform_get_resource(dev, IORESOURCE_MEM, 0); + if (!res) { + ret = -ENOENT; + goto out; + } + + irq = platform_get_irq(dev, 0); + if (irq < 0) { + ret = irq; + goto out; + } + + secondary_irq = platform_get_irq(dev, 1); + if (secondary_irq >= 0 && !pdata->get_secondary_status) { + ret = -EINVAL; + goto out; + } + + if (request_mem_region(res->start, resource_size(res), + dev_name(&dev->dev)) == NULL) { + ret = -EBUSY; + goto out; + } + + base = ioremap(res->start, resource_size(res)); + if (!base) { + ret = -ENOMEM; + goto out_release; + } + + clk = clk_get(&dev->dev, NULL); + if (IS_ERR(clk)) { + ret = PTR_ERR(clk); + goto out_unmap; + } + + nmk_chip = kzalloc(sizeof(*nmk_chip), GFP_KERNEL); + if (!nmk_chip) { + ret = -ENOMEM; + goto out_clk; + } + + /* + * The virt address in nmk_chip->addr is in the nomadik register space, + * so we can simply convert the resource address, without remapping + */ + nmk_chip->bank = dev->id; + nmk_chip->clk = clk; + nmk_chip->addr = base; + nmk_chip->chip = nmk_gpio_template; + nmk_chip->parent_irq = irq; + nmk_chip->secondary_parent_irq = secondary_irq; + nmk_chip->get_secondary_status = pdata->get_secondary_status; + nmk_chip->set_ioforce = pdata->set_ioforce; + nmk_chip->sleepmode = pdata->supports_sleepmode; + spin_lock_init(&nmk_chip->lock); + + chip = &nmk_chip->chip; + chip->base = pdata->first_gpio; + chip->ngpio = pdata->num_gpio; + chip->label = pdata->name ?: dev_name(&dev->dev); + chip->dev = &dev->dev; + chip->owner = THIS_MODULE; + + clk_enable(nmk_chip->clk); + nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI); + clk_disable(nmk_chip->clk); + +#ifdef CONFIG_OF_GPIO + chip->of_node = np; +#endif + + ret = gpiochip_add(&nmk_chip->chip); + if (ret) + goto out_free; + + BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips)); + + nmk_gpio_chips[nmk_chip->bank] = nmk_chip; + + platform_set_drvdata(dev, nmk_chip); + + nmk_chip->domain = irq_domain_add_legacy(np, NMK_GPIO_PER_CHIP, + NOMADIK_GPIO_TO_IRQ(pdata->first_gpio), + 0, &nmk_gpio_irq_simple_ops, nmk_chip); + if (!nmk_chip->domain) { + pr_err("%s: Failed to create irqdomain\n", np->full_name); + ret = -ENOSYS; + goto out_free; + } + + nmk_gpio_init_irq(nmk_chip); + + dev_info(&dev->dev, "at address %p\n", nmk_chip->addr); + + return 0; + +out_free: + kfree(nmk_chip); +out_clk: + clk_disable(clk); + clk_put(clk); +out_unmap: + iounmap(base); +out_release: + release_mem_region(res->start, resource_size(res)); +out: + dev_err(&dev->dev, "Failure %i for GPIO %i-%i\n", ret, + pdata->first_gpio, pdata->first_gpio+31); + if (np) + kfree(pdata); + + return ret; +} + +static int nmk_get_groups_cnt(struct pinctrl_dev *pctldev) +{ + struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); + + return npct->soc->ngroups; +} + +static const char *nmk_get_group_name(struct pinctrl_dev *pctldev, + unsigned selector) +{ + struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); + + return npct->soc->groups[selector].name; +} + +static int nmk_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, + const unsigned **pins, + unsigned *num_pins) +{ + struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); + + *pins = npct->soc->groups[selector].pins; + *num_pins = npct->soc->groups[selector].npins; + return 0; +} + +static struct pinctrl_gpio_range * +nmk_match_gpio_range(struct pinctrl_dev *pctldev, unsigned offset) +{ + struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); + int i; + + for (i = 0; i < npct->soc->gpio_num_ranges; i++) { + struct pinctrl_gpio_range *range; + + range = &npct->soc->gpio_ranges[i]; + if (offset >= range->pin_base && + offset <= (range->pin_base + range->npins - 1)) + return range; + } + return NULL; +} + +static void nmk_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, + unsigned offset) +{ + struct pinctrl_gpio_range *range; + struct gpio_chip *chip; + + range = nmk_match_gpio_range(pctldev, offset); + if (!range || !range->gc) { + seq_printf(s, "invalid pin offset"); + return; + } + chip = range->gc; + nmk_gpio_dbg_show_one(s, chip, offset - chip->base, offset); +} + +static struct pinctrl_ops nmk_pinctrl_ops = { + .get_groups_count = nmk_get_groups_cnt, + .get_group_name = nmk_get_group_name, + .get_group_pins = nmk_get_group_pins, + .pin_dbg_show = nmk_pin_dbg_show, +}; + +static int nmk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) +{ + struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); + + return npct->soc->nfunctions; +} + +static const char *nmk_pmx_get_func_name(struct pinctrl_dev *pctldev, + unsigned function) +{ + struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); + + return npct->soc->functions[function].name; +} + +static int nmk_pmx_get_func_groups(struct pinctrl_dev *pctldev, + unsigned function, + const char * const **groups, + unsigned * const num_groups) +{ + struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); + + *groups = npct->soc->functions[function].groups; + *num_groups = npct->soc->functions[function].ngroups; + + return 0; +} + +static int nmk_pmx_enable(struct pinctrl_dev *pctldev, unsigned function, + unsigned group) +{ + struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); + const struct nmk_pingroup *g; + static unsigned int slpm[NUM_BANKS]; + unsigned long flags; + bool glitch; + int ret = -EINVAL; + int i; + + g = &npct->soc->groups[group]; + + if (g->altsetting < 0) + return -EINVAL; + + dev_dbg(npct->dev, "enable group %s, %u pins\n", g->name, g->npins); + + /* Handle this special glitch on altfunction C */ + glitch = (g->altsetting == NMK_GPIO_ALT_C); + + if (glitch) { + spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); + + /* Initially don't put any pins to sleep when switching */ + memset(slpm, 0xff, sizeof(slpm)); + + /* + * Then mask the pins that need to be sleeping now when we're + * switching to the ALT C function. + */ + for (i = 0; i < g->npins; i++) + slpm[g->pins[i] / NMK_GPIO_PER_CHIP] &= ~BIT(g->pins[i]); + nmk_gpio_glitch_slpm_init(slpm); + } + + for (i = 0; i < g->npins; i++) { + struct pinctrl_gpio_range *range; + struct nmk_gpio_chip *nmk_chip; + struct gpio_chip *chip; + unsigned bit; + + range = nmk_match_gpio_range(pctldev, g->pins[i]); + if (!range) { + dev_err(npct->dev, + "invalid pin offset %d in group %s at index %d\n", + g->pins[i], g->name, i); + goto out_glitch; + } + if (!range->gc) { + dev_err(npct->dev, "GPIO chip missing in range for pin offset %d in group %s at index %d\n", + g->pins[i], g->name, i); + goto out_glitch; + } + chip = range->gc; + nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); + dev_dbg(npct->dev, "setting pin %d to altsetting %d\n", g->pins[i], g->altsetting); + + clk_enable(nmk_chip->clk); + bit = g->pins[i] % NMK_GPIO_PER_CHIP; + /* + * If the pin is switching to altfunc, and there was an + * interrupt installed on it which has been lazy disabled, + * actually mask the interrupt to prevent spurious interrupts + * that would occur while the pin is under control of the + * peripheral. Only SKE does this. + */ + nmk_gpio_disable_lazy_irq(nmk_chip, bit); + + __nmk_gpio_set_mode_safe(nmk_chip, bit, g->altsetting, glitch); + clk_disable(nmk_chip->clk); + } + + /* When all pins are successfully reconfigured we get here */ + ret = 0; + +out_glitch: + if (glitch) { + nmk_gpio_glitch_slpm_restore(slpm); + spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); + } + + return ret; +} + +static void nmk_pmx_disable(struct pinctrl_dev *pctldev, + unsigned function, unsigned group) +{ + struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); + const struct nmk_pingroup *g; + + g = &npct->soc->groups[group]; + + if (g->altsetting < 0) + return; + + /* Poke out the mux, set the pin to some default state? */ + dev_dbg(npct->dev, "disable group %s, %u pins\n", g->name, g->npins); +} + +int nmk_gpio_request_enable(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned offset) +{ + struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); + struct nmk_gpio_chip *nmk_chip; + struct gpio_chip *chip; + unsigned bit; + + if (!range) { + dev_err(npct->dev, "invalid range\n"); + return -EINVAL; + } + if (!range->gc) { + dev_err(npct->dev, "missing GPIO chip in range\n"); + return -EINVAL; + } + chip = range->gc; + nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); + + dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset); + + clk_enable(nmk_chip->clk); + bit = offset % NMK_GPIO_PER_CHIP; + /* There is no glitch when converting any pin to GPIO */ + __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO); + clk_disable(nmk_chip->clk); + + return 0; +} + +void nmk_gpio_disable_free(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned offset) +{ + struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); + + dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset); + /* Set the pin to some default state, GPIO is usually default */ +} + +static struct pinmux_ops nmk_pinmux_ops = { + .get_functions_count = nmk_pmx_get_funcs_cnt, + .get_function_name = nmk_pmx_get_func_name, + .get_function_groups = nmk_pmx_get_func_groups, + .enable = nmk_pmx_enable, + .disable = nmk_pmx_disable, + .gpio_request_enable = nmk_gpio_request_enable, + .gpio_disable_free = nmk_gpio_disable_free, +}; + +int nmk_pin_config_get(struct pinctrl_dev *pctldev, + unsigned pin, + unsigned long *config) +{ + /* Not implemented */ + return -EINVAL; +} + +int nmk_pin_config_set(struct pinctrl_dev *pctldev, + unsigned pin, + unsigned long config) +{ + static const char *pullnames[] = { + [NMK_GPIO_PULL_NONE] = "none", + [NMK_GPIO_PULL_UP] = "up", + [NMK_GPIO_PULL_DOWN] = "down", + [3] /* illegal */ = "??" + }; + static const char *slpmnames[] = { + [NMK_GPIO_SLPM_INPUT] = "input/wakeup", + [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup", + }; + struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); + struct nmk_gpio_chip *nmk_chip; + struct pinctrl_gpio_range *range; + struct gpio_chip *chip; + unsigned bit; + + /* + * The pin config contains pin number and altfunction fields, here + * we just ignore that part. It's being handled by the framework and + * pinmux callback respectively. + */ + pin_cfg_t cfg = (pin_cfg_t) config; + int pull = PIN_PULL(cfg); + int slpm = PIN_SLPM(cfg); + int output = PIN_DIR(cfg); + int val = PIN_VAL(cfg); + bool lowemi = PIN_LOWEMI(cfg); + bool gpiomode = PIN_GPIOMODE(cfg); + bool sleep = PIN_SLEEPMODE(cfg); + + range = nmk_match_gpio_range(pctldev, pin); + if (!range) { + dev_err(npct->dev, "invalid pin offset %d\n", pin); + return -EINVAL; + } + if (!range->gc) { + dev_err(npct->dev, "GPIO chip missing in range for pin %d\n", + pin); + return -EINVAL; + } + chip = range->gc; + nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); + + if (sleep) { + int slpm_pull = PIN_SLPM_PULL(cfg); + int slpm_output = PIN_SLPM_DIR(cfg); + int slpm_val = PIN_SLPM_VAL(cfg); + + /* All pins go into GPIO mode at sleep */ + gpiomode = true; + + /* + * The SLPM_* values are normal values + 1 to allow zero to + * mean "same as normal". + */ + if (slpm_pull) + pull = slpm_pull - 1; + if (slpm_output) + output = slpm_output - 1; + if (slpm_val) + val = slpm_val - 1; + + dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n", + pin, + slpm_pull ? pullnames[pull] : "same", + slpm_output ? (output ? "output" : "input") : "same", + slpm_val ? (val ? "high" : "low") : "same"); + } + + dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: pull %s, slpm %s (%s%s), lowemi %s\n", + pin, cfg, pullnames[pull], slpmnames[slpm], + output ? "output " : "input", + output ? (val ? "high" : "low") : "", + lowemi ? "on" : "off" ); + + clk_enable(nmk_chip->clk); + bit = pin % NMK_GPIO_PER_CHIP; + if (gpiomode) + /* No glitch when going to GPIO mode */ + __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO); + if (output) + __nmk_gpio_make_output(nmk_chip, bit, val); + else { + __nmk_gpio_make_input(nmk_chip, bit); + __nmk_gpio_set_pull(nmk_chip, bit, pull); + } + /* TODO: isn't this only applicable on output pins? */ + __nmk_gpio_set_lowemi(nmk_chip, bit, lowemi); + + __nmk_gpio_set_slpm(nmk_chip, bit, slpm); + clk_disable(nmk_chip->clk); + return 0; +} + +static struct pinconf_ops nmk_pinconf_ops = { + .pin_config_get = nmk_pin_config_get, + .pin_config_set = nmk_pin_config_set, +}; + +static struct pinctrl_desc nmk_pinctrl_desc = { + .name = "pinctrl-nomadik", + .pctlops = &nmk_pinctrl_ops, + .pmxops = &nmk_pinmux_ops, + .confops = &nmk_pinconf_ops, + .owner = THIS_MODULE, +}; + +static int __devinit nmk_pinctrl_probe(struct platform_device *pdev) +{ + const struct platform_device_id *platid = platform_get_device_id(pdev); + struct nmk_pinctrl *npct; + int i; + + npct = devm_kzalloc(&pdev->dev, sizeof(*npct), GFP_KERNEL); + if (!npct) + return -ENOMEM; + + /* Poke in other ASIC variants here */ + if (platid->driver_data == PINCTRL_NMK_DB8500) + nmk_pinctrl_db8500_init(&npct->soc); + + /* + * We need all the GPIO drivers to probe FIRST, or we will not be able + * to obtain references to the struct gpio_chip * for them, and we + * need this to proceed. + */ + for (i = 0; i < npct->soc->gpio_num_ranges; i++) { + if (!nmk_gpio_chips[i]) { + dev_warn(&pdev->dev, "GPIO chip %d not registered yet\n", i); + devm_kfree(&pdev->dev, npct); + return -EPROBE_DEFER; + } + npct->soc->gpio_ranges[i].gc = &nmk_gpio_chips[i]->chip; + } + + nmk_pinctrl_desc.pins = npct->soc->pins; + nmk_pinctrl_desc.npins = npct->soc->npins; + npct->dev = &pdev->dev; + npct->pctl = pinctrl_register(&nmk_pinctrl_desc, &pdev->dev, npct); + if (!npct->pctl) { + dev_err(&pdev->dev, "could not register Nomadik pinctrl driver\n"); + return -EINVAL; + } + + /* We will handle a range of GPIO pins */ + for (i = 0; i < npct->soc->gpio_num_ranges; i++) + pinctrl_add_gpio_range(npct->pctl, &npct->soc->gpio_ranges[i]); + + platform_set_drvdata(pdev, npct); + dev_info(&pdev->dev, "initialized Nomadik pin control driver\n"); + + return 0; +} + +static const struct of_device_id nmk_gpio_match[] = { + { .compatible = "st,nomadik-gpio", }, + {} +}; + +static struct platform_driver nmk_gpio_driver = { + .driver = { + .owner = THIS_MODULE, + .name = "gpio", + .of_match_table = nmk_gpio_match, + }, + .probe = nmk_gpio_probe, +}; + +static const struct platform_device_id nmk_pinctrl_id[] = { + { "pinctrl-stn8815", PINCTRL_NMK_STN8815 }, + { "pinctrl-db8500", PINCTRL_NMK_DB8500 }, +}; + +static struct platform_driver nmk_pinctrl_driver = { + .driver = { + .owner = THIS_MODULE, + .name = "pinctrl-nomadik", + }, + .probe = nmk_pinctrl_probe, + .id_table = nmk_pinctrl_id, +}; + +static int __init nmk_gpio_init(void) +{ + int ret; + + ret = platform_driver_register(&nmk_gpio_driver); + if (ret) + return ret; + return platform_driver_register(&nmk_pinctrl_driver); +} + +core_initcall(nmk_gpio_init); + +MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini"); +MODULE_DESCRIPTION("Nomadik GPIO Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/pinctrl-nomadik.h b/drivers/pinctrl/pinctrl-nomadik.h new file mode 100644 index 000000000000..bc91aed7185d --- /dev/null +++ b/drivers/pinctrl/pinctrl-nomadik.h @@ -0,0 +1,77 @@ +#ifndef PINCTRL_PINCTRL_NOMADIK_H +#define PINCTRL_PINCTRL_NOMADIK_H + +#include <plat/gpio-nomadik.h> + +/* Package definitions */ +#define PINCTRL_NMK_STN8815 0 +#define PINCTRL_NMK_DB8500 1 + +/** + * struct nmk_function - Nomadik pinctrl mux function + * @name: The name of the function, exported to pinctrl core. + * @groups: An array of pin groups that may select this function. + * @ngroups: The number of entries in @groups. + */ +struct nmk_function { + const char *name; + const char * const *groups; + unsigned ngroups; +}; + +/** + * struct nmk_pingroup - describes a Nomadik pin group + * @name: the name of this specific pin group + * @pins: an array of discrete physical pins used in this group, taken + * from the driver-local pin enumeration space + * @num_pins: the number of pins in this group array, i.e. the number of + * elements in .pins so we can iterate over that array + * @altsetting: the altsetting to apply to all pins in this group to + * configure them to be used by a function + */ +struct nmk_pingroup { + const char *name; + const unsigned int *pins; + const unsigned npins; + int altsetting; +}; + +/** + * struct nmk_pinctrl_soc_data - Nomadik pin controller per-SoC configuration + * @gpio_ranges: An array of GPIO ranges for this SoC + * @gpio_num_ranges: The number of GPIO ranges for this SoC + * @pins: An array describing all pins the pin controller affects. + * All pins which are also GPIOs must be listed first within the + * array, and be numbered identically to the GPIO controller's + * numbering. + * @npins: The number of entries in @pins. + * @functions: The functions supported on this SoC. + * @nfunction: The number of entries in @functions. + * @groups: An array describing all pin groups the pin SoC supports. + * @ngroups: The number of entries in @groups. + */ +struct nmk_pinctrl_soc_data { + struct pinctrl_gpio_range *gpio_ranges; + unsigned gpio_num_ranges; + const struct pinctrl_pin_desc *pins; + unsigned npins; + const struct nmk_function *functions; + unsigned nfunctions; + const struct nmk_pingroup *groups; + unsigned ngroups; +}; + +#ifdef CONFIG_PINCTRL_DB8500 + +void nmk_pinctrl_db8500_init(const struct nmk_pinctrl_soc_data **soc); + +#else + +static inline void +nmk_pinctrl_db8500_init(const struct nmk_pinctrl_soc_data **soc) +{ +} + +#endif + +#endif /* PINCTRL_PINCTRL_NOMADIK_H */ |