diff options
Diffstat (limited to 'drivers/media')
17 files changed, 2787 insertions, 3715 deletions
diff --git a/drivers/media/platform/chips-media/wave5/Kconfig b/drivers/media/platform/chips-media/wave5/Kconfig index a3b949356cd5..77e7ae5c8f35 100644 --- a/drivers/media/platform/chips-media/wave5/Kconfig +++ b/drivers/media/platform/chips-media/wave5/Kconfig @@ -1,7 +1,8 @@ # SPDX-License-Identifier: GPL-2.0 config VIDEO_WAVE_VPU tristate "Chips&Media Wave Codec Driver" - depends on VIDEO_DEV + depends on V4L_MEM2MEM_DRIVERS + depends on VIDEO_DEV && OF select VIDEOBUF2_DMA_CONTIG select VIDEOBUF2_VMALLOC select V4L2_MEM2MEM_DEV diff --git a/drivers/media/platform/chips-media/wave5/wave5-helper.c b/drivers/media/platform/chips-media/wave5/wave5-helper.c index 09dfb20e9a20..ec710b838dfe 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-helper.c +++ b/drivers/media/platform/chips-media/wave5/wave5-helper.c @@ -2,29 +2,45 @@ /* * Wave5 series multi-standard codec IP - decoder interface * - * Copyright (C) 2021 CHIPS&MEDIA INC + * Copyright (C) 2021-2023 CHIPS&MEDIA INC */ #include "wave5-helper.h" +const char *state_to_str(enum vpu_instance_state state) +{ + switch (state) { + case VPU_INST_STATE_NONE: + return "NONE"; + case VPU_INST_STATE_OPEN: + return "OPEN"; + case VPU_INST_STATE_INIT_SEQ: + return "INIT_SEQ"; + case VPU_INST_STATE_PIC_RUN: + return "PIC_RUN"; + case VPU_INST_STATE_STOP: + return "STOP"; + default: + return "UNKNOWN"; + } +} + void wave5_cleanup_instance(struct vpu_instance *inst) { int i; - for (i = 0; i < inst->dst_buf_count; i++) - wave5_vdi_free_dma_memory(inst->dev, &inst->frame_vbuf[i]); + for (i = 0; i < inst->fbc_buf_count; i++) + wave5_vpu_dec_reset_framebuffer(inst, i); wave5_vdi_free_dma_memory(inst->dev, &inst->bitstream_vbuf); v4l2_ctrl_handler_free(&inst->v4l2_ctrl_hdl); - if (inst->v4l2_m2m_dev != NULL) - v4l2_m2m_release(inst->v4l2_m2m_dev); - if (inst->v4l2_fh.vdev != NULL) { + if (inst->v4l2_fh.vdev) { v4l2_fh_del(&inst->v4l2_fh); v4l2_fh_exit(&inst->v4l2_fh); } list_del_init(&inst->list); - kfifo_free(&inst->irq_status); ida_free(&inst->dev->inst_ida, inst->id); + kfree(inst->codec_info); kfree(inst); } @@ -37,23 +53,12 @@ int wave5_vpu_release_device(struct file *filp, v4l2_m2m_ctx_release(inst->v4l2_fh.m2m_ctx); if (inst->state != VPU_INST_STATE_NONE) { u32 fail_res; - int retry_count = 10; int ret; - do { - fail_res = 0; - ret = close_func(inst, &fail_res); - if (ret && ret != -EIO) - break; - if (fail_res != WAVE5_SYSERR_VPU_STILL_RUNNING) - break; - if (!wave5_vpu_wait_interrupt(inst, VPU_DEC_TIMEOUT/10)) - break; - } while (--retry_count); - + ret = close_func(inst, &fail_res); if (fail_res == WAVE5_SYSERR_VPU_STILL_RUNNING) { dev_err(inst->dev->dev, "%s close failed, device is still running\n", - name); + name); return -EBUSY; } if (ret && ret != -EIO) { @@ -78,7 +83,7 @@ int wave5_vpu_queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue src_vq->mem_ops = &vb2_dma_contig_memops; src_vq->ops = ops; src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; - src_vq->buf_struct_size = sizeof(struct vpu_buffer); + src_vq->buf_struct_size = sizeof(struct vpu_src_buffer); src_vq->drv_priv = inst; src_vq->lock = &inst->dev->dev_lock; src_vq->dev = inst->dev->v4l2_dev.dev; @@ -91,7 +96,7 @@ int wave5_vpu_queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue dst_vq->mem_ops = &vb2_dma_contig_memops; dst_vq->ops = ops; dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; - dst_vq->buf_struct_size = sizeof(struct vpu_buffer); + dst_vq->buf_struct_size = sizeof(struct vpu_src_buffer); dst_vq->drv_priv = inst; dst_vq->lock = &inst->dev->dev_lock; dst_vq->dev = inst->dev->v4l2_dev.dev; @@ -129,13 +134,8 @@ int wave5_vpu_g_fmt_out(struct file *file, void *fh, struct v4l2_format *f) struct vpu_instance *inst = wave5_to_vpu_inst(fh); int i; - if (inst->state >= VPU_INST_STATE_INIT_SEQ){ - f->fmt.pix_mp.width = inst->src_fmt.width - inst->crop_rect.right; - f->fmt.pix_mp.height = inst->src_fmt.height - inst->crop_rect.bottom; - } else { - f->fmt.pix_mp.width = inst->src_fmt.width; - f->fmt.pix_mp.height = inst->src_fmt.height; - } + f->fmt.pix_mp.width = inst->src_fmt.width; + f->fmt.pix_mp.height = inst->src_fmt.height; f->fmt.pix_mp.pixelformat = inst->src_fmt.pixelformat; f->fmt.pix_mp.field = inst->src_fmt.field; f->fmt.pix_mp.flags = inst->src_fmt.flags; @@ -147,7 +147,6 @@ int wave5_vpu_g_fmt_out(struct file *file, void *fh, struct v4l2_format *f) f->fmt.pix_mp.colorspace = inst->colorspace; f->fmt.pix_mp.ycbcr_enc = inst->ycbcr_enc; - f->fmt.pix_mp.hsv_enc = inst->hsv_enc; f->fmt.pix_mp.quantization = inst->quantization; f->fmt.pix_mp.xfer_func = inst->xfer_func; @@ -178,3 +177,34 @@ const struct vpu_format *wave5_find_vpu_fmt_by_idx(unsigned int idx, return &fmt_list[idx]; } + +enum wave_std wave5_to_vpu_std(unsigned int v4l2_pix_fmt, enum vpu_instance_type type) +{ + switch (v4l2_pix_fmt) { + case V4L2_PIX_FMT_H264: + return type == VPU_INST_TYPE_DEC ? W_AVC_DEC : W_AVC_ENC; + case V4L2_PIX_FMT_HEVC: + return type == VPU_INST_TYPE_DEC ? W_HEVC_DEC : W_HEVC_ENC; + default: + return STD_UNKNOWN; + } +} + +void wave5_return_bufs(struct vb2_queue *q, u32 state) +{ + struct vpu_instance *inst = vb2_get_drv_priv(q); + struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx; + struct v4l2_ctrl_handler v4l2_ctrl_hdl = inst->v4l2_ctrl_hdl; + struct vb2_v4l2_buffer *vbuf; + + for (;;) { + if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) + vbuf = v4l2_m2m_src_buf_remove(m2m_ctx); + else + vbuf = v4l2_m2m_dst_buf_remove(m2m_ctx); + if (!vbuf) + return; + v4l2_ctrl_request_complete(vbuf->vb2_buf.req_obj.req, &v4l2_ctrl_hdl); + v4l2_m2m_buf_done(vbuf, state); + } +} diff --git a/drivers/media/platform/chips-media/wave5/wave5-helper.h b/drivers/media/platform/chips-media/wave5/wave5-helper.h index d586d624275e..b17c96670a3d 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-helper.h +++ b/drivers/media/platform/chips-media/wave5/wave5-helper.h @@ -2,7 +2,7 @@ /* * Wave5 series multi-standard codec IP - basic types * - * Copyright (C) 2021 CHIPS&MEDIA INC + * Copyright (C) 2021-2023 CHIPS&MEDIA INC */ #ifndef __WAVE_HELPER_H__ @@ -13,6 +13,7 @@ #define FMT_TYPES 2 #define MAX_FMTS 6 +const char *state_to_str(enum vpu_instance_state state); void wave5_cleanup_instance(struct vpu_instance *inst); int wave5_vpu_release_device(struct file *filp, int (*close_func)(struct vpu_instance *inst, u32 *fail_res), @@ -25,4 +26,6 @@ const struct vpu_format *wave5_find_vpu_fmt(unsigned int v4l2_pix_fmt, const struct vpu_format fmt_list[MAX_FMTS]); const struct vpu_format *wave5_find_vpu_fmt_by_idx(unsigned int idx, const struct vpu_format fmt_list[MAX_FMTS]); +enum wave_std wave5_to_vpu_std(unsigned int v4l2_pix_fmt, enum vpu_instance_type type); +void wave5_return_bufs(struct vb2_queue *q, u32 state); #endif diff --git a/drivers/media/platform/chips-media/wave5/wave5-hw.c b/drivers/media/platform/chips-media/wave5/wave5-hw.c index fdc5c7eeaee1..29e15888a21a 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-hw.c +++ b/drivers/media/platform/chips-media/wave5/wave5-hw.c @@ -2,10 +2,11 @@ /* * Wave5 series multi-standard codec IP - wave5 backend logic * - * Copyright (C) 2021 CHIPS&MEDIA INC + * Copyright (C) 2021-2023 CHIPS&MEDIA INC */ #include <linux/iopoll.h> +#include <linux/bitfield.h> #include "wave5-vpu.h" #include "wave5.h" #include "wave5-regdefine.h" @@ -16,40 +17,102 @@ #define VPU_BUSY_CHECK_TIMEOUT 10000000 #define QUEUE_REPORT_MASK 0xffff -static void wave5_print_reg_err(struct vpu_device *vpu_dev, u32 reg_fail_reason) +/* Encoder support fields */ +#define FEATURE_HEVC10BIT_ENC BIT(3) +#define FEATURE_AVC10BIT_ENC BIT(11) +#define FEATURE_AVC_ENCODER BIT(1) +#define FEATURE_HEVC_ENCODER BIT(0) + +/* Decoder support fields */ +#define FEATURE_AVC_DECODER BIT(3) +#define FEATURE_HEVC_DECODER BIT(2) + +#define FEATURE_BACKBONE BIT(16) +#define FEATURE_VCORE_BACKBONE BIT(22) +#define FEATURE_VCPU_BACKBONE BIT(28) + +#define REMAP_CTRL_MAX_SIZE_BITS ((W5_REMAP_MAX_SIZE >> 12) & 0x1ff) +#define REMAP_CTRL_REGISTER_VALUE(index) ( \ + (BIT(31) | (index << 12) | BIT(11) | REMAP_CTRL_MAX_SIZE_BITS) \ +) + +#define FASTIO_ADDRESS_MASK GENMASK(15, 0) +#define SEQ_PARAM_PROFILE_MASK GENMASK(30, 24) + +static void _wave5_print_reg_err(struct vpu_device *vpu_dev, u32 reg_fail_reason, + const char *func); +#define PRINT_REG_ERR(dev, reason) _wave5_print_reg_err((dev), (reason), __func__) + +static inline const char *cmd_to_str(int cmd, bool is_dec) +{ + switch (cmd) { + case W5_INIT_VPU: + return "W5_INIT_VPU"; + case W5_WAKEUP_VPU: + return "W5_WAKEUP_VPU"; + case W5_SLEEP_VPU: + return "W5_SLEEP_VPU"; + case W5_CREATE_INSTANCE: + return "W5_CREATE_INSTANCE"; + case W5_FLUSH_INSTANCE: + return "W5_FLUSH_INSTANCE"; + case W5_DESTROY_INSTANCE: + return "W5_DESTROY_INSTANCE"; + case W5_INIT_SEQ: + return "W5_INIT_SEQ"; + case W5_SET_FB: + return "W5_SET_FB"; + case W5_DEC_ENC_PIC: + if (is_dec) + return "W5_DEC_PIC"; + return "W5_ENC_PIC"; + case W5_ENC_SET_PARAM: + return "W5_ENC_SET_PARAM"; + case W5_QUERY: + return "W5_QUERY"; + case W5_UPDATE_BS: + return "W5_UPDATE_BS"; + case W5_MAX_VPU_COMD: + return "W5_MAX_VPU_COMD"; + default: + return "UNKNOWN"; + } +} + +static void _wave5_print_reg_err(struct vpu_device *vpu_dev, u32 reg_fail_reason, + const char *func) { - char *caller = __builtin_return_address(0); struct device *dev = vpu_dev->dev; u32 reg_val; switch (reg_fail_reason) { case WAVE5_SYSERR_QUEUEING_FAIL: reg_val = vpu_read_reg(vpu_dev, W5_RET_QUEUE_FAIL_REASON); - dev_dbg(dev, "%s: queueing failure: 0x%x\n", caller, reg_val); + dev_dbg(dev, "%s: queueing failure: 0x%x\n", func, reg_val); break; case WAVE5_SYSERR_RESULT_NOT_READY: - dev_err(dev, "%s: result not ready: 0x%x\n", caller, reg_fail_reason); + dev_err(dev, "%s: result not ready: 0x%x\n", func, reg_fail_reason); break; case WAVE5_SYSERR_ACCESS_VIOLATION_HW: - dev_err(dev, "%s: access violation: 0x%x\n", caller, reg_fail_reason); + dev_err(dev, "%s: access violation: 0x%x\n", func, reg_fail_reason); break; case WAVE5_SYSERR_WATCHDOG_TIMEOUT: - dev_err(dev, "%s: watchdog timeout: 0x%x\n", caller, reg_fail_reason); + dev_err(dev, "%s: watchdog timeout: 0x%x\n", func, reg_fail_reason); break; case WAVE5_SYSERR_BUS_ERROR: - dev_err(dev, "%s: bus error: 0x%x\n", caller, reg_fail_reason); + dev_err(dev, "%s: bus error: 0x%x\n", func, reg_fail_reason); break; case WAVE5_SYSERR_DOUBLE_FAULT: - dev_err(dev, "%s: double fault: 0x%x\n", caller, reg_fail_reason); + dev_err(dev, "%s: double fault: 0x%x\n", func, reg_fail_reason); break; case WAVE5_SYSERR_VPU_STILL_RUNNING: - dev_err(dev, "%s: still running: 0x%x\n", caller, reg_fail_reason); + dev_err(dev, "%s: still running: 0x%x\n", func, reg_fail_reason); break; case WAVE5_SYSERR_VLC_BUF_FULL: - dev_err(dev, "%s: vlc buf full: 0x%x\n", caller, reg_fail_reason); + dev_err(dev, "%s: vlc buf full: 0x%x\n", func, reg_fail_reason); break; default: - dev_err(dev, "%s: failure:: 0x%x\n", caller, reg_fail_reason); + dev_err(dev, "%s: failure:: 0x%x\n", func, reg_fail_reason); break; } } @@ -61,12 +124,14 @@ static int wave5_wait_fio_readl(struct vpu_device *vpu_dev, u32 addr, u32 val) ctrl = addr & 0xffff; wave5_vdi_write_register(vpu_dev, W5_VPU_FIO_CTRL_ADDR, ctrl); - ret = read_poll_timeout(wave5_vdi_readl, ctrl, ctrl & FIO_CTRL_READY, + ret = read_poll_timeout(wave5_vdi_read_register, ctrl, ctrl & FIO_CTRL_READY, 0, FIO_TIMEOUT, false, vpu_dev, W5_VPU_FIO_CTRL_ADDR); if (ret) return ret; - if (wave5_vdi_readl(vpu_dev, W5_VPU_FIO_DATA) != val) + + if (wave5_vdi_read_register(vpu_dev, W5_VPU_FIO_DATA) != val) return -ETIMEDOUT; + return 0; } @@ -76,14 +141,14 @@ static void wave5_fio_writel(struct vpu_device *vpu_dev, unsigned int addr, unsi unsigned int ctrl; wave5_vdi_write_register(vpu_dev, W5_VPU_FIO_DATA, data); - ctrl = FIO_CTRL_WRITE | (addr & 0xffff); + ctrl = FIELD_GET(FASTIO_ADDRESS_MASK, addr); + ctrl |= FIO_CTRL_WRITE; wave5_vdi_write_register(vpu_dev, W5_VPU_FIO_CTRL_ADDR, ctrl); - ret = read_poll_timeout(wave5_vdi_readl, ctrl, ctrl & FIO_CTRL_READY, 0, FIO_TIMEOUT, - false, vpu_dev, W5_VPU_FIO_CTRL_ADDR); - if (ret) { + ret = read_poll_timeout(wave5_vdi_read_register, ctrl, ctrl & FIO_CTRL_READY, 0, + FIO_TIMEOUT, false, vpu_dev, W5_VPU_FIO_CTRL_ADDR); + if (ret) dev_dbg_ratelimited(vpu_dev->dev, "FIO write timeout: addr=0x%x data=%x\n", ctrl, data); - } } static int wave5_wait_bus_busy(struct vpu_device *vpu_dev, unsigned int addr) @@ -102,7 +167,7 @@ static int wave5_wait_vpu_busy(struct vpu_device *vpu_dev, unsigned int addr) { u32 data; - return read_poll_timeout(wave5_vdi_readl, data, data == 0, + return read_poll_timeout(wave5_vdi_read_register, data, data == 0, 0, VPU_BUSY_CHECK_TIMEOUT, false, vpu_dev, addr); } @@ -118,65 +183,121 @@ bool wave5_vpu_is_init(struct vpu_device *vpu_dev) unsigned int wave5_vpu_get_product_id(struct vpu_device *vpu_dev) { - unsigned int product_id = PRODUCT_ID_NONE; - u32 val; - - val = vpu_read_reg(vpu_dev, W5_PRODUCT_NUMBER); + u32 val = vpu_read_reg(vpu_dev, W5_PRODUCT_NUMBER); switch (val) { - case WAVE521_CODE: + case WAVE511_CODE: + return PRODUCT_ID_511; case WAVE521C_CODE: + return PRODUCT_ID_521; + case WAVE521_CODE: case WAVE521C_DUAL_CODE: case WAVE521E1_CODE: - product_id = PRODUCT_ID_521; - break; - case WAVE511_CODE: - product_id = PRODUCT_ID_511; - break; case WAVE517_CODE: case WAVE537_CODE: - product_id = PRODUCT_ID_517; + dev_err(vpu_dev->dev, "Unsupported product id (%x)\n", val); break; default: dev_err(vpu_dev->dev, "Invalid product id (%x)\n", val); break; } - return product_id; + + return PRODUCT_ID_NONE; } -void wave5_bit_issue_command(struct vpu_instance *inst, u32 cmd) +static void wave5_bit_issue_command(struct vpu_device *vpu_dev, struct vpu_instance *inst, u32 cmd) { - u32 instance_index = inst->id; - u32 codec_mode = inst->std; + u32 instance_index; + u32 codec_mode; + + if (inst) { + instance_index = inst->id; + codec_mode = inst->std; + + vpu_write_reg(vpu_dev, W5_CMD_INSTANCE_INFO, (codec_mode << 16) | + (instance_index & 0xffff)); + vpu_write_reg(vpu_dev, W5_VPU_BUSY_STATUS, 1); + } - vpu_write_reg(inst->dev, W5_CMD_INSTANCE_INFO, (codec_mode << 16) | - (instance_index & 0xffff)); - vpu_write_reg(inst->dev, W5_VPU_BUSY_STATUS, 1); - vpu_write_reg(inst->dev, W5_COMMAND, cmd); + vpu_write_reg(vpu_dev, W5_COMMAND, cmd); - dev_dbg(inst->dev->dev, "%s: cmd=0x%x\n", __func__, cmd); + if (inst) { + dev_dbg(vpu_dev->dev, "%s: cmd=0x%x (%s)\n", __func__, cmd, + cmd_to_str(cmd, inst->type == VPU_INST_TYPE_DEC)); + } else { + dev_dbg(vpu_dev->dev, "%s: cmd=0x%x\n", __func__, cmd); + } - vpu_write_reg(inst->dev, W5_VPU_HOST_INT_REQ, 1); + vpu_write_reg(vpu_dev, W5_VPU_HOST_INT_REQ, 1); } -static int wave5_send_query(struct vpu_instance *inst, enum QUERY_OPT query_opt) +static int wave5_vpu_firmware_command_queue_error_check(struct vpu_device *dev, u32 *fail_res) { - int ret; + u32 reason = 0; - vpu_write_reg(inst->dev, W5_QUERY_OPTION, query_opt); - vpu_write_reg(inst->dev, W5_VPU_BUSY_STATUS, 1); - wave5_bit_issue_command(inst, W5_QUERY); + /* Check if we were able to add a command into the VCPU QUEUE */ + if (!vpu_read_reg(dev, W5_RET_SUCCESS)) { + reason = vpu_read_reg(dev, W5_RET_FAIL_REASON); + PRINT_REG_ERR(dev, reason); + /* + * The fail_res argument will be either NULL or 0. + * If the fail_res argument is NULL, then just return -EIO. + * Otherwise, assign the reason to fail_res, so that the + * calling function can use it. + */ + if (fail_res) + *fail_res = reason; + else + return -EIO; + + if (reason == WAVE5_SYSERR_VPU_STILL_RUNNING) + return -EBUSY; + } + return 0; +} + +static int send_firmware_command(struct vpu_instance *inst, u32 cmd, bool check_success, + u32 *queue_status, u32 *fail_result) +{ + int ret; + + wave5_bit_issue_command(inst->dev, inst, cmd); ret = wave5_wait_vpu_busy(inst->dev, W5_VPU_BUSY_STATUS); if (ret) { - dev_warn(inst->dev->dev, "command: 'W5_QUERY', timed out opt=0x%x\n", query_opt); - return ret; + dev_warn(inst->dev->dev, "%s: command: '%s', timed out\n", __func__, + cmd_to_str(cmd, inst->type == VPU_INST_TYPE_DEC)); + return -ETIMEDOUT; } - if (!vpu_read_reg(inst->dev, W5_RET_SUCCESS)) - return -EIO; + if (queue_status) + *queue_status = vpu_read_reg(inst->dev, W5_RET_QUEUE_STATUS); - return 0; + /* In some cases we want to send multiple commands before checking + * whether they are queued properly + */ + if (!check_success) + return 0; + + return wave5_vpu_firmware_command_queue_error_check(inst->dev, fail_result); +} + +static int wave5_send_query(struct vpu_device *vpu_dev, struct vpu_instance *inst, + enum query_opt query_opt) +{ + int ret; + + vpu_write_reg(vpu_dev, W5_QUERY_OPTION, query_opt); + vpu_write_reg(vpu_dev, W5_VPU_BUSY_STATUS, 1); + wave5_bit_issue_command(vpu_dev, inst, W5_QUERY); + + ret = wave5_wait_vpu_busy(vpu_dev, W5_VPU_BUSY_STATUS); + if (ret) { + dev_warn(vpu_dev->dev, "command: 'W5_QUERY', timed out opt=0x%x\n", query_opt); + return ret; + } + + return wave5_vpu_firmware_command_queue_error_check(vpu_dev, NULL); } static int setup_wave5_properties(struct device *dev) @@ -186,19 +307,12 @@ static int setup_wave5_properties(struct device *dev) u32 reg_val; u8 *str; int ret; - u32 hw_config_def0, hw_config_def1, hw_config_feature, hw_config_rev; + u32 hw_config_def0, hw_config_def1, hw_config_feature; - vpu_write_reg(vpu_dev, W5_QUERY_OPTION, GET_VPU_INFO); - vpu_write_reg(vpu_dev, W5_VPU_BUSY_STATUS, 1); - vpu_write_reg(vpu_dev, W5_COMMAND, W5_QUERY); - vpu_write_reg(vpu_dev, W5_VPU_HOST_INT_REQ, 1); - ret = wave5_wait_vpu_busy(vpu_dev, W5_VPU_BUSY_STATUS); + ret = wave5_send_query(vpu_dev, NULL, GET_VPU_INFO); if (ret) return ret; - if (!vpu_read_reg(vpu_dev, W5_RET_SUCCESS)) - return -EIO; - reg_val = vpu_read_reg(vpu_dev, W5_RET_PRODUCT_NAME); str = (u8 *)®_val; p_attr->product_name[0] = str[3]; @@ -214,51 +328,18 @@ static int setup_wave5_properties(struct device *dev) hw_config_def0 = vpu_read_reg(vpu_dev, W5_RET_STD_DEF0); hw_config_def1 = vpu_read_reg(vpu_dev, W5_RET_STD_DEF1); hw_config_feature = vpu_read_reg(vpu_dev, W5_RET_CONF_FEATURE); - hw_config_rev = vpu_read_reg(vpu_dev, W5_RET_CONF_REVISION); - p_attr->support_hevc10bit_enc = (hw_config_feature >> 3) & 1; - if (hw_config_rev > 167455) //20190321 - p_attr->support_avc10bit_enc = (hw_config_feature >> 11) & 1; - else - p_attr->support_avc10bit_enc = p_attr->support_hevc10bit_enc; - - p_attr->support_decoders = 0; - p_attr->support_encoders = 0; - if (p_attr->product_id == PRODUCT_ID_521) { - p_attr->support_dual_core = ((hw_config_def1 >> 26) & 0x01); - if (p_attr->support_dual_core || hw_config_rev < 206116) { - p_attr->support_decoders = BIT(STD_AVC); - p_attr->support_decoders |= BIT(STD_HEVC); - p_attr->support_encoders = BIT(STD_AVC); - p_attr->support_encoders |= BIT(STD_HEVC); - } else { - p_attr->support_decoders |= (((hw_config_def1 >> 3) & 0x01) << STD_AVC); - p_attr->support_decoders |= (((hw_config_def1 >> 2) & 0x01) << STD_HEVC); - p_attr->support_encoders = (((hw_config_def1 >> 1) & 0x01) << STD_AVC); - p_attr->support_encoders |= ((hw_config_def1 & 0x01) << STD_HEVC); - } - } else if (p_attr->product_id == PRODUCT_ID_511) { - p_attr->support_decoders = BIT(STD_HEVC); - p_attr->support_decoders |= BIT(STD_AVC); - } else if (p_attr->product_id == PRODUCT_ID_517) { - p_attr->support_decoders = (((hw_config_def1 >> 4) & 0x01) << STD_AV1); - p_attr->support_decoders |= (((hw_config_def1 >> 3) & 0x01) << STD_AVS2); - p_attr->support_decoders |= (((hw_config_def1 >> 2) & 0x01) << STD_AVC); - p_attr->support_decoders |= (((hw_config_def1 >> 1) & 0x01) << STD_VP9); - p_attr->support_decoders |= ((hw_config_def1 & 0x01) << STD_HEVC); - } - - p_attr->support_backbone = (hw_config_def0 >> 16) & 0x01; - p_attr->support_vcpu_backbone = (hw_config_def0 >> 28) & 0x01; - p_attr->support_vcore_backbone = (hw_config_def0 >> 22) & 0x01; - p_attr->support_dual_core = (hw_config_def1 >> 26) & 0x01; - p_attr->support_endian_mask = BIT(VDI_LITTLE_ENDIAN) | - BIT(VDI_BIG_ENDIAN) | - BIT(VDI_32BIT_LITTLE_ENDIAN) | - BIT(VDI_32BIT_BIG_ENDIAN) | - (0xffffUL << 16); - p_attr->support_bitstream_mode = BIT(BS_MODE_INTERRUPT) | - BIT(BS_MODE_PIC_END); + p_attr->support_hevc10bit_enc = FIELD_GET(FEATURE_HEVC10BIT_ENC, hw_config_feature); + p_attr->support_avc10bit_enc = FIELD_GET(FEATURE_AVC10BIT_ENC, hw_config_feature); + + p_attr->support_decoders = FIELD_GET(FEATURE_AVC_DECODER, hw_config_def1) << STD_AVC; + p_attr->support_decoders |= FIELD_GET(FEATURE_HEVC_DECODER, hw_config_def1) << STD_HEVC; + p_attr->support_encoders = FIELD_GET(FEATURE_AVC_ENCODER, hw_config_def1) << STD_AVC; + p_attr->support_encoders |= FIELD_GET(FEATURE_HEVC_ENCODER, hw_config_def1) << STD_HEVC; + + p_attr->support_backbone = FIELD_GET(FEATURE_BACKBONE, hw_config_def0); + p_attr->support_vcpu_backbone = FIELD_GET(FEATURE_VCPU_BACKBONE, hw_config_def0); + p_attr->support_vcore_backbone = FIELD_GET(FEATURE_VCORE_BACKBONE, hw_config_def0); return 0; } @@ -268,35 +349,22 @@ int wave5_vpu_get_version(struct vpu_device *vpu_dev, u32 *revision) u32 reg_val; int ret; - vpu_write_reg(vpu_dev, W5_QUERY_OPTION, GET_VPU_INFO); - vpu_write_reg(vpu_dev, W5_VPU_BUSY_STATUS, 1); - vpu_write_reg(vpu_dev, W5_COMMAND, W5_QUERY); - vpu_write_reg(vpu_dev, W5_VPU_HOST_INT_REQ, 1); - ret = wave5_wait_vpu_busy(vpu_dev, W5_VPU_BUSY_STATUS); - if (ret) { - dev_err(vpu_dev->dev, "%s: timeout\n", __func__); + ret = wave5_send_query(vpu_dev, NULL, GET_VPU_INFO); + if (ret) return ret; - } - - if (!vpu_read_reg(vpu_dev, W5_RET_SUCCESS)) { - dev_err(vpu_dev->dev, "%s: failed\n", __func__); - return -EIO; - } reg_val = vpu_read_reg(vpu_dev, W5_RET_FW_VERSION); - if (revision) + if (revision) { *revision = reg_val; + return 0; + } - return 0; + return -EINVAL; } static void remap_page(struct vpu_device *vpu_dev, dma_addr_t code_base, u32 index) { - u32 remap_size = (W5_REMAP_MAX_SIZE >> 12) & 0x1ff; - u32 reg_val = 0x80000000 | (WAVE5_UPPER_PROC_AXI_ID << 20) | (index << 12) | BIT(11) - | remap_size; - - vpu_write_reg(vpu_dev, W5_VPU_REMAP_CTRL, reg_val); + vpu_write_reg(vpu_dev, W5_VPU_REMAP_CTRL, REMAP_CTRL_REGISTER_VALUE(index)); vpu_write_reg(vpu_dev, W5_VPU_REMAP_VADDR, index * W5_REMAP_MAX_SIZE); vpu_write_reg(vpu_dev, W5_VPU_REMAP_PADDR, code_base + index * W5_REMAP_MAX_SIZE); } @@ -304,10 +372,9 @@ static void remap_page(struct vpu_device *vpu_dev, dma_addr_t code_base, u32 ind int wave5_vpu_init(struct device *dev, u8 *fw, size_t size) { struct vpu_buf *common_vb; - struct dma_vpu_buf *sram_vb; dma_addr_t code_base, temp_base; u32 code_size, temp_size; - u32 i, reg_val; + u32 i, reg_val, reason_code; int ret; struct vpu_device *vpu_dev = dev_get_drvdata(dev); @@ -322,7 +389,7 @@ int wave5_vpu_init(struct device *dev, u8 *fw, size_t size) temp_base = common_vb->daddr + WAVE5_TEMPBUF_OFFSET; temp_size = WAVE5_TEMPBUF_SIZE; - ret = wave5_vdi_write_memory(vpu_dev, common_vb, 0, fw, size, VDI_128BIT_LITTLE_ENDIAN); + ret = wave5_vdi_write_memory(vpu_dev, common_vb, 0, fw, size); if (ret < 0) { dev_err(vpu_dev->dev, "VPU init, Writing firmware to common buffer, fail: %d\n", ret); @@ -345,31 +412,24 @@ int wave5_vpu_init(struct device *dev, u8 *fw, size_t size) vpu_write_reg(vpu_dev, W5_ADDR_TEMP_BASE, temp_base); vpu_write_reg(vpu_dev, W5_TEMP_SIZE, temp_size); + /* These register must be reset explicitly */ vpu_write_reg(vpu_dev, W5_HW_OPTION, 0); + wave5_fio_writel(vpu_dev, W5_BACKBONE_PROC_EXT_ADDR, 0); + wave5_fio_writel(vpu_dev, W5_BACKBONE_AXI_PARAM, 0); + vpu_write_reg(vpu_dev, W5_SEC_AXI_PARAM, 0); - reg_val = (WAVE5_PROC_AXI_EXT_ADDR & 0xFFFF); - wave5_fio_writel(vpu_dev, W5_BACKBONE_PROC_EXT_ADDR, reg_val); - reg_val = ((WAVE5_PROC_AXI_AXPROT & 0x7) << 4) | - (WAVE5_PROC_AXI_AXCACHE & 0xF); - wave5_fio_writel(vpu_dev, W5_BACKBONE_AXI_PARAM, reg_val); - reg_val = ((WAVE5_SEC_AXI_AXPROT & 0x7) << 20) | - ((WAVE5_SEC_AXI_AXCACHE & 0xF) << 16) | - (WAVE5_SEC_AXI_EXT_ADDR & 0xFFFF); - vpu_write_reg(vpu_dev, W5_SEC_AXI_PARAM, reg_val); - - /* interrupt */ - // encoder + /* Encoder interrupt */ reg_val = BIT(INT_WAVE5_ENC_SET_PARAM); reg_val |= BIT(INT_WAVE5_ENC_PIC); reg_val |= BIT(INT_WAVE5_BSBUF_FULL); - // decoder + /* Decoder interrupt */ reg_val |= BIT(INT_WAVE5_INIT_SEQ); reg_val |= BIT(INT_WAVE5_DEC_PIC); reg_val |= BIT(INT_WAVE5_BSBUF_EMPTY); vpu_write_reg(vpu_dev, W5_VPU_VINT_ENABLE, reg_val); reg_val = vpu_read_reg(vpu_dev, W5_VPU_RET_VPU_CONFIG0); - if ((reg_val >> 16) & 1) { + if (FIELD_GET(FEATURE_BACKBONE, reg_val)) { reg_val = ((WAVE5_PROC_AXI_ID << 28) | (WAVE5_PRP_AXI_ID << 24) | (WAVE5_FBD_Y_AXI_ID << 20) | @@ -381,10 +441,6 @@ int wave5_vpu_init(struct device *dev, u8 *fw, size_t size) wave5_fio_writel(vpu_dev, W5_BACKBONE_PROG_AXI_ID, reg_val); } - sram_vb = &vpu_dev->sram_buf; - - vpu_write_reg(vpu_dev, W5_ADDR_SEC_AXI, sram_vb->daddr); - vpu_write_reg(vpu_dev, W5_SEC_AXI_SIZE, sram_vb->size); vpu_write_reg(vpu_dev, W5_VPU_BUSY_STATUS, 1); vpu_write_reg(vpu_dev, W5_COMMAND, W5_INIT_VPU); vpu_write_reg(vpu_dev, W5_VPU_REMAP_CORE_START, 1); @@ -394,13 +450,9 @@ int wave5_vpu_init(struct device *dev, u8 *fw, size_t size) return ret; } - reg_val = vpu_read_reg(vpu_dev, W5_RET_SUCCESS); - if (!reg_val) { - u32 reason_code = vpu_read_reg(vpu_dev, W5_RET_FAIL_REASON); - - wave5_print_reg_err(vpu_dev, reason_code); - return -EIO; - } + ret = wave5_vpu_firmware_command_queue_error_check(vpu_dev, &reason_code); + if (ret) + return ret; return setup_wave5_properties(dev); } @@ -410,157 +462,136 @@ int wave5_vpu_build_up_dec_param(struct vpu_instance *inst, { int ret; struct dec_info *p_dec_info = &inst->codec_info->dec_info; - u32 bs_endian; - struct dma_vpu_buf *sram_vb; struct vpu_device *vpu_dev = inst->dev; p_dec_info->cycle_per_tick = 256; + if (vpu_dev->sram_buf.size) { + p_dec_info->sec_axi_info.use_bit_enable = 1; + p_dec_info->sec_axi_info.use_ip_enable = 1; + p_dec_info->sec_axi_info.use_lf_row_enable = 1; + } switch (inst->std) { case W_HEVC_DEC: p_dec_info->seq_change_mask = SEQ_CHANGE_ENABLE_ALL_HEVC; break; - case W_VP9_DEC: - p_dec_info->seq_change_mask = SEQ_CHANGE_ENABLE_ALL_VP9; - break; - case W_AVS2_DEC: - p_dec_info->seq_change_mask = SEQ_CHANGE_ENABLE_ALL_AVS2; - break; case W_AVC_DEC: p_dec_info->seq_change_mask = SEQ_CHANGE_ENABLE_ALL_AVC; break; - case W_AV1_DEC: - p_dec_info->seq_change_mask = SEQ_CHANGE_ENABLE_ALL_AV1; - break; default: return -EINVAL; } - if (vpu_dev->product == PRODUCT_ID_517) - p_dec_info->vb_work.size = WAVE517_WORKBUF_SIZE; - else if (vpu_dev->product == PRODUCT_ID_521) - p_dec_info->vb_work.size = WAVE521DEC_WORKBUF_SIZE; - else if (vpu_dev->product == PRODUCT_ID_511) - p_dec_info->vb_work.size = WAVE521DEC_WORKBUF_SIZE; - + p_dec_info->vb_work.size = WAVE521DEC_WORKBUF_SIZE; ret = wave5_vdi_allocate_dma_memory(inst->dev, &p_dec_info->vb_work); if (ret) return ret; vpu_write_reg(inst->dev, W5_CMD_DEC_VCORE_INFO, 1); - sram_vb = &vpu_dev->sram_buf; - p_dec_info->sec_axi_info.buf_base = sram_vb->daddr; - p_dec_info->sec_axi_info.buf_size = sram_vb->size; - wave5_vdi_clear_memory(inst->dev, &p_dec_info->vb_work); vpu_write_reg(inst->dev, W5_ADDR_WORK_BASE, p_dec_info->vb_work.daddr); vpu_write_reg(inst->dev, W5_WORK_SIZE, p_dec_info->vb_work.size); + vpu_write_reg(inst->dev, W5_CMD_ADDR_SEC_AXI, vpu_dev->sram_buf.daddr); + vpu_write_reg(inst->dev, W5_CMD_SEC_AXI_SIZE, vpu_dev->sram_buf.size); + vpu_write_reg(inst->dev, W5_CMD_DEC_BS_START_ADDR, p_dec_info->stream_buf_start_addr); vpu_write_reg(inst->dev, W5_CMD_DEC_BS_SIZE, p_dec_info->stream_buf_size); - /* NOTE: when endian mode is 0, SDMA reads MSB first */ - bs_endian = wave5_vdi_convert_endian(inst->dev, param->stream_endian); - bs_endian = (~bs_endian & VDI_128BIT_ENDIAN_MASK); - vpu_write_reg(inst->dev, W5_CMD_BS_PARAM, bs_endian); - vpu_write_reg(inst->dev, W5_CMD_EXT_ADDR, (param->pri_axprot << 20) | - (param->pri_axcache << 16) | param->pri_ext_addr); + /* NOTE: SDMA reads MSB first */ + vpu_write_reg(inst->dev, W5_CMD_BS_PARAM, BITSTREAM_ENDIANNESS_BIG_ENDIAN); + /* This register must be reset explicitly */ + vpu_write_reg(inst->dev, W5_CMD_EXT_ADDR, 0); vpu_write_reg(inst->dev, W5_CMD_NUM_CQ_DEPTH_M1, (COMMAND_QUEUE_DEPTH - 1)); - vpu_write_reg(inst->dev, W5_CMD_ERR_CONCEAL, (param->error_conceal_unit << 2) | - (param->error_conceal_mode)); - wave5_bit_issue_command(inst, W5_CREATE_INSTANCE); - // check QUEUE_DONE - ret = wave5_wait_vpu_busy(inst->dev, W5_VPU_BUSY_STATUS); + ret = send_firmware_command(inst, W5_CREATE_INSTANCE, true, NULL, NULL); if (ret) { - dev_warn(inst->dev->dev, "command: 'W5_CREATE_INSTANCE' timed out\n"); - goto free_vb_work; + wave5_vdi_free_dma_memory(vpu_dev, &p_dec_info->vb_work); + return ret; } - // Check if we were able to add the parameters into the VCPU QUEUE - if (!vpu_read_reg(inst->dev, W5_RET_SUCCESS)) { - ret = -EIO; - goto free_vb_work; + p_dec_info->product_code = vpu_read_reg(inst->dev, W5_PRODUCT_NUMBER); + + return 0; +} + +int wave5_vpu_hw_flush_instance(struct vpu_instance *inst) +{ + struct dec_info *p_dec_info = &inst->codec_info->dec_info; + u32 instance_queue_count, report_queue_count; + u32 reg_val = 0; + u32 fail_res = 0; + int ret; + + ret = send_firmware_command(inst, W5_FLUSH_INSTANCE, true, ®_val, &fail_res); + if (ret) + return ret; + + instance_queue_count = (reg_val >> 16) & 0xff; + report_queue_count = (reg_val & QUEUE_REPORT_MASK); + if (instance_queue_count != 0 || report_queue_count != 0) { + dev_warn(inst->dev->dev, + "FLUSH_INSTANCE cmd didn't reset the amount of queued commands & reports"); } - p_dec_info->product_code = vpu_read_reg(inst->dev, W5_PRODUCT_NUMBER); + /* reset our local copy of the counts */ + p_dec_info->instance_queue_count = 0; + p_dec_info->report_queue_count = 0; return 0; -free_vb_work: - wave5_vdi_free_dma_memory(vpu_dev, &p_dec_info->vb_work); - return ret; +} + +static u32 get_bitstream_options(struct dec_info *info) +{ + u32 bs_option = BSOPTION_ENABLE_EXPLICIT_END; + + if (info->stream_endflag) + bs_option |= BSOPTION_HIGHLIGHT_STREAM_END; + return bs_option; } int wave5_vpu_dec_init_seq(struct vpu_instance *inst) { struct dec_info *p_dec_info = &inst->codec_info->dec_info; u32 cmd_option = INIT_SEQ_NORMAL; - u32 reg_val, bs_option; + u32 reg_val, fail_res; int ret; if (!inst->codec_info) return -EINVAL; - if (p_dec_info->thumbnail_mode) - cmd_option = INIT_SEQ_W_THUMBNAIL; - - /* set attributes of bitstream buffer controller */ - switch (p_dec_info->open_param.bitstream_mode) { - case BS_MODE_INTERRUPT: - bs_option = BSOPTION_ENABLE_EXPLICIT_END; - break; - case BS_MODE_PIC_END: - bs_option = BSOPTION_ENABLE_EXPLICIT_END; - break; - default: - return -EINVAL; - } - vpu_write_reg(inst->dev, W5_BS_RD_PTR, p_dec_info->stream_rd_ptr); vpu_write_reg(inst->dev, W5_BS_WR_PTR, p_dec_info->stream_wr_ptr); - if (p_dec_info->stream_endflag) - bs_option = 3; - if (inst->std == W_AV1_DEC) - bs_option |= ((p_dec_info->open_param.av1_format) << 2); - vpu_write_reg(inst->dev, W5_BS_OPTION, BIT(31) | bs_option); + vpu_write_reg(inst->dev, W5_BS_OPTION, get_bitstream_options(p_dec_info)); vpu_write_reg(inst->dev, W5_COMMAND_OPTION, cmd_option); vpu_write_reg(inst->dev, W5_CMD_DEC_USER_MASK, p_dec_info->user_data_enable); - wave5_bit_issue_command(inst, W5_INIT_SEQ); - - // check QUEUE_DONE - ret = wave5_wait_vpu_busy(inst->dev, W5_VPU_BUSY_STATUS); - if (ret) { - dev_warn(inst->dev->dev, "command: 'W5_INIT_SEQ', timed out\n"); + ret = send_firmware_command(inst, W5_INIT_SEQ, true, ®_val, &fail_res); + if (ret) return ret; - } - - reg_val = vpu_read_reg(inst->dev, W5_RET_QUEUE_STATUS); p_dec_info->instance_queue_count = (reg_val >> 16) & 0xff; p_dec_info->report_queue_count = (reg_val & QUEUE_REPORT_MASK); - // Check if we were able to add a command into VCPU QUEUE - if (!vpu_read_reg(inst->dev, W5_RET_SUCCESS)) { - reg_val = vpu_read_reg(inst->dev, W5_RET_FAIL_REASON); - wave5_print_reg_err(inst->dev, reg_val); - return -EIO; - } + dev_dbg(inst->dev->dev, "%s: init seq sent (queue %u : %u)\n", __func__, + p_dec_info->instance_queue_count, p_dec_info->report_queue_count); + + if (ret) + return ret; return 0; } static void wave5_get_dec_seq_result(struct vpu_instance *inst, struct dec_initial_info *info) { - u32 reg_val, sub_layer_info; + u32 reg_val; u32 profile_compatibility_flag; - u32 output_bit_depth_minus8; struct dec_info *p_dec_info = &inst->codec_info->dec_info; - p_dec_info->stream_rd_ptr = wave5_vpu_dec_get_rd_ptr(inst); + p_dec_info->stream_rd_ptr = wave5_dec_get_rd_ptr(inst); info->rd_ptr = p_dec_info->stream_rd_ptr; p_dec_info->frame_display_flag = vpu_read_reg(inst->dev, W5_RET_DEC_DISP_IDC); @@ -568,9 +599,7 @@ static void wave5_get_dec_seq_result(struct vpu_instance *inst, struct dec_initi reg_val = vpu_read_reg(inst->dev, W5_RET_DEC_PIC_SIZE); info->pic_width = ((reg_val >> 16) & 0xffff); info->pic_height = (reg_val & 0xffff); - dev_dbg(inst->dev->dev, "%s info->pic_width %d info->pic_height %d\n",__func__, info->pic_width, info->pic_height); info->min_frame_buffer_count = vpu_read_reg(inst->dev, W5_RET_DEC_NUM_REQUIRED_FB); - info->frame_buf_delay = vpu_read_reg(inst->dev, W5_RET_DEC_NUM_REORDER_DELAY); reg_val = vpu_read_reg(inst->dev, W5_RET_DEC_CROP_LEFT_RIGHT); info->pic_crop_rect.left = (reg_val >> 16) & 0xffff; @@ -578,8 +607,6 @@ static void wave5_get_dec_seq_result(struct vpu_instance *inst, struct dec_initi reg_val = vpu_read_reg(inst->dev, W5_RET_DEC_CROP_TOP_BOTTOM); info->pic_crop_rect.top = (reg_val >> 16) & 0xffff; info->pic_crop_rect.bottom = reg_val & 0xffff; - dev_dbg(inst->dev->dev, "%s pic_crop_rect.left %d pic_crop_rect.right %d pic_crop_rect.top %d pic_crop_rect.bottom %d\n",__func__, - info->pic_crop_rect.left, info->pic_crop_rect.right, info->pic_crop_rect.top, info->pic_crop_rect.bottom); info->f_rate_numerator = vpu_read_reg(inst->dev, W5_RET_DEC_FRAME_RATE_NR); info->f_rate_denominator = vpu_read_reg(inst->dev, W5_RET_DEC_FRAME_RATE_DR); @@ -598,46 +625,26 @@ static void wave5_get_dec_seq_result(struct vpu_instance *inst, struct dec_initi reg_val = vpu_read_reg(inst->dev, W5_RET_DEC_COLOR_SAMPLE_INFO); info->luma_bitdepth = reg_val & 0xf; info->chroma_bitdepth = (reg_val >> 4) & 0xf; - info->chroma_format_idc = (reg_val >> 8) & 0xf; - info->aspect_rate_info = (reg_val >> 16) & 0xff; - info->is_ext_sar = ((info->aspect_rate_info == 255) ? true : false); - /* [0:15] - vertical size, [16:31] - horizontal size */ - if (info->is_ext_sar) - info->aspect_rate_info = vpu_read_reg(inst->dev, W5_RET_DEC_ASPECT_RATIO); - info->bit_rate = vpu_read_reg(inst->dev, W5_RET_DEC_BIT_RATE); - - sub_layer_info = vpu_read_reg(inst->dev, W5_RET_DEC_SUB_LAYER_INFO); - info->max_temporal_layers = (sub_layer_info >> 8) & 0x7; reg_val = vpu_read_reg(inst->dev, W5_RET_DEC_SEQ_PARAM); - info->level = reg_val & 0xff; profile_compatibility_flag = (reg_val >> 12) & 0xff; info->profile = (reg_val >> 24) & 0x1f; - info->tier = (reg_val >> 29) & 0x01; - output_bit_depth_minus8 = (reg_val >> 30) & 0x03; if (inst->std == W_HEVC_DEC) { /* guessing profile */ if (!info->profile) { if ((profile_compatibility_flag & 0x06) == 0x06) info->profile = HEVC_PROFILE_MAIN; /* main profile */ - else if ((profile_compatibility_flag & 0x04) == 0x04) + else if (profile_compatibility_flag & 0x04) info->profile = HEVC_PROFILE_MAIN10; /* main10 profile */ - else if ((profile_compatibility_flag & 0x08) == 0x08) + else if (profile_compatibility_flag & 0x08) /* main still picture profile */ info->profile = HEVC_PROFILE_STILLPICTURE; else info->profile = HEVC_PROFILE_MAIN; /* for old version HM */ } - - } else if (inst->std == W_AVS2_DEC) { - if (info->luma_bitdepth == 10 && output_bit_depth_minus8 == 2) - info->output_bit_depth = 10; - else - info->output_bit_depth = 8; - } else if (inst->std == W_AVC_DEC) { - info->profile = (reg_val >> 24) & 0x7f; + info->profile = FIELD_GET(SEQ_PARAM_PROFILE_MASK, reg_val); } info->vlc_buf_size = vpu_read_reg(inst->dev, W5_RET_VLC_BUF_SIZE); @@ -654,42 +661,25 @@ int wave5_vpu_dec_get_seq_info(struct vpu_instance *inst, struct dec_initial_inf vpu_write_reg(inst->dev, W5_CMD_DEC_ADDR_REPORT_BASE, p_dec_info->user_data_buf_addr); vpu_write_reg(inst->dev, W5_CMD_DEC_REPORT_SIZE, p_dec_info->user_data_buf_size); - vpu_write_reg(inst->dev, W5_CMD_DEC_REPORT_PARAM, - VPU_USER_DATA_ENDIAN & VDI_128BIT_ENDIAN_MASK); + vpu_write_reg(inst->dev, W5_CMD_DEC_REPORT_PARAM, REPORT_PARAM_ENDIANNESS_BIG_ENDIAN); - // send QUERY cmd - ret = wave5_send_query(inst, GET_RESULT); - if (ret) { - if (ret == -EIO) { - reg_val = vpu_read_reg(inst->dev, W5_RET_FAIL_REASON); - wave5_print_reg_err(inst->dev, reg_val); - } + /* send QUERY cmd */ + ret = wave5_send_query(inst->dev, inst, GET_RESULT); + if (ret) return ret; - } - - dev_dbg(inst->dev->dev, "%s: init seq complete\n", __func__); reg_val = vpu_read_reg(inst->dev, W5_RET_QUEUE_STATUS); p_dec_info->instance_queue_count = (reg_val >> 16) & 0xff; p_dec_info->report_queue_count = (reg_val & QUEUE_REPORT_MASK); + dev_dbg(inst->dev->dev, "%s: init seq complete (queue %u : %u)\n", __func__, + p_dec_info->instance_queue_count, p_dec_info->report_queue_count); + /* this is not a fatal error, set ret to -EIO but don't return immediately */ if (vpu_read_reg(inst->dev, W5_RET_DEC_DECODING_SUCCESS) != 1) { info->seq_init_err_reason = vpu_read_reg(inst->dev, W5_RET_DEC_ERR_INFO); ret = -EIO; - } else { - info->warn_info = vpu_read_reg(inst->dev, W5_RET_DEC_WARN_INFO); - } - - // get sequence info - info->user_data_size = 0; - info->user_data_buf_full = false; - info->user_data_header = vpu_read_reg(inst->dev, W5_RET_DEC_USERDATA_IDC); - if (info->user_data_header) { - if (info->user_data_header & BIT(USERDATA_FLAG_BUFF_FULL)) - info->user_data_buf_full = true; - info->user_data_size = p_dec_info->user_data_buf_size; } wave5_get_dec_seq_result(inst, info); @@ -697,36 +687,20 @@ int wave5_vpu_dec_get_seq_info(struct vpu_instance *inst, struct dec_initial_inf return ret; } -static u32 calculate_table_size(u32 bit_depth, u32 frame_width, u32 frame_height, u32 ot_bg_width) -{ - u32 bgs_width = ((bit_depth > 8) ? 256 : 512); - u32 comp_frame_width = ALIGN(ALIGN(frame_width, 16) + 16, 16); - u32 ot_frame_width = ALIGN(comp_frame_width, ot_bg_width); - - // sizeof_offset_table() - u32 ot_bg_height = 32; - u32 bgs_height = BIT(14) / bgs_width / ((bit_depth > 8) ? 2 : 1); - u32 comp_frame_height = ALIGN(ALIGN(frame_height, 4) + 4, bgs_height); - u32 ot_frame_height = ALIGN(comp_frame_height, ot_bg_height); - - return (ot_frame_width / 16) * (ot_frame_height / 4) * 2; -} - int wave5_vpu_dec_register_framebuffer(struct vpu_instance *inst, struct frame_buffer *fb_arr, enum tiled_map_type map_type, unsigned int count) { int ret; struct dec_info *p_dec_info = &inst->codec_info->dec_info; struct dec_initial_info *init_info = &p_dec_info->initial_info; - size_t remain, idx, j, i, cnt_8_chunk; + size_t remain, idx, j, i, cnt_8_chunk, size; u32 start_no, end_no; u32 reg_val, cbcr_interleave, nv21, pic_size; - u32 endian, yuv_format; u32 addr_y, addr_cb, addr_cr; - u32 table_width = init_info->pic_width; - u32 table_height = init_info->pic_height; u32 mv_col_size, frame_width, frame_height, fbc_y_tbl_size, fbc_c_tbl_size; struct vpu_buf vb_buf; + bool justified = WTL_RIGHT_JUSTIFIED; + u32 format_no = WTL_PIXEL_8BIT; u32 color_format = 0; u32 pixel_order = 1; u32 bwb_flag = (map_type == LINEAR_FRAME_MAP) ? 1 : 0; @@ -746,132 +720,77 @@ int wave5_vpu_dec_register_framebuffer(struct vpu_instance *inst, struct frame_b mv_col_size = WAVE5_DEC_HEVC_BUF_SIZE(init_info->pic_width, init_info->pic_height); break; - case W_VP9_DEC: - mv_col_size = WAVE5_DEC_VP9_BUF_SIZE(init_info->pic_width, - init_info->pic_height); - table_width = ALIGN(table_width, 64); - table_height = ALIGN(table_height, 64); - break; - case W_AVS2_DEC: - mv_col_size = WAVE5_DEC_AVS2_BUF_SIZE(init_info->pic_width, - init_info->pic_height); - break; case W_AVC_DEC: mv_col_size = WAVE5_DEC_AVC_BUF_SIZE(init_info->pic_width, init_info->pic_height); break; - case W_AV1_DEC: - mv_col_size = WAVE5_DEC_AV1_BUF_SZ_1(init_info->pic_width, - init_info->pic_height) + - WAVE5_DEC_AV1_BUF_SZ_2(init_info->pic_width, init_info->pic_width, - init_info->pic_height); - table_width = ALIGN(table_width, 16); - table_height = ALIGN(table_height, 8); - break; default: return -EINVAL; } - mv_col_size = ALIGN(mv_col_size, 16); - vb_buf.daddr = 0; - if (inst->std == W_HEVC_DEC || inst->std == W_AVS2_DEC || inst->std == - W_VP9_DEC || inst->std == W_AVC_DEC || inst->std == - W_AV1_DEC) { - vb_buf.size = ALIGN(mv_col_size, BUFFER_MARGIN) + BUFFER_MARGIN; - - for (i = 0 ; i < count ; i++) { - if (p_dec_info->vb_mv[i].size == 0) { - ret = wave5_vdi_allocate_dma_memory(inst->dev, &vb_buf); - if (ret) - goto free_mv_buffers; - p_dec_info->vb_mv[i] = vb_buf; - } - } + if (inst->std == W_HEVC_DEC || inst->std == W_AVC_DEC) { + size = ALIGN(ALIGN(mv_col_size, 16), BUFFER_MARGIN) + BUFFER_MARGIN; + ret = wave5_vdi_allocate_array(inst->dev, p_dec_info->vb_mv, count, size); + if (ret) + goto free_mv_buffers; } - frame_width = ALIGN(init_info->pic_width, 16); - frame_height = ALIGN(init_info->pic_height, 16); - if (p_dec_info->product_code == WAVE521C_DUAL_CODE) { - // Use a offset table BG width of 1024 for all decoders - fbc_y_tbl_size = calculate_table_size(init_info->luma_bitdepth, - frame_width, frame_height, 1024); - } else { - fbc_y_tbl_size = ALIGN(WAVE5_FBC_LUMA_TABLE_SIZE(table_width, - table_height), 16); - } + frame_width = init_info->pic_width; + frame_height = init_info->pic_height; + fbc_y_tbl_size = ALIGN(WAVE5_FBC_LUMA_TABLE_SIZE(frame_width, frame_height), 16); + fbc_c_tbl_size = ALIGN(WAVE5_FBC_CHROMA_TABLE_SIZE(frame_width, frame_height), 16); - vb_buf.daddr = 0; - vb_buf.size = ALIGN(fbc_y_tbl_size, BUFFER_MARGIN) + BUFFER_MARGIN; - for (i = 0 ; i < count ; i++) { - if (p_dec_info->vb_fbc_y_tbl[i].size == 0) { - ret = wave5_vdi_allocate_dma_memory(inst->dev, &vb_buf); - if (ret) - goto free_fbc_y_tbl_buffers; - p_dec_info->vb_fbc_y_tbl[i] = vb_buf; - } - } + size = ALIGN(fbc_y_tbl_size, BUFFER_MARGIN) + BUFFER_MARGIN; + ret = wave5_vdi_allocate_array(inst->dev, p_dec_info->vb_fbc_y_tbl, count, size); + if (ret) + goto free_fbc_y_tbl_buffers; - if (p_dec_info->product_code == WAVE521C_DUAL_CODE) { - // Use a offset table BG width of 1024 for all decoders - fbc_c_tbl_size = calculate_table_size(init_info->chroma_bitdepth, - frame_width / 2, frame_height, 1024); - } else { - fbc_c_tbl_size = ALIGN(WAVE5_FBC_CHROMA_TABLE_SIZE(table_width, - table_height), 16); - } + size = ALIGN(fbc_c_tbl_size, BUFFER_MARGIN) + BUFFER_MARGIN; + ret = wave5_vdi_allocate_array(inst->dev, p_dec_info->vb_fbc_c_tbl, count, size); + if (ret) + goto free_fbc_c_tbl_buffers; - vb_buf.daddr = 0; - vb_buf.size = ALIGN(fbc_c_tbl_size, BUFFER_MARGIN) + BUFFER_MARGIN; - for (i = 0 ; i < count ; i++) { - if (p_dec_info->vb_fbc_c_tbl[i].size == 0) { - ret = wave5_vdi_allocate_dma_memory(inst->dev, &vb_buf); - if (ret) - goto free_fbc_c_tbl_buffers; - p_dec_info->vb_fbc_c_tbl[i] = vb_buf; - } - } pic_size = (init_info->pic_width << 16) | (init_info->pic_height); - // allocate task_buffer vb_buf.size = (p_dec_info->vlc_buf_size * VLC_BUF_NUM) + (p_dec_info->param_buf_size * COMMAND_QUEUE_DEPTH); vb_buf.daddr = 0; - ret = wave5_vdi_allocate_dma_memory(inst->dev, &vb_buf); - if (ret) - goto free_fbc_c_tbl_buffers; - p_dec_info->vb_task = vb_buf; + if (vb_buf.size != p_dec_info->vb_task.size) { + wave5_vdi_free_dma_memory(inst->dev, &p_dec_info->vb_task); + ret = wave5_vdi_allocate_dma_memory(inst->dev, &vb_buf); + if (ret) + goto free_fbc_c_tbl_buffers; + + p_dec_info->vb_task = vb_buf; + } vpu_write_reg(inst->dev, W5_CMD_SET_FB_ADDR_TASK_BUF, p_dec_info->vb_task.daddr); vpu_write_reg(inst->dev, W5_CMD_SET_FB_TASK_BUF_SIZE, vb_buf.size); } else { pic_size = (init_info->pic_width << 16) | (init_info->pic_height); + + if (inst->output_format == FORMAT_422) + color_format = 1; } - dev_dbg(inst->dev->dev, "set pic_size 0x%x\n", pic_size); - endian = wave5_vdi_convert_endian(inst->dev, fb_arr[0].endian); vpu_write_reg(inst->dev, W5_PIC_SIZE, pic_size); - yuv_format = 0; - color_format = 0; - - reg_val = - (bwb_flag << 28) | - (pixel_order << 23) | /* PIXEL ORDER in 128bit. first pixel in low address */ - (yuv_format << 20) | - (color_format << 19) | - (nv21 << 17) | - (cbcr_interleave << 16) | - (fb_arr[0].stride); - dev_dbg(inst->dev->dev, "set W5_COMMON_PIC_INFO 0x%x\n",reg_val); + reg_val = (bwb_flag << 28) | + (pixel_order << 23) | + (justified << 22) | + (format_no << 20) | + (color_format << 19) | + (nv21 << 17) | + (cbcr_interleave << 16) | + (fb_arr[0].stride); vpu_write_reg(inst->dev, W5_COMMON_PIC_INFO, reg_val); remain = count; - cnt_8_chunk = ALIGN(count, 8) / 8; + cnt_8_chunk = DIV_ROUND_UP(count, 8); idx = 0; for (j = 0; j < cnt_8_chunk; j++) { - reg_val = (endian << 16) | (j == cnt_8_chunk - 1) << 4 | ((j == 0) << 3); - reg_val |= (p_dec_info->open_param.enable_non_ref_fbc_write << 26); + reg_val = (j == cnt_8_chunk - 1) << 4 | ((j == 0) << 3); vpu_write_reg(inst->dev, W5_SFB_OPTION, reg_val); start_no = j * 8; end_no = start_no + ((remain >= 8) ? 8 : remain) - 1; @@ -879,16 +798,9 @@ int wave5_vpu_dec_register_framebuffer(struct vpu_instance *inst, struct frame_b vpu_write_reg(inst->dev, W5_SET_FB_NUM, (start_no << 8) | end_no); for (i = 0; i < 8 && i < remain; i++) { - if (map_type == LINEAR_FRAME_MAP && p_dec_info->open_param.cbcr_order == - CBCR_ORDER_REVERSED) { - addr_y = fb_arr[i + start_no].buf_y; - addr_cb = fb_arr[i + start_no].buf_cr; - addr_cr = fb_arr[i + start_no].buf_cb; - } else { - addr_y = fb_arr[i + start_no].buf_y; - addr_cb = fb_arr[i + start_no].buf_cb; - addr_cr = fb_arr[i + start_no].buf_cr; - } + addr_y = fb_arr[i + start_no].buf_y; + addr_cb = fb_arr[i + start_no].buf_cb; + addr_cr = fb_arr[i + start_no].buf_cr; vpu_write_reg(inst->dev, W5_ADDR_LUMA_BASE0 + (i << 4), addr_y); vpu_write_reg(inst->dev, W5_ADDR_CB_BASE0 + (i << 4), addr_cb); if (map_type >= COMPRESSED_FRAME_MAP) { @@ -909,8 +821,7 @@ int wave5_vpu_dec_register_framebuffer(struct vpu_instance *inst, struct frame_b } remain -= i; - wave5_bit_issue_command(inst, W5_SET_FB); - ret = wave5_wait_vpu_busy(inst->dev, W5_VPU_BUSY_STATUS); + ret = send_firmware_command(inst, W5_SET_FB, false, NULL, NULL); if (ret) goto free_buffers; } @@ -937,93 +848,46 @@ free_mv_buffers: return ret; } -int wave5_vpu_decode(struct vpu_instance *inst, struct dec_param *option, u32 *fail_res) +int wave5_vpu_decode(struct vpu_instance *inst, u32 *fail_res) { - u32 mode_option = DEC_PIC_NORMAL, bs_option, reg_val; - u32 force_latency = 0; + u32 reg_val; struct dec_info *p_dec_info = &inst->codec_info->dec_info; - struct dec_open_param *p_open_param = &p_dec_info->open_param; int ret; - if (p_dec_info->thumbnail_mode) { - mode_option = DEC_PIC_W_THUMBNAIL; - } else if (option->skipframe_mode) { - switch (option->skipframe_mode) { - case WAVE_SKIPMODE_NON_IRAP: - mode_option = SKIP_NON_IRAP; - force_latency = 1; - break; - case WAVE_SKIPMODE_NON_REF: - mode_option = SKIP_NON_REF_PIC; - break; - default: - // skip mode off - break; - } - } - - // set disable reorder - if (!p_dec_info->reorder_enable) - force_latency = 1; - - /* set attributes of bitstream buffer controller */ - bs_option = 0; - switch (p_open_param->bitstream_mode) { - case BS_MODE_INTERRUPT: - bs_option = BSOPTION_ENABLE_EXPLICIT_END; - break; - case BS_MODE_PIC_END: - bs_option = BSOPTION_ENABLE_EXPLICIT_END; - break; - default: - return -EINVAL; - } - vpu_write_reg(inst->dev, W5_BS_RD_PTR, p_dec_info->stream_rd_ptr); vpu_write_reg(inst->dev, W5_BS_WR_PTR, p_dec_info->stream_wr_ptr); - bs_option = (p_dec_info->stream_endflag << 1) | BS_EXPLICIT_END_MODE_ON; - if (p_open_param->bitstream_mode == BS_MODE_PIC_END) - bs_option |= BIT(31); - if (inst->std == W_AV1_DEC) - bs_option |= ((p_open_param->av1_format) << 2); - vpu_write_reg(inst->dev, W5_BS_OPTION, bs_option); + + vpu_write_reg(inst->dev, W5_BS_OPTION, get_bitstream_options(p_dec_info)); /* secondary AXI */ - reg_val = p_dec_info->sec_axi_info.wave.use_bit_enable | - (p_dec_info->sec_axi_info.wave.use_ip_enable << 9) | - (p_dec_info->sec_axi_info.wave.use_lf_row_enable << 15); + reg_val = p_dec_info->sec_axi_info.use_bit_enable | + (p_dec_info->sec_axi_info.use_ip_enable << 9) | + (p_dec_info->sec_axi_info.use_lf_row_enable << 15); vpu_write_reg(inst->dev, W5_USE_SEC_AXI, reg_val); /* set attributes of user buffer */ vpu_write_reg(inst->dev, W5_CMD_DEC_USER_MASK, p_dec_info->user_data_enable); - vpu_write_reg(inst->dev, W5_COMMAND_OPTION, - ((option->disable_film_grain << 6) | (option->cra_as_bla_flag << 5) | - mode_option)); + vpu_write_reg(inst->dev, W5_COMMAND_OPTION, DEC_PIC_NORMAL); vpu_write_reg(inst->dev, W5_CMD_DEC_TEMPORAL_ID_PLUS1, (p_dec_info->target_spatial_id << 9) | (p_dec_info->temp_id_select_mode << 8) | p_dec_info->target_temp_id); vpu_write_reg(inst->dev, W5_CMD_SEQ_CHANGE_ENABLE_FLAG, p_dec_info->seq_change_mask); - vpu_write_reg(inst->dev, W5_CMD_DEC_FORCE_FB_LATENCY_PLUS1, force_latency); + /* When reordering is disabled we force the latency of the framebuffers */ + vpu_write_reg(inst->dev, W5_CMD_DEC_FORCE_FB_LATENCY_PLUS1, !p_dec_info->reorder_enable); - wave5_bit_issue_command(inst, W5_DEC_PIC); - // check QUEUE_DONE - ret = wave5_wait_vpu_busy(inst->dev, W5_VPU_BUSY_STATUS); - if (ret) { - dev_warn(inst->dev->dev, "command: 'W5_DEC_PIC', timed out\n"); - return -ETIMEDOUT; - } - - reg_val = vpu_read_reg(inst->dev, W5_RET_QUEUE_STATUS); + ret = send_firmware_command(inst, W5_DEC_ENC_PIC, true, ®_val, fail_res); + if (ret == -ETIMEDOUT) + return ret; p_dec_info->instance_queue_count = (reg_val >> 16) & 0xff; p_dec_info->report_queue_count = (reg_val & QUEUE_REPORT_MASK); - // Check if we were able to add a command into the VCPU QUEUE - if (!vpu_read_reg(inst->dev, W5_RET_SUCCESS)) { - *fail_res = vpu_read_reg(inst->dev, W5_RET_FAIL_REASON); - wave5_print_reg_err(inst->dev, *fail_res); - return -EIO; - } + + dev_dbg(inst->dev->dev, "%s: dec pic sent (queue %u : %u)\n", __func__, + p_dec_info->instance_queue_count, p_dec_info->report_queue_count); + + if (ret) + return ret; return 0; } @@ -1037,41 +901,26 @@ int wave5_vpu_dec_get_result(struct vpu_instance *inst, struct dec_output_info * vpu_write_reg(inst->dev, W5_CMD_DEC_ADDR_REPORT_BASE, p_dec_info->user_data_buf_addr); vpu_write_reg(inst->dev, W5_CMD_DEC_REPORT_SIZE, p_dec_info->user_data_buf_size); - vpu_write_reg(inst->dev, W5_CMD_DEC_REPORT_PARAM, - VPU_USER_DATA_ENDIAN & VDI_128BIT_ENDIAN_MASK); - - // send QUERY cmd - ret = wave5_send_query(inst, GET_RESULT); - if (ret) { - if (ret == -EIO) { - reg_val = vpu_read_reg(inst->dev, W5_RET_FAIL_REASON); - wave5_print_reg_err(inst->dev, reg_val); - } + vpu_write_reg(inst->dev, W5_CMD_DEC_REPORT_PARAM, REPORT_PARAM_ENDIANNESS_BIG_ENDIAN); + /* send QUERY cmd */ + ret = wave5_send_query(vpu_dev, inst, GET_RESULT); + if (ret) return ret; - } - - dev_dbg(inst->dev->dev, "%s: dec pic complete\n", __func__); reg_val = vpu_read_reg(inst->dev, W5_RET_QUEUE_STATUS); p_dec_info->instance_queue_count = (reg_val >> 16) & 0xff; p_dec_info->report_queue_count = (reg_val & QUEUE_REPORT_MASK); + dev_dbg(inst->dev->dev, "%s: dec pic complete (queue %u : %u)\n", __func__, + p_dec_info->instance_queue_count, p_dec_info->report_queue_count); + reg_val = vpu_read_reg(inst->dev, W5_RET_DEC_PIC_TYPE); nal_unit_type = (reg_val >> 4) & 0x3f; - if (inst->std == W_VP9_DEC) { - if (reg_val & 0x01) - result->pic_type = PIC_TYPE_I; - else if (reg_val & 0x02) - result->pic_type = PIC_TYPE_P; - else if (reg_val & 0x04) - result->pic_type = PIC_TYPE_REPEAT; - else - result->pic_type = PIC_TYPE_MAX; - } else if (inst->std == W_HEVC_DEC) { + if (inst->std == W_HEVC_DEC) { if (reg_val & 0x04) result->pic_type = PIC_TYPE_B; else if (reg_val & 0x02) @@ -1094,51 +943,6 @@ int wave5_vpu_dec_get_result(struct vpu_instance *inst, struct dec_output_info * result->pic_type = PIC_TYPE_MAX; if (nal_unit_type == 5 && result->pic_type == PIC_TYPE_I) result->pic_type = PIC_TYPE_IDR; - } else if (inst->std == W_AV1_DEC) { - switch (reg_val & 0x07) { - case 0: - result->pic_type = PIC_TYPE_KEY; - break; - case 1: - result->pic_type = PIC_TYPE_INTER; - break; - case 2: - result->pic_type = PIC_TYPE_AV1_INTRA; - break; - case 3: - result->pic_type = PIC_TYPE_AV1_SWITCH; - break; - default: - result->pic_type = PIC_TYPE_MAX; - break; - } - } else { // AVS2 - switch (reg_val & 0x07) { - case 0: - result->pic_type = PIC_TYPE_I; - break; - case 1: - result->pic_type = PIC_TYPE_P; - break; - case 2: - result->pic_type = PIC_TYPE_B; - break; - case 3: - result->pic_type = PIC_TYPE_AVS2_F; - break; - case 4: - result->pic_type = PIC_TYPE_AVS2_S; - break; - case 5: - result->pic_type = PIC_TYPE_AVS2_G; - break; - case 6: - result->pic_type = PIC_TYPE_AVS2_GB; - break; - default: - result->pic_type = PIC_TYPE_MAX; - break; - } } index = vpu_read_reg(inst->dev, W5_RET_DEC_DISPLAY_INDEX); result->index_frame_display = index; @@ -1149,23 +953,7 @@ int wave5_vpu_dec_get_result(struct vpu_instance *inst, struct dec_output_info * sub_layer_info = vpu_read_reg(inst->dev, W5_RET_DEC_SUB_LAYER_INFO); result->temporal_id = sub_layer_info & 0x7; - if (inst->std == W_HEVC_DEC) { - result->decoded_poc = -1; - if (result->index_frame_decoded >= 0 || - result->index_frame_decoded == DECODED_IDX_FLAG_SKIP) - result->decoded_poc = vpu_read_reg(inst->dev, W5_RET_DEC_PIC_POC); - } else if (inst->std == W_AVS2_DEC) { - result->avs2_info.decoded_poi = -1; - result->avs2_info.display_poi = -1; - if (result->index_frame_decoded >= 0) - result->avs2_info.decoded_poi = - vpu_read_reg(inst->dev, W5_RET_DEC_PIC_POC); - } else if (inst->std == W_AVC_DEC) { - result->decoded_poc = -1; - if (result->index_frame_decoded >= 0 || - result->index_frame_decoded == DECODED_IDX_FLAG_SKIP) - result->decoded_poc = vpu_read_reg(inst->dev, W5_RET_DEC_PIC_POC); - } else if (inst->std == W_AV1_DEC) { + if (inst->std == W_HEVC_DEC || inst->std == W_AVC_DEC) { result->decoded_poc = -1; if (result->index_frame_decoded >= 0 || result->index_frame_decoded == DECODED_IDX_FLAG_SKIP) @@ -1203,7 +991,7 @@ int wave5_vpu_dec_get_result(struct vpu_instance *inst, struct dec_output_info * p_dec_info->cycle_per_tick; } - // no remaining command. reset frame cycle. + /* no remaining command. reset frame cycle. */ if (p_dec_info->instance_queue_count == 0 && p_dec_info->report_queue_count == 0) p_dec_info->first_cycle_check = false; @@ -1215,7 +1003,7 @@ int wave5_vpu_re_init(struct device *dev, u8 *fw, size_t size) struct vpu_buf *common_vb; dma_addr_t code_base, temp_base; dma_addr_t old_code_base, temp_size; - u32 code_size; + u32 code_size, reason_code; u32 reg_val; struct vpu_device *vpu_dev = dev_get_drvdata(dev); @@ -1233,10 +1021,8 @@ int wave5_vpu_re_init(struct device *dev, u8 *fw, size_t size) if (old_code_base != code_base + W5_REMAP_INDEX1 * W5_REMAP_MAX_SIZE) { int ret; - struct dma_vpu_buf *sram_vb; - ret = wave5_vdi_write_memory(vpu_dev, common_vb, 0, fw, size, - VDI_128BIT_LITTLE_ENDIAN); + ret = wave5_vdi_write_memory(vpu_dev, common_vb, 0, fw, size); if (ret < 0) { dev_err(vpu_dev->dev, "VPU init, Writing firmware to common buffer, fail: %d\n", ret); @@ -1260,31 +1046,24 @@ int wave5_vpu_re_init(struct device *dev, u8 *fw, size_t size) vpu_write_reg(vpu_dev, W5_ADDR_TEMP_BASE, temp_base); vpu_write_reg(vpu_dev, W5_TEMP_SIZE, temp_size); + /* These register must be reset explicitly */ vpu_write_reg(vpu_dev, W5_HW_OPTION, 0); + wave5_fio_writel(vpu_dev, W5_BACKBONE_PROC_EXT_ADDR, 0); + wave5_fio_writel(vpu_dev, W5_BACKBONE_AXI_PARAM, 0); + vpu_write_reg(vpu_dev, W5_SEC_AXI_PARAM, 0); - reg_val = (WAVE5_PROC_AXI_EXT_ADDR & 0xFFFF); - wave5_fio_writel(vpu_dev, W5_BACKBONE_PROC_EXT_ADDR, reg_val); - reg_val = ((WAVE5_PROC_AXI_AXPROT & 0x7) << 4) | - (WAVE5_PROC_AXI_AXCACHE & 0xF); - wave5_fio_writel(vpu_dev, W5_BACKBONE_AXI_PARAM, reg_val); - reg_val = ((WAVE5_SEC_AXI_AXPROT & 0x7) << 20) | - ((WAVE5_SEC_AXI_AXCACHE & 0xF) << 16) | - (WAVE5_SEC_AXI_EXT_ADDR & 0xFFFF); - vpu_write_reg(vpu_dev, W5_SEC_AXI_PARAM, reg_val); - - /* interrupt */ - // encoder + /* Encoder interrupt */ reg_val = BIT(INT_WAVE5_ENC_SET_PARAM); reg_val |= BIT(INT_WAVE5_ENC_PIC); reg_val |= BIT(INT_WAVE5_BSBUF_FULL); - // decoder + /* Decoder interrupt */ reg_val |= BIT(INT_WAVE5_INIT_SEQ); reg_val |= BIT(INT_WAVE5_DEC_PIC); reg_val |= BIT(INT_WAVE5_BSBUF_EMPTY); vpu_write_reg(vpu_dev, W5_VPU_VINT_ENABLE, reg_val); reg_val = vpu_read_reg(vpu_dev, W5_VPU_RET_VPU_CONFIG0); - if ((reg_val >> 16) & 1) { + if (FIELD_GET(FEATURE_BACKBONE, reg_val)) { reg_val = ((WAVE5_PROC_AXI_ID << 28) | (WAVE5_PRP_AXI_ID << 24) | (WAVE5_FBD_Y_AXI_ID << 20) | @@ -1296,10 +1075,6 @@ int wave5_vpu_re_init(struct device *dev, u8 *fw, size_t size) wave5_fio_writel(vpu_dev, W5_BACKBONE_PROG_AXI_ID, reg_val); } - sram_vb = &vpu_dev->sram_buf; - - vpu_write_reg(vpu_dev, W5_ADDR_SEC_AXI, sram_vb->daddr); - vpu_write_reg(vpu_dev, W5_SEC_AXI_SIZE, sram_vb->size); vpu_write_reg(vpu_dev, W5_VPU_BUSY_STATUS, 1); vpu_write_reg(vpu_dev, W5_COMMAND, W5_INIT_VPU); vpu_write_reg(vpu_dev, W5_VPU_REMAP_CORE_START, 1); @@ -1310,13 +1085,9 @@ int wave5_vpu_re_init(struct device *dev, u8 *fw, size_t size) return ret; } - reg_val = vpu_read_reg(vpu_dev, W5_RET_SUCCESS); - if (!reg_val) { - u32 reason_code = vpu_read_reg(vpu_dev, W5_RET_FAIL_REASON); - - wave5_print_reg_err(vpu_dev, reason_code); - return -EIO; - } + ret = wave5_vpu_firmware_command_queue_error_check(vpu_dev, &reason_code); + if (ret) + return ret; } return setup_wave5_properties(dev); @@ -1328,7 +1099,7 @@ static int wave5_vpu_sleep_wake(struct device *dev, bool i_sleep_wake, const uin u32 reg_val; struct vpu_buf *common_vb; dma_addr_t code_base; - u32 code_size; + u32 code_size, reason_code; struct vpu_device *vpu_dev = dev_get_drvdata(dev); int ret; @@ -1340,7 +1111,7 @@ static int wave5_vpu_sleep_wake(struct device *dev, bool i_sleep_wake, const uin /* * Declare who has ownership for the host interface access * 1 = VPU - * 0 = Host processer + * 0 = Host processor */ vpu_write_reg(vpu_dev, W5_VPU_BUSY_STATUS, 1); vpu_write_reg(vpu_dev, W5_COMMAND, W5_SLEEP_VPU); @@ -1351,12 +1122,9 @@ static int wave5_vpu_sleep_wake(struct device *dev, bool i_sleep_wake, const uin if (ret) return ret; - if (!vpu_read_reg(vpu_dev, W5_RET_SUCCESS)) { - u32 reason = vpu_read_reg(vpu_dev, W5_RET_FAIL_REASON); - - wave5_print_reg_err(vpu_dev, reason); - return -EIO; - } + ret = wave5_vpu_firmware_command_queue_error_check(vpu_dev, &reason_code); + if (ret) + return ret; } else { /* restore */ common_vb = &vpu_dev->common_mem; @@ -1378,31 +1146,24 @@ static int wave5_vpu_sleep_wake(struct device *dev, bool i_sleep_wake, const uin vpu_write_reg(vpu_dev, W5_CODE_SIZE, code_size); vpu_write_reg(vpu_dev, W5_CODE_PARAM, (WAVE5_UPPER_PROC_AXI_ID << 4) | 0); + /* These register must be reset explicitly */ vpu_write_reg(vpu_dev, W5_HW_OPTION, 0); + wave5_fio_writel(vpu_dev, W5_BACKBONE_PROC_EXT_ADDR, 0); + wave5_fio_writel(vpu_dev, W5_BACKBONE_AXI_PARAM, 0); + vpu_write_reg(vpu_dev, W5_SEC_AXI_PARAM, 0); - reg_val = (WAVE5_PROC_AXI_EXT_ADDR & 0xFFFF); - wave5_fio_writel(vpu_dev, W5_BACKBONE_PROC_EXT_ADDR, reg_val); - reg_val = ((WAVE5_PROC_AXI_AXPROT & 0x7) << 4) | - (WAVE5_PROC_AXI_AXCACHE & 0xF); - wave5_fio_writel(vpu_dev, W5_BACKBONE_AXI_PARAM, reg_val); - reg_val = ((WAVE5_SEC_AXI_AXPROT & 0x7) << 20) | - ((WAVE5_SEC_AXI_AXCACHE & 0xF) << 16) | - (WAVE5_SEC_AXI_EXT_ADDR & 0xFFFF); - vpu_write_reg(vpu_dev, W5_SEC_AXI_PARAM, reg_val); - - /* interrupt */ - // encoder + /* Encoder interrupt */ reg_val = BIT(INT_WAVE5_ENC_SET_PARAM); reg_val |= BIT(INT_WAVE5_ENC_PIC); reg_val |= BIT(INT_WAVE5_BSBUF_FULL); - // decoder + /* Decoder interrupt */ reg_val |= BIT(INT_WAVE5_INIT_SEQ); reg_val |= BIT(INT_WAVE5_DEC_PIC); reg_val |= BIT(INT_WAVE5_BSBUF_EMPTY); vpu_write_reg(vpu_dev, W5_VPU_VINT_ENABLE, reg_val); reg_val = vpu_read_reg(vpu_dev, W5_VPU_RET_VPU_CONFIG0); - if ((reg_val >> 16) & 1) { + if (FIELD_GET(FEATURE_BACKBONE, reg_val)) { reg_val = ((WAVE5_PROC_AXI_ID << 28) | (WAVE5_PRP_AXI_ID << 24) | (WAVE5_FBD_Y_AXI_ID << 20) | @@ -1425,13 +1186,7 @@ static int wave5_vpu_sleep_wake(struct device *dev, bool i_sleep_wake, const uin return ret; } - reg_val = vpu_read_reg(vpu_dev, W5_RET_SUCCESS); - if (!reg_val) { - u32 reason_code = vpu_read_reg(vpu_dev, W5_RET_FAIL_REASON); - - wave5_print_reg_err(vpu_dev, reason_code); - return -EIO; - } + return wave5_vpu_firmware_command_queue_error_check(vpu_dev, &reason_code); } return 0; @@ -1443,7 +1198,7 @@ int wave5_vpu_reset(struct device *dev, enum sw_reset_mode reset_mode) int ret = 0; struct vpu_device *vpu_dev = dev_get_drvdata(dev); struct vpu_attr *p_attr = &vpu_dev->attr; - // VPU doesn't send response. force to set BUSY flag to 0. + /* VPU doesn't send response. force to set BUSY flag to 0. */ vpu_write_reg(vpu_dev, W5_VPU_BUSY_STATUS, 0); if (reset_mode == SW_RESET_SAFETY) { @@ -1460,39 +1215,16 @@ int wave5_vpu_reset(struct device *dev, enum sw_reset_mode reset_mode) if ((val >> 28) & 0x1) p_attr->support_vcpu_backbone = true; - val = vpu_read_reg(vpu_dev, W5_VPU_RET_VPU_CONFIG1); - if ((val >> 26) & 0x1) - p_attr->support_dual_core = true; - - // waiting for completion of bus transaction + /* waiting for completion of bus transaction */ if (p_attr->support_backbone) { dev_dbg(dev, "%s: backbone supported\n", __func__); - if (p_attr->support_dual_core) { - // check CORE0 - wave5_fio_writel(vpu_dev, W5_BACKBONE_BUS_CTRL_VCORE0, 0x7); - - ret = wave5_wait_bus_busy(vpu_dev, W5_BACKBONE_BUS_STATUS_VCORE0); - if (ret) { - wave5_fio_writel(vpu_dev, W5_BACKBONE_BUS_CTRL_VCORE0, 0x00); - return ret; - } - - // check CORE1 - wave5_fio_writel(vpu_dev, W5_BACKBONE_BUS_CTRL_VCORE1, 0x7); - - ret = wave5_wait_bus_busy(vpu_dev, W5_BACKBONE_BUS_STATUS_VCORE1); - if (ret) { - wave5_fio_writel(vpu_dev, W5_BACKBONE_BUS_CTRL_VCORE1, 0x00); - return ret; - } - - } else if (p_attr->support_vcore_backbone) { + if (p_attr->support_vcore_backbone) { if (p_attr->support_vcpu_backbone) { - // step1 : disable request + /* step1 : disable request */ wave5_fio_writel(vpu_dev, W5_BACKBONE_BUS_CTRL_VCPU, 0xFF); - // step2 : waiting for completion of bus transaction + /* step2 : waiting for completion of bus transaction */ ret = wave5_wait_vcpu_bus_busy(vpu_dev, W5_BACKBONE_BUS_STATUS_VCPU); if (ret) { @@ -1500,19 +1232,19 @@ int wave5_vpu_reset(struct device *dev, enum sw_reset_mode reset_mode) return ret; } } - // step1 : disable request + /* step1 : disable request */ wave5_fio_writel(vpu_dev, W5_BACKBONE_BUS_CTRL_VCORE0, 0x7); - // step2 : waiting for completion of bus transaction + /* step2 : waiting for completion of bus transaction */ if (wave5_wait_bus_busy(vpu_dev, W5_BACKBONE_BUS_STATUS_VCORE0)) { wave5_fio_writel(vpu_dev, W5_BACKBONE_BUS_CTRL_VCORE0, 0x00); return -EBUSY; } } else { - // step1 : disable request + /* step1 : disable request */ wave5_fio_writel(vpu_dev, W5_COMBINED_BACKBONE_BUS_CTRL, 0x7); - // step2 : waiting for completion of bus transaction + /* step2 : waiting for completion of bus transaction */ if (wave5_wait_bus_busy(vpu_dev, W5_COMBINED_BACKBONE_BUS_STATUS)) { wave5_fio_writel(vpu_dev, W5_COMBINED_BACKBONE_BUS_CTRL, 0x00); return -EBUSY; @@ -1520,10 +1252,10 @@ int wave5_vpu_reset(struct device *dev, enum sw_reset_mode reset_mode) } } else { dev_dbg(dev, "%s: backbone NOT supported\n", __func__); - // step1 : disable request + /* step1 : disable request */ wave5_fio_writel(vpu_dev, W5_GDI_BUS_CTRL, 0x100); - // step2 : waiting for completion of bus transaction + /* step2 : waiting for completion of bus transaction */ ret = wave5_wait_bus_busy(vpu_dev, W5_GDI_BUS_STATUS); if (ret) { wave5_fio_writel(vpu_dev, W5_GDI_BUS_CTRL, 0x00); @@ -1551,12 +1283,9 @@ int wave5_vpu_reset(struct device *dev, enum sw_reset_mode reset_mode) } vpu_write_reg(vpu_dev, W5_VPU_RESET_REQ, 0); } - // step3 : must clear GDI_BUS_CTRL after done SW_RESET + /* step3 : must clear GDI_BUS_CTRL after done SW_RESET */ if (p_attr->support_backbone) { - if (p_attr->support_dual_core) { - wave5_fio_writel(vpu_dev, W5_BACKBONE_BUS_CTRL_VCORE0, 0x00); - wave5_fio_writel(vpu_dev, W5_BACKBONE_BUS_CTRL_VCORE1, 0x00); - } else if (p_attr->support_vcore_backbone) { + if (p_attr->support_vcore_backbone) { if (p_attr->support_vcpu_backbone) wave5_fio_writel(vpu_dev, W5_BACKBONE_BUS_CTRL_VCPU, 0x00); wave5_fio_writel(vpu_dev, W5_BACKBONE_BUS_CTRL_VCORE0, 0x00); @@ -1574,47 +1303,18 @@ int wave5_vpu_reset(struct device *dev, enum sw_reset_mode reset_mode) int wave5_vpu_dec_finish_seq(struct vpu_instance *inst, u32 *fail_res) { - int ret; - - wave5_bit_issue_command(inst, W5_DESTROY_INSTANCE); - ret = wave5_wait_vpu_busy(inst->dev, W5_VPU_BUSY_STATUS); - if (ret) - return -ETIMEDOUT; - - if (!vpu_read_reg(inst->dev, W5_RET_SUCCESS)) { - *fail_res = vpu_read_reg(inst->dev, W5_RET_FAIL_REASON); - wave5_print_reg_err(inst->dev, *fail_res); - return -EIO; - } - - return 0; + return send_firmware_command(inst, W5_DESTROY_INSTANCE, true, NULL, fail_res); } int wave5_vpu_dec_set_bitstream_flag(struct vpu_instance *inst, bool eos) { struct dec_info *p_dec_info = &inst->codec_info->dec_info; - enum bit_stream_mode bs_mode = (enum bit_stream_mode)p_dec_info->open_param.bitstream_mode; p_dec_info->stream_endflag = eos ? 1 : 0; + vpu_write_reg(inst->dev, W5_BS_OPTION, get_bitstream_options(p_dec_info)); + vpu_write_reg(inst->dev, W5_BS_WR_PTR, p_dec_info->stream_wr_ptr); - if (bs_mode == BS_MODE_INTERRUPT) { - int ret; - - vpu_write_reg(inst->dev, W5_BS_OPTION, (p_dec_info->stream_endflag << 1) | - p_dec_info->stream_endflag); - vpu_write_reg(inst->dev, W5_BS_WR_PTR, p_dec_info->stream_wr_ptr); - - wave5_bit_issue_command(inst, W5_UPDATE_BS); - ret = wave5_wait_vpu_busy(inst->dev, - W5_VPU_BUSY_STATUS); - if (ret) - return ret; - - if (!vpu_read_reg(inst->dev, W5_RET_SUCCESS)) - return -EIO; - } - - return 0; + return send_firmware_command(inst, W5_UPDATE_BS, true, NULL, NULL); } int wave5_dec_clr_disp_flag(struct vpu_instance *inst, unsigned int index) @@ -1624,16 +1324,10 @@ int wave5_dec_clr_disp_flag(struct vpu_instance *inst, unsigned int index) vpu_write_reg(inst->dev, W5_CMD_DEC_CLR_DISP_IDC, BIT(index)); vpu_write_reg(inst->dev, W5_CMD_DEC_SET_DISP_IDC, 0); - ret = wave5_send_query(inst, UPDATE_DISP_FLAG); - - if (ret) { - if (ret == -EIO) { - u32 reg_val = vpu_read_reg(inst->dev, W5_RET_FAIL_REASON); - wave5_print_reg_err(inst->dev, reg_val); - } + ret = wave5_send_query(inst->dev, inst, UPDATE_DISP_FLAG); + if (ret) return ret; - } p_dec_info->frame_display_flag = vpu_read_reg(inst->dev, W5_RET_DEC_DISP_IDC); @@ -1646,16 +1340,10 @@ int wave5_dec_set_disp_flag(struct vpu_instance *inst, unsigned int index) vpu_write_reg(inst->dev, W5_CMD_DEC_CLR_DISP_IDC, 0); vpu_write_reg(inst->dev, W5_CMD_DEC_SET_DISP_IDC, BIT(index)); - ret = wave5_send_query(inst, UPDATE_DISP_FLAG); - if (ret) { - if (ret == -EIO) { - u32 reg_val = vpu_read_reg(inst->dev, W5_RET_FAIL_REASON); - - wave5_print_reg_err(inst->dev, reg_val); - } + ret = wave5_send_query(inst->dev, inst, UPDATE_DISP_FLAG); + if (ret) return ret; - } return 0; } @@ -1671,12 +1359,11 @@ int wave5_vpu_clear_interrupt(struct vpu_instance *inst, u32 flags) return 0; } -dma_addr_t wave5_vpu_dec_get_rd_ptr(struct vpu_instance *inst) +dma_addr_t wave5_dec_get_rd_ptr(struct vpu_instance *inst) { int ret; - ret = wave5_send_query(inst, GET_BS_RD_PTR); - + ret = wave5_send_query(inst->dev, inst, GET_BS_RD_PTR); if (ret) return inst->codec_info->dec_info.stream_rd_ptr; @@ -1689,7 +1376,7 @@ int wave5_dec_set_rd_ptr(struct vpu_instance *inst, dma_addr_t addr) vpu_write_reg(inst->dev, W5_RET_QUERY_DEC_SET_BS_RD_PTR, addr); - ret = wave5_send_query(inst, SET_BS_RD_PTR); + ret = wave5_send_query(inst->dev, inst, SET_BS_RD_PTR); return ret; } @@ -1704,20 +1391,17 @@ int wave5_vpu_build_up_enc_param(struct device *dev, struct vpu_instance *inst, int ret; struct enc_info *p_enc_info = &inst->codec_info->enc_info; u32 reg_val; - struct dma_vpu_buf *sram_vb; - u32 bs_endian; struct vpu_device *vpu_dev = dev_get_drvdata(dev); dma_addr_t buffer_addr; size_t buffer_size; p_enc_info->cycle_per_tick = 256; - sram_vb = &vpu_dev->sram_buf; - p_enc_info->sec_axi_info.buf_base = sram_vb->daddr; - p_enc_info->sec_axi_info.buf_size = sram_vb->size; - - if (vpu_dev->product == PRODUCT_ID_521) - p_enc_info->vb_work.size = WAVE521ENC_WORKBUF_SIZE; + if (vpu_dev->sram_buf.size) { + p_enc_info->sec_axi_info.use_enc_rdo_enable = 1; + p_enc_info->sec_axi_info.use_enc_lf_enable = 1; + } + p_enc_info->vb_work.size = WAVE521ENC_WORKBUF_SIZE; ret = wave5_vdi_allocate_dma_memory(vpu_dev, &p_enc_info->vb_work); if (ret) { memset(&p_enc_info->vb_work, 0, sizeof(p_enc_info->vb_work)); @@ -1729,43 +1413,24 @@ int wave5_vpu_build_up_enc_param(struct device *dev, struct vpu_instance *inst, vpu_write_reg(inst->dev, W5_ADDR_WORK_BASE, p_enc_info->vb_work.daddr); vpu_write_reg(inst->dev, W5_WORK_SIZE, p_enc_info->vb_work.size); - reg_val = wave5_vdi_convert_endian(vpu_dev, open_param->stream_endian); - bs_endian = (~reg_val & VDI_128BIT_ENDIAN_MASK); + vpu_write_reg(inst->dev, W5_CMD_ADDR_SEC_AXI, vpu_dev->sram_buf.daddr); + vpu_write_reg(inst->dev, W5_CMD_SEC_AXI_SIZE, vpu_dev->sram_buf.size); - reg_val = (open_param->line_buf_int_en << 6) | bs_endian; + reg_val = (open_param->line_buf_int_en << 6) | BITSTREAM_ENDIANNESS_BIG_ENDIAN; vpu_write_reg(inst->dev, W5_CMD_BS_PARAM, reg_val); - vpu_write_reg(inst->dev, W5_CMD_EXT_ADDR, (open_param->pri_axprot << 20) | - (open_param->pri_axcache << 16) | open_param->pri_ext_addr); + vpu_write_reg(inst->dev, W5_CMD_EXT_ADDR, 0); vpu_write_reg(inst->dev, W5_CMD_NUM_CQ_DEPTH_M1, (COMMAND_QUEUE_DEPTH - 1)); - reg_val = 0; - if (vpu_dev->product == PRODUCT_ID_521) - reg_val |= (open_param->sub_frame_sync_enable | - open_param->sub_frame_sync_mode << 1); - vpu_write_reg(inst->dev, W5_CMD_ENC_SRC_OPTIONS, reg_val); - + /* This register must be reset explicitly */ + vpu_write_reg(inst->dev, W5_CMD_ENC_SRC_OPTIONS, 0); vpu_write_reg(inst->dev, W5_CMD_ENC_VCORE_INFO, 1); - wave5_bit_issue_command(inst, W5_CREATE_INSTANCE); - // check QUEUE_DONE - ret = wave5_wait_vpu_busy(inst->dev, W5_VPU_BUSY_STATUS); - if (ret) { - dev_warn(inst->dev->dev, "command: 'W5_CREATE_INSTANCE' timed out\n"); + ret = send_firmware_command(inst, W5_CREATE_INSTANCE, true, NULL, NULL); + if (ret) goto free_vb_work; - } - - // Check if we were able to add the parameters into the VCPU QUEUE - if (!vpu_read_reg(inst->dev, W5_RET_SUCCESS)) { - reg_val = vpu_read_reg(inst->dev, W5_RET_FAIL_REASON); - wave5_print_reg_err(inst->dev, reg_val); - ret = -EIO; - goto free_vb_work; - } buffer_addr = open_param->bitstream_buffer; buffer_size = open_param->bitstream_buffer_size; - p_enc_info->sub_frame_sync_config.sub_frame_sync_mode = open_param->sub_frame_sync_mode; - p_enc_info->sub_frame_sync_config.sub_frame_sync_on = open_param->sub_frame_sync_enable; p_enc_info->stream_rd_ptr = buffer_addr; p_enc_info->stream_wr_ptr = buffer_addr; p_enc_info->line_buf_int_en = open_param->line_buf_int_en; @@ -1778,7 +1443,8 @@ int wave5_vpu_build_up_enc_param(struct device *dev, struct vpu_instance *inst, return 0; free_vb_work: - wave5_vdi_free_dma_memory(vpu_dev, &p_enc_info->vb_work); + if (wave5_vdi_free_dma_memory(vpu_dev, &p_enc_info->vb_work)) + memset(&p_enc_info->vb_work, 0, sizeof(p_enc_info->vb_work)); return ret; } @@ -1789,10 +1455,10 @@ static void wave5_set_enc_crop_info(u32 codec, struct enc_wave_param *param, int int aligned_height = (codec == W_HEVC_ENC) ? ALIGN(src_height, 32) : ALIGN(src_height, 16); int pad_right, pad_bot; int crop_right, crop_left, crop_top, crop_bot; - int prp_mode = rot_mode >> 1; // remove prp_enable bit + int prp_mode = rot_mode >> 1; /* remove prp_enable bit */ if (codec == W_HEVC_ENC && - (!rot_mode || prp_mode == 14)) // prp_mode 14 : hor_mir && ver_mir && rot_180 + (!rot_mode || prp_mode == 14)) /* prp_mode 14 : hor_mir && ver_mir && rot_180 */ return; pad_right = aligned_width - src_width; @@ -1816,37 +1482,56 @@ static void wave5_set_enc_crop_info(u32 codec, struct enc_wave_param *param, int param->conf_win_bot = crop_bot; param->conf_win_right = crop_right; - if (prp_mode == 1 || prp_mode == 15) { + switch (prp_mode) { + case 0: + return; + case 1: + case 15: param->conf_win_top = crop_right; param->conf_win_left = crop_top; param->conf_win_bot = crop_left; param->conf_win_right = crop_bot; - } else if (prp_mode == 2 || prp_mode == 12) { + break; + case 2: + case 12: param->conf_win_top = crop_bot; param->conf_win_left = crop_right; param->conf_win_bot = crop_top; param->conf_win_right = crop_left; - } else if (prp_mode == 3 || prp_mode == 13) { + break; + case 3: + case 13: param->conf_win_top = crop_left; param->conf_win_left = crop_bot; param->conf_win_bot = crop_right; param->conf_win_right = crop_top; - } else if (prp_mode == 4 || prp_mode == 10) { + break; + case 4: + case 10: param->conf_win_top = crop_bot; param->conf_win_bot = crop_top; - } else if (prp_mode == 8 || prp_mode == 6) { + break; + case 8: + case 6: param->conf_win_left = crop_right; param->conf_win_right = crop_left; - } else if (prp_mode == 5 || prp_mode == 11) { + break; + case 5: + case 11: param->conf_win_top = crop_left; param->conf_win_left = crop_top; param->conf_win_bot = crop_right; param->conf_win_right = crop_bot; - } else if (prp_mode == 7 || prp_mode == 9) { + break; + case 7: + case 9: param->conf_win_top = crop_right; param->conf_win_left = crop_bot; param->conf_win_bot = crop_left; param->conf_win_right = crop_top; + break; + default: + WARN(1, "Invalid prp_mode: %d, must be in range of 1 - 15\n", prp_mode); } } @@ -1856,53 +1541,11 @@ int wave5_vpu_enc_init_seq(struct vpu_instance *inst) struct enc_info *p_enc_info = &inst->codec_info->enc_info; struct enc_open_param *p_open_param = &p_enc_info->open_param; struct enc_wave_param *p_param = &p_open_param->wave_param; - int ret; - - if (inst->dev->product != PRODUCT_ID_521) - return -EINVAL; - /*==============================================*/ - /* OPT_CUSTOM_GOP */ - /*==============================================*/ /* - * SET_PARAM + CUSTOM_GOP - * only when gop_preset_idx == custom_gop, custom_gop related registers should be set + * OPT_COMMON: + * the last SET_PARAM command should be called with OPT_COMMON */ - if (p_param->gop_preset_idx == PRESET_IDX_CUSTOM_GOP) { - int i = 0, j = 0; - - vpu_write_reg(inst->dev, W5_CMD_ENC_CUSTOM_GOP_PARAM, - p_param->gop_param.custom_gop_size); - for (i = 0; i < p_param->gop_param.custom_gop_size; i++) { - vpu_write_reg(inst->dev, W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_0 + (i * 4), - p_param->gop_param.pic_param[i].pic_type | - (p_param->gop_param.pic_param[i].poc_offset << 2) | - (p_param->gop_param.pic_param[i].pic_qp << 6) | - (p_param->gop_param.pic_param[i].use_multi_ref_p << 13) | - ((p_param->gop_param.pic_param[i].ref_poc_l0 & 0x1F) << 14) | - ((p_param->gop_param.pic_param[i].ref_poc_l1 & 0x1F) << 19) | - (p_param->gop_param.pic_param[i].temporal_id << 24)); - } - - for (j = i; j < MAX_GOP_NUM; j++) - vpu_write_reg(inst->dev, - W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_0 + (j * 4), 0); - - vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_SET_PARAM_OPTION, OPT_CUSTOM_GOP); - wave5_bit_issue_command(inst, W5_ENC_SET_PARAM); - - ret = wave5_wait_vpu_busy(inst->dev, W5_VPU_BUSY_STATUS); - if (ret) { - dev_warn(inst->dev->dev, "command: 'W5_ENC_SET_PARAM', timed out op=0x%x\n", - OPT_CUSTOM_GOP); - return ret; - } - } - - /*======================================================================*/ - /* OPT_COMMON: */ - /* the last SET_PARAM command should be called with OPT_COMMON */ - /*======================================================================*/ rot_mir_mode = 0; if (p_enc_info->rotation_enable) { switch (p_enc_info->rotation_angle) { @@ -1947,37 +1590,21 @@ int wave5_vpu_enc_init_seq(struct vpu_instance *inst) | p_open_param->pic_width); vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_MAP_ENDIAN, VDI_LITTLE_ENDIAN); - if (inst->std == W_AVC_ENC) { - reg_val = p_param->profile | (p_param->level << 3) | - (p_param->internal_bit_depth << 14) | (p_param->use_long_term << 21); - if (p_param->scaling_list_enable == 2) { - reg_val |= BIT(22) | BIT(23); // [23]=USE_DEFAULT_SCALING_LIST - } else { // 0 or 1 - reg_val |= (p_param->scaling_list_enable << 22); - } - } else { // HEVC enc - reg_val = p_param->profile | - (p_param->level << 3) | - (p_param->tier << 12) | - (p_param->internal_bit_depth << 14) | - (p_param->use_long_term << 21) | + reg_val = p_param->profile | + (p_param->level << 3) | + (p_param->internal_bit_depth << 14); + if (inst->std == W_HEVC_ENC) + reg_val |= (p_param->tier << 12) | (p_param->tmvp_enable << 23) | (p_param->sao_enable << 24) | (p_param->skip_intra_trans << 25) | (p_param->strong_intra_smooth_enable << 27) | (p_param->en_still_picture << 30); - if (p_param->scaling_list_enable == 2) - reg_val |= BIT(22) | BIT(31); // [31]=USE_DEFAULT_SCALING_LIST - else - reg_val |= (p_param->scaling_list_enable << 22); - } - vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_SPS_PARAM, reg_val); reg_val = (p_param->lossless_enable) | (p_param->const_intra_pred_flag << 1) | (p_param->lf_cross_slice_boundary_enable << 2) | - (p_param->weight_pred_enable << 3) | (p_param->wpp_enable << 4) | (p_param->disable_deblk << 5) | ((p_param->beta_offset_div2 & 0xF) << 6) | @@ -1993,51 +1620,40 @@ int wave5_vpu_enc_init_seq(struct vpu_instance *inst) if (inst->std == W_AVC_ENC) vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_INTRA_PARAM, p_param->intra_qp | ((p_param->intra_period & 0x7ff) << 6) | - ((p_param->avc_idr_period & 0x7ff) << 17) | - ((p_param->forced_idr_header_enable & 3) << 28)); - else + ((p_param->avc_idr_period & 0x7ff) << 17)); + else if (inst->std == W_HEVC_ENC) vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_INTRA_PARAM, p_param->decoding_refresh_type | (p_param->intra_qp << 3) | - (p_param->forced_idr_header_enable << 9) | (p_param->intra_period << 16)); - reg_val = (p_param->use_recommend_enc_param) | - (p_param->rdo_skip << 2) | + reg_val = (p_param->rdo_skip << 2) | (p_param->lambda_scaling_enable << 3) | - (p_param->coef_clear_disable << 4) | (fixed_cu_size_mode << 5) | (p_param->intra_nx_n_enable << 8) | - (p_param->max_num_merge << 18) | - (p_param->custom_md_enable << 20) | - (p_param->custom_lambda_enable << 21) | - (p_param->monochrome_enable << 22); + (p_param->max_num_merge << 18); vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RDO_PARAM, reg_val); if (inst->std == W_AVC_ENC) vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_INTRA_REFRESH, p_param->intra_mb_refresh_arg << 16 | p_param->intra_mb_refresh_mode); - else + else if (inst->std == W_HEVC_ENC) vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_INTRA_REFRESH, p_param->intra_refresh_arg << 16 | p_param->intra_refresh_mode); vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RC_FRAME_RATE, p_open_param->frame_rate_info); vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RC_TARGET_RATE, p_open_param->bit_rate); + reg_val = p_open_param->rc_enable | + (p_param->hvs_qp_enable << 2) | + (p_param->hvs_qp_scale << 4) | + ((p_param->initial_rc_qp & 0x3F) << 14) | + (p_open_param->vbv_buffer_size << 20); if (inst->std == W_AVC_ENC) - vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RC_PARAM, - p_open_param->rc_enable | (p_param->mb_level_rc_enable << 1) | - (p_param->hvs_qp_enable << 2) | (p_param->hvs_qp_scale << 4) | - (p_param->bit_alloc_mode << 8) | (p_param->roi_enable << 13) | - ((p_param->initial_rc_qp & 0x3F) << 14) | - (p_open_param->vbv_buffer_size << 20)); - else - vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RC_PARAM, - p_open_param->rc_enable | (p_param->cu_level_rc_enable << 1) | - (p_param->hvs_qp_enable << 2) | (p_param->hvs_qp_scale << 4) | - (p_param->bit_alloc_mode << 8) | (p_param->roi_enable << 13) | - ((p_param->initial_rc_qp & 0x3F) << 14) | - (p_open_param->vbv_buffer_size << 20)); + reg_val |= (p_param->mb_level_rc_enable << 1); + else if (inst->std == W_HEVC_ENC) + reg_val |= (p_param->cu_level_rc_enable << 1); + vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RC_PARAM, reg_val); vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RC_WEIGHT_PARAM, p_param->rc_weight_buf << 8 | p_param->rc_weight_param); @@ -2049,101 +1665,42 @@ int wave5_vpu_enc_init_seq(struct vpu_instance *inst) (p_param->max_qp_p << 6) | (p_param->min_qp_b << 12) | (p_param->max_qp_b << 18)); - vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RC_BIT_RATIO_LAYER_0_3, - (u32)p_param->fixed_bit_ratio[0] | - ((u32)p_param->fixed_bit_ratio[1] << 8) | - ((u32)p_param->fixed_bit_ratio[2] << 16) | - ((u32)p_param->fixed_bit_ratio[3] << 24)); - - vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RC_BIT_RATIO_LAYER_4_7, - (u32)p_param->fixed_bit_ratio[4] | - ((u32)p_param->fixed_bit_ratio[5] << 8) | - ((u32)p_param->fixed_bit_ratio[6] << 16) | - ((u32)p_param->fixed_bit_ratio[7] << 24)); - + vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RC_BIT_RATIO_LAYER_0_3, 0); + vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RC_BIT_RATIO_LAYER_4_7, 0); vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_ROT_PARAM, rot_mir_mode); - vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_BG_PARAM, (p_param->bg_detect_enable) | - (p_param->bg_thr_diff << 1) | (p_param->bg_thr_mean_diff << 10) | - (p_param->bg_lambda_qp << 18) | ((p_param->bg_delta_qp & 0x1F) << 24) | - ((inst->std == W_AVC_ENC) ? p_param->s2fme_disable << 29 : 0)); - - if (inst->std == W_HEVC_ENC || inst->std == W_AVC_ENC) { - vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_LAMBDA_ADDR, - p_param->custom_lambda_addr); + vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_BG_PARAM, 0); + vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_LAMBDA_ADDR, 0); + vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CONF_WIN_TOP_BOT, + p_param->conf_win_bot << 16 | p_param->conf_win_top); + vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CONF_WIN_LEFT_RIGHT, + p_param->conf_win_right << 16 | p_param->conf_win_left); - vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CONF_WIN_TOP_BOT, - p_param->conf_win_bot << 16 | p_param->conf_win_top); - vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CONF_WIN_LEFT_RIGHT, - p_param->conf_win_right << 16 | p_param->conf_win_left); - - if (inst->std == W_AVC_ENC) - vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_INDEPENDENT_SLICE, - p_param->avc_slice_arg << 16 | p_param->avc_slice_mode); - else - vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_INDEPENDENT_SLICE, - p_param->independ_slice_mode_arg << 16 | - p_param->independ_slice_mode); - - vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_USER_SCALING_LIST_ADDR, - p_param->user_scaling_list_addr); - - vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_NUM_UNITS_IN_TICK, - p_param->num_units_in_tick); - vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_TIME_SCALE, p_param->time_scale); - vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_NUM_TICKS_POC_DIFF_ONE, - p_param->num_ticks_poc_diff_one); - } + if (inst->std == W_AVC_ENC) + vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_INDEPENDENT_SLICE, + p_param->avc_slice_arg << 16 | p_param->avc_slice_mode); + else if (inst->std == W_HEVC_ENC) + vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_INDEPENDENT_SLICE, + p_param->independ_slice_mode_arg << 16 | + p_param->independ_slice_mode); + + vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_USER_SCALING_LIST_ADDR, 0); + vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_NUM_UNITS_IN_TICK, 0); + vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_TIME_SCALE, 0); + vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_NUM_TICKS_POC_DIFF_ONE, 0); if (inst->std == W_HEVC_ENC) { - vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_MD_PU04, - (p_param->pu04_delta_rate & 0xFF) | - ((p_param->pu04_intra_planar_delta_rate & 0xFF) << 8) | - ((p_param->pu04_intra_dc_delta_rate & 0xFF) << 16) | - ((p_param->pu04_intra_angle_delta_rate & 0xFF) << 24)); - - vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_MD_PU08, - (p_param->pu08_delta_rate & 0xFF) | - ((p_param->pu08_intra_planar_delta_rate & 0xFF) << 8) | - ((p_param->pu08_intra_dc_delta_rate & 0xFF) << 16) | - ((p_param->pu08_intra_angle_delta_rate & 0xFF) << 24)); - - vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_MD_PU16, - (p_param->pu16_delta_rate & 0xFF) | - ((p_param->pu16_intra_planar_delta_rate & 0xFF) << 8) | - ((p_param->pu16_intra_dc_delta_rate & 0xFF) << 16) | - ((p_param->pu16_intra_angle_delta_rate & 0xFF) << 24)); - - vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_MD_PU32, - (p_param->pu32_delta_rate & 0xFF) | - ((p_param->pu32_intra_planar_delta_rate & 0xFF) << 8) | - ((p_param->pu32_intra_dc_delta_rate & 0xFF) << 16) | - ((p_param->pu32_intra_angle_delta_rate & 0xFF) << 24)); - - vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_MD_CU08, - (p_param->cu08_intra_delta_rate & 0xFF) | - ((p_param->cu08_inter_delta_rate & 0xFF) << 8) | - ((p_param->cu08_merge_delta_rate & 0xFF) << 16)); - - vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_MD_CU16, - (p_param->cu16_intra_delta_rate & 0xFF) | - ((p_param->cu16_inter_delta_rate & 0xFF) << 8) | - ((p_param->cu16_merge_delta_rate & 0xFF) << 16)); - - vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_MD_CU32, - (p_param->cu32_intra_delta_rate & 0xFF) | - ((p_param->cu32_inter_delta_rate & 0xFF) << 8) | - ((p_param->cu32_merge_delta_rate & 0xFF) << 16)); - + vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_MD_PU04, 0); + vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_MD_PU08, 0); + vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_MD_PU16, 0); + vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_MD_PU32, 0); + vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_MD_CU08, 0); + vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_MD_CU16, 0); + vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_MD_CU32, 0); vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_DEPENDENT_SLICE, p_param->depend_slice_mode_arg << 16 | p_param->depend_slice_mode); - vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_NR_PARAM, p_param->nr_y_enable | - (p_param->nr_cb_enable << 1) | (p_param->nr_cr_enable << 2) | - (p_param->nr_noise_est_enable << 3) | - (p_param->nr_noise_sigma_y << 4) | - (p_param->nr_noise_sigma_cb << 12) | - (p_param->nr_noise_sigma_cr << 20)); + vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_NR_PARAM, 0); vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_NR_WEIGHT, p_param->nr_intra_weight_y | @@ -2153,35 +1710,9 @@ int wave5_vpu_enc_init_seq(struct vpu_instance *inst) (p_param->nr_inter_weight_cb << 20) | (p_param->nr_inter_weight_cr << 25)); } - if (p_enc_info->open_param.encode_vui_rbsp || p_enc_info->open_param.enc_hrd_rbsp_in_vps) { - vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_VUI_HRD_PARAM, - (p_enc_info->open_param.hrd_rbsp_data_size << 18) | - (p_enc_info->open_param.vui_rbsp_data_size << 4) | - (p_enc_info->open_param.enc_hrd_rbsp_in_vps << 2) | - (p_enc_info->open_param.encode_vui_rbsp)); - vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_VUI_RBSP_ADDR, - p_enc_info->open_param.vui_rbsp_data_addr); - vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_HRD_RBSP_ADDR, - p_enc_info->open_param.hrd_rbsp_data_addr); - } else { - vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_VUI_HRD_PARAM, 0); - } + vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_VUI_HRD_PARAM, 0); - wave5_bit_issue_command(inst, W5_ENC_SET_PARAM); - - ret = wave5_wait_vpu_busy(inst->dev, W5_VPU_BUSY_STATUS); - if (ret) { - dev_warn(inst->dev->dev, "command: 'W5_ENC_SET_PARAM', timed out\n"); - return ret; - } - - if (!vpu_read_reg(inst->dev, W5_RET_SUCCESS)) { - reg_val = vpu_read_reg(inst->dev, W5_RET_FAIL_REASON); - wave5_print_reg_err(inst->dev, reg_val); - return -EIO; - } - - return 0; + return send_firmware_command(inst, W5_ENC_SET_PARAM, true, NULL, NULL); } int wave5_vpu_enc_get_seq_info(struct vpu_instance *inst, struct enc_initial_info *info) @@ -2190,18 +1721,10 @@ int wave5_vpu_enc_get_seq_info(struct vpu_instance *inst, struct enc_initial_inf u32 reg_val; struct enc_info *p_enc_info = &inst->codec_info->enc_info; - if (inst->dev->product != PRODUCT_ID_521) - return -EINVAL; - - // send QUERY cmd - ret = wave5_send_query(inst, GET_RESULT); - if (ret) { - if (ret == -EIO) { - reg_val = vpu_read_reg(inst->dev, W5_RET_FAIL_REASON); - wave5_print_reg_err(inst->dev, reg_val); - } + /* send QUERY cmd */ + ret = wave5_send_query(inst->dev, inst, GET_RESULT); + if (ret) return ret; - } dev_dbg(inst->dev->dev, "%s: init seq\n", __func__); @@ -2219,7 +1742,6 @@ int wave5_vpu_enc_get_seq_info(struct vpu_instance *inst, struct enc_initial_inf info->min_frame_buffer_count = vpu_read_reg(inst->dev, W5_RET_ENC_NUM_REQUIRED_FB); info->min_src_frame_count = vpu_read_reg(inst->dev, W5_RET_ENC_MIN_SRC_BUF_NUM); - info->max_latency_pictures = vpu_read_reg(inst->dev, W5_RET_ENC_PIC_MAX_LATENCY_PICS); info->vlc_buf_size = vpu_read_reg(inst->dev, W5_RET_VLC_BUF_SIZE); info->param_buf_size = vpu_read_reg(inst->dev, W5_RET_PARAM_BUF_SIZE); p_enc_info->vlc_buf_size = info->vlc_buf_size; @@ -2249,7 +1771,7 @@ int wave5_vpu_enc_register_framebuffer(struct device *dev, struct vpu_instance * size_t remain, idx, j, i, cnt_8_chunk; u32 reg_val = 0, pic_size = 0, mv_col_size, fbc_y_tbl_size, fbc_c_tbl_size; u32 sub_sampled_size = 0; - u32 endian, luma_stride, chroma_stride, frame_width, frame_height; + u32 luma_stride, chroma_stride; u32 buf_height = 0, buf_width = 0; u32 bit_depth; bool avc_encoding = (inst->std == W_AVC_ENC); @@ -2319,16 +1841,8 @@ int wave5_vpu_enc_register_framebuffer(struct device *dev, struct vpu_instance * p_enc_info->vb_mv = vb_mv; - frame_width = ALIGN(buf_width, 16); - frame_height = ALIGN(buf_height, 16); - if (p_enc_info->product_code == WAVE521C_DUAL_CODE) { - // Use 1024 for H264(AVC) and 512 for H265(HEVC) - fbc_y_tbl_size = calculate_table_size(bit_depth, frame_width, frame_height, - (avc_encoding ? 1024 : 512)); - } else { - fbc_y_tbl_size = WAVE5_FBC_LUMA_TABLE_SIZE(buf_width, buf_height); - fbc_y_tbl_size = ALIGN(fbc_y_tbl_size, 16); - } + fbc_y_tbl_size = ALIGN(WAVE5_FBC_LUMA_TABLE_SIZE(buf_width, buf_height), 16); + fbc_c_tbl_size = ALIGN(WAVE5_FBC_CHROMA_TABLE_SIZE(buf_width, buf_height), 16); vb_fbc_y_tbl.daddr = 0; vb_fbc_y_tbl.size = ALIGN(fbc_y_tbl_size * count, BUFFER_MARGIN) + BUFFER_MARGIN; @@ -2338,15 +1852,6 @@ int wave5_vpu_enc_register_framebuffer(struct device *dev, struct vpu_instance * p_enc_info->vb_fbc_y_tbl = vb_fbc_y_tbl; - if (p_enc_info->product_code == WAVE521C_DUAL_CODE) { - // Use 1024 for H264(AVC) and 512 for HEVC - fbc_c_tbl_size = calculate_table_size(bit_depth, frame_width, frame_height, - (avc_encoding ? 1024 : 512)); - } else { - fbc_c_tbl_size = WAVE5_FBC_CHROMA_TABLE_SIZE(buf_width, buf_height); - fbc_c_tbl_size = ALIGN(fbc_c_tbl_size, 16); - } - vb_fbc_c_tbl.daddr = 0; vb_fbc_c_tbl.size = ALIGN(fbc_c_tbl_size * count, BUFFER_MARGIN) + BUFFER_MARGIN; ret = wave5_vdi_allocate_dma_memory(vpu_dev, &vb_fbc_c_tbl); @@ -2382,16 +1887,14 @@ int wave5_vpu_enc_register_framebuffer(struct device *dev, struct vpu_instance * vpu_write_reg(inst->dev, W5_CMD_SET_FB_TASK_BUF_SIZE, vb_task.size); } - // set sub-sampled buffer base addr + /* set sub-sampled buffer base addr */ vpu_write_reg(inst->dev, W5_ADDR_SUB_SAMPLED_FB_BASE, vb_sub_sam_buf.daddr); - // set sub-sampled buffer size for one frame + /* set sub-sampled buffer size for one frame */ vpu_write_reg(inst->dev, W5_SUB_SAMPLED_ONE_FB_SIZE, sub_sampled_size); - endian = wave5_vdi_convert_endian(vpu_dev, fb_arr[0].endian); - vpu_write_reg(inst->dev, W5_PIC_SIZE, pic_size); - // set stride of luma/chroma for compressed buffer + /* set stride of luma/chroma for compressed buffer */ if ((p_enc_info->rotation_angle || p_enc_info->mirror_direction) && !(p_enc_info->rotation_angle == 180 && p_enc_info->mirror_direction == MIRDIR_HOR_VER)) { @@ -2406,11 +1909,10 @@ int wave5_vpu_enc_register_framebuffer(struct device *dev, struct vpu_instance * vpu_write_reg(inst->dev, W5_COMMON_PIC_INFO, stride); remain = count; - cnt_8_chunk = ALIGN(count, 8) / 8; + cnt_8_chunk = DIV_ROUND_UP(count, 8); idx = 0; for (j = 0; j < cnt_8_chunk; j++) { - reg_val = (endian << 16) | (j == cnt_8_chunk - 1) << 4 | ((j == 0) << 3); - reg_val |= (p_open_param->enable_non_ref_fbc_write << 26); + reg_val = (j == cnt_8_chunk - 1) << 4 | ((j == 0) << 3); vpu_write_reg(inst->dev, W5_SFB_OPTION, reg_val); start_no = j * 8; end_no = start_no + ((remain >= 8) ? 8 : remain) - 1; @@ -2435,17 +1937,14 @@ int wave5_vpu_enc_register_framebuffer(struct device *dev, struct vpu_instance * } remain -= i; - wave5_bit_issue_command(inst, W5_SET_FB); - ret = wave5_wait_vpu_busy(inst->dev, W5_VPU_BUSY_STATUS); + ret = send_firmware_command(inst, W5_SET_FB, false, NULL, NULL); if (ret) goto free_vb_mem; } - reg_val = vpu_read_reg(inst->dev, W5_RET_SUCCESS); - if (!reg_val) { - ret = -EIO; + ret = wave5_vpu_firmware_command_queue_error_check(vpu_dev, NULL); + if (ret) goto free_vb_mem; - } return ret; @@ -2465,7 +1964,7 @@ free_vb_fbc_y_tbl: int wave5_vpu_encode(struct vpu_instance *inst, struct enc_param *option, u32 *fail_res) { u32 src_frame_format; - u32 reg_val = 0, bs_endian; + u32 reg_val = 0; u32 src_stride_c = 0; struct enc_info *p_enc_info = &inst->codec_info->enc_info; struct frame_buffer *p_src_frame = option->source_frame; @@ -2474,9 +1973,6 @@ int wave5_vpu_encode(struct vpu_instance *inst, struct enc_param *option, u32 *f u32 format_no = WTL_PIXEL_8BIT; int ret; - if (inst->dev->product != PRODUCT_ID_521) - return -EINVAL; - vpu_write_reg(inst->dev, W5_CMD_ENC_BS_START_ADDR, option->pic_stream_buffer_addr); vpu_write_reg(inst->dev, W5_CMD_ENC_BS_SIZE, option->pic_stream_buffer_size); p_enc_info->stream_buf_start_addr = option->pic_stream_buffer_addr; @@ -2486,8 +1982,8 @@ int wave5_vpu_encode(struct vpu_instance *inst, struct enc_param *option, u32 *f vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SRC_AXI_SEL, DEFAULT_SRC_AXI); /* secondary AXI */ - reg_val = (p_enc_info->sec_axi_info.wave.use_enc_rdo_enable << 11) | - (p_enc_info->sec_axi_info.wave.use_enc_lf_enable << 15); + reg_val = (p_enc_info->sec_axi_info.use_enc_rdo_enable << 11) | + (p_enc_info->sec_axi_info.use_enc_lf_enable << 15); vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_USE_SEC_AXI, reg_val); vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_REPORT_PARAM, 0); @@ -2513,26 +2009,17 @@ int wave5_vpu_encode(struct vpu_instance *inst, struct enc_param *option, u32 *f (option->code_option.encode_eos << 6) | (option->code_option.encode_eob << 7)); - vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_PIC_PARAM, option->skip_picture | - (option->force_pic_qp_enable << 1) | (option->force_pic_qp_i << 2) | - (option->force_pic_qp_p << 8) | (option->force_pic_qp_b << 14) | - (option->force_pic_type_enable << 20) | (option->force_pic_type << 21) | - (option->force_all_ctu_coef_drop_enable << 24)); + vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_PIC_PARAM, 0); if (option->src_end_flag) - // no more source images. + /* no more source images. */ vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SRC_PIC_IDX, 0xFFFFFFFF); else vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SRC_PIC_IDX, option->src_idx); vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SRC_ADDR_Y, p_src_frame->buf_y); - if (p_open_param->cbcr_order == CBCR_ORDER_NORMAL) { - vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SRC_ADDR_U, p_src_frame->buf_cb); - vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SRC_ADDR_V, p_src_frame->buf_cr); - } else { - vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SRC_ADDR_U, p_src_frame->buf_cr); - vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SRC_ADDR_V, p_src_frame->buf_cb); - } + vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SRC_ADDR_U, p_src_frame->buf_cb); + vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SRC_ADDR_V, p_src_frame->buf_cr); switch (p_open_param->src_format) { case FORMAT_420: @@ -2622,59 +2109,32 @@ int wave5_vpu_encode(struct vpu_instance *inst, struct enc_param *option, u32 *f break; } - reg_val = wave5_vdi_convert_endian(inst->dev, p_open_param->source_endian); - bs_endian = (~reg_val & VDI_128BIT_ENDIAN_MASK); - vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SRC_STRIDE, (p_src_frame->stride << 16) | src_stride_c); vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SRC_FORMAT, src_frame_format | - (format_no << 3) | (justified << 5) | (bs_endian << 6)); - - vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_CUSTOM_MAP_OPTION_ADDR, - option->custom_map_opt.addr_custom_map); - - vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_CUSTOM_MAP_OPTION_PARAM, - option->custom_map_opt.custom_roi_map_enable | - (option->custom_map_opt.roi_avg_qp << 1) | - (option->custom_map_opt.custom_lambda_map_enable << 8) | - (option->custom_map_opt.custom_mode_map_enable << 9) | - (option->custom_map_opt.custom_coef_drop_enable << 10)); - - vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_LONGTERM_PIC, - option->use_cur_src_as_longterm_pic | (option->use_longterm_ref << 1)); - - vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_WP_PIXEL_SIGMA_Y, option->wp_pix_sigma_y); - vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_WP_PIXEL_SIGMA_C, - (option->wp_pix_sigma_cr << 16) | option->wp_pix_sigma_cb); - vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_WP_PIXEL_MEAN_Y, option->wp_pix_mean_y); - vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_WP_PIXEL_MEAN_C, - (option->wp_pix_mean_cr << 16) | (option->wp_pix_mean_cb)); - + (format_no << 3) | (justified << 5) | (PIC_SRC_ENDIANNESS_BIG_ENDIAN << 6)); + + vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_CUSTOM_MAP_OPTION_ADDR, 0); + vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_CUSTOM_MAP_OPTION_PARAM, 0); + vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_LONGTERM_PIC, 0); + vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_WP_PIXEL_SIGMA_Y, 0); + vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_WP_PIXEL_SIGMA_C, 0); + vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_WP_PIXEL_MEAN_Y, 0); + vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_WP_PIXEL_MEAN_C, 0); vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_PREFIX_SEI_INFO, 0); vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_PREFIX_SEI_NAL_ADDR, 0); vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SUFFIX_SEI_INFO, 0); vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SUFFIX_SEI_NAL_ADDR, 0); - wave5_bit_issue_command(inst, W5_ENC_PIC); - - // check QUEUE_DONE - ret = wave5_wait_vpu_busy(inst->dev, W5_VPU_BUSY_STATUS); - if (ret) { - dev_warn(inst->dev->dev, "command: 'W5_ENC_PIC', timed out\n"); - return -ETIMEDOUT; - } - - reg_val = vpu_read_reg(inst->dev, W5_RET_QUEUE_STATUS); + ret = send_firmware_command(inst, W5_DEC_ENC_PIC, true, ®_val, fail_res); + if (ret == -ETIMEDOUT) + return ret; p_enc_info->instance_queue_count = (reg_val >> 16) & 0xff; p_enc_info->report_queue_count = (reg_val & QUEUE_REPORT_MASK); - // Check if we were able to add a command into the VCPU QUEUE - if (!vpu_read_reg(inst->dev, W5_RET_SUCCESS)) { - *fail_res = vpu_read_reg(inst->dev, W5_RET_FAIL_REASON); - wave5_print_reg_err(inst->dev, *fail_res); - return -EIO; - } + if (ret) + return ret; return 0; } @@ -2687,17 +2147,10 @@ int wave5_vpu_enc_get_result(struct vpu_instance *inst, struct enc_output_info * struct enc_info *p_enc_info = &inst->codec_info->enc_info; struct vpu_device *vpu_dev = inst->dev; - if (vpu_dev->product != PRODUCT_ID_521) - return -EINVAL; - - ret = wave5_send_query(inst, GET_RESULT); - if (ret) { - if (ret == -EIO) { - reg_val = vpu_read_reg(inst->dev, W5_RET_FAIL_REASON); - wave5_print_reg_err(inst->dev, reg_val); - } + ret = wave5_send_query(inst->dev, inst, GET_RESULT); + if (ret) return ret; - } + dev_dbg(inst->dev->dev, "%s: enc pic complete\n", __func__); reg_val = vpu_read_reg(inst->dev, W5_RET_QUEUE_STATUS); @@ -2731,7 +2184,7 @@ int wave5_vpu_enc_get_result(struct vpu_instance *inst, struct enc_output_info * result->rd_ptr = p_enc_info->stream_rd_ptr; result->wr_ptr = p_enc_info->stream_wr_ptr; - //result for header only(no vcl) encoding + /*result for header only(no vcl) encoding */ if (result->recon_frame_index == RECON_IDX_FLAG_HEADER_ONLY) result->bitstream_size = result->enc_pic_byte; else if (result->recon_frame_index < 0) @@ -2761,28 +2214,12 @@ int wave5_vpu_enc_get_result(struct vpu_instance *inst, struct enc_output_info * int wave5_vpu_enc_finish_seq(struct vpu_instance *inst, u32 *fail_res) { - int ret; - - if (inst->dev->product != PRODUCT_ID_521) - return -EINVAL; - - wave5_bit_issue_command(inst, W5_DESTROY_INSTANCE); - ret = wave5_wait_vpu_busy(inst->dev, W5_VPU_BUSY_STATUS); - if (ret) - return -ETIMEDOUT; - - if (!vpu_read_reg(inst->dev, W5_RET_SUCCESS)) { - *fail_res = vpu_read_reg(inst->dev, W5_RET_FAIL_REASON); - wave5_print_reg_err(inst->dev, *fail_res); - return -EIO; - } - return 0; + return send_firmware_command(inst, W5_DESTROY_INSTANCE, true, NULL, fail_res); } -static int wave5_vpu_enc_check_common_param_valid(struct vpu_instance *inst, - struct enc_open_param *open_param) +static bool wave5_vpu_enc_check_common_param_valid(struct vpu_instance *inst, + struct enc_open_param *open_param) { - int i = 0; bool low_delay = true; struct enc_wave_param *param = &open_param->wave_param; struct vpu_device *vpu_dev = inst->dev; @@ -2791,21 +2228,6 @@ static int wave5_vpu_enc_check_common_param_valid(struct vpu_instance *inst, u32 num_ctu_col = (open_param->pic_width + 64 - 1) / 64; u32 ctu_sz = num_ctu_col * num_ctu_row; - // check low-delay gop structure - if (param->gop_preset_idx == PRESET_IDX_CUSTOM_GOP) { /* common gop */ - if (param->gop_param.custom_gop_size > 1) { - s32 min_val = param->gop_param.pic_param[0].poc_offset; - - for (i = 1; i < param->gop_param.custom_gop_size; i++) { - if (min_val > param->gop_param.pic_param[i].poc_offset) { - low_delay = false; - break; - } - min_val = param->gop_param.pic_param[i].poc_offset; - } - } - } - if (inst->std == W_HEVC_ENC && low_delay && param->decoding_refresh_type == DEC_REFRESH_TYPE_CRA) { dev_warn(dev, @@ -2814,115 +2236,81 @@ static int wave5_vpu_enc_check_common_param_valid(struct vpu_instance *inst, param->decoding_refresh_type = 2; } - if (param->gop_preset_idx == PRESET_IDX_CUSTOM_GOP) { - for (i = 0; i < param->gop_param.custom_gop_size; i++) { - if (param->gop_param.pic_param[i].temporal_id >= MAX_NUM_TEMPORAL_LAYER) { - dev_err(dev, "temporal_id: %d exceeds MAX_NUM_TEMPORAL_LAYER (%u)\n", - param->gop_param.pic_param[i].temporal_id, - MAX_NUM_TEMPORAL_LAYER); - return -EINVAL; - } - - if (param->gop_param.pic_param[i].temporal_id < 0) { - dev_err(dev, "temporal_id: %d must be greater or equal to 0\n", - param->gop_param.pic_param[i].temporal_id); - return -EINVAL; - } - } - } - if (param->wpp_enable && param->independ_slice_mode) { unsigned int num_ctb_in_width = ALIGN(open_param->pic_width, 64) >> 6; if (param->independ_slice_mode_arg % num_ctb_in_width) { dev_err(dev, "independ_slice_mode_arg %u must be a multiple of %u\n", param->independ_slice_mode_arg, num_ctb_in_width); - return -EINVAL; + return false; } } - // multi-slice & wpp + /* multi-slice & wpp */ if (param->wpp_enable && param->depend_slice_mode) { dev_err(dev, "wpp_enable && depend_slice_mode cannot be used simultaneously\n"); - return -EINVAL; + return false; } if (!param->independ_slice_mode && param->depend_slice_mode) { dev_err(dev, "depend_slice_mode requires independ_slice_mode\n"); - return -EINVAL; + return false; } else if (param->independ_slice_mode && param->depend_slice_mode == DEPEND_SLICE_MODE_RECOMMENDED && param->independ_slice_mode_arg < param->depend_slice_mode_arg) { dev_err(dev, "independ_slice_mode_arg: %u must be smaller than %u\n", param->independ_slice_mode_arg, param->depend_slice_mode_arg); - return -EINVAL; + return false; } if (param->independ_slice_mode && param->independ_slice_mode_arg > 65535) { dev_err(dev, "independ_slice_mode_arg: %u must be smaller than 65535\n", param->independ_slice_mode_arg); - return -EINVAL; + return false; } if (param->depend_slice_mode && param->depend_slice_mode_arg > 65535) { dev_err(dev, "depend_slice_mode_arg: %u must be smaller than 65535\n", param->depend_slice_mode_arg); - return -EINVAL; + return false; } if (param->conf_win_top % 2) { dev_err(dev, "conf_win_top: %u, must be a multiple of 2\n", param->conf_win_top); - return -EINVAL; + return false; } if (param->conf_win_bot % 2) { dev_err(dev, "conf_win_bot: %u, must be a multiple of 2\n", param->conf_win_bot); - return -EINVAL; + return false; } if (param->conf_win_left % 2) { dev_err(dev, "conf_win_left: %u, must be a multiple of 2\n", param->conf_win_left); - return -EINVAL; + return false; } if (param->conf_win_right % 2) { dev_err(dev, "conf_win_right: %u, Must be a multiple of 2\n", param->conf_win_right); - return -EINVAL; - } - - if (param->lossless_enable && (param->nr_y_enable || param->nr_cb_enable || - param->nr_cr_enable)) { - /* Noise reduction => en_nr_y, en_nr_cb, en_nr_cr */ - dev_err(dev, "option noise_reduction cannot be used with lossless_coding\n"); - return -EINVAL; - } - - if (param->lossless_enable && param->bg_detect_enable) { - dev_err(dev, "option bg_detect cannot be used with lossless_coding\n"); - return -EINVAL; + return false; } if (param->lossless_enable && open_param->rc_enable) { dev_err(dev, "option rate_control cannot be used with lossless_coding\n"); - return -EINVAL; - } - - if (param->lossless_enable && param->roi_enable) { - dev_err(dev, "option roi cannot be used with lossless_coding\n"); - return -EINVAL; + return false; } if (param->lossless_enable && !param->skip_intra_trans) { dev_err(dev, "option intra_trans_skip must be enabled with lossless_coding\n"); - return -EINVAL; + return false; } - // intra refresh + /* intra refresh */ if (param->intra_refresh_mode && param->intra_refresh_arg == 0) { dev_err(dev, "Invalid refresh argument, mode: %u, refresh: %u must be > 0\n", param->intra_refresh_mode, param->intra_refresh_arg); - return -EINVAL; + return false; } switch (param->intra_refresh_mode) { case REFRESH_MODE_CTU_ROWS: @@ -2943,25 +2331,20 @@ static int wave5_vpu_enc_check_common_param_valid(struct vpu_instance *inst, if (param->lossless_enable) { dev_err(dev, "mode: %u cannot be used lossless_enable", param->intra_refresh_mode); - return -EINVAL; - } - if (param->roi_enable) { - dev_err(dev, "mode: %u cannot be used and roi_enable", - param->intra_refresh_mode); - return -EINVAL; + return false; } }; - return 0; + return true; invalid_refresh_argument: dev_err(dev, "Invalid refresh argument, mode: %u, refresh: %u > W(%u)xH(%u)\n", param->intra_refresh_mode, param->intra_refresh_arg, num_ctu_row, num_ctu_col); - return -EINVAL; + return false; } -static int wave5_vpu_enc_check_param_valid(struct vpu_device *vpu_dev, - struct enc_open_param *open_param) +static bool wave5_vpu_enc_check_param_valid(struct vpu_device *vpu_dev, + struct enc_open_param *open_param) { struct enc_wave_param *param = &open_param->wave_param; @@ -2970,132 +2353,18 @@ static int wave5_vpu_enc_check_param_valid(struct vpu_device *vpu_dev, param->min_qp_b > param->max_qp_b) { dev_err(vpu_dev->dev, "Configuration failed because min_qp is greater than max_qp\n"); dev_err(vpu_dev->dev, "Suggested configuration parameters: min_qp = max_qp\n"); - return -EINVAL; + return false; } if (open_param->bit_rate <= (int)open_param->frame_rate_info) { dev_err(vpu_dev->dev, "enc_bit_rate: %u must be greater than the frame_rate: %u\n", open_param->bit_rate, (int)open_param->frame_rate_info); - return -EINVAL; - } - } - - return 0; -} - -static int wave5_vpu_enc_check_custom_gop(struct vpu_device *vpu_dev, - struct enc_open_param *open_param) -{ - struct custom_gop_param *gop_param; - struct custom_gop_pic_param *gop_pic_param; - struct custom_gop_pic_param new_gop[MAX_GOP_NUM * 2 + 1]; - - unsigned int i, ei, gi; - u32 gop_size; - s32 curr_poc, ref_poc; - s32 enc_tid[MAX_GOP_NUM * 2 + 1]; - - gop_param = &open_param->wave_param.gop_param; - gop_size = gop_param->custom_gop_size; - - new_gop[0].poc_offset = 0; - new_gop[0].temporal_id = 0; - new_gop[0].pic_type = PIC_TYPE_I; - new_gop[0].use_multi_ref_p = 0; - enc_tid[0] = 0; - - for (i = 0; i < gop_size * 2; i++) { - ei = i % gop_size; - gi = i / gop_size; - gop_pic_param = &gop_param->pic_param[ei]; - - curr_poc = gi * gop_size + gop_pic_param->poc_offset; - new_gop[i + 1].poc_offset = curr_poc; - new_gop[i + 1].temporal_id = gop_pic_param->temporal_id; - new_gop[i + 1].pic_type = gop_pic_param->pic_type; - new_gop[i + 1].ref_poc_l0 = gop_pic_param->ref_poc_l0 + gi * gop_size; - new_gop[i + 1].ref_poc_l1 = gop_pic_param->ref_poc_l1 + gi * gop_size; - new_gop[i + 1].use_multi_ref_p = gop_pic_param->use_multi_ref_p; - enc_tid[i + 1] = -1; - } - - for (i = 0; i < gop_size; i++) { - gop_pic_param = &gop_param->pic_param[i]; - - if (gop_pic_param->poc_offset <= 0) { - dev_err(vpu_dev->dev, "POC of the %u-th pic not greater then -1\n", i + 1); - return -EINVAL; - } - if (gop_pic_param->poc_offset > gop_size) { - dev_err(vpu_dev->dev, "POC of %uth pic bigger than gop_size\n", i + 1); - return -EINVAL; - } - if (gop_pic_param->temporal_id < 0) { - dev_err(vpu_dev->dev, "temporal_id of the %d-th < 0\n", i + 1); - return -EINVAL; + return false; } } - for (ei = 1; ei < gop_size * 2 + 1; ei++) { - struct custom_gop_pic_param *cur_pic = &new_gop[ei]; - - if (ei <= gop_size) { - enc_tid[cur_pic->poc_offset] = cur_pic->temporal_id; - continue; - } - - if (new_gop[ei].pic_type != PIC_TYPE_I) { - ref_poc = cur_pic->ref_poc_l0; - - /* reference picture is not encoded yet */ - if (enc_tid[ref_poc] < 0) { - dev_err(vpu_dev->dev, "1st ref pic can't be ref of pic (POC: %u)\n", - cur_pic->poc_offset - gop_size); - return -EINVAL; - } - if (enc_tid[ref_poc] > cur_pic->temporal_id) { - dev_err(vpu_dev->dev, "wrong temporal_id of pic (POC: %u)\n", - cur_pic->poc_offset - gop_size); - return -EINVAL; - } - if (ref_poc >= cur_pic->poc_offset) { - dev_err(vpu_dev->dev, "POC of 1st ref pic of %u-th pic is wrong\n", - cur_pic->poc_offset - gop_size); - return -EINVAL; - } - } - if (new_gop[ei].pic_type != PIC_TYPE_P) { - ref_poc = cur_pic->ref_poc_l1; - - /* reference picture is not encoded yet */ - if (enc_tid[ref_poc] < 0) { - dev_err(vpu_dev->dev, "2nd ref pic can't be ref of pic (POC: %u)\n" - , cur_pic->poc_offset - gop_size); - return -EINVAL; - } - if (enc_tid[ref_poc] > cur_pic->temporal_id) { - dev_err(vpu_dev->dev, "temporal_id of %u-th picture is wrong\n", - cur_pic->poc_offset - gop_size); - return -EINVAL; - } - if (new_gop[ei].pic_type == PIC_TYPE_P && new_gop[ei].use_multi_ref_p > 0) { - if (ref_poc >= cur_pic->poc_offset) { - dev_err(vpu_dev->dev, "bad POC of 2nd ref pic of %uth pic\n", - cur_pic->poc_offset - gop_size); - return -EINVAL; - } - } else if (ref_poc == cur_pic->poc_offset) { - /* HOST_PIC_TYPE_B */ - dev_err(vpu_dev->dev, "POC of 2nd ref pic of %uth pic is wrong\n", - cur_pic->poc_offset - gop_size); - return -EINVAL; - } - } - curr_poc = cur_pic->poc_offset; - enc_tid[curr_poc] = cur_pic->temporal_id; - } - return 0; + return true; } int wave5_vpu_enc_check_open_param(struct vpu_instance *inst, struct enc_open_param *open_param) @@ -3137,37 +2406,11 @@ int wave5_vpu_enc_check_open_param(struct vpu_instance *inst, struct enc_open_pa } } - if (open_param->ring_buffer_enable) { - if (open_param->bitstream_buffer % 8) { - dev_err(inst->dev->dev, - "Bitstream buffer must be aligned to a multiple of 8\n"); - return -EINVAL; - } - if (open_param->bitstream_buffer_size % 1024 || - open_param->bitstream_buffer_size < MIN_BITSTREAM_BUFFER_SIZE) { - dev_err(inst->dev->dev, - "Bitstream buffer size must be aligned to a multiple of 1024 and have a minimum size of %u\n", - MIN_BITSTREAM_BUFFER_SIZE); - return -EINVAL; - } - if (product_id == PRODUCT_ID_521) { - if (open_param->bitstream_buffer % 16) { - dev_err(inst->dev->dev, - "Bitstream buffer must be aligned to a multiple of 16\n"); - return -EINVAL; - } - if (open_param->bitstream_buffer_size < MIN_BITSTREAM_BUFFER_SIZE_WAVE521) { - dev_err(inst->dev->dev, - "Bitstream buffer too small: %u (minimum: %u)\n", - open_param->bitstream_buffer_size, - MIN_BITSTREAM_BUFFER_SIZE_WAVE521); - return -EINVAL; - } - } + if (!open_param->frame_rate_info) { + dev_err(inst->dev->dev, "No frame rate information.\n"); + return -EINVAL; } - if (!open_param->frame_rate_info) - return -EINVAL; if (open_param->bit_rate > MAX_BIT_RATE) { dev_err(inst->dev->dev, "Invalid encoding bit-rate: %u (valid: 0-%u)\n", open_param->bit_rate, MAX_BIT_RATE); @@ -3212,21 +2455,6 @@ int wave5_vpu_enc_check_open_param(struct vpu_instance *inst, struct enc_open_pa return -EINVAL; } - if (param->gop_preset_idx == PRESET_IDX_CUSTOM_GOP) { - if (param->gop_param.custom_gop_size < 1 || - param->gop_param.custom_gop_size > MAX_GOP_NUM) { - dev_err(inst->dev->dev, - "Invalid custom group of pictures size: %u (valid: 1-%u)\n", - param->gop_param.custom_gop_size, MAX_GOP_NUM); - return -EINVAL; - } - } - - if (inst->std == W_AVC_ENC && param->custom_lambda_enable) { - dev_err(inst->dev->dev, - "Cannot combine AVC encoding with the custom lambda option\n"); - return -EINVAL; - } if (param->intra_refresh_mode > REFRESH_MODE_CTUS) { dev_err(inst->dev->dev, "Invalid intra refresh mode: %d (valid: 0-4)\n", param->intra_refresh_mode); @@ -3240,12 +2468,6 @@ int wave5_vpu_enc_check_open_param(struct vpu_instance *inst, struct enc_open_pa return -EINVAL; } - if (param->scaling_list_enable > 2) { - dev_err(inst->dev->dev, "Invalid scaling_list_enable: %u (valid: 0-2)\n", - param->scaling_list_enable); - return -EINVAL; - } - if (!param->disable_deblk) { if (param->beta_offset_div2 < -6 || param->beta_offset_div2 > 6) { dev_err(inst->dev->dev, "Invalid beta offset: %d (valid: -6-6)\n", @@ -3286,12 +2508,6 @@ int wave5_vpu_enc_check_open_param(struct vpu_instance *inst, struct enc_open_pa return -EINVAL; } - if (param->bit_alloc_mode > BIT_ALLOC_MODE_FIXED_RATIO) { - dev_err(inst->dev->dev, "Invalid bit alloc mode: %u (valid: 0-2)\n", - param->bit_alloc_mode); - return -EINVAL; - } - if (open_param->vbv_buffer_size < MIN_VBV_BUFFER_SIZE || open_param->vbv_buffer_size > MAX_VBV_BUFFER_SIZE) { dev_err(inst->dev->dev, "VBV buffer size: %u (valid: %u-%u)\n", @@ -3301,17 +2517,12 @@ int wave5_vpu_enc_check_open_param(struct vpu_instance *inst, struct enc_open_pa } } - if (wave5_vpu_enc_check_common_param_valid(inst, open_param)) + if (!wave5_vpu_enc_check_common_param_valid(inst, open_param)) return -EINVAL; - if (wave5_vpu_enc_check_param_valid(inst->dev, open_param)) + if (!wave5_vpu_enc_check_param_valid(inst->dev, open_param)) return -EINVAL; - if (param->gop_preset_idx == PRESET_IDX_CUSTOM_GOP) { - if (wave5_vpu_enc_check_custom_gop(inst->dev, open_param)) - return -EINVAL; - } - if (param->chroma_cb_qp_offset < -12 || param->chroma_cb_qp_offset > 12) { dev_err(inst->dev->dev, "Invalid chroma Cb quantization parameter offset: %d (valid: -12-12)\n", @@ -3333,16 +2544,6 @@ int wave5_vpu_enc_check_open_param(struct vpu_instance *inst, struct enc_open_pa } if (inst->std == W_HEVC_ENC) { - if (param->nr_noise_sigma_y > MAX_NOISE_SIGMA || - param->nr_noise_sigma_cb > MAX_NOISE_SIGMA || - param->nr_noise_sigma_cr > MAX_NOISE_SIGMA) { - dev_err(inst->dev->dev, - "Invalid noise sigma Y(%u) Cb(%u) Cr(%u) (valid: %u)\n", - param->nr_noise_sigma_y, param->nr_noise_sigma_cb, - param->nr_noise_sigma_cr, MAX_NOISE_SIGMA); - return -EINVAL; - } - if (param->nr_intra_weight_y > MAX_INTRA_WEIGHT || param->nr_intra_weight_cb > MAX_INTRA_WEIGHT || param->nr_intra_weight_cr > MAX_INTRA_WEIGHT) { @@ -3362,13 +2563,6 @@ int wave5_vpu_enc_check_open_param(struct vpu_instance *inst, struct enc_open_pa param->nr_inter_weight_cr, MAX_INTER_WEIGHT); return -EINVAL; } - - if ((param->nr_y_enable || param->nr_cb_enable || param->nr_cr_enable) && - param->lossless_enable) { - dev_err(inst->dev->dev, - "Can't enable lossless mode with either nr_y, nr_cb or nr_cr\n"); - return -EINVAL; - } } return 0; diff --git a/drivers/media/platform/chips-media/wave5/wave5-regdefine.h b/drivers/media/platform/chips-media/wave5/wave5-regdefine.h index 79b2f17dd7f0..28c89b2f1888 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-regdefine.h +++ b/drivers/media/platform/chips-media/wave5/wave5-regdefine.h @@ -2,62 +2,51 @@ /* * Wave5 series multi-standard codec IP - wave5 register definitions * - * Copyright (C) 2021 CHIPS&MEDIA INC + * Copyright (C) 2021-2023 CHIPS&MEDIA INC */ #ifndef __WAVE5_REGISTER_DEFINE_H__ #define __WAVE5_REGISTER_DEFINE_H__ enum W5_VPU_COMMAND { - W5_INIT_VPU = 0x0001, - W5_WAKEUP_VPU = 0x0002, - W5_SLEEP_VPU = 0x0004, - W5_CREATE_INSTANCE = 0x0008, /* queuing command */ - W5_FLUSH_INSTANCE = 0x0010, - W5_DESTROY_INSTANCE = 0x0020, /* queuing command */ - W5_INIT_SEQ = 0x0040, /* queuing command */ - W5_SET_FB = 0x0080, - W5_DEC_PIC = 0x0100, /* queuing command */ - W5_ENC_PIC = 0x0100, /* queuing command */ - W5_ENC_SET_PARAM = 0x0200, /* queuing command */ - W5_QUERY = 0x4000, - W5_UPDATE_BS = 0x8000, - W5_MAX_VPU_COMD = 0x10000, + W5_INIT_VPU = 0x0001, + W5_WAKEUP_VPU = 0x0002, + W5_SLEEP_VPU = 0x0004, + W5_CREATE_INSTANCE = 0x0008, /* queuing command */ + W5_FLUSH_INSTANCE = 0x0010, + W5_DESTROY_INSTANCE = 0x0020, /* queuing command */ + W5_INIT_SEQ = 0x0040, /* queuing command */ + W5_SET_FB = 0x0080, + W5_DEC_ENC_PIC = 0x0100, /* queuing command */ + W5_ENC_SET_PARAM = 0x0200, /* queuing command */ + W5_QUERY = 0x4000, + W5_UPDATE_BS = 0x8000, + W5_MAX_VPU_COMD = 0x10000, }; -enum QUERY_OPT { - GET_VPU_INFO = 0, - SET_WRITE_PROT = 1, - GET_RESULT = 2, - UPDATE_DISP_FLAG = 3, - GET_BW_REPORT = 4, - GET_BS_RD_PTR = 5, // for decoder - GET_BS_WR_PTR = 6, // for encoder - GET_SRC_BUF_FLAG = 7, // for encoder - SET_BS_RD_PTR = 8, // for decoder - GET_DEBUG_INFO = 0x61, +enum query_opt { + GET_VPU_INFO = 0, + SET_WRITE_PROT = 1, + GET_RESULT = 2, + UPDATE_DISP_FLAG = 3, + GET_BW_REPORT = 4, + GET_BS_RD_PTR = 5, /* for decoder */ + GET_BS_WR_PTR = 6, /* for encoder */ + GET_SRC_BUF_FLAG = 7, /* for encoder */ + SET_BS_RD_PTR = 8, /* for decoder */ + GET_DEBUG_INFO = 0x61, }; -/* - * A flag of user data buffer full. - * User data buffer full flag equal to 1 specifies that de- - * coded frame has more user data size than VPU internal - * buffer. VPU only dumps the internal buffer size of us- - * er data to USER_DATA_BUF_BASE buffer. In other - * words, VPU is unable to report the rest of the user data to - * USER_DATA_BUF_BASE buffer after the internal buffer - * fullness happens. - */ -#define USERDATA_FLAG_BUFF_FULL 1 - #define W5_REG_BASE 0x00000000 #define W5_CMD_REG_BASE 0x00000100 #define W5_CMD_REG_END 0x00000200 /* - * common - */ -/* power on configuration + * COMMON + * + * ---- + * + * Power on configuration * PO_DEBUG_MODE [0] 1 - power on with debug mode * USE_PO_CONF [3] 1 - use power-on-configuration */ @@ -65,10 +54,10 @@ enum QUERY_OPT { #define W5_VCPU_CUR_PC (W5_REG_BASE + 0x0004) #define W5_VCPU_CUR_LR (W5_REG_BASE + 0x0008) #define W5_VPU_PDBG_STEP_MASK_V (W5_REG_BASE + 0x000C) -#define W5_VPU_PDBG_CTRL (W5_REG_BASE + 0x0010) // v_cpu debugger ctrl register -#define W5_VPU_PDBG_IDX_REG (W5_REG_BASE + 0x0014) // v_cpu debugger index register -#define W5_VPU_PDBG_WDATA_REG (W5_REG_BASE + 0x0018) // v_cpu debugger write data register -#define W5_VPU_PDBG_RDATA_REG (W5_REG_BASE + 0x001C) // v_cpu debugger read data register +#define W5_VPU_PDBG_CTRL (W5_REG_BASE + 0x0010) /* v_cpu debugger ctrl register */ +#define W5_VPU_PDBG_IDX_REG (W5_REG_BASE + 0x0014) /* v_cpu debugger index register */ +#define W5_VPU_PDBG_WDATA_REG (W5_REG_BASE + 0x0018) /* v_cpu debugger write data reg */ +#define W5_VPU_PDBG_RDATA_REG (W5_REG_BASE + 0x001C) /* v_cpu debugger read data reg */ #define W5_VPU_FIO_CTRL_ADDR (W5_REG_BASE + 0x0020) #define W5_VPU_FIO_DATA (W5_REG_BASE + 0x0024) @@ -105,7 +94,7 @@ enum QUERY_OPT { * REGION ATTR2 [11] 0 - normal * 1 - bypass region * REMAP INDEX [15:12] - 0 ~ 3 - * ENDIAN [19:16] - see endian_mode in vdi.h + * ENDIAN [19:16] - NOTE: Currently not supported in this driver * AXI-ID [23:20] - upper AXI-ID * BUS_ERROR [29] 0 - bypass * 1 - make BUS_ERROR for unmapped region @@ -198,12 +187,12 @@ enum QUERY_OPT { #define W5_BS_OPTION (W5_REG_BASE + 0x0120) -// return info when QUERY (GET_RESULT) for en/decoder +/* return info when QUERY (GET_RESULT) for en/decoder */ #define W5_RET_VLC_BUF_SIZE (W5_REG_BASE + 0x01B0) -// return info when QUERY (GET_RESULT) for en/decoder +/* return info when QUERY (GET_RESULT) for en/decoder */ #define W5_RET_PARAM_BUF_SIZE (W5_REG_BASE + 0x01B4) -// set when SET_FB for en/decoder +/* set when SET_FB for en/decoder */ #define W5_CMD_SET_FB_ADDR_TASK_BUF (W5_REG_BASE + 0x01D4) #define W5_CMD_SET_FB_TASK_BUF_SIZE (W5_REG_BASE + 0x01D8) /************************************************************************/ @@ -228,6 +217,8 @@ enum QUERY_OPT { #define W5_CMD_DEC_BS_START_ADDR (W5_REG_BASE + 0x011C) #define W5_CMD_DEC_BS_SIZE (W5_REG_BASE + 0x0120) #define W5_CMD_BS_PARAM (W5_REG_BASE + 0x0124) +#define W5_CMD_ADDR_SEC_AXI (W5_REG_BASE + 0x0130) +#define W5_CMD_SEC_AXI_SIZE (W5_REG_BASE + 0x0134) #define W5_CMD_EXT_ADDR (W5_REG_BASE + 0x0138) #define W5_CMD_NUM_CQ_DEPTH_M1 (W5_REG_BASE + 0x013C) #define W5_CMD_ERR_CONCEAL (W5_REG_BASE + 0x0140) @@ -252,58 +243,58 @@ enum QUERY_OPT { #define W5_ADDR_LUMA_BASE0 (W5_REG_BASE + 0x0134) #define W5_ADDR_CB_BASE0 (W5_REG_BASE + 0x0138) #define W5_ADDR_CR_BASE0 (W5_REG_BASE + 0x013C) -// compression offset table for luma +/* compression offset table for luma */ #define W5_ADDR_FBC_Y_OFFSET0 (W5_REG_BASE + 0x013C) -// compression offset table for chroma +/* compression offset table for chroma */ #define W5_ADDR_FBC_C_OFFSET0 (W5_REG_BASE + 0x0140) #define W5_ADDR_LUMA_BASE1 (W5_REG_BASE + 0x0144) #define W5_ADDR_CB_ADDR1 (W5_REG_BASE + 0x0148) #define W5_ADDR_CR_ADDR1 (W5_REG_BASE + 0x014C) -// compression offset table for luma +/* compression offset table for luma */ #define W5_ADDR_FBC_Y_OFFSET1 (W5_REG_BASE + 0x014C) -// compression offset table for chroma +/* compression offset table for chroma */ #define W5_ADDR_FBC_C_OFFSET1 (W5_REG_BASE + 0x0150) #define W5_ADDR_LUMA_BASE2 (W5_REG_BASE + 0x0154) #define W5_ADDR_CB_ADDR2 (W5_REG_BASE + 0x0158) #define W5_ADDR_CR_ADDR2 (W5_REG_BASE + 0x015C) -// compression offset table for luma +/* compression offset table for luma */ #define W5_ADDR_FBC_Y_OFFSET2 (W5_REG_BASE + 0x015C) -// compression offset table for chroma +/* compression offset table for chroma */ #define W5_ADDR_FBC_C_OFFSET2 (W5_REG_BASE + 0x0160) #define W5_ADDR_LUMA_BASE3 (W5_REG_BASE + 0x0164) #define W5_ADDR_CB_ADDR3 (W5_REG_BASE + 0x0168) #define W5_ADDR_CR_ADDR3 (W5_REG_BASE + 0x016C) -// compression offset table for luma +/* compression offset table for luma */ #define W5_ADDR_FBC_Y_OFFSET3 (W5_REG_BASE + 0x016C) -// compression offset table for chroma +/* compression offset table for chroma */ #define W5_ADDR_FBC_C_OFFSET3 (W5_REG_BASE + 0x0170) #define W5_ADDR_LUMA_BASE4 (W5_REG_BASE + 0x0174) #define W5_ADDR_CB_ADDR4 (W5_REG_BASE + 0x0178) #define W5_ADDR_CR_ADDR4 (W5_REG_BASE + 0x017C) -// compression offset table for luma +/* compression offset table for luma */ #define W5_ADDR_FBC_Y_OFFSET4 (W5_REG_BASE + 0x017C) -// compression offset table for chroma +/* compression offset table for chroma */ #define W5_ADDR_FBC_C_OFFSET4 (W5_REG_BASE + 0x0180) #define W5_ADDR_LUMA_BASE5 (W5_REG_BASE + 0x0184) #define W5_ADDR_CB_ADDR5 (W5_REG_BASE + 0x0188) #define W5_ADDR_CR_ADDR5 (W5_REG_BASE + 0x018C) -// compression offset table for luma +/* compression offset table for luma */ #define W5_ADDR_FBC_Y_OFFSET5 (W5_REG_BASE + 0x018C) -// compression offset table for chroma +/* compression offset table for chroma */ #define W5_ADDR_FBC_C_OFFSET5 (W5_REG_BASE + 0x0190) #define W5_ADDR_LUMA_BASE6 (W5_REG_BASE + 0x0194) #define W5_ADDR_CB_ADDR6 (W5_REG_BASE + 0x0198) #define W5_ADDR_CR_ADDR6 (W5_REG_BASE + 0x019C) -// compression offset table for luma +/* compression offset table for luma */ #define W5_ADDR_FBC_Y_OFFSET6 (W5_REG_BASE + 0x019C) -// compression offset table for chroma +/* compression offset table for chroma */ #define W5_ADDR_FBC_C_OFFSET6 (W5_REG_BASE + 0x01A0) #define W5_ADDR_LUMA_BASE7 (W5_REG_BASE + 0x01A4) #define W5_ADDR_CB_ADDR7 (W5_REG_BASE + 0x01A8) #define W5_ADDR_CR_ADDR7 (W5_REG_BASE + 0x01AC) -// compression offset table for luma +/* compression offset table for luma */ #define W5_ADDR_FBC_Y_OFFSET7 (W5_REG_BASE + 0x01AC) -// compression offset table for chroma +/* compression offset table for chroma */ #define W5_ADDR_FBC_C_OFFSET7 (W5_REG_BASE + 0x01B0) #define W5_ADDR_MV_COL0 (W5_REG_BASE + 0x01B4) #define W5_ADDR_MV_COL1 (W5_REG_BASE + 0x01B8) @@ -508,7 +499,7 @@ enum QUERY_OPT { #define W5_BACKBONE_BUS_CTRL_VCORE0 (W5_BACKBONE_BASE_VCORE0 + 0x010) #define W5_BACKBONE_BUS_STATUS_VCORE0 (W5_BACKBONE_BASE_VCORE0 + 0x014) -#define W5_BACKBONE_BASE_VCORE1 0x9E00 // for dual-core product +#define W5_BACKBONE_BASE_VCORE1 0x9E00 /* for dual-core product */ #define W5_BACKBONE_BUS_CTRL_VCORE1 (W5_BACKBONE_BASE_VCORE1 + 0x010) #define W5_BACKBONE_BUS_STATUS_VCORE1 (W5_BACKBONE_BASE_VCORE1 + 0x014) @@ -525,7 +516,7 @@ enum QUERY_OPT { /************************************************************************/ /* ENCODER - CREATE_INSTANCE */ /************************************************************************/ -// 0x114 ~ 0x124 : defined above (CREATE_INSTANCE COMMON) +/* 0x114 ~ 0x124 : defined above (CREATE_INSTANCE COMMON) */ #define W5_CMD_ENC_VCORE_INFO (W5_REG_BASE + 0x0194) #define W5_CMD_ENC_SRC_OPTIONS (W5_REG_BASE + 0x0128) diff --git a/drivers/media/platform/chips-media/wave5/wave5-vdi.c b/drivers/media/platform/chips-media/wave5/wave5-vdi.c index e829feee2b26..beae8c747b3d 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-vdi.c +++ b/drivers/media/platform/chips-media/wave5/wave5-vdi.c @@ -2,7 +2,7 @@ /* * Wave5 series multi-standard codec IP - low level access functions * - * Copyright (C) 2021 CHIPS&MEDIA INC + * Copyright (C) 2021-2023 CHIPS&MEDIA INC */ #include <linux/bug.h> @@ -10,11 +10,17 @@ #include "wave5-vpu.h" #include "wave5-regdefine.h" #include <linux/delay.h> -#include <soc/sifive/sifive_l2_cache.h> +extern void sifive_l2_flush64_range(unsigned long start, unsigned long len); +extern void sifive_ccache_flush_entire(void); -#define VDI_SYSTEM_ENDIAN VDI_LITTLE_ENDIAN -#define VDI_128BIT_BUS_SYSTEM_ENDIAN VDI_128BIT_LITTLE_ENDIAN +void wave5_flush_l2_cache(unsigned long start, unsigned long len) +{ + if (len >= 0x80000) + sifive_ccache_flush_entire(); + else + sifive_l2_flush64_range(start, len); +} static int wave5_vdi_allocate_common_memory(struct device *dev) { @@ -50,11 +56,11 @@ int wave5_vdi_init(struct device *dev) if (!PRODUCT_CODE_W_SERIES(vpu_dev->product_code)) { WARN_ONCE(1, "unsupported product code: 0x%x\n", vpu_dev->product_code); - return 0; + return -EOPNOTSUPP; } - // if BIT processor is not running. - if (wave5_vdi_readl(vpu_dev, W5_VCPU_CUR_PC) == 0) { + /* if BIT processor is not running. */ + if (wave5_vdi_read_register(vpu_dev, W5_VCPU_CUR_PC) == 0) { int i; for (i = 0; i < 64; i++) @@ -81,7 +87,7 @@ void wave5_vdi_write_register(struct vpu_device *vpu_dev, u32 addr, u32 data) writel(data, vpu_dev->vdb_register + addr); } -unsigned int wave5_vdi_readl(struct vpu_device *vpu_dev, u32 addr) +unsigned int wave5_vdi_read_register(struct vpu_device *vpu_dev, u32 addr) { return readl(vpu_dev->vdb_register + addr); } @@ -94,15 +100,12 @@ int wave5_vdi_clear_memory(struct vpu_device *vpu_dev, struct vpu_buf *vb) } memset(vb->vaddr, 0, vb->size); - sifive_l2_flush64_range(vb->daddr, vb->size); + wave5_flush_l2_cache(vb->daddr, vb->size); return vb->size; } -static void wave5_swap_endian(struct vpu_device *vpu_dev, u8 *data, size_t len, - unsigned int endian); - int wave5_vdi_write_memory(struct vpu_device *vpu_dev, struct vpu_buf *vb, size_t offset, - u8 *data, size_t len, unsigned int endian) + u8 *data, size_t len) { if (!vb || !vb->vaddr) { dev_err(vpu_dev->dev, "%s: unable to write to unmapped buffer\n", __func__); @@ -114,9 +117,8 @@ int wave5_vdi_write_memory(struct vpu_device *vpu_dev, struct vpu_buf *vb, size_ return -ENOSPC; } - wave5_swap_endian(vpu_dev, data, len, endian); memcpy(vb->vaddr + offset, data, len); - sifive_l2_flush64_range(vb->daddr + offset, len); + wave5_flush_l2_cache(vb->daddr + offset, len); return len; } @@ -137,15 +139,15 @@ int wave5_vdi_allocate_dma_memory(struct vpu_device *vpu_dev, struct vpu_buf *vb vb->vaddr = vaddr; vb->daddr = daddr; - sifive_l2_flush64_range(daddr, vb->size); + wave5_flush_l2_cache(daddr, vb->size); return 0; } -void wave5_vdi_free_dma_memory(struct vpu_device *vpu_dev, struct vpu_buf *vb) +int wave5_vdi_free_dma_memory(struct vpu_device *vpu_dev, struct vpu_buf *vb) { if (vb->size == 0) - return; + return -EINVAL; if (!vb->vaddr) dev_err(vpu_dev->dev, "%s: requested free of unmapped buffer\n", __func__); @@ -153,97 +155,66 @@ void wave5_vdi_free_dma_memory(struct vpu_device *vpu_dev, struct vpu_buf *vb) dma_free_coherent(vpu_dev->dev, vb->size, vb->vaddr, vb->daddr); memset(vb, 0, sizeof(*vb)); + + return 0; } -unsigned int wave5_vdi_convert_endian(struct vpu_device *vpu_dev, unsigned int endian) +int wave5_vdi_allocate_array(struct vpu_device *vpu_dev, struct vpu_buf *array, unsigned int count, + size_t size) { - if (PRODUCT_CODE_W_SERIES(vpu_dev->product_code)) { - switch (endian) { - case VDI_LITTLE_ENDIAN: - endian = 0x00; - break; - case VDI_BIG_ENDIAN: - endian = 0x0f; - break; - case VDI_32BIT_LITTLE_ENDIAN: - endian = 0x04; - break; - case VDI_32BIT_BIG_ENDIAN: - endian = 0x03; - break; - } - } + struct vpu_buf vb_buf; + int i, ret = 0; - return (endian & 0x0f); -} + vb_buf.size = size; -static void byte_swap(unsigned char *data, size_t len) -{ - unsigned int i; + for (i = 0; i < count; i++) { + if (array[i].size == size) + continue; - for (i = 0; i < len; i += 2) - swap(data[i], data[i + 1]); -} + if (array[i].size != 0) + wave5_vdi_free_dma_memory(vpu_dev, &array[i]); -static void word_swap(unsigned char *data, size_t len) -{ - u16 *ptr = (u16 *)data; - unsigned int i; - size_t size = len / sizeof(uint16_t); + ret = wave5_vdi_allocate_dma_memory(vpu_dev, &vb_buf); + if (ret) + return -ENOMEM; + array[i] = vb_buf; + } + + for (i = count; i < MAX_REG_FRAME; i++) + wave5_vdi_free_dma_memory(vpu_dev, &array[i]); - for (i = 0; i < size; i += 2) - swap(ptr[i], ptr[i + 1]); + return 0; } -static void dword_swap(unsigned char *data, size_t len) +void wave5_vdi_allocate_sram(struct vpu_device *vpu_dev) { - u32 *ptr = (u32 *)data; - size_t size = len / sizeof(u32); - unsigned int i; + struct vpu_buf *vb = &vpu_dev->sram_buf; - for (i = 0; i < size; i += 2) - swap(ptr[i], ptr[i + 1]); -} + if (!vpu_dev->sram_pool || !vpu_dev->sram_size) + return; -static void lword_swap(unsigned char *data, size_t len) -{ - u64 *ptr = (u64 *)data; - size_t size = len / sizeof(uint64_t); - unsigned int i; + if (!vb->vaddr) { + vb->size = vpu_dev->sram_size; + vb->vaddr = gen_pool_dma_alloc(vpu_dev->sram_pool, vb->size, + &vb->daddr); + if (!vb->vaddr) + vb->size = 0; + } - for (i = 0; i < size; i += 2) - swap(ptr[i], ptr[i + 1]); + dev_dbg(vpu_dev->dev, "%s: sram daddr: %pad, size: %zu, vaddr: 0x%p\n", + __func__, &vb->daddr, vb->size, vb->vaddr); } -static void wave5_swap_endian(struct vpu_device *vpu_dev, u8 *data, size_t len, - unsigned int endian) +void wave5_vdi_free_sram(struct vpu_device *vpu_dev) { - int changes; - unsigned int sys_endian = VDI_128BIT_BUS_SYSTEM_ENDIAN; - bool byte_change, word_change, dword_change, lword_change; + struct vpu_buf *vb = &vpu_dev->sram_buf; - if (!PRODUCT_CODE_W_SERIES(vpu_dev->product_code)) { - dev_err(vpu_dev->dev, "unknown product id: %08x\n", vpu_dev->product_code); + if (!vb->size || !vb->vaddr) return; - } - endian = wave5_vdi_convert_endian(vpu_dev, endian); - sys_endian = wave5_vdi_convert_endian(vpu_dev, sys_endian); - if (endian == sys_endian) - return; + if (vb->vaddr) + gen_pool_free(vpu_dev->sram_pool, (unsigned long)vb->vaddr, + vb->size); - changes = endian ^ sys_endian; - byte_change = changes & 0x01; - word_change = ((changes & 0x02) == 0x02); - dword_change = ((changes & 0x04) == 0x04); - lword_change = ((changes & 0x08) == 0x08); - - if (byte_change) - byte_swap(data, len); - if (word_change) - word_swap(data, len); - if (dword_change) - dword_swap(data, len); - if (lword_change) - lword_swap(data, len); + memset(vb, 0, sizeof(*vb)); } diff --git a/drivers/media/platform/chips-media/wave5/wave5-vdi.h b/drivers/media/platform/chips-media/wave5/wave5-vdi.h index 780be5747332..3dbc3376c716 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-vdi.h +++ b/drivers/media/platform/chips-media/wave5/wave5-vdi.h @@ -2,7 +2,7 @@ /* * Wave5 series multi-standard codec IP - low level access functions * - * Copyright (C) 2021 CHIPS&MEDIA INC + * Copyright (C) 2021-2023 CHIPS&MEDIA INC */ #ifndef _VDI_H_ @@ -21,7 +21,7 @@ /* system register write */ #define vpu_write_reg(VPU_INST, ADDR, DATA) wave5_vdi_write_register(VPU_INST, ADDR, DATA) /* system register read */ -#define vpu_read_reg(CORE, ADDR) wave5_vdi_readl(CORE, ADDR) +#define vpu_read_reg(CORE, ADDR) wave5_vdi_read_register(CORE, ADDR) struct vpu_buf { size_t size; @@ -29,39 +29,8 @@ struct vpu_buf { void *vaddr; }; -struct dma_vpu_buf { - size_t size; - dma_addr_t daddr; -}; - -enum endian_mode { - VDI_LITTLE_ENDIAN = 0, /* 64bit LE */ - VDI_BIG_ENDIAN, /* 64bit BE */ - VDI_32BIT_LITTLE_ENDIAN, - VDI_32BIT_BIG_ENDIAN, - /* WAVE PRODUCTS */ - VDI_128BIT_LITTLE_ENDIAN = 16, - VDI_128BIT_LE_BYTE_SWAP, - VDI_128BIT_LE_WORD_SWAP, - VDI_128BIT_LE_WORD_BYTE_SWAP, - VDI_128BIT_LE_DWORD_SWAP, - VDI_128BIT_LE_DWORD_BYTE_SWAP, - VDI_128BIT_LE_DWORD_WORD_SWAP, - VDI_128BIT_LE_DWORD_WORD_BYTE_SWAP, - VDI_128BIT_BE_DWORD_WORD_BYTE_SWAP, - VDI_128BIT_BE_DWORD_WORD_SWAP, - VDI_128BIT_BE_DWORD_BYTE_SWAP, - VDI_128BIT_BE_DWORD_SWAP, - VDI_128BIT_BE_WORD_BYTE_SWAP, - VDI_128BIT_BE_WORD_SWAP, - VDI_128BIT_BE_BYTE_SWAP, - VDI_128BIT_BIG_ENDIAN = 31, - VDI_ENDIAN_MAX -}; - -#define VDI_128BIT_ENDIAN_MASK 0xf - int wave5_vdi_init(struct device *dev); int wave5_vdi_release(struct device *dev); //this function may be called only at system off. +void wave5_flush_l2_cache(unsigned long start, unsigned long len); #endif //#ifndef _VDI_H_ diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c b/drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c index b5ee9f270343..7a8d0ea9193c 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c +++ b/drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c @@ -2,15 +2,17 @@ /* * Wave5 series multi-standard codec IP - decoder interface * - * Copyright (C) 2021 CHIPS&MEDIA INC + * Copyright (C) 2021-2023 CHIPS&MEDIA INC */ #include "wave5-helper.h" -#include <soc/sifive/sifive_l2_cache.h> #define VPU_DEC_DEV_NAME "C&M Wave5 VPU decoder" #define VPU_DEC_DRV_NAME "wave5-dec" -#define V4L2_CID_VPU_THUMBNAIL_MODE (V4L2_CID_USER_BASE + 0x1001) + +#define DEFAULT_SRC_SIZE(width, height) ({ \ + (width) * (height) / 8 * 3; \ +}) static const struct vpu_format dec_fmt_list[FMT_TYPES][MAX_FMTS] = { [VPU_FMT_TYPE_CODEC] = { @@ -75,152 +77,146 @@ static const struct vpu_format dec_fmt_list[FMT_TYPES][MAX_FMTS] = { } }; -static enum wave_std wave5_to_vpu_codstd(unsigned int v4l2_pix_fmt) +/* + * Make sure that the state switch is allowed and add logging for debugging + * purposes + */ +static int switch_state(struct vpu_instance *inst, enum vpu_instance_state state) { - switch (v4l2_pix_fmt) { - case V4L2_PIX_FMT_H264: - return W_AVC_DEC; - case V4L2_PIX_FMT_HEVC: - return W_HEVC_DEC; - default: - return STD_UNKNOWN; + switch (state) { + case VPU_INST_STATE_NONE: + break; + case VPU_INST_STATE_OPEN: + if (inst->state != VPU_INST_STATE_NONE) + goto invalid_state_switch; + goto valid_state_switch; + case VPU_INST_STATE_INIT_SEQ: + if (inst->state != VPU_INST_STATE_OPEN && inst->state != VPU_INST_STATE_STOP) + goto invalid_state_switch; + goto valid_state_switch; + case VPU_INST_STATE_PIC_RUN: + if (inst->state != VPU_INST_STATE_INIT_SEQ) + goto invalid_state_switch; + goto valid_state_switch; + case VPU_INST_STATE_STOP: + goto valid_state_switch; } +invalid_state_switch: + WARN(1, "Invalid state switch from %s to %s.\n", + state_to_str(inst->state), state_to_str(state)); + return -EINVAL; +valid_state_switch: + dev_dbg(inst->dev->dev, "Switch state from %s to %s.\n", + state_to_str(inst->state), state_to_str(state)); + inst->state = state; + return 0; } -static void wave5_handle_bitstream_buffer(struct vpu_instance *inst) +static int wave5_vpu_dec_set_eos_on_firmware(struct vpu_instance *inst) { - struct v4l2_m2m_buffer *buf, *n; int ret; - v4l2_m2m_for_each_src_buf_safe(inst->v4l2_fh.m2m_ctx, buf, n) { - struct vb2_v4l2_buffer *vbuf = &buf->vb; - struct vpu_buffer *vpu_buf = wave5_to_vpu_buf(vbuf); - size_t src_size = vb2_get_plane_payload(&vbuf->vb2_buf, 0); - void *src_buf = vb2_plane_vaddr(&vbuf->vb2_buf, 0); - dma_addr_t rd_ptr = 0; - dma_addr_t wr_ptr = 0; - size_t remain_size = 0; - size_t offset; + ret = wave5_vpu_dec_update_bitstream_buffer(inst, 0); + if (ret) { + /* + * To set the EOS flag, a command is sent to the firmware. + * That command may never return (timeout) or may report an error. + */ + dev_err(inst->dev->dev, + "Setting EOS for the bitstream, fail: %d\n", ret); + return ret; + } + return 0; +} - if (src_size == vb2_plane_size(&vbuf->vb2_buf, 0)) - src_size = 0; +static bool wave5_last_src_buffer_consumed(struct v4l2_m2m_ctx *m2m_ctx) +{ + struct vpu_src_buffer *vpu_buf; - if (vpu_buf->consumed) { - dev_dbg(inst->dev->dev, "already consumed src buf (%u)\n", - vbuf->vb2_buf.index); - continue; - } + if (!m2m_ctx->last_src_buf) + return false; - if (!src_buf) { - dev_dbg(inst->dev->dev, - "%s: Acquiring kernel pointer to src buf (%u), fail\n", - __func__, vbuf->vb2_buf.index); - break; - } + vpu_buf = wave5_to_vpu_src_buf(m2m_ctx->last_src_buf); + return vpu_buf->consumed; +} - ret = wave5_vpu_dec_get_bitstream_buffer(inst, &rd_ptr, &wr_ptr, &remain_size); - if (ret) { - dev_err(inst->dev->dev, "Getting the bitstream buffer, fail: %d\n", - ret); - return; - } +static void wave5_handle_src_buffer(struct vpu_instance *inst, dma_addr_t rd_ptr) +{ + struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx; + struct v4l2_m2m_buffer *buf, *n; + size_t consumed_bytes = 0; + int i, j, ret; + u64 flag; - if (remain_size < src_size) { - dev_dbg(inst->dev->dev, - "%s: remaining size: %zu < source size: %zu for src buf (%u)\n", - __func__, remain_size, src_size, vbuf->vb2_buf.index); - break; - } + if (rd_ptr >= inst->last_rd_ptr) { + consumed_bytes = rd_ptr - inst->last_rd_ptr; + } else { + size_t rd_offs = rd_ptr - inst->bitstream_vbuf.daddr; + size_t last_rd_offs = inst->last_rd_ptr - inst->bitstream_vbuf.daddr; - offset = wr_ptr - inst->bitstream_vbuf.daddr; - if (wr_ptr + src_size > inst->bitstream_vbuf.daddr + inst->bitstream_vbuf.size) { - size_t size; - - size = inst->bitstream_vbuf.daddr + inst->bitstream_vbuf.size - wr_ptr; - ret = wave5_vdi_write_memory(inst->dev, &inst->bitstream_vbuf, offset, - (u8 *)src_buf, size, VDI_128BIT_LITTLE_ENDIAN); - if (ret < 0) { - dev_dbg(inst->dev->dev, - "%s: 1/2 write src buf (%u) into bitstream buf, fail: %d\n", - __func__, vbuf->vb2_buf.index, ret); - break; - } - ret = wave5_vdi_write_memory(inst->dev, &inst->bitstream_vbuf, 0, - (u8 *)src_buf + size, src_size - size, - VDI_128BIT_LITTLE_ENDIAN); - if (ret < 0) { - dev_dbg(inst->dev->dev, - "%s: 2/2 write src buf (%u) into bitstream buf, fail: %d\n", - __func__, vbuf->vb2_buf.index, ret); - break; - } - } else { - ret = wave5_vdi_write_memory(inst->dev, &inst->bitstream_vbuf, offset, - (u8 *)src_buf, src_size, - VDI_128BIT_LITTLE_ENDIAN); - if (ret < 0) { - dev_dbg(inst->dev->dev, - "%s: write src buf (%u) into bitstream buf, fail: %d", - __func__, vbuf->vb2_buf.index, ret); - break; - } - } + consumed_bytes = rd_offs + (inst->bitstream_vbuf.size - last_rd_offs); + } - ret = wave5_vpu_dec_update_bitstream_buffer(inst, src_size); - if (ret) { - dev_dbg(inst->dev->dev, - "vpu_dec_update_bitstream_buffer fail: %d for src buf (%u)\n", - ret, vbuf->vb2_buf.index); - break; - } + inst->last_rd_ptr = rd_ptr; + consumed_bytes += inst->remaining_consumed_bytes; - vpu_buf->consumed = true; - } -} + dev_dbg(inst->dev->dev, "%s: %zu bytes of bitstream was consumed", __func__, + consumed_bytes); -static void wave5_handle_src_buffer(struct vpu_instance *inst) -{ - struct vb2_v4l2_buffer *src_buf; - int i, j, ret; - u64 flag; + v4l2_m2m_for_each_src_buf_safe(m2m_ctx, buf, n) { + struct vb2_v4l2_buffer *src_buf = &buf->vb; + size_t src_size = vb2_get_plane_payload(&src_buf->vb2_buf, 0); - src_buf = v4l2_m2m_next_src_buf(inst->v4l2_fh.m2m_ctx); - if (src_buf) { - struct vpu_buffer *vpu_buf = wave5_to_vpu_buf(src_buf); + if (src_size > consumed_bytes) + break; - if (vpu_buf->consumed) { - dev_dbg(inst->dev->dev, "%s: already consumed buffer\n", __func__); - src_buf = v4l2_m2m_src_buf_remove(inst->v4l2_fh.m2m_ctx); + dev_dbg(inst->dev->dev, "%s: removing src buffer %i", + __func__, src_buf->vb2_buf.index); + src_buf = v4l2_m2m_src_buf_remove(m2m_ctx); - if (!inst->monotonic_timestamp && !src_buf->vb2_buf.timestamp) { - inst->timestamp_zero_cnt++; - if (inst->timestamp_zero_cnt > 1) { - inst->monotonic_timestamp = TRUE; - } + if (!inst->monotonic_timestamp && !src_buf->vb2_buf.timestamp) { + inst->timestamp_zero_cnt++; + if (inst->timestamp_zero_cnt > 1) { + inst->monotonic_timestamp = TRUE; } + } - if(!inst->monotonic_timestamp) { - ret = mutex_lock_interruptible(&inst->time_stamp.lock); - if (ret) { - dev_err(inst->dev->dev, "%s: lock err\n", __func__); - return; - } - inst->time_stamp.buf[inst->time_stamp.cnt] = src_buf->vb2_buf.timestamp; - inst->time_stamp.cnt++; - - for (i = 1; i < inst->time_stamp.cnt; i++) { - flag = inst->time_stamp.buf[i]; - for (j = i - 1; j >= 0 && inst->time_stamp.buf[j] < flag ; j--) { - inst->time_stamp.buf[j + 1] = inst->time_stamp.buf[j]; - } - inst->time_stamp.buf[j + 1] = flag; + if(!inst->monotonic_timestamp) { + ret = mutex_lock_interruptible(&inst->time_stamp.lock); + if (ret) { + dev_err(inst->dev->dev, "%s: lock err\n", __func__); + return; + } + inst->time_stamp.buf[inst->time_stamp.cnt] = src_buf->vb2_buf.timestamp; + inst->time_stamp.cnt++; + + for (i = 1; i < inst->time_stamp.cnt; i++) { + flag = inst->time_stamp.buf[i]; + for (j = i - 1; j >= 0 && inst->time_stamp.buf[j] < flag ; j--) { + inst->time_stamp.buf[j + 1] = inst->time_stamp.buf[j]; } - mutex_unlock(&inst->time_stamp.lock); + inst->time_stamp.buf[j + 1] = flag; } + mutex_unlock(&inst->time_stamp.lock); + } + + v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE); + consumed_bytes -= src_size; - v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE); + /* Handle the case the last bitstream buffer has been picked */ + if (src_buf == m2m_ctx->last_src_buf) { + int ret; + + m2m_ctx->last_src_buf = NULL; + ret = wave5_vpu_dec_set_eos_on_firmware(inst); + if (ret) + dev_warn(inst->dev->dev, + "Setting EOS for the bitstream, fail: %d\n", ret); + break; } } + + inst->remaining_consumed_bytes = consumed_bytes; } static void wave5_update_pix_fmt(struct v4l2_pix_format_mplane *pix_mp, unsigned int width, @@ -235,6 +231,14 @@ static void wave5_update_pix_fmt(struct v4l2_pix_format_mplane *pix_mp, unsigned pix_mp->plane_fmt[0].bytesperline = round_up(width, 32); pix_mp->plane_fmt[0].sizeimage = width * height * 3 / 2; break; + case V4L2_PIX_FMT_YUV422P: + case V4L2_PIX_FMT_NV16: + case V4L2_PIX_FMT_NV61: + pix_mp->width = round_up(width, 32); + pix_mp->height = round_up(height, 16); + pix_mp->plane_fmt[0].bytesperline = round_up(width, 32); + pix_mp->plane_fmt[0].sizeimage = width * height * 2; + break; case V4L2_PIX_FMT_YUV420M: pix_mp->width = round_up(width, 32); pix_mp->height = round_up(height, 16); @@ -254,6 +258,25 @@ static void wave5_update_pix_fmt(struct v4l2_pix_format_mplane *pix_mp, unsigned pix_mp->plane_fmt[1].bytesperline = round_up(width, 32); pix_mp->plane_fmt[1].sizeimage = width * height / 2; break; + case V4L2_PIX_FMT_YUV422M: + pix_mp->width = round_up(width, 32); + pix_mp->height = round_up(height, 16); + pix_mp->plane_fmt[0].bytesperline = round_up(width, 32); + pix_mp->plane_fmt[0].sizeimage = width * height; + pix_mp->plane_fmt[1].bytesperline = round_up(width, 32) / 2; + pix_mp->plane_fmt[1].sizeimage = width * height / 2; + pix_mp->plane_fmt[2].bytesperline = round_up(width, 32) / 2; + pix_mp->plane_fmt[2].sizeimage = width * height / 2; + break; + case V4L2_PIX_FMT_NV16M: + case V4L2_PIX_FMT_NV61M: + pix_mp->width = round_up(width, 32); + pix_mp->height = round_up(height, 16); + pix_mp->plane_fmt[0].bytesperline = round_up(width, 32); + pix_mp->plane_fmt[0].sizeimage = width * height; + pix_mp->plane_fmt[1].bytesperline = round_up(width, 32); + pix_mp->plane_fmt[1].sizeimage = width * height; + break; default: pix_mp->width = width; pix_mp->height = height; @@ -263,185 +286,244 @@ static void wave5_update_pix_fmt(struct v4l2_pix_format_mplane *pix_mp, unsigned } } -static void wave5_vpu_dec_start_decode(struct vpu_instance *inst) +static int start_decode(struct vpu_instance *inst, u32 *fail_res) { - struct dec_param pic_param; - int ret; - u32 fail_res = 0; + struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx; + int ret = 0; - memset(&pic_param, 0, sizeof(struct dec_param)); + ret = wave5_vpu_dec_start_one_frame(inst, fail_res); + if (ret) { + struct vb2_v4l2_buffer *src_buf; - if (inst->state == VPU_INST_STATE_INIT_SEQ) { - u32 non_linear_num = inst->dst_buf_count; - u32 linear_num = inst->dst_buf_count; - u32 stride = inst->dst_fmt.width; + src_buf = v4l2_m2m_src_buf_remove(m2m_ctx); + if (src_buf) + v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_ERROR); + switch_state(inst, VPU_INST_STATE_STOP); - ret = wave5_vpu_dec_register_frame_buffer_ex(inst, non_linear_num, linear_num, - stride, inst->dst_fmt.height, - COMPRESSED_FRAME_MAP); - if (ret) - dev_dbg(inst->dev->dev, "%s: vpu_dec_register_frame_buffer_ex fail: %d", - __func__, ret); + dev_dbg(inst->dev->dev, "%s: pic run failed / finish job", __func__); + v4l2_m2m_job_finish(inst->v4l2_m2m_dev, m2m_ctx); } - ret = wave5_vpu_dec_start_one_frame(inst, &pic_param, &fail_res); - if (ret && fail_res != WAVE5_SYSERR_QUEUEING_FAIL) { - struct vb2_v4l2_buffer *src_buf; + return ret; +} - src_buf = v4l2_m2m_src_buf_remove(inst->v4l2_fh.m2m_ctx); - inst->state = VPU_INST_STATE_STOP; - v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_ERROR); +static void flag_last_buffer_done(struct vpu_instance *inst) +{ + struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx; + struct vb2_v4l2_buffer *vb; + int i; + + lockdep_assert_held(&inst->state_spinlock); + + vb = v4l2_m2m_dst_buf_remove(m2m_ctx); + if (!vb) { + m2m_ctx->is_draining = true; + m2m_ctx->next_buf_last = true; + return; } + + for (i = 0; i < vb->vb2_buf.num_planes; i++) + vb2_set_plane_payload(&vb->vb2_buf, i, 0); + vb->field = V4L2_FIELD_NONE; + + v4l2_m2m_last_buffer_done(m2m_ctx, vb); } -static void wave5_vpu_dec_stop_decode(struct vpu_instance *inst) +static void send_eos_event(struct vpu_instance *inst) { - unsigned int i; - int ret; + static const struct v4l2_event vpu_event_eos = { + .type = V4L2_EVENT_EOS + }; - inst->state = VPU_INST_STATE_STOP; + lockdep_assert_held(&inst->state_spinlock); - ret = wave5_vpu_dec_update_bitstream_buffer(inst, 0); - if (ret) { - dev_warn(inst->dev->dev, - "Setting EOS for the bitstream, fail: %d\n", ret); + v4l2_event_queue_fh(&inst->v4l2_fh, &vpu_event_eos); + inst->eos = false; +} + +static int handle_dynamic_resolution_change(struct vpu_instance *inst) +{ + struct v4l2_fh *fh = &inst->v4l2_fh; + struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx; + + static const struct v4l2_event vpu_event_src_ch = { + .type = V4L2_EVENT_SOURCE_CHANGE, + .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION, + }; + struct dec_info *p_dec_info = &inst->codec_info->dec_info; + struct dec_initial_info *initial_info = &inst->codec_info->dec_info.initial_info; + + lockdep_assert_held(&inst->state_spinlock); + + dev_dbg(inst->dev->dev, "%s: rd_ptr %pad", __func__, &initial_info->rd_ptr); + + dev_dbg(inst->dev->dev, "%s: width: %u height: %u profile: %u | minbuffer: %u\n", + __func__, initial_info->pic_width, initial_info->pic_height, + initial_info->profile, initial_info->min_frame_buffer_count); + + inst->needs_reallocation = true; + inst->fbc_buf_count = initial_info->min_frame_buffer_count + 1; + if (inst->fbc_buf_count != v4l2_m2m_num_dst_bufs_ready(m2m_ctx)) { + struct v4l2_ctrl *ctrl; + + ctrl = v4l2_ctrl_find(&inst->v4l2_ctrl_hdl, + V4L2_CID_MIN_BUFFERS_FOR_CAPTURE); + if (ctrl) + v4l2_ctrl_s_ctrl(ctrl, inst->fbc_buf_count); } - for (i = 0; i < inst->dst_buf_count; i++) { - ret = wave5_vpu_dec_clr_disp_flag(inst, i); - if (ret) { - dev_dbg(inst->dev->dev, - "%s: Clearing the display flag of buffer index: %u, fail: %d\n", - __func__, i, ret); - } + if (p_dec_info->initial_info_obtained) { + inst->conf_win.left = initial_info->pic_crop_rect.left; + inst->conf_win.top = initial_info->pic_crop_rect.top; + inst->conf_win.width = initial_info->pic_width - + initial_info->pic_crop_rect.left - initial_info->pic_crop_rect.right; + inst->conf_win.height = initial_info->pic_height - + initial_info->pic_crop_rect.top - initial_info->pic_crop_rect.bottom; + + //wave5_update_pix_fmt(&inst->src_fmt, initial_info->pic_width, + // initial_info->pic_height); + wave5_update_pix_fmt(&inst->dst_fmt, initial_info->pic_width, + initial_info->pic_height); } - v4l2_m2m_job_finish(inst->v4l2_m2m_dev, inst->v4l2_fh.m2m_ctx); + v4l2_event_queue_fh(fh, &vpu_event_src_ch); + + return 0; } static void wave5_vpu_dec_finish_decode(struct vpu_instance *inst) { - struct dec_output_info dec_output_info; + struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx; + struct dec_output_info dec_info; int ret; - u32 irq_status; + struct vb2_v4l2_buffer *dec_buf = NULL; + struct vb2_v4l2_buffer *disp_buf = NULL; + struct vb2_queue *dst_vq = v4l2_m2m_get_dst_vq(m2m_ctx); + struct queue_status_info q_status; u32 stride, height; - if (kfifo_out(&inst->irq_status, &irq_status, sizeof(int))) - wave5_vpu_clear_interrupt_ex(inst, irq_status); + dev_dbg(inst->dev->dev, "%s: Fetch output info from firmware.", __func__); - ret = wave5_vpu_dec_get_output_info(inst, &dec_output_info); + ret = wave5_vpu_dec_get_output_info(inst, &dec_info); if (ret) { - v4l2_m2m_job_finish(inst->v4l2_m2m_dev, inst->v4l2_fh.m2m_ctx); + dev_warn(inst->dev->dev, "%s: could not get output info.", __func__); + v4l2_m2m_job_finish(inst->v4l2_m2m_dev, m2m_ctx); return; } - if (dec_output_info.index_frame_decoded == DECODED_IDX_FLAG_NO_FB && - dec_output_info.index_frame_display == DISPLAY_IDX_FLAG_NO_FB) { - dev_dbg(inst->dev->dev, "%s: no more frame buffer\n", __func__); - } else { - wave5_handle_src_buffer(inst); - if (dec_output_info.index_frame_display >= 0) { - struct vb2_v4l2_buffer *dst_buf = - v4l2_m2m_dst_buf_remove_by_idx(inst->v4l2_fh.m2m_ctx, - dec_output_info.index_frame_display); + dev_dbg(inst->dev->dev, "%s: rd_ptr %pad wr_ptr %pad", __func__, &dec_info.rd_ptr, + &dec_info.wr_ptr); + wave5_handle_src_buffer(inst, dec_info.rd_ptr); - if (!dst_buf) { - dev_dbg(inst->dev->dev,"find no dst_buf \n"); - return; - } + dev_dbg(inst->dev->dev, "%s: dec_info dec_idx %i disp_idx %i", __func__, + dec_info.index_frame_decoded, dec_info.index_frame_display); - stride = dec_output_info.disp_frame.stride; - height = dec_output_info.disp_pic_height - - dec_output_info.rc_display.bottom; - dev_dbg(inst->dev->dev, "%s %d disp_pic_height %u rc_display.bottom %u\n", - __func__, __LINE__, dec_output_info.disp_pic_height, dec_output_info.rc_display.bottom); - dev_dbg(inst->dev->dev, "%s %d stride %u height %u num %d\n", __func__, __LINE__, stride, height,inst->dst_fmt.num_planes); - - if (inst->dst_fmt.num_planes == 1) { - vb2_set_plane_payload(&dst_buf->vb2_buf, 0, - (stride * height * 3 / 2)); - } else if (inst->dst_fmt.num_planes == 2) { - vb2_set_plane_payload(&dst_buf->vb2_buf, 0, - (stride * height)); - vb2_set_plane_payload(&dst_buf->vb2_buf, 1, - ((stride / 2) * height)); - } else if (inst->dst_fmt.num_planes == 3) { - vb2_set_plane_payload(&dst_buf->vb2_buf, 0, - (stride * height)); - vb2_set_plane_payload(&dst_buf->vb2_buf, 1, - ((stride / 2) * (height / 2))); - vb2_set_plane_payload(&dst_buf->vb2_buf, 2, - ((stride / 2) * (height / 2))); - } + if (!vb2_is_streaming(dst_vq)) { + dev_dbg(inst->dev->dev, "%s: capture is not streaming..", __func__); + v4l2_m2m_job_finish(inst->v4l2_m2m_dev, m2m_ctx); + return; + } - if (!inst->monotonic_timestamp) { - ret = mutex_lock_interruptible(&inst->time_stamp.lock); - if (ret) { - dev_err(inst->dev->dev, "%s: lock err\n", __func__); - return; - } - dst_buf->vb2_buf.timestamp = inst->time_stamp.buf[inst->time_stamp.cnt - 1]; - inst->time_stamp.cnt--; - mutex_unlock(&inst->time_stamp.lock); - } else { - dst_buf->vb2_buf.timestamp = inst->timestamp_cnt++ * inst->codec_info->dec_info.initial_info.ns_per_frame; - } + /* Remove decoded buffer from the ready queue now that it has been + * decoded. + */ + if (dec_info.index_frame_decoded >= 0) { + struct vb2_buffer *vb = vb2_get_buffer(dst_vq, + dec_info.index_frame_decoded); + if (vb) { + dec_buf = to_vb2_v4l2_buffer(vb); + } else { + dev_warn(inst->dev->dev, "%s: invalid decoded frame index %i", + __func__, dec_info.index_frame_decoded); + } + } - dst_buf->field = V4L2_FIELD_NONE; - v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_DONE); + if (dec_info.index_frame_display >= 0) { + disp_buf = v4l2_m2m_dst_buf_remove_by_idx(m2m_ctx, dec_info.index_frame_display); + if (!disp_buf) + dev_warn(inst->dev->dev, "%s: invalid display frame index %i", + __func__, dec_info.index_frame_display); + } - dev_dbg(inst->dev->dev, "%s: frame_cycle %8u\n", - __func__, dec_output_info.frame_cycle); - } else if (dec_output_info.index_frame_display == DISPLAY_IDX_FLAG_SEQ_END && - !inst->eos) { - static const struct v4l2_event vpu_event_eos = { - .type = V4L2_EVENT_EOS - }; - struct vb2_v4l2_buffer *dst_buf = - v4l2_m2m_dst_buf_remove(inst->v4l2_fh.m2m_ctx); + /* If there is anything to display, do that now */ + if (disp_buf) { + struct vpu_dst_buffer *dst_vpu_buf = wave5_to_vpu_dst_buf(disp_buf); + stride = dec_info.disp_frame.stride; + height = dec_info.disp_pic_height - + dec_info.rc_display.bottom; + dev_dbg(inst->dev->dev, "%s %d disp_pic_height %u rc_display.bottom %u\n", + __func__, __LINE__, dec_info.disp_pic_height, dec_info.rc_display.bottom); + dev_dbg(inst->dev->dev, "%s %d stride %u height %u num %d\n", __func__, __LINE__, stride, height,inst->dst_fmt.num_planes); - if (!dst_buf) - return; + if (inst->dst_fmt.num_planes == 1) { + vb2_set_plane_payload(&disp_buf->vb2_buf, 0, + (stride * height * 3 / 2)); + } else if (inst->dst_fmt.num_planes == 2) { + vb2_set_plane_payload(&disp_buf->vb2_buf, 0, + (stride * height)); + vb2_set_plane_payload(&disp_buf->vb2_buf, 1, + ((stride / 2) * height)); + } else if (inst->dst_fmt.num_planes == 3) { + vb2_set_plane_payload(&disp_buf->vb2_buf, 0, + (stride * height)); + vb2_set_plane_payload(&disp_buf->vb2_buf, 1, + ((stride / 2) * (height / 2))); + vb2_set_plane_payload(&disp_buf->vb2_buf, 2, + ((stride / 2) * (height / 2))); + } - if (inst->dst_fmt.num_planes == 1) { - vb2_set_plane_payload(&dst_buf->vb2_buf, 0, - vb2_plane_size(&dst_buf->vb2_buf, 0)); - } else if (inst->dst_fmt.num_planes == 2) { - vb2_set_plane_payload(&dst_buf->vb2_buf, 0, - vb2_plane_size(&dst_buf->vb2_buf, 0)); - vb2_set_plane_payload(&dst_buf->vb2_buf, 1, - vb2_plane_size(&dst_buf->vb2_buf, 1)); - } else if (inst->dst_fmt.num_planes == 3) { - vb2_set_plane_payload(&dst_buf->vb2_buf, 0, - vb2_plane_size(&dst_buf->vb2_buf, 0)); - vb2_set_plane_payload(&dst_buf->vb2_buf, 1, - vb2_plane_size(&dst_buf->vb2_buf, 1)); - vb2_set_plane_payload(&dst_buf->vb2_buf, 2, - vb2_plane_size(&dst_buf->vb2_buf, 2)); - } + /* TODO implement interlace support */ + disp_buf->field = V4L2_FIELD_NONE; + dst_vpu_buf->display = true; - if (!inst->monotonic_timestamp) { - ret = mutex_lock_interruptible(&inst->time_stamp.lock); - if (ret) { - dev_err(inst->dev->dev, "%s: lock err\n", __func__); - return; - } - dst_buf->vb2_buf.timestamp = inst->time_stamp.buf[inst->time_stamp.cnt - 1]; - inst->time_stamp.cnt--; - mutex_unlock(&inst->time_stamp.lock); - } else { - dst_buf->vb2_buf.timestamp = inst->timestamp_cnt++ * inst->codec_info->dec_info.initial_info.ns_per_frame; + if (!inst->monotonic_timestamp) { + ret = mutex_lock_interruptible(&inst->time_stamp.lock); + if (ret) { + dev_err(inst->dev->dev, "%s: lock err\n", __func__); + return; } + disp_buf->vb2_buf.timestamp = inst->time_stamp.buf[inst->time_stamp.cnt - 1]; + inst->time_stamp.cnt--; + mutex_unlock(&inst->time_stamp.lock); + } else { + disp_buf->vb2_buf.timestamp = inst->timestamp_cnt++ * inst->codec_info->dec_info.initial_info.ns_per_frame; + } + + v4l2_m2m_buf_done(disp_buf, VB2_BUF_STATE_DONE); + + dev_dbg(inst->dev->dev, "%s: frame_cycle %8u (payload %lu)\n", + __func__, dec_info.frame_cycle, + vb2_get_plane_payload(&disp_buf->vb2_buf, 0)); + } + + if ((dec_info.index_frame_display == DISPLAY_IDX_FLAG_SEQ_END || + dec_info.sequence_changed)) { + unsigned long flags; - dst_buf->flags |= V4L2_BUF_FLAG_LAST; - dst_buf->field = V4L2_FIELD_NONE; - v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_DONE); + spin_lock_irqsave(&inst->state_spinlock, flags); + if (!v4l2_m2m_has_stopped(m2m_ctx)) { + switch_state(inst, VPU_INST_STATE_STOP); - inst->eos = TRUE; - v4l2_event_queue_fh(&inst->v4l2_fh, &vpu_event_eos); + if (dec_info.sequence_changed) + handle_dynamic_resolution_change(inst); + else + send_eos_event(inst); - v4l2_m2m_job_finish(inst->v4l2_m2m_dev, inst->v4l2_fh.m2m_ctx); + flag_last_buffer_done(inst); } + spin_unlock_irqrestore(&inst->state_spinlock, flags); + } + + /* + * During a resolution change and while draining, the firmware may flush + * the reorder queue regardless of having a matching decoding operation + * pending. Only terminate the job if there are no more IRQ coming. + */ + wave5_vpu_dec_give_command(inst, DEC_GET_QUEUE_STATUS, &q_status); + if (q_status.report_queue_count == 0 && + (q_status.instance_queue_count == 0 || dec_info.sequence_changed)) { + dev_dbg(inst->dev->dev, "%s: finishing job.\n", __func__); + v4l2_m2m_job_finish(inst->v4l2_m2m_dev, m2m_ctx); } } @@ -449,7 +531,6 @@ static int wave5_vpu_dec_querycap(struct file *file, void *fh, struct v4l2_capab { strscpy(cap->driver, VPU_DEC_DRV_NAME, sizeof(cap->driver)); strscpy(cap->card, VPU_DEC_DRV_NAME, sizeof(cap->card)); - strscpy(cap->bus_info, "platform:" VPU_DEC_DRV_NAME, sizeof(cap->bus_info)); return 0; } @@ -496,39 +577,45 @@ static int wave5_vpu_dec_enum_fmt_cap(struct file *file, void *fh, struct v4l2_f static int wave5_vpu_dec_try_fmt_cap(struct file *file, void *fh, struct v4l2_format *f) { struct vpu_instance *inst = wave5_to_vpu_inst(fh); + struct dec_info *p_dec_info = &inst->codec_info->dec_info; + struct dec_initial_info *initial_info; const struct vpu_format *vpu_fmt; + int width, height; dev_dbg(inst->dev->dev, "%s: fourcc: %u width: %u height: %u nm planes: %u colorspace: %u field: %u\n", __func__, f->fmt.pix_mp.pixelformat, f->fmt.pix_mp.width, f->fmt.pix_mp.height, f->fmt.pix_mp.num_planes, f->fmt.pix_mp.colorspace, f->fmt.pix_mp.field); - if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) - return -EINVAL; - vpu_fmt = wave5_find_vpu_fmt(f->fmt.pix_mp.pixelformat, dec_fmt_list[VPU_FMT_TYPE_RAW]); if (!vpu_fmt) { + width = inst->dst_fmt.width; + height = inst->dst_fmt.height; f->fmt.pix_mp.pixelformat = inst->dst_fmt.pixelformat; f->fmt.pix_mp.num_planes = inst->dst_fmt.num_planes; - wave5_update_pix_fmt(&f->fmt.pix_mp, inst->dst_fmt.width, inst->dst_fmt.height); } else { - int width = clamp(f->fmt.pix_mp.width, vpu_fmt->min_width, vpu_fmt->max_width); - int height = clamp(f->fmt.pix_mp.height, vpu_fmt->min_height, vpu_fmt->max_height); const struct v4l2_format_info *info = v4l2_format_info(vpu_fmt->v4l2_pix_fmt); + width = clamp(f->fmt.pix_mp.width, vpu_fmt->min_width, vpu_fmt->max_width); + height = clamp(f->fmt.pix_mp.height, vpu_fmt->min_height, vpu_fmt->max_height); f->fmt.pix_mp.pixelformat = vpu_fmt->v4l2_pix_fmt; f->fmt.pix_mp.num_planes = info->mem_planes; - wave5_update_pix_fmt(&f->fmt.pix_mp, width, height); } + if (p_dec_info->initial_info_obtained) { + initial_info = &inst->codec_info->dec_info.initial_info; + width = inst->dst_fmt.width; + height = initial_info->pic_height - + initial_info->pic_crop_rect.top - initial_info->pic_crop_rect.bottom; + } + + wave5_update_pix_fmt(&f->fmt.pix_mp, width, height); f->fmt.pix_mp.flags = 0; f->fmt.pix_mp.field = V4L2_FIELD_NONE; f->fmt.pix_mp.colorspace = inst->colorspace; f->fmt.pix_mp.ycbcr_enc = inst->ycbcr_enc; - f->fmt.pix_mp.hsv_enc = inst->hsv_enc; f->fmt.pix_mp.quantization = inst->quantization; f->fmt.pix_mp.xfer_func = inst->xfer_func; - memset(&f->fmt.pix_mp.reserved, 0, sizeof(f->fmt.pix_mp.reserved)); return 0; } @@ -562,13 +649,31 @@ static int wave5_vpu_dec_s_fmt_cap(struct file *file, void *fh, struct v4l2_form inst->dst_fmt.pixelformat == V4L2_PIX_FMT_NV12M) { inst->cbcr_interleave = true; inst->nv21 = false; + inst->output_format = FORMAT_420; } else if (inst->dst_fmt.pixelformat == V4L2_PIX_FMT_NV21 || inst->dst_fmt.pixelformat == V4L2_PIX_FMT_NV21M) { inst->cbcr_interleave = true; inst->nv21 = true; + inst->output_format = FORMAT_420; + } else if (inst->dst_fmt.pixelformat == V4L2_PIX_FMT_NV16 || + inst->dst_fmt.pixelformat == V4L2_PIX_FMT_NV16M) { + inst->cbcr_interleave = true; + inst->nv21 = false; + inst->output_format = FORMAT_422; + } else if (inst->dst_fmt.pixelformat == V4L2_PIX_FMT_NV61 || + inst->dst_fmt.pixelformat == V4L2_PIX_FMT_NV61M) { + inst->cbcr_interleave = true; + inst->nv21 = true; + inst->output_format = FORMAT_422; + } else if (inst->dst_fmt.pixelformat == V4L2_PIX_FMT_YUV422P || + inst->dst_fmt.pixelformat == V4L2_PIX_FMT_YUV422M) { + inst->cbcr_interleave = false; + inst->nv21 = false; + inst->output_format = FORMAT_422; } else { inst->cbcr_interleave = false; inst->nv21 = false; + inst->output_format = FORMAT_420; } return 0; @@ -592,7 +697,6 @@ static int wave5_vpu_dec_g_fmt_cap(struct file *file, void *fh, struct v4l2_form f->fmt.pix_mp.colorspace = inst->colorspace; f->fmt.pix_mp.ycbcr_enc = inst->ycbcr_enc; - f->fmt.pix_mp.hsv_enc = inst->hsv_enc; f->fmt.pix_mp.quantization = inst->quantization; f->fmt.pix_mp.xfer_func = inst->xfer_func; @@ -611,7 +715,7 @@ static int wave5_vpu_dec_enum_fmt_out(struct file *file, void *fh, struct v4l2_f return -EINVAL; f->pixelformat = vpu_fmt->v4l2_pix_fmt; - f->flags = 0; + f->flags = V4L2_FMT_FLAG_DYN_RESOLUTION | V4L2_FMT_FLAG_COMPRESSED; return 0; } @@ -626,9 +730,6 @@ static int wave5_vpu_dec_try_fmt_out(struct file *file, void *fh, struct v4l2_fo __func__, f->fmt.pix_mp.pixelformat, f->fmt.pix_mp.width, f->fmt.pix_mp.height, f->fmt.pix_mp.num_planes, f->fmt.pix_mp.colorspace, f->fmt.pix_mp.field); - if (f->type != V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) - return -EINVAL; - vpu_fmt = wave5_find_vpu_fmt(f->fmt.pix_mp.pixelformat, dec_fmt_list[VPU_FMT_TYPE_CODEC]); if (!vpu_fmt) { f->fmt.pix_mp.pixelformat = inst->src_fmt.pixelformat; @@ -645,7 +746,6 @@ static int wave5_vpu_dec_try_fmt_out(struct file *file, void *fh, struct v4l2_fo f->fmt.pix_mp.flags = 0; f->fmt.pix_mp.field = V4L2_FIELD_NONE; - memset(&f->fmt.pix_mp.reserved, 0, sizeof(f->fmt.pix_mp.reserved)); return 0; } @@ -664,6 +764,13 @@ static int wave5_vpu_dec_s_fmt_out(struct file *file, void *fh, struct v4l2_form if (ret) return ret; + inst->std = wave5_to_vpu_std(f->fmt.pix_mp.pixelformat, inst->type); + if (inst->std == STD_UNKNOWN) { + dev_warn(inst->dev->dev, "unsupported pixelformat: %.4s\n", + (char *)&f->fmt.pix_mp.pixelformat); + return -EINVAL; + } + inst->src_fmt.width = f->fmt.pix_mp.width; inst->src_fmt.height = f->fmt.pix_mp.height; inst->src_fmt.pixelformat = f->fmt.pix_mp.pixelformat; @@ -677,7 +784,6 @@ static int wave5_vpu_dec_s_fmt_out(struct file *file, void *fh, struct v4l2_form inst->colorspace = f->fmt.pix_mp.colorspace; inst->ycbcr_enc = f->fmt.pix_mp.ycbcr_enc; - inst->hsv_enc = f->fmt.pix_mp.hsv_enc; inst->quantization = f->fmt.pix_mp.quantization; inst->xfer_func = f->fmt.pix_mp.xfer_func; @@ -707,8 +813,7 @@ static int wave5_vpu_dec_g_selection(struct file *file, void *fh, struct v4l2_se s->r.left = 0; s->r.top = 0; if (inst->state > VPU_INST_STATE_OPEN) { - s->r.width = inst->conf_win_width; - s->r.height = inst->conf_win_height; + s->r = inst->conf_win; } else { s->r.width = inst->src_fmt.width; s->r.height = inst->src_fmt.height; @@ -742,9 +847,100 @@ static int wave5_vpu_dec_s_selection(struct file *file, void *fh, struct v4l2_se return 0; } +static int wave5_vpu_dec_stop(struct vpu_instance *inst) +{ + int ret = 0; + unsigned long flags; + struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx; + + spin_lock_irqsave(&inst->state_spinlock, flags); + + if (m2m_ctx->is_draining) { + ret = -EBUSY; + goto unlock_and_return; + } + + if (inst->state != VPU_INST_STATE_NONE) { + /* + * Temporarily release the state_spinlock so that subsequent + * calls do not block on a mutex while inside this spinlock. + */ + spin_unlock_irqrestore(&inst->state_spinlock, flags); + ret = wave5_vpu_dec_set_eos_on_firmware(inst); + if (ret) + return ret; + + spin_lock_irqsave(&inst->state_spinlock, flags); + /* + * TODO eliminate this check by using a separate check for + * draining triggered by a resolution change. + */ + if (m2m_ctx->is_draining) { + ret = -EBUSY; + goto unlock_and_return; + } + } + + /* + * Used to remember the EOS state after the streamoff/on transition on + * the capture queue. + */ + inst->eos = true; + + if (m2m_ctx->has_stopped) + goto unlock_and_return; + + m2m_ctx->last_src_buf = v4l2_m2m_last_src_buf(m2m_ctx); + m2m_ctx->is_draining = true; + + /* + * Deferred to device run in case it wasn't in the ring buffer + * yet. In other case, we have to send the EOS signal to the + * firmware so that any pending PIC_RUN ends without new + * bitstream buffer. + */ + if (m2m_ctx->last_src_buf) + goto unlock_and_return; + + if (inst->state == VPU_INST_STATE_NONE) { + send_eos_event(inst); + flag_last_buffer_done(inst); + } + +unlock_and_return: + spin_unlock_irqrestore(&inst->state_spinlock, flags); + return ret; +} + +static int wave5_vpu_dec_start(struct vpu_instance *inst) +{ + int ret = 0; + unsigned long flags; + struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx; + struct vb2_queue *dst_vq = v4l2_m2m_get_dst_vq(m2m_ctx); + + spin_lock_irqsave(&inst->state_spinlock, flags); + + if (m2m_ctx->is_draining) { + ret = -EBUSY; + goto unlock_and_return; + } + + if (m2m_ctx->has_stopped) + m2m_ctx->has_stopped = false; + + vb2_clear_last_buffer_dequeued(dst_vq); + inst->eos = false; + +unlock_and_return: + spin_unlock_irqrestore(&inst->state_spinlock, flags); + return ret; +} + static int wave5_vpu_dec_decoder_cmd(struct file *file, void *fh, struct v4l2_decoder_cmd *dc) { struct vpu_instance *inst = wave5_to_vpu_inst(fh); + struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx; int ret; dev_dbg(inst->dev->dev, "decoder command: %u\n", dc->cmd); @@ -753,29 +949,20 @@ static int wave5_vpu_dec_decoder_cmd(struct file *file, void *fh, struct v4l2_de if (ret) return ret; - if (!wave5_vpu_both_queues_are_streaming(inst)) - return 0; - switch (dc->cmd) { case V4L2_DEC_CMD_STOP: - wave5_handle_bitstream_buffer(inst); - inst->ops->start_process(inst); - inst->state = VPU_INST_STATE_STOP; - - ret = wave5_vpu_dec_update_bitstream_buffer(inst, 0); - if (ret) { - dev_err(inst->dev->dev, - "Setting EOS for the bitstream, fail: %d\n", ret); - return ret; - } + ret = wave5_vpu_dec_stop(inst); + /* Just in case we don't have anything to decode anymore */ + v4l2_m2m_try_schedule(m2m_ctx); break; case V4L2_DEC_CMD_START: + ret = wave5_vpu_dec_start(inst); break; default: - return -EINVAL; + ret = -EINVAL; } - return 0; + return ret; } static const struct v4l2_ioctl_ops wave5_vpu_dec_ioctl_ops = { @@ -796,8 +983,13 @@ static const struct v4l2_ioctl_ops wave5_vpu_dec_ioctl_ops = { .vidioc_s_selection = wave5_vpu_dec_s_selection, .vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs, - .vidioc_querybuf = v4l2_m2m_ioctl_querybuf, .vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs, + /* + * Firmware does not support CREATE_BUFS for CAPTURE queue. Since + * there is no immediate use-case for supporting CREATE_BUFS on + * just the OUTPUT queue, disable CREATE_BUFS altogether. + */ + .vidioc_querybuf = v4l2_m2m_ioctl_querybuf, .vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf, .vidioc_qbuf = v4l2_m2m_ioctl_qbuf, .vidioc_expbuf = v4l2_m2m_ioctl_expbuf, @@ -812,49 +1004,6 @@ static const struct v4l2_ioctl_ops wave5_vpu_dec_ioctl_ops = { .vidioc_unsubscribe_event = v4l2_event_unsubscribe, }; -static int wave5_vpu_dec_s_ctrl(struct v4l2_ctrl *ctrl) -{ - struct vpu_instance *inst = wave5_ctrl_to_vpu_inst(ctrl); - - dev_dbg(inst->dev->dev, "%s: name: %s | value: %d\n", - __func__, ctrl->name, ctrl->val); - - switch (ctrl->id) { - case V4L2_CID_VPU_THUMBNAIL_MODE: - inst->thumbnail_mode = ctrl->val; - break; - case V4L2_CID_MIN_BUFFERS_FOR_CAPTURE: - break; - default: - return -EINVAL; - } - - return 0; -} - -static const struct v4l2_ctrl_ops wave5_vpu_dec_ctrl_ops = { - .s_ctrl = wave5_vpu_dec_s_ctrl, -}; - -static const struct v4l2_ctrl_config wave5_vpu_thumbnail_mode = { - .ops = &wave5_vpu_dec_ctrl_ops, - .id = V4L2_CID_VPU_THUMBNAIL_MODE, - .name = "thumbnail mode", - .type = V4L2_CTRL_TYPE_BOOLEAN, - .def = 0, - .min = 0, - .max = 1, - .step = 1, - .flags = V4L2_CTRL_FLAG_WRITE_ONLY, -}; - -static void wave5_set_default_dec_openparam(struct dec_open_param *open_param) -{ - open_param->bitstream_mode = BS_MODE_INTERRUPT; - open_param->stream_endian = VPU_STREAM_ENDIAN; - open_param->frame_endian = VPU_FRAME_ENDIAN; -} - static int wave5_vpu_dec_queue_setup(struct vb2_queue *q, unsigned int *num_buffers, unsigned int *num_planes, unsigned int sizes[], struct device *alloc_devs[]) @@ -862,363 +1011,361 @@ static int wave5_vpu_dec_queue_setup(struct vb2_queue *q, unsigned int *num_buff struct vpu_instance *inst = vb2_get_drv_priv(q); struct v4l2_pix_format_mplane inst_format = (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) ? inst->src_fmt : inst->dst_fmt; - unsigned int i; - int ret; dev_dbg(inst->dev->dev, "%s: num_buffers: %u | num_planes: %u | type: %u\n", __func__, *num_buffers, *num_planes, q->type); - if (*num_planes) { - if (inst_format.num_planes != *num_planes) - return -EINVAL; + *num_planes = inst_format.num_planes; - for (i = 0; i < *num_planes; i++) { - if (sizes[i] < inst_format.plane_fmt[i].sizeimage) - return -EINVAL; - } - } else { - *num_planes = inst_format.num_planes; + if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { + sizes[0] = inst_format.plane_fmt[0].sizeimage; + dev_dbg(inst->dev->dev, "%s: size[0]: %u\n", __func__, sizes[0]); + } else if (q->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) { + if (*num_buffers < inst->fbc_buf_count) + *num_buffers = inst->fbc_buf_count; if (*num_planes == 1) { - sizes[0] = inst_format.width * inst_format.height * 3 / 2; - if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) - sizes[0] = inst_format.plane_fmt[0].sizeimage; + if (inst->output_format == FORMAT_422) + sizes[0] = inst_format.width * inst_format.height * 2; + else + sizes[0] = inst_format.width * inst_format.height * 3 / 2; dev_dbg(inst->dev->dev, "%s: size[0]: %u\n", __func__, sizes[0]); } else if (*num_planes == 2) { sizes[0] = inst_format.width * inst_format.height; - sizes[1] = inst_format.width * inst_format.height / 2; + if (inst->output_format == FORMAT_422) + sizes[1] = inst_format.width * inst_format.height; + else + sizes[1] = inst_format.width * inst_format.height / 2; dev_dbg(inst->dev->dev, "%s: size[0]: %u | size[1]: %u\n", __func__, sizes[0], sizes[1]); } else if (*num_planes == 3) { sizes[0] = inst_format.width * inst_format.height; - sizes[1] = inst_format.width * inst_format.height / 4; - sizes[2] = inst_format.width * inst_format.height / 4; + if (inst->output_format == FORMAT_422) { + sizes[1] = inst_format.width * inst_format.height / 2; + sizes[2] = inst_format.width * inst_format.height / 2; + } else { + sizes[1] = inst_format.width * inst_format.height / 4; + sizes[2] = inst_format.width * inst_format.height / 4; + } dev_dbg(inst->dev->dev, "%s: size[0]: %u | size[1]: %u | size[2]: %u\n", __func__, sizes[0], sizes[1], sizes[2]); } } - if (inst->state == VPU_INST_STATE_NONE && q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { - struct dec_open_param open_param; - - *num_buffers = 4; + return 0; +} - memset(&open_param, 0, sizeof(struct dec_open_param)); - wave5_set_default_dec_openparam(&open_param); +static int wave5_prepare_fb(struct vpu_instance *inst) +{ + int linear_num; + int non_linear_num; + int fb_stride = 0, fb_height = 0; + int luma_size, chroma_size; + int ret, i; + struct v4l2_m2m_buffer *buf, *n; + struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx; - inst->bitstream_vbuf.size = ALIGN(inst->src_fmt.plane_fmt[0].sizeimage, 1024) * 4; - ret = wave5_vdi_allocate_dma_memory(inst->dev, &inst->bitstream_vbuf); - if (ret) { - dev_dbg(inst->dev->dev, "%s: alloc bitstream of size %zu fail: %d\n", - __func__, inst->bitstream_vbuf.size, ret); - return ret; - } + linear_num = v4l2_m2m_num_dst_bufs_ready(m2m_ctx); + non_linear_num = inst->fbc_buf_count; - inst->std = wave5_to_vpu_codstd(inst->src_fmt.pixelformat); - if (inst->std == STD_UNKNOWN) { - dev_warn(inst->dev->dev, "unsupported pixelformat: %.4s\n", - (char *)&inst->src_fmt.pixelformat); - ret = -EINVAL; - goto free_bitstream_vbuf; - } - open_param.bitstream_buffer = inst->bitstream_vbuf.daddr; - open_param.bitstream_buffer_size = inst->bitstream_vbuf.size; + for (i = 0; i < non_linear_num; i++) { + struct frame_buffer *frame = &inst->frame_buf[i]; + struct vpu_buf *vframe = &inst->frame_vbuf[i]; - ret = wave5_vpu_dec_open(inst, &open_param); - if (ret) { - dev_dbg(inst->dev->dev, "%s: wave5_vpu_dec_open, fail: %d\n", - __func__, ret); - goto free_bitstream_vbuf; + if (inst->codec_info->dec_info.initial_info.luma_bitdepth > 8 || + inst->codec_info->dec_info.initial_info.chroma_bitdepth > 8) { + fb_stride = ALIGN(ALIGN(inst->dst_fmt.width, 16) * 5, 32) / 4; + fb_stride = ALIGN(fb_stride, 32); + } else { + fb_stride = inst->dst_fmt.width; } + fb_height = ALIGN(inst->dst_fmt.height, 32); + luma_size = fb_stride * fb_height; - inst->state = VPU_INST_STATE_OPEN; - - if (inst->thumbnail_mode) - wave5_vpu_dec_give_command(inst, ENABLE_DEC_THUMBNAIL_MODE, NULL); - - } else if (inst->state == VPU_INST_STATE_INIT_SEQ && - q->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) { - u32 non_linear_num; - u32 fb_stride, fb_height; - u32 luma_size, chroma_size; - - //if (*num_buffers > inst->min_dst_buf_count && - // *num_buffers < WAVE5_MAX_FBS) - // inst->dst_buf_count = *num_buffers; - inst->dst_buf_count += 2; - - *num_buffers = inst->dst_buf_count; - non_linear_num = inst->dst_buf_count; + chroma_size = ALIGN(fb_stride / 2, 16) * fb_height; - for (i = 0; i < non_linear_num; i++) { - struct frame_buffer *frame = &inst->frame_buf[i]; - struct vpu_buf *vframe = &inst->frame_vbuf[i]; - - if (inst->codec_info->dec_info.initial_info.luma_bitdepth > 8 || - inst->codec_info->dec_info.initial_info.chroma_bitdepth > 8) { - fb_stride = ALIGN(ALIGN(inst->dst_fmt.width, 16) * 5, 32) / 4; - fb_stride = ALIGN(fb_stride, 32); - } else { - fb_stride = inst->dst_fmt.width; - } - - fb_height = ALIGN(inst->dst_fmt.height, 32); - luma_size = fb_stride * fb_height; - chroma_size = ALIGN(fb_stride / 2, 16) * fb_height; + if (vframe->size == (luma_size + chroma_size)) + continue; - vframe->size = luma_size + chroma_size; - ret = wave5_vdi_allocate_dma_memory(inst->dev, vframe); - if (ret) { - dev_dbg(inst->dev->dev, - "%s: Allocating FBC buf of size %zu, fail: %d\n", - __func__, vframe->size, ret); - return ret; - } + if (vframe->size) + wave5_vpu_dec_reset_framebuffer(inst, i); - frame->buf_y = vframe->daddr; - frame->buf_cb = vframe->daddr + luma_size; - frame->buf_cr = (dma_addr_t)-1; - frame->size = vframe->size; - frame->width = inst->src_fmt.width; - frame->stride = fb_stride; - frame->map_type = COMPRESSED_FRAME_MAP; - frame->update_fb_info = true; - dev_dbg(inst->dev->dev, "no linear framebuf y 0x%llx cb 0x%llx cr 0x%llx\n", - frame->buf_y, frame->buf_cb, frame->buf_cr); + vframe->size = luma_size + chroma_size; + ret = wave5_vdi_allocate_dma_memory(inst->dev, vframe); + if (ret) { + dev_dbg(inst->dev->dev, + "%s: Allocating FBC buf of size %zu, fail: %d\n", + __func__, vframe->size, ret); + return ret; } - } else if (inst->state == VPU_INST_STATE_STOP && - q->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) { - *num_buffers = 0; - } - return 0; + frame->buf_y = vframe->daddr; + frame->buf_cb = vframe->daddr + luma_size; + frame->buf_cr = (dma_addr_t)-1; + frame->size = vframe->size; + frame->width = inst->src_fmt.width; + frame->stride = fb_stride; + frame->map_type = COMPRESSED_FRAME_MAP; + frame->update_fb_info = true; + } + /* In case the count has reduced, clean up leftover framebuffer memory */ + for (i = non_linear_num; i < MAX_REG_FRAME; i++) { + ret = wave5_vpu_dec_reset_framebuffer(inst, i); + if (ret) + break; + } -free_bitstream_vbuf: - wave5_vdi_free_dma_memory(inst->dev, &inst->bitstream_vbuf); - return ret; -} + for (i = 0; i < linear_num; i++) { + struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx; + struct vb2_queue *dst_vq = v4l2_m2m_get_dst_vq(m2m_ctx); + struct vb2_buffer *vb = vb2_get_buffer(dst_vq, i); + struct frame_buffer *frame = &inst->frame_buf[non_linear_num + i]; + dma_addr_t buf_addr_y = 0, buf_addr_cb = 0, buf_addr_cr = 0; + u32 buf_size = 0; + u32 fb_stride = inst->dst_fmt.width; + u32 luma_size = fb_stride * inst->dst_fmt.height; + u32 chroma_size; -static int wave5_vpu_dec_start_streaming_open(struct vpu_instance *inst) -{ - struct dec_initial_info initial_info; - int ret = 0; + if (inst->output_format == FORMAT_422) + chroma_size = fb_stride * inst->dst_fmt.height / 2; + else + chroma_size = fb_stride * inst->dst_fmt.height / 4; - inst->time_stamp.cnt = 0; - mutex_init(&inst->time_stamp.lock); - memset(&inst->time_stamp.buf, 0, sizeof(MAX_TIMESTAMP_CIR_BUF)); + if (inst->dst_fmt.num_planes == 1) { + buf_size = vb2_plane_size(vb, 0); + buf_addr_y = vb2_dma_contig_plane_dma_addr(vb, 0); + buf_addr_cb = buf_addr_y + luma_size; + buf_addr_cr = buf_addr_cb + chroma_size; + } else if (inst->dst_fmt.num_planes == 2) { + buf_size = vb2_plane_size(vb, 0) + + vb2_plane_size(vb, 1); + buf_addr_y = vb2_dma_contig_plane_dma_addr(vb, 0); + buf_addr_cb = vb2_dma_contig_plane_dma_addr(vb, 1); + buf_addr_cr = buf_addr_cb + chroma_size; + } else if (inst->dst_fmt.num_planes == 3) { + buf_size = vb2_plane_size(vb, 0) + + vb2_plane_size(vb, 1) + + vb2_plane_size(vb, 2); + buf_addr_y = vb2_dma_contig_plane_dma_addr(vb, 0); + buf_addr_cb = vb2_dma_contig_plane_dma_addr(vb, 1); + buf_addr_cr = vb2_dma_contig_plane_dma_addr(vb, 2); + } - memset(&initial_info, 0, sizeof(struct dec_initial_info)); + frame->buf_y = buf_addr_y; + frame->buf_cb = buf_addr_cb; + frame->buf_cr = buf_addr_cr; + frame->size = buf_size; + frame->width = inst->src_fmt.width; + frame->stride = fb_stride; + frame->map_type = LINEAR_FRAME_MAP; + frame->update_fb_info = true; + + if (frame->size < inst->dev->l2_cache_size) + wave5_flush_l2_cache(frame->buf_y, frame->size); + } - ret = wave5_vpu_dec_issue_seq_init(inst); + ret = wave5_vpu_dec_register_frame_buffer_ex(inst, non_linear_num, linear_num, + fb_stride, inst->dst_fmt.height); if (ret) { - dev_err(inst->dev->dev, "%s: wave5_vpu_dec_issue_seq_init, fail: %d\n", + dev_dbg(inst->dev->dev, "%s: vpu_dec_register_frame_buffer_ex fail: %d", __func__, ret); return ret; } - if (wave5_vpu_wait_interrupt(inst, VPU_DEC_TIMEOUT) < 0) - dev_err(inst->dev->dev, "%s: failed to call vpu_wait_interrupt()\n", __func__); - - ret = wave5_vpu_dec_complete_seq_init(inst, &initial_info); - if (ret) { - dev_err(inst->dev->dev, "%s: vpu_dec_complete_seq_init, fail: %d, reason: %u\n", - __func__, ret, initial_info.seq_init_err_reason); - } else { - static const struct v4l2_event vpu_event_src_ch = { - .type = V4L2_EVENT_SOURCE_CHANGE, - .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION, - }; - struct v4l2_ctrl *ctrl; - - dev_dbg(inst->dev->dev, "%s: width: %u height: %u profile: %u | minbuffer: %u\n", - __func__, initial_info.pic_width, initial_info.pic_height, - initial_info.profile, initial_info.min_frame_buffer_count); + /* + * Mark all frame buffers as out of display, to avoid using them before + * the application have them queued. + */ + for (i = 0; i < v4l2_m2m_num_dst_bufs_ready(m2m_ctx); i++) { + ret = wave5_vpu_dec_set_disp_flag(inst, i); + if (ret) { + dev_dbg(inst->dev->dev, + "%s: Setting display flag of buf index: %u, fail: %d\n", + __func__, i, ret); + } + } - inst->state = VPU_INST_STATE_INIT_SEQ; - inst->min_dst_buf_count = initial_info.min_frame_buffer_count + 1; - inst->dst_buf_count = inst->min_dst_buf_count; + v4l2_m2m_for_each_dst_buf_safe(m2m_ctx, buf, n) { + struct vb2_v4l2_buffer *vbuf = &buf->vb; - inst->conf_win_width = initial_info.pic_width - initial_info.pic_crop_rect.right; - inst->conf_win_height = initial_info.pic_height - initial_info.pic_crop_rect.bottom; + ret = wave5_vpu_dec_clr_disp_flag(inst, vbuf->vb2_buf.index); + if (ret) + dev_dbg(inst->dev->dev, + "%s: Clearing display flag of buf index: %u, fail: %d\n", + __func__, i, ret); + } - ctrl = v4l2_ctrl_find(&inst->v4l2_ctrl_hdl, - V4L2_CID_MIN_BUFFERS_FOR_CAPTURE); - if (ctrl) - v4l2_ctrl_s_ctrl(ctrl, inst->min_dst_buf_count); - - if (initial_info.pic_width != inst->src_fmt.width || - initial_info.pic_height != inst->src_fmt.height) { - wave5_update_pix_fmt(&inst->src_fmt, initial_info.pic_width, - initial_info.pic_height); - wave5_update_pix_fmt(&inst->dst_fmt, initial_info.pic_width, - initial_info.pic_height); - } + return 0; +} - inst->crop_rect.right = initial_info.pic_crop_rect.right; - inst->crop_rect.bottom = initial_info.pic_crop_rect.bottom; +static int write_to_ringbuffer(struct vpu_instance *inst, void *buffer, size_t buffer_size, + struct vpu_buf *ring_buffer, dma_addr_t wr_ptr) +{ + size_t size; + size_t offset = wr_ptr - ring_buffer->daddr; + int ret; - dev_dbg(inst->dev->dev, "wave5 queue event type: %d id: %d\n",vpu_event_src_ch.type, vpu_event_src_ch.id); - v4l2_event_queue_fh(&inst->v4l2_fh, &vpu_event_src_ch); + if (wr_ptr + buffer_size > ring_buffer->daddr + ring_buffer->size) { + size = ring_buffer->daddr + ring_buffer->size - wr_ptr; + ret = wave5_vdi_write_memory(inst->dev, ring_buffer, offset, (u8 *)buffer, size); + if (ret < 0) + return ret; - wave5_handle_src_buffer(inst); + ret = wave5_vdi_write_memory(inst->dev, ring_buffer, 0, (u8 *)buffer + size, + buffer_size - size); + if (ret < 0) + return ret; + } else { + ret = wave5_vdi_write_memory(inst->dev, ring_buffer, offset, (u8 *)buffer, + buffer_size); + if (ret < 0) + return ret; } - return ret; + return 0; } -static int wave5_vpu_dec_start_streaming_seek(struct vpu_instance *inst) +static int fill_ringbuffer(struct vpu_instance *inst) { - struct dec_initial_info initial_info; - struct dec_param pic_param; - struct dec_output_info dec_output_info; - int ret = 0; - u32 fail_res = 0; + struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx; + struct v4l2_m2m_buffer *buf, *n; + int ret; - memset(&pic_param, 0, sizeof(struct dec_param)); + if (m2m_ctx->last_src_buf) { + struct vpu_src_buffer *vpu_buf = wave5_to_vpu_src_buf(m2m_ctx->last_src_buf); - ret = wave5_vpu_dec_start_one_frame(inst, &pic_param, &fail_res); - if (ret && fail_res != WAVE5_SYSERR_QUEUEING_FAIL) { - struct vb2_v4l2_buffer *src_buf; - - src_buf = v4l2_m2m_src_buf_remove(inst->v4l2_fh.m2m_ctx); - inst->state = VPU_INST_STATE_STOP; - v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_ERROR); - dev_dbg(inst->dev->dev, "%s: wave5_vpu_dec_start_one_frame\n", __func__); - return ret; + if (vpu_buf->consumed) { + dev_dbg(inst->dev->dev, "last src buffer already written\n"); + return 0; + } } - if (wave5_vpu_wait_interrupt(inst, VPU_DEC_TIMEOUT) < 0) - dev_dbg(inst->dev->dev, "%s: failed to call vpu_wait_interrupt()\n", __func__); + v4l2_m2m_for_each_src_buf_safe(m2m_ctx, buf, n) { + struct vb2_v4l2_buffer *vbuf = &buf->vb; + struct vpu_src_buffer *vpu_buf = wave5_to_vpu_src_buf(vbuf); + struct vpu_buf *ring_buffer = &inst->bitstream_vbuf; + size_t src_size = vb2_get_plane_payload(&vbuf->vb2_buf, 0); + void *src_buf = vb2_plane_vaddr(&vbuf->vb2_buf, 0); + dma_addr_t rd_ptr = 0; + dma_addr_t wr_ptr = 0; + size_t remain_size = 0; - ret = wave5_vpu_dec_get_output_info(inst, &dec_output_info); - if (ret) { - dev_dbg(inst->dev->dev, "%s: wave5_vpu_dec_get_output_info, fail: %d\n", - __func__, ret); - return ret; - } + if (src_size == vb2_plane_size(&vbuf->vb2_buf, 0)) + src_size = 0; - if (dec_output_info.sequence_changed) { - static const struct v4l2_event vpu_event_src_ch = { - .type = V4L2_EVENT_SOURCE_CHANGE, - .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION, - }; - struct v4l2_ctrl *ctrl; + if (vpu_buf->consumed) { + dev_dbg(inst->dev->dev, "already copied src buf (%u) to the ring buffer\n", + vbuf->vb2_buf.index); + continue; + } - wave5_vpu_dec_give_command(inst, DEC_RESET_FRAMEBUF_INFO, NULL); - wave5_vpu_dec_give_command(inst, DEC_GET_SEQ_INFO, &initial_info); + if (!src_buf) { + dev_dbg(inst->dev->dev, + "%s: Acquiring kernel pointer to src buf (%u), fail\n", + __func__, vbuf->vb2_buf.index); + break; + } - dev_dbg(inst->dev->dev, "%s: width: %u height: %u profile: %u | minbuffer: %u\n", - __func__, initial_info.pic_width, initial_info.pic_height, - initial_info.profile, initial_info.min_frame_buffer_count); + ret = wave5_vpu_dec_get_bitstream_buffer(inst, &rd_ptr, &wr_ptr, &remain_size); + if (ret) { + /* Unable to acquire the mutex */ + dev_err(inst->dev->dev, "Getting the bitstream buffer, fail: %d\n", + ret); + return ret; + } - inst->min_dst_buf_count = initial_info.min_frame_buffer_count + 1; - inst->dst_buf_count = inst->min_dst_buf_count; + dev_dbg(inst->dev->dev, "%s: rd_ptr %pad wr_ptr %pad", __func__, &rd_ptr, &wr_ptr); - inst->conf_win_width = initial_info.pic_width - initial_info.pic_crop_rect.right; - inst->conf_win_height = initial_info.pic_height - initial_info.pic_crop_rect.bottom; + if (remain_size < src_size) { + dev_dbg(inst->dev->dev, + "%s: remaining size: %zu < source size: %zu for src buf (%u)\n", + __func__, remain_size, src_size, vbuf->vb2_buf.index); + break; + } - ctrl = v4l2_ctrl_find(&inst->v4l2_ctrl_hdl, - V4L2_CID_MIN_BUFFERS_FOR_CAPTURE); - if (ctrl) - v4l2_ctrl_s_ctrl(ctrl, inst->min_dst_buf_count); - - if (initial_info.pic_width != inst->src_fmt.width || - initial_info.pic_height != inst->src_fmt.height) { - wave5_update_pix_fmt(&inst->src_fmt, initial_info.pic_width, - initial_info.pic_height); - wave5_update_pix_fmt(&inst->dst_fmt, initial_info.pic_width, - initial_info.pic_height); + ret = write_to_ringbuffer(inst, src_buf, src_size, ring_buffer, wr_ptr); + if (ret) { + dev_err(inst->dev->dev, "Write src buf (%u) to ring buffer, fail: %d\n", + vbuf->vb2_buf.index, ret); + return ret; } - inst->crop_rect.right = initial_info.pic_crop_rect.right; - inst->crop_rect.bottom = initial_info.pic_crop_rect.bottom; + ret = wave5_vpu_dec_update_bitstream_buffer(inst, src_size); + if (ret) { + dev_dbg(inst->dev->dev, + "update_bitstream_buffer fail: %d for src buf (%u)\n", + ret, vbuf->vb2_buf.index); + break; + } - v4l2_event_queue_fh(&inst->v4l2_fh, &vpu_event_src_ch); + vpu_buf->consumed = true; - wave5_handle_src_buffer(inst); + /* Don't write buffers passed the last one while draining. */ + if (v4l2_m2m_is_last_draining_src_buf(m2m_ctx, vbuf)) { + dev_dbg(inst->dev->dev, "last src buffer written to the ring buffer\n"); + break; + } } - return ret; + return 0; } static void wave5_vpu_dec_buf_queue_src(struct vb2_buffer *vb) { - struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); struct vpu_instance *inst = vb2_get_drv_priv(vb->vb2_queue); - struct vpu_buffer *vpu_buf = wave5_to_vpu_buf(vbuf); + struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx; + struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); + struct vpu_src_buffer *vpu_buf = wave5_to_vpu_src_buf(vbuf); vpu_buf->consumed = false; vbuf->sequence = inst->queued_src_buf_num++; - if (inst->state == VPU_INST_STATE_PIC_RUN) { - wave5_handle_bitstream_buffer(inst); - inst->ops->start_process(inst); - } + v4l2_m2m_buf_queue(m2m_ctx, vbuf); } static void wave5_vpu_dec_buf_queue_dst(struct vb2_buffer *vb) { struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); struct vpu_instance *inst = vb2_get_drv_priv(vb->vb2_queue); + struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx; struct frame_buffer *frame_buf; - int ret; vbuf->sequence = inst->queued_dst_buf_num++; - if (inst->state == VPU_INST_STATE_INIT_SEQ) { - dma_addr_t buf_addr_y = 0, buf_addr_cb = 0, buf_addr_cr = 0; - u32 buf_size = 0; - u32 non_linear_num = inst->dst_buf_count; - u32 fb_stride = inst->dst_fmt.width; - u32 luma_size = fb_stride * inst->dst_fmt.height; - u32 chroma_size = (fb_stride / 2) * (inst->dst_fmt.height / 2); + if (inst->state == VPU_INST_STATE_PIC_RUN) { + struct vpu_dst_buffer *vpu_buf = wave5_to_vpu_dst_buf(vbuf); + int ret; - if (inst->dst_fmt.num_planes == 1) { - buf_size = vb2_plane_size(&vbuf->vb2_buf, 0); - buf_addr_y = vb2_dma_contig_plane_dma_addr(&vbuf->vb2_buf, 0); - buf_addr_cb = buf_addr_y + luma_size; - buf_addr_cr = buf_addr_cb + chroma_size; - } else if (inst->dst_fmt.num_planes == 2) { - buf_size = vb2_plane_size(&vbuf->vb2_buf, 0) + - vb2_plane_size(&vbuf->vb2_buf, 1); - buf_addr_y = vb2_dma_contig_plane_dma_addr(&vbuf->vb2_buf, 0); - buf_addr_cb = vb2_dma_contig_plane_dma_addr(&vbuf->vb2_buf, 1); - buf_addr_cr = buf_addr_cb + chroma_size; - } else if (inst->dst_fmt.num_planes == 3) { - buf_size = vb2_plane_size(&vbuf->vb2_buf, 0) + - vb2_plane_size(&vbuf->vb2_buf, 1) + - vb2_plane_size(&vbuf->vb2_buf, 2); - buf_addr_y = vb2_dma_contig_plane_dma_addr(&vbuf->vb2_buf, 0); - buf_addr_cb = vb2_dma_contig_plane_dma_addr(&vbuf->vb2_buf, 1); - buf_addr_cr = vb2_dma_contig_plane_dma_addr(&vbuf->vb2_buf, 2); + frame_buf = &inst->frame_buf[vb->index + inst->fbc_buf_count]; + if (frame_buf->size < inst->dev->l2_cache_size) + wave5_flush_l2_cache(frame_buf->buf_y, frame_buf->size); + + /* + * The buffer is already registered just clear the display flag + * to let the firmware know it can be used. + */ + vpu_buf->display = false; + ret = wave5_vpu_dec_clr_disp_flag(inst, vb->index); + if (ret) { + dev_dbg(inst->dev->dev, + "%s: Clearing the display flag of buffer index: %u, fail: %d\n", + __func__, vb->index, ret); } - inst->frame_buf[vb->index + non_linear_num].buf_y = buf_addr_y; - inst->frame_buf[vb->index + non_linear_num].buf_cb = buf_addr_cb; - inst->frame_buf[vb->index + non_linear_num].buf_cr = buf_addr_cr; - inst->frame_buf[vb->index + non_linear_num].size = buf_size; - inst->frame_buf[vb->index + non_linear_num].width = inst->src_fmt.width; - inst->frame_buf[vb->index + non_linear_num].stride = fb_stride; - inst->frame_buf[vb->index + non_linear_num].map_type = LINEAR_FRAME_MAP; - inst->frame_buf[vb->index + non_linear_num].update_fb_info = true; - dev_dbg(inst->dev->dev, "linear framebuf y 0x%llx cb 0x%llx cr 0x%llx\n",buf_addr_y, buf_addr_cb, buf_addr_cr); } - frame_buf = &inst->frame_buf[vb->index + inst->dst_buf_count]; - if (frame_buf->size < inst->dev->l2_cache_size) - sifive_l2_flush64_range(frame_buf->buf_y, frame_buf->size); + if (vb2_is_streaming(vb->vb2_queue) && v4l2_m2m_dst_buf_is_last(m2m_ctx)) { + unsigned int i; - ret = wave5_vpu_dec_clr_disp_flag(inst, vb->index); - if (ret) { - dev_dbg(inst->dev->dev, - "%s: Clearing the display flag of buffer index: %u, fail: %d\n", - __func__, vb->index, ret); - } + for (i = 0; i < vb->num_planes; i++) + vb2_set_plane_payload(vb, i, 0); - if (!vb2_is_streaming(vb->vb2_queue)) - return; + vbuf->field = V4L2_FIELD_NONE; - if (inst->state == VPU_INST_STATE_STOP && inst->eos == FALSE) - inst->ops->start_process(inst); + send_eos_event(inst); + v4l2_m2m_last_buffer_done(m2m_ctx, vbuf); + } else { + v4l2_m2m_buf_queue(m2m_ctx, vbuf); + } } static void wave5_vpu_dec_buf_queue(struct vb2_buffer *vb) @@ -1227,10 +1374,8 @@ static void wave5_vpu_dec_buf_queue(struct vb2_buffer *vb) struct vpu_instance *inst = vb2_get_drv_priv(vb->vb2_queue); dev_dbg(inst->dev->dev, "%s: type: %4u index: %4u size: ([0]=%4lu, [1]=%4lu, [2]=%4lu)\n", - __func__, vb->type, vb->index, vb2_get_plane_payload(&vbuf->vb2_buf, 0), - vb2_get_plane_payload(&vbuf->vb2_buf, 1), vb2_get_plane_payload(&vbuf->vb2_buf, 2)); - - v4l2_m2m_buf_queue(inst->v4l2_fh.m2m_ctx, vbuf); + __func__, vb->type, vb->index, vb2_plane_size(&vbuf->vb2_buf, 0), + vb2_plane_size(&vbuf->vb2_buf, 1), vb2_plane_size(&vbuf->vb2_buf, 2)); if (vb->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) wave5_vpu_dec_buf_queue_src(vb); @@ -1238,39 +1383,163 @@ static void wave5_vpu_dec_buf_queue(struct vb2_buffer *vb) wave5_vpu_dec_buf_queue_dst(vb); } +static int wave5_vpu_dec_allocate_ring_buffer(struct vpu_instance *inst) +{ + int ret; + struct vpu_buf *ring_buffer = &inst->bitstream_vbuf; + + ring_buffer->size = ALIGN(inst->src_fmt.plane_fmt[0].sizeimage, 1024) * 4; + ret = wave5_vdi_allocate_dma_memory(inst->dev, ring_buffer); + if (ret) { + dev_dbg(inst->dev->dev, "%s: allocate ring buffer of size %zu fail: %d\n", + __func__, ring_buffer->size, ret); + return ret; + } + + inst->last_rd_ptr = ring_buffer->daddr; + + return 0; +} + static int wave5_vpu_dec_start_streaming(struct vb2_queue *q, unsigned int count) { struct vpu_instance *inst = vb2_get_drv_priv(q); + struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx; int ret = 0; dev_dbg(inst->dev->dev, "%s: type: %u\n", __func__, q->type); - if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { - wave5_handle_bitstream_buffer(inst); - if (inst->state == VPU_INST_STATE_OPEN) - ret = wave5_vpu_dec_start_streaming_open(inst); - else if (inst->state == VPU_INST_STATE_INIT_SEQ) - ret = wave5_vpu_dec_start_streaming_seek(inst); + v4l2_m2m_update_start_streaming_state(m2m_ctx, q); + + if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE && inst->state == VPU_INST_STATE_NONE) { + struct dec_open_param open_param; + + memset(&open_param, 0, sizeof(struct dec_open_param)); + + ret = wave5_vpu_dec_allocate_ring_buffer(inst); + if (ret) + goto return_buffers; + + open_param.bitstream_buffer = inst->bitstream_vbuf.daddr; + open_param.bitstream_buffer_size = inst->bitstream_vbuf.size; + ret = wave5_vpu_dec_open(inst, &open_param); if (ret) { - struct vb2_v4l2_buffer *buf; + dev_dbg(inst->dev->dev, "%s: decoder opening, fail: %d\n", + __func__, ret); + goto free_bitstream_vbuf; + } + + ret = switch_state(inst, VPU_INST_STATE_OPEN); + if (ret) + goto free_bitstream_vbuf; + } else if (q->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) { + struct dec_initial_info *initial_info = + &inst->codec_info->dec_info.initial_info; - while ((buf = v4l2_m2m_src_buf_remove(inst->v4l2_fh.m2m_ctx))) { - dev_dbg(inst->dev->dev, "%s: (Multiplanar) buf type %4d | index %4d\n", - __func__, buf->vb2_buf.type, buf->vb2_buf.index); - v4l2_m2m_buf_done(buf, VB2_BUF_STATE_QUEUED); + if (inst->state == VPU_INST_STATE_STOP) + ret = switch_state(inst, VPU_INST_STATE_INIT_SEQ); + if (ret) + goto return_buffers; + + if (inst->state == VPU_INST_STATE_INIT_SEQ) { + if (initial_info->luma_bitdepth != 8 && initial_info->luma_bitdepth != 10) { + dev_info(inst->dev->dev, "%s: no support for %d bit depth", + __func__, initial_info->luma_bitdepth); + ret = -EINVAL; + goto return_buffers; } } } return ret; + +free_bitstream_vbuf: + wave5_vdi_free_dma_memory(inst->dev, &inst->bitstream_vbuf); +return_buffers: + wave5_return_bufs(q, VB2_BUF_STATE_QUEUED); + return ret; } -static void wave5_vpu_dec_stop_streaming(struct vb2_queue *q) +static int streamoff_output(struct vb2_queue *q) +{ + struct vpu_instance *inst = vb2_get_drv_priv(q); + struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx; + struct vb2_v4l2_buffer *buf; + int ret; + dma_addr_t new_rd_ptr; + + while ((buf = v4l2_m2m_src_buf_remove(m2m_ctx))) { + dev_dbg(inst->dev->dev, "%s: (Multiplanar) buf type %4u | index %4u\n", + __func__, buf->vb2_buf.type, buf->vb2_buf.index); + v4l2_m2m_buf_done(buf, VB2_BUF_STATE_ERROR); + } + + ret = wave5_vpu_flush_instance(inst); + if (ret) + return ret; + + /* Reset the ring buffer information */ + new_rd_ptr = wave5_vpu_dec_get_rd_ptr(inst); + inst->last_rd_ptr = new_rd_ptr; + inst->codec_info->dec_info.stream_rd_ptr = new_rd_ptr; + inst->codec_info->dec_info.stream_wr_ptr = new_rd_ptr; + + if (v4l2_m2m_has_stopped(m2m_ctx)) + send_eos_event(inst); + + /* streamoff on output cancels any draining operation */ + inst->eos = false; + + return 0; +} + +static int streamoff_capture(struct vb2_queue *q) { struct vpu_instance *inst = vb2_get_drv_priv(q); + struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx; struct vb2_v4l2_buffer *buf; - int try_cnt = 0; + unsigned int i; + int ret = 0; + + for (i = 0; i < v4l2_m2m_num_dst_bufs_ready(m2m_ctx); i++) { + ret = wave5_vpu_dec_set_disp_flag(inst, i); + if (ret) + dev_dbg(inst->dev->dev, + "%s: Setting display flag of buf index: %u, fail: %d\n", + __func__, i, ret); + } + + while ((buf = v4l2_m2m_dst_buf_remove(m2m_ctx))) { + u32 plane; + + dev_dbg(inst->dev->dev, "%s: buf type %4u | index %4u\n", + __func__, buf->vb2_buf.type, buf->vb2_buf.index); + + for (plane = 0; plane < inst->dst_fmt.num_planes; plane++) + vb2_set_plane_payload(&buf->vb2_buf, plane, 0); + + v4l2_m2m_buf_done(buf, VB2_BUF_STATE_ERROR); + } + + if (inst->needs_reallocation) { + wave5_vpu_dec_give_command(inst, DEC_RESET_FRAMEBUF_INFO, NULL); + inst->needs_reallocation = false; + } + + if (v4l2_m2m_has_stopped(m2m_ctx)) { + ret = switch_state(inst, VPU_INST_STATE_INIT_SEQ); + if (ret) + return ret; + } + + return 0; +} + +static void wave5_vpu_dec_stop_streaming(struct vb2_queue *q) +{ + struct vpu_instance *inst = vb2_get_drv_priv(q); + struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx; bool check_cmd = TRUE; dev_dbg(inst->dev->dev, "%s: type: %u\n", __func__, q->type); @@ -1281,71 +1550,22 @@ static void wave5_vpu_dec_stop_streaming(struct vb2_queue *q) wave5_vpu_dec_give_command(inst, DEC_GET_QUEUE_STATUS, &q_status); - if (q_status.instance_queue_count + q_status.report_queue_count == 0) + if (q_status.report_queue_count == 0) break; - if (wave5_vpu_wait_interrupt(inst, 600) < 0){ - try_cnt++; - if (try_cnt >= 10) - break; - continue; - } + if (wave5_vpu_wait_interrupt(inst, VPU_DEC_TIMEOUT) < 0) + break; if (wave5_vpu_dec_get_output_info(inst, &dec_output_info)) dev_dbg(inst->dev->dev, "Getting decoding results from fw, fail\n"); } - if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { - while ((buf = v4l2_m2m_src_buf_remove(inst->v4l2_fh.m2m_ctx))) { - dev_dbg(inst->dev->dev, "%s: (Multiplanar) buf type %4u | index %4u\n", - __func__, buf->vb2_buf.type, buf->vb2_buf.index); - v4l2_m2m_buf_done(buf, VB2_BUF_STATE_ERROR); - } - inst->queued_src_buf_num = 0; - } else { - unsigned int i; - int ret; - dma_addr_t rd_ptr, wr_ptr; - - while ((buf = v4l2_m2m_dst_buf_remove(inst->v4l2_fh.m2m_ctx))) { - u32 plane; - - dev_dbg(inst->dev->dev, "%s: buf type %4u | index %4u\n", - __func__, buf->vb2_buf.type, buf->vb2_buf.index); - - for (plane = 0; plane < inst->dst_fmt.num_planes; plane++) - vb2_set_plane_payload(&buf->vb2_buf, plane, 0); - - v4l2_m2m_buf_done(buf, VB2_BUF_STATE_ERROR); - } - - for (i = 0; i < inst->dst_buf_count; i++) { - ret = wave5_vpu_dec_set_disp_flag(inst, i); - if (ret) { - dev_dbg(inst->dev->dev, - "%s: Setting display flag of buf index: %u, fail: %d\n", - __func__, i, ret); - } - } + v4l2_m2m_update_stop_streaming_state(m2m_ctx, q); - ret = wave5_vpu_dec_get_bitstream_buffer(inst, &rd_ptr, &wr_ptr, NULL); - if (ret) { - dev_err(inst->dev->dev, - "Getting bitstream buf, fail: %d\n", ret); - return; - } - ret = wave5_vpu_dec_set_rd_ptr(inst, wr_ptr, TRUE); - if (ret) { - dev_err(inst->dev->dev, - "Setting read pointer for the decoder, fail: %d\n", ret); - return; - } - if (inst->eos) { - inst->eos = FALSE; - inst->state = VPU_INST_STATE_INIT_SEQ; - } - inst->queued_dst_buf_num = 0; - } + if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) + streamoff_output(q); + else + streamoff_capture(q); } static const struct vb2_ops wave5_vpu_dec_vb2_ops = { @@ -1382,31 +1602,217 @@ static int wave5_vpu_dec_queue_init(void *priv, struct vb2_queue *src_vq, struct } static const struct vpu_instance_ops wave5_vpu_dec_inst_ops = { - .start_process = wave5_vpu_dec_start_decode, - .stop_process = wave5_vpu_dec_stop_decode, .finish_process = wave5_vpu_dec_finish_decode, }; +static int initialize_sequence(struct vpu_instance *inst) +{ + struct dec_initial_info initial_info; + int ret = 0; + + inst->time_stamp.cnt = 0; + mutex_init(&inst->time_stamp.lock); + memset(&inst->time_stamp.buf, 0, sizeof(MAX_TIMESTAMP_CIR_BUF)); + + memset(&initial_info, 0, sizeof(struct dec_initial_info)); + + ret = wave5_vpu_dec_issue_seq_init(inst); + if (ret) { + dev_err(inst->dev->dev, "%s: wave5_vpu_dec_issue_seq_init, fail: %d\n", + __func__, ret); + return ret; + } + + if (wave5_vpu_wait_interrupt(inst, VPU_DEC_TIMEOUT) < 0) + dev_err(inst->dev->dev, "%s: failed to call vpu_wait_interrupt()\n", __func__); + + ret = wave5_vpu_dec_complete_seq_init(inst, &initial_info); + if (ret) { + dev_err(inst->dev->dev, "%s: vpu_dec_complete_seq_init, fail: %d, reason: %u\n", + __func__, ret, initial_info.seq_init_err_reason); + wave5_handle_src_buffer(inst, initial_info.rd_ptr); + return ret; + } + + handle_dynamic_resolution_change(inst); + + return 0; +} + +static bool wave5_is_draining_or_eos(struct vpu_instance *inst) +{ + struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx; + + lockdep_assert_held(&inst->state_spinlock); + return m2m_ctx->is_draining || inst->eos; +} + static void wave5_vpu_dec_device_run(void *priv) { struct vpu_instance *inst = priv; + struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx; + struct queue_status_info q_status; + u32 fail_res = 0; + int ret = 0; + + dev_dbg(inst->dev->dev, "%s: Fill the ring buffer with new bitstream data", __func__); + + ret = fill_ringbuffer(inst); + if (ret) { + dev_warn(inst->dev->dev, "Filling ring buffer failed\n"); + goto finish_job_and_return; + } + + switch (inst->state) { + case VPU_INST_STATE_OPEN: + ret = initialize_sequence(inst); + if (ret) { + unsigned long flags; + + spin_lock_irqsave(&inst->state_spinlock, flags); + if (wave5_is_draining_or_eos(inst) && + wave5_last_src_buffer_consumed(m2m_ctx)) { + struct vb2_queue *dst_vq = v4l2_m2m_get_dst_vq(m2m_ctx); + + switch_state(inst, VPU_INST_STATE_STOP); + + if (vb2_is_streaming(dst_vq)) + send_eos_event(inst); + else + handle_dynamic_resolution_change(inst); + + flag_last_buffer_done(inst); + } + spin_unlock_irqrestore(&inst->state_spinlock, flags); + } else { + switch_state(inst, VPU_INST_STATE_INIT_SEQ); + } + + break; + + case VPU_INST_STATE_INIT_SEQ: + /* + * Do this early, preparing the fb can trigger an IRQ before + * we had a chance to switch, which leads to an invalid state + * change. + */ + switch_state(inst, VPU_INST_STATE_PIC_RUN); + + /* + * During DRC, the picture decoding remains pending, so just leave the job + * active until this decode operation completes. + */ + wave5_vpu_dec_give_command(inst, DEC_GET_QUEUE_STATUS, &q_status); - wave5_handle_bitstream_buffer(inst); - inst->ops->start_process(inst); + /* + * The sequence must be analyzed first to calculate the proper + * size of the auxiliary buffers. + */ + ret = wave5_prepare_fb(inst); + if (ret) { + dev_warn(inst->dev->dev, "Framebuffer preparation, fail: %d\n", ret); + switch_state(inst, VPU_INST_STATE_STOP); + break; + } - inst->state = VPU_INST_STATE_PIC_RUN; + if (q_status.instance_queue_count) { + dev_dbg(inst->dev->dev, "%s: leave with active job", __func__); + return; + } + + fallthrough; + case VPU_INST_STATE_PIC_RUN: + ret = start_decode(inst, &fail_res); + if (ret) { + dev_err(inst->dev->dev, + "Frame decoding on m2m context (%p), fail: %d (result: %d)\n", + m2m_ctx, ret, fail_res); + break; + } + /* Return so that we leave this job active */ + dev_dbg(inst->dev->dev, "%s: leave with active job", __func__); + return; + default: + WARN(1, "Execution of a job in state %s illegal.\n", state_to_str(inst->state)); + break; + } + +finish_job_and_return: + dev_dbg(inst->dev->dev, "%s: leave and finish job", __func__); + v4l2_m2m_job_finish(inst->v4l2_m2m_dev, m2m_ctx); } static void wave5_vpu_dec_job_abort(void *priv) { struct vpu_instance *inst = priv; + int ret; - inst->ops->stop_process(inst); + ret = switch_state(inst, VPU_INST_STATE_STOP); + if (ret) + return; + + ret = wave5_vpu_dec_set_eos_on_firmware(inst); + if (ret) + dev_warn(inst->dev->dev, + "Setting EOS for the bitstream, fail: %d\n", ret); + + v4l2_m2m_job_finish(inst->v4l2_m2m_dev, inst->v4l2_fh.m2m_ctx); +} + +static int wave5_vpu_dec_job_ready(void *priv) +{ + struct vpu_instance *inst = priv; + struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx; + unsigned long flags; + int ret = 0; + + spin_lock_irqsave(&inst->state_spinlock, flags); + + switch (inst->state) { + case VPU_INST_STATE_NONE: + dev_dbg(inst->dev->dev, "Decoder must be open to start queueing M2M jobs!\n"); + break; + case VPU_INST_STATE_OPEN: + if (wave5_is_draining_or_eos(inst) || !v4l2_m2m_has_stopped(m2m_ctx) || + v4l2_m2m_num_src_bufs_ready(m2m_ctx) > 0) { + ret = 1; + break; + } + + dev_dbg(inst->dev->dev, + "Decoder must be draining or >= 1 OUTPUT queue buffer must be queued!\n"); + break; + case VPU_INST_STATE_INIT_SEQ: + case VPU_INST_STATE_PIC_RUN: + if (!m2m_ctx->cap_q_ctx.q.streaming) { + dev_dbg(inst->dev->dev, "CAPTURE queue must be streaming to queue jobs!\n"); + break; + } else if (v4l2_m2m_num_dst_bufs_ready(m2m_ctx) < (inst->fbc_buf_count - 1)) { + dev_dbg(inst->dev->dev, + "No capture buffer ready to decode!\n"); + break; + } else if (!wave5_is_draining_or_eos(inst) && + !v4l2_m2m_num_src_bufs_ready(m2m_ctx)) { + dev_dbg(inst->dev->dev, + "No bitstream data to decode!\n"); + break; + } + ret = 1; + break; + case VPU_INST_STATE_STOP: + dev_dbg(inst->dev->dev, "Decoder is stopped, not running.\n"); + break; + } + + spin_unlock_irqrestore(&inst->state_spinlock, flags); + + return ret; } static const struct v4l2_m2m_ops wave5_vpu_dec_m2m_ops = { .device_run = wave5_vpu_dec_device_run, .job_abort = wave5_vpu_dec_job_abort, + .job_ready = wave5_vpu_dec_job_ready, }; static int wave5_vpu_open_dec(struct file *filp) @@ -1414,6 +1820,7 @@ static int wave5_vpu_open_dec(struct file *filp) struct video_device *vdev = video_devdata(filp); struct vpu_device *dev = video_drvdata(filp); struct vpu_instance *inst = NULL; + struct v4l2_m2m_ctx *m2m_ctx; int ret = 0; inst = kzalloc(sizeof(*inst), GFP_KERNEL); @@ -1424,6 +1831,12 @@ static int wave5_vpu_open_dec(struct file *filp) inst->type = VPU_INST_TYPE_DEC; inst->ops = &wave5_vpu_dec_inst_ops; + spin_lock_init(&inst->state_spinlock); + + inst->codec_info = kzalloc(sizeof(*inst->codec_info), GFP_KERNEL); + if (!inst->codec_info) + return -ENOMEM; + v4l2_fh_init(&inst->v4l2_fh, vdev); filp->private_data = &inst->v4l2_fh; v4l2_fh_add(&inst->v4l2_fh); @@ -1431,23 +1844,34 @@ static int wave5_vpu_open_dec(struct file *filp) INIT_LIST_HEAD(&inst->list); list_add_tail(&inst->list, &dev->instances); - inst->v4l2_m2m_dev = v4l2_m2m_init(&wave5_vpu_dec_m2m_ops); - if (IS_ERR(inst->v4l2_m2m_dev)) { - ret = PTR_ERR(inst->v4l2_m2m_dev); - dev_err(inst->dev->dev, "v4l2_m2m_init, fail: %d\n", ret); - goto cleanup_inst; - } - + inst->v4l2_m2m_dev = inst->dev->v4l2_m2m_dec_dev; inst->v4l2_fh.m2m_ctx = v4l2_m2m_ctx_init(inst->v4l2_m2m_dev, inst, wave5_vpu_dec_queue_init); if (IS_ERR(inst->v4l2_fh.m2m_ctx)) { ret = PTR_ERR(inst->v4l2_fh.m2m_ctx); goto cleanup_inst; } + m2m_ctx = inst->v4l2_fh.m2m_ctx; + + v4l2_m2m_set_src_buffered(m2m_ctx, true); + v4l2_m2m_set_dst_buffered(m2m_ctx, true); + /* + * We use the M2M job queue to ensure synchronization of steps where + * needed, as IOCTLs can occur at anytime and we need to run commands on + * the firmware in a specified order. + * In order to initialize the sequence on the firmware within an M2M + * job, the M2M framework needs to be able to queue jobs before + * the CAPTURE queue has been started, because we need the results of the + * initialization to properly prepare the CAPTURE queue with the correct + * amount of buffers. + * By setting ignore_cap_streaming to true the m2m framework will call + * job_ready as soon as the OUTPUT queue is streaming, instead of + * waiting until both the CAPTURE and OUTPUT queues are streaming. + */ + m2m_ctx->ignore_cap_streaming = true; v4l2_ctrl_handler_init(&inst->v4l2_ctrl_hdl, 10); - v4l2_ctrl_new_custom(&inst->v4l2_ctrl_hdl, &wave5_vpu_thumbnail_mode, NULL); - v4l2_ctrl_new_std(&inst->v4l2_ctrl_hdl, &wave5_vpu_dec_ctrl_ops, + v4l2_ctrl_new_std(&inst->v4l2_ctrl_hdl, NULL, V4L2_CID_MIN_BUFFERS_FOR_CAPTURE, 1, 32, 1, 1); if (inst->v4l2_ctrl_hdl.error) { @@ -1461,16 +1885,10 @@ static int wave5_vpu_open_dec(struct file *filp) wave5_set_default_format(&inst->src_fmt, &inst->dst_fmt); inst->colorspace = V4L2_COLORSPACE_REC709; inst->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT; - inst->hsv_enc = 0; inst->quantization = V4L2_QUANTIZATION_DEFAULT; inst->xfer_func = V4L2_XFER_FUNC_DEFAULT; init_completion(&inst->irq_done); - ret = kfifo_alloc(&inst->irq_status, 16 * sizeof(int), GFP_KERNEL); - if (ret) { - dev_err(inst->dev->dev, "failed to allocate fifo\n"); - goto cleanup_inst; - } inst->id = ida_alloc(&inst->dev->inst_ida, GFP_KERNEL); if (inst->id < 0) { @@ -1509,6 +1927,13 @@ int wave5_vpu_dec_register_device(struct vpu_device *dev) if (!vdev_dec) return -ENOMEM; + dev->v4l2_m2m_dec_dev = v4l2_m2m_init(&wave5_vpu_dec_m2m_ops); + if (IS_ERR(dev->v4l2_m2m_dec_dev)) { + ret = PTR_ERR(dev->v4l2_m2m_dec_dev); + dev_err(dev->dev, "v4l2_m2m_init, fail: %d\n", ret); + return -EINVAL; + } + dev->video_dev_dec = vdev_dec; strscpy(vdev_dec->name, VPU_DEC_DEV_NAME, sizeof(vdev_dec->name)); @@ -1532,4 +1957,6 @@ int wave5_vpu_dec_register_device(struct vpu_device *dev) void wave5_vpu_dec_unregister_device(struct vpu_device *dev) { video_unregister_device(dev->video_dev_dec); + if (dev->v4l2_m2m_dec_dev) + v4l2_m2m_release(dev->v4l2_m2m_dec_dev); } diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c b/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c index 285111c2d9cd..f29cfa3af94a 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c +++ b/drivers/media/platform/chips-media/wave5/wave5-vpu-enc.c @@ -2,7 +2,7 @@ /* * Wave5 series multi-standard codec IP - encoder interface * - * Copyright (C) 2021 CHIPS&MEDIA INC + * Copyright (C) 2021-2023 CHIPS&MEDIA INC */ #include "wave5-helper.h" @@ -73,58 +73,36 @@ static const struct vpu_format enc_fmt_list[FMT_TYPES][MAX_FMTS] = { } }; -static enum wave_std wave5_to_vpu_wavestd(unsigned int v4l2_pix_fmt) +static int switch_state(struct vpu_instance *inst, enum vpu_instance_state state) { - switch (v4l2_pix_fmt) { - case V4L2_PIX_FMT_H264: - return W_AVC_ENC; - case V4L2_PIX_FMT_HEVC: - return W_HEVC_ENC; - default: - return STD_UNKNOWN; - } -} - -static struct vb2_v4l2_buffer *wave5_get_valid_src_buf(struct vpu_instance *inst) -{ - struct v4l2_m2m_buffer *v4l2_m2m_buf; - - v4l2_m2m_for_each_src_buf(inst->v4l2_fh.m2m_ctx, v4l2_m2m_buf) { - struct vb2_v4l2_buffer *vb2_v4l2_buf; - struct vpu_buffer *vpu_buf = NULL; - - vb2_v4l2_buf = &v4l2_m2m_buf->vb; - vpu_buf = wave5_to_vpu_buf(vb2_v4l2_buf); - - if (!vpu_buf->consumed) { - dev_dbg(inst->dev->dev, "%s: src buf (index: %u) has not been consumed\n", - __func__, vb2_v4l2_buf->vb2_buf.index); - return vb2_v4l2_buf; - } - } - - return NULL; -} - -static struct vb2_v4l2_buffer *wave5_get_valid_dst_buf(struct vpu_instance *inst) -{ - struct v4l2_m2m_buffer *v4l2_m2m_buf; - - v4l2_m2m_for_each_dst_buf(inst->v4l2_fh.m2m_ctx, v4l2_m2m_buf) { - struct vb2_v4l2_buffer *vb2_v4l2_buf; - struct vpu_buffer *vpu_buf = NULL; - - vb2_v4l2_buf = &v4l2_m2m_buf->vb; - vpu_buf = wave5_to_vpu_buf(vb2_v4l2_buf); + switch (state) { + case VPU_INST_STATE_NONE: + goto invalid_state_switch; + case VPU_INST_STATE_OPEN: + if (inst->state != VPU_INST_STATE_NONE) + goto invalid_state_switch; + break; + case VPU_INST_STATE_INIT_SEQ: + if (inst->state != VPU_INST_STATE_OPEN && inst->state != VPU_INST_STATE_STOP) + goto invalid_state_switch; + break; + case VPU_INST_STATE_PIC_RUN: + if (inst->state != VPU_INST_STATE_INIT_SEQ) + goto invalid_state_switch; + break; + case VPU_INST_STATE_STOP: + break; + }; - if (!vpu_buf->consumed) { - dev_dbg(inst->dev->dev, "%s: dst buf (index: %u) has not been consumed\n", - __func__, vb2_v4l2_buf->vb2_buf.index); - return vb2_v4l2_buf; - } - } + dev_dbg(inst->dev->dev, "Switch state from %s to %s.\n", + state_to_str(inst->state), state_to_str(state)); + inst->state = state; + return 0; - return NULL; +invalid_state_switch: + WARN(1, "Invalid state switch from %s to %s.\n", + state_to_str(inst->state), state_to_str(state)); + return -EINVAL; } static void wave5_update_pix_fmt(struct v4l2_pix_format_mplane *pix_mp, unsigned int width, @@ -162,138 +140,118 @@ static void wave5_update_pix_fmt(struct v4l2_pix_format_mplane *pix_mp, unsigned pix_mp->width = width; pix_mp->height = height; pix_mp->plane_fmt[0].bytesperline = 0; - pix_mp->plane_fmt[0].sizeimage = width * height; + pix_mp->plane_fmt[0].sizeimage = width * height / 8 * 3; break; } } -static void wave5_vpu_enc_start_encode(struct vpu_instance *inst) +static int start_encode(struct vpu_instance *inst, u32 *fail_res) { - u32 max_cmd_q = 0; - - max_cmd_q = (inst->src_buf_count < COMMAND_QUEUE_DEPTH) ? - inst->src_buf_count : COMMAND_QUEUE_DEPTH; - - if (inst->state == VPU_INST_STATE_STOP) - max_cmd_q = 1; - - while (max_cmd_q) { - struct vb2_v4l2_buffer *src_buf; - struct vb2_v4l2_buffer *dst_buf; - struct vpu_buffer *src_vbuf; - struct vpu_buffer *dst_vbuf; - struct frame_buffer frame_buf; - struct enc_param pic_param; - u32 stride = ALIGN(inst->dst_fmt.width, 32); - u32 luma_size = (stride * inst->dst_fmt.height); - u32 chroma_size = ((stride / 2) * (inst->dst_fmt.height / 2)); - u32 fail_res; - int ret; - - memset(&pic_param, 0, sizeof(struct enc_param)); - memset(&frame_buf, 0, sizeof(struct frame_buffer)); + struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx; + int ret; + struct vb2_v4l2_buffer *src_buf; + struct vb2_v4l2_buffer *dst_buf; + struct frame_buffer frame_buf; + struct enc_param pic_param; + u32 stride = ALIGN(inst->dst_fmt.width, 32); + u32 luma_size = (stride * inst->dst_fmt.height); + u32 chroma_size = ((stride / 2) * (inst->dst_fmt.height / 2)); + + memset(&pic_param, 0, sizeof(struct enc_param)); + memset(&frame_buf, 0, sizeof(struct frame_buffer)); + + dst_buf = v4l2_m2m_next_dst_buf(m2m_ctx); + if (!dst_buf) { + dev_dbg(inst->dev->dev, "%s: No destination buffer found\n", __func__); + return -EAGAIN; + } - src_buf = wave5_get_valid_src_buf(inst); - dst_buf = wave5_get_valid_dst_buf(inst); + pic_param.pic_stream_buffer_addr = + vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0); + pic_param.pic_stream_buffer_size = + vb2_plane_size(&dst_buf->vb2_buf, 0); - if (!dst_buf) { - dev_dbg(inst->dev->dev, "%s: No valid dst buf\n", __func__); - break; + src_buf = v4l2_m2m_next_src_buf(m2m_ctx); + if (!src_buf) { + dev_dbg(inst->dev->dev, "%s: No source buffer found\n", __func__); + if (m2m_ctx->is_draining) + pic_param.src_end_flag = 1; + else + return -EAGAIN; + } else { + if (inst->src_fmt.num_planes == 1) { + frame_buf.buf_y = + vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0); + frame_buf.buf_cb = frame_buf.buf_y + luma_size; + frame_buf.buf_cr = frame_buf.buf_cb + chroma_size; + } else if (inst->src_fmt.num_planes == 2) { + frame_buf.buf_y = + vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0); + frame_buf.buf_cb = + vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 1); + frame_buf.buf_cr = frame_buf.buf_cb + chroma_size; + } else if (inst->src_fmt.num_planes == 3) { + frame_buf.buf_y = + vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0); + frame_buf.buf_cb = + vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 1); + frame_buf.buf_cr = + vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 2); } + frame_buf.stride = stride; + pic_param.src_idx = src_buf->vb2_buf.index; + } - dst_vbuf = wave5_to_vpu_buf(dst_buf); - pic_param.pic_stream_buffer_addr = - vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0); - pic_param.pic_stream_buffer_size = - vb2_plane_size(&dst_buf->vb2_buf, 0); + pic_param.source_frame = &frame_buf; + pic_param.code_option.implicit_header_encode = 1; + pic_param.code_option.encode_aud = inst->encode_aud; + ret = wave5_vpu_enc_start_one_frame(inst, &pic_param, fail_res); + if (ret) { + if (*fail_res == WAVE5_SYSERR_QUEUEING_FAIL) + return -EINVAL; + dev_dbg(inst->dev->dev, "%s: wave5_vpu_enc_start_one_frame fail: %d\n", + __func__, ret); + src_buf = v4l2_m2m_src_buf_remove(m2m_ctx); if (!src_buf) { - dev_dbg(inst->dev->dev, "%s: No valid src buf\n", __func__); - if (inst->state == VPU_INST_STATE_STOP) - pic_param.src_end_flag = true; - else - break; - } else { - src_vbuf = wave5_to_vpu_buf(src_buf); - if (inst->src_fmt.num_planes == 1) { - frame_buf.buf_y = - vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0); - frame_buf.buf_cb = frame_buf.buf_y + luma_size; - frame_buf.buf_cr = frame_buf.buf_cb + chroma_size; - } else if (inst->src_fmt.num_planes == 2) { - frame_buf.buf_y = - vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0); - frame_buf.buf_cb = - vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 1); - frame_buf.buf_cr = frame_buf.buf_cb + chroma_size; - } else if (inst->src_fmt.num_planes == 3) { - frame_buf.buf_y = - vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0); - frame_buf.buf_cb = - vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 1); - frame_buf.buf_cr = - vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 2); - } - frame_buf.stride = stride; - pic_param.src_idx = src_buf->vb2_buf.index; + dev_dbg(inst->dev->dev, + "%s: Removing src buf failed, the queue is empty\n", + __func__); + return -EINVAL; } - - pic_param.source_frame = &frame_buf; - pic_param.code_option.implicit_header_encode = 1; - ret = wave5_vpu_enc_start_one_frame(inst, &pic_param, &fail_res); - if (ret) { - if (fail_res == WAVE5_SYSERR_QUEUEING_FAIL) - break; - - dev_dbg(inst->dev->dev, "%s: wave5_vpu_enc_start_one_frame fail: %d\n", - __func__, ret); - src_buf = v4l2_m2m_src_buf_remove(inst->v4l2_fh.m2m_ctx); - if (!src_buf) { - dev_dbg(inst->dev->dev, - "%s: Removing src buf failed, the queue is empty\n", - __func__); - continue; - } - dst_buf = v4l2_m2m_dst_buf_remove(inst->v4l2_fh.m2m_ctx); - if (!dst_buf) { - dev_dbg(inst->dev->dev, - "%s: Removing dst buf failed, the queue is empty\n", - __func__); - continue; - } - inst->state = VPU_INST_STATE_STOP; - v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_ERROR); - v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_ERROR); - } else { - dev_dbg(inst->dev->dev, "%s: wave5_vpu_enc_start_one_frame success\n", + dst_buf = v4l2_m2m_dst_buf_remove(m2m_ctx); + if (!dst_buf) { + dev_dbg(inst->dev->dev, + "%s: Removing dst buf failed, the queue is empty\n", __func__); - if (src_buf) - src_vbuf->consumed = true; - if (dst_buf) - dst_vbuf->consumed = true; + return -EINVAL; } - - max_cmd_q--; + switch_state(inst, VPU_INST_STATE_STOP); + dst_buf->vb2_buf.timestamp = src_buf->vb2_buf.timestamp; + v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_ERROR); + v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_ERROR); + } else { + dev_dbg(inst->dev->dev, "%s: wave5_vpu_enc_start_one_frame success\n", + __func__); + /* + * Remove the source buffer from the ready-queue now and finish + * it in the videobuf2 framework once the index is returned by the + * firmware in finish_encode + */ + if (src_buf) + v4l2_m2m_src_buf_remove_by_idx(m2m_ctx, src_buf->vb2_buf.index); } -} - -static void wave5_vpu_enc_stop_encode(struct vpu_instance *inst) -{ - inst->state = VPU_INST_STATE_STOP; - v4l2_m2m_job_finish(inst->v4l2_m2m_dev, inst->v4l2_fh.m2m_ctx); + return 0; } static void wave5_vpu_enc_finish_encode(struct vpu_instance *inst) { + struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx; int ret; struct enc_output_info enc_output_info; - u32 irq_status; + struct vb2_v4l2_buffer *src_buf = NULL; struct vb2_v4l2_buffer *dst_buf = NULL; - struct v4l2_m2m_buffer *v4l2_m2m_buf = NULL; - - if (kfifo_out(&inst->irq_status, &irq_status, sizeof(int))) - wave5_vpu_clear_interrupt_ex(inst, irq_status); ret = wave5_vpu_enc_get_output_info(inst, &enc_output_info); if (ret) { @@ -303,39 +261,57 @@ static void wave5_vpu_enc_finish_encode(struct vpu_instance *inst) return; } - v4l2_m2m_for_each_dst_buf(inst->v4l2_fh.m2m_ctx, v4l2_m2m_buf) { - dst_buf = &v4l2_m2m_buf->vb; - if (enc_output_info.bitstream_buffer == - vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0)) - break; - } + dev_dbg(inst->dev->dev, + "%s: pic_type %i recon_idx %i src_idx %i pic_byte %u pts %llu\n", + __func__, enc_output_info.pic_type, enc_output_info.recon_frame_index, + enc_output_info.enc_src_idx, enc_output_info.enc_pic_byte, enc_output_info.pts); + /* + * The source buffer will not be found in the ready-queue as it has been + * dropped after sending of the encode firmware command, locate it in + * the videobuf2 queue directly + */ if (enc_output_info.enc_src_idx >= 0) { - struct vb2_v4l2_buffer *src_buf = - v4l2_m2m_src_buf_remove_by_idx(inst->v4l2_fh.m2m_ctx, + struct vb2_buffer *vb = vb2_get_buffer(v4l2_m2m_get_src_vq(m2m_ctx), enc_output_info.enc_src_idx); + if (vb->state != VB2_BUF_STATE_ACTIVE) + dev_warn(inst->dev->dev, + "%s: encoded buffer (%d) was not in ready queue %i.", + __func__, enc_output_info.enc_src_idx, vb->state); + else + src_buf = to_vb2_v4l2_buffer(vb); - inst->timestamp = src_buf->vb2_buf.timestamp; - v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE); + if (src_buf) { + inst->timestamp = src_buf->vb2_buf.timestamp; + v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE); + } else { + dev_warn(inst->dev->dev, "%s: no source buffer with index: %d found\n", + __func__, enc_output_info.enc_src_idx); + } } + dst_buf = v4l2_m2m_dst_buf_remove(m2m_ctx); if (enc_output_info.recon_frame_index == RECON_IDX_FLAG_ENC_END) { static const struct v4l2_event vpu_event_eos = { .type = V4L2_EVENT_EOS }; - vb2_set_plane_payload(&dst_buf->vb2_buf, 0, 0); - dst_buf->vb2_buf.timestamp = inst->timestamp; - dst_buf->field = V4L2_FIELD_NONE; - dst_buf->flags |= V4L2_BUF_FLAG_LAST; - v4l2_m2m_dst_buf_remove_by_buf(inst->v4l2_fh.m2m_ctx, dst_buf); - v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_DONE); + if (!WARN_ON(!dst_buf)) { + vb2_set_plane_payload(&dst_buf->vb2_buf, 0, 0); + dst_buf->field = V4L2_FIELD_NONE; + v4l2_m2m_last_buffer_done(m2m_ctx, dst_buf); + } - inst->state = VPU_INST_STATE_PIC_RUN; v4l2_event_queue_fh(&inst->v4l2_fh, &vpu_event_eos); - v4l2_m2m_job_finish(inst->v4l2_m2m_dev, inst->v4l2_fh.m2m_ctx); + v4l2_m2m_job_finish(inst->v4l2_m2m_dev, m2m_ctx); } else { + if (!dst_buf) { + dev_warn(inst->dev->dev, "No bitstream buffer."); + v4l2_m2m_job_finish(inst->v4l2_m2m_dev, m2m_ctx); + return; + } + vb2_set_plane_payload(&dst_buf->vb2_buf, 0, enc_output_info.bitstream_size); dst_buf->vb2_buf.timestamp = inst->timestamp; @@ -352,11 +328,12 @@ static void wave5_vpu_enc_finish_encode(struct vpu_instance *inst) dst_buf->flags |= V4L2_BUF_FLAG_BFRAME; } - v4l2_m2m_dst_buf_remove_by_buf(inst->v4l2_fh.m2m_ctx, dst_buf); v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_DONE); dev_dbg(inst->dev->dev, "%s: frame_cycle %8u\n", __func__, enc_output_info.frame_cycle); + + v4l2_m2m_job_finish(inst->v4l2_m2m_dev, m2m_ctx); } } @@ -364,7 +341,6 @@ static int wave5_vpu_enc_querycap(struct file *file, void *fh, struct v4l2_capab { strscpy(cap->driver, VPU_ENC_DRV_NAME, sizeof(cap->driver)); strscpy(cap->card, VPU_ENC_DRV_NAME, sizeof(cap->card)); - strscpy(cap->bus_info, "platform:" VPU_ENC_DRV_NAME, sizeof(cap->bus_info)); return 0; } @@ -420,9 +396,6 @@ static int wave5_vpu_enc_try_fmt_cap(struct file *file, void *fh, struct v4l2_fo __func__, f->fmt.pix_mp.pixelformat, f->fmt.pix_mp.width, f->fmt.pix_mp.height, f->fmt.pix_mp.num_planes, f->fmt.pix_mp.field); - if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) - return -EINVAL; - vpu_fmt = wave5_find_vpu_fmt(f->fmt.pix_mp.pixelformat, enc_fmt_list[VPU_FMT_TYPE_CODEC]); if (!vpu_fmt) { f->fmt.pix_mp.pixelformat = inst->dst_fmt.pixelformat; @@ -441,10 +414,8 @@ static int wave5_vpu_enc_try_fmt_cap(struct file *file, void *fh, struct v4l2_fo f->fmt.pix_mp.field = V4L2_FIELD_NONE; f->fmt.pix_mp.colorspace = inst->colorspace; f->fmt.pix_mp.ycbcr_enc = inst->ycbcr_enc; - f->fmt.pix_mp.hsv_enc = inst->hsv_enc; f->fmt.pix_mp.quantization = inst->quantization; f->fmt.pix_mp.xfer_func = inst->xfer_func; - memset(&f->fmt.pix_mp.reserved, 0, sizeof(f->fmt.pix_mp.reserved)); return 0; } @@ -462,6 +433,13 @@ static int wave5_vpu_enc_s_fmt_cap(struct file *file, void *fh, struct v4l2_form if (ret) return ret; + inst->std = wave5_to_vpu_std(f->fmt.pix_mp.pixelformat, inst->type); + if (inst->std == STD_UNKNOWN) { + dev_warn(inst->dev->dev, "unsupported pixelformat: %.4s\n", + (char *)&f->fmt.pix_mp.pixelformat); + return -EINVAL; + } + inst->dst_fmt.width = f->fmt.pix_mp.width; inst->dst_fmt.height = f->fmt.pix_mp.height; inst->dst_fmt.pixelformat = f->fmt.pix_mp.pixelformat; @@ -494,7 +472,6 @@ static int wave5_vpu_enc_g_fmt_cap(struct file *file, void *fh, struct v4l2_form f->fmt.pix_mp.colorspace = inst->colorspace; f->fmt.pix_mp.ycbcr_enc = inst->ycbcr_enc; - f->fmt.pix_mp.hsv_enc = inst->hsv_enc; f->fmt.pix_mp.quantization = inst->quantization; f->fmt.pix_mp.xfer_func = inst->xfer_func; @@ -527,9 +504,6 @@ static int wave5_vpu_enc_try_fmt_out(struct file *file, void *fh, struct v4l2_fo __func__, f->fmt.pix_mp.pixelformat, f->fmt.pix_mp.width, f->fmt.pix_mp.height, f->fmt.pix_mp.num_planes, f->fmt.pix_mp.field); - if (f->type != V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) - return -EINVAL; - vpu_fmt = wave5_find_vpu_fmt(f->fmt.pix_mp.pixelformat, enc_fmt_list[VPU_FMT_TYPE_RAW]); if (!vpu_fmt) { f->fmt.pix_mp.pixelformat = inst->src_fmt.pixelformat; @@ -547,7 +521,6 @@ static int wave5_vpu_enc_try_fmt_out(struct file *file, void *fh, struct v4l2_fo f->fmt.pix_mp.flags = 0; f->fmt.pix_mp.field = V4L2_FIELD_NONE; - memset(&f->fmt.pix_mp.reserved, 0, sizeof(f->fmt.pix_mp.reserved)); return 0; } @@ -591,7 +564,6 @@ static int wave5_vpu_enc_s_fmt_out(struct file *file, void *fh, struct v4l2_form inst->colorspace = f->fmt.pix_mp.colorspace; inst->ycbcr_enc = f->fmt.pix_mp.ycbcr_enc; - inst->hsv_enc = f->fmt.pix_mp.hsv_enc; inst->quantization = f->fmt.pix_mp.quantization; inst->xfer_func = f->fmt.pix_mp.xfer_func; @@ -606,27 +578,18 @@ static int wave5_vpu_enc_g_selection(struct file *file, void *fh, struct v4l2_se dev_dbg(inst->dev->dev, "%s: type: %u | target: %u\n", __func__, s->type, s->target); - if (s->type == V4L2_BUF_TYPE_VIDEO_OUTPUT) { - switch (s->target) { - case V4L2_SEL_TGT_CROP_DEFAULT: - case V4L2_SEL_TGT_CROP_BOUNDS: - s->r.left = 0; - s->r.top = 0; - s->r.width = inst->dst_fmt.width; - s->r.height = inst->dst_fmt.height; - break; - case V4L2_SEL_TGT_CROP: - s->r.left = 0; - s->r.top = 0; - s->r.width = inst->dst_fmt.width; - s->r.height = inst->dst_fmt.height; - dev_dbg(inst->dev->dev, "%s: V4L2_SEL_TGT_CROP width: %u | height: %u\n", - __func__, s->r.width, s->r.height); - break; - default: - return -EINVAL; - } - } else { + if (s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) + return -EINVAL; + switch (s->target) { + case V4L2_SEL_TGT_CROP_DEFAULT: + case V4L2_SEL_TGT_CROP_BOUNDS: + case V4L2_SEL_TGT_CROP: + s->r.left = 0; + s->r.top = 0; + s->r.width = inst->dst_fmt.width; + s->r.height = inst->dst_fmt.height; + break; + default: return -EINVAL; } @@ -657,6 +620,7 @@ static int wave5_vpu_enc_s_selection(struct file *file, void *fh, struct v4l2_se static int wave5_vpu_enc_encoder_cmd(struct file *file, void *fh, struct v4l2_encoder_cmd *ec) { struct vpu_instance *inst = wave5_to_vpu_inst(fh); + struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx; int ret; ret = v4l2_m2m_ioctl_try_encoder_cmd(file, fh, ec); @@ -668,8 +632,14 @@ static int wave5_vpu_enc_encoder_cmd(struct file *file, void *fh, struct v4l2_en switch (ec->cmd) { case V4L2_ENC_CMD_STOP: - inst->state = VPU_INST_STATE_STOP; - inst->ops->start_process(inst); + if (m2m_ctx->is_draining) + return -EBUSY; + + if (m2m_ctx->has_stopped) + return 0; + + m2m_ctx->last_src_buf = v4l2_m2m_last_src_buf(m2m_ctx); + m2m_ctx->is_draining = true; break; case V4L2_ENC_CMD_START: break; @@ -769,6 +739,9 @@ static int wave5_vpu_enc_s_ctrl(struct v4l2_ctrl *ctrl) dev_dbg(inst->dev->dev, "%s: name: %s | value: %d\n", __func__, ctrl->name, ctrl->val); switch (ctrl->id) { + case V4L2_CID_MPEG_VIDEO_AU_DELIMITER: + inst->encode_aud = ctrl->val; + break; case V4L2_CID_HFLIP: inst->mirror_direction |= (ctrl->val << 1); break; @@ -1101,6 +1074,57 @@ static const struct v4l2_ctrl_ops wave5_vpu_enc_ctrl_ops = { .s_ctrl = wave5_vpu_enc_s_ctrl, }; +static int wave5_vpu_enc_queue_setup(struct vb2_queue *q, unsigned int *num_buffers, + unsigned int *num_planes, unsigned int sizes[], + struct device *alloc_devs[]) +{ + struct vpu_instance *inst = vb2_get_drv_priv(q); + struct v4l2_pix_format_mplane inst_format = + (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) ? inst->src_fmt : inst->dst_fmt; + unsigned int i; + + dev_dbg(inst->dev->dev, "%s: num_buffers: %u | num_planes: %u | type: %u\n", __func__, + *num_buffers, *num_planes, q->type); + + if (*num_planes) { + if (inst_format.num_planes != *num_planes) + return -EINVAL; + + for (i = 0; i < *num_planes; i++) { + if (sizes[i] < inst_format.plane_fmt[i].sizeimage) + return -EINVAL; + } + } else { + *num_planes = inst_format.num_planes; + for (i = 0; i < *num_planes; i++) { + sizes[i] = inst_format.plane_fmt[i].sizeimage; + dev_dbg(inst->dev->dev, "%s: size[%u]: %u\n", __func__, i, sizes[i]); + } + } + + dev_dbg(inst->dev->dev, "%s: size: %u\n", __func__, sizes[0]); + + return 0; +} + +static void wave5_vpu_enc_buf_queue(struct vb2_buffer *vb) +{ + struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); + struct vpu_instance *inst = vb2_get_drv_priv(vb->vb2_queue); + struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx; + + dev_dbg(inst->dev->dev, "%s: type: %4u index: %4u size: ([0]=%4lu, [1]=%4lu, [2]=%4lu)\n", + __func__, vb->type, vb->index, vb2_plane_size(&vbuf->vb2_buf, 0), + vb2_plane_size(&vbuf->vb2_buf, 1), vb2_plane_size(&vbuf->vb2_buf, 2)); + + if (vb->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) + vbuf->sequence = inst->queued_src_buf_num++; + else + vbuf->sequence = inst->queued_dst_buf_num++; + + v4l2_m2m_buf_queue(m2m_ctx, vbuf); +} + static void wave5_set_enc_openparam(struct enc_open_param *open_param, struct vpu_instance *inst) { @@ -1122,8 +1146,6 @@ static void wave5_set_enc_openparam(struct enc_open_param *open_param, open_param->wave_param.rdo_skip = 1; open_param->wave_param.lambda_scaling_enable = 1; - open_param->stream_endian = VPU_STREAM_ENDIAN; - open_param->source_endian = VPU_SOURCE_ENDIAN; open_param->line_buf_int_en = true; open_param->pic_width = inst->dst_fmt.width; open_param->pic_height = inst->dst_fmt.height; @@ -1199,65 +1221,107 @@ static void wave5_set_enc_openparam(struct enc_open_param *open_param, } } -static int wave5_vpu_enc_queue_setup(struct vb2_queue *q, unsigned int *num_buffers, - unsigned int *num_planes, unsigned int sizes[], - struct device *alloc_devs[]) +static int initialize_sequence(struct vpu_instance *inst) { - struct vpu_instance *inst = vb2_get_drv_priv(q); - struct v4l2_pix_format_mplane inst_format = - (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) ? inst->src_fmt : inst->dst_fmt; - unsigned int i; + struct enc_initial_info initial_info; + struct v4l2_ctrl *ctrl; int ret; - dev_dbg(inst->dev->dev, "%s: num_buffers: %u | num_planes: %u | type: %u\n", __func__, - *num_buffers, *num_planes, q->type); + ret = wave5_vpu_enc_issue_seq_init(inst); + if (ret) { + dev_err(inst->dev->dev, "%s: wave5_vpu_enc_issue_seq_init, fail: %d\n", + __func__, ret); + return ret; + } - if (*num_planes) { - if (inst_format.num_planes != *num_planes) - return -EINVAL; + if (wave5_vpu_wait_interrupt(inst, VPU_ENC_TIMEOUT) < 0) { + dev_err(inst->dev->dev, "%s: wave5_vpu_wait_interrupt failed\n", __func__); + return -EINVAL; + } - for (i = 0; i < *num_planes; i++) { - if (sizes[i] < inst_format.plane_fmt[i].sizeimage) - return -EINVAL; - } - } else { - *num_planes = inst_format.num_planes; - for (i = 0; i < *num_planes; i++) { - sizes[i] = inst_format.plane_fmt[i].sizeimage; - dev_dbg(inst->dev->dev, "%s: size[%u]: %u\n", __func__, i, sizes[i]); + ret = wave5_vpu_enc_complete_seq_init(inst, &initial_info); + if (ret) + return ret; + + dev_dbg(inst->dev->dev, "%s: min_frame_buffer: %u | min_source_buffer: %u\n", + __func__, initial_info.min_frame_buffer_count, + initial_info.min_src_frame_count); + inst->min_src_buf_count = initial_info.min_src_frame_count + + COMMAND_QUEUE_DEPTH; + + ctrl = v4l2_ctrl_find(&inst->v4l2_ctrl_hdl, + V4L2_CID_MIN_BUFFERS_FOR_OUTPUT); + if (ctrl) + v4l2_ctrl_s_ctrl(ctrl, inst->min_src_buf_count); + + inst->fbc_buf_count = initial_info.min_frame_buffer_count; + + return 0; +} + +static int prepare_fb(struct vpu_instance *inst) +{ + u32 fb_stride = ALIGN(inst->dst_fmt.width, 32); + u32 fb_height = ALIGN(inst->dst_fmt.height, 32); + int i, ret = 0; + + for (i = 0; i < inst->fbc_buf_count; i++) { + u32 luma_size = fb_stride * fb_height; + u32 chroma_size = ALIGN(fb_stride / 2, 16) * fb_height; + + inst->frame_vbuf[i].size = luma_size + chroma_size; + ret = wave5_vdi_allocate_dma_memory(inst->dev, &inst->frame_vbuf[i]); + if (ret < 0) { + dev_err(inst->dev->dev, "%s: failed to allocate FBC buffer %zu\n", + __func__, inst->frame_vbuf[i].size); + goto free_buffers; } + + inst->frame_buf[i].buf_y = inst->frame_vbuf[i].daddr; + inst->frame_buf[i].buf_cb = (dma_addr_t)-1; + inst->frame_buf[i].buf_cr = (dma_addr_t)-1; + inst->frame_buf[i].update_fb_info = true; + inst->frame_buf[i].size = inst->frame_vbuf[i].size; } - dev_dbg(inst->dev->dev, "%s: size: %u\n", __func__, sizes[0]); + ret = wave5_vpu_enc_register_frame_buffer(inst, inst->fbc_buf_count, fb_stride, + fb_height, COMPRESSED_FRAME_MAP); + if (ret) { + dev_err(inst->dev->dev, + "%s: wave5_vpu_enc_register_frame_buffer, fail: %d\n", + __func__, ret); + goto free_buffers; + } + + return 0; +free_buffers: + for (i = 0; i < inst->fbc_buf_count; i++) + wave5_vpu_dec_reset_framebuffer(inst, i); + return ret; +} + +static int wave5_vpu_enc_start_streaming(struct vb2_queue *q, unsigned int count) +{ + struct vpu_instance *inst = vb2_get_drv_priv(q); + struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx; + int ret = 0; + + v4l2_m2m_update_start_streaming_state(m2m_ctx, q); if (inst->state == VPU_INST_STATE_NONE && q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { - unsigned int non_linear_num = 0; - u32 fb_stride = 0; - u32 fb_height = 0; struct enc_open_param open_param; - struct enc_initial_info initial_info; - struct v4l2_ctrl *ctrl; memset(&open_param, 0, sizeof(struct enc_open_param)); - inst->std = wave5_to_vpu_wavestd(inst->dst_fmt.pixelformat); - if (inst->std == STD_UNKNOWN) { - dev_warn(inst->dev->dev, "unsupported pixelformat: %.4s\n", - (char *)&inst->dst_fmt.pixelformat); - return -EINVAL; - } - wave5_set_enc_openparam(&open_param, inst); ret = wave5_vpu_enc_open(inst, &open_param); if (ret) { dev_dbg(inst->dev->dev, "%s: wave5_vpu_enc_open, fail: %d\n", __func__, ret); - return ret; + goto return_buffers; } - inst->state = VPU_INST_STATE_OPEN; - if (inst->mirror_direction) { wave5_vpu_enc_give_command(inst, ENABLE_MIRRORING, NULL); wave5_vpu_enc_give_command(inst, SET_MIRROR_DIRECTION, @@ -1268,123 +1332,81 @@ static int wave5_vpu_enc_queue_setup(struct vb2_queue *q, unsigned int *num_buff wave5_vpu_enc_give_command(inst, SET_ROTATION_ANGLE, &inst->rot_angle); } - ret = wave5_vpu_enc_issue_seq_init(inst); + ret = switch_state(inst, VPU_INST_STATE_OPEN); + if (ret) + goto return_buffers; + } + if (inst->state == VPU_INST_STATE_OPEN && m2m_ctx->cap_q_ctx.q.streaming) { + ret = initialize_sequence(inst); if (ret) { - dev_dbg(inst->dev->dev, "%s: wave5_vpu_enc_issue_seq_init, fail: %d\n", - __func__, ret); - return ret; - } - - if (wave5_vpu_wait_interrupt(inst, VPU_ENC_TIMEOUT) < 0) { - dev_dbg(inst->dev->dev, "%s: wave5_vpu_wait_interrupt failed\n", __func__); - return -EINVAL; + dev_warn(inst->dev->dev, "Sequence not found: %d\n", ret); + goto return_buffers; } - - ret = wave5_vpu_enc_complete_seq_init(inst, &initial_info); + ret = switch_state(inst, VPU_INST_STATE_INIT_SEQ); if (ret) - return ret; - - dev_dbg(inst->dev->dev, "%s: min_frame_buffer: %u | min_source_buffer: %u\n", - __func__, initial_info.min_frame_buffer_count, - initial_info.min_src_frame_count); - inst->state = VPU_INST_STATE_INIT_SEQ; - inst->min_src_buf_count = initial_info.min_src_frame_count + - COMMAND_QUEUE_DEPTH; - - ctrl = v4l2_ctrl_find(&inst->v4l2_ctrl_hdl, - V4L2_CID_MIN_BUFFERS_FOR_OUTPUT); - if (ctrl) - v4l2_ctrl_s_ctrl(ctrl, inst->min_src_buf_count); - - inst->min_dst_buf_count = initial_info.min_frame_buffer_count; - inst->src_buf_count = inst->min_src_buf_count; - - if (*num_buffers > inst->src_buf_count) - inst->src_buf_count = *num_buffers; - - *num_buffers = inst->src_buf_count; - non_linear_num = inst->min_dst_buf_count; - - fb_stride = ALIGN(inst->dst_fmt.width, 32); - fb_height = ALIGN(inst->dst_fmt.height, 32); - - for (i = 0; i < non_linear_num; i++) { - u32 luma_size = fb_stride * fb_height; - u32 chroma_size = ALIGN(fb_stride / 2, 16) * fb_height; - - inst->frame_vbuf[i].size = luma_size + chroma_size; - ret = wave5_vdi_allocate_dma_memory(inst->dev, &inst->frame_vbuf[i]); - if (ret < 0) { - dev_dbg(inst->dev->dev, "%s: failed to allocate FBC buffer %zu\n", - __func__, inst->frame_vbuf[i].size); - goto free_buffers; - } - - inst->frame_buf[i].buf_y = inst->frame_vbuf[i].daddr; - inst->frame_buf[i].buf_cb = (dma_addr_t)-1; - inst->frame_buf[i].buf_cr = (dma_addr_t)-1; - inst->frame_buf[i].update_fb_info = true; - inst->frame_buf[i].size = inst->frame_vbuf[i].size; - } - - ret = wave5_vpu_enc_register_frame_buffer(inst, non_linear_num, fb_stride, - fb_height, COMPRESSED_FRAME_MAP); + goto return_buffers; + /* + * The sequence must be analyzed first to calculate the proper + * size of the auxiliary buffers. + */ + ret = prepare_fb(inst); if (ret) { - dev_dbg(inst->dev->dev, - "%s: wave5_vpu_enc_register_frame_buffer, fail: %d\n", - __func__, ret); - goto free_buffers; + dev_warn(inst->dev->dev, "Framebuffer preparation, fail: %d\n", ret); + goto return_buffers; } - inst->state = VPU_INST_STATE_PIC_RUN; - } - - if (inst->state == VPU_INST_STATE_INIT_SEQ && - q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { - *num_buffers = inst->src_buf_count; - dev_dbg(inst->dev->dev, "%s: src buf num: %u", __func__, *num_buffers); + ret = switch_state(inst, VPU_INST_STATE_PIC_RUN); } + if (ret) + goto return_buffers; return 0; - -free_buffers: - for (i = 0; i < inst->min_dst_buf_count; i++) - wave5_vdi_free_dma_memory(inst->dev, &inst->frame_vbuf[i]); +return_buffers: + wave5_return_bufs(q, VB2_BUF_STATE_QUEUED); return ret; } -static void wave5_vpu_enc_buf_queue(struct vb2_buffer *vb) +static void streamoff_output(struct vpu_instance *inst, struct vb2_queue *q) { - struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); - struct vpu_instance *inst = vb2_get_drv_priv(vb->vb2_queue); - struct vpu_buffer *vpu_buf = wave5_to_vpu_buf(vbuf); + struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx; + struct vb2_v4l2_buffer *buf; - dev_dbg(inst->dev->dev, "%s: type: %4u index: %4u size: ([0]=%4lu, [1]=%4lu, [2]=%4lu)\n", - __func__, vb->type, vb->index, vb2_plane_size(&vbuf->vb2_buf, 0), - vb2_plane_size(&vbuf->vb2_buf, 1), vb2_plane_size(&vbuf->vb2_buf, 2)); + while ((buf = v4l2_m2m_src_buf_remove(m2m_ctx))) { + dev_dbg(inst->dev->dev, "%s: buf type %4u | index %4u\n", + __func__, buf->vb2_buf.type, buf->vb2_buf.index); + v4l2_m2m_buf_done(buf, VB2_BUF_STATE_ERROR); + } +} - if (vb->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) - vbuf->sequence = inst->queued_src_buf_num++; - else - vbuf->sequence = inst->queued_dst_buf_num++; +static void streamoff_capture(struct vpu_instance *inst, struct vb2_queue *q) +{ + struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx; + struct vb2_v4l2_buffer *buf; - vpu_buf->consumed = FALSE; - v4l2_m2m_buf_queue(inst->v4l2_fh.m2m_ctx, vbuf); + while ((buf = v4l2_m2m_dst_buf_remove(m2m_ctx))) { + dev_dbg(inst->dev->dev, "%s: buf type %4u | index %4u\n", + __func__, buf->vb2_buf.type, buf->vb2_buf.index); + vb2_set_plane_payload(&buf->vb2_buf, 0, 0); + v4l2_m2m_buf_done(buf, VB2_BUF_STATE_ERROR); + } - if (vb2_start_streaming_called(vb->vb2_queue)) - inst->ops->start_process(inst); + v4l2_m2m_clear_state(m2m_ctx); } static void wave5_vpu_enc_stop_streaming(struct vb2_queue *q) { struct vpu_instance *inst = vb2_get_drv_priv(q); - struct vb2_v4l2_buffer *buf; bool check_cmd = true; + /* + * Note that we don't need m2m_ctx->next_buf_last for this driver, so we + * don't call v4l2_m2m_update_stop_streaming_state(). + */ + dev_dbg(inst->dev->dev, "%s: type: %u\n", __func__, q->type); if (wave5_vpu_both_queues_are_streaming(inst)) - inst->state = VPU_INST_STATE_STOP; + switch_state(inst, VPU_INST_STATE_STOP); while (check_cmd) { struct queue_status_info q_status; @@ -1392,7 +1414,7 @@ static void wave5_vpu_enc_stop_streaming(struct vb2_queue *q) wave5_vpu_enc_give_command(inst, ENC_GET_QUEUE_STATUS, &q_status); - if (q_status.instance_queue_count + q_status.report_queue_count == 0) + if (q_status.report_queue_count == 0) break; if (wave5_vpu_wait_interrupt(inst, VPU_ENC_TIMEOUT) < 0) @@ -1402,20 +1424,10 @@ static void wave5_vpu_enc_stop_streaming(struct vb2_queue *q) dev_dbg(inst->dev->dev, "Getting encoding results from fw, fail\n"); } - if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { - while ((buf = v4l2_m2m_src_buf_remove(inst->v4l2_fh.m2m_ctx))) { - dev_dbg(inst->dev->dev, "%s: buf type %4u | index %4u\n", - __func__, buf->vb2_buf.type, buf->vb2_buf.index); - v4l2_m2m_buf_done(buf, VB2_BUF_STATE_ERROR); - } - } else { - while ((buf = v4l2_m2m_dst_buf_remove(inst->v4l2_fh.m2m_ctx))) { - dev_dbg(inst->dev->dev, "%s: buf type %4u | index %4u\n", - __func__, buf->vb2_buf.type, buf->vb2_buf.index); - vb2_set_plane_payload(&buf->vb2_buf, 0, 0); - v4l2_m2m_buf_done(buf, VB2_BUF_STATE_ERROR); - } - } + if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) + streamoff_output(inst, q); + else + streamoff_capture(inst, q); } static const struct vb2_ops wave5_vpu_enc_vb2_ops = { @@ -1423,6 +1435,7 @@ static const struct vb2_ops wave5_vpu_enc_vb2_ops = { .wait_prepare = vb2_ops_wait_prepare, .wait_finish = vb2_ops_wait_finish, .buf_queue = wave5_vpu_enc_buf_queue, + .start_streaming = wave5_vpu_enc_start_streaming, .stop_streaming = wave5_vpu_enc_stop_streaming, }; @@ -1451,39 +1464,68 @@ static int wave5_vpu_enc_queue_init(void *priv, struct vb2_queue *src_vq, struct } static const struct vpu_instance_ops wave5_vpu_enc_inst_ops = { - .start_process = wave5_vpu_enc_start_encode, - .stop_process = wave5_vpu_enc_stop_encode, .finish_process = wave5_vpu_enc_finish_encode, }; static void wave5_vpu_enc_device_run(void *priv) { struct vpu_instance *inst = priv; + struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx; + u32 fail_res = 0; + int ret = 0; - inst->ops->start_process(inst); + switch (inst->state) { + case VPU_INST_STATE_PIC_RUN: + ret = start_encode(inst, &fail_res); + if (ret) { + if (ret == -EINVAL) + dev_err(inst->dev->dev, + "Frame encoding on m2m context (%p), fail: %d (res: %d)\n", + m2m_ctx, ret, fail_res); + else if (ret == -EAGAIN) + dev_dbg(inst->dev->dev, "Missing buffers for encode, try again\n"); + break; + } + dev_dbg(inst->dev->dev, "%s: leave with active job", __func__); + return; + default: + WARN(1, "Execution of a job in state %s is invalid.\n", + state_to_str(inst->state)); + break; + } + dev_dbg(inst->dev->dev, "%s: leave and finish job", __func__); + v4l2_m2m_job_finish(inst->v4l2_m2m_dev, m2m_ctx); } static int wave5_vpu_enc_job_ready(void *priv) { struct vpu_instance *inst = priv; - - if (inst->state == VPU_INST_STATE_STOP) - return 0; - - return 1; -} - -static void wave5_vpu_enc_job_abort(void *priv) -{ - struct vpu_instance *inst = priv; - - inst->ops->stop_process(inst); + struct v4l2_m2m_ctx *m2m_ctx = inst->v4l2_fh.m2m_ctx; + + switch (inst->state) { + case VPU_INST_STATE_NONE: + dev_dbg(inst->dev->dev, "Encoder must be open to start queueing M2M jobs!\n"); + return false; + case VPU_INST_STATE_PIC_RUN: + if (m2m_ctx->is_draining || v4l2_m2m_num_src_bufs_ready(m2m_ctx)) { + dev_dbg(inst->dev->dev, "Encoder ready for a job, state: %s\n", + state_to_str(inst->state)); + return true; + } + fallthrough; + default: + dev_dbg(inst->dev->dev, + "Encoder not ready for a job, state: %s, %s draining, %d src bufs ready\n", + state_to_str(inst->state), m2m_ctx->is_draining ? "is" : "is not", + v4l2_m2m_num_src_bufs_ready(m2m_ctx)); + break; + } + return false; } static const struct v4l2_m2m_ops wave5_vpu_enc_m2m_ops = { .device_run = wave5_vpu_enc_device_run, .job_ready = wave5_vpu_enc_job_ready, - .job_abort = wave5_vpu_enc_job_abort, }; static int wave5_vpu_open_enc(struct file *filp) @@ -1503,6 +1545,10 @@ static int wave5_vpu_open_enc(struct file *filp) inst->type = VPU_INST_TYPE_ENC; inst->ops = &wave5_vpu_enc_inst_ops; + inst->codec_info = kzalloc(sizeof(*inst->codec_info), GFP_KERNEL); + if (!inst->codec_info) + return -ENOMEM; + v4l2_fh_init(&inst->v4l2_fh, vdev); filp->private_data = &inst->v4l2_fh; v4l2_fh_add(&inst->v4l2_fh); @@ -1510,19 +1556,14 @@ static int wave5_vpu_open_enc(struct file *filp) INIT_LIST_HEAD(&inst->list); list_add_tail(&inst->list, &dev->instances); - inst->v4l2_m2m_dev = v4l2_m2m_init(&wave5_vpu_enc_m2m_ops); - if (IS_ERR(inst->v4l2_m2m_dev)) { - ret = PTR_ERR(inst->v4l2_m2m_dev); - dev_err(inst->dev->dev, "v4l2_m2m_init, fail: %d\n", ret); - goto cleanup_inst; - } - + inst->v4l2_m2m_dev = inst->dev->v4l2_m2m_enc_dev; inst->v4l2_fh.m2m_ctx = v4l2_m2m_ctx_init(inst->v4l2_m2m_dev, inst, wave5_vpu_enc_queue_init); if (IS_ERR(inst->v4l2_fh.m2m_ctx)) { ret = PTR_ERR(inst->v4l2_fh.m2m_ctx); goto cleanup_inst; } + v4l2_m2m_set_src_buffered(inst->v4l2_fh.m2m_ctx, true); v4l2_ctrl_handler_init(v4l2_ctrl_hdl, 50); v4l2_ctrl_new_std_menu(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, @@ -1555,7 +1596,7 @@ static int wave5_vpu_open_enc(struct file *filp) v4l2_ctrl_new_std_menu(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_TYPE, V4L2_MPEG_VIDEO_HEVC_REFRESH_IDR, 0, - V4L2_MPEG_VIDEO_HEVC_REFRESH_CRA); + V4L2_MPEG_VIDEO_HEVC_REFRESH_IDR); v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_PERIOD, 0, 2047, 1, 0); @@ -1621,7 +1662,9 @@ static int wave5_vpu_open_enc(struct file *filp) V4L2_CID_MPEG_VIDEO_H264_ENTROPY_MODE, V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC, 0, V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC); - + v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, + V4L2_CID_MPEG_VIDEO_AU_DELIMITER, + 0, 1, 1, 1); v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, V4L2_CID_HFLIP, 0, 1, 1, 0); @@ -1633,7 +1676,7 @@ static int wave5_vpu_open_enc(struct file *filp) 0, 270, 90, 0); v4l2_ctrl_new_std(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, V4L2_CID_MPEG_VIDEO_VBV_SIZE, - 10, 3000, 1, 3000); + 10, 3000, 1, 1000); v4l2_ctrl_new_std_menu(v4l2_ctrl_hdl, &wave5_vpu_enc_ctrl_ops, V4L2_CID_MPEG_VIDEO_BITRATE_MODE, V4L2_MPEG_VIDEO_BITRATE_MODE_CBR, 0, @@ -1671,17 +1714,11 @@ static int wave5_vpu_open_enc(struct file *filp) wave5_set_default_format(&inst->src_fmt, &inst->dst_fmt); inst->colorspace = V4L2_COLORSPACE_REC709; inst->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT; - inst->hsv_enc = 0; inst->quantization = V4L2_QUANTIZATION_DEFAULT; inst->xfer_func = V4L2_XFER_FUNC_DEFAULT; inst->frame_rate = 30; init_completion(&inst->irq_done); - ret = kfifo_alloc(&inst->irq_status, 16 * sizeof(int), GFP_KERNEL); - if (ret) { - dev_err(inst->dev->dev, "Allocating fifo, fail: %d\n", ret); - goto cleanup_inst; - } inst->id = ida_alloc(&inst->dev->inst_ida, GFP_KERNEL); if (inst->id < 0) { @@ -1690,6 +1727,8 @@ static int wave5_vpu_open_enc(struct file *filp) goto cleanup_inst; } + wave5_vdi_allocate_sram(inst->dev); + return 0; cleanup_inst: @@ -1720,6 +1759,13 @@ int wave5_vpu_enc_register_device(struct vpu_device *dev) if (!vdev_enc) return -ENOMEM; + dev->v4l2_m2m_enc_dev = v4l2_m2m_init(&wave5_vpu_enc_m2m_ops); + if (IS_ERR(dev->v4l2_m2m_enc_dev)) { + ret = PTR_ERR(dev->v4l2_m2m_enc_dev); + dev_err(dev->dev, "v4l2_m2m_init, fail: %d\n", ret); + return -EINVAL; + } + dev->video_dev_enc = vdev_enc; strscpy(vdev_enc->name, VPU_ENC_DEV_NAME, sizeof(vdev_enc->name)); @@ -1743,4 +1789,6 @@ int wave5_vpu_enc_register_device(struct vpu_device *dev) void wave5_vpu_enc_unregister_device(struct vpu_device *dev) { video_unregister_device(dev->video_dev_enc); + if (dev->v4l2_m2m_enc_dev) + v4l2_m2m_release(dev->v4l2_m2m_enc_dev); } diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpu.c b/drivers/media/platform/chips-media/wave5/wave5-vpu.c index 9aee7e90a9ac..3a20bc1c0a8c 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-vpu.c +++ b/drivers/media/platform/chips-media/wave5/wave5-vpu.c @@ -2,16 +2,13 @@ /* * Wave5 series multi-standard codec IP - platform driver * - * Copyright (C) 2021 CHIPS&MEDIA INC + * Copyright (C) 2021-2023 CHIPS&MEDIA INC */ #include <linux/kernel.h> #include <linux/module.h> #include <linux/platform_device.h> #include <linux/clk.h> -#include <linux/clk-provider.h> -#include <linux/pm_runtime.h> #include <linux/reset.h> -#include <linux/of_address.h> #include <linux/firmware.h> #include <linux/interrupt.h> #include "wave5-vpu.h" @@ -44,99 +41,55 @@ int wave5_vpu_wait_interrupt(struct vpu_instance *inst, unsigned int timeout) return 0; } -static void wave5_vpu_get_interrupt_for_inst(struct vpu_instance *inst, u32 status) +static irqreturn_t wave5_vpu_irq_thread(int irq, void *dev_id) { - struct vpu_device *dev = inst->dev; u32 seq_done; u32 cmd_done; - int val; - - seq_done = wave5_vdi_readl(dev, W5_RET_SEQ_DONE_INSTANCE_INFO); - cmd_done = wave5_vdi_readl(dev, W5_RET_QUEUE_CMD_DONE_INST); - - if (status & BIT(INT_WAVE5_INIT_SEQ)) { - if (seq_done & BIT(inst->id)) { - seq_done &= ~BIT(inst->id); - wave5_vdi_write_register(dev, W5_RET_SEQ_DONE_INSTANCE_INFO, seq_done); - val = BIT(INT_WAVE5_INIT_SEQ); - kfifo_in(&inst->irq_status, &val, sizeof(int)); - } - } - if (status & BIT(INT_WAVE5_ENC_SET_PARAM)) { - if (seq_done & BIT(inst->id)) { - seq_done &= ~BIT(inst->id); - wave5_vdi_write_register(dev, W5_RET_SEQ_DONE_INSTANCE_INFO, seq_done); - val = BIT(INT_WAVE5_ENC_SET_PARAM); - kfifo_in(&inst->irq_status, &val, sizeof(int)); - } - } - if (status & BIT(INT_WAVE5_DEC_PIC) || - status & BIT(INT_WAVE5_ENC_PIC)) { - if (cmd_done & BIT(inst->id)) { - cmd_done &= ~BIT(inst->id); - wave5_vdi_write_register(dev, W5_RET_QUEUE_CMD_DONE_INST, cmd_done); - val = BIT(INT_WAVE5_DEC_PIC); - kfifo_in(&inst->irq_status, &val, sizeof(int)); - } - } -} - -static irqreturn_t wave5_vpu_irq(int irq, void *dev_id) -{ + u32 irq_reason; + struct vpu_instance *inst; struct vpu_device *dev = dev_id; - if (wave5_vdi_readl(dev, W5_VPU_VPU_INT_STS)) { - struct vpu_instance *inst; - u32 irq_status = wave5_vdi_readl(dev, W5_VPU_VINT_REASON); - - list_for_each_entry(inst, &dev->instances, list) { - wave5_vpu_get_interrupt_for_inst(inst, irq_status); - } - - wave5_vdi_write_register(dev, W5_VPU_VINT_REASON_CLR, irq_status); + if (wave5_vdi_read_register(dev, W5_VPU_VPU_INT_STS)) { + irq_reason = wave5_vdi_read_register(dev, W5_VPU_VINT_REASON); + wave5_vdi_write_register(dev, W5_VPU_VINT_REASON_CLR, irq_reason); wave5_vdi_write_register(dev, W5_VPU_VINT_CLEAR, 0x1); - return IRQ_WAKE_THREAD; - } - - return IRQ_HANDLED; -} + list_for_each_entry(inst, &dev->instances, list) { + seq_done = wave5_vdi_read_register(dev, W5_RET_SEQ_DONE_INSTANCE_INFO); + cmd_done = wave5_vdi_read_register(dev, W5_RET_QUEUE_CMD_DONE_INST); + + if (irq_reason & BIT(INT_WAVE5_INIT_SEQ) || + irq_reason & BIT(INT_WAVE5_ENC_SET_PARAM)) { + if (seq_done & BIT(inst->id)) { + seq_done &= ~BIT(inst->id); + wave5_vdi_write_register(dev, W5_RET_SEQ_DONE_INSTANCE_INFO, + seq_done); + complete(&inst->irq_done); + } + } -static irqreturn_t wave5_vpu_irq_thread(int irq, void *dev_id) -{ - struct vpu_device *dev = dev_id; - struct vpu_instance *inst; - int irq_status, ret; - u32 val; - - list_for_each_entry(inst, &dev->instances, list) { - while (kfifo_len(&inst->irq_status)) { - struct vpu_instance *curr; - - curr = v4l2_m2m_get_curr_priv(inst->v4l2_m2m_dev); - if (curr) { - inst->ops->finish_process(inst); - } else { - ret = kfifo_out(&inst->irq_status, &irq_status, sizeof(int)); - if (!ret) - break; - - val = wave5_vdi_readl(dev, W5_VPU_VINT_REASON_USR); - val &= ~irq_status; - wave5_vdi_write_register(dev, W5_VPU_VINT_REASON_USR, val); - complete(&inst->irq_done); + if (irq_reason & BIT(INT_WAVE5_DEC_PIC) || + irq_reason & BIT(INT_WAVE5_ENC_PIC)) { + if (cmd_done & BIT(inst->id)) { + cmd_done &= ~BIT(inst->id); + wave5_vdi_write_register(dev, W5_RET_QUEUE_CMD_DONE_INST, + cmd_done); + inst->ops->finish_process(inst); + } } + + wave5_vpu_clear_interrupt(inst, irq_reason); } } return IRQ_HANDLED; } -static int wave5_vpu_load_firmware(struct device *dev, const char *fw_name) +static int wave5_vpu_load_firmware(struct device *dev, const char *fw_name, + u32 *revision) { const struct firmware *fw; int ret; - u32 revision; unsigned int product_id; ret = request_firmware(&fw, fw_name, dev); @@ -148,25 +101,21 @@ static int wave5_vpu_load_firmware(struct device *dev, const char *fw_name) ret = wave5_vpu_init_with_bitcode(dev, (u8 *)fw->data, fw->size); if (ret) { dev_err(dev, "vpu_init_with_bitcode, fail: %d\n", ret); - goto release_fw; + release_firmware(fw); + return ret; } release_firmware(fw); - ret = wave5_vpu_get_version_info(dev, &revision, &product_id); + ret = wave5_vpu_get_version_info(dev, revision, &product_id); if (ret) { dev_err(dev, "vpu_get_version_info fail: %d\n", ret); - goto err_without_release; + return ret; } dev_dbg(dev, "%s: enum product_id: %08x, fw revision: %u\n", - __func__, product_id, revision); + __func__, product_id, *revision); return 0; - -release_fw: - release_firmware(fw); -err_without_release: - return ret; } static const struct of_device_id sifive_l2_ids[] = { @@ -180,6 +129,7 @@ static int wave5_vpu_probe(struct platform_device *pdev) struct vpu_device *dev; const struct wave5_match_data *match_data; struct device_node *np; + u32 fw_revision; match_data = device_get_match_data(&pdev->dev); if (!match_data) { @@ -188,8 +138,11 @@ static int wave5_vpu_probe(struct platform_device *pdev) } /* physical addresses limited to 32 bits */ - dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); - dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); + ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); + if (ret) { + dev_err(&pdev->dev, "Failed to set DMA mask: %d\n", ret); + return ret; + } dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); if (!dev) @@ -198,7 +151,6 @@ static int wave5_vpu_probe(struct platform_device *pdev) dev->vdb_register = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(dev->vdb_register)) return PTR_ERR(dev->vdb_register); - dev_dbg(&pdev->dev, "vdb_register %p\n",dev->vdb_register); ida_init(&dev->inst_ida); mutex_init(&dev->dev_lock); @@ -210,8 +162,8 @@ static int wave5_vpu_probe(struct platform_device *pdev) /* continue without clock, assume externally managed */ if (ret < 0) { - dev_err(&pdev->dev, "Getting clocks, fail: %d\n", ret); - return ret; + dev_warn(&pdev->dev, "Getting clocks, fail: %d\n", ret); + ret = 0; } dev->num_clks = ret; @@ -236,15 +188,13 @@ static int wave5_vpu_probe(struct platform_device *pdev) goto err_clk_dis; } - dev->product_code = wave5_vdi_readl(dev, VPU_PRODUCT_CODE_REGISTER); - dev_dbg(&pdev->dev, "product_code %d\n",dev->product_code); + dev->product_code = wave5_vdi_read_register(dev, VPU_PRODUCT_CODE_REGISTER); ret = wave5_vdi_init(&pdev->dev); if (ret < 0) { dev_err(&pdev->dev, "wave5_vdi_init, fail: %d\n", ret); goto err_rst_dis; } dev->product = wave5_vpu_get_product_id(dev); - dev_dbg(&pdev->dev, "product %d\n",dev->product); INIT_LIST_HEAD(&dev->instances); ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev); @@ -274,16 +224,15 @@ static int wave5_vpu_probe(struct platform_device *pdev) ret = -ENXIO; goto err_enc_unreg; } - dev_dbg(&pdev->dev, "irq %d\n",dev->irq); - ret = devm_request_threaded_irq(&pdev->dev, dev->irq, wave5_vpu_irq, - wave5_vpu_irq_thread, 0, "vpu_irq", dev); + ret = devm_request_threaded_irq(&pdev->dev, dev->irq, NULL, + wave5_vpu_irq_thread, IRQF_ONESHOT, "vpu_irq", dev); if (ret) { dev_err(&pdev->dev, "Register interrupt handler, fail: %d\n", ret); goto err_enc_unreg; } - ret = wave5_vpu_load_firmware(&pdev->dev, match_data->fw_name); + ret = wave5_vpu_load_firmware(&pdev->dev, match_data->fw_name, &fw_revision); if (ret) { dev_err(&pdev->dev, "wave5_vpu_load_firmware, fail: %d\n", ret); goto err_enc_unreg; @@ -299,10 +248,11 @@ static int wave5_vpu_probe(struct platform_device *pdev) if (ret) dev->l2_cache_size = 0x200000; - dev_dbg(&pdev->dev, "Added wave5 driver with caps: %s %s and product code: 0x%x\n", - (match_data->flags & WAVE5_IS_ENC) ? "'ENCODE'" : "", - (match_data->flags & WAVE5_IS_DEC) ? "'DECODE'" : "", - dev->product_code); + dev_dbg(&pdev->dev, "Added wave5 driver with caps: %s %s\n", + (match_data->flags & WAVE5_IS_ENC) ? "'ENCODE'" : "", + (match_data->flags & WAVE5_IS_DEC) ? "'DECODE'" : ""); + dev_dbg(&pdev->dev, "Product Code: 0x%x\n", dev->product_code); + dev_dbg(&pdev->dev, "Firmware Revision: %u\n", fw_revision); return 0; err_enc_unreg: @@ -327,7 +277,8 @@ static int wave5_vpu_remove(struct platform_device *pdev) { struct vpu_device *dev = dev_get_drvdata(&pdev->dev); - reset_control_assert(dev->resets); + mutex_destroy(&dev->dev_lock); + mutex_destroy(&dev->hw_lock); clk_bulk_disable_unprepare(dev->num_clks, dev->clks); wave5_vpu_enc_unregister_device(dev); wave5_vpu_dec_unregister_device(dev); @@ -338,39 +289,18 @@ static int wave5_vpu_remove(struct platform_device *pdev) return 0; } -static const struct wave5_match_data wave511_data = { - .flags = WAVE5_IS_DEC, - .fw_name = "wave511_dec_fw.bin", -}; - -static const struct wave5_match_data wave521_data = { - .flags = WAVE5_IS_ENC, - .fw_name = "wave521_enc_fw.bin", -}; - -static const struct wave5_match_data wave521c_data = { - .flags = WAVE5_IS_ENC | WAVE5_IS_DEC, - .fw_name = "wave521c_codec_fw.bin", -}; - -static const struct wave5_match_data default_match_data = { +static const struct wave5_match_data ti_wave521c_data = { .flags = WAVE5_IS_ENC | WAVE5_IS_DEC, - .fw_name = "chagall.bin", + .fw_name = "cnm/wave521c_k3_codec_fw.bin", }; static const struct wave5_match_data sfdec_match_data = { .flags = WAVE5_IS_DEC, - .fw_name = "chagall.bin", + .fw_name = "wave511_dec_fw.bin", }; static const struct of_device_id wave5_dt_ids[] = { - { .compatible = "cnm,cm511-vpu", .data = &wave511_data }, - { .compatible = "cnm,cm517-vpu", .data = &default_match_data }, - { .compatible = "cnm,cm521-vpu", .data = &wave521_data }, - { .compatible = "cnm,cm521c-vpu", .data = &wave521c_data }, - { .compatible = "cnm,cm521c-dual-vpu", .data = &wave521c_data }, - { .compatible = "cnm,cm521e1-vpu", .data = &default_match_data }, - { .compatible = "cnm,cm537-vpu", .data = &default_match_data }, + { .compatible = "ti,k3-j721s2-wave521c", .data = &ti_wave521c_data }, { .compatible = "starfive,vdec", .data = &sfdec_match_data }, { /* sentinel */ } }; diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpu.h b/drivers/media/platform/chips-media/wave5/wave5-vpu.h index e83c186a498e..fe1de3e8a22c 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-vpu.h +++ b/drivers/media/platform/chips-media/wave5/wave5-vpu.h @@ -2,7 +2,7 @@ /* * Wave5 series multi-standard codec IP - basic types * - * Copyright (C) 2021 CHIPS&MEDIA INC + * Copyright (C) 2021-2023 CHIPS&MEDIA INC */ #ifndef __VPU_DRV_H__ #define __VPU_DRV_H__ @@ -23,9 +23,15 @@ #define VDI_SRAM_BASE_ADDR 0x00000000 #define VDI_WAVE511_SRAM_SIZE 0x2D000 -struct vpu_buffer { +struct vpu_src_buffer { + struct v4l2_m2m_buffer v4l2_m2m_buf; + struct list_head list; + bool consumed; +}; + +struct vpu_dst_buffer { struct v4l2_m2m_buffer v4l2_m2m_buf; - bool consumed; + bool display; }; enum vpu_fmt_type { @@ -51,9 +57,14 @@ static inline struct vpu_instance *wave5_ctrl_to_vpu_inst(struct v4l2_ctrl *vctr return container_of(vctrl->handler, struct vpu_instance, v4l2_ctrl_hdl); } -static inline struct vpu_buffer *wave5_to_vpu_buf(struct vb2_v4l2_buffer *vbuf) +static inline struct vpu_src_buffer *wave5_to_vpu_src_buf(struct vb2_v4l2_buffer *vbuf) +{ + return container_of(vbuf, struct vpu_src_buffer, v4l2_m2m_buf.vb); +} + +static inline struct vpu_dst_buffer *wave5_to_vpu_dst_buf(struct vb2_v4l2_buffer *vbuf) { - return container_of(vbuf, struct vpu_buffer, v4l2_m2m_buf.vb); + return container_of(vbuf, struct vpu_dst_buffer, v4l2_m2m_buf.vb); } int wave5_vpu_wait_interrupt(struct vpu_instance *inst, unsigned int timeout); diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpuapi.c b/drivers/media/platform/chips-media/wave5/wave5-vpuapi.c index 5a0078a0d174..1a3efb638dde 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-vpuapi.c +++ b/drivers/media/platform/chips-media/wave5/wave5-vpuapi.c @@ -2,7 +2,7 @@ /* * Wave5 series multi-standard codec IP - helper functions * - * Copyright (C) 2021 CHIPS&MEDIA INC + * Copyright (C) 2021-2023 CHIPS&MEDIA INC */ #include <linux/bug.h> @@ -13,11 +13,6 @@ #define DECODE_ALL_TEMPORAL_LAYERS 0 #define DECODE_ALL_SPATIAL_LAYERS 0 -void wave5_vpu_clear_interrupt_ex(struct vpu_instance *inst, u32 intr_flag) -{ - wave5_vpu_clear_interrupt(inst, intr_flag); -} - static int wave5_initialize_vpu(struct device *dev, u8 *code, size_t size) { int ret; @@ -52,6 +47,39 @@ int wave5_vpu_init_with_bitcode(struct device *dev, u8 *bitcode, size_t size) return wave5_initialize_vpu(dev, bitcode, size); } +int wave5_vpu_flush_instance(struct vpu_instance *inst) +{ + int ret = 0; + int retry = 0; + + ret = mutex_lock_interruptible(&inst->dev->hw_lock); + if (ret) + return ret; + do { + /* + * Repeat the FLUSH command until the firmware reports that the + * VPU isn't running anymore + */ + ret = wave5_vpu_hw_flush_instance(inst); + if (ret < 0 && ret != -EBUSY) { + dev_warn(inst->dev->dev, "Flush of %s instance with id: %d fail: %d\n", + inst->type == VPU_INST_TYPE_DEC ? "DECODER" : "ENCODER", inst->id, + ret); + mutex_unlock(&inst->dev->hw_lock); + return ret; + } + if (ret == -EBUSY && retry++ >= MAX_FIRMWARE_CALL_RETRY) { + dev_warn(inst->dev->dev, "Flush of %s instance with id: %d timed out!\n", + inst->type == VPU_INST_TYPE_DEC ? "DECODER" : "ENCODER", inst->id); + mutex_unlock(&inst->dev->hw_lock); + return -ETIMEDOUT; + } + } while (ret != 0); + mutex_unlock(&inst->dev->hw_lock); + + return ret; +} + int wave5_vpu_get_version_info(struct device *dev, u32 *revision, unsigned int *product_id) { int ret; @@ -77,8 +105,6 @@ err_out: static int wave5_check_dec_open_param(struct vpu_instance *inst, struct dec_open_param *param) { - struct vpu_attr *p_attr = &inst->dev->attr; - if (inst->id >= MAX_NUM_INSTANCE) { dev_err(inst->dev->dev, "Too many simultaneous instances: %d (max: %u)\n", inst->id, MAX_NUM_INSTANCE); @@ -91,33 +117,14 @@ static int wave5_check_dec_open_param(struct vpu_instance *inst, struct dec_open return -EINVAL; } - if (param->bitstream_mode == BS_MODE_INTERRUPT && - (param->bitstream_buffer_size % 1024 || - param->bitstream_buffer_size < MIN_BITSTREAM_BUFFER_SIZE)) { + if (param->bitstream_buffer_size % 1024 || + param->bitstream_buffer_size < MIN_BITSTREAM_BUFFER_SIZE) { dev_err(inst->dev->dev, "Bitstream buffer size must be aligned to a multiple of 1024 and have a minimum size of %d\n", MIN_BITSTREAM_BUFFER_SIZE); return -EINVAL; } - if (!(BIT(param->bitstream_mode) && p_attr->support_bitstream_mode)) { - dev_err(inst->dev->dev, - "Bitstream mode only configurable with the 'support_bitstream_mode' flag"); - return -EINVAL; - } - - if (!(BIT(param->frame_endian) && p_attr->support_endian_mask)) { - dev_err(inst->dev->dev, - "Frame endianness only configurable with the 'support_endian_mask' flag"); - return -EINVAL; - } - - if (!(BIT(param->stream_endian) && p_attr->support_endian_mask)) { - dev_err(inst->dev->dev, - "Stream endianness only configurable with the 'support_endian_mask' flag"); - return -EINVAL; - } - return 0; } @@ -142,12 +149,6 @@ int wave5_vpu_dec_open(struct vpu_instance *inst, struct dec_open_param *open_pa return -ENODEV; } - inst->codec_info = kzalloc(sizeof(*inst->codec_info), GFP_KERNEL); - if (!inst->codec_info) { - mutex_unlock(&vpu_dev->hw_lock); - return -ENOMEM; - } - p_dec_info = &inst->codec_info->dec_info; memcpy(&p_dec_info->open_param, open_param, sizeof(struct dec_open_param)); @@ -159,30 +160,39 @@ int wave5_vpu_dec_open(struct vpu_instance *inst, struct dec_open_param *open_pa p_dec_info->stream_buf_size = buffer_size; p_dec_info->stream_buf_end_addr = buffer_addr + buffer_size; p_dec_info->reorder_enable = TRUE; - p_dec_info->mirror_direction = MIRDIR_NONE; p_dec_info->temp_id_select_mode = TEMPORAL_ID_MODE_ABSOLUTE; p_dec_info->target_temp_id = DECODE_ALL_TEMPORAL_LAYERS; p_dec_info->target_spatial_id = DECODE_ALL_SPATIAL_LAYERS; ret = wave5_vpu_build_up_dec_param(inst, open_param); - if (ret) - goto free_codec_info; - mutex_unlock(&vpu_dev->hw_lock); - return 0; + return ret; +} -free_codec_info: - kfree(inst->codec_info); - mutex_unlock(&vpu_dev->hw_lock); +static int reset_auxiliary_buffers(struct vpu_instance *inst, unsigned int index) +{ + struct dec_info *p_dec_info = &inst->codec_info->dec_info; - return ret; + if (index >= MAX_REG_FRAME) + return 1; + + if (p_dec_info->vb_mv[index].size == 0 && p_dec_info->vb_fbc_y_tbl[index].size == 0 && + p_dec_info->vb_fbc_c_tbl[index].size == 0) + return 1; + + wave5_vdi_free_dma_memory(inst->dev, &p_dec_info->vb_mv[index]); + wave5_vdi_free_dma_memory(inst->dev, &p_dec_info->vb_fbc_y_tbl[index]); + wave5_vdi_free_dma_memory(inst->dev, &p_dec_info->vb_fbc_c_tbl[index]); + + return 0; } int wave5_vpu_dec_close(struct vpu_instance *inst, u32 *fail_res) { struct dec_info *p_dec_info = &inst->codec_info->dec_info; int ret; + int retry = 0; struct vpu_device *vpu_dev = inst->dev; int i; @@ -194,38 +204,38 @@ int wave5_vpu_dec_close(struct vpu_instance *inst, u32 *fail_res) if (ret) return ret; - ret = wave5_vpu_dec_finish_seq(inst, fail_res); - if (ret) { - dev_warn(inst->dev->dev, "dec_finish_seq timed out\n"); + do { + ret = wave5_vpu_dec_finish_seq(inst, fail_res); + if (ret < 0 && *fail_res != WAVE5_SYSERR_VPU_STILL_RUNNING) { + dev_warn(inst->dev->dev, "dec_finish_seq timed out\n"); + goto unlock_and_return; + } - if (*fail_res == WAVE5_SYSERR_VPU_STILL_RUNNING) { - mutex_unlock(&vpu_dev->hw_lock); - return ret; + if (*fail_res == WAVE5_SYSERR_VPU_STILL_RUNNING && + retry++ >= MAX_FIRMWARE_CALL_RETRY) { + ret = -ETIMEDOUT; + goto unlock_and_return; } - } + } while (ret != 0); dev_dbg(inst->dev->dev, "%s: dec_finish_seq complete\n", __func__); - if (p_dec_info->vb_work.size) - wave5_vdi_free_dma_memory(vpu_dev, &p_dec_info->vb_work); + wave5_vdi_free_dma_memory(vpu_dev, &p_dec_info->vb_work); for (i = 0 ; i < MAX_REG_FRAME; i++) { - if (p_dec_info->vb_mv[i].size) - wave5_vdi_free_dma_memory(vpu_dev, &p_dec_info->vb_mv[i]); - if (p_dec_info->vb_fbc_y_tbl[i].size) - wave5_vdi_free_dma_memory(vpu_dev, &p_dec_info->vb_fbc_y_tbl[i]); - if (p_dec_info->vb_fbc_c_tbl[i].size) - wave5_vdi_free_dma_memory(vpu_dev, &p_dec_info->vb_fbc_c_tbl[i]); + ret = reset_auxiliary_buffers(inst, i); + if (ret) { + ret = 0; + break; + } } - if (p_dec_info->vb_task.size) - wave5_vdi_free_dma_memory(vpu_dev, &p_dec_info->vb_task); + wave5_vdi_free_dma_memory(vpu_dev, &p_dec_info->vb_task); +unlock_and_return: mutex_unlock(&vpu_dev->hw_lock); - kfree(inst->codec_info); - - return 0; + return ret; } int wave5_vpu_dec_issue_seq_init(struct vpu_instance *inst) @@ -258,7 +268,7 @@ int wave5_vpu_dec_complete_seq_init(struct vpu_instance *inst, struct dec_initia if (!ret) p_dec_info->initial_info_obtained = true; - info->rd_ptr = wave5_vpu_dec_get_rd_ptr(inst); + info->rd_ptr = wave5_dec_get_rd_ptr(inst); info->wr_ptr = p_dec_info->stream_wr_ptr; p_dec_info->initial_info = *info; @@ -269,8 +279,7 @@ int wave5_vpu_dec_complete_seq_init(struct vpu_instance *inst, struct dec_initia } int wave5_vpu_dec_register_frame_buffer_ex(struct vpu_instance *inst, int num_of_decoding_fbs, - int num_of_display_fbs, int stride, int height, - int map_type) + int num_of_display_fbs, int stride, int height) { struct dec_info *p_dec_info; int ret; @@ -326,21 +335,17 @@ int wave5_vpu_dec_get_bitstream_buffer(struct vpu_instance *inst, dma_addr_t *pr ret = mutex_lock_interruptible(&vpu_dev->hw_lock); if (ret) return ret; - rd_ptr = wave5_vpu_dec_get_rd_ptr(inst); + rd_ptr = wave5_dec_get_rd_ptr(inst); mutex_unlock(&vpu_dev->hw_lock); wr_ptr = p_dec_info->stream_wr_ptr; - if (p_dec_info->open_param.bitstream_mode != BS_MODE_PIC_END) { - if (wr_ptr < rd_ptr) - room = rd_ptr - wr_ptr; - else - room = (p_dec_info->stream_buf_end_addr - wr_ptr) + - (rd_ptr - p_dec_info->stream_buf_start_addr); - room--; - } else { - room = (p_dec_info->stream_buf_end_addr - wr_ptr); - } + if (wr_ptr < rd_ptr) + room = rd_ptr - wr_ptr; + else + room = (p_dec_info->stream_buf_end_addr - wr_ptr) + + (rd_ptr - p_dec_info->stream_buf_start_addr); + room--; if (prd_ptr) *prd_ptr = rd_ptr; @@ -373,15 +378,13 @@ int wave5_vpu_dec_update_bitstream_buffer(struct vpu_instance *inst, size_t size wr_ptr += size; - if (p_dec_info->open_param.bitstream_mode != BS_MODE_PIC_END) { - if (wr_ptr > p_dec_info->stream_buf_end_addr) { - u32 room = wr_ptr - p_dec_info->stream_buf_end_addr; + if (wr_ptr > p_dec_info->stream_buf_end_addr) { + u32 room = wr_ptr - p_dec_info->stream_buf_end_addr; - wr_ptr = p_dec_info->stream_buf_start_addr; - wr_ptr += room; - } else if (wr_ptr == p_dec_info->stream_buf_end_addr) { - wr_ptr = p_dec_info->stream_buf_start_addr; - } + wr_ptr = p_dec_info->stream_buf_start_addr; + wr_ptr += room; + } else if (wr_ptr == p_dec_info->stream_buf_end_addr) { + wr_ptr = p_dec_info->stream_buf_start_addr; } p_dec_info->stream_wr_ptr = wr_ptr; @@ -397,20 +400,20 @@ int wave5_vpu_dec_update_bitstream_buffer(struct vpu_instance *inst, size_t size return ret; } -int wave5_vpu_dec_start_one_frame(struct vpu_instance *inst, struct dec_param *param, u32 *res_fail) +int wave5_vpu_dec_start_one_frame(struct vpu_instance *inst, u32 *res_fail) { struct dec_info *p_dec_info = &inst->codec_info->dec_info; int ret; struct vpu_device *vpu_dev = inst->dev; - if (p_dec_info->stride == 0) // this means frame buffers have not been registered. + if (p_dec_info->stride == 0) /* this means frame buffers have not been registered. */ return -EINVAL; ret = mutex_lock_interruptible(&vpu_dev->hw_lock); if (ret) return ret; - ret = wave5_vpu_decode(inst, param, res_fail); + ret = wave5_vpu_decode(inst, res_fail); mutex_unlock(&vpu_dev->hw_lock); @@ -438,6 +441,22 @@ int wave5_vpu_dec_set_rd_ptr(struct vpu_instance *inst, dma_addr_t addr, int upd return ret; } +dma_addr_t wave5_vpu_dec_get_rd_ptr(struct vpu_instance *inst) +{ + int ret; + dma_addr_t rd_ptr; + + ret = mutex_lock_interruptible(&inst->dev->hw_lock); + if (ret) + return ret; + + rd_ptr = wave5_dec_get_rd_ptr(inst); + + mutex_unlock(&inst->dev->hw_lock); + + return rd_ptr; +} + int wave5_vpu_dec_get_output_info(struct vpu_instance *inst, struct dec_output_info *info) { struct dec_info *p_dec_info; @@ -470,13 +489,13 @@ int wave5_vpu_dec_get_output_info(struct vpu_instance *inst, struct dec_output_i decoded_index = info->index_frame_decoded; - // calculate display frame region + /* calculate display frame region */ val = 0; - //default value rect_info.left = 0; rect_info.right = 0; rect_info.top = 0; rect_info.bottom = 0; + if (decoded_index < WAVE5_MAX_FBS) { if (inst->std == W_HEVC_DEC || inst->std == W_AVC_DEC) rect_info = p_dec_info->initial_info.pic_crop_rect; @@ -484,120 +503,48 @@ int wave5_vpu_dec_get_output_info(struct vpu_instance *inst, struct dec_output_i if (inst->std == W_HEVC_DEC) p_dec_info->dec_out_info[decoded_index].decoded_poc = info->decoded_poc; - if (inst->std == W_AVS2_DEC) - p_dec_info->dec_out_info[decoded_index].avs2_info.decoded_poi = - info->avs2_info.decoded_poi; - p_dec_info->dec_out_info[decoded_index].rc_decoded = rect_info; } info->rc_decoded = rect_info; - dev_dbg(inst->dev->dev, "%s %d %u %u %u %u\n", __func__, __LINE__, - rect_info.left, rect_info.right, rect_info.top, rect_info.bottom); disp_idx = info->index_frame_display; - disp_info = &p_dec_info->dec_out_info[disp_idx]; if (info->index_frame_display >= 0 && info->index_frame_display < WAVE5_MAX_FBS) { - u32 width = info->dec_pic_width; - u32 height = info->dec_pic_height; - dev_dbg(inst->dev->dev, "%s %d dec_pic_width %u dec_pic_height %u\n", - __func__, __LINE__, info->dec_pic_width, info->dec_pic_height); - + disp_info = &p_dec_info->dec_out_info[disp_idx]; if (info->index_frame_display != info->index_frame_decoded) { /* * when index_frame_decoded < 0, and index_frame_display >= 0 * info->dec_pic_width and info->dec_pic_height are still valid * but those of p_dec_info->dec_out_info[disp_idx] are invalid in VP9 */ - width = disp_info->dec_pic_width; - height = disp_info->dec_pic_height; - } - // TODO no rotation/mirror v4l2 cmd implemented for the decoder - if (p_dec_info->rotation_enable || p_dec_info->mirror_enable) - if (p_dec_info->rotation_angle == 90 || p_dec_info->rotation_angle == 270) - swap(width, height); - - if (p_dec_info->rotation_enable) { - switch (p_dec_info->rotation_angle) { - case 90: - info->rc_display.left = disp_info->rc_decoded.top; - info->rc_display.right = disp_info->rc_decoded.bottom; - info->rc_display.top = disp_info->rc_decoded.right; - info->rc_display.bottom = disp_info->rc_decoded.left; - break; - case 270: - info->rc_display.left = disp_info->rc_decoded.bottom; - info->rc_display.right = disp_info->rc_decoded.top; - info->rc_display.top = disp_info->rc_decoded.left; - info->rc_display.bottom = disp_info->rc_decoded.right; - break; - case 180: - info->rc_display.left = disp_info->rc_decoded.right; - info->rc_display.right = disp_info->rc_decoded.left; - info->rc_display.top = disp_info->rc_decoded.bottom; - info->rc_display.bottom = disp_info->rc_decoded.top; - break; - default: - info->rc_display = disp_info->rc_decoded; - break; - } + info->disp_pic_width = disp_info->dec_pic_width; + info->disp_pic_height = disp_info->dec_pic_height; } else { - info->rc_display = disp_info->rc_decoded; - } - - if (p_dec_info->mirror_enable) { - if (p_dec_info->mirror_direction & MIRDIR_VER) - swap(info->rc_display.top, info->rc_display.bottom); - if (p_dec_info->mirror_direction & MIRDIR_HOR) - swap(info->rc_display.left, info->rc_display.right); + info->disp_pic_width = info->dec_pic_width; + info->disp_pic_height = info->dec_pic_height; } - switch (inst->std) { - case W_AVS2_DEC: - info->avs2_info.display_poi = - disp_info->avs2_info.decoded_poi; - break; - default: - break; - } + info->rc_display = disp_info->rc_decoded; - info->disp_pic_width = width; - info->disp_pic_height = height; } else { info->rc_display.left = 0; info->rc_display.right = 0; info->rc_display.top = 0; info->rc_display.bottom = 0; - - if (p_dec_info->rotation_enable || p_dec_info->mirror_enable || - p_dec_info->dering_enable) { - info->disp_pic_width = info->dec_pic_width; - info->disp_pic_height = info->dec_pic_height; - } else { - info->disp_pic_width = 0; - info->disp_pic_height = 0; - } + info->disp_pic_width = 0; + info->disp_pic_height = 0; } - dev_dbg(inst->dev->dev, "%s %d disp_pic_width %u disp_pic_height %u\n", - __func__, __LINE__, info->disp_pic_width, info->disp_pic_height); - p_dec_info->stream_rd_ptr = wave5_vpu_dec_get_rd_ptr(inst); + p_dec_info->stream_rd_ptr = wave5_dec_get_rd_ptr(inst); p_dec_info->frame_display_flag = vpu_read_reg(vpu_dev, W5_RET_DEC_DISP_IDC); - if (inst->std == W_VP9_DEC) - p_dec_info->frame_display_flag &= 0xFFFF; - if (p_dec_info->dering_enable || p_dec_info->mirror_enable || p_dec_info->rotation_enable) { - info->disp_frame = p_dec_info->rotator_output; - info->disp_frame.stride = p_dec_info->rotator_stride; - } else { - val = p_dec_info->num_of_decoding_fbs; //fb_offset + val = p_dec_info->num_of_decoding_fbs; //fb_offset - max_dec_index = (p_dec_info->num_of_decoding_fbs > p_dec_info->num_of_display_fbs) ? - p_dec_info->num_of_decoding_fbs : p_dec_info->num_of_display_fbs; + max_dec_index = (p_dec_info->num_of_decoding_fbs > p_dec_info->num_of_display_fbs) ? + p_dec_info->num_of_decoding_fbs : p_dec_info->num_of_display_fbs; - if (info->index_frame_display >= 0 && - info->index_frame_display < (int)max_dec_index) - info->disp_frame = inst->frame_buf[val + info->index_frame_display]; - } + if (info->index_frame_display >= 0 && + info->index_frame_display < (int)max_dec_index) + info->disp_frame = inst->frame_buf[val + info->index_frame_display]; info->rd_ptr = p_dec_info->stream_rd_ptr; info->wr_ptr = p_dec_info->stream_wr_ptr; @@ -610,8 +557,7 @@ int wave5_vpu_dec_get_output_info(struct vpu_instance *inst, struct dec_output_i if (disp_idx < WAVE5_MAX_FBS) info->disp_frame.sequence_no = info->sequence_no; - if (info->sequence_changed && - !(info->sequence_changed & SEQ_CHANGE_INTER_RES_CHANGE)) { + if (info->sequence_changed) { memcpy((void *)&p_dec_info->initial_info, (void *)&p_dec_info->new_seq_info, sizeof(struct dec_initial_info)); p_dec_info->initial_info.sequence_no++; @@ -626,7 +572,7 @@ err_out: int wave5_vpu_dec_clr_disp_flag(struct vpu_instance *inst, int index) { struct dec_info *p_dec_info = &inst->codec_info->dec_info; - int ret = 0; + int ret; struct vpu_device *vpu_dev = inst->dev; if (index >= p_dec_info->num_of_display_fbs) @@ -659,9 +605,23 @@ int wave5_vpu_dec_set_disp_flag(struct vpu_instance *inst, int index) return ret; } +int wave5_vpu_dec_reset_framebuffer(struct vpu_instance *inst, unsigned int index) +{ + if (index >= MAX_REG_FRAME) + return -EINVAL; + + if (inst->frame_vbuf[index].size == 0) + return -EINVAL; + + wave5_vdi_free_dma_memory(inst->dev, &inst->frame_vbuf[index]); + + return 0; +} + int wave5_vpu_dec_give_command(struct vpu_instance *inst, enum codec_command cmd, void *parameter) { struct dec_info *p_dec_info = &inst->codec_info->dec_info; + int ret = 0; switch (cmd) { case DEC_GET_QUEUE_STATUS: { @@ -671,17 +631,19 @@ int wave5_vpu_dec_give_command(struct vpu_instance *inst, enum codec_command cmd queue_info->report_queue_count = p_dec_info->report_queue_count; break; } - case ENABLE_DEC_THUMBNAIL_MODE: - p_dec_info->thumbnail_mode = true; - break; case DEC_RESET_FRAMEBUF_INFO: { int i; - for (i = 0; i < inst->dst_buf_count; i++) { - wave5_vdi_free_dma_memory(inst->dev, &inst->frame_vbuf[i]); - wave5_vdi_free_dma_memory(inst->dev, &p_dec_info->vb_mv[i]); - wave5_vdi_free_dma_memory(inst->dev, &p_dec_info->vb_fbc_y_tbl[i]); - wave5_vdi_free_dma_memory(inst->dev, &p_dec_info->vb_fbc_c_tbl[i]); + for (i = 0; i < MAX_REG_FRAME; i++) { + ret = wave5_vpu_dec_reset_framebuffer(inst, i); + if (ret) + break; + } + + for (i = 0; i < MAX_REG_FRAME; i++) { + ret = reset_auxiliary_buffers(inst, i); + if (ret) + break; } wave5_vdi_free_dma_memory(inst->dev, &p_dec_info->vb_task); @@ -698,7 +660,7 @@ int wave5_vpu_dec_give_command(struct vpu_instance *inst, enum codec_command cmd return -EINVAL; } - return 0; + return ret; } int wave5_vpu_enc_open(struct vpu_instance *inst, struct enc_open_param *open_param) @@ -720,24 +682,10 @@ int wave5_vpu_enc_open(struct vpu_instance *inst, struct enc_open_param *open_pa return -ENODEV; } - inst->codec_info = kzalloc(sizeof(*inst->codec_info), GFP_KERNEL); - if (!inst->codec_info) { - mutex_unlock(&vpu_dev->hw_lock); - return -ENOMEM; - } - p_enc_info = &inst->codec_info->enc_info; p_enc_info->open_param = *open_param; ret = wave5_vpu_build_up_enc_param(vpu_dev->dev, inst, open_param); - if (ret) - goto free_codec_info; - mutex_unlock(&vpu_dev->hw_lock); - - return 0; - -free_codec_info: - kfree(inst->codec_info); mutex_unlock(&vpu_dev->hw_lock); return ret; @@ -745,55 +693,49 @@ free_codec_info: int wave5_vpu_enc_close(struct vpu_instance *inst, u32 *fail_res) { - struct enc_info *p_enc_info; + struct enc_info *p_enc_info = &inst->codec_info->enc_info; int ret; + int retry = 0; struct vpu_device *vpu_dev = inst->dev; - *fail_res = 0; + *fail_res = 0; if (!inst->codec_info) return -EINVAL; - p_enc_info = &inst->codec_info->enc_info; ret = mutex_lock_interruptible(&vpu_dev->hw_lock); if (ret) return ret; - ret = wave5_vpu_enc_finish_seq(inst, fail_res); - if (ret) { - dev_warn(inst->dev->dev, "enc seq end timed out\n"); - - if (*fail_res == WAVE5_SYSERR_VPU_STILL_RUNNING) { + do { + ret = wave5_vpu_enc_finish_seq(inst, fail_res); + if (ret < 0 && *fail_res != WAVE5_SYSERR_VPU_STILL_RUNNING) { + dev_warn(inst->dev->dev, "enc_finish_seq timed out\n"); mutex_unlock(&vpu_dev->hw_lock); return ret; } - } - - dev_dbg(inst->dev->dev, "%s: enc seq end timed out\n", __func__); - if (p_enc_info->vb_work.size) - wave5_vdi_free_dma_memory(vpu_dev, &p_enc_info->vb_work); - - if (inst->std == W_HEVC_ENC || inst->std == W_AVC_ENC) { - if (p_enc_info->vb_sub_sam_buf.size) - wave5_vdi_free_dma_memory(vpu_dev, &p_enc_info->vb_sub_sam_buf); + if (*fail_res == WAVE5_SYSERR_VPU_STILL_RUNNING && + retry++ >= MAX_FIRMWARE_CALL_RETRY) { + mutex_unlock(&vpu_dev->hw_lock); + return -ETIMEDOUT; + } + } while (ret != 0); - if (p_enc_info->vb_mv.size) - wave5_vdi_free_dma_memory(vpu_dev, &p_enc_info->vb_mv); + dev_dbg(inst->dev->dev, "%s: enc_finish_seq complete\n", __func__); - if (p_enc_info->vb_fbc_y_tbl.size) - wave5_vdi_free_dma_memory(vpu_dev, &p_enc_info->vb_fbc_y_tbl); + wave5_vdi_free_dma_memory(vpu_dev, &p_enc_info->vb_work); - if (p_enc_info->vb_fbc_c_tbl.size) - wave5_vdi_free_dma_memory(vpu_dev, &p_enc_info->vb_fbc_c_tbl); + if (inst->std == W_HEVC_ENC || inst->std == W_AVC_ENC) { + wave5_vdi_free_dma_memory(vpu_dev, &p_enc_info->vb_sub_sam_buf); + wave5_vdi_free_dma_memory(vpu_dev, &p_enc_info->vb_mv); + wave5_vdi_free_dma_memory(vpu_dev, &p_enc_info->vb_fbc_y_tbl); + wave5_vdi_free_dma_memory(vpu_dev, &p_enc_info->vb_fbc_c_tbl); } - if (p_enc_info->vb_task.size) - wave5_vdi_free_dma_memory(vpu_dev, &p_enc_info->vb_task); + wave5_vdi_free_dma_memory(vpu_dev, &p_enc_info->vb_task); mutex_unlock(&vpu_dev->hw_lock); - kfree(inst->codec_info); - return 0; } @@ -840,7 +782,6 @@ int wave5_vpu_enc_register_frame_buffer(struct vpu_instance *inst, unsigned int inst->frame_buf[i].stride = stride; inst->frame_buf[i].height = height; inst->frame_buf[i].map_type = COMPRESSED_FRAME_MAP; - inst->frame_buf[i].endian = VDI_128BIT_LITTLE_ENDIAN; inst->frame_buf[i].buf_y_size = size_luma; inst->frame_buf[i].buf_cb = inst->frame_buf[i].buf_y + size_luma; inst->frame_buf[i].buf_cb_size = size_chroma; @@ -863,45 +804,19 @@ static int wave5_check_enc_param(struct vpu_instance *inst, struct enc_param *pa if (!param) return -EINVAL; - if (!param->skip_picture && !param->source_frame) + if (!param->source_frame) return -EINVAL; if (p_enc_info->open_param.bit_rate == 0 && inst->std == W_HEVC_ENC) { - if (param->force_pic_qp_enable && - (param->force_pic_qp_i > MAX_INTRA_QP || param->force_pic_qp_p > MAX_INTRA_QP || - param->force_pic_qp_b > MAX_INTRA_QP)) - return -EINVAL; - if (!p_enc_info->ring_buffer_enable && - (param->pic_stream_buffer_addr % 16 || param->pic_stream_buffer_size == 0)) + if (param->pic_stream_buffer_addr % 16 || param->pic_stream_buffer_size == 0) return -EINVAL; } - if (!p_enc_info->ring_buffer_enable && - (param->pic_stream_buffer_addr % 8 || param->pic_stream_buffer_size == 0)) + if (param->pic_stream_buffer_addr % 8 || param->pic_stream_buffer_size == 0) return -EINVAL; return 0; } -static uint64_t wave5_get_timestamp(struct vpu_instance *inst) -{ - struct enc_info *p_enc_info; - u64 pts; - u32 fps; - - if (!inst->codec_info) - return 0; - - p_enc_info = &inst->codec_info->enc_info; - fps = p_enc_info->open_param.frame_rate_info; - if (fps == 0) - fps = 30; - - pts = p_enc_info->cur_pts; - p_enc_info->cur_pts += 90000 / fps; /* 90_k_hz/fps */ - - return pts; -} - int wave5_vpu_enc_start_one_frame(struct vpu_instance *inst, struct enc_param *param, u32 *fail_res) { struct enc_info *p_enc_info = &inst->codec_info->enc_info; @@ -910,7 +825,7 @@ int wave5_vpu_enc_start_one_frame(struct vpu_instance *inst, struct enc_param *p *fail_res = 0; - if (p_enc_info->stride == 0) // this means frame buffers have not been registered. + if (p_enc_info->stride == 0) /* this means frame buffers have not been registered. */ return -EINVAL; ret = wave5_check_enc_param(inst, param); @@ -921,8 +836,7 @@ int wave5_vpu_enc_start_one_frame(struct vpu_instance *inst, struct enc_param *p if (ret) return ret; - p_enc_info->pts_map[param->src_idx] = p_enc_info->open_param.enable_pts ? - wave5_get_timestamp(inst) : param->pts; + p_enc_info->pts_map[param->src_idx] = param->pts; ret = wave5_vpu_encode(inst, param, fail_res); diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h b/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h index d7b5717fd9c1..3c70d4572455 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h +++ b/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h @@ -2,14 +2,14 @@ /* * Wave5 series multi-standard codec IP - helper definitions * - * Copyright (C) 2021 CHIPS&MEDIA INC + * Copyright (C) 2021-2023 CHIPS&MEDIA INC */ #ifndef VPUAPI_H_INCLUDED #define VPUAPI_H_INCLUDED -#include <linux/kfifo.h> #include <linux/idr.h> +#include <linux/genalloc.h> #include <media/v4l2-device.h> #include <media/v4l2-mem2mem.h> #include <media/v4l2-ctrls.h> @@ -39,6 +39,7 @@ enum vpu_instance_state { VPU_INST_STATE_STOP = 4 }; +/* Maximum available on hardware. */ #define WAVE5_MAX_FBS 32 #define MAX_REG_FRAME (WAVE5_MAX_FBS * 2) @@ -47,13 +48,6 @@ enum vpu_instance_state { #define WAVE5_DEC_HEVC_BUF_SIZE(_w, _h) (DIV_ROUND_UP(_w, 64) * DIV_ROUND_UP(_h, 64) * 256 + 64) #define WAVE5_DEC_AVC_BUF_SIZE(_w, _h) ((((ALIGN(_w, 256) / 16) * (ALIGN(_h, 16) / 16)) + 16) * 80) -#define WAVE5_DEC_VP9_BUF_SIZE(_w, _h) (((ALIGN(_w, 64) * ALIGN(_h, 64)) >> 2)) -#define WAVE5_DEC_AVS2_BUF_SIZE(_w, _h) (((ALIGN(_w, 64) * ALIGN(_h, 64)) >> 5)) -// AV1 BUF SIZE : MFMV + segment ID + CDF probs table + film grain param Y+ film graim param C -#define WAVE5_DEC_AV1_BUF_SZ_1(_w, _h) \ - (((ALIGN(_w, 64) / 64) * (ALIGN(_h, 64) / 64) * 512) + 41984 + 8192 + 4864) -#define WAVE5_DEC_AV1_BUF_SZ_2(_w1, _w2, _h) \ - (((ALIGN(_w1, 64) / 64) * 256 + (ALIGN(_w2, 256) / 64) * 128) * (ALIGN(_h, 64) / 64)) #define WAVE5_FBC_LUMA_TABLE_SIZE(_w, _h) (ALIGN(_h, 64) * ALIGN(_w, 256) / 32) #define WAVE5_FBC_CHROMA_TABLE_SIZE(_w, _h) (ALIGN((_h), 64) * ALIGN((_w) / 2, 256) / 32) @@ -65,20 +59,7 @@ enum vpu_instance_state { */ enum cod_std { STD_AVC = 0, - STD_VC1 = 1, - STD_MPEG2 = 2, - STD_MPEG4 = 3, - STD_H263 = 4, - STD_DIV3 = 5, - STD_RV = 6, - STD_AVS = 7, - STD_THO = 9, - STD_VP3 = 10, - STD_VP8 = 11, STD_HEVC = 12, - STD_VP9 = 13, - STD_AVS2 = 14, - STD_AV1 = 16, STD_MAX }; @@ -87,13 +68,10 @@ enum wave_std { W_HEVC_ENC = 0x01, W_AVC_DEC = 0x02, W_AVC_ENC = 0x03, - W_VP9_DEC = 0x16, - W_AVS2_DEC = 0x18, - W_AV1_DEC = 0x1A, STD_UNKNOWN = 0xFF }; -enum SET_PARAM_OPTION { +enum set_param_option { OPT_COMMON = 0, /* SET_PARAM command option for encoding sequence */ OPT_CUSTOM_GOP = 1, /* SET_PARAM command option for setting custom GOP */ OPT_CUSTOM_HEADER = 2, /* SET_PARAM command option for setting custom VPS/SPS/PPS */ @@ -101,18 +79,6 @@ enum SET_PARAM_OPTION { OPT_CHANGE_PARAM = 0x10, }; -enum DEC_PIC_HDR_OPTION { - INIT_SEQ_NORMAL = 0x01, - INIT_SEQ_W_THUMBNAIL = 0x11, -}; - -enum DEC_PIC_OPTION { - DEC_PIC_NORMAL = 0x00, /* it is normal mode of DEC_PIC command */ - DEC_PIC_W_THUMBNAIL = 0x10, /* thumbnail mode (skip non-IRAP without reference reg) */ - SKIP_NON_IRAP = 0x11, /* it skips to decode non-IRAP pictures */ - SKIP_NON_REF_PIC = 0x13 -}; - /************************************************************************/ /* PROFILE & LEVEL */ /************************************************************************/ @@ -139,6 +105,12 @@ enum DEC_PIC_OPTION { /* utility macros */ /************************************************************************/ +/* Initialize sequence firmware command mode */ +#define INIT_SEQ_NORMAL 1 + +/* Decode firmware command mode */ +#define DEC_PIC_NORMAL 0 + /* bit_alloc_mode */ #define BIT_ALLOC_MODE_FIXED_RATIO 2 @@ -190,56 +162,34 @@ enum DEC_PIC_OPTION { #define MIN_VBV_BUFFER_SIZE 10 #define MAX_VBV_BUFFER_SIZE 3000 -/* Bitstream buffer option: Explicit End - * When set to 1 the VPU assumes that the bitstream has at least one frame and - * will read until the end of the bitstream buffer. - * When set to 0 the VPU will not read the last few bytes. - * This option can be set anytime but cannot be cleared during processing. - * It can be set to force finish decoding even though there is not enough - * bitstream data for a full frame. - */ -#define BS_EXPLICIT_END_MODE_ON 1 - #define BUFFER_MARGIN 4096 -/************************************************************************/ -/* */ -/************************************************************************/ -/** - * \brief parameters of DEC_SET_SEQ_CHANGE_MASK +#define MAX_FIRMWARE_CALL_RETRY 10 + +#define VDI_LITTLE_ENDIAN 0x0 + +/* + * Parameters of DEC_SET_SEQ_CHANGE_MASK */ #define SEQ_CHANGE_ENABLE_PROFILE BIT(5) -#define SEQ_CHANGE_CHROMA_FORMAT_IDC BIT(15) /* AV1 */ #define SEQ_CHANGE_ENABLE_SIZE BIT(16) -#define SEQ_CHANGE_INTER_RES_CHANGE BIT(17) /* VP9 */ #define SEQ_CHANGE_ENABLE_BITDEPTH BIT(18) #define SEQ_CHANGE_ENABLE_DPB_COUNT BIT(19) - -#define SEQ_CHANGE_ENABLE_ALL_VP9 (SEQ_CHANGE_ENABLE_PROFILE | \ - SEQ_CHANGE_ENABLE_SIZE | \ - SEQ_CHANGE_INTER_RES_CHANGE | \ - SEQ_CHANGE_ENABLE_BITDEPTH | \ - SEQ_CHANGE_ENABLE_DPB_COUNT) +#define SEQ_CHANGE_ENABLE_ASPECT_RATIO BIT(21) +#define SEQ_CHANGE_ENABLE_VIDEO_SIGNAL BIT(23) +#define SEQ_CHANGE_ENABLE_VUI_TIMING_INFO BIT(29) #define SEQ_CHANGE_ENABLE_ALL_HEVC (SEQ_CHANGE_ENABLE_PROFILE | \ SEQ_CHANGE_ENABLE_SIZE | \ SEQ_CHANGE_ENABLE_BITDEPTH | \ SEQ_CHANGE_ENABLE_DPB_COUNT) -#define SEQ_CHANGE_ENABLE_ALL_AVS2 (SEQ_CHANGE_ENABLE_PROFILE | \ - SEQ_CHANGE_ENABLE_SIZE | \ - SEQ_CHANGE_ENABLE_BITDEPTH | \ - SEQ_CHANGE_ENABLE_DPB_COUNT) - #define SEQ_CHANGE_ENABLE_ALL_AVC (SEQ_CHANGE_ENABLE_SIZE | \ SEQ_CHANGE_ENABLE_BITDEPTH | \ - SEQ_CHANGE_ENABLE_DPB_COUNT) - -#define SEQ_CHANGE_ENABLE_ALL_AV1 (SEQ_CHANGE_ENABLE_PROFILE | \ - SEQ_CHANGE_CHROMA_FORMAT_IDC | \ - SEQ_CHANGE_ENABLE_SIZE | \ - SEQ_CHANGE_ENABLE_BITDEPTH | \ - SEQ_CHANGE_ENABLE_DPB_COUNT) + SEQ_CHANGE_ENABLE_DPB_COUNT | \ + SEQ_CHANGE_ENABLE_ASPECT_RATIO | \ + SEQ_CHANGE_ENABLE_VIDEO_SIGNAL | \ + SEQ_CHANGE_ENABLE_VUI_TIMING_INFO) #define DISPLAY_IDX_FLAG_SEQ_END -1 #define DISPLAY_IDX_FLAG_NO_FB -3 @@ -256,31 +206,12 @@ enum codec_command { ENABLE_MIRRORING, SET_MIRROR_DIRECTION, SET_ROTATION_ANGLE, - ENABLE_DEC_THUMBNAIL_MODE, DEC_GET_QUEUE_STATUS, ENC_GET_QUEUE_STATUS, DEC_RESET_FRAMEBUF_INFO, DEC_GET_SEQ_INFO, }; -enum error_conceal_mode { - ERROR_CONCEAL_MODE_OFF = 0, /* conceal off */ - ERROR_CONCEAL_MODE_INTRA_ONLY = 1, /* intra conceal in intra-picture, inter-picture */ - ERROR_CONCEAL_MODE_INTRA_INTER = 2 -}; - -enum error_conceal_unit { - ERROR_CONCEAL_UNIT_PICTURE = 0, /* picture-level error conceal */ - ERROR_CONCEAL_UNIT_SLICE_TILE = 1, /* slice/tile-level error conceal */ - ERROR_CONCEAL_UNIT_BLOCK_ROW = 2, /* block-row-level error conceal */ - ERROR_CONCEAL_UNIT_BLOCK = 3 /* block-level conceal */ -}; - -enum cb_cr_order { - CBCR_ORDER_NORMAL, - CBCR_ORDER_REVERSED -}; - enum mirror_direction { MIRDIR_NONE, /* no mirroring */ MIRDIR_VER, /* vertical mirroring */ @@ -364,34 +295,13 @@ enum wave5_interrupt_bit { }; enum pic_type { - PIC_TYPE_I = 0, /* I picture */ - PIC_TYPE_KEY = 0, /* KEY frame for AV1*/ - PIC_TYPE_P = 1, /* P picture */ - PIC_TYPE_INTER = 1, /* inter frame for AV1*/ - PIC_TYPE_B = 2, /* B picture (except VC1) */ - PIC_TYPE_REPEAT = 2, /* repeat frame (VP9 only) */ - PIC_TYPE_AV1_INTRA = 2, /* intra only frame (AV1 only) */ - PIC_TYPE_VC1_BI = 2, /* VC1 BI picture (VC1 only) */ - PIC_TYPE_VC1_B = 3, /* VC1 B picture (VC1 only) */ - PIC_TYPE_D = 3, - PIC_TYPE_S = 3, - PIC_TYPE_AVS2_F = 3, /* F picture in AVS2 */ - PIC_TYPE_AV1_SWITCH = 3, /* switch frame (AV1 only) */ - PIC_TYPE_VC1_P_SKIP = 4, /* VC1 P skip picture (VC1 only) */ - PIC_TYPE_MP4_P_SKIP_NOT_CODED = 4, /* not coded P picture in MPEG4 packed mode */ - PIC_TYPE_AVS2_S = 4, /* S picture in AVS2 */ - PIC_TYPE_IDR = 5, /* H.264/H.265 IDR picture */ - PIC_TYPE_AVS2_G = 5, /* G picture in AVS2 */ - PIC_TYPE_AVS2_GB = 6, /* GB picture in AVS2 */ + PIC_TYPE_I = 0, + PIC_TYPE_P = 1, + PIC_TYPE_B = 2, + PIC_TYPE_IDR = 5, /* H.264/H.265 IDR (Instantaneous Decoder Refresh) picture */ PIC_TYPE_MAX /* no meaning */ }; -enum bit_stream_mode { - BS_MODE_INTERRUPT, - BS_MODE_RESERVED, /* reserved for the future */ - BS_MODE_PIC_END, -}; - enum sw_reset_mode { SW_RESET_SAFETY, SW_RESET_FORCE, @@ -409,19 +319,16 @@ enum temporal_id_mode { }; struct vpu_attr { - u32 product_id; /* the product ID */ - char product_name[8]; /* the product name in ascii code */ - u32 product_version; /* the product version number */ - u32 fw_version; /* the F/W version */ - u32 customer_id; /* customer ID number */ - u32 support_decoders; /* bitmask: see <<vpuapi_h_cod_std>> */ - u32 support_encoders; /* bitmask: see <<vpuapi_h_cod_std>> */ - u32 support_endian_mask; /* A variable of supported endian mode in product */ - u32 support_bitstream_mode; + u32 product_id; + char product_name[8]; /* product name in ascii code */ + u32 product_version; + u32 fw_version; + u32 customer_id; + u32 support_decoders; /* bitmask */ + u32 support_encoders; /* bitmask */ u32 support_backbone: 1; u32 support_avc10bit_enc: 1; u32 support_hevc10bit_enc: 1; - u32 support_dual_core: 1; /* this indicates whether a product has two vcores */ u32 support_vcore_backbone: 1; u32 support_vcpu_backbone: 1; }; @@ -433,12 +340,11 @@ struct frame_buffer { unsigned int buf_y_size; unsigned int buf_cb_size; unsigned int buf_cr_size; - unsigned int endian; enum tiled_map_type map_type; - unsigned int stride; /* A horizontal stride for given frame buffer */ - unsigned int width; /* A width for given frame buffer */ - unsigned int height; /* A height for given frame buffer */ - size_t size; /* A size for given frame buffer */ + unsigned int stride; /* horizontal stride for the given frame buffer */ + unsigned int width; /* width of the given frame buffer */ + unsigned int height; /* height of the given frame buffer */ + size_t size; /* size of the given frame buffer */ unsigned int sequence_no; bool update_fb_info; }; @@ -457,17 +363,6 @@ struct vpu_rect { struct dec_open_param { dma_addr_t bitstream_buffer; size_t bitstream_buffer_size; - enum cb_cr_order cbcr_order; - unsigned int frame_endian; - unsigned int stream_endian; - enum bit_stream_mode bitstream_mode; - u32 av1_format; - enum error_conceal_unit error_conceal_unit; - enum error_conceal_mode error_conceal_mode; - u32 pri_ext_addr; - u32 pri_axprot; - u32 pri_axcache; - u32 enable_non_ref_fbc_write: 1; }; struct dec_initial_info { @@ -478,73 +373,43 @@ struct dec_initial_info { u64 ns_per_frame; struct vpu_rect pic_crop_rect; u32 min_frame_buffer_count; /* between 1 to 16 */ - u32 frame_buf_delay; - u32 max_temporal_layers; /* it indicates the max number of temporal sub-layers */ u32 profile; - u32 level; - u32 tier; - bool is_ext_sar; - u32 aspect_rate_info; - u32 bit_rate; - u32 user_data_header; - u32 user_data_size; - bool user_data_buf_full; - u32 chroma_format_idc;/* A chroma format indicator */ - u32 luma_bitdepth; /* A bit-depth of luma sample */ - u32 chroma_bitdepth; /* A bit-depth of chroma sample */ + u32 luma_bitdepth; /* bit-depth of the luma sample */ + u32 chroma_bitdepth; /* bit-depth of the chroma sample */ u32 seq_init_err_reason; - u32 warn_info; - dma_addr_t rd_ptr; /* A read pointer of bitstream buffer */ - dma_addr_t wr_ptr; /* A write pointer of bitstream buffer */ + dma_addr_t rd_ptr; /* read pointer of bitstream buffer */ + dma_addr_t wr_ptr; /* write pointer of bitstream buffer */ u32 sequence_no; - u32 output_bit_depth; - u32 vlc_buf_size; /* the size of vlc buffer */ - u32 param_buf_size; /* the size of param buffer */ -}; - -#define WAVE_SKIPMODE_WAVE_NONE 0 -#define WAVE_SKIPMODE_NON_IRAP 1 -#define WAVE_SKIPMODE_NON_REF 2 - -struct dec_param { - u32 skipframe_mode: 2; - u32 cra_as_bla_flag: 1; - u32 disable_film_grain: 1; -}; - -struct avs2_info { - s32 decoded_poi; - int display_poi; + u32 vlc_buf_size; + u32 param_buf_size; }; struct dec_output_info { /** - * this is a frame buffer index for the picture to be displayed at the moment among - * frame buffers which are registered using vpu_dec_register_frame_buffer(). frame - * data to be displayed are stored into the frame buffer with this index - * when there is no display delay, this index is always - * the same with index_frame_decoded, however, if display delay does exist for display - * reordering in AVC - * or B-frames in VC1), this index might be different with index_frame_decoded. - * by checking this index, HOST application can easily know whether sequence decoding - * has been finished or not. + * This is a frame buffer index for the picture to be displayed at the moment + * among frame buffers which are registered using vpu_dec_register_frame_buffer(). + * Frame data that will be displayed is stored in the frame buffer with this index + * When there is no display delay, this index is always the equal to + * index_frame_decoded, however, if displaying is delayed (for display + * reordering in AVC or B-frames in VC1), this index might be different to + * index_frame_decoded. By checking this index, HOST applications can easily figure + * out whether sequence decoding has been finished or not. * - * -3(0xFFFD) or -2(0xFFFE) : it is when a display output cannot be given due to picture + * -3(0xFFFD) or -2(0xFFFE) : when a display output cannot be given due to picture * reordering or skip option - * -1(0xFFFF) : it is when there is no more output for display at the end of sequence + * -1(0xFFFF) : when there is no more output for display at the end of sequence * decoding */ s32 index_frame_display; /** - * this is a frame buffer index of decoded picture among frame buffers which were - * registered using vpu_dec_register_frame_buffer(). the currently decoded frame is stored - * into the frame buffer specified by - * this index. + * This is the frame buffer index of the decoded picture among the frame buffers which were + * registered using vpu_dec_register_frame_buffer(). The currently decoded frame is stored + * into the frame buffer specified by this index. * - * -2 : it indicates that no decoded output is generated because decoder meets EOS + * -2 : indicates that no decoded output is generated because decoder meets EOS * (end of sequence) or skip - * -1 : it indicates that decoder fails to decode a picture because there is no available + * -1 : indicates that the decoder fails to decode a picture because there is no available * frame buffer */ s32 index_frame_decoded; @@ -557,11 +422,10 @@ struct dec_output_info { struct vpu_rect rc_decoded; u32 dec_pic_width; u32 dec_pic_height; - struct avs2_info avs2_info; s32 decoded_poc; - int temporal_id; /* A temporal ID of the picture */ - dma_addr_t rd_ptr; /* A stream buffer read pointer for the current decoder instance */ - dma_addr_t wr_ptr; /* A stream buffer write pointer for the current decoder instance */ + int temporal_id; /* temporal ID of the picture */ + dma_addr_t rd_ptr; /* stream buffer read pointer for the current decoder instance */ + dma_addr_t wr_ptr; /* stream buffer write pointer for the current decoder instance */ struct frame_buffer disp_frame; u32 frame_display_flag; /* it reports a frame buffer flag to be displayed */ /** @@ -599,64 +463,47 @@ struct queue_status_info { #define MAX_GOP_NUM 8 struct custom_gop_pic_param { - u32 pic_type; /* A picture type of nth picture in the custom GOP */ - u32 poc_offset; /* A POC of nth picture in the custom GOP */ - u32 pic_qp; /* A quantization parameter of nth picture in the custom GOP */ + u32 pic_type; /* picture type of nth picture in the custom GOP */ + u32 poc_offset; /* POC of nth picture in the custom GOP */ + u32 pic_qp; /* quantization parameter of nth picture in the custom GOP */ u32 use_multi_ref_p; /* use multiref pic for P picture. valid only if PIC_TYPE is P */ - u32 ref_poc_l0; /* A POC of reference L0 of nth picture in the custom GOP */ - u32 ref_poc_l1; /* A POC of reference L1 of nth picture in the custom GOP */ - s32 temporal_id; /* A temporal ID of nth picture in the custom GOP */ -}; - -struct custom_gop_param { - u32 custom_gop_size; /* the size of custom GOP (0~8) */ - struct custom_gop_pic_param pic_param[MAX_GOP_NUM]; -}; - -struct wave_custom_map_opt { - u32 roi_avg_qp; /* it sets an average QP of ROI map */ - u32 addr_custom_map; - u32 custom_roi_map_enable: 1; /* it enables ROI map */ - u32 custom_lambda_map_enable: 1; /* it enables custom lambda map */ - u32 custom_mode_map_enable: 1; - u32 custom_coef_drop_enable: 1; + u32 ref_poc_l0; /* POC of reference L0 of nth picture in the custom GOP */ + u32 ref_poc_l1; /* POC of reference L1 of nth picture in the custom GOP */ + s32 temporal_id; /* temporal ID of nth picture in the custom GOP */ }; struct enc_wave_param { /* - * A profile indicator (HEVC only) + * profile indicator (HEVC only) * - * 0 : the firmware determines a profile according to internalbitdepth + * 0 : the firmware determines a profile according to the internal_bit_depth * 1 : main profile * 2 : main10 profile * 3 : main still picture profile - * in AVC encoder, a profile cannot be set by host application. the firmware decides it - * based on internalbitdepth. it is HIGH profile for bitdepth of 8 and HIGH10 profile for - * bitdepth of 10. + * In the AVC encoder, a profile cannot be set by the host application. + * The firmware decides it based on internal_bit_depth. + * profile = HIGH (bitdepth 8) profile = HIGH10 (bitdepth 10) */ u32 profile; - u32 level; /* A level indicator (level * 10) */ + u32 level; /* level indicator (level * 10) */ u32 internal_bit_depth: 4; /* 8/10 */ u32 gop_preset_idx: 4; /* 0 - 9 */ u32 decoding_refresh_type: 2; /* 0=non-IRAP, 1=CRA, 2=IDR */ - u32 intra_qp; /* A quantization parameter of intra picture */ - u32 intra_period; /* A period of intra picture in GOP size */ - u32 forced_idr_header_enable: 2; - u32 conf_win_top; /* A top offset of conformance window */ - u32 conf_win_bot; /* A bottom offset of conformance window */ - u32 conf_win_left; /* A left offset of conformance window */ - u32 conf_win_right; /* A right offset of conformance window */ - u32 independ_slice_mode_arg; - u32 depend_slice_mode_arg; + u32 intra_qp; /* quantization parameter of intra picture */ + u32 intra_period; /* period of intra picture in GOP size */ + u32 conf_win_top; /* top offset of conformance window */ + u32 conf_win_bot; /* bottom offset of conformance window */ + u32 conf_win_left; /* left offset of conformance window */ + u32 conf_win_right; /* right offset of conformance window */ u32 intra_refresh_mode: 3; /* - * it specifies an intra CTU refresh interval. depending on intra_refresh_mode, - * it can mean one of the following. + * Argument for intra_ctu_refresh_mode. * - * the number of consecutive CTU rows for intra_ctu_refresh_mode of 1 - * the number of consecutive CTU columns for intra_ctu_refresh_mode of 2 - * A step size in CTU for intra_ctu_refresh_mode of 3 - * the number of intra ct_us to be encoded in a picture for intra_ctu_refresh_mode of 4 + * Depending on intra_refresh_mode, it can mean one of the following: + * - intra_ctu_refresh_mode (1) -> number of consecutive CTU rows + * - intra_ctu_refresh_mode (2) -> the number of consecutive CTU columns + * - intra_ctu_refresh_mode (3) -> step size in CTU + * - intra_ctu_refresh_mode (4) -> number of intra ct_us to be encoded in a picture */ u32 intra_refresh_arg; /* @@ -666,90 +513,38 @@ struct enc_wave_param { * 3 : fast mode (fast encoding speed, low picture quality) */ u32 depend_slice_mode : 2; - u32 use_recommend_enc_param: 2; + u32 depend_slice_mode_arg; + u32 independ_slice_mode : 1; /* 0=no-multi-slice, 1=slice-in-ctu-number*/ + u32 independ_slice_mode_arg; u32 max_num_merge: 2; - u32 scaling_list_enable: 2; - u32 bit_alloc_mode: 2; /* 0=ref-pic-priority, 1=uniform, 2=fixed_bit_ratio */ - s32 beta_offset_div2: 4; /* it sets beta_offset_div2 for deblocking filter */ - s32 tc_offset_div2: 4; /* it sets tc_offset_div3 for deblocking filter */ + s32 beta_offset_div2: 4; /* sets beta_offset_div2 for deblocking filter */ + s32 tc_offset_div2: 4; /* sets tc_offset_div3 for deblocking filter */ u32 hvs_qp_scale: 4; /* QP scaling factor for CU QP adjust if hvs_qp_scale_enable is 1 */ - u32 hvs_max_delta_qp; /* A maximum delta QP for HVS */ - /* - * A fixed bit ratio (1 ~ 255) for each picture of GOP's bit - * allocation - * - * N = 0 ~ (MAX_GOP_SIZE - 1) - * MAX_GOP_SIZE = 8 - * - * for instance when MAX_GOP_SIZE is 3, fixed_bit_ratio0, fixed_bit_ratio1, and - * fixed_bit_ratio2 can be set as 2, 1, and 1 respectively for - * the fixed bit ratio 2:1:1. this is only valid when bit_alloc_mode is 2. - */ - u8 fixed_bit_ratio[MAX_GOP_NUM]; - struct custom_gop_param gop_param; /* <<vpuapi_h_custom_gop_param>> */ - u32 num_units_in_tick; - u32 time_scale; - u32 num_ticks_poc_diff_one; + u32 hvs_max_delta_qp; /* maximum delta QP for HVS */ s32 chroma_cb_qp_offset; /* the value of chroma(cb) QP offset */ s32 chroma_cr_qp_offset; /* the value of chroma(cr) QP offset */ s32 initial_rc_qp; u32 nr_intra_weight_y; - u32 nr_intra_weight_cb; /* A weight to cb noise level for intra picture (0 ~ 31) */ - u32 nr_intra_weight_cr; /* A weight to cr noise level for intra picture (0 ~ 31) */ + u32 nr_intra_weight_cb; /* weight to cb noise level for intra picture (0 ~ 31) */ + u32 nr_intra_weight_cr; /* weight to cr noise level for intra picture (0 ~ 31) */ u32 nr_inter_weight_y; - u32 nr_inter_weight_cb; /* A weight to cb noise level for inter picture (0 ~ 31) */ - u32 nr_inter_weight_cr; /* A weight to cr noise level for inter picture (0 ~ 31) */ - u32 nr_noise_sigma_y; /* Y noise standard deviation if nr_noise_est_enable is 0 */ - u32 nr_noise_sigma_cb;/* cb noise standard deviation if nr_noise_est_enable is 0 */ - u32 nr_noise_sigma_cr;/* cr noise standard deviation if nr_noise_est_enable is 0 */ - u32 bg_thr_diff; - u32 bg_thr_mean_diff; - u32 bg_lambda_qp; - u32 bg_delta_qp; - u32 pu04_delta_rate: 8; /* added to the total cost of 4x4 blocks */ - u32 pu08_delta_rate: 8; /* added to the total cost of 8x8 blocks */ - u32 pu16_delta_rate: 8; /* added to the total cost of 16x16 blocks */ - u32 pu32_delta_rate: 8; /* added to the total cost of 32x32 blocks */ - u32 pu04_intra_planar_delta_rate: 8; - u32 pu04_intra_dc_delta_rate: 8; - u32 pu04_intra_angle_delta_rate: 8; - u32 pu08_intra_planar_delta_rate: 8; - u32 pu08_intra_dc_delta_rate: 8; - u32 pu08_intra_angle_delta_rate: 8; - u32 pu16_intra_planar_delta_rate: 8; - u32 pu16_intra_dc_delta_rate: 8; - u32 pu16_intra_angle_delta_rate: 8; - u32 pu32_intra_planar_delta_rate: 8; - u32 pu32_intra_dc_delta_rate: 8; - u32 pu32_intra_angle_delta_rate: 8; - u32 cu08_intra_delta_rate: 8; - u32 cu08_inter_delta_rate: 8; - u32 cu08_merge_delta_rate: 8; - u32 cu16_intra_delta_rate: 8; - u32 cu16_inter_delta_rate: 8; - u32 cu16_merge_delta_rate: 8; - u32 cu32_intra_delta_rate: 8; - u32 cu32_inter_delta_rate: 8; - u32 cu32_merge_delta_rate: 8; - u32 coef_clear_disable: 8; - u32 min_qp_i; /* A minimum QP of I picture for rate control */ - u32 max_qp_i; /* A maximum QP of I picture for rate control */ - u32 min_qp_p; /* A minimum QP of P picture for rate control */ - u32 max_qp_p; /* A maximum QP of P picture for rate control */ - u32 min_qp_b; /* A minimum QP of B picture for rate control */ - u32 max_qp_b; /* A maximum QP of B picture for rate control */ - u32 custom_lambda_addr; /* it specifies the address of custom lambda map */ - u32 user_scaling_list_addr; /* it specifies the address of user scaling list file */ - u32 avc_idr_period;/* A period of IDR picture (0 ~ 1024). 0 - implies an infinite period */ - u32 avc_slice_arg; /* the number of MB for a slice when avc_slice_mode is set with 1 */ + u32 nr_inter_weight_cb; /* weight to cb noise level for inter picture (0 ~ 31) */ + u32 nr_inter_weight_cr; /* weight to cr noise level for inter picture (0 ~ 31) */ + u32 min_qp_i; /* minimum QP of I picture for rate control */ + u32 max_qp_i; /* maximum QP of I picture for rate control */ + u32 min_qp_p; /* minimum QP of P picture for rate control */ + u32 max_qp_p; /* maximum QP of P picture for rate control */ + u32 min_qp_b; /* minimum QP of B picture for rate control */ + u32 max_qp_b; /* maximum QP of B picture for rate control */ + u32 avc_idr_period; /* period of IDR picture (0 ~ 1024). 0 - implies an infinite period */ + u32 avc_slice_arg; /* the number of MB for a slice when avc_slice_mode is set with 1 */ u32 intra_mb_refresh_mode: 2; /* 0=none, 1=row, 2=column, 3=step-size-in-mb */ /** - * it specifies an intra MB refresh interval. depending on intra_mb_refresh_mode, - * it can mean one of the following. + * Argument for intra_mb_refresh_mode. * - * the number of consecutive MB rows for intra_mb_refresh_mode of 1 - * the number of consecutive MB columns for intra_mb_refresh_mode of 2 - * A step size in MB for intra_mb_refresh_mode of 3 + * intra_mb_refresh_mode (1) -> number of consecutive MB rows + * intra_mb_refresh_mode (2) ->the number of consecutive MB columns + * intra_mb_refresh_mode (3) -> step size in MB */ u32 intra_mb_refresh_arg; u32 rc_weight_param; @@ -758,150 +553,99 @@ struct enc_wave_param { /* flags */ u32 en_still_picture: 1; /* still picture profile */ u32 tier: 1; /* 0=main, 1=high */ - u32 independ_slice_mode : 1; /* 0=no-multi-slice, 1=slice-in-ctu-number*/ u32 avc_slice_mode: 1; /* 0=none, 1=slice-in-mb-number */ u32 entropy_coding_mode: 1; /* 0=CAVLC, 1=CABAC */ - u32 lossless_enable: 1; /* enables lossless coding */ - u32 const_intra_pred_flag: 1; /* enables constrained intra prediction */ - u32 tmvp_enable: 1; /* enables temporal motion vector prediction */ + u32 lossless_enable: 1; /* enable lossless encoding */ + u32 const_intra_pred_flag: 1; /* enable constrained intra prediction */ + u32 tmvp_enable: 1; /* enable temporal motion vector prediction */ u32 wpp_enable: 1; - u32 disable_deblk: 1; /* it disables in-loop deblocking filtering */ + u32 disable_deblk: 1; /* disable in-loop deblocking filtering */ u32 lf_cross_slice_boundary_enable: 1; u32 skip_intra_trans: 1; - u32 sao_enable: 1; /* it enables SAO (sample adaptive offset) */ - u32 intra_nx_n_enable: 1; /* it enables intra nx_n p_us */ - u32 cu_level_rc_enable: 1; /* it enable CU level rate control */ + u32 sao_enable: 1; /* enable SAO (sample adaptive offset) */ + u32 intra_nx_n_enable: 1; /* enables intra nx_n p_us */ + u32 cu_level_rc_enable: 1; /* enable CU level rate control */ u32 hvs_qp_enable: 1; /* enable CU QP adjustment for subjective quality enhancement */ - u32 roi_enable: 1; /* it enables ROI map. NOTE: it is valid when rate control is on */ - u32 nr_y_enable: 1; /* it enables noise reduction algorithm to Y component */ - u32 nr_noise_est_enable: 1; - u32 nr_cb_enable: 1; /* it enables noise reduction algorithm to cb component */ - u32 nr_cr_enable: 1; /* it enables noise reduction algorithm to cr component */ - u32 use_long_term: 1; /* it enables long-term reference function */ - u32 monochrome_enable: 1; /* it enables monochrom encoding mode */ - u32 strong_intra_smooth_enable: 1; /* it enables strong intra smoothing */ - u32 weight_pred_enable: 1; /* it enables to use weighted prediction*/ - u32 bg_detect_enable: 1; /* it enables background detection */ - u32 custom_lambda_enable: 1; /* it enables custom lambda table */ - u32 custom_md_enable: 1; /* it enables custom mode decision */ - u32 rdo_skip: 1; /* it skips RDO(rate distortion optimization) */ - u32 lambda_scaling_enable: 1; /* it enables lambda scaling using custom GOP */ - u32 transform8x8_enable: 1; /* it enables 8x8 intra prediction and 8x8 transform */ - u32 mb_level_rc_enable: 1; /* it enables MB-level rate control */ - u32 s2fme_disable: 1; /* it disables s2me_fme (only for AVC encoder) */ -}; - -struct enc_sub_frame_sync_config { - u32 sub_frame_sync_mode; /* 0=wire-based, 1=register-based */ - u32 sub_frame_sync_on; + u32 strong_intra_smooth_enable: 1; /* enable strong intra smoothing */ + u32 rdo_skip: 1; /* skip RDO (rate distortion optimization) */ + u32 lambda_scaling_enable: 1; /* enable lambda scaling using custom GOP */ + u32 transform8x8_enable: 1; /* enable 8x8 intra prediction and 8x8 transform */ + u32 mb_level_rc_enable: 1; /* enable MB-level rate control */ }; struct enc_open_param { dma_addr_t bitstream_buffer; unsigned int bitstream_buffer_size; - u32 pic_width; /* the width of a picture to be encoded in unit of sample */ - u32 pic_height; /* the height of a picture to be encoded in unit of sample */ + u32 pic_width; /* width of a picture to be encoded in unit of sample */ + u32 pic_height; /* height of a picture to be encoded in unit of sample */ u32 frame_rate_info;/* desired fps */ u32 vbv_buffer_size; u32 bit_rate; /* target bitrate in bps */ struct enc_wave_param wave_param; - enum cb_cr_order cbcr_order; - unsigned int stream_endian; - unsigned int source_endian; enum packed_format_num packed_format; /* <<vpuapi_h_packed_format_num>> */ enum frame_buffer_format src_format; - /* enum frame_buffer_format output_format; not used yet */ - u32 enc_hrd_rbsp_in_vps; /* it encodes the HRD syntax rbsp into VPS */ - u32 hrd_rbsp_data_size; /* the bit size of the HRD rbsp data */ - u32 hrd_rbsp_data_addr; /* the address of the HRD rbsp data */ - u32 encode_vui_rbsp; - u32 vui_rbsp_data_size; /* the bit size of the VUI rbsp data */ - u32 vui_rbsp_data_addr; /* the address of the VUI rbsp data */ - u32 pri_ext_addr; - u32 pri_axprot; - u32 pri_axcache; - bool ring_buffer_enable; bool line_buf_int_en; - bool enable_pts; /* an enable flag to report PTS(presentation timestamp) */ u32 rc_enable : 1; /* rate control */ - u32 enable_non_ref_fbc_write: 1; - u32 sub_frame_sync_enable: 1; - u32 sub_frame_sync_mode: 1; }; struct enc_initial_info { - u32 min_frame_buffer_count; /* minimum number of frame buffer */ - u32 min_src_frame_count; /* minimum number of source buffer */ - u32 max_latency_pictures; /* maximum number of picture latency */ - u32 seq_init_err_reason; /* error information */ - u32 warn_info; /* warn information */ - u32 vlc_buf_size; /* the size of task buffer */ - u32 param_buf_size; /* the size of task buffer */ + u32 min_frame_buffer_count; /* minimum number of frame buffers */ + u32 min_src_frame_count; /* minimum number of source buffers */ + u32 seq_init_err_reason; + u32 warn_info; + u32 vlc_buf_size; /* size of task buffer */ + u32 param_buf_size; /* size of task buffer */ }; +/* + * Flags to encode NAL units explicitly + */ struct enc_code_opt { u32 implicit_header_encode: 1; - u32 encode_vcl: 1; /* A flag to encode VCL nal unit explicitly */ - u32 encode_vps: 1; /* A flag to encode VPS nal unit explicitly */ - u32 encode_sps: 1; /* A flag to encode SPS nal unit explicitly */ - u32 encode_pps: 1; /* A flag to encode PPS nal unit explicitly */ - u32 encode_aud: 1; /* A flag to encode AUD nal unit explicitly */ + u32 encode_vcl: 1; + u32 encode_vps: 1; + u32 encode_sps: 1; + u32 encode_pps: 1; + u32 encode_aud: 1; u32 encode_eos: 1; u32 encode_eob: 1; - u32 encode_vui: 1; /* A flag to encode VUI nal unit explicitly */ + u32 encode_vui: 1; }; struct enc_param { struct frame_buffer *source_frame; u32 pic_stream_buffer_addr; u64 pic_stream_buffer_size; - u32 force_pic_qp_i; - u32 force_pic_qp_p; - u32 force_pic_qp_b; - u32 force_pic_type: 2; - u32 src_idx; /* A source frame buffer index */ + u32 src_idx; /* source frame buffer index */ struct enc_code_opt code_option; - u32 use_cur_src_as_longterm_pic; - u32 use_longterm_ref; - u64 pts; /* the presentation timestamp (PTS) of input source */ - struct wave_custom_map_opt custom_map_opt; - u32 wp_pix_sigma_y; /* pixel variance of Y component for weighted prediction */ - u32 wp_pix_sigma_cb; /* pixel variance of cb component for weighted prediction */ - u32 wp_pix_sigma_cr; /* pixel variance of cr component for weighted prediction */ - u32 wp_pix_mean_y; /* pixel mean value of Y component for weighted prediction */ - u32 wp_pix_mean_cb; /* pixel mean value of cb component for weighted prediction */ - u32 wp_pix_mean_cr; /* pixel mean value of cr component for weighted prediction */ + u64 pts; /* presentation timestamp (PTS) of the input source */ bool src_end_flag; - u32 skip_picture: 1; - u32 force_pic_qp_enable: 1; /* flag used to force picture quantization parameter */ - u32 force_pic_type_enable: 1; /* A flag to use a force picture type */ - u32 force_all_ctu_coef_drop_enable: 1; /* forces all coefficients to be zero after TQ */ }; struct enc_output_info { u32 bitstream_buffer; - u32 bitstream_size; /* the byte size of encoded bitstream */ + u32 bitstream_size; /* byte size of encoded bitstream */ u32 pic_type: 2; /* <<vpuapi_h_pic_type>> */ s32 recon_frame_index; dma_addr_t rd_ptr; dma_addr_t wr_ptr; - u32 enc_pic_byte; /* the number of encoded picture bytes */ - s32 enc_src_idx; /* the source buffer index of the currently encoded picture */ + u32 enc_pic_byte; /* number of encoded picture bytes */ + s32 enc_src_idx; /* source buffer index of the currently encoded picture */ u32 enc_vcl_nut; - u32 error_reason; /* the error reason of the currently encoded picture */ - u32 warn_info; /* the warning information of the currently encoded picture */ + u32 error_reason; /* error reason of the currently encoded picture */ + u32 warn_info; /* warning information on the currently encoded picture */ unsigned int frame_cycle; /* param for reporting the cycle number of encoding one frame*/ u64 pts; u32 enc_host_cmd_tick; /* tick of ENC_PIC command for the picture */ u32 enc_encode_end_tick; /* end tick of encoding slices of the picture */ }; -enum ENC_PIC_CODE_OPTION { +enum enc_pic_code_option { CODEOPT_ENC_HEADER_IMPLICIT = BIT(0), - CODEOPT_ENC_VCL = BIT(1), /* A flag to encode VCL nal unit explicitly */ + CODEOPT_ENC_VCL = BIT(1), /* flag to encode VCL nal unit explicitly */ }; -enum GOP_PRESET_IDX { +enum gop_preset_idx { PRESET_IDX_CUSTOM_GOP = 0, /* user defined GOP structure */ PRESET_IDX_ALL_I = 1, /* all intra, gopsize = 1 */ PRESET_IDX_IPP = 2, /* consecutive P, cyclic gopsize = 1 */ @@ -915,15 +659,11 @@ enum GOP_PRESET_IDX { }; struct sec_axi_info { - struct { - u32 use_ip_enable; - u32 use_bit_enable; - u32 use_lf_row_enable: 1; - u32 use_enc_rdo_enable: 1; - u32 use_enc_lf_enable: 1; - } wave; - unsigned int buf_size; - dma_addr_t buf_base; + u32 use_ip_enable; + u32 use_bit_enable; + u32 use_lf_row_enable: 1; + u32 use_enc_rdo_enable: 1; + u32 use_enc_lf_enable: 1; }; struct dec_info { @@ -939,13 +679,9 @@ struct dec_info { struct vpu_buf vb_mv[MAX_REG_FRAME]; struct vpu_buf vb_fbc_y_tbl[MAX_REG_FRAME]; struct vpu_buf vb_fbc_c_tbl[MAX_REG_FRAME]; - unsigned int num_of_decoding_fbs; - unsigned int num_of_display_fbs; + unsigned int num_of_decoding_fbs: 7; + unsigned int num_of_display_fbs: 7; unsigned int stride; - enum mirror_direction mirror_direction; - unsigned int rotation_angle; - struct frame_buffer rotator_output; - unsigned int rotator_stride; struct sec_axi_info sec_axi_info; dma_addr_t user_data_buf_addr; u32 user_data_enable; @@ -963,12 +699,8 @@ struct dec_info { u32 product_code; u32 vlc_buf_size; u32 param_buf_size; - bool rotation_enable; - bool mirror_enable; - bool dering_enable; bool initial_info_obtained; bool reorder_enable; - bool thumbnail_mode; bool first_cycle_check; u32 stream_endflag: 1; }; @@ -988,9 +720,7 @@ struct enc_info { enum mirror_direction mirror_direction; unsigned int rotation_angle; bool initial_info_obtained; - bool ring_buffer_enable; struct sec_axi_info sec_axi_info; - struct enc_sub_frame_sync_config sub_frame_sync_config; bool line_buf_int_en; struct vpu_buf vb_work; struct vpu_buf vb_mv; /* col_mv buffer */ @@ -1012,17 +742,21 @@ struct enc_info { struct vpu_device { struct device *dev; struct v4l2_device v4l2_dev; + struct v4l2_m2m_dev *v4l2_m2m_dec_dev; + struct v4l2_m2m_dev *v4l2_m2m_enc_dev; struct list_head instances; struct video_device *video_dev_dec; struct video_device *video_dev_enc; - struct mutex dev_lock; /* the lock for the src,dst v4l2 queues */ + struct mutex dev_lock; /* lock for the src, dst v4l2 queues */ struct mutex hw_lock; /* lock hw configurations */ int irq; - enum product_id product; - struct vpu_attr attr; + enum product_id product; + struct vpu_attr attr; struct vpu_buf common_mem; u32 last_performance_cycles; - struct dma_vpu_buf sram_buf; + u32 sram_size; + struct gen_pool *sram_pool; + struct vpu_buf sram_buf; void __iomem *vdb_register; u32 product_code; u32 l2_cache_size; @@ -1035,8 +769,6 @@ struct vpu_device { struct vpu_instance; struct vpu_instance_ops { - void (*start_process)(struct vpu_instance *inst); - void (*stop_process)(struct vpu_instance *inst); void (*finish_process)(struct vpu_instance *inst); }; @@ -1052,10 +784,9 @@ struct timestamp_circ_buf { struct vpu_instance { struct list_head list; struct v4l2_fh v4l2_fh; + struct v4l2_m2m_dev *v4l2_m2m_dev; struct v4l2_ctrl_handler v4l2_ctrl_hdl; struct vpu_device *dev; - struct v4l2_m2m_dev *v4l2_m2m_dev; - struct kfifo irq_status; struct completion irq_done; struct v4l2_pix_format_mplane src_fmt; @@ -1064,41 +795,41 @@ struct vpu_instance { enum v4l2_xfer_func xfer_func; enum v4l2_ycbcr_encoding ycbcr_enc; enum v4l2_quantization quantization; - enum v4l2_hsv_encoding hsv_enc; enum vpu_instance_state state; enum vpu_instance_type type; const struct vpu_instance_ops *ops; - struct vpu_rect crop_rect; + spinlock_t state_spinlock; /* This protects the instance state */ - enum wave_std std; - s32 id; + enum wave_std std; + s32 id; union { struct enc_info enc_info; struct dec_info dec_info; } *codec_info; struct frame_buffer frame_buf[MAX_REG_FRAME]; struct vpu_buf frame_vbuf[MAX_REG_FRAME]; - u32 min_dst_buf_count; - u32 dst_buf_count; + u32 fbc_buf_count; u32 queued_src_buf_num; u32 queued_dst_buf_num; - u32 conf_win_width; - u32 conf_win_height; + struct list_head avail_src_bufs; + struct list_head avail_dst_bufs; + struct v4l2_rect conf_win; u64 timestamp; struct timestamp_circ_buf time_stamp; u64 timestamp_cnt; u32 timestamp_zero_cnt; bool monotonic_timestamp; + enum frame_buffer_format output_format; bool cbcr_interleave; bool nv21; bool eos; - struct vpu_buf bitstream_vbuf; - bool thumbnail_mode; + dma_addr_t last_rd_ptr; + size_t remaining_consumed_bytes; + bool needs_reallocation; unsigned int min_src_buf_count; - unsigned int src_buf_count; unsigned int rot_angle; unsigned int mirror_direction; unsigned int bit_depth; @@ -1107,32 +838,36 @@ struct vpu_instance { unsigned int rc_mode; unsigned int rc_enable; unsigned int bit_rate; + unsigned int encode_aud; struct enc_wave_param enc_param; }; void wave5_vdi_write_register(struct vpu_device *vpu_dev, u32 addr, u32 data); -u32 wave5_vdi_readl(struct vpu_device *vpu_dev, u32 addr); +u32 wave5_vdi_read_register(struct vpu_device *vpu_dev, u32 addr); int wave5_vdi_clear_memory(struct vpu_device *vpu_dev, struct vpu_buf *vb); int wave5_vdi_allocate_dma_memory(struct vpu_device *vpu_dev, struct vpu_buf *vb); +int wave5_vdi_allocate_array(struct vpu_device *vpu_dev, struct vpu_buf *array, unsigned int count, + size_t size); int wave5_vdi_write_memory(struct vpu_device *vpu_dev, struct vpu_buf *vb, size_t offset, - u8 *data, size_t len, unsigned int endian); -unsigned int wave5_vdi_convert_endian(struct vpu_device *vpu_dev, unsigned int endian); -void wave5_vdi_free_dma_memory(struct vpu_device *vpu_dev, struct vpu_buf *vb); + u8 *data, size_t len); +int wave5_vdi_free_dma_memory(struct vpu_device *vpu_dev, struct vpu_buf *vb); +void wave5_vdi_allocate_sram(struct vpu_device *vpu_dev); +void wave5_vdi_free_sram(struct vpu_device *vpu_dev); int wave5_vpu_init_with_bitcode(struct device *dev, u8 *bitcode, size_t size); -void wave5_vpu_clear_interrupt_ex(struct vpu_instance *inst, u32 intr_flag); +int wave5_vpu_flush_instance(struct vpu_instance *inst); int wave5_vpu_get_version_info(struct device *dev, u32 *revision, unsigned int *product_id); int wave5_vpu_dec_open(struct vpu_instance *inst, struct dec_open_param *open_param); int wave5_vpu_dec_close(struct vpu_instance *inst, u32 *fail_res); int wave5_vpu_dec_issue_seq_init(struct vpu_instance *inst); int wave5_vpu_dec_complete_seq_init(struct vpu_instance *inst, struct dec_initial_info *info); int wave5_vpu_dec_register_frame_buffer_ex(struct vpu_instance *inst, int num_of_decoding_fbs, - int num_of_display_fbs, int stride, int height, - int map_type); -int wave5_vpu_dec_start_one_frame(struct vpu_instance *inst, struct dec_param *param, - u32 *res_fail); + int num_of_display_fbs, int stride, int height); +int wave5_vpu_dec_start_one_frame(struct vpu_instance *inst, u32 *res_fail); int wave5_vpu_dec_get_output_info(struct vpu_instance *inst, struct dec_output_info *info); int wave5_vpu_dec_set_rd_ptr(struct vpu_instance *inst, dma_addr_t addr, int update_wr_ptr); +dma_addr_t wave5_vpu_dec_get_rd_ptr(struct vpu_instance *inst); +int wave5_vpu_dec_reset_framebuffer(struct vpu_instance *inst, unsigned int index); int wave5_vpu_dec_give_command(struct vpu_instance *inst, enum codec_command cmd, void *parameter); int wave5_vpu_dec_get_bitstream_buffer(struct vpu_instance *inst, dma_addr_t *prd_ptr, dma_addr_t *pwr_ptr, size_t *size); diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpuconfig.h b/drivers/media/platform/chips-media/wave5/wave5-vpuconfig.h index 4527eaf88848..d9751eedb0f9 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-vpuconfig.h +++ b/drivers/media/platform/chips-media/wave5/wave5-vpuconfig.h @@ -2,7 +2,7 @@ /* * Wave5 series multi-standard codec IP - product config definitions * - * Copyright (C) 2021 CHIPS&MEDIA INC + * Copyright (C) 2021-2023 CHIPS&MEDIA INC */ #ifndef _VPU_CONFIG_H_ @@ -39,12 +39,6 @@ #define VPU_ENC_TIMEOUT 60000 #define VPU_DEC_TIMEOUT 60000 -#define HOST_ENDIAN VDI_128BIT_LITTLE_ENDIAN -#define VPU_FRAME_ENDIAN HOST_ENDIAN -#define VPU_STREAM_ENDIAN HOST_ENDIAN -#define VPU_USER_DATA_ENDIAN HOST_ENDIAN -#define VPU_SOURCE_ENDIAN HOST_ENDIAN - // for WAVE encoder #define USE_SRC_PRP_AXI 0 #define USE_SRC_PRI_AXI 1 @@ -53,9 +47,9 @@ /************************************************************************/ /* VPU COMMON MEMORY */ /************************************************************************/ -#define VLC_BUF_NUM (3) +#define VLC_BUF_NUM (2) -#define COMMAND_QUEUE_DEPTH (4) +#define COMMAND_QUEUE_DEPTH (2) #define W5_REMAP_INDEX0 0 #define W5_REMAP_INDEX1 1 @@ -80,11 +74,4 @@ #define WAVE5_SEC_AXI_ID 0x0 #define WAVE5_PRI_AXI_ID 0x0 -#define WAVE5_PROC_AXI_AXPROT 0x0 -#define WAVE5_PROC_AXI_AXCACHE 0x0 -#define WAVE5_PROC_AXI_EXT_ADDR 0x0 -#define WAVE5_SEC_AXI_AXPROT 0x0 -#define WAVE5_SEC_AXI_AXCACHE 0x0 -#define WAVE5_SEC_AXI_EXT_ADDR 0x0 - #endif /* _VPU_CONFIG_H_ */ diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpuerror.h b/drivers/media/platform/chips-media/wave5/wave5-vpuerror.h index 6d8c7bb0e8b2..905d5c34fd4e 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-vpuerror.h +++ b/drivers/media/platform/chips-media/wave5/wave5-vpuerror.h @@ -2,7 +2,7 @@ /* * Wave5 series multi-standard codec IP - error values * - * Copyright (C) 2021 CHIPS&MEDIA INC + * Copyright (C) 2021-2023 CHIPS&MEDIA INC */ #ifndef ERROR_CODE_H_INCLUDED @@ -210,126 +210,6 @@ #define AVC_ETCERR_FMO 0x00005005 #define AVC_ETCERR_INPLACE_V 0x0000500F -// AV1 -#define AV1_SPSERR_MAX_FRAME_WIDTH 0x00001001 -#define AV1_SPSERR_MAX_FRAME_HEIGHT 0x00001002 -#define AV1_SPSERR_ID_LEN_EXCEED_16 0x00001004 -#define AV1_SPSERR_NOT_FOUND_FIRST_SPS 0x0000100A -#define AV1_SPSERR_SEQ_PROFILE 0x0000100B -#define AV1_SPSERR_STILL_PICTURE 0x0000100C -#define AV1_PPSERR_FRAME_SIZE_WIDTH 0x00002001 -#define AV1_PPSERR_FRAME_SIZE_HEIGHT 0x00002002 -#define AV1_PPSERR_SEEN_FRAME_HEADER 0x00002003 -#define AV1_PPSERR_REF_VALID 0x00002007 -#define AV1_PPSERR_LAST_ORDER_HINT 0x0000200B -#define AV1_PPSERR_GOLD_ORDER_HINT 0x0000200C -#define AV1_PPSERR_CODED_LOSSLESS_DELTA_Q 0x0000200E -#define AV1_PPSERR_FILM_GRAIN_PARAM_REF_IDX 0x0000200F -#define AV1_PPSERR_SEQ_CHANGE_BIT_DEPTH 0x00002010 -#define AV1_PPSERR_SEQ_CHANGE_PROFILE 0x00002012 -#define AV1_PPSERR_SEQ_CHANGE_DETECTED_INTER 0x00002013 -#define AV1_PPSERR_NUM_Y_POINTS 0x00002014 -#define AV1_PPSERR_POINT_Y_VALUE 0x00002015 -#define AV1_PPSERR_NUM_CB_POINTS 0x00002016 -#define AV1_PPSERR_POINT_CB_VALUE 0x00002017 -#define AV1_PPSERR_NUM_CR_POINTS 0x00002018 -#define AV1_PPSERR_POINT_CR_VALUE 0x00002019 -#define AV1_PPSERR_SUBSAMPLING_FORMAT 0x0000201A -#define AV1_FRAMEERR_TILE_START_END_PRESENT 0x00003001 -#define AV1_FRAMEERR_SHOW_EXISING_FRAME 0x00003002 -#define AV1_TGERR_NUM_TILES_ZERO 0x00004001 -#define AV1_TGERR_START_NOT_TILE_NUM 0x00004002 -#define AV1_TGERR_END_LESS_THAN_TG_START 0x00004003 -#define AV1_TGERR_TILE_SIZE_GREATER_THAN_32M 0x00004004 -#define AV1_SPECERR_OVER_MAX_H_SIZE 0x00005001 -#define AV1_SPECERR_OVER_MAX_V_SIZE 0x00005002 -#define AV1_SPECERR_OVER_MAX_TILE_COLS 0x00005004 -#define AV1_SPECERR_OVER_MAX_TILE_ROWS 0x00005005 -#define AV1_SPECERR_OVER_TILE_SIZE 0x00005006 -#define AV1_SPECERR_OVER_NUMTILES_GT_MAX_TILES 0x00005007 -#define AV1_ETCERR_OBU_HEADER 0x00006001 -#define AV1_ETCERR_OBU_SIZE 0x00006003 -#define AV1_ETCERR_OVERCONSUME 0x00006004 -#define AV1_ETCERR_NOT_SUPPORTED_FEATURE 0x00006005 -#define AV1_ETCERR_RESILIENCE_FAIL 0x00006006 - -// VP9 -#define VP9_PICERR_FRAME_MARKER 0x00001000 -#define VP9_PICERR_PROFILE 0x00001001 -#define VP9_PICERR_SYNC_CODE 0x00001002 -#define VP9_PICERR_PROFILE_COLOR_SAMPLE 0x00001003 -#define VP9_PICERR_FRAME_SIZE 0x00001004 -#define VP9_PICERR_SEGMENT 0x00001005 -#define VP9_PICERR_TILE 0x00001006 -#define VP9_PICERR_PROFILE_COMP_MISMATCH_WITH_REF 0x00001007 -#define VP9_PICERR_COMP_DAT_OVER_CS 0x00001008 -#define VP9_PICERR_COMP_TRAILING_BIT_ERR 0x00001009 -#define VP9_PICERR_MARKER 0x0000100A -#define VP9_PICERR_NOT_EXIST_REF_FRAME 0x0000100B -#define VP9_PICERR_UNINIT_CTX 0x0000100C -#define VP9_PICERR_FRAME_SIZE_LIMIT_BY_REF 0x0000100D -#define VP9_SPECERR_OVER_PICTURE_WIDTH_SIZE 0x00004000 -#define VP9_SPECERR_OVER_PICTURE_HEIGHT_SIZE 0x00004001 -#define VP9_SPECERR_OVER_CHROMA_FORMAT 0x00004002 -#define VP9_SPECERR_OVER_BIT_DEPTH 0x00004003 -#define VP9_ETCERR_INIT_KEY_FRAME_NOT_FOUND 0x00005000 -#define VP9_ETCERR_FORBIDDEN_BS_MODE 0x00005004 -#define VP9_ETCERR_SPP_OVER_CS_AU 0x00005005 - -// AVS2 -#define AVS2_SPSERR_PROFILE_ID 0x00001000 -#define AVS2_SPSERR_LEVEL_ID 0x00001001 -#define AVS2_SPSERR_HORIZONTAL_SIZE 0x00001002 -#define AVS2_SPSERR_VERTICAL_SIZE 0x00001003 -#define AVS2_SPSERR_CHROMA_FORMAT 0x00001004 -#define AVS2_SPSERR_SAMPLE_PRECISION 0x00001005 -#define AVS2_SPSERR_ENCODING_PRECISION 0x00001006 -#define AVS2_SPSERR_LCU_SIZE 0x00001007 -#define AVS2_SPSERR_WEIGHT_QUANT_MATRIX 0x00001008 -#define AVS2_SPSERR_NUM_OF_RCS 0x00001009 -#define AVS2_SPSERR_REFERENCE_CONFIGURATION_SET 0x0000100A -#define AVS2_SPSERR_OUTPUT_REORDER_DELAY 0x0000100B -#define AVS2_PPSERR_BBV_DELAY 0x00002000 -#define AVS2_PPSERR_TIME_CODE 0x00002001 -#define AVS2_PPSERR_DECODE_ORDER_INDEX 0x00002002 -#define AVS2_PPSERR_TEMPORAL_ID 0x00002003 -#define AVS2_PPSERR_PICTURE_OUTPUT_DELAY 0x00002004 -#define AVS2_PPSERR_RCS_INDEX 0x00002005 -#define AVS2_PPSERR_REFERENCE_CONFIGURATION_SET 0x00002006 -#define AVS2_PPSERR_BBV_CHECK_TIMES 0x00002007 -#define AVS2_PPSERR_PICTURE_QP 0x00002008 -#define AVS2_PPSERR_ALPHA_C_OFFSET 0x00002009 -#define AVS2_PPSERR_BETA_OFFSET 0x0000200A -#define AVS2_PPSERR_CHROMA_QUANT_PARAM_DELTA_CB 0x0000200B -#define AVS2_PPSERR_CHROMA_QUANT_PARAM_DELTA_CR 0x0000200C -#define AVS2_PPSERR_WEIGHT_QUANT_PARAM_DELTA1 0x0000200D -#define AVS2_PPSERR_WEIGHT_QUANT_PARAM_DELTA2 0x0000200E -#define AVS2_PPSERR_PICTURE_CODING_TYPE 0x0000200F -#define AVS2_PPSERR_ALF_FILTER_NUM_MINUS1 0x00002010 -#define AVS2_PPSERR_ALF_REGION_DISTANCE 0x00002011 -#define AVS2_PPSERR_ALF_COEFF_LUMA 0x00002012 -#define AVS2_PPSERR_ALF_COEFF_CHROMA_CB 0x00002013 -#define AVS2_PPSERR_ALF_COEFF_CHROMA_CR 0x00002014 -#define AVS2_SHERR_SLICE_VERTICAL_POSITION 0x00003000 -#define AVS2_SHERR_SLICE_VERTICAL_POSITION_EXTENSION 0x00003001 -#define AVS2_SHERR_SLICE_HORIZONTAL_POSITION 0x00003002 -#define AVS2_SHERR_SLICE_HORIZONTAL_POSITION_EXTENSION 0x00003003 -#define AVS2_SHERR_FIXED_SLICE_QP 0x00003004 -#define AVS2_SHERR_SLICE_QP 0x00003005 -#define AVS2_SHERR_SLICE_SAO_ENABLE_FLAG 0x00003006 -#define AVS2_SHERR_AEC_BYTE_ALIGNMENT_BIT 0x00003007 -#define AVS2_SHERR_STREAM_END 0x00003008 -#define AVS2_SPECERR_OVER_PICTURE_WIDTH_SIZE 0x00004000 -#define AVS2_SPECERR_OVER_PICTURE_HEIGHT_SIZE 0x00004001 -#define AVS2_SPECERR_OVER_CHROMA_FORMAT 0x00004002 -#define AVS2_SPECERR_OVER_BIT_DEPTH 0x00004003 -#define AVS2_SPECERR_OVER_REF_TEMPORAL_ID 0x00004004 -#define AVS2_ETCERR_SPS_NOT_FOUND 0x00005000 -#define AVS2_ETCERR_DEC_PIC_VCL_NOT_FOUND 0x00005001 -#define AVS2_ETCERR_NO_VALID_SLICE_IN_AU 0x00005002 -#define AVS2_ETCERR_PPS_ERROR 0x00005003 -#define AVS2_ETCERR_SLICE_NUM_OVERFLOW 0x00005004 - /************************************************************************/ /* WAVE5 WARNING ON DECODER (WARN_INFO) */ /************************************************************************/ @@ -392,48 +272,6 @@ #define AVC_PRESWARN_OVERCONSUME 0x01100000 #define AVC_PRESWARN_MISSING_SLICE 0x01200000 -// AV1 -#define AV1_SPSWARN_OBU_EXTENSION_FLAG_ZERO 0x00001000 -#define AV1_SPSWARN_DUPLICATE_OPERATING_POINT_IDX 0x00001001 -#define AV1_SPSWARN_MC_IDENTIY_SUBSAMPLING_X 0x00001002 -#define AV1_PPSWARN_MC_IDENTIY_SUBSAMPLING_Y 0x00001003 -#define AV1_SPSWARN_NUM_UNITS_IN_DISPLAY_TICK 0x00001004 -#define AV1_SPSWARN_TIME_SCALE_ZERO 0x00001005 -#define AV1_SPSWARN_NUM_TICKS_PER_PICTURE 0x00001006 -#define AV1_PPSWARN_TILE_WIDTH 0x00002001 -#define AV1_PPSWARN_TILE_HEIGHT 0x00002002 -#define AV1_PPSWARN_SHOW_EXISTING_KEY_FRAME_OUTPUT 0x00002004 -#define AV1_PPSWARN_DIFF_FRAME_ID 0x00002008 -#define AV1_PPSWARN_CURRENT_FRAME_ID 0x00002010 -#define AV1_PPSWARN_REFRESH_FRAME_FLAGS 0x00002020 -#define AV1_PPSWARN_DISPLAY_ID 0x00002040 -#define AV1_PPSWARN_PREV_FRAME_SHOWABLE_FLAG_ZERO 0x00002080 -#define AV1_PPSWARN_EXPECTED_FRAME_ID 0x00002100 -#define AV1_SPECWARN_OVER_MAX_TILE_AREA_SB 0x00005000 -#define AV1_SPECWARN_OVER_MAX_PIC_SIZE 0x00005001 -#define AV1_ETCWARN_OBU_EXTENSION_FLAG 0x00006000 -#define AV1_TGWARN_TRAIL_BIT_POS 0x00400000 -#define AV1_TGWARN_TRAIL_PAD_BIT 0x00800000 -#define AV1_TGWARN_SYM_MAX_OVER 0x01000000 -#define AV1_TGWARN_EXP_GOLB_OVER 0x02000000 -#define AV1_TGWARN_MV_NOT_VALID 0x04000000 - -// VP9 -#define VP9_PICWARN_COLOR_SPACE_MISMATCH_WITH_REF 0x00001000 -#define VP9_PRESWARN_OVERCONSUME 0x00400000 -#define VP9_PRESWARN_TRAILING_BITS 0x00800000 -#define VP9_PRESWARN_MARKER 0x01000000 -#define VP9_PRESWARN_MV_RANGE_OVER 0x02000000 -#define VP9_PRESWARN_MISIZE_SEG_LVL_ACTIVE 0x04000000 - -// AVS2 -#define AVS2_ETCWARN_INIT_SEQ_VCL_NOT_FOUND 0x00010000 -#define AVS2_ETCWARN_MISSING_REFERENCE_PICTURE 0x00020000 -#define AVS2_ETCWARN_WRONG_TEMPORAL_ID 0x00040000 -#define AVS2_ETCWARN_ERROR_PICTURE_IS_REFERENCED 0x00080000 -#define AVS2_ETCWARN_REF_WRONG_TEMPORAL_ID 0x00080001 -#define AVS2_ETCWARN_SPS_ERROR 0x00080002 - /************************************************************************/ /* WAVE5 ERROR ON ENCODER (ERR_INFO) */ /************************************************************************/ diff --git a/drivers/media/platform/chips-media/wave5/wave5.h b/drivers/media/platform/chips-media/wave5/wave5.h index d3afb541e356..063028eccd3b 100644 --- a/drivers/media/platform/chips-media/wave5/wave5.h +++ b/drivers/media/platform/chips-media/wave5/wave5.h @@ -2,7 +2,7 @@ /* * Wave5 series multi-standard codec IP - wave5 backend definitions * - * Copyright (C) 2021 CHIPS&MEDIA INC + * Copyright (C) 2021-2023 CHIPS&MEDIA INC */ #ifndef __WAVE5_FUNCTION_H__ @@ -11,7 +11,27 @@ #define WAVE5_SUBSAMPLED_ONE_SIZE(_w, _h) (ALIGN((_w) / 4, 16) * ALIGN((_h) / 4, 8)) #define WAVE5_SUBSAMPLED_ONE_SIZE_AVC(_w, _h) (ALIGN((_w) / 4, 32) * ALIGN((_h) / 4, 4)) -#define BSOPTION_ENABLE_EXPLICIT_END BIT(0) +/* + * Bitstream buffer option: Explicit End + * When set to 1 the VPU assumes that the bitstream has at least one frame and + * will read until the end of the bitstream buffer. + * When set to 0 the VPU will not read the last few bytes. + * This option can be set anytime but cannot be cleared during processing. + * It can be set to force finish decoding even though there is not enough + * bitstream data for a full frame. + */ +#define BSOPTION_ENABLE_EXPLICIT_END BIT(0) +#define BSOPTION_HIGHLIGHT_STREAM_END BIT(1) + +/* + * Currently the driver only supports hardware with little endian but for source + * picture format, the bitstream and the report parameter the hardware works + * with the opposite endianness, thus hard-code big endian for the register + * writes + */ +#define PIC_SRC_ENDIANNESS_BIG_ENDIAN 0xf +#define BITSTREAM_ENDIANNESS_BIG_ENDIAN 0xf +#define REPORT_PARAM_ENDIANNESS_BIG_ENDIAN 0xf #define WTL_RIGHT_JUSTIFIED 0 #define WTL_LEFT_JUSTIFIED 1 @@ -32,8 +52,6 @@ bool wave5_vpu_is_init(struct vpu_device *vpu_dev); unsigned int wave5_vpu_get_product_id(struct vpu_device *vpu_dev); -void wave5_bit_issue_command(struct vpu_instance *inst, u32 cmd); - int wave5_vpu_get_version(struct vpu_device *vpu_dev, u32 *revision); int wave5_vpu_init(struct device *dev, u8 *fw, size_t size); @@ -44,6 +62,8 @@ int wave5_vpu_build_up_dec_param(struct vpu_instance *inst, struct dec_open_para int wave5_vpu_dec_set_bitstream_flag(struct vpu_instance *inst, bool eos); +int wave5_vpu_hw_flush_instance(struct vpu_instance *inst); + int wave5_vpu_dec_register_framebuffer(struct vpu_instance *inst, struct frame_buffer *fb_arr, enum tiled_map_type map_type, unsigned int count); @@ -54,7 +74,7 @@ int wave5_vpu_dec_init_seq(struct vpu_instance *inst); int wave5_vpu_dec_get_seq_info(struct vpu_instance *inst, struct dec_initial_info *info); -int wave5_vpu_decode(struct vpu_instance *inst, struct dec_param *option, u32 *fail_res); +int wave5_vpu_decode(struct vpu_instance *inst, u32 *fail_res); int wave5_vpu_dec_get_result(struct vpu_instance *inst, struct dec_output_info *result); @@ -66,7 +86,7 @@ int wave5_dec_set_disp_flag(struct vpu_instance *inst, unsigned int index); int wave5_vpu_clear_interrupt(struct vpu_instance *inst, u32 flags); -dma_addr_t wave5_vpu_dec_get_rd_ptr(struct vpu_instance *inst); +dma_addr_t wave5_dec_get_rd_ptr(struct vpu_instance *inst); int wave5_dec_set_rd_ptr(struct vpu_instance *inst, dma_addr_t addr); diff --git a/drivers/media/v4l2-core/v4l2-mem2mem.c b/drivers/media/v4l2-core/v4l2-mem2mem.c index e7f4bf5bc8dd..ee367e5151bc 100644 --- a/drivers/media/v4l2-core/v4l2-mem2mem.c +++ b/drivers/media/v4l2-core/v4l2-mem2mem.c @@ -301,9 +301,12 @@ static void __v4l2_m2m_try_queue(struct v4l2_m2m_dev *m2m_dev, dprintk("Trying to schedule a job for m2m_ctx: %p\n", m2m_ctx); - if (!m2m_ctx->out_q_ctx.q.streaming - || !m2m_ctx->cap_q_ctx.q.streaming) { - dprintk("Streaming needs to be on for both queues\n"); + if (!m2m_ctx->out_q_ctx.q.streaming || + (!m2m_ctx->cap_q_ctx.q.streaming && !m2m_ctx->ignore_cap_streaming)) { + if (!m2m_ctx->ignore_cap_streaming) + dprintk("Streaming needs to be on for both queues\n"); + else + dprintk("Streaming needs to be on for the OUTPUT queue\n"); return; } |