diff options
Diffstat (limited to 'drivers/iio')
33 files changed, 2078 insertions, 226 deletions
diff --git a/drivers/iio/Kconfig b/drivers/iio/Kconfig index 1d736a4952ab..5bd51853b15e 100644 --- a/drivers/iio/Kconfig +++ b/drivers/iio/Kconfig @@ -28,7 +28,7 @@ config IIO_CONFIGFS help This allows configuring various IIO bits through configfs (e.g. software triggers). For more info see - Documentation/iio/iio_configfs.txt. + Documentation/iio/iio_configfs.rst. config IIO_TRIGGER bool "Enable triggered sampling support" diff --git a/drivers/iio/accel/adis16201.c b/drivers/iio/accel/adis16201.c index 0af4b289fc63..c4810c73b2a2 100644 --- a/drivers/iio/accel/adis16201.c +++ b/drivers/iio/accel/adis16201.c @@ -70,7 +70,7 @@ #define ADIS16201_DIAG_STAT_FLASH_UPT_FAIL_BIT 2 /* Power supply above 3.625 V */ #define ADIS16201_DIAG_STAT_POWER_HIGH_BIT 1 -/* Power supply below 3.15 V */ +/* Power supply below 2.975 V */ #define ADIS16201_DIAG_STAT_POWER_LOW_BIT 0 /* System Command Register Definition */ @@ -230,7 +230,7 @@ static const char * const adis16201_status_error_msgs[] = { [ADIS16201_DIAG_STAT_SPI_FAIL_BIT] = "SPI failure", [ADIS16201_DIAG_STAT_FLASH_UPT_FAIL_BIT] = "Flash update failed", [ADIS16201_DIAG_STAT_POWER_HIGH_BIT] = "Power supply above 3.625V", - [ADIS16201_DIAG_STAT_POWER_LOW_BIT] = "Power supply below 3.15V", + [ADIS16201_DIAG_STAT_POWER_LOW_BIT] = "Power supply below 2.975V", }; static const struct adis_data adis16201_data = { diff --git a/drivers/iio/accel/adis16209.c b/drivers/iio/accel/adis16209.c index 40be7adfa1f2..98d77af8a2b0 100644 --- a/drivers/iio/accel/adis16209.c +++ b/drivers/iio/accel/adis16209.c @@ -72,7 +72,7 @@ #define ADIS16209_STAT_FLASH_UPT_FAIL_BIT 2 /* Power supply above 3.625 V */ #define ADIS16209_STAT_POWER_HIGH_BIT 1 -/* Power supply below 3.15 V */ +/* Power supply below 2.975 V */ #define ADIS16209_STAT_POWER_LOW_BIT 0 #define ADIS16209_CMD_REG 0x3E @@ -240,7 +240,7 @@ static const char * const adis16209_status_error_msgs[] = { [ADIS16209_STAT_SPI_FAIL_BIT] = "SPI failure", [ADIS16209_STAT_FLASH_UPT_FAIL_BIT] = "Flash update failed", [ADIS16209_STAT_POWER_HIGH_BIT] = "Power supply above 3.625V", - [ADIS16209_STAT_POWER_LOW_BIT] = "Power supply below 3.15V", + [ADIS16209_STAT_POWER_LOW_BIT] = "Power supply below 2.975V", }; static const struct adis_data adis16209_data = { diff --git a/drivers/iio/accel/adxl372.c b/drivers/iio/accel/adxl372.c index 3b84cb243a87..055227cb3d43 100644 --- a/drivers/iio/accel/adxl372.c +++ b/drivers/iio/accel/adxl372.c @@ -782,10 +782,14 @@ static int adxl372_buffer_postenable(struct iio_dev *indio_dev) unsigned int mask; int i, ret; - ret = adxl372_set_interrupts(st, ADXL372_INT1_MAP_FIFO_FULL_MSK, 0); + ret = iio_triggered_buffer_postenable(indio_dev); if (ret < 0) return ret; + ret = adxl372_set_interrupts(st, ADXL372_INT1_MAP_FIFO_FULL_MSK, 0); + if (ret < 0) + goto err; + mask = *indio_dev->active_scan_mask; for (i = 0; i < ARRAY_SIZE(adxl372_axis_lookup_table); i++) { @@ -793,8 +797,10 @@ static int adxl372_buffer_postenable(struct iio_dev *indio_dev) break; } - if (i == ARRAY_SIZE(adxl372_axis_lookup_table)) - return -EINVAL; + if (i == ARRAY_SIZE(adxl372_axis_lookup_table)) { + ret = -EINVAL; + goto err; + } st->fifo_format = adxl372_axis_lookup_table[i].fifo_format; st->fifo_set_size = bitmap_weight(indio_dev->active_scan_mask, @@ -814,26 +820,25 @@ static int adxl372_buffer_postenable(struct iio_dev *indio_dev) if (ret < 0) { st->fifo_mode = ADXL372_FIFO_BYPASSED; adxl372_set_interrupts(st, 0, 0); - return ret; + goto err; } - return iio_triggered_buffer_postenable(indio_dev); + return 0; + +err: + iio_triggered_buffer_predisable(indio_dev); + return ret; } static int adxl372_buffer_predisable(struct iio_dev *indio_dev) { struct adxl372_state *st = iio_priv(indio_dev); - int ret; - - ret = iio_triggered_buffer_predisable(indio_dev); - if (ret < 0) - return ret; adxl372_set_interrupts(st, 0, 0); st->fifo_mode = ADXL372_FIFO_BYPASSED; adxl372_configure_fifo(st); - return 0; + return iio_triggered_buffer_predisable(indio_dev); } static const struct iio_buffer_setup_ops adxl372_buffer_ops = { diff --git a/drivers/iio/accel/kxcjk-1013.c b/drivers/iio/accel/kxcjk-1013.c index e589f64eab9d..6645771aa349 100644 --- a/drivers/iio/accel/kxcjk-1013.c +++ b/drivers/iio/accel/kxcjk-1013.c @@ -1487,6 +1487,7 @@ static const struct acpi_device_id kx_acpi_match[] = { {"KIOX0009", KXTJ21009}, {"KIOX000A", KXCJ91008}, {"KIOX010A", KXCJ91008}, /* KXCJ91008 inside the display of a 2-in-1 */ + {"KIOX020A", KXCJ91008}, {"KXTJ1009", KXTJ21009}, {"KXJ2109", KXTJ21009}, {"SMO8500", KXCJ91008}, diff --git a/drivers/iio/accel/sca3000.c b/drivers/iio/accel/sca3000.c index 274ce2f8bddf..a923f90f6e80 100644 --- a/drivers/iio/accel/sca3000.c +++ b/drivers/iio/accel/sca3000.c @@ -869,8 +869,9 @@ static int sca3000_read_event_value(struct iio_dev *indio_dev, enum iio_event_info info, int *val, int *val2) { - int ret, i; struct sca3000_state *st = iio_priv(indio_dev); + long ret; + int i; switch (info) { case IIO_EV_INFO_VALUE: @@ -882,11 +883,11 @@ static int sca3000_read_event_value(struct iio_dev *indio_dev, return ret; *val = 0; if (chan->channel2 == IIO_MOD_Y) - for_each_set_bit(i, (unsigned long *)&ret, + for_each_set_bit(i, &ret, ARRAY_SIZE(st->info->mot_det_mult_y)) *val += st->info->mot_det_mult_y[i]; else - for_each_set_bit(i, (unsigned long *)&ret, + for_each_set_bit(i, &ret, ARRAY_SIZE(st->info->mot_det_mult_xz)) *val += st->info->mot_det_mult_xz[i]; diff --git a/drivers/iio/accel/st_accel_buffer.c b/drivers/iio/accel/st_accel_buffer.c index 54f2ae91f614..0205c0167cdd 100644 --- a/drivers/iio/accel/st_accel_buffer.c +++ b/drivers/iio/accel/st_accel_buffer.c @@ -45,17 +45,19 @@ static int st_accel_buffer_postenable(struct iio_dev *indio_dev) goto allocate_memory_error; } - err = st_sensors_set_axis_enable(indio_dev, - (u8)indio_dev->active_scan_mask[0]); + err = iio_triggered_buffer_postenable(indio_dev); if (err < 0) goto st_accel_buffer_postenable_error; - err = iio_triggered_buffer_postenable(indio_dev); + err = st_sensors_set_axis_enable(indio_dev, + (u8)indio_dev->active_scan_mask[0]); if (err < 0) - goto st_accel_buffer_postenable_error; + goto st_sensors_set_axis_enable_error; return err; +st_sensors_set_axis_enable_error: + iio_triggered_buffer_predisable(indio_dev); st_accel_buffer_postenable_error: kfree(adata->buffer_data); allocate_memory_error: @@ -64,20 +66,22 @@ allocate_memory_error: static int st_accel_buffer_predisable(struct iio_dev *indio_dev) { - int err; + int err, err2; struct st_sensor_data *adata = iio_priv(indio_dev); - err = iio_triggered_buffer_predisable(indio_dev); - if (err < 0) - goto st_accel_buffer_predisable_error; - err = st_sensors_set_axis_enable(indio_dev, ST_SENSORS_ENABLE_ALL_AXIS); if (err < 0) goto st_accel_buffer_predisable_error; err = st_sensors_set_enable(indio_dev, false); + if (err < 0) + goto st_accel_buffer_predisable_error; st_accel_buffer_predisable_error: + err2 = iio_triggered_buffer_predisable(indio_dev); + if (!err) + err = err2; + kfree(adata->buffer_data); return err; } diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index f96a7702b020..7e3286265a38 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -1085,7 +1085,6 @@ config VIPERBOARD_ADC config XILINX_XADC tristate "Xilinx XADC driver" - depends on ARCH_ZYNQ || MICROBLAZE || COMPILE_TEST depends on HAS_IOMEM select IIO_BUFFER select IIO_TRIGGERED_BUFFER diff --git a/drivers/iio/adc/ad7124.c b/drivers/iio/adc/ad7124.c index 659ef37d5fe8..edc6f1cc90b2 100644 --- a/drivers/iio/adc/ad7124.c +++ b/drivers/iio/adc/ad7124.c @@ -61,6 +61,8 @@ #define AD7124_CONFIG_REF_SEL(x) FIELD_PREP(AD7124_CONFIG_REF_SEL_MSK, x) #define AD7124_CONFIG_PGA_MSK GENMASK(2, 0) #define AD7124_CONFIG_PGA(x) FIELD_PREP(AD7124_CONFIG_PGA_MSK, x) +#define AD7124_CONFIG_IN_BUFF_MSK GENMASK(7, 6) +#define AD7124_CONFIG_IN_BUFF(x) FIELD_PREP(AD7124_CONFIG_IN_BUFF_MSK, x) /* AD7124_FILTER_X */ #define AD7124_FILTER_FS_MSK GENMASK(10, 0) @@ -108,6 +110,8 @@ struct ad7124_chip_info { struct ad7124_channel_config { enum ad7124_ref_sel refsel; bool bipolar; + bool buf_positive; + bool buf_negative; unsigned int ain; unsigned int vref_mv; unsigned int pga_bits; @@ -117,7 +121,7 @@ struct ad7124_channel_config { struct ad7124_state { const struct ad7124_chip_info *chip_info; struct ad_sigma_delta sd; - struct ad7124_channel_config channel_config[4]; + struct ad7124_channel_config *channel_config; struct regulator *vref[4]; struct clk *mclk; unsigned int adc_control; @@ -435,6 +439,7 @@ static int ad7124_of_parse_channel_config(struct iio_dev *indio_dev, struct ad7124_state *st = iio_priv(indio_dev); struct device_node *child; struct iio_chan_spec *chan; + struct ad7124_channel_config *chan_config; unsigned int ain[2], channel = 0, tmp; int ret; @@ -449,8 +454,14 @@ static int ad7124_of_parse_channel_config(struct iio_dev *indio_dev, if (!chan) return -ENOMEM; + chan_config = devm_kcalloc(indio_dev->dev.parent, st->num_channels, + sizeof(*chan_config), GFP_KERNEL); + if (!chan_config) + return -ENOMEM; + indio_dev->channels = chan; indio_dev->num_channels = st->num_channels; + st->channel_config = chan_config; for_each_available_child_of_node(np, child) { ret = of_property_read_u32(child, "reg", &channel); @@ -462,13 +473,6 @@ static int ad7124_of_parse_channel_config(struct iio_dev *indio_dev, if (ret) goto err; - if (ain[0] >= st->chip_info->num_inputs || - ain[1] >= st->chip_info->num_inputs) { - dev_err(indio_dev->dev.parent, - "Input pin number out of range.\n"); - ret = -EINVAL; - goto err; - } st->channel_config[channel].ain = AD7124_CHANNEL_AINP(ain[0]) | AD7124_CHANNEL_AINM(ain[1]); st->channel_config[channel].bipolar = @@ -480,6 +484,11 @@ static int ad7124_of_parse_channel_config(struct iio_dev *indio_dev, else st->channel_config[channel].refsel = tmp; + st->channel_config[channel].buf_positive = + of_property_read_bool(child, "adi,buffered-positive"); + st->channel_config[channel].buf_negative = + of_property_read_bool(child, "adi,buffered-negative"); + *chan = ad7124_channel_template; chan->address = channel; chan->scan_index = channel; @@ -499,7 +508,7 @@ err: static int ad7124_setup(struct ad7124_state *st) { unsigned int val, fclk, power_mode; - int i, ret; + int i, ret, tmp; fclk = clk_get_rate(st->mclk); if (!fclk) @@ -532,8 +541,12 @@ static int ad7124_setup(struct ad7124_state *st) if (ret < 0) return ret; + tmp = (st->channel_config[i].buf_positive << 1) + + st->channel_config[i].buf_negative; + val = AD7124_CONFIG_BIPOLAR(st->channel_config[i].bipolar) | - AD7124_CONFIG_REF_SEL(st->channel_config[i].refsel); + AD7124_CONFIG_REF_SEL(st->channel_config[i].refsel) | + AD7124_CONFIG_IN_BUFF(tmp); ret = ad_sd_write_reg(&st->sd, AD7124_CONFIG(i), 2, val); if (ret < 0) return ret; diff --git a/drivers/iio/adc/ad7606.c b/drivers/iio/adc/ad7606.c index 24c70c3cefb4..aba0fd123a51 100644 --- a/drivers/iio/adc/ad7606.c +++ b/drivers/iio/adc/ad7606.c @@ -140,7 +140,7 @@ static int ad7606_read_raw(struct iio_dev *indio_dev, int *val2, long m) { - int ret; + int ret, ch = 0; struct ad7606_state *st = iio_priv(indio_dev); switch (m) { @@ -157,8 +157,10 @@ static int ad7606_read_raw(struct iio_dev *indio_dev, *val = (short)ret; return IIO_VAL_INT; case IIO_CHAN_INFO_SCALE: + if (st->sw_mode_en) + ch = chan->address; *val = 0; - *val2 = st->scale_avail[st->range]; + *val2 = st->scale_avail[st->range[ch]]; return IIO_VAL_INT_PLUS_MICRO; case IIO_CHAN_INFO_OVERSAMPLING_RATIO: *val = st->oversampling; @@ -194,6 +196,32 @@ static ssize_t in_voltage_scale_available_show(struct device *dev, static IIO_DEVICE_ATTR_RO(in_voltage_scale_available, 0); +static int ad7606_write_scale_hw(struct iio_dev *indio_dev, int ch, int val) +{ + struct ad7606_state *st = iio_priv(indio_dev); + + gpiod_set_value(st->gpio_range, val); + + return 0; +} + +static int ad7606_write_os_hw(struct iio_dev *indio_dev, int val) +{ + struct ad7606_state *st = iio_priv(indio_dev); + DECLARE_BITMAP(values, 3); + + values[0] = val; + + gpiod_set_array_value(ARRAY_SIZE(values), st->gpio_os->desc, + st->gpio_os->info, values); + + /* AD7616 requires a reset to update value */ + if (st->chip_info->os_req_reset) + ad7606_reset(st); + + return 0; +} + static int ad7606_write_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int val, @@ -201,15 +229,20 @@ static int ad7606_write_raw(struct iio_dev *indio_dev, long mask) { struct ad7606_state *st = iio_priv(indio_dev); - DECLARE_BITMAP(values, 3); - int i; + int i, ret, ch = 0; switch (mask) { case IIO_CHAN_INFO_SCALE: mutex_lock(&st->lock); i = find_closest(val2, st->scale_avail, st->num_scales); - gpiod_set_value(st->gpio_range, i); - st->range = i; + if (st->sw_mode_en) + ch = chan->address; + ret = st->write_scale(indio_dev, ch, i); + if (ret < 0) { + mutex_unlock(&st->lock); + return ret; + } + st->range[ch] = i; mutex_unlock(&st->lock); return 0; @@ -218,17 +251,12 @@ static int ad7606_write_raw(struct iio_dev *indio_dev, return -EINVAL; i = find_closest(val, st->oversampling_avail, st->num_os_ratios); - - values[0] = i; - mutex_lock(&st->lock); - gpiod_set_array_value(ARRAY_SIZE(values), st->gpio_os->desc, - st->gpio_os->info, values); - - /* AD7616 requires a reset to update value */ - if (st->chip_info->os_req_reset) - ad7606_reset(st); - + ret = st->write_os(indio_dev, i); + if (ret < 0) { + mutex_unlock(&st->lock); + return ret; + } st->oversampling = st->oversampling_avail[i]; mutex_unlock(&st->lock); @@ -536,7 +564,7 @@ int ad7606_probe(struct device *dev, int irq, void __iomem *base_address, st->bops = bops; st->base_address = base_address; /* tied to logic low, analog input range is +/- 5V */ - st->range = 0; + st->range[0] = 0; st->oversampling = 1; st->scale_avail = ad7606_scale_avail; st->num_scales = ARRAY_SIZE(ad7606_scale_avail); @@ -589,6 +617,39 @@ int ad7606_probe(struct device *dev, int irq, void __iomem *base_address, if (ret) dev_warn(st->dev, "failed to RESET: no RESET GPIO specified\n"); + st->write_scale = ad7606_write_scale_hw; + st->write_os = ad7606_write_os_hw; + + if (st->chip_info->sw_mode_config) + st->sw_mode_en = device_property_present(st->dev, + "adi,sw-mode"); + + if (st->sw_mode_en) { + /* After reset, in software mode, ±10 V is set by default */ + memset32(st->range, 2, ARRAY_SIZE(st->range)); + indio_dev->info = &ad7606_info_os_and_range; + + /* + * In software mode, the range gpio has no longer its function. + * Instead, the scale can be configured individually for each + * channel from the range registers. + */ + if (st->chip_info->write_scale_sw) + st->write_scale = st->chip_info->write_scale_sw; + + /* + * In software mode, the oversampling is no longer configured + * with GPIO pins. Instead, the oversampling can be configured + * in configuratiion register. + */ + if (st->chip_info->write_os_sw) + st->write_os = st->chip_info->write_os_sw; + + ret = st->chip_info->sw_mode_config(indio_dev); + if (ret < 0) + return ret; + } + st->trig = devm_iio_trigger_alloc(dev, "%s-dev%d", indio_dev->name, indio_dev->id); if (!st->trig) @@ -643,7 +704,7 @@ static int ad7606_resume(struct device *dev) struct ad7606_state *st = iio_priv(indio_dev); if (st->gpio_standby) { - gpiod_set_value(st->gpio_range, st->range); + gpiod_set_value(st->gpio_range, st->range[0]); gpiod_set_value(st->gpio_standby, 1); ad7606_reset(st); } diff --git a/drivers/iio/adc/ad7606.h b/drivers/iio/adc/ad7606.h index f9ef52131e74..d8a509c2c428 100644 --- a/drivers/iio/adc/ad7606.h +++ b/drivers/iio/adc/ad7606.h @@ -16,6 +16,12 @@ * oversampling ratios. * @oversampling_num number of elements stored in oversampling_avail array * @os_req_reset some devices require a reset to update oversampling + * @write_scale_sw pointer to the function which writes the scale via spi + in software mode + * @write_os_sw pointer to the function which writes the os via spi + in software mode + * @sw_mode_config: pointer to a function which configured the device + * for software mode */ struct ad7606_chip_info { const struct iio_chan_spec *channels; @@ -23,6 +29,9 @@ struct ad7606_chip_info { const unsigned int *oversampling_avail; unsigned int oversampling_num; bool os_req_reset; + int (*write_scale_sw)(struct iio_dev *indio_dev, int ch, int val); + int (*write_os_sw)(struct iio_dev *indio_dev, int val); + int (*sw_mode_config)(struct iio_dev *indio_dev); }; /** @@ -34,11 +43,14 @@ struct ad7606_chip_info { * @range voltage range selection, selects which scale to apply * @oversampling oversampling selection * @base_address address from where to read data in parallel operation + * @sw_mode_en software mode enabled * @scale_avail pointer to the array which stores the available scales * @num_scales number of elements stored in the scale_avail array * @oversampling_avail pointer to the array which stores the available * oversampling ratios. * @num_os_ratios number of elements stored in oversampling_avail array + * @write_scale pointer to the function which writes the scale + * @write_os pointer to the function which writes the os * @lock protect sensor state from concurrent accesses to GPIOs * @gpio_convst GPIO descriptor for conversion start signal (CONVST) * @gpio_reset GPIO descriptor for device hard-reset @@ -57,13 +69,16 @@ struct ad7606_state { const struct ad7606_chip_info *chip_info; struct regulator *reg; const struct ad7606_bus_ops *bops; - unsigned int range; + unsigned int range[16]; unsigned int oversampling; void __iomem *base_address; + bool sw_mode_en; const unsigned int *scale_avail; unsigned int num_scales; const unsigned int *oversampling_avail; unsigned int num_os_ratios; + int (*write_scale)(struct iio_dev *indio_dev, int ch, int val); + int (*write_os)(struct iio_dev *indio_dev, int val); struct mutex lock; /* protect sensor state */ struct gpio_desc *gpio_convst; diff --git a/drivers/iio/adc/ad_sigma_delta.c b/drivers/iio/adc/ad_sigma_delta.c index 1423221c6e06..2640b75fb774 100644 --- a/drivers/iio/adc/ad_sigma_delta.c +++ b/drivers/iio/adc/ad_sigma_delta.c @@ -357,7 +357,7 @@ static int ad_sd_buffer_postenable(struct iio_dev *indio_dev) ret = ad_sigma_delta_set_channel(sigma_delta, indio_dev->channels[channel].address); if (ret) - goto err_predisable; + return ret; spi_bus_lock(sigma_delta->spi->master); sigma_delta->bus_locked = true; @@ -374,7 +374,6 @@ static int ad_sd_buffer_postenable(struct iio_dev *indio_dev) err_unlock: spi_bus_unlock(sigma_delta->spi->master); -err_predisable: return ret; } diff --git a/drivers/iio/adc/imx7d_adc.c b/drivers/iio/adc/imx7d_adc.c index 4fe97c2a0f43..26a7bbe4d534 100644 --- a/drivers/iio/adc/imx7d_adc.c +++ b/drivers/iio/adc/imx7d_adc.c @@ -78,6 +78,7 @@ #define IMX7D_REG_ADC_INT_STATUS_CHANNEL_CONV_TIME_OUT 0xf0000 #define IMX7D_ADC_TIMEOUT msecs_to_jiffies(100) +#define IMX7D_ADC_INPUT_CLK 24000000 enum imx7d_adc_clk_pre_div { IMX7D_ADC_ANALOG_CLK_PRE_DIV_4, @@ -100,8 +101,6 @@ struct imx7d_adc_feature { enum imx7d_adc_average_num avg_num; u32 core_time_unit; /* impact the sample rate */ - - bool average_en; }; struct imx7d_adc { @@ -179,7 +178,6 @@ static void imx7d_adc_feature_config(struct imx7d_adc *info) info->adc_feature.clk_pre_div = IMX7D_ADC_ANALOG_CLK_PRE_DIV_4; info->adc_feature.avg_num = IMX7D_ADC_AVERAGE_NUM_32; info->adc_feature.core_time_unit = 1; - info->adc_feature.average_en = true; } static void imx7d_adc_sample_rate_set(struct imx7d_adc *info) @@ -240,9 +238,8 @@ static void imx7d_adc_channel_set(struct imx7d_adc *info) /* the channel choose single conversion, and enable average mode */ cfg1 |= (IMX7D_REG_ADC_CH_CFG1_CHANNEL_EN | - IMX7D_REG_ADC_CH_CFG1_CHANNEL_SINGLE); - if (info->adc_feature.average_en) - cfg1 |= IMX7D_REG_ADC_CH_CFG1_CHANNEL_AVG_EN; + IMX7D_REG_ADC_CH_CFG1_CHANNEL_SINGLE | + IMX7D_REG_ADC_CH_CFG1_CHANNEL_AVG_EN); /* * physical channel 0 chose logical channel A @@ -272,13 +269,11 @@ static void imx7d_adc_channel_set(struct imx7d_adc *info) static u32 imx7d_adc_get_sample_rate(struct imx7d_adc *info) { - /* input clock is always 24MHz */ - u32 input_clk = 24000000; u32 analogue_core_clk; u32 core_time_unit = info->adc_feature.core_time_unit; u32 tmp; - analogue_core_clk = input_clk / info->pre_div_num; + analogue_core_clk = IMX7D_ADC_INPUT_CLK / info->pre_div_num; tmp = (core_time_unit + 1) * 6; return analogue_core_clk / tmp; @@ -493,11 +488,8 @@ static int imx7d_adc_probe(struct platform_device *pdev) info->dev = dev; info->regs = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(info->regs)) { - ret = PTR_ERR(info->regs); - dev_err(dev, "Failed to remap adc memory, err = %d\n", ret); - return ret; - } + if (IS_ERR(info->regs)) + return PTR_ERR(info->regs); irq = platform_get_irq(pdev, 0); if (irq < 0) { @@ -531,9 +523,7 @@ static int imx7d_adc_probe(struct platform_device *pdev) indio_dev->channels = imx7d_adc_iio_channels; indio_dev->num_channels = ARRAY_SIZE(imx7d_adc_iio_channels); - ret = devm_request_irq(dev, irq, - imx7d_adc_isr, 0, - dev_name(dev), info); + ret = devm_request_irq(dev, irq, imx7d_adc_isr, 0, dev_name(dev), info); if (ret < 0) { dev_err(dev, "Failed requesting irq, irq = %d\n", irq); return ret; diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c index 70bbcf253cb6..7b28d045d271 100644 --- a/drivers/iio/adc/meson_saradc.c +++ b/drivers/iio/adc/meson_saradc.c @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0-only +// SPDX-License-Identifier: GPL-2.0 /* * Amlogic Meson Successive Approximation Register (SAR) A/D Converter * diff --git a/drivers/iio/adc/stm32-adc-core.c b/drivers/iio/adc/stm32-adc-core.c index 2327ec18b40c..1f7ce5186dfc 100644 --- a/drivers/iio/adc/stm32-adc-core.c +++ b/drivers/iio/adc/stm32-adc-core.c @@ -87,6 +87,7 @@ struct stm32_adc_priv_cfg { * @domain: irq domain reference * @aclk: clock reference for the analog circuitry * @bclk: bus clock common for all ADCs, depends on part used + * @vdda: vdda analog supply reference * @vref: regulator reference * @cfg: compatible configuration data * @common: common data for all ADC instances @@ -97,6 +98,7 @@ struct stm32_adc_priv { struct irq_domain *domain; struct clk *aclk; struct clk *bclk; + struct regulator *vdda; struct regulator *vref; const struct stm32_adc_priv_cfg *cfg; struct stm32_adc_common common; @@ -394,10 +396,16 @@ static int stm32_adc_core_hw_start(struct device *dev) struct stm32_adc_priv *priv = to_stm32_adc_priv(common); int ret; + ret = regulator_enable(priv->vdda); + if (ret < 0) { + dev_err(dev, "vdda enable failed %d\n", ret); + return ret; + } + ret = regulator_enable(priv->vref); if (ret < 0) { dev_err(dev, "vref enable failed\n"); - return ret; + goto err_vdda_disable; } if (priv->bclk) { @@ -425,6 +433,8 @@ err_bclk_disable: clk_disable_unprepare(priv->bclk); err_regulator_disable: regulator_disable(priv->vref); +err_vdda_disable: + regulator_disable(priv->vdda); return ret; } @@ -441,6 +451,7 @@ static void stm32_adc_core_hw_stop(struct device *dev) if (priv->bclk) clk_disable_unprepare(priv->bclk); regulator_disable(priv->vref); + regulator_disable(priv->vdda); } static int stm32_adc_probe(struct platform_device *pdev) @@ -468,6 +479,14 @@ static int stm32_adc_probe(struct platform_device *pdev) return PTR_ERR(priv->common.base); priv->common.phys_base = res->start; + priv->vdda = devm_regulator_get(&pdev->dev, "vdda"); + if (IS_ERR(priv->vdda)) { + ret = PTR_ERR(priv->vdda); + if (ret != -EPROBE_DEFER) + dev_err(&pdev->dev, "vdda get failed, %d\n", ret); + return ret; + } + priv->vref = devm_regulator_get(&pdev->dev, "vref"); if (IS_ERR(priv->vref)) { ret = PTR_ERR(priv->vref); diff --git a/drivers/iio/adc/stm32-dfsdm-adc.c b/drivers/iio/adc/stm32-dfsdm-adc.c index 588907cc3b6b..ee1e0569d0e1 100644 --- a/drivers/iio/adc/stm32-dfsdm-adc.c +++ b/drivers/iio/adc/stm32-dfsdm-adc.c @@ -39,9 +39,16 @@ #define DFSDM_MAX_INT_OVERSAMPLING 256 #define DFSDM_MAX_FL_OVERSAMPLING 1024 -/* Max sample resolutions */ -#define DFSDM_MAX_RES BIT(31) -#define DFSDM_DATA_RES BIT(23) +/* Limit filter output resolution to 31 bits. (i.e. sample range is +/-2^30) */ +#define DFSDM_DATA_MAX BIT(30) +/* + * Data are output as two's complement data in a 24 bit field. + * Data from filters are in the range +/-2^(n-1) + * 2^(n-1) maximum positive value cannot be coded in 2's complement n bits + * An extra bit is required to avoid wrap-around of the binary code for 2^(n-1) + * So, the resolution of samples from filter is actually limited to 23 bits + */ +#define DFSDM_DATA_RES 24 /* Filter configuration */ #define DFSDM_CR1_CFG_MASK (DFSDM_CR1_RCH_MASK | DFSDM_CR1_RCONT_MASK | \ @@ -181,14 +188,15 @@ static int stm32_dfsdm_get_jextsel(struct iio_dev *indio_dev, return -EINVAL; } -static int stm32_dfsdm_set_osrs(struct stm32_dfsdm_filter *fl, - unsigned int fast, unsigned int oversamp) +static int stm32_dfsdm_compute_osrs(struct stm32_dfsdm_filter *fl, + unsigned int fast, unsigned int oversamp) { unsigned int i, d, fosr, iosr; - u64 res; - s64 delta; + u64 res, max; + int bits, shift; unsigned int m = 1; /* multiplication factor */ unsigned int p = fl->ford; /* filter order (ford) */ + struct stm32_dfsdm_filter_osr *flo = &fl->flo[fast]; pr_debug("%s: Requested oversampling: %d\n", __func__, oversamp); /* @@ -207,11 +215,8 @@ static int stm32_dfsdm_set_osrs(struct stm32_dfsdm_filter *fl, /* * Look for filter and integrator oversampling ratios which allows - * to reach 24 bits data output resolution. - * Leave as soon as if exact resolution if reached. - * Otherwise the higher resolution below 32 bits is kept. + * to maximize data output resolution. */ - fl->res = 0; for (fosr = 1; fosr <= DFSDM_MAX_FL_OVERSAMPLING; fosr++) { for (iosr = 1; iosr <= DFSDM_MAX_INT_OVERSAMPLING; iosr++) { if (fast) @@ -236,33 +241,91 @@ static int stm32_dfsdm_set_osrs(struct stm32_dfsdm_filter *fl, res = fosr; for (i = p - 1; i > 0; i--) { res = res * (u64)fosr; - if (res > DFSDM_MAX_RES) + if (res > DFSDM_DATA_MAX) break; } - if (res > DFSDM_MAX_RES) + if (res > DFSDM_DATA_MAX) continue; + res = res * (u64)m * (u64)iosr; - if (res > DFSDM_MAX_RES) + if (res > DFSDM_DATA_MAX) continue; - delta = res - DFSDM_DATA_RES; - - if (res >= fl->res) { - fl->res = res; - fl->fosr = fosr; - fl->iosr = iosr; - fl->fast = fast; - pr_debug("%s: fosr = %d, iosr = %d\n", - __func__, fl->fosr, fl->iosr); + if (res >= flo->res) { + flo->res = res; + flo->fosr = fosr; + flo->iosr = iosr; + + bits = fls(flo->res); + /* 8 LBSs in data register contain chan info */ + max = flo->res << 8; + + /* if resolution is not a power of two */ + if (flo->res > BIT(bits - 1)) + bits++; + else + max--; + + shift = DFSDM_DATA_RES - bits; + /* + * Compute right/left shift + * Right shift is performed by hardware + * when transferring samples to data register. + * Left shift is done by software on buffer + */ + if (shift > 0) { + /* Resolution is lower than 24 bits */ + flo->rshift = 0; + flo->lshift = shift; + } else { + /* + * If resolution is 24 bits or more, + * max positive value may be ambiguous + * (equal to max negative value as sign + * bit is dropped). + * Reduce resolution to 23 bits (rshift) + * to keep the sign on bit 23 and treat + * saturation before rescaling on 24 + * bits (lshift). + */ + flo->rshift = 1 - shift; + flo->lshift = 1; + max >>= flo->rshift; + } + flo->max = (s32)max; + + pr_debug("%s: fast %d, fosr %d, iosr %d, res 0x%llx/%d bits, rshift %d, lshift %d\n", + __func__, fast, flo->fosr, flo->iosr, + flo->res, bits, flo->rshift, + flo->lshift); } - - if (!delta) - return 0; } } - if (!fl->res) + if (!flo->res) + return -EINVAL; + + return 0; +} + +static int stm32_dfsdm_compute_all_osrs(struct iio_dev *indio_dev, + unsigned int oversamp) +{ + struct stm32_dfsdm_adc *adc = iio_priv(indio_dev); + struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[adc->fl_id]; + int ret0, ret1; + + memset(&fl->flo[0], 0, sizeof(fl->flo[0])); + memset(&fl->flo[1], 0, sizeof(fl->flo[1])); + + ret0 = stm32_dfsdm_compute_osrs(fl, 0, oversamp); + ret1 = stm32_dfsdm_compute_osrs(fl, 1, oversamp); + if (ret0 < 0 && ret1 < 0) { + dev_err(&indio_dev->dev, + "Filter parameters not found: errors %d/%d\n", + ret0, ret1); return -EINVAL; + } return 0; } @@ -384,6 +447,50 @@ static int stm32_dfsdm_filter_set_trig(struct stm32_dfsdm_adc *adc, return 0; } +static int stm32_dfsdm_channels_configure(struct stm32_dfsdm_adc *adc, + unsigned int fl_id, + struct iio_trigger *trig) +{ + struct iio_dev *indio_dev = iio_priv_to_dev(adc); + struct regmap *regmap = adc->dfsdm->regmap; + struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[fl_id]; + struct stm32_dfsdm_filter_osr *flo = &fl->flo[0]; + const struct iio_chan_spec *chan; + unsigned int bit; + int ret; + + fl->fast = 0; + + /* + * In continuous mode, use fast mode configuration, + * if it provides a better resolution. + */ + if (adc->nconv == 1 && !trig && + (indio_dev->currentmode & INDIO_BUFFER_SOFTWARE)) { + if (fl->flo[1].res >= fl->flo[0].res) { + fl->fast = 1; + flo = &fl->flo[1]; + } + } + + if (!flo->res) + return -EINVAL; + + for_each_set_bit(bit, &adc->smask, + sizeof(adc->smask) * BITS_PER_BYTE) { + chan = indio_dev->channels + bit; + + ret = regmap_update_bits(regmap, + DFSDM_CHCFGR2(chan->channel), + DFSDM_CHCFGR2_DTRBS_MASK, + DFSDM_CHCFGR2_DTRBS(flo->rshift)); + if (ret) + return ret; + } + + return 0; +} + static int stm32_dfsdm_filter_configure(struct stm32_dfsdm_adc *adc, unsigned int fl_id, struct iio_trigger *trig) @@ -391,6 +498,7 @@ static int stm32_dfsdm_filter_configure(struct stm32_dfsdm_adc *adc, struct iio_dev *indio_dev = iio_priv_to_dev(adc); struct regmap *regmap = adc->dfsdm->regmap; struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[fl_id]; + struct stm32_dfsdm_filter_osr *flo = &fl->flo[fl->fast]; u32 cr1; const struct iio_chan_spec *chan; unsigned int bit, jchg = 0; @@ -398,13 +506,13 @@ static int stm32_dfsdm_filter_configure(struct stm32_dfsdm_adc *adc, /* Average integrator oversampling */ ret = regmap_update_bits(regmap, DFSDM_FCR(fl_id), DFSDM_FCR_IOSR_MASK, - DFSDM_FCR_IOSR(fl->iosr - 1)); + DFSDM_FCR_IOSR(flo->iosr - 1)); if (ret) return ret; /* Filter order and Oversampling */ ret = regmap_update_bits(regmap, DFSDM_FCR(fl_id), DFSDM_FCR_FOSR_MASK, - DFSDM_FCR_FOSR(fl->fosr - 1)); + DFSDM_FCR_FOSR(flo->fosr - 1)); if (ret) return ret; @@ -417,6 +525,12 @@ static int stm32_dfsdm_filter_configure(struct stm32_dfsdm_adc *adc, if (ret) return ret; + ret = regmap_update_bits(regmap, DFSDM_CR1(fl_id), + DFSDM_CR1_FAST_MASK, + DFSDM_CR1_FAST(fl->fast)); + if (ret) + return ret; + /* * DFSDM modes configuration W.R.T audio/iio type modes * ---------------------------------------------------------------- @@ -563,7 +677,6 @@ static int dfsdm_adc_set_samp_freq(struct iio_dev *indio_dev, unsigned int spi_freq) { struct stm32_dfsdm_adc *adc = iio_priv(indio_dev); - struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[adc->fl_id]; unsigned int oversamp; int ret; @@ -573,11 +686,10 @@ static int dfsdm_adc_set_samp_freq(struct iio_dev *indio_dev, "Rate not accurate. requested (%u), actual (%u)\n", sample_freq, spi_freq / oversamp); - ret = stm32_dfsdm_set_osrs(fl, 0, oversamp); - if (ret < 0) { - dev_err(&indio_dev->dev, "No filter parameters that match!\n"); + ret = stm32_dfsdm_compute_all_osrs(indio_dev, oversamp); + if (ret < 0) return ret; - } + adc->sample_freq = spi_freq / oversamp; adc->oversamp = oversamp; @@ -623,6 +735,10 @@ static int stm32_dfsdm_start_conv(struct stm32_dfsdm_adc *adc, struct regmap *regmap = adc->dfsdm->regmap; int ret; + ret = stm32_dfsdm_channels_configure(adc, adc->fl_id, trig); + if (ret < 0) + return ret; + ret = stm32_dfsdm_start_channel(adc); if (ret < 0) return ret; @@ -702,6 +818,30 @@ static unsigned int stm32_dfsdm_adc_dma_residue(struct stm32_dfsdm_adc *adc) return 0; } +static inline void stm32_dfsdm_process_data(struct stm32_dfsdm_adc *adc, + s32 *buffer) +{ + struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[adc->fl_id]; + struct stm32_dfsdm_filter_osr *flo = &fl->flo[fl->fast]; + unsigned int i = adc->nconv; + s32 *ptr = buffer; + + while (i--) { + /* Mask 8 LSB that contains the channel ID */ + *ptr &= 0xFFFFFF00; + /* Convert 2^(n-1) sample to 2^(n-1)-1 to avoid wrap-around */ + if (*ptr > flo->max) + *ptr -= 1; + /* + * Samples from filter are retrieved with 23 bits resolution + * or less. Shift left to align MSB on 24 bits. + */ + *ptr <<= flo->lshift; + + ptr++; + } +} + static irqreturn_t stm32_dfsdm_adc_trigger_handler(int irq, void *p) { struct iio_poll_func *pf = p; @@ -710,7 +850,9 @@ static irqreturn_t stm32_dfsdm_adc_trigger_handler(int irq, void *p) int available = stm32_dfsdm_adc_dma_residue(adc); while (available >= indio_dev->scan_bytes) { - u32 *buffer = (u32 *)&adc->rx_buf[adc->bufi]; + s32 *buffer = (s32 *)&adc->rx_buf[adc->bufi]; + + stm32_dfsdm_process_data(adc, buffer); iio_push_to_buffers_with_timestamp(indio_dev, buffer, pf->timestamp); @@ -751,10 +893,10 @@ static void stm32_dfsdm_dma_buffer_done(void *data) old_pos = adc->bufi; while (available >= indio_dev->scan_bytes) { - u32 *buffer = (u32 *)&adc->rx_buf[adc->bufi]; + s32 *buffer = (s32 *)&adc->rx_buf[adc->bufi]; + + stm32_dfsdm_process_data(adc, buffer); - /* Mask 8 LSB that contains the channel ID */ - *buffer = (*buffer & 0xFFFFFF00) << 8; available -= indio_dev->scan_bytes; adc->bufi += indio_dev->scan_bytes; if (adc->bufi >= adc->buf_sz) { @@ -776,6 +918,11 @@ static void stm32_dfsdm_dma_buffer_done(void *data) static int stm32_dfsdm_adc_dma_start(struct iio_dev *indio_dev) { struct stm32_dfsdm_adc *adc = iio_priv(indio_dev); + /* + * The DFSDM supports half-word transfers. However, for 16 bits record, + * 4 bytes buswidth is kept, to avoid losing samples LSBs when left + * shift is required. + */ struct dma_slave_config config = { .src_addr = (dma_addr_t)adc->dfsdm->phys_base, .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, @@ -1068,7 +1215,6 @@ static int stm32_dfsdm_write_raw(struct iio_dev *indio_dev, int val, int val2, long mask) { struct stm32_dfsdm_adc *adc = iio_priv(indio_dev); - struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[adc->fl_id]; struct stm32_dfsdm_channel *ch = &adc->dfsdm->ch_list[chan->channel]; unsigned int spi_freq; int ret = -EINVAL; @@ -1078,7 +1224,7 @@ static int stm32_dfsdm_write_raw(struct iio_dev *indio_dev, ret = iio_device_claim_direct_mode(indio_dev); if (ret) return ret; - ret = stm32_dfsdm_set_osrs(fl, 0, val); + ret = stm32_dfsdm_compute_all_osrs(indio_dev, val); if (!ret) adc->oversamp = val; iio_device_release_direct_mode(indio_dev); @@ -1277,11 +1423,11 @@ static int stm32_dfsdm_adc_chan_init_one(struct iio_dev *indio_dev, BIT(IIO_CHAN_INFO_SAMP_FREQ); if (adc->dev_data->type == DFSDM_AUDIO) { - ch->scan_type.sign = 's'; ch->ext_info = dfsdm_adc_audio_ext_info; } else { - ch->scan_type.sign = 'u'; + ch->scan_type.shift = 8; } + ch->scan_type.sign = 's'; ch->scan_type.realbits = 24; ch->scan_type.storagebits = 32; @@ -1327,8 +1473,7 @@ static int stm32_dfsdm_adc_init(struct iio_dev *indio_dev) int ret, chan_idx; adc->oversamp = DFSDM_DEFAULT_OVERSAMPLING; - ret = stm32_dfsdm_set_osrs(&adc->dfsdm->fl_list[adc->fl_id], 0, - adc->oversamp); + ret = stm32_dfsdm_compute_all_osrs(indio_dev, adc->oversamp); if (ret < 0) return ret; diff --git a/drivers/iio/adc/stm32-dfsdm.h b/drivers/iio/adc/stm32-dfsdm.h index 8708394b0725..5dbdae4ed881 100644 --- a/drivers/iio/adc/stm32-dfsdm.h +++ b/drivers/iio/adc/stm32-dfsdm.h @@ -243,19 +243,33 @@ enum stm32_dfsdm_sinc_order { }; /** - * struct stm32_dfsdm_filter - structure relative to stm32 FDSDM filter + * struct stm32_dfsdm_filter_osr - DFSDM filter settings linked to oversampling * @iosr: integrator oversampling * @fosr: filter oversampling - * @ford: filter order + * @rshift: output sample right shift (hardware shift) + * @lshift: output sample left shift (software shift) * @res: output sample resolution + * @max: output sample maximum positive value + */ +struct stm32_dfsdm_filter_osr { + unsigned int iosr; + unsigned int fosr; + unsigned int rshift; + unsigned int lshift; + u64 res; + s32 max; +}; + +/** + * struct stm32_dfsdm_filter - structure relative to stm32 FDSDM filter + * @ford: filter order + * @flo: filter oversampling data table indexed by fast mode flag * @sync_mode: filter synchronized with filter 0 * @fast: filter fast mode */ struct stm32_dfsdm_filter { - unsigned int iosr; - unsigned int fosr; enum stm32_dfsdm_sinc_order ford; - u64 res; + struct stm32_dfsdm_filter_osr flo[2]; unsigned int sync_mode; unsigned int fast; }; diff --git a/drivers/iio/amplifiers/Kconfig b/drivers/iio/amplifiers/Kconfig index 863d73519c0d..da7f126d197b 100644 --- a/drivers/iio/amplifiers/Kconfig +++ b/drivers/iio/amplifiers/Kconfig @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0-only +# SPDX-License-Identifier: GPL-2.0 # # Gain Amplifiers, etc. # @@ -7,12 +7,17 @@ menu "Amplifiers" config AD8366 - tristate "Analog Devices AD8366 VGA" + tristate "Analog Devices AD8366 and similar Gain Amplifiers" depends on SPI + depends on GPIOLIB select BITREVERSE help - Say yes here to build support for Analog Devices AD8366 - SPI Dual-Digital Variable Gain Amplifier (VGA). + Say yes here to build support for Analog Devices AD8366 and similar + gain amplifiers. This driver supports the following gain amplifiers + from Analog Devices: + AD8366 Dual-Digital Variable Gain Amplifier (VGA) + ADA4961 BiCMOS RF Digital Gain Amplifier (DGA) + ADL5240 Digitally controlled variable gain amplifier (VGA) To compile this driver as a module, choose M here: the module will be called ad8366. diff --git a/drivers/iio/amplifiers/ad8366.c b/drivers/iio/amplifiers/ad8366.c index 3d6246f86429..0176d3d8cc9c 100644 --- a/drivers/iio/amplifiers/ad8366.c +++ b/drivers/iio/amplifiers/ad8366.c @@ -1,8 +1,12 @@ -// SPDX-License-Identifier: GPL-2.0-only +// SPDX-License-Identifier: GPL-2.0 /* - * AD8366 SPI Dual-Digital Variable Gain Amplifier (VGA) + * AD8366 and similar Gain Amplifiers + * This driver supports the following gain amplifiers: + * AD8366 Dual-Digital Variable Gain Amplifier (VGA) + * ADA4961 BiCMOS RF Digital Gain Amplifier (DGA) + * ADL5240 Digitally controlled variable gain amplifier (VGA) * - * Copyright 2012 Analog Devices Inc. + * Copyright 2012-2019 Analog Devices Inc. */ #include <linux/device.h> @@ -11,6 +15,7 @@ #include <linux/sysfs.h> #include <linux/spi/spi.h> #include <linux/regulator/consumer.h> +#include <linux/gpio/consumer.h> #include <linux/err.h> #include <linux/module.h> #include <linux/bitrev.h> @@ -18,10 +23,25 @@ #include <linux/iio/iio.h> #include <linux/iio/sysfs.h> +enum ad8366_type { + ID_AD8366, + ID_ADA4961, + ID_ADL5240, +}; + +struct ad8366_info { + int gain_min; + int gain_max; +}; + struct ad8366_state { struct spi_device *spi; struct regulator *reg; + struct mutex lock; /* protect sensor state */ + struct gpio_desc *reset_gpio; unsigned char ch[2]; + enum ad8366_type type; + struct ad8366_info *info; /* * DMA (thus cache coherency maintenance) requires the * transfer buffers to live in their own cache lines. @@ -29,19 +49,44 @@ struct ad8366_state { unsigned char data[2] ____cacheline_aligned; }; +static struct ad8366_info ad8366_infos[] = { + [ID_AD8366] = { + .gain_min = 4500, + .gain_max = 20500, + }, + [ID_ADA4961] = { + .gain_min = -6000, + .gain_max = 15000, + }, + [ID_ADL5240] = { + .gain_min = -11500, + .gain_max = 20000, + }, +}; + static int ad8366_write(struct iio_dev *indio_dev, unsigned char ch_a, unsigned char ch_b) { struct ad8366_state *st = iio_priv(indio_dev); int ret; - ch_a = bitrev8(ch_a & 0x3F); - ch_b = bitrev8(ch_b & 0x3F); + switch (st->type) { + case ID_AD8366: + ch_a = bitrev8(ch_a & 0x3F); + ch_b = bitrev8(ch_b & 0x3F); - st->data[0] = ch_b >> 4; - st->data[1] = (ch_b << 4) | (ch_a >> 2); + st->data[0] = ch_b >> 4; + st->data[1] = (ch_b << 4) | (ch_a >> 2); + break; + case ID_ADA4961: + st->data[0] = ch_a & 0x1F; + break; + case ID_ADL5240: + st->data[0] = (ch_a & 0x3F); + break; + } - ret = spi_write(st->spi, st->data, ARRAY_SIZE(st->data)); + ret = spi_write(st->spi, st->data, indio_dev->num_channels); if (ret < 0) dev_err(&indio_dev->dev, "write failed (%d)", ret); @@ -56,24 +101,35 @@ static int ad8366_read_raw(struct iio_dev *indio_dev, { struct ad8366_state *st = iio_priv(indio_dev); int ret; - unsigned code; + int code, gain = 0; - mutex_lock(&indio_dev->mlock); + mutex_lock(&st->lock); switch (m) { case IIO_CHAN_INFO_HARDWAREGAIN: code = st->ch[chan->channel]; + switch (st->type) { + case ID_AD8366: + gain = code * 253 + 4500; + break; + case ID_ADA4961: + gain = 15000 - code * 1000; + break; + case ID_ADL5240: + gain = 20000 - 31500 + code * 500; + break; + } + /* Values in dB */ - code = code * 253 + 4500; - *val = code / 1000; - *val2 = (code % 1000) * 1000; + *val = gain / 1000; + *val2 = (gain % 1000) * 1000; ret = IIO_VAL_INT_PLUS_MICRO_DB; break; default: ret = -EINVAL; } - mutex_unlock(&indio_dev->mlock); + mutex_unlock(&st->lock); return ret; }; @@ -85,21 +141,32 @@ static int ad8366_write_raw(struct iio_dev *indio_dev, long mask) { struct ad8366_state *st = iio_priv(indio_dev); - unsigned code; + struct ad8366_info *inf = st->info; + int code = 0, gain; int ret; - if (val < 0 || val2 < 0) - return -EINVAL; - /* Values in dB */ - code = (((u8)val * 1000) + ((u32)val2 / 1000)); + if (val < 0) + gain = (val * 1000) - (val2 / 1000); + else + gain = (val * 1000) + (val2 / 1000); - if (code > 20500 || code < 4500) + if (gain > inf->gain_max || gain < inf->gain_min) return -EINVAL; - code = (code - 4500) / 253; + switch (st->type) { + case ID_AD8366: + code = (gain - 4500) / 253; + break; + case ID_ADA4961: + code = (15000 - gain) / 1000; + break; + case ID_ADL5240: + code = ((gain - 500 - 20000) / 500) & 0x3F; + break; + } - mutex_lock(&indio_dev->mlock); + mutex_lock(&st->lock); switch (mask) { case IIO_CHAN_INFO_HARDWAREGAIN: st->ch[chan->channel] = code; @@ -108,7 +175,7 @@ static int ad8366_write_raw(struct iio_dev *indio_dev, default: ret = -EINVAL; } - mutex_unlock(&indio_dev->mlock); + mutex_unlock(&st->lock); return ret; } @@ -131,6 +198,10 @@ static const struct iio_chan_spec ad8366_channels[] = { AD8366_CHAN(1), }; +static const struct iio_chan_spec ada4961_channels[] = { + AD8366_CHAN(0), +}; + static int ad8366_probe(struct spi_device *spi) { struct iio_dev *indio_dev; @@ -151,14 +222,33 @@ static int ad8366_probe(struct spi_device *spi) } spi_set_drvdata(spi, indio_dev); + mutex_init(&st->lock); st->spi = spi; + st->type = spi_get_device_id(spi)->driver_data; + + switch (st->type) { + case ID_AD8366: + indio_dev->channels = ad8366_channels; + indio_dev->num_channels = ARRAY_SIZE(ad8366_channels); + break; + case ID_ADA4961: + case ID_ADL5240: + st->reset_gpio = devm_gpiod_get(&spi->dev, "reset", + GPIOD_OUT_HIGH); + indio_dev->channels = ada4961_channels; + indio_dev->num_channels = ARRAY_SIZE(ada4961_channels); + break; + default: + dev_err(&spi->dev, "Invalid device ID\n"); + ret = -EINVAL; + goto error_disable_reg; + } + st->info = &ad8366_infos[st->type]; indio_dev->dev.parent = &spi->dev; indio_dev->name = spi_get_device_id(spi)->name; indio_dev->info = &ad8366_info; indio_dev->modes = INDIO_DIRECT_MODE; - indio_dev->channels = ad8366_channels; - indio_dev->num_channels = ARRAY_SIZE(ad8366_channels); ret = ad8366_write(indio_dev, 0 , 0); if (ret < 0) @@ -192,7 +282,9 @@ static int ad8366_remove(struct spi_device *spi) } static const struct spi_device_id ad8366_id[] = { - {"ad8366", 0}, + {"ad8366", ID_AD8366}, + {"ada4961", ID_ADA4961}, + {"adl5240", ID_ADL5240}, {} }; MODULE_DEVICE_TABLE(spi, ad8366_id); @@ -209,5 +301,5 @@ static struct spi_driver ad8366_driver = { module_spi_driver(ad8366_driver); MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>"); -MODULE_DESCRIPTION("Analog Devices AD8366 VGA"); +MODULE_DESCRIPTION("Analog Devices AD8366 and similar Gain Amplifiers"); MODULE_LICENSE("GPL v2"); diff --git a/drivers/iio/frequency/Kconfig b/drivers/iio/frequency/Kconfig index c86db8b42380..240b81502512 100644 --- a/drivers/iio/frequency/Kconfig +++ b/drivers/iio/frequency/Kconfig @@ -39,5 +39,15 @@ config ADF4350 To compile this driver as a module, choose M here: the module will be called adf4350. +config ADF4371 + tristate "Analog Devices ADF4371/ADF4372 Wideband Synthesizers" + depends on SPI + select REGMAP_SPI + help + Say yes here to build support for Analog Devices ADF4371 and ADF4372 + Wideband Synthesizers. The driver provides direct access via sysfs. + + To compile this driver as a module, choose M here: the + module will be called adf4371. endmenu endmenu diff --git a/drivers/iio/frequency/Makefile b/drivers/iio/frequency/Makefile index f2e396d40ddd..518b1e50caef 100644 --- a/drivers/iio/frequency/Makefile +++ b/drivers/iio/frequency/Makefile @@ -6,3 +6,4 @@ # When adding new entries keep the list in alphabetical order obj-$(CONFIG_AD9523) += ad9523.o obj-$(CONFIG_ADF4350) += adf4350.o +obj-$(CONFIG_ADF4371) += adf4371.o diff --git a/drivers/iio/frequency/adf4371.c b/drivers/iio/frequency/adf4371.c new file mode 100644 index 000000000000..e48f15cc9ab5 --- /dev/null +++ b/drivers/iio/frequency/adf4371.c @@ -0,0 +1,632 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Analog Devices ADF4371 SPI Wideband Synthesizer driver + * + * Copyright 2019 Analog Devices Inc. + */ +#include <linux/bitfield.h> +#include <linux/clk.h> +#include <linux/device.h> +#include <linux/err.h> +#include <linux/gcd.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/regmap.h> +#include <linux/sysfs.h> +#include <linux/spi/spi.h> + +#include <linux/iio/iio.h> + +/* Registers address macro */ +#define ADF4371_REG(x) (x) + +/* ADF4371_REG0 */ +#define ADF4371_ADDR_ASC_MSK BIT(2) +#define ADF4371_ADDR_ASC(x) FIELD_PREP(ADF4371_ADDR_ASC_MSK, x) +#define ADF4371_ADDR_ASC_R_MSK BIT(5) +#define ADF4371_ADDR_ASC_R(x) FIELD_PREP(ADF4371_ADDR_ASC_R_MSK, x) +#define ADF4371_RESET_CMD 0x81 + +/* ADF4371_REG17 */ +#define ADF4371_FRAC2WORD_L_MSK GENMASK(7, 1) +#define ADF4371_FRAC2WORD_L(x) FIELD_PREP(ADF4371_FRAC2WORD_L_MSK, x) +#define ADF4371_FRAC1WORD_MSK BIT(0) +#define ADF4371_FRAC1WORD(x) FIELD_PREP(ADF4371_FRAC1WORD_MSK, x) + +/* ADF4371_REG18 */ +#define ADF4371_FRAC2WORD_H_MSK GENMASK(6, 0) +#define ADF4371_FRAC2WORD_H(x) FIELD_PREP(ADF4371_FRAC2WORD_H_MSK, x) + +/* ADF4371_REG1A */ +#define ADF4371_MOD2WORD_MSK GENMASK(5, 0) +#define ADF4371_MOD2WORD(x) FIELD_PREP(ADF4371_MOD2WORD_MSK, x) + +/* ADF4371_REG24 */ +#define ADF4371_RF_DIV_SEL_MSK GENMASK(6, 4) +#define ADF4371_RF_DIV_SEL(x) FIELD_PREP(ADF4371_RF_DIV_SEL_MSK, x) + +/* ADF4371_REG25 */ +#define ADF4371_MUTE_LD_MSK BIT(7) +#define ADF4371_MUTE_LD(x) FIELD_PREP(ADF4371_MUTE_LD_MSK, x) + +/* ADF4371_REG32 */ +#define ADF4371_TIMEOUT_MSK GENMASK(1, 0) +#define ADF4371_TIMEOUT(x) FIELD_PREP(ADF4371_TIMEOUT_MSK, x) + +/* ADF4371_REG34 */ +#define ADF4371_VCO_ALC_TOUT_MSK GENMASK(4, 0) +#define ADF4371_VCO_ALC_TOUT(x) FIELD_PREP(ADF4371_VCO_ALC_TOUT_MSK, x) + +/* Specifications */ +#define ADF4371_MIN_VCO_FREQ 4000000000ULL /* 4000 MHz */ +#define ADF4371_MAX_VCO_FREQ 8000000000ULL /* 8000 MHz */ +#define ADF4371_MAX_OUT_RF8_FREQ ADF4371_MAX_VCO_FREQ /* Hz */ +#define ADF4371_MIN_OUT_RF8_FREQ (ADF4371_MIN_VCO_FREQ / 64) /* Hz */ +#define ADF4371_MAX_OUT_RF16_FREQ (ADF4371_MAX_VCO_FREQ * 2) /* Hz */ +#define ADF4371_MIN_OUT_RF16_FREQ (ADF4371_MIN_VCO_FREQ * 2) /* Hz */ +#define ADF4371_MAX_OUT_RF32_FREQ (ADF4371_MAX_VCO_FREQ * 4) /* Hz */ +#define ADF4371_MIN_OUT_RF32_FREQ (ADF4371_MIN_VCO_FREQ * 4) /* Hz */ + +#define ADF4371_MAX_FREQ_PFD 250000000UL /* Hz */ +#define ADF4371_MAX_FREQ_REFIN 600000000UL /* Hz */ + +/* MOD1 is a 24-bit primary modulus with fixed value of 2^25 */ +#define ADF4371_MODULUS1 33554432ULL +/* MOD2 is the programmable, 14-bit auxiliary fractional modulus */ +#define ADF4371_MAX_MODULUS2 BIT(14) + +#define ADF4371_CHECK_RANGE(freq, range) \ + ((freq > ADF4371_MAX_ ## range) || (freq < ADF4371_MIN_ ## range)) + +enum { + ADF4371_FREQ, + ADF4371_POWER_DOWN, + ADF4371_CHANNEL_NAME +}; + +enum { + ADF4371_CH_RF8, + ADF4371_CH_RFAUX8, + ADF4371_CH_RF16, + ADF4371_CH_RF32 +}; + +enum adf4371_variant { + ADF4371, + ADF4372 +}; + +struct adf4371_pwrdown { + unsigned int reg; + unsigned int bit; +}; + +static const char * const adf4371_ch_names[] = { + "RF8x", "RFAUX8x", "RF16x", "RF32x" +}; + +static const struct adf4371_pwrdown adf4371_pwrdown_ch[4] = { + [ADF4371_CH_RF8] = { ADF4371_REG(0x25), 2 }, + [ADF4371_CH_RFAUX8] = { ADF4371_REG(0x72), 3 }, + [ADF4371_CH_RF16] = { ADF4371_REG(0x25), 3 }, + [ADF4371_CH_RF32] = { ADF4371_REG(0x25), 4 }, +}; + +static const struct reg_sequence adf4371_reg_defaults[] = { + { ADF4371_REG(0x0), 0x18 }, + { ADF4371_REG(0x12), 0x40 }, + { ADF4371_REG(0x1E), 0x48 }, + { ADF4371_REG(0x20), 0x14 }, + { ADF4371_REG(0x22), 0x00 }, + { ADF4371_REG(0x23), 0x00 }, + { ADF4371_REG(0x24), 0x80 }, + { ADF4371_REG(0x25), 0x07 }, + { ADF4371_REG(0x27), 0xC5 }, + { ADF4371_REG(0x28), 0x83 }, + { ADF4371_REG(0x2C), 0x44 }, + { ADF4371_REG(0x2D), 0x11 }, + { ADF4371_REG(0x2E), 0x12 }, + { ADF4371_REG(0x2F), 0x94 }, + { ADF4371_REG(0x32), 0x04 }, + { ADF4371_REG(0x35), 0xFA }, + { ADF4371_REG(0x36), 0x30 }, + { ADF4371_REG(0x39), 0x07 }, + { ADF4371_REG(0x3A), 0x55 }, + { ADF4371_REG(0x3E), 0x0C }, + { ADF4371_REG(0x3F), 0x80 }, + { ADF4371_REG(0x40), 0x50 }, + { ADF4371_REG(0x41), 0x28 }, + { ADF4371_REG(0x47), 0xC0 }, + { ADF4371_REG(0x52), 0xF4 }, + { ADF4371_REG(0x70), 0x03 }, + { ADF4371_REG(0x71), 0x60 }, + { ADF4371_REG(0x72), 0x32 }, +}; + +static const struct regmap_config adf4371_regmap_config = { + .reg_bits = 16, + .val_bits = 8, + .read_flag_mask = BIT(7), +}; + +struct adf4371_chip_info { + unsigned int num_channels; + const struct iio_chan_spec *channels; +}; + +struct adf4371_state { + struct spi_device *spi; + struct regmap *regmap; + struct clk *clkin; + /* + * Lock for accessing device registers. Some operations require + * multiple consecutive R/W operations, during which the device + * shouldn't be interrupted. The buffers are also shared across + * all operations so need to be protected on stand alone reads and + * writes. + */ + struct mutex lock; + const struct adf4371_chip_info *chip_info; + unsigned long clkin_freq; + unsigned long fpfd; + unsigned int integer; + unsigned int fract1; + unsigned int fract2; + unsigned int mod2; + unsigned int rf_div_sel; + unsigned int ref_div_factor; + u8 buf[10] ____cacheline_aligned; +}; + +static unsigned long long adf4371_pll_fract_n_get_rate(struct adf4371_state *st, + u32 channel) +{ + unsigned long long val, tmp; + unsigned int ref_div_sel; + + val = (((u64)st->integer * ADF4371_MODULUS1) + st->fract1) * st->fpfd; + tmp = (u64)st->fract2 * st->fpfd; + do_div(tmp, st->mod2); + val += tmp + ADF4371_MODULUS1 / 2; + + if (channel == ADF4371_CH_RF8 || channel == ADF4371_CH_RFAUX8) + ref_div_sel = st->rf_div_sel; + else + ref_div_sel = 0; + + do_div(val, ADF4371_MODULUS1 * (1 << ref_div_sel)); + + if (channel == ADF4371_CH_RF16) + val <<= 1; + else if (channel == ADF4371_CH_RF32) + val <<= 2; + + return val; +} + +static void adf4371_pll_fract_n_compute(unsigned long long vco, + unsigned long long pfd, + unsigned int *integer, + unsigned int *fract1, + unsigned int *fract2, + unsigned int *mod2) +{ + unsigned long long tmp; + u32 gcd_div; + + tmp = do_div(vco, pfd); + tmp = tmp * ADF4371_MODULUS1; + *fract2 = do_div(tmp, pfd); + + *integer = vco; + *fract1 = tmp; + + *mod2 = pfd; + + while (*mod2 > ADF4371_MAX_MODULUS2) { + *mod2 >>= 1; + *fract2 >>= 1; + } + + gcd_div = gcd(*fract2, *mod2); + *mod2 /= gcd_div; + *fract2 /= gcd_div; +} + +static int adf4371_set_freq(struct adf4371_state *st, unsigned long long freq, + unsigned int channel) +{ + u32 cp_bleed; + u8 int_mode = 0; + int ret; + + switch (channel) { + case ADF4371_CH_RF8: + case ADF4371_CH_RFAUX8: + if (ADF4371_CHECK_RANGE(freq, OUT_RF8_FREQ)) + return -EINVAL; + + st->rf_div_sel = 0; + + while (freq < ADF4371_MIN_VCO_FREQ) { + freq <<= 1; + st->rf_div_sel++; + } + break; + case ADF4371_CH_RF16: + /* ADF4371 RF16 8000...16000 MHz */ + if (ADF4371_CHECK_RANGE(freq, OUT_RF16_FREQ)) + return -EINVAL; + + freq >>= 1; + break; + case ADF4371_CH_RF32: + /* ADF4371 RF32 16000...32000 MHz */ + if (ADF4371_CHECK_RANGE(freq, OUT_RF32_FREQ)) + return -EINVAL; + + freq >>= 2; + break; + default: + return -EINVAL; + } + + adf4371_pll_fract_n_compute(freq, st->fpfd, &st->integer, &st->fract1, + &st->fract2, &st->mod2); + st->buf[0] = st->integer >> 8; + st->buf[1] = 0x40; /* REG12 default */ + st->buf[2] = 0x00; + st->buf[3] = st->fract2 & 0xFF; + st->buf[4] = st->fract2 >> 7; + st->buf[5] = st->fract2 >> 15; + st->buf[6] = ADF4371_FRAC2WORD_L(st->fract2 & 0x7F) | + ADF4371_FRAC1WORD(st->fract1 >> 23); + st->buf[7] = ADF4371_FRAC2WORD_H(st->fract2 >> 7); + st->buf[8] = st->mod2 & 0xFF; + st->buf[9] = ADF4371_MOD2WORD(st->mod2 >> 8); + + ret = regmap_bulk_write(st->regmap, ADF4371_REG(0x11), st->buf, 10); + if (ret < 0) + return ret; + /* + * The R counter allows the input reference frequency to be + * divided down to produce the reference clock to the PFD + */ + ret = regmap_write(st->regmap, ADF4371_REG(0x1F), st->ref_div_factor); + if (ret < 0) + return ret; + + ret = regmap_update_bits(st->regmap, ADF4371_REG(0x24), + ADF4371_RF_DIV_SEL_MSK, + ADF4371_RF_DIV_SEL(st->rf_div_sel)); + if (ret < 0) + return ret; + + cp_bleed = DIV_ROUND_UP(400 * 1750, st->integer * 375); + cp_bleed = clamp(cp_bleed, 1U, 255U); + ret = regmap_write(st->regmap, ADF4371_REG(0x26), cp_bleed); + if (ret < 0) + return ret; + /* + * Set to 1 when in INT mode (when FRAC1 = FRAC2 = 0), + * and set to 0 when in FRAC mode. + */ + if (st->fract1 == 0 && st->fract2 == 0) + int_mode = 0x01; + + ret = regmap_write(st->regmap, ADF4371_REG(0x2B), int_mode); + if (ret < 0) + return ret; + + return regmap_write(st->regmap, ADF4371_REG(0x10), st->integer & 0xFF); +} + +static ssize_t adf4371_read(struct iio_dev *indio_dev, + uintptr_t private, + const struct iio_chan_spec *chan, + char *buf) +{ + struct adf4371_state *st = iio_priv(indio_dev); + unsigned long long val = 0; + unsigned int readval, reg, bit; + int ret; + + switch ((u32)private) { + case ADF4371_FREQ: + val = adf4371_pll_fract_n_get_rate(st, chan->channel); + ret = regmap_read(st->regmap, ADF4371_REG(0x7C), &readval); + if (ret < 0) + break; + + if (readval == 0x00) { + dev_dbg(&st->spi->dev, "PLL un-locked\n"); + ret = -EBUSY; + } + break; + case ADF4371_POWER_DOWN: + reg = adf4371_pwrdown_ch[chan->channel].reg; + bit = adf4371_pwrdown_ch[chan->channel].bit; + + ret = regmap_read(st->regmap, reg, &readval); + if (ret < 0) + break; + + val = !(readval & BIT(bit)); + break; + case ADF4371_CHANNEL_NAME: + return sprintf(buf, "%s\n", adf4371_ch_names[chan->channel]); + default: + ret = -EINVAL; + val = 0; + break; + } + + return ret < 0 ? ret : sprintf(buf, "%llu\n", val); +} + +static ssize_t adf4371_write(struct iio_dev *indio_dev, + uintptr_t private, + const struct iio_chan_spec *chan, + const char *buf, size_t len) +{ + struct adf4371_state *st = iio_priv(indio_dev); + unsigned long long freq; + bool power_down; + unsigned int bit, readval, reg; + int ret; + + mutex_lock(&st->lock); + switch ((u32)private) { + case ADF4371_FREQ: + ret = kstrtoull(buf, 10, &freq); + if (ret) + break; + + ret = adf4371_set_freq(st, freq, chan->channel); + break; + case ADF4371_POWER_DOWN: + ret = kstrtobool(buf, &power_down); + if (ret) + break; + + reg = adf4371_pwrdown_ch[chan->channel].reg; + bit = adf4371_pwrdown_ch[chan->channel].bit; + ret = regmap_read(st->regmap, reg, &readval); + if (ret < 0) + break; + + readval &= ~BIT(bit); + readval |= (!power_down << bit); + + ret = regmap_write(st->regmap, reg, readval); + break; + default: + ret = -EINVAL; + break; + } + mutex_unlock(&st->lock); + + return ret ? ret : len; +} + +#define _ADF4371_EXT_INFO(_name, _ident) { \ + .name = _name, \ + .read = adf4371_read, \ + .write = adf4371_write, \ + .private = _ident, \ + .shared = IIO_SEPARATE, \ +} + +static const struct iio_chan_spec_ext_info adf4371_ext_info[] = { + /* + * Ideally we use IIO_CHAN_INFO_FREQUENCY, but there are + * values > 2^32 in order to support the entire frequency range + * in Hz. Using scale is a bit ugly. + */ + _ADF4371_EXT_INFO("frequency", ADF4371_FREQ), + _ADF4371_EXT_INFO("powerdown", ADF4371_POWER_DOWN), + _ADF4371_EXT_INFO("name", ADF4371_CHANNEL_NAME), + { }, +}; + +#define ADF4371_CHANNEL(index) { \ + .type = IIO_ALTVOLTAGE, \ + .output = 1, \ + .channel = index, \ + .ext_info = adf4371_ext_info, \ + .indexed = 1, \ + } + +static const struct iio_chan_spec adf4371_chan[] = { + ADF4371_CHANNEL(ADF4371_CH_RF8), + ADF4371_CHANNEL(ADF4371_CH_RFAUX8), + ADF4371_CHANNEL(ADF4371_CH_RF16), + ADF4371_CHANNEL(ADF4371_CH_RF32), +}; + +static const struct adf4371_chip_info adf4371_chip_info[] = { + [ADF4371] = { + .channels = adf4371_chan, + .num_channels = 4, + }, + [ADF4372] = { + .channels = adf4371_chan, + .num_channels = 3, + } +}; + +static int adf4371_reg_access(struct iio_dev *indio_dev, + unsigned int reg, + unsigned int writeval, + unsigned int *readval) +{ + struct adf4371_state *st = iio_priv(indio_dev); + + if (readval) + return regmap_read(st->regmap, reg, readval); + else + return regmap_write(st->regmap, reg, writeval); +} + +static const struct iio_info adf4371_info = { + .debugfs_reg_access = &adf4371_reg_access, +}; + +static int adf4371_setup(struct adf4371_state *st) +{ + unsigned int synth_timeout = 2, timeout = 1, vco_alc_timeout = 1; + unsigned int vco_band_div, tmp; + int ret; + + /* Perform a software reset */ + ret = regmap_write(st->regmap, ADF4371_REG(0x0), ADF4371_RESET_CMD); + if (ret < 0) + return ret; + + ret = regmap_multi_reg_write(st->regmap, adf4371_reg_defaults, + ARRAY_SIZE(adf4371_reg_defaults)); + if (ret < 0) + return ret; + + /* Mute to Lock Detect */ + if (device_property_read_bool(&st->spi->dev, "adi,mute-till-lock-en")) { + ret = regmap_update_bits(st->regmap, ADF4371_REG(0x25), + ADF4371_MUTE_LD_MSK, + ADF4371_MUTE_LD(1)); + if (ret < 0) + return ret; + } + + /* Set address in ascending order, so the bulk_write() will work */ + ret = regmap_update_bits(st->regmap, ADF4371_REG(0x0), + ADF4371_ADDR_ASC_MSK | ADF4371_ADDR_ASC_R_MSK, + ADF4371_ADDR_ASC(1) | ADF4371_ADDR_ASC_R(1)); + if (ret < 0) + return ret; + /* + * Calculate and maximize PFD frequency + * fPFD = REFIN × ((1 + D)/(R × (1 + T))) + * Where D is the REFIN doubler bit, T is the reference divide by 2, + * R is the reference division factor + * TODO: it is assumed D and T equal 0. + */ + do { + st->ref_div_factor++; + st->fpfd = st->clkin_freq / st->ref_div_factor; + } while (st->fpfd > ADF4371_MAX_FREQ_PFD); + + /* Calculate Timeouts */ + vco_band_div = DIV_ROUND_UP(st->fpfd, 2400000U); + + tmp = DIV_ROUND_CLOSEST(st->fpfd, 1000000U); + do { + timeout++; + if (timeout > 1023) { + timeout = 2; + synth_timeout++; + } + } while (synth_timeout * 1024 + timeout <= 20 * tmp); + + do { + vco_alc_timeout++; + } while (vco_alc_timeout * 1024 - timeout <= 50 * tmp); + + st->buf[0] = vco_band_div; + st->buf[1] = timeout & 0xFF; + st->buf[2] = ADF4371_TIMEOUT(timeout >> 8) | 0x04; + st->buf[3] = synth_timeout; + st->buf[4] = ADF4371_VCO_ALC_TOUT(vco_alc_timeout); + + return regmap_bulk_write(st->regmap, ADF4371_REG(0x30), st->buf, 5); +} + +static void adf4371_clk_disable(void *data) +{ + struct adf4371_state *st = data; + + clk_disable_unprepare(st->clkin); +} + +static int adf4371_probe(struct spi_device *spi) +{ + const struct spi_device_id *id = spi_get_device_id(spi); + struct iio_dev *indio_dev; + struct adf4371_state *st; + struct regmap *regmap; + int ret; + + indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); + if (!indio_dev) + return -ENOMEM; + + regmap = devm_regmap_init_spi(spi, &adf4371_regmap_config); + if (IS_ERR(regmap)) { + dev_err(&spi->dev, "Error initializing spi regmap: %ld\n", + PTR_ERR(regmap)); + return PTR_ERR(regmap); + } + + st = iio_priv(indio_dev); + spi_set_drvdata(spi, indio_dev); + st->spi = spi; + st->regmap = regmap; + mutex_init(&st->lock); + + st->chip_info = &adf4371_chip_info[id->driver_data]; + indio_dev->dev.parent = &spi->dev; + indio_dev->name = id->name; + indio_dev->info = &adf4371_info; + indio_dev->modes = INDIO_DIRECT_MODE; + indio_dev->channels = st->chip_info->channels; + indio_dev->num_channels = st->chip_info->num_channels; + + st->clkin = devm_clk_get(&spi->dev, "clkin"); + if (IS_ERR(st->clkin)) + return PTR_ERR(st->clkin); + + ret = clk_prepare_enable(st->clkin); + if (ret < 0) + return ret; + + ret = devm_add_action_or_reset(&spi->dev, adf4371_clk_disable, st); + if (ret) + return ret; + + st->clkin_freq = clk_get_rate(st->clkin); + + ret = adf4371_setup(st); + if (ret < 0) { + dev_err(&spi->dev, "ADF4371 setup failed\n"); + return ret; + } + + return devm_iio_device_register(&spi->dev, indio_dev); +} + +static const struct spi_device_id adf4371_id_table[] = { + { "adf4371", ADF4371 }, + { "adf4372", ADF4372 }, + {} +}; +MODULE_DEVICE_TABLE(spi, adf4371_id_table); + +static const struct of_device_id adf4371_of_match[] = { + { .compatible = "adi,adf4371" }, + { .compatible = "adi,adf4372" }, + { }, +}; +MODULE_DEVICE_TABLE(of, adf4371_of_match); + +static struct spi_driver adf4371_driver = { + .driver = { + .name = "adf4371", + .of_match_table = adf4371_of_match, + }, + .probe = adf4371_probe, + .id_table = adf4371_id_table, +}; +module_spi_driver(adf4371_driver); + +MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>"); +MODULE_DESCRIPTION("Analog Devices ADF4371 SPI PLL"); +MODULE_LICENSE("GPL"); diff --git a/drivers/iio/humidity/dht11.c b/drivers/iio/humidity/dht11.c index c8159205c77d..f5128d8f777a 100644 --- a/drivers/iio/humidity/dht11.c +++ b/drivers/iio/humidity/dht11.c @@ -22,8 +22,7 @@ #include <linux/completion.h> #include <linux/mutex.h> #include <linux/delay.h> -#include <linux/gpio.h> -#include <linux/of_gpio.h> +#include <linux/gpio/consumer.h> #include <linux/timekeeping.h> #include <linux/iio/iio.h> @@ -72,7 +71,7 @@ struct dht11 { struct device *dev; - int gpio; + struct gpio_desc *gpiod; int irq; struct completion completion; @@ -179,7 +178,7 @@ static irqreturn_t dht11_handle_irq(int irq, void *data) if (dht11->num_edges < DHT11_EDGES_PER_READ && dht11->num_edges >= 0) { dht11->edges[dht11->num_edges].ts = ktime_get_boot_ns(); dht11->edges[dht11->num_edges++].value = - gpio_get_value(dht11->gpio); + gpiod_get_value(dht11->gpiod); if (dht11->num_edges >= DHT11_EDGES_PER_READ) complete(&dht11->completion); @@ -217,12 +216,12 @@ static int dht11_read_raw(struct iio_dev *iio_dev, reinit_completion(&dht11->completion); dht11->num_edges = 0; - ret = gpio_direction_output(dht11->gpio, 0); + ret = gpiod_direction_output(dht11->gpiod, 0); if (ret) goto err; usleep_range(DHT11_START_TRANSMISSION_MIN, DHT11_START_TRANSMISSION_MAX); - ret = gpio_direction_input(dht11->gpio); + ret = gpiod_direction_input(dht11->gpiod); if (ret) goto err; @@ -294,10 +293,8 @@ MODULE_DEVICE_TABLE(of, dht11_dt_ids); static int dht11_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; - struct device_node *node = dev->of_node; struct dht11 *dht11; struct iio_dev *iio; - int ret; iio = devm_iio_device_alloc(dev, sizeof(*dht11)); if (!iio) { @@ -307,18 +304,13 @@ static int dht11_probe(struct platform_device *pdev) dht11 = iio_priv(iio); dht11->dev = dev; + dht11->gpiod = devm_gpiod_get(dev, NULL, GPIOD_IN); + if (IS_ERR(dht11->gpiod)) + return PTR_ERR(dht11->gpiod); - ret = of_get_gpio(node, 0); - if (ret < 0) - return ret; - dht11->gpio = ret; - ret = devm_gpio_request_one(dev, dht11->gpio, GPIOF_IN, pdev->name); - if (ret) - return ret; - - dht11->irq = gpio_to_irq(dht11->gpio); + dht11->irq = gpiod_to_irq(dht11->gpiod); if (dht11->irq < 0) { - dev_err(dev, "GPIO %d has no interrupt\n", dht11->gpio); + dev_err(dev, "GPIO %d has no interrupt\n", desc_to_gpio(dht11->gpiod)); return -EINVAL; } diff --git a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h index 5e461f0e759c..c14bf533b66b 100644 --- a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h +++ b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h @@ -197,7 +197,7 @@ struct st_lsm6dsx_ext_dev_settings { * struct st_lsm6dsx_settings - ST IMU sensor settings * @wai: Sensor WhoAmI default value. * @max_fifo_size: Sensor max fifo length in FIFO words. - * @id: List of hw id supported by the driver configuration. + * @id: List of hw id/device name supported by the driver configuration. * @decimator: List of decimator register info (addr + mask). * @batch: List of FIFO batching register info (addr + mask). * @fifo_ops: Sensor hw FIFO parameters. @@ -207,7 +207,10 @@ struct st_lsm6dsx_ext_dev_settings { struct st_lsm6dsx_settings { u8 wai; u16 max_fifo_size; - enum st_lsm6dsx_hw_id id[ST_LSM6DSX_MAX_ID]; + struct { + enum st_lsm6dsx_hw_id hw_id; + const char *name; + } id[ST_LSM6DSX_MAX_ID]; struct st_lsm6dsx_reg decimator[ST_LSM6DSX_MAX_ID]; struct st_lsm6dsx_reg batch[ST_LSM6DSX_MAX_ID]; struct st_lsm6dsx_fifo_ops fifo_ops; @@ -303,7 +306,7 @@ struct st_lsm6dsx_hw { static const unsigned long st_lsm6dsx_available_scan_masks[] = {0x7, 0x0}; extern const struct dev_pm_ops st_lsm6dsx_pm_ops; -int st_lsm6dsx_probe(struct device *dev, int irq, int hw_id, const char *name, +int st_lsm6dsx_probe(struct device *dev, int irq, int hw_id, struct regmap *regmap); int st_lsm6dsx_sensor_set_enable(struct st_lsm6dsx_sensor *sensor, bool enable); diff --git a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c index fd95d924a996..a6702a74570e 100644 --- a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c +++ b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c @@ -124,7 +124,10 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sensor_settings[] = { .wai = 0x69, .max_fifo_size = 1365, .id = { - [0] = ST_LSM6DS3_ID, + { + .hw_id = ST_LSM6DS3_ID, + .name = ST_LSM6DS3_DEV_NAME, + }, }, .decimator = { [ST_LSM6DSX_ID_ACC] = { @@ -171,7 +174,10 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sensor_settings[] = { .wai = 0x69, .max_fifo_size = 682, .id = { - [0] = ST_LSM6DS3H_ID, + { + .hw_id = ST_LSM6DS3H_ID, + .name = ST_LSM6DS3H_DEV_NAME, + }, }, .decimator = { [ST_LSM6DSX_ID_ACC] = { @@ -218,9 +224,16 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sensor_settings[] = { .wai = 0x6a, .max_fifo_size = 682, .id = { - [0] = ST_LSM6DSL_ID, - [1] = ST_LSM6DSM_ID, - [2] = ST_ISM330DLC_ID, + { + .hw_id = ST_LSM6DSL_ID, + .name = ST_LSM6DSL_DEV_NAME, + }, { + .hw_id = ST_LSM6DSM_ID, + .name = ST_LSM6DSM_DEV_NAME, + }, { + .hw_id = ST_ISM330DLC_ID, + .name = ST_ISM330DLC_DEV_NAME, + }, }, .decimator = { [ST_LSM6DSX_ID_ACC] = { @@ -267,8 +280,13 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sensor_settings[] = { .wai = 0x6c, .max_fifo_size = 512, .id = { - [0] = ST_LSM6DSO_ID, - [1] = ST_LSM6DSOX_ID, + { + .hw_id = ST_LSM6DSO_ID, + .name = ST_LSM6DSO_DEV_NAME, + }, { + .hw_id = ST_LSM6DSOX_ID, + .name = ST_LSM6DSOX_DEV_NAME, + }, }, .batch = { [ST_LSM6DSX_ID_ACC] = { @@ -333,7 +351,10 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sensor_settings[] = { .wai = 0x6b, .max_fifo_size = 512, .id = { - [0] = ST_ASM330LHH_ID, + { + .hw_id = ST_ASM330LHH_ID, + .name = ST_ASM330LHH_DEV_NAME, + }, }, .batch = { [ST_LSM6DSX_ID_ACC] = { @@ -372,7 +393,10 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sensor_settings[] = { .wai = 0x6b, .max_fifo_size = 512, .id = { - [0] = ST_LSM6DSR_ID, + { + .hw_id = ST_LSM6DSR_ID, + .name = ST_LSM6DSR_DEV_NAME, + }, }, .batch = { [ST_LSM6DSX_ID_ACC] = { @@ -470,13 +494,14 @@ int st_lsm6dsx_set_page(struct st_lsm6dsx_hw *hw, bool enable) return err; } -static int st_lsm6dsx_check_whoami(struct st_lsm6dsx_hw *hw, int id) +static int st_lsm6dsx_check_whoami(struct st_lsm6dsx_hw *hw, int id, + const char **name) { int err, i, j, data; for (i = 0; i < ARRAY_SIZE(st_lsm6dsx_sensor_settings); i++) { for (j = 0; j < ST_LSM6DSX_MAX_ID; j++) { - if (id == st_lsm6dsx_sensor_settings[i].id[j]) + if (id == st_lsm6dsx_sensor_settings[i].id[j].hw_id) break; } if (j < ST_LSM6DSX_MAX_ID) @@ -499,6 +524,7 @@ static int st_lsm6dsx_check_whoami(struct st_lsm6dsx_hw *hw, int id) return -ENODEV; } + *name = st_lsm6dsx_sensor_settings[i].id[j].name; hw->settings = &st_lsm6dsx_sensor_settings[i]; return 0; @@ -1040,11 +1066,12 @@ static struct iio_dev *st_lsm6dsx_alloc_iiodev(struct st_lsm6dsx_hw *hw, return iio_dev; } -int st_lsm6dsx_probe(struct device *dev, int irq, int hw_id, const char *name, +int st_lsm6dsx_probe(struct device *dev, int irq, int hw_id, struct regmap *regmap) { const struct st_lsm6dsx_shub_settings *hub_settings; struct st_lsm6dsx_hw *hw; + const char *name = NULL; int i, err; hw = devm_kzalloc(dev, sizeof(*hw), GFP_KERNEL); @@ -1065,7 +1092,7 @@ int st_lsm6dsx_probe(struct device *dev, int irq, int hw_id, const char *name, hw->irq = irq; hw->regmap = regmap; - err = st_lsm6dsx_check_whoami(hw, hw_id); + err = st_lsm6dsx_check_whoami(hw, hw_id, &name); if (err < 0) return err; diff --git a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_i2c.c b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_i2c.c index 966d52a4bf1d..b3211e0ac07b 100644 --- a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_i2c.c +++ b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_i2c.c @@ -35,8 +35,7 @@ static int st_lsm6dsx_i2c_probe(struct i2c_client *client, return PTR_ERR(regmap); } - return st_lsm6dsx_probe(&client->dev, client->irq, - hw_id, id->name, regmap); + return st_lsm6dsx_probe(&client->dev, client->irq, hw_id, regmap); } static const struct of_device_id st_lsm6dsx_i2c_of_match[] = { diff --git a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_spi.c b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_spi.c index 24e4e50414e6..c9d3c4711018 100644 --- a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_spi.c +++ b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_spi.c @@ -35,8 +35,7 @@ static int st_lsm6dsx_spi_probe(struct spi_device *spi) return PTR_ERR(regmap); } - return st_lsm6dsx_probe(&spi->dev, spi->irq, - hw_id, id->name, regmap); + return st_lsm6dsx_probe(&spi->dev, spi->irq, hw_id, regmap); } static const struct of_device_id st_lsm6dsx_spi_of_match[] = { diff --git a/drivers/iio/industrialio-core.c b/drivers/iio/industrialio-core.c index 245b5844028d..65de9980b82c 100644 --- a/drivers/iio/industrialio-core.c +++ b/drivers/iio/industrialio-core.c @@ -366,39 +366,25 @@ static void iio_device_unregister_debugfs(struct iio_dev *indio_dev) debugfs_remove_recursive(indio_dev->debugfs_dentry); } -static int iio_device_register_debugfs(struct iio_dev *indio_dev) +static void iio_device_register_debugfs(struct iio_dev *indio_dev) { - struct dentry *d; - if (indio_dev->info->debugfs_reg_access == NULL) - return 0; + return; if (!iio_debugfs_dentry) - return 0; + return; indio_dev->debugfs_dentry = debugfs_create_dir(dev_name(&indio_dev->dev), iio_debugfs_dentry); - if (indio_dev->debugfs_dentry == NULL) { - dev_warn(indio_dev->dev.parent, - "Failed to create debugfs directory\n"); - return -EFAULT; - } - - d = debugfs_create_file("direct_reg_access", 0644, - indio_dev->debugfs_dentry, - indio_dev, &iio_debugfs_reg_fops); - if (!d) { - iio_device_unregister_debugfs(indio_dev); - return -ENOMEM; - } - return 0; + debugfs_create_file("direct_reg_access", 0644, + indio_dev->debugfs_dentry, indio_dev, + &iio_debugfs_reg_fops); } #else -static int iio_device_register_debugfs(struct iio_dev *indio_dev) +static void iio_device_register_debugfs(struct iio_dev *indio_dev) { - return 0; } static void iio_device_unregister_debugfs(struct iio_dev *indio_dev) @@ -1104,6 +1090,8 @@ static int iio_device_add_info_mask_type_avail(struct iio_dev *indio_dev, char *avail_postfix; for_each_set_bit(i, infomask, sizeof(*infomask) * 8) { + if (i >= ARRAY_SIZE(iio_chan_info_postfix)) + return -EINVAL; avail_postfix = kasprintf(GFP_KERNEL, "%s_available", iio_chan_info_postfix[i]); @@ -1669,12 +1657,7 @@ int __iio_device_register(struct iio_dev *indio_dev, struct module *this_mod) /* configure elements for the chrdev */ indio_dev->dev.devt = MKDEV(MAJOR(iio_devt), indio_dev->id); - ret = iio_device_register_debugfs(indio_dev); - if (ret) { - dev_err(indio_dev->dev.parent, - "Failed to register debugfs interfaces\n"); - return ret; - } + iio_device_register_debugfs(indio_dev); ret = iio_buffer_alloc_sysfs_and_mask(indio_dev); if (ret) { diff --git a/drivers/iio/light/bh1780.c b/drivers/iio/light/bh1780.c index 340d64d0ac59..a8361006dcd9 100644 --- a/drivers/iio/light/bh1780.c +++ b/drivers/iio/light/bh1780.c @@ -146,7 +146,7 @@ static int bh1780_probe(struct i2c_client *client, { int ret; struct bh1780_data *bh1780; - struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent); + struct i2c_adapter *adapter = client->adapter; struct iio_dev *indio_dev; if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE)) diff --git a/drivers/iio/light/stk3310.c b/drivers/iio/light/stk3310.c index eff7ac9ae669..b955183edfe8 100644 --- a/drivers/iio/light/stk3310.c +++ b/drivers/iio/light/stk3310.c @@ -37,6 +37,7 @@ #define STK3310_CHIP_ID_VAL 0x13 #define STK3311_CHIP_ID_VAL 0x1D +#define STK3335_CHIP_ID_VAL 0x51 #define STK3310_PSINT_EN 0x01 #define STK3310_PS_MAX_VAL 0xFFFF @@ -451,7 +452,8 @@ static int stk3310_init(struct iio_dev *indio_dev) return ret; if (chipid != STK3310_CHIP_ID_VAL && - chipid != STK3311_CHIP_ID_VAL) { + chipid != STK3311_CHIP_ID_VAL && + chipid != STK3335_CHIP_ID_VAL) { dev_err(&client->dev, "invalid chip id: 0x%x\n", chipid); return -ENODEV; } @@ -663,6 +665,7 @@ static SIMPLE_DEV_PM_OPS(stk3310_pm_ops, stk3310_suspend, stk3310_resume); static const struct i2c_device_id stk3310_i2c_id[] = { {"STK3310", 0}, {"STK3311", 0}, + {"STK3335", 0}, {} }; MODULE_DEVICE_TABLE(i2c, stk3310_i2c_id); @@ -670,6 +673,7 @@ MODULE_DEVICE_TABLE(i2c, stk3310_i2c_id); static const struct acpi_device_id stk3310_acpi_id[] = { {"STK3310", 0}, {"STK3311", 0}, + {"STK3335", 0}, {} }; diff --git a/drivers/iio/pressure/Kconfig b/drivers/iio/pressure/Kconfig index b191811fd749..ba420e484787 100644 --- a/drivers/iio/pressure/Kconfig +++ b/drivers/iio/pressure/Kconfig @@ -53,6 +53,17 @@ config IIO_CROS_EC_BARO To compile this driver as a module, choose M here: the module will be called cros_ec_baro. +config DPS310 + tristate "Infineon DPS310 pressure and temperature sensor" + depends on I2C + select REGMAP_I2C + help + Support for the Infineon DPS310 digital barometric pressure sensor. + It can be accessed over I2C bus. + + This driver can also be built as a module. If so, the module will be + called dps310. + config HID_SENSOR_PRESS depends on HID_SENSOR_HUB select IIO_BUFFER diff --git a/drivers/iio/pressure/Makefile b/drivers/iio/pressure/Makefile index c2058d7b2f93..d8f5ace1f25d 100644 --- a/drivers/iio/pressure/Makefile +++ b/drivers/iio/pressure/Makefile @@ -9,6 +9,7 @@ obj-$(CONFIG_BMP280) += bmp280.o bmp280-objs := bmp280-core.o bmp280-regmap.o obj-$(CONFIG_BMP280_I2C) += bmp280-i2c.o obj-$(CONFIG_BMP280_SPI) += bmp280-spi.o +obj-$(CONFIG_DPS310) += dps310.o obj-$(CONFIG_IIO_CROS_EC_BARO) += cros_ec_baro.o obj-$(CONFIG_HID_SENSOR_PRESS) += hid-sensor-press.o obj-$(CONFIG_HP03) += hp03.o diff --git a/drivers/iio/pressure/dps310.c b/drivers/iio/pressure/dps310.c new file mode 100644 index 000000000000..2c1943bbc433 --- /dev/null +++ b/drivers/iio/pressure/dps310.c @@ -0,0 +1,827 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright IBM Corp 2019 +/* + * The DPS310 is a barometric pressure and temperature sensor. + * Currently only reading a single temperature is supported by + * this driver. + * + * https://www.infineon.com/dgdl/?fileId=5546d462576f34750157750826c42242 + * + * Temperature calculation: + * c0 * 0.5 + c1 * T_raw / kT °C + * + * TODO: + * - Optionally support the FIFO + */ + +#include <linux/i2c.h> +#include <linux/limits.h> +#include <linux/math64.h> +#include <linux/module.h> +#include <linux/regmap.h> + +#include <linux/iio/iio.h> +#include <linux/iio/sysfs.h> + +#define DPS310_DEV_NAME "dps310" + +#define DPS310_PRS_B0 0x00 +#define DPS310_PRS_B1 0x01 +#define DPS310_PRS_B2 0x02 +#define DPS310_TMP_B0 0x03 +#define DPS310_TMP_B1 0x04 +#define DPS310_TMP_B2 0x05 +#define DPS310_PRS_CFG 0x06 +#define DPS310_PRS_RATE_BITS GENMASK(6, 4) +#define DPS310_PRS_PRC_BITS GENMASK(3, 0) +#define DPS310_TMP_CFG 0x07 +#define DPS310_TMP_RATE_BITS GENMASK(6, 4) +#define DPS310_TMP_PRC_BITS GENMASK(3, 0) +#define DPS310_TMP_EXT BIT(7) +#define DPS310_MEAS_CFG 0x08 +#define DPS310_MEAS_CTRL_BITS GENMASK(2, 0) +#define DPS310_PRS_EN BIT(0) +#define DPS310_TEMP_EN BIT(1) +#define DPS310_BACKGROUND BIT(2) +#define DPS310_PRS_RDY BIT(4) +#define DPS310_TMP_RDY BIT(5) +#define DPS310_SENSOR_RDY BIT(6) +#define DPS310_COEF_RDY BIT(7) +#define DPS310_CFG_REG 0x09 +#define DPS310_INT_HL BIT(7) +#define DPS310_TMP_SHIFT_EN BIT(3) +#define DPS310_PRS_SHIFT_EN BIT(4) +#define DPS310_FIFO_EN BIT(5) +#define DPS310_SPI_EN BIT(6) +#define DPS310_RESET 0x0c +#define DPS310_RESET_MAGIC 0x09 +#define DPS310_COEF_BASE 0x10 + +/* Make sure sleep time is <= 20ms for usleep_range */ +#define DPS310_POLL_SLEEP_US(t) min(20000, (t) / 8) +/* Silently handle error in rate value here */ +#define DPS310_POLL_TIMEOUT_US(rc) ((rc) <= 0 ? 1000000 : 1000000 / (rc)) + +#define DPS310_PRS_BASE DPS310_PRS_B0 +#define DPS310_TMP_BASE DPS310_TMP_B0 + +/* + * These values (defined in the spec) indicate how to scale the raw register + * values for each level of precision available. + */ +static const int scale_factors[] = { + 524288, + 1572864, + 3670016, + 7864320, + 253952, + 516096, + 1040384, + 2088960, +}; + +struct dps310_data { + struct i2c_client *client; + struct regmap *regmap; + struct mutex lock; /* Lock for sequential HW access functions */ + + s32 c0, c1; + s32 c00, c10, c20, c30, c01, c11, c21; + s32 pressure_raw; + s32 temp_raw; +}; + +static const struct iio_chan_spec dps310_channels[] = { + { + .type = IIO_TEMP, + .info_mask_separate = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO) | + BIT(IIO_CHAN_INFO_SAMP_FREQ) | + BIT(IIO_CHAN_INFO_PROCESSED), + }, + { + .type = IIO_PRESSURE, + .info_mask_separate = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO) | + BIT(IIO_CHAN_INFO_SAMP_FREQ) | + BIT(IIO_CHAN_INFO_PROCESSED), + }, +}; + +/* To be called after checking the COEF_RDY bit in MEAS_CFG */ +static int dps310_get_coefs(struct dps310_data *data) +{ + int rc; + u8 coef[18]; + u32 c0, c1; + u32 c00, c10, c20, c30, c01, c11, c21; + + /* Read all sensor calibration coefficients from the COEF registers. */ + rc = regmap_bulk_read(data->regmap, DPS310_COEF_BASE, coef, + sizeof(coef)); + if (rc < 0) + return rc; + + /* + * Calculate temperature calibration coefficients c0 and c1. The + * numbers are 12-bit 2's complement numbers. + */ + c0 = (coef[0] << 4) | (coef[1] >> 4); + data->c0 = sign_extend32(c0, 11); + + c1 = ((coef[1] & GENMASK(3, 0)) << 8) | coef[2]; + data->c1 = sign_extend32(c1, 11); + + /* + * Calculate pressure calibration coefficients. c00 and c10 are 20 bit + * 2's complement numbers, while the rest are 16 bit 2's complement + * numbers. + */ + c00 = (coef[3] << 12) | (coef[4] << 4) | (coef[5] >> 4); + data->c00 = sign_extend32(c00, 19); + + c10 = ((coef[5] & GENMASK(3, 0)) << 16) | (coef[6] << 8) | coef[7]; + data->c10 = sign_extend32(c10, 19); + + c01 = (coef[8] << 8) | coef[9]; + data->c01 = sign_extend32(c01, 15); + + c11 = (coef[10] << 8) | coef[11]; + data->c11 = sign_extend32(c11, 15); + + c20 = (coef[12] << 8) | coef[13]; + data->c20 = sign_extend32(c20, 15); + + c21 = (coef[14] << 8) | coef[15]; + data->c21 = sign_extend32(c21, 15); + + c30 = (coef[16] << 8) | coef[17]; + data->c30 = sign_extend32(c30, 15); + + return 0; +} + +static int dps310_get_pres_precision(struct dps310_data *data) +{ + int rc; + int val; + + rc = regmap_read(data->regmap, DPS310_PRS_CFG, &val); + if (rc < 0) + return rc; + + return BIT(val & GENMASK(2, 0)); +} + +static int dps310_get_temp_precision(struct dps310_data *data) +{ + int rc; + int val; + + rc = regmap_read(data->regmap, DPS310_TMP_CFG, &val); + if (rc < 0) + return rc; + + /* + * Scale factor is bottom 4 bits of the register, but 1111 is + * reserved so just grab bottom three + */ + return BIT(val & GENMASK(2, 0)); +} + +/* Called with lock held */ +static int dps310_set_pres_precision(struct dps310_data *data, int val) +{ + int rc; + u8 shift_en; + + if (val < 0 || val > 128) + return -EINVAL; + + shift_en = val >= 16 ? DPS310_PRS_SHIFT_EN : 0; + rc = regmap_write_bits(data->regmap, DPS310_CFG_REG, + DPS310_PRS_SHIFT_EN, shift_en); + if (rc) + return rc; + + return regmap_update_bits(data->regmap, DPS310_PRS_CFG, + DPS310_PRS_PRC_BITS, ilog2(val)); +} + +/* Called with lock held */ +static int dps310_set_temp_precision(struct dps310_data *data, int val) +{ + int rc; + u8 shift_en; + + if (val < 0 || val > 128) + return -EINVAL; + + shift_en = val >= 16 ? DPS310_TMP_SHIFT_EN : 0; + rc = regmap_write_bits(data->regmap, DPS310_CFG_REG, + DPS310_TMP_SHIFT_EN, shift_en); + if (rc) + return rc; + + return regmap_update_bits(data->regmap, DPS310_TMP_CFG, + DPS310_TMP_PRC_BITS, ilog2(val)); +} + +/* Called with lock held */ +static int dps310_set_pres_samp_freq(struct dps310_data *data, int freq) +{ + u8 val; + + if (freq < 0 || freq > 128) + return -EINVAL; + + val = ilog2(freq) << 4; + + return regmap_update_bits(data->regmap, DPS310_PRS_CFG, + DPS310_PRS_RATE_BITS, val); +} + +/* Called with lock held */ +static int dps310_set_temp_samp_freq(struct dps310_data *data, int freq) +{ + u8 val; + + if (freq < 0 || freq > 128) + return -EINVAL; + + val = ilog2(freq) << 4; + + return regmap_update_bits(data->regmap, DPS310_TMP_CFG, + DPS310_TMP_RATE_BITS, val); +} + +static int dps310_get_pres_samp_freq(struct dps310_data *data) +{ + int rc; + int val; + + rc = regmap_read(data->regmap, DPS310_PRS_CFG, &val); + if (rc < 0) + return rc; + + return BIT((val & DPS310_PRS_RATE_BITS) >> 4); +} + +static int dps310_get_temp_samp_freq(struct dps310_data *data) +{ + int rc; + int val; + + rc = regmap_read(data->regmap, DPS310_TMP_CFG, &val); + if (rc < 0) + return rc; + + return BIT((val & DPS310_TMP_RATE_BITS) >> 4); +} + +static int dps310_get_pres_k(struct dps310_data *data) +{ + int rc = dps310_get_pres_precision(data); + + if (rc < 0) + return rc; + + return scale_factors[ilog2(rc)]; +} + +static int dps310_get_temp_k(struct dps310_data *data) +{ + int rc = dps310_get_temp_precision(data); + + if (rc < 0) + return rc; + + return scale_factors[ilog2(rc)]; +} + +static int dps310_read_pres_raw(struct dps310_data *data) +{ + int rc; + int rate; + int ready; + int timeout; + s32 raw; + u8 val[3]; + + if (mutex_lock_interruptible(&data->lock)) + return -EINTR; + + rate = dps310_get_pres_samp_freq(data); + timeout = DPS310_POLL_TIMEOUT_US(rate); + + /* Poll for sensor readiness; base the timeout upon the sample rate. */ + rc = regmap_read_poll_timeout(data->regmap, DPS310_MEAS_CFG, ready, + ready & DPS310_PRS_RDY, + DPS310_POLL_SLEEP_US(timeout), timeout); + if (rc) + goto done; + + rc = regmap_bulk_read(data->regmap, DPS310_PRS_BASE, val, sizeof(val)); + if (rc < 0) + goto done; + + raw = (val[0] << 16) | (val[1] << 8) | val[2]; + data->pressure_raw = sign_extend32(raw, 23); + +done: + mutex_unlock(&data->lock); + return rc; +} + +/* Called with lock held */ +static int dps310_read_temp_ready(struct dps310_data *data) +{ + int rc; + u8 val[3]; + s32 raw; + + rc = regmap_bulk_read(data->regmap, DPS310_TMP_BASE, val, sizeof(val)); + if (rc < 0) + return rc; + + raw = (val[0] << 16) | (val[1] << 8) | val[2]; + data->temp_raw = sign_extend32(raw, 23); + + return 0; +} + +static int dps310_read_temp_raw(struct dps310_data *data) +{ + int rc; + int rate; + int ready; + int timeout; + + if (mutex_lock_interruptible(&data->lock)) + return -EINTR; + + rate = dps310_get_temp_samp_freq(data); + timeout = DPS310_POLL_TIMEOUT_US(rate); + + /* Poll for sensor readiness; base the timeout upon the sample rate. */ + rc = regmap_read_poll_timeout(data->regmap, DPS310_MEAS_CFG, ready, + ready & DPS310_TMP_RDY, + DPS310_POLL_SLEEP_US(timeout), timeout); + if (rc < 0) + goto done; + + rc = dps310_read_temp_ready(data); + +done: + mutex_unlock(&data->lock); + return rc; +} + +static bool dps310_is_writeable_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case DPS310_PRS_CFG: + case DPS310_TMP_CFG: + case DPS310_MEAS_CFG: + case DPS310_CFG_REG: + case DPS310_RESET: + /* No documentation available on the registers below */ + case 0x0e: + case 0x0f: + case 0x62: + return true; + default: + return false; + } +} + +static bool dps310_is_volatile_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case DPS310_PRS_B0: + case DPS310_PRS_B1: + case DPS310_PRS_B2: + case DPS310_TMP_B0: + case DPS310_TMP_B1: + case DPS310_TMP_B2: + case DPS310_MEAS_CFG: + case 0x32: /* No documentation available on this register */ + return true; + default: + return false; + } +} + +static int dps310_write_raw(struct iio_dev *iio, + struct iio_chan_spec const *chan, int val, + int val2, long mask) +{ + int rc; + struct dps310_data *data = iio_priv(iio); + + if (mutex_lock_interruptible(&data->lock)) + return -EINTR; + + switch (mask) { + case IIO_CHAN_INFO_SAMP_FREQ: + switch (chan->type) { + case IIO_PRESSURE: + rc = dps310_set_pres_samp_freq(data, val); + break; + + case IIO_TEMP: + rc = dps310_set_temp_samp_freq(data, val); + break; + + default: + rc = -EINVAL; + break; + } + break; + + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: + switch (chan->type) { + case IIO_PRESSURE: + rc = dps310_set_pres_precision(data, val); + break; + + case IIO_TEMP: + rc = dps310_set_temp_precision(data, val); + break; + + default: + rc = -EINVAL; + break; + } + break; + + default: + rc = -EINVAL; + break; + } + + mutex_unlock(&data->lock); + return rc; +} + +static int dps310_calculate_pressure(struct dps310_data *data) +{ + int i; + int rc; + int t_ready; + int kpi = dps310_get_pres_k(data); + int kti = dps310_get_temp_k(data); + s64 rem = 0ULL; + s64 pressure = 0ULL; + s64 p; + s64 t; + s64 denoms[7]; + s64 nums[7]; + s64 rems[7]; + s64 kp; + s64 kt; + + if (kpi < 0) + return kpi; + + if (kti < 0) + return kti; + + kp = (s64)kpi; + kt = (s64)kti; + + /* Refresh temp if it's ready, otherwise just use the latest value */ + if (mutex_trylock(&data->lock)) { + rc = regmap_read(data->regmap, DPS310_MEAS_CFG, &t_ready); + if (rc >= 0 && t_ready & DPS310_TMP_RDY) + dps310_read_temp_ready(data); + + mutex_unlock(&data->lock); + } + + p = (s64)data->pressure_raw; + t = (s64)data->temp_raw; + + /* Section 4.9.1 of the DPS310 spec; algebra'd to avoid underflow */ + nums[0] = (s64)data->c00; + denoms[0] = 1LL; + nums[1] = p * (s64)data->c10; + denoms[1] = kp; + nums[2] = p * p * (s64)data->c20; + denoms[2] = kp * kp; + nums[3] = p * p * p * (s64)data->c30; + denoms[3] = kp * kp * kp; + nums[4] = t * (s64)data->c01; + denoms[4] = kt; + nums[5] = t * p * (s64)data->c11; + denoms[5] = kp * kt; + nums[6] = t * p * p * (s64)data->c21; + denoms[6] = kp * kp * kt; + + /* Kernel lacks a div64_s64_rem function; denoms are all positive */ + for (i = 0; i < 7; ++i) { + u64 irem; + + if (nums[i] < 0LL) { + pressure -= div64_u64_rem(-nums[i], denoms[i], &irem); + rems[i] = -irem; + } else { + pressure += div64_u64_rem(nums[i], denoms[i], &irem); + rems[i] = (s64)irem; + } + } + + /* Increase precision and calculate the remainder sum */ + for (i = 0; i < 7; ++i) + rem += div64_s64((s64)rems[i] * 1000000000LL, denoms[i]); + + pressure += div_s64(rem, 1000000000LL); + if (pressure < 0LL) + return -ERANGE; + + return (int)min_t(s64, pressure, INT_MAX); +} + +static int dps310_read_pressure(struct dps310_data *data, int *val, int *val2, + long mask) +{ + int rc; + + switch (mask) { + case IIO_CHAN_INFO_SAMP_FREQ: + rc = dps310_get_pres_samp_freq(data); + if (rc < 0) + return rc; + + *val = rc; + return IIO_VAL_INT; + + case IIO_CHAN_INFO_PROCESSED: + rc = dps310_read_pres_raw(data); + if (rc) + return rc; + + rc = dps310_calculate_pressure(data); + if (rc < 0) + return rc; + + *val = rc; + *val2 = 1000; /* Convert Pa to KPa per IIO ABI */ + return IIO_VAL_FRACTIONAL; + + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: + rc = dps310_get_pres_precision(data); + if (rc < 0) + return rc; + + *val = rc; + return IIO_VAL_INT; + + default: + return -EINVAL; + } +} + +static int dps310_calculate_temp(struct dps310_data *data) +{ + s64 c0; + s64 t; + int kt = dps310_get_temp_k(data); + + if (kt < 0) + return kt; + + /* Obtain inverse-scaled offset */ + c0 = div_s64((s64)kt * (s64)data->c0, 2); + + /* Add the offset to the unscaled temperature */ + t = c0 + ((s64)data->temp_raw * (s64)data->c1); + + /* Convert to milliCelsius and scale the temperature */ + return (int)div_s64(t * 1000LL, kt); +} + +static int dps310_read_temp(struct dps310_data *data, int *val, int *val2, + long mask) +{ + int rc; + + switch (mask) { + case IIO_CHAN_INFO_SAMP_FREQ: + rc = dps310_get_temp_samp_freq(data); + if (rc < 0) + return rc; + + *val = rc; + return IIO_VAL_INT; + + case IIO_CHAN_INFO_PROCESSED: + rc = dps310_read_temp_raw(data); + if (rc) + return rc; + + rc = dps310_calculate_temp(data); + if (rc < 0) + return rc; + + *val = rc; + return IIO_VAL_INT; + + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: + rc = dps310_get_temp_precision(data); + if (rc < 0) + return rc; + + *val = rc; + return IIO_VAL_INT; + + default: + return -EINVAL; + } +} + +static int dps310_read_raw(struct iio_dev *iio, + struct iio_chan_spec const *chan, + int *val, int *val2, long mask) +{ + struct dps310_data *data = iio_priv(iio); + + switch (chan->type) { + case IIO_PRESSURE: + return dps310_read_pressure(data, val, val2, mask); + + case IIO_TEMP: + return dps310_read_temp(data, val, val2, mask); + + default: + return -EINVAL; + } +} + +static void dps310_reset(void *action_data) +{ + struct dps310_data *data = action_data; + + regmap_write(data->regmap, DPS310_RESET, DPS310_RESET_MAGIC); +} + +static const struct regmap_config dps310_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + .writeable_reg = dps310_is_writeable_reg, + .volatile_reg = dps310_is_volatile_reg, + .cache_type = REGCACHE_RBTREE, + .max_register = 0x62, /* No documentation available on this register */ +}; + +static const struct iio_info dps310_info = { + .read_raw = dps310_read_raw, + .write_raw = dps310_write_raw, +}; + +/* + * Some verions of chip will read temperatures in the ~60C range when + * its actually ~20C. This is the manufacturer recommended workaround + * to correct the issue. The registers used below are undocumented. + */ +static int dps310_temp_workaround(struct dps310_data *data) +{ + int rc; + int reg; + + rc = regmap_read(data->regmap, 0x32, ®); + if (rc < 0) + return rc; + + /* + * If bit 1 is set then the device is okay, and the workaround does not + * need to be applied + */ + if (reg & BIT(1)) + return 0; + + rc = regmap_write(data->regmap, 0x0e, 0xA5); + if (rc < 0) + return rc; + + rc = regmap_write(data->regmap, 0x0f, 0x96); + if (rc < 0) + return rc; + + rc = regmap_write(data->regmap, 0x62, 0x02); + if (rc < 0) + return rc; + + rc = regmap_write(data->regmap, 0x0e, 0x00); + if (rc < 0) + return rc; + + return regmap_write(data->regmap, 0x0f, 0x00); +} + +static int dps310_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct dps310_data *data; + struct iio_dev *iio; + int rc, ready; + + iio = devm_iio_device_alloc(&client->dev, sizeof(*data)); + if (!iio) + return -ENOMEM; + + data = iio_priv(iio); + data->client = client; + mutex_init(&data->lock); + + iio->dev.parent = &client->dev; + iio->name = id->name; + iio->channels = dps310_channels; + iio->num_channels = ARRAY_SIZE(dps310_channels); + iio->info = &dps310_info; + iio->modes = INDIO_DIRECT_MODE; + + data->regmap = devm_regmap_init_i2c(client, &dps310_regmap_config); + if (IS_ERR(data->regmap)) + return PTR_ERR(data->regmap); + + /* Register to run the device reset when the device is removed */ + rc = devm_add_action_or_reset(&client->dev, dps310_reset, data); + if (rc) + return rc; + + /* + * Set up pressure sensor in single sample, one measurement per second + * mode + */ + rc = regmap_write(data->regmap, DPS310_PRS_CFG, 0); + + /* + * Set up external (MEMS) temperature sensor in single sample, one + * measurement per second mode + */ + rc = regmap_write(data->regmap, DPS310_TMP_CFG, DPS310_TMP_EXT); + if (rc < 0) + return rc; + + /* Temp and pressure shifts are disabled when PRC <= 8 */ + rc = regmap_write_bits(data->regmap, DPS310_CFG_REG, + DPS310_PRS_SHIFT_EN | DPS310_TMP_SHIFT_EN, 0); + if (rc < 0) + return rc; + + /* MEAS_CFG doesn't update correctly unless first written with 0 */ + rc = regmap_write_bits(data->regmap, DPS310_MEAS_CFG, + DPS310_MEAS_CTRL_BITS, 0); + if (rc < 0) + return rc; + + /* Turn on temperature and pressure measurement in the background */ + rc = regmap_write_bits(data->regmap, DPS310_MEAS_CFG, + DPS310_MEAS_CTRL_BITS, DPS310_PRS_EN | + DPS310_TEMP_EN | DPS310_BACKGROUND); + if (rc < 0) + return rc; + + /* + * Calibration coefficients required for reporting temperature. + * They are available 40ms after the device has started + */ + rc = regmap_read_poll_timeout(data->regmap, DPS310_MEAS_CFG, ready, + ready & DPS310_COEF_RDY, 10000, 40000); + if (rc < 0) + return rc; + + rc = dps310_get_coefs(data); + if (rc < 0) + return rc; + + rc = dps310_temp_workaround(data); + if (rc < 0) + return rc; + + rc = devm_iio_device_register(&client->dev, iio); + if (rc) + return rc; + + i2c_set_clientdata(client, iio); + + return 0; +} + +static const struct i2c_device_id dps310_id[] = { + { DPS310_DEV_NAME, 0 }, + {} +}; +MODULE_DEVICE_TABLE(i2c, dps310_id); + +static struct i2c_driver dps310_driver = { + .driver = { + .name = DPS310_DEV_NAME, + }, + .probe = dps310_probe, + .id_table = dps310_id, +}; +module_i2c_driver(dps310_driver); + +MODULE_AUTHOR("Joel Stanley <joel@jms.id.au>"); +MODULE_DESCRIPTION("Infineon DPS310 pressure and temperature sensor"); +MODULE_LICENSE("GPL v2"); |