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path: root/drivers/gpu/drm/radeon
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Diffstat (limited to 'drivers/gpu/drm/radeon')
-rw-r--r--drivers/gpu/drm/radeon/atombios_crtc.c25
-rw-r--r--drivers/gpu/drm/radeon/atombios_i2c.c2
-rw-r--r--drivers/gpu/drm/radeon/cik.c2
-rw-r--r--drivers/gpu/drm/radeon/r600_reg.h31
-rw-r--r--drivers/gpu/drm/radeon/radeon_object.c4
-rw-r--r--drivers/gpu/drm/radeon/radeon_test.c10
-rw-r--r--drivers/gpu/drm/radeon/si.c2
7 files changed, 62 insertions, 14 deletions
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index efbd5816082d..d75ae17ff3ad 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -1254,6 +1254,16 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
/* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
bypass_lut = true;
break;
+ case DRM_FORMAT_XBGR8888:
+ case DRM_FORMAT_ABGR8888:
+ fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
+ EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
+ fb_swap = (EVERGREEN_GRPH_RED_CROSSBAR(EVERGREEN_GRPH_RED_SEL_B) |
+ EVERGREEN_GRPH_BLUE_CROSSBAR(EVERGREEN_GRPH_BLUE_SEL_R));
+#ifdef __BIG_ENDIAN
+ fb_swap |= EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
+#endif
+ break;
default:
DRM_ERROR("Unsupported screen format %s\n",
drm_get_format_name(target_fb->format->format, &format_name));
@@ -1551,6 +1561,21 @@ static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
/* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
bypass_lut = true;
break;
+ case DRM_FORMAT_XBGR8888:
+ case DRM_FORMAT_ABGR8888:
+ fb_format =
+ AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
+ AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
+ if (rdev->family >= CHIP_R600)
+ fb_swap =
+ (R600_D1GRPH_RED_CROSSBAR(R600_D1GRPH_RED_SEL_B) |
+ R600_D1GRPH_BLUE_CROSSBAR(R600_D1GRPH_BLUE_SEL_R));
+ else /* DCE1 (R5xx) */
+ fb_format |= AVIVO_D1GRPH_SWAP_RB;
+#ifdef __BIG_ENDIAN
+ fb_swap |= R600_D1GRPH_SWAP_ENDIAN_32BIT;
+#endif
+ break;
default:
DRM_ERROR("Unsupported screen format %s\n",
drm_get_format_name(target_fb->format->format, &format_name));
diff --git a/drivers/gpu/drm/radeon/atombios_i2c.c b/drivers/gpu/drm/radeon/atombios_i2c.c
index 4157780585a0..9022e9af11a0 100644
--- a/drivers/gpu/drm/radeon/atombios_i2c.c
+++ b/drivers/gpu/drm/radeon/atombios_i2c.c
@@ -35,7 +35,7 @@
static int radeon_process_i2c_ch(struct radeon_i2c_chan *chan,
u8 slave_addr, u8 flags,
- u8 *buf, u8 num)
+ u8 *buf, int num)
{
struct drm_device *dev = chan->dev;
struct radeon_device *rdev = dev->dev_private;
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index ebce4601a305..ab7b4e2ffcd2 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -9600,7 +9600,7 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev)
tmp |= LC_REDO_EQ;
WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
- mdelay(100);
+ msleep(100);
/* linkctl */
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &tmp16);
diff --git a/drivers/gpu/drm/radeon/r600_reg.h b/drivers/gpu/drm/radeon/r600_reg.h
index 3ef202629e7e..85e85ac3ba4d 100644
--- a/drivers/gpu/drm/radeon/r600_reg.h
+++ b/drivers/gpu/drm/radeon/r600_reg.h
@@ -87,11 +87,32 @@
#define R600_MEDIUM_VID_LOWER_GPIO_CNTL 0x720
#define R600_LOW_VID_LOWER_GPIO_CNTL 0x724
-#define R600_D1GRPH_SWAP_CONTROL 0x610C
-# define R600_D1GRPH_SWAP_ENDIAN_NONE (0 << 0)
-# define R600_D1GRPH_SWAP_ENDIAN_16BIT (1 << 0)
-# define R600_D1GRPH_SWAP_ENDIAN_32BIT (2 << 0)
-# define R600_D1GRPH_SWAP_ENDIAN_64BIT (3 << 0)
+#define R600_D1GRPH_SWAP_CONTROL 0x610C
+# define R600_D1GRPH_ENDIAN_SWAP(x) (((x) & 0x3) << 0)
+# define R600_D1GRPH_SWAP_ENDIAN_NONE 0
+# define R600_D1GRPH_SWAP_ENDIAN_16BIT 1
+# define R600_D1GRPH_SWAP_ENDIAN_32BIT 2
+# define R600_D1GRPH_SWAP_ENDIAN_64BIT 3
+# define R600_D1GRPH_RED_CROSSBAR(x) (((x) & 0x3) << 4)
+# define R600_D1GRPH_RED_SEL_R 0
+# define R600_D1GRPH_RED_SEL_G 1
+# define R600_D1GRPH_RED_SEL_B 2
+# define R600_D1GRPH_RED_SEL_A 3
+# define R600_D1GRPH_GREEN_CROSSBAR(x) (((x) & 0x3) << 6)
+# define R600_D1GRPH_GREEN_SEL_G 0
+# define R600_D1GRPH_GREEN_SEL_B 1
+# define R600_D1GRPH_GREEN_SEL_A 2
+# define R600_D1GRPH_GREEN_SEL_R 3
+# define R600_D1GRPH_BLUE_CROSSBAR(x) (((x) & 0x3) << 8)
+# define R600_D1GRPH_BLUE_SEL_B 0
+# define R600_D1GRPH_BLUE_SEL_A 1
+# define R600_D1GRPH_BLUE_SEL_R 2
+# define R600_D1GRPH_BLUE_SEL_G 3
+# define R600_D1GRPH_ALPHA_CROSSBAR(x) (((x) & 0x3) << 10)
+# define R600_D1GRPH_ALPHA_SEL_A 0
+# define R600_D1GRPH_ALPHA_SEL_R 1
+# define R600_D1GRPH_ALPHA_SEL_G 2
+# define R600_D1GRPH_ALPHA_SEL_B 3
#define R600_HDP_NONSURFACE_BASE 0x2c04
diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c
index ba2fd295697f..92f6d4002eea 100644
--- a/drivers/gpu/drm/radeon/radeon_object.c
+++ b/drivers/gpu/drm/radeon/radeon_object.c
@@ -421,11 +421,13 @@ int radeon_bo_unpin(struct radeon_bo *bo)
int radeon_bo_evict_vram(struct radeon_device *rdev)
{
/* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
- if (0 && (rdev->flags & RADEON_IS_IGP)) {
+#ifndef CONFIG_HIBERNATION
+ if (rdev->flags & RADEON_IS_IGP) {
if (rdev->mc.igp_sideport_enabled == false)
/* Useless to evict on IGP chips */
return 0;
}
+#endif
return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
}
diff --git a/drivers/gpu/drm/radeon/radeon_test.c b/drivers/gpu/drm/radeon/radeon_test.c
index 0c7f228db6e3..701c4a59e3c3 100644
--- a/drivers/gpu/drm/radeon/radeon_test.c
+++ b/drivers/gpu/drm/radeon/radeon_test.c
@@ -348,7 +348,7 @@ void radeon_test_ring_sync(struct radeon_device *rdev,
if (r)
goto out_cleanup;
- mdelay(1000);
+ msleep(1000);
if (radeon_fence_signaled(fence1)) {
DRM_ERROR("Fence 1 signaled without waiting for semaphore.\n");
@@ -369,7 +369,7 @@ void radeon_test_ring_sync(struct radeon_device *rdev,
goto out_cleanup;
}
- mdelay(1000);
+ msleep(1000);
if (radeon_fence_signaled(fence2)) {
DRM_ERROR("Fence 2 signaled without waiting for semaphore.\n");
@@ -442,7 +442,7 @@ static void radeon_test_ring_sync2(struct radeon_device *rdev,
if (r)
goto out_cleanup;
- mdelay(1000);
+ msleep(1000);
if (radeon_fence_signaled(fenceA)) {
DRM_ERROR("Fence A signaled without waiting for semaphore.\n");
@@ -462,7 +462,7 @@ static void radeon_test_ring_sync2(struct radeon_device *rdev,
radeon_ring_unlock_commit(rdev, ringC, false);
for (i = 0; i < 30; ++i) {
- mdelay(100);
+ msleep(100);
sigA = radeon_fence_signaled(fenceA);
sigB = radeon_fence_signaled(fenceB);
if (sigA || sigB)
@@ -487,7 +487,7 @@ static void radeon_test_ring_sync2(struct radeon_device *rdev,
radeon_semaphore_emit_signal(rdev, ringC->idx, semaphore);
radeon_ring_unlock_commit(rdev, ringC, false);
- mdelay(1000);
+ msleep(1000);
r = radeon_fence_wait(fenceA, false);
if (r) {
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 85c604d29235..841bc8bc333d 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -7183,7 +7183,7 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev)
tmp |= LC_REDO_EQ;
WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
- mdelay(100);
+ msleep(100);
/* linkctl */
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &tmp16);
generated by cgit v1.2.3 (git 2.39.0) at 2025-03-08 01:25:32 +0300