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path: root/drivers/gpu/drm/panel/panel-simple.c
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Diffstat (limited to 'drivers/gpu/drm/panel/panel-simple.c')
-rw-r--r--drivers/gpu/drm/panel/panel-simple.c90
1 files changed, 90 insertions, 0 deletions
diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c
index c4566ce8fda7..474fa759e06e 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -638,6 +638,34 @@ static const struct panel_desc auo_g185han01 = {
.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
};
+static const struct display_timing auo_p320hvn03_timings = {
+ .pixelclock = { 106000000, 148500000, 164000000 },
+ .hactive = { 1920, 1920, 1920 },
+ .hfront_porch = { 25, 50, 130 },
+ .hback_porch = { 25, 50, 130 },
+ .hsync_len = { 20, 40, 105 },
+ .vactive = { 1080, 1080, 1080 },
+ .vfront_porch = { 8, 17, 150 },
+ .vback_porch = { 8, 17, 150 },
+ .vsync_len = { 4, 11, 100 },
+};
+
+static const struct panel_desc auo_p320hvn03 = {
+ .timings = &auo_p320hvn03_timings,
+ .num_timings = 1,
+ .bpc = 8,
+ .size = {
+ .width = 698,
+ .height = 393,
+ },
+ .delay = {
+ .prepare = 1,
+ .enable = 450,
+ .unprepare = 500,
+ },
+ .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
+};
+
static const struct drm_display_mode auo_t215hvn01_mode = {
.clock = 148800,
.hdisplay = 1920,
@@ -1322,6 +1350,33 @@ static const struct panel_desc lg_lp129qe = {
},
};
+static const struct display_timing nec_nl12880bc20_05_timing = {
+ .pixelclock = { 67000000, 71000000, 75000000 },
+ .hactive = { 1280, 1280, 1280 },
+ .hfront_porch = { 2, 30, 30 },
+ .hback_porch = { 6, 100, 100 },
+ .hsync_len = { 2, 30, 30 },
+ .vactive = { 800, 800, 800 },
+ .vfront_porch = { 5, 5, 5 },
+ .vback_porch = { 11, 11, 11 },
+ .vsync_len = { 7, 7, 7 },
+};
+
+static const struct panel_desc nec_nl12880bc20_05 = {
+ .timings = &nec_nl12880bc20_05_timing,
+ .num_timings = 1,
+ .bpc = 8,
+ .size = {
+ .width = 261,
+ .height = 163,
+ },
+ .delay = {
+ .enable = 50,
+ .disable = 50,
+ },
+ .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
+};
+
static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
.clock = 10870,
.hdisplay = 480,
@@ -1371,6 +1426,32 @@ static const struct panel_desc netron_dy_e231732 = {
.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
};
+static const struct display_timing nlt_nl192108ac18_02d_timing = {
+ .pixelclock = { 130000000, 148350000, 163000000 },
+ .hactive = { 1920, 1920, 1920 },
+ .hfront_porch = { 80, 100, 100 },
+ .hback_porch = { 100, 120, 120 },
+ .hsync_len = { 50, 60, 60 },
+ .vactive = { 1080, 1080, 1080 },
+ .vfront_porch = { 12, 30, 30 },
+ .vback_porch = { 4, 10, 10 },
+ .vsync_len = { 4, 5, 5 },
+};
+
+static const struct panel_desc nlt_nl192108ac18_02d = {
+ .timings = &nlt_nl192108ac18_02d_timing,
+ .num_timings = 1,
+ .bpc = 8,
+ .size = {
+ .width = 344,
+ .height = 194,
+ },
+ .delay = {
+ .unprepare = 500,
+ },
+ .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
+};
+
static const struct drm_display_mode nvd_9128_mode = {
.clock = 29500,
.hdisplay = 800,
@@ -1888,6 +1969,9 @@ static const struct of_device_id platform_of_match[] = {
.compatible = "auo,g185han01",
.data = &auo_g185han01,
}, {
+ .compatible = "auo,p320hvn03",
+ .data = &auo_p320hvn03,
+ }, {
.compatible = "auo,t215hvn01",
.data = &auo_t215hvn01,
}, {
@@ -1972,12 +2056,18 @@ static const struct of_device_id platform_of_match[] = {
.compatible = "lg,lp129qe",
.data = &lg_lp129qe,
}, {
+ .compatible = "nec,nl12880bc20-05",
+ .data = &nec_nl12880bc20_05,
+ }, {
.compatible = "nec,nl4827hc19-05b",
.data = &nec_nl4827hc19_05b,
}, {
.compatible = "netron-dy,e231732",
.data = &netron_dy_e231732,
}, {
+ .compatible = "nlt,nl192108ac18-02d",
+ .data = &nlt_nl192108ac18_02d,
+ }, {
.compatible = "nvd,9128",
.data = &nvd_9128,
}, {