diff options
Diffstat (limited to 'drivers/gpu/drm/nouveau/nvc0_pm.c')
| -rw-r--r-- | drivers/gpu/drm/nouveau/nvc0_pm.c | 189 |
1 files changed, 189 insertions, 0 deletions
diff --git a/drivers/gpu/drm/nouveau/nvc0_pm.c b/drivers/gpu/drm/nouveau/nvc0_pm.c index ce65f81bb871..7c95c44e2887 100644 --- a/drivers/gpu/drm/nouveau/nvc0_pm.c +++ b/drivers/gpu/drm/nouveau/nvc0_pm.c @@ -164,7 +164,9 @@ struct nvc0_pm_clock { }; struct nvc0_pm_state { + struct nouveau_pm_level *perflvl; struct nvc0_pm_clock eng[16]; + struct nvc0_pm_clock mem; }; static u32 @@ -303,6 +305,48 @@ calc_clk(struct drm_device *dev, int clk, struct nvc0_pm_clock *info, u32 freq) return 0; } +static int +calc_mem(struct drm_device *dev, struct nvc0_pm_clock *info, u32 freq) +{ + struct pll_lims pll; + int N, M, P, ret; + u32 ctrl; + + /* mclk pll input freq comes from another pll, make sure it's on */ + ctrl = nv_rd32(dev, 0x132020); + if (!(ctrl & 0x00000001)) { + /* if not, program it to 567MHz. nfi where this value comes + * from - it looks like it's in the pll limits table for + * 132000 but the binary driver ignores all my attempts to + * change this value. + */ + nv_wr32(dev, 0x137320, 0x00000103); + nv_wr32(dev, 0x137330, 0x81200606); + nv_wait(dev, 0x132020, 0x00010000, 0x00010000); + nv_wr32(dev, 0x132024, 0x0001150f); + nv_mask(dev, 0x132020, 0x00000001, 0x00000001); + nv_wait(dev, 0x137390, 0x00020000, 0x00020000); + nv_mask(dev, 0x132020, 0x00000004, 0x00000004); + } + + /* for the moment, until the clock tree is better understood, use + * pll mode for all clock frequencies + */ + ret = get_pll_limits(dev, 0x132000, &pll); + if (ret == 0) { + pll.refclk = read_pll(dev, 0x132020); + if (pll.refclk) { + ret = nva3_calc_pll(dev, &pll, freq, &N, NULL, &M, &P); + if (ret > 0) { + info->coef = (P << 16) | (N << 8) | M; + return 0; + } + } + } + + return -EINVAL; +} + void * nvc0_pm_clocks_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl) { @@ -335,6 +379,15 @@ nvc0_pm_clocks_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl) return ERR_PTR(ret); } + if (perflvl->memory) { + ret = calc_mem(dev, &info->mem, perflvl->memory); + if (ret) { + kfree(info); + return ERR_PTR(ret); + } + } + + info->perflvl = perflvl; return info; } @@ -375,12 +428,148 @@ prog_clk(struct drm_device *dev, int clk, struct nvc0_pm_clock *info) nv_mask(dev, 0x137250 + (clk * 0x04), 0x00003f3f, info->mdiv); } +static void +mclk_precharge(struct nouveau_mem_exec_func *exec) +{ +} + +static void +mclk_refresh(struct nouveau_mem_exec_func *exec) +{ +} + +static void +mclk_refresh_auto(struct nouveau_mem_exec_func *exec, bool enable) +{ + nv_wr32(exec->dev, 0x10f210, enable ? 0x80000000 : 0x00000000); +} + +static void +mclk_refresh_self(struct nouveau_mem_exec_func *exec, bool enable) +{ +} + +static void +mclk_wait(struct nouveau_mem_exec_func *exec, u32 nsec) +{ + udelay((nsec + 500) / 1000); +} + +static u32 +mclk_mrg(struct nouveau_mem_exec_func *exec, int mr) +{ + struct drm_device *dev = exec->dev; + struct drm_nouveau_private *dev_priv = dev->dev_private; + if (dev_priv->vram_type != NV_MEM_TYPE_GDDR5) { + if (mr <= 1) + return nv_rd32(dev, 0x10f300 + ((mr - 0) * 4)); + return nv_rd32(dev, 0x10f320 + ((mr - 2) * 4)); + } else { + if (mr == 0) + return nv_rd32(dev, 0x10f300 + (mr * 4)); + else + if (mr <= 7) + return nv_rd32(dev, 0x10f32c + (mr * 4)); + return nv_rd32(dev, 0x10f34c); + } +} + +static void +mclk_mrs(struct nouveau_mem_exec_func *exec, int mr, u32 data) +{ + struct drm_device *dev = exec->dev; + struct drm_nouveau_private *dev_priv = dev->dev_private; + if (dev_priv->vram_type != NV_MEM_TYPE_GDDR5) { + if (mr <= 1) { + nv_wr32(dev, 0x10f300 + ((mr - 0) * 4), data); + if (dev_priv->vram_rank_B) + nv_wr32(dev, 0x10f308 + ((mr - 0) * 4), data); + } else + if (mr <= 3) { + nv_wr32(dev, 0x10f320 + ((mr - 2) * 4), data); + if (dev_priv->vram_rank_B) + nv_wr32(dev, 0x10f328 + ((mr - 2) * 4), data); + } + } else { + if (mr == 0) nv_wr32(dev, 0x10f300 + (mr * 4), data); + else if (mr <= 7) nv_wr32(dev, 0x10f32c + (mr * 4), data); + else if (mr == 15) nv_wr32(dev, 0x10f34c, data); + } +} + +static void +mclk_clock_set(struct nouveau_mem_exec_func *exec) +{ + struct nvc0_pm_state *info = exec->priv; + struct drm_device *dev = exec->dev; + u32 ctrl = nv_rd32(dev, 0x132000); + + nv_wr32(dev, 0x137360, 0x00000001); + nv_wr32(dev, 0x137370, 0x00000000); + nv_wr32(dev, 0x137380, 0x00000000); + if (ctrl & 0x00000001) + nv_wr32(dev, 0x132000, (ctrl &= ~0x00000001)); + + nv_wr32(dev, 0x132004, info->mem.coef); + nv_wr32(dev, 0x132000, (ctrl |= 0x00000001)); + nv_wait(dev, 0x137390, 0x00000002, 0x00000002); + nv_wr32(dev, 0x132018, 0x00005000); + + nv_wr32(dev, 0x137370, 0x00000001); + nv_wr32(dev, 0x137380, 0x00000001); + nv_wr32(dev, 0x137360, 0x00000000); +} + +static void +mclk_timing_set(struct nouveau_mem_exec_func *exec) +{ + struct nvc0_pm_state *info = exec->priv; + struct nouveau_pm_level *perflvl = info->perflvl; + int i; + + for (i = 0; i < 5; i++) + nv_wr32(exec->dev, 0x10f290 + (i * 4), perflvl->timing.reg[i]); +} + +static void +prog_mem(struct drm_device *dev, struct nvc0_pm_state *info) +{ + struct drm_nouveau_private *dev_priv = dev->dev_private; + struct nouveau_mem_exec_func exec = { + .dev = dev, + .precharge = mclk_precharge, + .refresh = mclk_refresh, + .refresh_auto = mclk_refresh_auto, + .refresh_self = mclk_refresh_self, + .wait = mclk_wait, + .mrg = mclk_mrg, + .mrs = mclk_mrs, + .clock_set = mclk_clock_set, + .timing_set = mclk_timing_set, + .priv = info + }; + + if (dev_priv->chipset < 0xd0) + nv_wr32(dev, 0x611200, 0x00003300); + else + nv_wr32(dev, 0x62c000, 0x03030000); + + nouveau_mem_exec(&exec, info->perflvl); + + if (dev_priv->chipset < 0xd0) + nv_wr32(dev, 0x611200, 0x00003300); + else + nv_wr32(dev, 0x62c000, 0x03030300); +} int nvc0_pm_clocks_set(struct drm_device *dev, void *data) { struct nvc0_pm_state *info = data; int i; + if (info->mem.coef) + prog_mem(dev, info); + for (i = 0; i < 16; i++) { if (!info->eng[i].freq) continue; |