diff options
Diffstat (limited to 'drivers/gpu/drm/img/img-rogue/include/rgx_mips.h')
| -rw-r--r-- | drivers/gpu/drm/img/img-rogue/include/rgx_mips.h | 82 |
1 files changed, 41 insertions, 41 deletions
diff --git a/drivers/gpu/drm/img/img-rogue/include/rgx_mips.h b/drivers/gpu/drm/img/img-rogue/include/rgx_mips.h index 4c358517b00f..c2f381882f74 100644 --- a/drivers/gpu/drm/img/img-rogue/include/rgx_mips.h +++ b/drivers/gpu/drm/img/img-rogue/include/rgx_mips.h @@ -72,7 +72,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /* Total number of TLB entries */ #define RGXMIPSFW_NUMBER_OF_TLB_ENTRIES (16) /* "Uncached" caching policy */ -#define RGXMIPSFW_UNCACHED_CACHE_POLICY (0X00000002) +#define RGXMIPSFW_UNCACHED_CACHE_POLICY (0X00000002U) /* "Write-back write-allocate" caching policy */ #define RGXMIPSFW_WRITEBACK_CACHE_POLICY (0X00000003) /* "Write-through no write-allocate" caching policy */ @@ -91,11 +91,11 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define RGXMIPSFW_ENTRYLO_READ_INHIBIT_SHIFT (31U) #define RGXMIPSFW_ENTRYLO_READ_INHIBIT_CLRMSK (0X7FFFFFFF) -#define RGXMIPSFW_ENTRYLO_READ_INHIBIT_EN (0X80000000) +#define RGXMIPSFW_ENTRYLO_READ_INHIBIT_EN (0X80000000U) #define RGXMIPSFW_ENTRYLO_EXEC_INHIBIT_SHIFT (30U) #define RGXMIPSFW_ENTRYLO_EXEC_INHIBIT_CLRMSK (0XBFFFFFFF) -#define RGXMIPSFW_ENTRYLO_EXEC_INHIBIT_EN (0X40000000) +#define RGXMIPSFW_ENTRYLO_EXEC_INHIBIT_EN (0X40000000U) /* Page Frame Number */ #define RGXMIPSFW_ENTRYLO_PFN_SHIFT (6) @@ -104,25 +104,25 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define RGXMIPSFW_ENTRYLO_PFN_MASK (0x03FFFFC0) #define RGXMIPSFW_ENTRYLO_PFN_SIZE (20) /* Mask used for the MIPS Page Table in case of physical bus on more than 32 bit */ -#define RGXMIPSFW_ENTRYLO_PFN_MASK_ABOVE_32BIT (0x3FFFFFC0) +#define RGXMIPSFW_ENTRYLO_PFN_MASK_ABOVE_32BIT (0x3FFFFFC0U) #define RGXMIPSFW_ENTRYLO_PFN_SIZE_ABOVE_32BIT (24) #define RGXMIPSFW_ADDR_TO_ENTRYLO_PFN_RSHIFT (RGXMIPSFW_ENTRYLO_PFN_ALIGNSHIFT - \ RGXMIPSFW_ENTRYLO_PFN_SHIFT) #define RGXMIPSFW_ENTRYLO_CACHE_POLICY_SHIFT (3U) -#define RGXMIPSFW_ENTRYLO_CACHE_POLICY_CLRMSK (0XFFFFFFC7) +#define RGXMIPSFW_ENTRYLO_CACHE_POLICY_CLRMSK (0XFFFFFFC7U) #define RGXMIPSFW_ENTRYLO_DIRTY_SHIFT (2U) #define RGXMIPSFW_ENTRYLO_DIRTY_CLRMSK (0XFFFFFFFB) -#define RGXMIPSFW_ENTRYLO_DIRTY_EN (0X00000004) +#define RGXMIPSFW_ENTRYLO_DIRTY_EN (0X00000004U) #define RGXMIPSFW_ENTRYLO_VALID_SHIFT (1U) #define RGXMIPSFW_ENTRYLO_VALID_CLRMSK (0XFFFFFFFD) -#define RGXMIPSFW_ENTRYLO_VALID_EN (0X00000002) +#define RGXMIPSFW_ENTRYLO_VALID_EN (0X00000002U) #define RGXMIPSFW_ENTRYLO_GLOBAL_SHIFT (0U) #define RGXMIPSFW_ENTRYLO_GLOBAL_CLRMSK (0XFFFFFFFE) -#define RGXMIPSFW_ENTRYLO_GLOBAL_EN (0X00000001) +#define RGXMIPSFW_ENTRYLO_GLOBAL_EN (0X00000001U) #define RGXMIPSFW_ENTRYLO_DVG (RGXMIPSFW_ENTRYLO_DIRTY_EN | \ RGXMIPSFW_ENTRYLO_VALID_EN | \ @@ -158,14 +158,14 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #define RGXMIPSFW_TRAMPOLINE_LOG2_NUMPAGES (2) -#define RGXMIPSFW_TRAMPOLINE_NUMPAGES (1 << RGXMIPSFW_TRAMPOLINE_LOG2_NUMPAGES) +#define RGXMIPSFW_TRAMPOLINE_NUMPAGES (1U << RGXMIPSFW_TRAMPOLINE_LOG2_NUMPAGES) #define RGXMIPSFW_TRAMPOLINE_SIZE (RGXMIPSFW_TRAMPOLINE_NUMPAGES << RGXMIPSFW_LOG2_PAGE_SIZE_4K) #define RGXMIPSFW_TRAMPOLINE_LOG2_SEGMENT_SIZE (RGXMIPSFW_TRAMPOLINE_LOG2_NUMPAGES + RGXMIPSFW_LOG2_PAGE_SIZE_4K) #define RGXMIPSFW_TRAMPOLINE_TARGET_PHYS_ADDR (RGXMIPSFW_BOOT_REMAP_PHYS_ADDR_IN) #define RGXMIPSFW_TRAMPOLINE_OFFSET(a) (a - RGXMIPSFW_BOOT_REMAP_PHYS_ADDR_IN) -#define RGXMIPSFW_SENSITIVE_ADDR(a) (RGXMIPSFW_BOOT_REMAP_PHYS_ADDR_IN == (~((1<<RGXMIPSFW_TRAMPOLINE_LOG2_SEGMENT_SIZE)-1) & a)) +#define RGXMIPSFW_SENSITIVE_ADDR(a) (RGXMIPSFW_BOOT_REMAP_PHYS_ADDR_IN == (~((1UL << RGXMIPSFW_TRAMPOLINE_LOG2_SEGMENT_SIZE)-1U) & a)) /* * Firmware virtual layout and remap configuration @@ -183,20 +183,20 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /* Boot remap setup */ #define RGXMIPSFW_BOOT_REMAP_VIRTUAL_BASE (0xBFC00000) -#define RGXMIPSFW_BOOT_REMAP_PHYS_ADDR_IN (0x1FC00000) +#define RGXMIPSFW_BOOT_REMAP_PHYS_ADDR_IN (0x1FC00000U) #define RGXMIPSFW_BOOT_REMAP_LOG2_SEGMENT_SIZE (12) #define RGXMIPSFW_BOOT_NMI_CODE_VIRTUAL_BASE (RGXMIPSFW_BOOT_REMAP_VIRTUAL_BASE) /* Data remap setup */ #define RGXMIPSFW_DATA_REMAP_VIRTUAL_BASE (0xBFC01000) #define RGXMIPSFW_DATA_CACHED_REMAP_VIRTUAL_BASE (0x9FC01000) -#define RGXMIPSFW_DATA_REMAP_PHYS_ADDR_IN (0x1FC01000) +#define RGXMIPSFW_DATA_REMAP_PHYS_ADDR_IN (0x1FC01000U) #define RGXMIPSFW_DATA_REMAP_LOG2_SEGMENT_SIZE (12) #define RGXMIPSFW_BOOT_NMI_DATA_VIRTUAL_BASE (RGXMIPSFW_DATA_REMAP_VIRTUAL_BASE) /* Code remap setup */ #define RGXMIPSFW_CODE_REMAP_VIRTUAL_BASE (0x9FC02000) -#define RGXMIPSFW_CODE_REMAP_PHYS_ADDR_IN (0x1FC02000) +#define RGXMIPSFW_CODE_REMAP_PHYS_ADDR_IN (0x1FC02000U) #define RGXMIPSFW_CODE_REMAP_LOG2_SEGMENT_SIZE (12) #define RGXMIPSFW_EXCEPTIONS_VIRTUAL_BASE (RGXMIPSFW_CODE_REMAP_VIRTUAL_BASE) @@ -211,7 +211,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ /* Bootloader configuration offset (where RGXMIPSFW_BOOT_DATA lives) * within the bootloader/NMI data page */ -#define RGXMIPSFW_BOOTLDR_CONF_OFFSET (0x0) +#define RGXMIPSFW_BOOTLDR_CONF_OFFSET (0x0U) /* @@ -241,7 +241,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /* The things that follow are excluded when compiling assembly sources */ #if !defined(RGXMIPSFW_ASSEMBLY_CODE) #include "img_types.h" -#include "rgxdefs_km.h" +#include "km/rgxdefs_km.h" typedef struct { @@ -292,40 +292,40 @@ typedef struct #define RGXMIPSFW_C0_NBHWIRQ 8 /* Macros to decode C0_Cause register */ -#define RGXMIPSFW_C0_CAUSE_EXCCODE(CAUSE) (((CAUSE) & 0x7c) >> 2) +#define RGXMIPSFW_C0_CAUSE_EXCCODE(CAUSE) (((CAUSE) & 0x7cU) >> 2U) #define RGXMIPSFW_C0_CAUSE_EXCCODE_FWERROR 9 /* Use only when Coprocessor Unusable exception */ -#define RGXMIPSFW_C0_CAUSE_UNUSABLE_UNIT(CAUSE) (((CAUSE) >> 28) & 0x3) +#define RGXMIPSFW_C0_CAUSE_UNUSABLE_UNIT(CAUSE) (((CAUSE) >> 28U) & 0x3U) #define RGXMIPSFW_C0_CAUSE_PENDING_HWIRQ(CAUSE) (((CAUSE) & 0x3fc00) >> 10) -#define RGXMIPSFW_C0_CAUSE_FDCIPENDING (1 << 21) -#define RGXMIPSFW_C0_CAUSE_IV (1 << 23) -#define RGXMIPSFW_C0_CAUSE_IC (1 << 25) -#define RGXMIPSFW_C0_CAUSE_PCIPENDING (1 << 26) -#define RGXMIPSFW_C0_CAUSE_TIPENDING (1 << 30) -#define RGXMIPSFW_C0_CAUSE_BRANCH_DELAY (1 << 31) +#define RGXMIPSFW_C0_CAUSE_FDCIPENDING (1UL << 21) +#define RGXMIPSFW_C0_CAUSE_IV (1UL << 23) +#define RGXMIPSFW_C0_CAUSE_IC (1UL << 25) +#define RGXMIPSFW_C0_CAUSE_PCIPENDING (1UL << 26) +#define RGXMIPSFW_C0_CAUSE_TIPENDING (1UL << 30) +#define RGXMIPSFW_C0_CAUSE_BRANCH_DELAY (1UL << 31) /* Macros to decode C0_Debug register */ -#define RGXMIPSFW_C0_DEBUG_EXCCODE(DEBUG) (((DEBUG) >> 10) & 0x1f) -#define RGXMIPSFW_C0_DEBUG_DSS (1 << 0) -#define RGXMIPSFW_C0_DEBUG_DBP (1 << 1) -#define RGXMIPSFW_C0_DEBUG_DDBL (1 << 2) -#define RGXMIPSFW_C0_DEBUG_DDBS (1 << 3) -#define RGXMIPSFW_C0_DEBUG_DIB (1 << 4) -#define RGXMIPSFW_C0_DEBUG_DINT (1 << 5) -#define RGXMIPSFW_C0_DEBUG_DIBIMPR (1 << 6) -#define RGXMIPSFW_C0_DEBUG_DDBLIMPR (1 << 18) -#define RGXMIPSFW_C0_DEBUG_DDBSIMPR (1 << 19) -#define RGXMIPSFW_C0_DEBUG_IEXI (1 << 20) -#define RGXMIPSFW_C0_DEBUG_DBUSEP (1 << 21) -#define RGXMIPSFW_C0_DEBUG_CACHEEP (1 << 22) -#define RGXMIPSFW_C0_DEBUG_MCHECKP (1 << 23) -#define RGXMIPSFW_C0_DEBUG_IBUSEP (1 << 24) -#define RGXMIPSFW_C0_DEBUG_DM (1 << 30) -#define RGXMIPSFW_C0_DEBUG_DBD (1 << 31) +#define RGXMIPSFW_C0_DEBUG_EXCCODE(DEBUG) (((DEBUG) >> 10U) & 0x1fU) +#define RGXMIPSFW_C0_DEBUG_DSS (1UL << 0) +#define RGXMIPSFW_C0_DEBUG_DBP (1UL << 1) +#define RGXMIPSFW_C0_DEBUG_DDBL (1UL << 2) +#define RGXMIPSFW_C0_DEBUG_DDBS (1UL << 3) +#define RGXMIPSFW_C0_DEBUG_DIB (1UL << 4) +#define RGXMIPSFW_C0_DEBUG_DINT (1UL << 5) +#define RGXMIPSFW_C0_DEBUG_DIBIMPR (1UL << 6) +#define RGXMIPSFW_C0_DEBUG_DDBLIMPR (1UL << 18) +#define RGXMIPSFW_C0_DEBUG_DDBSIMPR (1UL << 19) +#define RGXMIPSFW_C0_DEBUG_IEXI (1UL << 20) +#define RGXMIPSFW_C0_DEBUG_DBUSEP (1UL << 21) +#define RGXMIPSFW_C0_DEBUG_CACHEEP (1UL << 22) +#define RGXMIPSFW_C0_DEBUG_MCHECKP (1UL << 23) +#define RGXMIPSFW_C0_DEBUG_IBUSEP (1UL << 24) +#define RGXMIPSFW_C0_DEBUG_DM (1UL << 30) +#define RGXMIPSFW_C0_DEBUG_DBD (1UL << 31) /* Macros to decode TLB entries */ #define RGXMIPSFW_TLB_GET_MASK(PAGE_MASK) (((PAGE_MASK) >> 13) & 0XFFFFU) -#define RGXMIPSFW_TLB_GET_PAGE_SIZE(PAGE_MASK) ((((PAGE_MASK) | 0x1FFF) + 1) >> 11) /* page size in KB */ +#define RGXMIPSFW_TLB_GET_PAGE_SIZE(PAGE_MASK) ((((PAGE_MASK) | 0x1FFFU) + 1U) >> 11U) /* page size in KB */ #define RGXMIPSFW_TLB_GET_PAGE_MASK(PAGE_SIZE) ((((PAGE_SIZE) << 11) - 1) & ~0x7FF) /* page size in KB */ #define RGXMIPSFW_TLB_GET_VPN2(ENTRY_HI) ((ENTRY_HI) >> 13) #define RGXMIPSFW_TLB_GET_COHERENCY(ENTRY_LO) (((ENTRY_LO) >> 3) & 0x7U) |