diff options
Diffstat (limited to 'drivers/clk/qcom/gcc-sm8350.c')
| -rw-r--r-- | drivers/clk/qcom/gcc-sm8350.c | 15 |
1 files changed, 0 insertions, 15 deletions
diff --git a/drivers/clk/qcom/gcc-sm8350.c b/drivers/clk/qcom/gcc-sm8350.c index c3731f96c8e6..af4a1ea28421 100644 --- a/drivers/clk/qcom/gcc-sm8350.c +++ b/drivers/clk/qcom/gcc-sm8350.c @@ -22,7 +22,6 @@ enum { P_BI_TCXO, - P_CORE_BI_PLL_TEST_SE, P_GCC_GPLL0_OUT_EVEN, P_GCC_GPLL0_OUT_MAIN, P_GCC_GPLL4_OUT_MAIN, @@ -119,14 +118,12 @@ static const struct parent_map gcc_parent_map_0[] = { { P_BI_TCXO, 0 }, { P_GCC_GPLL0_OUT_MAIN, 1 }, { P_GCC_GPLL0_OUT_EVEN, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const struct clk_parent_data gcc_parent_data_0[] = { { .fw_name = "bi_tcxo" }, { .hw = &gcc_gpll0.clkr.hw }, { .hw = &gcc_gpll0_out_even.clkr.hw }, - { .fw_name = "core_bi_pll_test_se" }, }; static const struct parent_map gcc_parent_map_1[] = { @@ -134,7 +131,6 @@ static const struct parent_map gcc_parent_map_1[] = { { P_GCC_GPLL0_OUT_MAIN, 1 }, { P_SLEEP_CLK, 5 }, { P_GCC_GPLL0_OUT_EVEN, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const struct clk_parent_data gcc_parent_data_1[] = { @@ -142,29 +138,24 @@ static const struct clk_parent_data gcc_parent_data_1[] = { { .hw = &gcc_gpll0.clkr.hw }, { .fw_name = "sleep_clk" }, { .hw = &gcc_gpll0_out_even.clkr.hw }, - { .fw_name = "core_bi_pll_test_se" }, }; static const struct parent_map gcc_parent_map_2[] = { { P_BI_TCXO, 0 }, { P_SLEEP_CLK, 5 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const struct clk_parent_data gcc_parent_data_2[] = { { .fw_name = "bi_tcxo" }, { .fw_name = "sleep_clk" }, - { .fw_name = "core_bi_pll_test_se" }, }; static const struct parent_map gcc_parent_map_3[] = { { P_BI_TCXO, 0 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const struct clk_parent_data gcc_parent_data_3[] = { { .fw_name = "bi_tcxo" }, - { .fw_name = "core_bi_pll_test_se" }, }; static const struct parent_map gcc_parent_map_4[] = { @@ -193,7 +184,6 @@ static const struct parent_map gcc_parent_map_6[] = { { P_GCC_GPLL9_OUT_MAIN, 2 }, { P_GCC_GPLL4_OUT_MAIN, 5 }, { P_GCC_GPLL0_OUT_EVEN, 6 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const struct clk_parent_data gcc_parent_data_6[] = { @@ -202,7 +192,6 @@ static const struct clk_parent_data gcc_parent_data_6[] = { { .hw = &gcc_gpll9.clkr.hw }, { .hw = &gcc_gpll4.clkr.hw }, { .hw = &gcc_gpll0_out_even.clkr.hw }, - { .fw_name = "core_bi_pll_test_se" }, }; static const struct parent_map gcc_parent_map_7[] = { @@ -267,25 +256,21 @@ static const struct clk_parent_data gcc_parent_data_12[] = { static const struct parent_map gcc_parent_map_13[] = { { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 }, - { P_CORE_BI_PLL_TEST_SE, 1 }, { P_BI_TCXO, 2 }, }; static const struct clk_parent_data gcc_parent_data_13[] = { { .fw_name = "usb3_phy_wrapper_gcc_usb30_pipe_clk" }, - { .fw_name = "core_bi_pll_test_se" }, { .fw_name = "bi_tcxo" }, }; static const struct parent_map gcc_parent_map_14[] = { { P_USB3_UNI_PHY_SEC_GCC_USB30_PIPE_CLK, 0 }, - { P_CORE_BI_PLL_TEST_SE, 1 }, { P_BI_TCXO, 2 }, }; static const struct clk_parent_data gcc_parent_data_14[] = { { .fw_name = "usb3_uni_phy_sec_gcc_usb30_pipe_clk" }, - { .fw_name = "core_bi_pll_test_se" }, { .fw_name = "bi_tcxo" }, }; |