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path: root/drivers/clk/qcom/gcc-sdx55.c
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Diffstat (limited to 'drivers/clk/qcom/gcc-sdx55.c')
-rw-r--r--drivers/clk/qcom/gcc-sdx55.c64
1 files changed, 26 insertions, 38 deletions
diff --git a/drivers/clk/qcom/gcc-sdx55.c b/drivers/clk/qcom/gcc-sdx55.c
index 4fca19006a77..d5e17122698c 100644
--- a/drivers/clk/qcom/gcc-sdx55.c
+++ b/drivers/clk/qcom/gcc-sdx55.c
@@ -22,7 +22,6 @@
enum {
P_BI_TCXO,
- P_CORE_BI_PLL_TEST_SE,
P_GPLL0_OUT_EVEN,
P_GPLL0_OUT_MAIN,
P_GPLL4_OUT_EVEN,
@@ -137,21 +136,18 @@ static const struct parent_map gcc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL0_OUT_EVEN, 6 },
- { P_CORE_BI_PLL_TEST_SE, 7 },
};
static const struct clk_parent_data gcc_parents_0[] = {
{ .fw_name = "bi_tcxo" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_out_even.clkr.hw },
- { .fw_name = "core_bi_pll_test_se" },
};
static const struct clk_parent_data gcc_parents_0_ao[] = {
{ .fw_name = "bi_tcxo_ao" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll0_out_even.clkr.hw },
- { .fw_name = "core_bi_pll_test_se" },
};
static const struct parent_map gcc_parent_map_2[] = {
@@ -160,7 +156,6 @@ static const struct parent_map gcc_parent_map_2[] = {
{ P_GPLL4_OUT_EVEN, 2 },
{ P_GPLL5_OUT_MAIN, 5 },
{ P_GPLL0_OUT_EVEN, 6 },
- { P_CORE_BI_PLL_TEST_SE, 7 },
};
static const struct clk_parent_data gcc_parents_2[] = {
@@ -169,7 +164,6 @@ static const struct clk_parent_data gcc_parents_2[] = {
{ .hw = &gpll4_out_even.clkr.hw },
{ .hw = &gpll5.clkr.hw },
{ .hw = &gpll0_out_even.clkr.hw },
- { .fw_name = "core_bi_pll_test_se" },
};
static const struct parent_map gcc_parent_map_3[] = {
@@ -177,7 +171,6 @@ static const struct parent_map gcc_parent_map_3[] = {
{ P_GPLL0_OUT_MAIN, 1 },
{ P_SLEEP_CLK, 5 },
{ P_GPLL0_OUT_EVEN, 6 },
- { P_CORE_BI_PLL_TEST_SE, 7 },
};
static const struct clk_parent_data gcc_parents_3[] = {
@@ -185,19 +178,16 @@ static const struct clk_parent_data gcc_parents_3[] = {
{ .hw = &gpll0.clkr.hw },
{ .fw_name = "sleep_clk", .name = "sleep_clk" },
{ .hw = &gpll0_out_even.clkr.hw },
- { .fw_name = "core_bi_pll_test_se" },
};
static const struct parent_map gcc_parent_map_4[] = {
{ P_BI_TCXO, 0 },
{ P_SLEEP_CLK, 5 },
- { P_CORE_BI_PLL_TEST_SE, 7 },
};
static const struct clk_parent_data gcc_parents_4[] = {
{ .fw_name = "bi_tcxo" },
{ .fw_name = "sleep_clk", .name = "sleep_clk" },
- { .fw_name = "core_bi_pll_test_se" },
};
static const struct parent_map gcc_parent_map_5[] = {
@@ -205,7 +195,6 @@ static const struct parent_map gcc_parent_map_5[] = {
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL4_OUT_EVEN, 2 },
{ P_GPLL0_OUT_EVEN, 6 },
- { P_CORE_BI_PLL_TEST_SE, 7 },
};
static const struct clk_parent_data gcc_parents_5[] = {
@@ -213,7 +202,6 @@ static const struct clk_parent_data gcc_parents_5[] = {
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll4_out_even.clkr.hw },
{ .hw = &gpll0_out_even.clkr.hw },
- { .fw_name = "core_bi_pll_test_se" },
};
static const struct freq_tbl ftbl_gcc_blsp1_qup1_i2c_apps_clk_src[] = {
@@ -232,7 +220,7 @@ static struct clk_rcg2 gcc_blsp1_qup1_i2c_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup1_i2c_apps_clk_src",
.parent_data = gcc_parents_0,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(gcc_parents_0),
.ops = &clk_rcg2_ops,
},
};
@@ -258,7 +246,7 @@ static struct clk_rcg2 gcc_blsp1_qup1_spi_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup1_spi_apps_clk_src",
.parent_data = gcc_parents_0,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(gcc_parents_0),
.ops = &clk_rcg2_ops,
},
};
@@ -272,7 +260,7 @@ static struct clk_rcg2 gcc_blsp1_qup2_i2c_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup2_i2c_apps_clk_src",
.parent_data = gcc_parents_0,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(gcc_parents_0),
.ops = &clk_rcg2_ops,
},
};
@@ -286,7 +274,7 @@ static struct clk_rcg2 gcc_blsp1_qup2_spi_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup2_spi_apps_clk_src",
.parent_data = gcc_parents_0,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(gcc_parents_0),
.ops = &clk_rcg2_ops,
},
};
@@ -300,7 +288,7 @@ static struct clk_rcg2 gcc_blsp1_qup3_i2c_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup3_i2c_apps_clk_src",
.parent_data = gcc_parents_0,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(gcc_parents_0),
.ops = &clk_rcg2_ops,
},
};
@@ -314,7 +302,7 @@ static struct clk_rcg2 gcc_blsp1_qup3_spi_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup3_spi_apps_clk_src",
.parent_data = gcc_parents_0,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(gcc_parents_0),
.ops = &clk_rcg2_ops,
},
};
@@ -328,7 +316,7 @@ static struct clk_rcg2 gcc_blsp1_qup4_i2c_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup4_i2c_apps_clk_src",
.parent_data = gcc_parents_0,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(gcc_parents_0),
.ops = &clk_rcg2_ops,
},
};
@@ -342,7 +330,7 @@ static struct clk_rcg2 gcc_blsp1_qup4_spi_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup4_spi_apps_clk_src",
.parent_data = gcc_parents_0,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(gcc_parents_0),
.ops = &clk_rcg2_ops,
},
};
@@ -386,7 +374,7 @@ static struct clk_rcg2 gcc_blsp1_uart1_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart1_apps_clk_src",
.parent_data = gcc_parents_0,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(gcc_parents_0),
.ops = &clk_rcg2_ops,
},
};
@@ -400,7 +388,7 @@ static struct clk_rcg2 gcc_blsp1_uart2_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart2_apps_clk_src",
.parent_data = gcc_parents_0,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(gcc_parents_0),
.ops = &clk_rcg2_ops,
},
};
@@ -414,7 +402,7 @@ static struct clk_rcg2 gcc_blsp1_uart3_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart3_apps_clk_src",
.parent_data = gcc_parents_0,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(gcc_parents_0),
.ops = &clk_rcg2_ops,
},
};
@@ -428,7 +416,7 @@ static struct clk_rcg2 gcc_blsp1_uart4_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart4_apps_clk_src",
.parent_data = gcc_parents_0,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(gcc_parents_0),
.ops = &clk_rcg2_ops,
},
};
@@ -450,7 +438,7 @@ static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_cpuss_ahb_clk_src",
.parent_data = gcc_parents_0_ao,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(gcc_parents_0_ao),
.ops = &clk_rcg2_ops,
},
};
@@ -469,7 +457,7 @@ static struct clk_rcg2 gcc_cpuss_rbcpr_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_cpuss_rbcpr_clk_src",
.parent_data = gcc_parents_0_ao,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(gcc_parents_0_ao),
.ops = &clk_rcg2_ops,
},
};
@@ -493,7 +481,7 @@ static struct clk_rcg2 gcc_emac_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_emac_clk_src",
.parent_data = gcc_parents_5,
- .num_parents = 5,
+ .num_parents = ARRAY_SIZE(gcc_parents_5),
.ops = &clk_rcg2_ops,
},
};
@@ -514,7 +502,7 @@ static struct clk_rcg2 gcc_emac_ptp_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_emac_ptp_clk_src",
.parent_data = gcc_parents_2,
- .num_parents = 6,
+ .num_parents = ARRAY_SIZE(gcc_parents_2),
.ops = &clk_rcg2_ops,
},
};
@@ -537,7 +525,7 @@ static struct clk_rcg2 gcc_gp1_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_gp1_clk_src",
.parent_data = gcc_parents_3,
- .num_parents = 5,
+ .num_parents = ARRAY_SIZE(gcc_parents_3),
.ops = &clk_rcg2_ops,
},
};
@@ -551,7 +539,7 @@ static struct clk_rcg2 gcc_gp2_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_gp2_clk_src",
.parent_data = gcc_parents_3,
- .num_parents = 5,
+ .num_parents = ARRAY_SIZE(gcc_parents_3),
.ops = &clk_rcg2_ops,
},
};
@@ -565,7 +553,7 @@ static struct clk_rcg2 gcc_gp3_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_gp3_clk_src",
.parent_data = gcc_parents_3,
- .num_parents = 5,
+ .num_parents = ARRAY_SIZE(gcc_parents_3),
.ops = &clk_rcg2_ops,
},
};
@@ -579,7 +567,7 @@ static struct clk_rcg2 gcc_pcie_aux_phy_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_aux_phy_clk_src",
.parent_data = gcc_parents_4,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_parents_4),
.ops = &clk_rcg2_ops,
},
};
@@ -598,7 +586,7 @@ static struct clk_rcg2 gcc_pcie_rchng_phy_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_rchng_phy_clk_src",
.parent_data = gcc_parents_3,
- .num_parents = 5,
+ .num_parents = ARRAY_SIZE(gcc_parents_3),
.ops = &clk_rcg2_ops,
},
};
@@ -619,7 +607,7 @@ static struct clk_rcg2 gcc_pdm2_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_pdm2_clk_src",
.parent_data = gcc_parents_0,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(gcc_parents_0),
.ops = &clk_rcg2_ops,
},
};
@@ -633,7 +621,7 @@ static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_apps_clk_src",
.parent_data = gcc_parents_0,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(gcc_parents_0),
.ops = &clk_rcg2_ops,
},
};
@@ -652,7 +640,7 @@ static struct clk_rcg2 gcc_usb30_master_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_master_clk_src",
.parent_data = gcc_parents_0,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(gcc_parents_0),
.ops = &clk_rcg2_ops,
},
};
@@ -671,7 +659,7 @@ static struct clk_rcg2 gcc_usb30_mock_utmi_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_mock_utmi_clk_src",
.parent_data = gcc_parents_0,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(gcc_parents_0),
.ops = &clk_rcg2_ops,
},
};
@@ -691,7 +679,7 @@ static struct clk_rcg2 gcc_usb3_phy_aux_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_phy_aux_clk_src",
.parent_data = gcc_parents_4,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_parents_4),
.ops = &clk_rcg2_ops,
},
};
generated by cgit v1.2.3 (git 2.39.0) at 2024-11-22 07:38:13 +0300