diff options
Diffstat (limited to 'drivers/acpi/cppc_acpi.c')
| -rw-r--r-- | drivers/acpi/cppc_acpi.c | 96 | 
1 files changed, 44 insertions, 52 deletions
| diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index 69057fcd2c04..a4d4eebba1da 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -33,7 +33,6 @@  #define pr_fmt(fmt)	"ACPI CPPC: " fmt -#include <linux/cpufreq.h>  #include <linux/delay.h>  #include <linux/iopoll.h>  #include <linux/ktime.h> @@ -101,14 +100,14 @@ static DEFINE_PER_CPU(struct cpc_desc *, cpc_desc_ptr);  				(cpc)->cpc_entry.reg.space_id ==	\  				ACPI_ADR_SPACE_PLATFORM_COMM) -/* Evalutes to True if reg is a NULL register descriptor */ +/* Evaluates to True if reg is a NULL register descriptor */  #define IS_NULL_REG(reg) ((reg)->space_id ==  ACPI_ADR_SPACE_SYSTEM_MEMORY && \  				(reg)->address == 0 &&			\  				(reg)->bit_width == 0 &&		\  				(reg)->bit_offset == 0 &&		\  				(reg)->access_width == 0) -/* Evalutes to True if an optional cpc field is supported */ +/* Evaluates to True if an optional cpc field is supported */  #define CPC_SUPPORTED(cpc) ((cpc)->type == ACPI_TYPE_INTEGER ?		\  				!!(cpc)->cpc_entry.int_value :		\  				!IS_NULL_REG(&(cpc)->cpc_entry.reg)) @@ -119,23 +118,15 @@ static DEFINE_PER_CPU(struct cpc_desc *, cpc_desc_ptr);   */  #define NUM_RETRIES 500ULL -struct cppc_attr { -	struct attribute attr; -	ssize_t (*show)(struct kobject *kobj, -			struct attribute *attr, char *buf); -	ssize_t (*store)(struct kobject *kobj, -			struct attribute *attr, const char *c, ssize_t count); -}; -  #define define_one_cppc_ro(_name)		\ -static struct cppc_attr _name =			\ +static struct kobj_attribute _name =		\  __ATTR(_name, 0444, show_##_name, NULL)  #define to_cpc_desc(a) container_of(a, struct cpc_desc, kobj)  #define show_cppc_data(access_fn, struct_name, member_name)		\  	static ssize_t show_##member_name(struct kobject *kobj,		\ -					struct attribute *attr,	char *buf) \ +				struct kobj_attribute *attr, char *buf)	\  	{								\  		struct cpc_desc *cpc_ptr = to_cpc_desc(kobj);		\  		struct struct_name st_name = {0};			\ @@ -161,7 +152,7 @@ show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, reference_perf);  show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, wraparound_time);  static ssize_t show_feedback_ctrs(struct kobject *kobj, -		struct attribute *attr, char *buf) +		struct kobj_attribute *attr, char *buf)  {  	struct cpc_desc *cpc_ptr = to_cpc_desc(kobj);  	struct cppc_perf_fb_ctrs fb_ctrs = {0}; @@ -327,6 +318,7 @@ end:  		if (unlikely(ret)) {  			for_each_possible_cpu(i) {  				struct cpc_desc *desc = per_cpu(cpc_desc_ptr, i); +  				if (!desc)  					continue; @@ -778,7 +770,7 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)  			cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_BUFFER;  			memcpy(&cpc_ptr->cpc_regs[i-2].cpc_entry.reg, gas_t, sizeof(*gas_t));  		} else { -			pr_debug("Err in entry:%d in CPC table of CPU:%d \n", i, pr->id); +			pr_debug("Err in entry:%d in CPC table of CPU:%d\n", i, pr->id);  			goto out_free;  		}  	} @@ -868,7 +860,7 @@ void acpi_cppc_processor_exit(struct acpi_processor *pr)  	void __iomem *addr;  	int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, pr->id); -	if (pcc_ss_id >=0 && pcc_data[pcc_ss_id]) { +	if (pcc_ss_id >= 0 && pcc_data[pcc_ss_id]) {  		if (pcc_data[pcc_ss_id]->pcc_channel_acquired) {  			pcc_data[pcc_ss_id]->refcount--;  			if (!pcc_data[pcc_ss_id]->refcount) { @@ -955,22 +947,22 @@ static int cpc_read(int cpu, struct cpc_register_resource *reg_res, u64 *val)  				val, reg->bit_width);  	switch (reg->bit_width) { -		case 8: -			*val = readb_relaxed(vaddr); -			break; -		case 16: -			*val = readw_relaxed(vaddr); -			break; -		case 32: -			*val = readl_relaxed(vaddr); -			break; -		case 64: -			*val = readq_relaxed(vaddr); -			break; -		default: -			pr_debug("Error: Cannot read %u bit width from PCC for ss: %d\n", -				 reg->bit_width, pcc_ss_id); -			ret_val = -EFAULT; +	case 8: +		*val = readb_relaxed(vaddr); +		break; +	case 16: +		*val = readw_relaxed(vaddr); +		break; +	case 32: +		*val = readl_relaxed(vaddr); +		break; +	case 64: +		*val = readq_relaxed(vaddr); +		break; +	default: +		pr_debug("Error: Cannot read %u bit width from PCC for ss: %d\n", +			 reg->bit_width, pcc_ss_id); +		ret_val = -EFAULT;  	}  	return ret_val; @@ -994,23 +986,23 @@ static int cpc_write(int cpu, struct cpc_register_resource *reg_res, u64 val)  				val, reg->bit_width);  	switch (reg->bit_width) { -		case 8: -			writeb_relaxed(val, vaddr); -			break; -		case 16: -			writew_relaxed(val, vaddr); -			break; -		case 32: -			writel_relaxed(val, vaddr); -			break; -		case 64: -			writeq_relaxed(val, vaddr); -			break; -		default: -			pr_debug("Error: Cannot write %u bit width to PCC for ss: %d\n", -				 reg->bit_width, pcc_ss_id); -			ret_val = -EFAULT; -			break; +	case 8: +		writeb_relaxed(val, vaddr); +		break; +	case 16: +		writew_relaxed(val, vaddr); +		break; +	case 32: +		writel_relaxed(val, vaddr); +		break; +	case 64: +		writeq_relaxed(val, vaddr); +		break; +	default: +		pr_debug("Error: Cannot write %u bit width to PCC for ss: %d\n", +			 reg->bit_width, pcc_ss_id); +		ret_val = -EFAULT; +		break;  	}  	return ret_val; @@ -1330,7 +1322,7 @@ int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)  	 * is still with OSPM.  	 *   pending_pcc_write_cmd can also be cleared by a different CPU, if  	 * there was a pcc CMD_READ waiting on down_write and it steals the lock -	 * before the pcc CMD_WRITE is completed. pcc_send_cmd checks for this +	 * before the pcc CMD_WRITE is completed. send_pcc_cmd checks for this  	 * case during a CMD_READ and if there are pending writes it delivers  	 * the write command before servicing the read command  	 */ @@ -1355,8 +1347,8 @@ EXPORT_SYMBOL_GPL(cppc_set_perf);  /**   * cppc_get_transition_latency - returns frequency transition latency in ns   * - * ACPI CPPC does not explicitly specifiy how a platform can specify the - * transition latency for perfromance change requests. The closest we have + * ACPI CPPC does not explicitly specify how a platform can specify the + * transition latency for performance change requests. The closest we have   * is the timing information from the PCCT tables which provides the info   * on the number and frequency of PCC commands the platform can handle.   */ | 
