diff options
Diffstat (limited to 'arch')
619 files changed, 22477 insertions, 5924 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 6aa7dc4db2fc..621cda54eac1 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -129,6 +129,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \ bcm4709-tplink-archer-c9-v1.dtb \ bcm47094-asus-rt-ac88u.dtb \ bcm47094-dlink-dir-885l.dtb \ + bcm47094-dlink-dir-890l.dtb \ bcm47094-linksys-panamera.dtb \ bcm47094-luxul-abr-4500.dtb \ bcm47094-luxul-xap-1610.dtb \ @@ -139,6 +140,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \ bcm47094-netgear-r8500.dtb \ bcm47094-phicomm-k3.dtb \ bcm53015-meraki-mr26.dtb \ + bcm53016-dlink-dwl-8610ap.dtb \ bcm53016-meraki-mr32.dtb \ bcm94708.dtb \ bcm94709.dtb \ @@ -355,6 +357,7 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += \ kirkwood-ns2mini.dtb \ kirkwood-nsa310.dtb \ kirkwood-nsa310a.dtb \ + kirkwood-nsa310s.dtb \ kirkwood-nsa320.dtb \ kirkwood-nsa325.dtb \ kirkwood-openblocks_a6.dtb \ @@ -681,6 +684,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6s-dhcom-drc02.dtb dtb-$(CONFIG_SOC_IMX6SL) += \ imx6sl-evk.dtb \ + imx6sl-kobo-aura2.dtb \ imx6sl-tolino-shine2hd.dtb \ imx6sl-tolino-shine3.dtb \ imx6sl-tolino-vision5.dtb \ @@ -1214,6 +1218,7 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32mp151a-prtt1a.dtb \ stm32mp151a-prtt1c.dtb \ stm32mp151a-prtt1s.dtb \ + stm32mp151a-dhcor-testbench.dtb \ stm32mp153c-dhcom-drc02.dtb \ stm32mp153c-dhcor-drc-compact.dtb \ stm32mp157a-avenger96.dtb \ @@ -1454,6 +1459,8 @@ dtb-$(CONFIG_ARCH_UNIPHIER) += \ uniphier-pro4-ace.dtb \ uniphier-pro4-ref.dtb \ uniphier-pro4-sanji.dtb \ + uniphier-pro5-epcore.dtb \ + uniphier-pro5-proex.dtb \ uniphier-pxs2-gentil.dtb \ uniphier-pxs2-vodka.dtb \ uniphier-sld8-ref.dtb @@ -1588,6 +1595,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-bmc-asrock-e3c246d4i.dtb \ aspeed-bmc-asrock-romed8hm3.dtb \ aspeed-bmc-bytedance-g220a.dtb \ + aspeed-bmc-delta-ahe50dc.dtb \ aspeed-bmc-facebook-bletchley.dtb \ aspeed-bmc-facebook-cloudripper.dtb \ aspeed-bmc-facebook-cmm.dtb \ @@ -1601,6 +1609,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-bmc-facebook-wedge400.dtb \ aspeed-bmc-facebook-yamp.dtb \ aspeed-bmc-facebook-yosemitev2.dtb \ + aspeed-bmc-ibm-bonnell.dtb \ aspeed-bmc-ibm-everest.dtb \ aspeed-bmc-ibm-rainier.dtb \ aspeed-bmc-ibm-rainier-1s4u.dtb \ @@ -1612,7 +1621,6 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-bmc-lenovo-hr855xg2.dtb \ aspeed-bmc-microsoft-olympus.dtb \ aspeed-bmc-opp-lanyang.dtb \ - aspeed-bmc-opp-mihawk.dtb \ aspeed-bmc-opp-mowgli.dtb \ aspeed-bmc-opp-nicole.dtb \ aspeed-bmc-opp-palmetto.dtb \ diff --git a/arch/arm/boot/dts/am335x-baltos-leds.dtsi b/arch/arm/boot/dts/am335x-baltos-leds.dtsi index 9a79f727baf6..025014657d12 100644 --- a/arch/arm/boot/dts/am335x-baltos-leds.dtsi +++ b/arch/arm/boot/dts/am335x-baltos-leds.dtsi @@ -17,18 +17,18 @@ compatible = "gpio-leds"; - power { + led-power { label = "onrisc:red:power"; linux,default-trigger = "default-on"; gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; default-state = "on"; }; - wlan { + led-wlan { label = "onrisc:blue:wlan"; gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - app { + led-app { label = "onrisc:green:app"; gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>; default-state = "off"; diff --git a/arch/arm/boot/dts/am335x-boneblack-hdmi.dtsi b/arch/arm/boot/dts/am335x-boneblack-hdmi.dtsi index 7cfddada9348..486f24deb875 100644 --- a/arch/arm/boot/dts/am335x-boneblack-hdmi.dtsi +++ b/arch/arm/boot/dts/am335x-boneblack-hdmi.dtsi @@ -85,8 +85,13 @@ audio-ports = < TDA998x_I2S 0x03>; ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { - hdmi_0: endpoint@0 { + reg = <0>; + + hdmi_0: endpoint { remote-endpoint = <&lcdc_0>; }; }; diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts index 25c6ac9913d2..5beabaa5ff6a 100644 --- a/arch/arm/boot/dts/am335x-evm.dts +++ b/arch/arm/boot/dts/am335x-evm.dts @@ -126,7 +126,7 @@ backlight = <&backlight>; port { - panel_0: endpoint@0 { + panel_0: endpoint { remote-endpoint = <&lcdc_0>; }; }; @@ -544,7 +544,7 @@ #size-cells = <1>; partition@0 { label = "NAND.SPL"; - reg = <0x00000000 0x000020000>; + reg = <0x00000000 0x00020000>; }; partition@1 { label = "NAND.SPL.backup1"; diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts index 9c458e5a95b7..5b3278c0c46a 100644 --- a/arch/arm/boot/dts/am335x-evmsk.dts +++ b/arch/arm/boot/dts/am335x-evmsk.dts @@ -191,7 +191,7 @@ backlight = <&lcd_bl>; port { - panel_0: endpoint@0 { + panel_0: endpoint { remote-endpoint = <&lcdc_0>; }; }; diff --git a/arch/arm/boot/dts/am335x-guardian.dts b/arch/arm/boot/dts/am335x-guardian.dts index f6356266564c..b357364e93f9 100644 --- a/arch/arm/boot/dts/am335x-guardian.dts +++ b/arch/arm/boot/dts/am335x-guardian.dts @@ -103,8 +103,9 @@ }; - guardian_beeper: dmtimer-pwm@7 { + guardian_beeper: pwm-7 { compatible = "ti,omap-dmtimer-pwm"; + #pwm-cells = <3>; ti,timers = <&timer7>; pinctrl-names = "default"; pinctrl-0 = <&guardian_beeper_pins>; diff --git a/arch/arm/boot/dts/am335x-igep0033.dtsi b/arch/arm/boot/dts/am335x-igep0033.dtsi index cc14415a4eb9..3fddf80dcf71 100644 --- a/arch/arm/boot/dts/am335x-igep0033.dtsi +++ b/arch/arm/boot/dts/am335x-igep0033.dtsi @@ -168,7 +168,7 @@ /* MTD partition table */ partition@0 { label = "SPL"; - reg = <0x00000000 0x000080000>; + reg = <0x00000000 0x00080000>; }; partition@1 { @@ -188,7 +188,7 @@ partition@4 { label = "File System"; - reg = <0x00780000 0x007880000>; + reg = <0x00780000 0x07880000>; }; }; }; diff --git a/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi b/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi index 7b40ca9483ca..49e280b42442 100644 --- a/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi +++ b/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi @@ -16,11 +16,11 @@ /* Power supply provides a fixed 3.3V @3A */ vmmcsd_fixed: vmmcsd-regulator { - compatible = "regulator-fixed"; - regulator-name = "vmmcsd_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; + compatible = "regulator-fixed"; + regulator-name = "vmmcsd_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; }; buttons: push_button { diff --git a/arch/arm/boot/dts/am335x-moxa-uc-8100-common.dtsi b/arch/arm/boot/dts/am335x-moxa-uc-8100-common.dtsi index e0364adb8393..7d00e8b20f18 100644 --- a/arch/arm/boot/dts/am335x-moxa-uc-8100-common.dtsi +++ b/arch/arm/boot/dts/am335x-moxa-uc-8100-common.dtsi @@ -21,11 +21,11 @@ /* Power supply provides a fixed 3.3V @3A */ vmmcsd_fixed: vmmcsd-regulator { - compatible = "regulator-fixed"; - regulator-name = "vmmcsd_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; + compatible = "regulator-fixed"; + regulator-name = "vmmcsd_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; }; buttons: push_button { diff --git a/arch/arm/boot/dts/am335x-myirtech-myd.dts b/arch/arm/boot/dts/am335x-myirtech-myd.dts index 9d81d4cc6890..425ad9b81a68 100644 --- a/arch/arm/boot/dts/am335x-myirtech-myd.dts +++ b/arch/arm/boot/dts/am335x-myirtech-myd.dts @@ -161,8 +161,13 @@ #sound-dai-cells = <0>; ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { - hdmi_0: endpoint@0 { + reg = <0>; + + hdmi_0: endpoint { remote-endpoint = <&lcdc_0>; }; }; diff --git a/arch/arm/boot/dts/am335x-pcm-953.dtsi b/arch/arm/boot/dts/am335x-pcm-953.dtsi index dae448040a97..947497413977 100644 --- a/arch/arm/boot/dts/am335x-pcm-953.dtsi +++ b/arch/arm/boot/dts/am335x-pcm-953.dtsi @@ -12,22 +12,20 @@ compatible = "phytec,am335x-pcm-953", "phytec,am335x-phycore-som", "ti,am33xx"; /* Power */ - regulators { - vcc3v3: fixedregulator@1 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; + vcc3v3: fixedregulator1 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; - vcc1v8: fixedregulator@2 { - compatible = "regulator-fixed"; - regulator-name = "vcc1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - }; + vcc1v8: fixedregulator2 { + compatible = "regulator-fixed"; + regulator-name = "vcc1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; }; /* User IO */ diff --git a/arch/arm/boot/dts/am335x-pepper.dts b/arch/arm/boot/dts/am335x-pepper.dts index 8691eec33b61..a4509e9e1056 100644 --- a/arch/arm/boot/dts/am335x-pepper.dts +++ b/arch/arm/boot/dts/am335x-pepper.dts @@ -555,11 +555,11 @@ }; &usb0 { - dr_mode = "host"; + dr_mode = "host"; }; &usb1 { - dr_mode = "host"; + dr_mode = "host"; }; &am33xx_pinmux { diff --git a/arch/arm/boot/dts/am335x-pocketbeagle.dts b/arch/arm/boot/dts/am335x-pocketbeagle.dts index 5e415d8ffdd8..0ba4883cd4ef 100644 --- a/arch/arm/boot/dts/am335x-pocketbeagle.dts +++ b/arch/arm/boot/dts/am335x-pocketbeagle.dts @@ -23,28 +23,28 @@ compatible = "gpio-leds"; - usr0 { + led-usr0 { label = "beaglebone:green:usr0"; gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; default-state = "off"; }; - usr1 { + led-usr1 { label = "beaglebone:green:usr1"; gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>; linux,default-trigger = "mmc0"; default-state = "off"; }; - usr2 { + led-usr2 { label = "beaglebone:green:usr2"; gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "cpu0"; default-state = "off"; }; - usr3 { + led-usr3 { label = "beaglebone:green:usr3"; gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; default-state = "off"; diff --git a/arch/arm/boot/dts/am3517-evm.dts b/arch/arm/boot/dts/am3517-evm.dts index 35b653014f2b..11618aa501fc 100644 --- a/arch/arm/boot/dts/am3517-evm.dts +++ b/arch/arm/boot/dts/am3517-evm.dts @@ -26,12 +26,12 @@ reg = <0x80000000 0x10000000>; /* 256 MB */ }; - vmmc_fixed: vmmc { - compatible = "regulator-fixed"; - regulator-name = "vmmc_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; + vmmc_fixed: vmmc { + compatible = "regulator-fixed"; + regulator-name = "vmmc_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; gpio-keys { compatible = "gpio-keys-polled"; @@ -150,7 +150,7 @@ enable-gpios = <&gpio6 22 GPIO_ACTIVE_HIGH>; /* gpio_182 */ }; - pwm11: dmtimer-pwm@11 { + pwm11: pwm-11 { compatible = "ti,omap-dmtimer-pwm"; pinctrl-names = "default"; pinctrl-0 = <&pwm_pins>; @@ -176,7 +176,7 @@ }; &davinci_mdio { - status = "okay"; + status = "okay"; }; &dss { @@ -227,7 +227,7 @@ }; &mmc3 { - status = "disabled"; + status = "disabled"; }; &usbhshost { diff --git a/arch/arm/boot/dts/am3517.dtsi b/arch/arm/boot/dts/am3517.dtsi index cb316135bc7c..823f63502e9f 100644 --- a/arch/arm/boot/dts/am3517.dtsi +++ b/arch/arm/boot/dts/am3517.dtsi @@ -49,13 +49,35 @@ }; ocp@68000000 { - am35x_otg_hs: am35x_otg_hs@5c040000 { - compatible = "ti,omap3-musb"; - ti,hwmods = "am35x_otg_hs"; - status = "disabled"; - reg = <0x5c040000 0x1000>; - interrupts = <71>; - interrupt-names = "mc"; + target-module@5c040000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x5c040400 0x4>, + <0x5c040404 0x4>, + <0x5c040408 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-midle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>; + ti,syss-mask = <1>; + clocks = <&hsotgusb_ick_am35xx>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x5c040000 0x1000>; + + am35x_otg_hs: am35x_otg_hs@0 { + compatible = "ti,omap3-musb"; + status = "disabled"; + reg = <0 0x1000>; + interrupts = <71>; + interrupt-names = "mc"; + }; }; davinci_emac: ethernet@5c000000 { @@ -154,7 +176,7 @@ }; /* Table Table 5-79 of the TRM shows 480ab000 is reserved */ -&usb_otg_hs { +&usb_otg_target { status = "disabled"; }; diff --git a/arch/arm/boot/dts/am437x-idk-evm.dts b/arch/arm/boot/dts/am437x-idk-evm.dts index 123a95f87554..e46cf2a9d075 100644 --- a/arch/arm/boot/dts/am437x-idk-evm.dts +++ b/arch/arm/boot/dts/am437x-idk-evm.dts @@ -452,7 +452,7 @@ */ partition@0 { label = "QSPI.U_BOOT"; - reg = <0x00000000 0x000080000>; + reg = <0x00000000 0x00080000>; }; partition@1 { label = "QSPI.U_BOOT.backup"; diff --git a/arch/arm/boot/dts/am437x-sk-evm.dts b/arch/arm/boot/dts/am437x-sk-evm.dts index 036f3831dc26..511a02e13e2c 100644 --- a/arch/arm/boot/dts/am437x-sk-evm.dts +++ b/arch/arm/boot/dts/am437x-sk-evm.dts @@ -763,7 +763,7 @@ */ partition@0 { label = "QSPI.U_BOOT"; - reg = <0x00000000 0x000080000>; + reg = <0x00000000 0x00080000>; }; partition@1 { label = "QSPI.U_BOOT.backup"; diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts index 27f4ce855549..9fc915a2582e 100644 --- a/arch/arm/boot/dts/am43x-epos-evm.dts +++ b/arch/arm/boot/dts/am43x-epos-evm.dts @@ -919,7 +919,7 @@ */ partition@0 { label = "QSPI.U_BOOT"; - reg = <0x00000000 0x000080000>; + reg = <0x00000000 0x00080000>; }; partition@1 { label = "QSPI.U_BOOT.backup"; diff --git a/arch/arm/boot/dts/am57xx-idk-common.dtsi b/arch/arm/boot/dts/am57xx-idk-common.dtsi index c06eda817242..7f092a8811e8 100644 --- a/arch/arm/boot/dts/am57xx-idk-common.dtsi +++ b/arch/arm/boot/dts/am57xx-idk-common.dtsi @@ -542,7 +542,7 @@ */ partition@0 { label = "QSPI.SPL"; - reg = <0x00000000 0x000040000>; + reg = <0x00000000 0x00040000>; }; partition@1 { label = "QSPI.u-boot"; diff --git a/arch/arm/boot/dts/armada-370-dlink-dns327l.dts b/arch/arm/boot/dts/armada-370-dlink-dns327l.dts index 2008c6eaaa52..561195b749eb 100644 --- a/arch/arm/boot/dts/armada-370-dlink-dns327l.dts +++ b/arch/arm/boot/dts/armada-370-dlink-dns327l.dts @@ -86,19 +86,19 @@ pinctrl-names = "default"; - sata-r-amber-pin { + led-sata-r-amber { label = "dns327l:amber:sata-r"; gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>; default-state = "keep"; }; - sata-l-amber-pin { + led-sata-l-amber { label = "dns327l:amber:sata-l"; gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; default-state = "keep"; }; - backup-led-pin { + led-backup { label = "dns327l:white:usb"; gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; default-state = "keep"; diff --git a/arch/arm/boot/dts/armada-370-netgear-rn102.dts b/arch/arm/boot/dts/armada-370-netgear-rn102.dts index b0b640b7de40..079b37cf148a 100644 --- a/arch/arm/boot/dts/armada-370-netgear-rn102.dts +++ b/arch/arm/boot/dts/armada-370-netgear-rn102.dts @@ -85,11 +85,11 @@ }; clocks { - g762_clk: g762-oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <8192>; - }; + g762_clk: g762-oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <8192>; + }; }; gpio-leds { diff --git a/arch/arm/boot/dts/armada-370-netgear-rn104.dts b/arch/arm/boot/dts/armada-370-netgear-rn104.dts index 85e2e9e27a9f..d752ac1d7b58 100644 --- a/arch/arm/boot/dts/armada-370-netgear-rn104.dts +++ b/arch/arm/boot/dts/armada-370-netgear-rn104.dts @@ -94,11 +94,11 @@ }; clocks { - g762_clk: g762-oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <8192>; - }; + g762_clk: g762-oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <8192>; + }; }; gpio-leds { diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts index 6ba7699b69ed..be005c9f42ef 100644 --- a/arch/arm/boot/dts/armada-370-rd.dts +++ b/arch/arm/boot/dts/armada-370-rd.dts @@ -61,8 +61,8 @@ status = "okay"; phy-mode = "rgmii-id"; fixed-link { - speed = <1000>; - full-duplex; + speed = <1000>; + full-duplex; }; }; @@ -155,18 +155,18 @@ }; port@1 { - reg = <1>; - label = "lan1"; + reg = <1>; + label = "lan1"; }; port@2 { - reg = <2>; - label = "lan2"; + reg = <2>; + label = "lan2"; }; port@3 { - reg = <3>; - label = "lan3"; + reg = <3>; + label = "lan3"; }; port@5 { diff --git a/arch/arm/boot/dts/armada-370-seagate-nas-4bay.dts b/arch/arm/boot/dts/armada-370-seagate-nas-4bay.dts index 3cf70c72c5ca..9cb69999b1db 100644 --- a/arch/arm/boot/dts/armada-370-seagate-nas-4bay.dts +++ b/arch/arm/boot/dts/armada-370-seagate-nas-4bay.dts @@ -72,11 +72,11 @@ }; gpio-leds { - red-sata2 { + led-red-sata2 { label = "dart:red:sata2"; gpios = <&pca9554 0 GPIO_ACTIVE_LOW>; }; - red-sata3 { + led-red-sata3 { label = "dart:red:sata3"; gpios = <&pca9554 3 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi b/arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi index 866b8630d407..822f10734946 100644 --- a/arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi +++ b/arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi @@ -132,21 +132,21 @@ gpio-leds { compatible = "gpio-leds"; - white-power { + led-white-power { label = "dart:white:power"; gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; linux,default-trigger = "timer"; }; - red-power { + led-red-power { label = "dart:red:power"; gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; }; - red-sata0 { + led-red-sata0 { label = "dart:red:sata0"; gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; }; - red-sata1 { + led-red-sata1 { label = "dart:red:sata1"; gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi b/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi index 702a85af2078..124a8ba279e3 100644 --- a/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi +++ b/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi @@ -107,7 +107,7 @@ gpio-leds { compatible = "gpio-leds"; - red-sata0 { + led-red-sata0 { label = "cumulus:red:sata0"; gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; default-state = "off"; diff --git a/arch/arm/boot/dts/armada-370-synology-ds213j.dts b/arch/arm/boot/dts/armada-370-synology-ds213j.dts index e72b8ed4b997..f0893cc06607 100644 --- a/arch/arm/boot/dts/armada-370-synology-ds213j.dts +++ b/arch/arm/boot/dts/armada-370-synology-ds213j.dts @@ -91,9 +91,9 @@ }; ethernet@70000 { - status = "okay"; - phy = <&phy1>; - phy-mode = "sgmii"; + status = "okay"; + phy = <&phy1>; + phy-mode = "sgmii"; }; sata@a0000 { diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi index 9dc928859ad3..2013a5ccecd3 100644 --- a/arch/arm/boot/dts/armada-370.dtsi +++ b/arch/arm/boot/dts/armada-370.dtsi @@ -84,7 +84,7 @@ pcie2: pcie@2,0 { device_type = "pci"; - assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; + assigned-addresses = <0x82001000 0 0x80000 0 0x2000>; reg = <0x1000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi index 929deaf312a5..c310ef26d1cc 100644 --- a/arch/arm/boot/dts/armada-375.dtsi +++ b/arch/arm/boot/dts/armada-375.dtsi @@ -592,7 +592,7 @@ pcie1: pcie@2,0 { device_type = "pci"; - assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; + assigned-addresses = <0x82001000 0 0x44000 0 0x2000>; reg = <0x1000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; diff --git a/arch/arm/boot/dts/armada-380.dtsi b/arch/arm/boot/dts/armada-380.dtsi index ce1dddb2269b..e94f22b0e9b5 100644 --- a/arch/arm/boot/dts/armada-380.dtsi +++ b/arch/arm/boot/dts/armada-380.dtsi @@ -89,7 +89,7 @@ /* x1 port */ pcie@2,0 { device_type = "pci"; - assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; + assigned-addresses = <0x82001000 0 0x40000 0 0x2000>; reg = <0x1000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; @@ -118,7 +118,7 @@ /* x1 port */ pcie@3,0 { device_type = "pci"; - assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; + assigned-addresses = <0x82001800 0 0x44000 0 0x2000>; reg = <0x1800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; diff --git a/arch/arm/boot/dts/armada-385-linksys-caiman.dts b/arch/arm/boot/dts/armada-385-linksys-caiman.dts index a03050c97084..88b2921fed55 100644 --- a/arch/arm/boot/dts/armada-385-linksys-caiman.dts +++ b/arch/arm/boot/dts/armada-385-linksys-caiman.dts @@ -62,11 +62,11 @@ }; &gpio_leds { - power { + led-power { label = "caiman:white:power"; }; - sata { + led-sata { label = "caiman:white:sata"; }; }; diff --git a/arch/arm/boot/dts/armada-385-linksys-cobra.dts b/arch/arm/boot/dts/armada-385-linksys-cobra.dts index e3e4877a6f49..88200f930d0d 100644 --- a/arch/arm/boot/dts/armada-385-linksys-cobra.dts +++ b/arch/arm/boot/dts/armada-385-linksys-cobra.dts @@ -62,11 +62,11 @@ }; &gpio_leds { - power { + led-power { label = "cobra:white:power"; }; - sata { + led-sata { label = "cobra:white:sata"; }; }; diff --git a/arch/arm/boot/dts/armada-385-linksys-rango.dts b/arch/arm/boot/dts/armada-385-linksys-rango.dts index 3c4af57ec2b9..4ab45f294de2 100644 --- a/arch/arm/boot/dts/armada-385-linksys-rango.dts +++ b/arch/arm/boot/dts/armada-385-linksys-rango.dts @@ -54,22 +54,22 @@ }; &gpio_leds { - power { + led-power { gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; label = "rango:white:power"; }; - sata { + led-sata { gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; label = "rango:white:sata"; }; - wlan_2g { + led-wlan_2g { gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; label = "rango:white:wlan_2g"; }; - wlan_5g { + led-wlan_5g { gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; label = "rango:white:wlan_5g"; }; diff --git a/arch/arm/boot/dts/armada-385-linksys-shelby.dts b/arch/arm/boot/dts/armada-385-linksys-shelby.dts index 3451cd3e5dff..f1b1f22413f1 100644 --- a/arch/arm/boot/dts/armada-385-linksys-shelby.dts +++ b/arch/arm/boot/dts/armada-385-linksys-shelby.dts @@ -62,11 +62,11 @@ }; &gpio_leds { - power { + led-power { label = "shelby:white:power"; }; - sata { + led-sata { label = "shelby:white:sata"; }; }; diff --git a/arch/arm/boot/dts/armada-385-linksys.dtsi b/arch/arm/boot/dts/armada-385-linksys.dtsi index 116aca5e688f..85e8d966f6c1 100644 --- a/arch/arm/boot/dts/armada-385-linksys.dtsi +++ b/arch/arm/boot/dts/armada-385-linksys.dtsi @@ -71,12 +71,12 @@ pinctrl-0 = <&gpio_leds_pins>; pinctrl-names = "default"; - power { + led-power { gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; default-state = "on"; }; - sata { + led-sata { gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; default-state = "off"; linux,default-trigger = "disk-activity"; diff --git a/arch/arm/boot/dts/armada-385-synology-ds116.dts b/arch/arm/boot/dts/armada-385-synology-ds116.dts index 2622af73c9da..ea91ff964d94 100644 --- a/arch/arm/boot/dts/armada-385-synology-ds116.dts +++ b/arch/arm/boot/dts/armada-385-synology-ds116.dts @@ -149,7 +149,7 @@ * sata0, and accesses to SATA disk 0 make it blink so it * doesn't need to be declared here. */ - orange { + led-orange { gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; label = "ds116:orange:disk"; default-state = "off"; diff --git a/arch/arm/boot/dts/armada-385-turris-omnia.dts b/arch/arm/boot/dts/armada-385-turris-omnia.dts index 72ac807cae25..0c1f238e4c30 100644 --- a/arch/arm/boot/dts/armada-385-turris-omnia.dts +++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts @@ -23,6 +23,12 @@ stdout-path = &uart0; }; + aliases { + ethernet0 = ð0; + ethernet1 = ð1; + ethernet2 = ð2; + }; + memory { device_type = "memory"; reg = <0x00000000 0x40000000>; /* 1024 MB */ @@ -483,7 +489,17 @@ }; }; - /* port 6 is connected to eth0 */ + ports@6 { + reg = <6>; + label = "cpu"; + ethernet = <ð0>; + phy-mode = "rgmii-id"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; }; }; }; diff --git a/arch/arm/boot/dts/armada-385.dtsi b/arch/arm/boot/dts/armada-385.dtsi index 83392b92dae2..be8d607c59b2 100644 --- a/arch/arm/boot/dts/armada-385.dtsi +++ b/arch/arm/boot/dts/armada-385.dtsi @@ -93,7 +93,7 @@ /* x1 port */ pcie2: pcie@2,0 { device_type = "pci"; - assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; + assigned-addresses = <0x82001000 0 0x40000 0 0x2000>; reg = <0x1000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; @@ -121,7 +121,7 @@ /* x1 port */ pcie3: pcie@3,0 { device_type = "pci"; - assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; + assigned-addresses = <0x82001800 0 0x44000 0 0x2000>; reg = <0x1800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; @@ -152,7 +152,7 @@ */ pcie4: pcie@4,0 { device_type = "pci"; - assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; + assigned-addresses = <0x82002000 0 0x48000 0 0x2000>; reg = <0x2000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi index 446861b6b17b..12933eff419f 100644 --- a/arch/arm/boot/dts/armada-38x.dtsi +++ b/arch/arm/boot/dts/armada-38x.dtsi @@ -304,7 +304,7 @@ }; gpio0: gpio@18100 { - compatible = "marvell,armada-370-gpio", + compatible = "marvell,armadaxp-gpio", "marvell,orion-gpio"; reg = <0x18100 0x40>, <0x181c0 0x08>; reg-names = "gpio", "pwm"; @@ -323,7 +323,7 @@ }; gpio1: gpio@18140 { - compatible = "marvell,armada-370-gpio", + compatible = "marvell,armadaxp-gpio", "marvell,orion-gpio"; reg = <0x18140 0x40>, <0x181c8 0x08>; reg-names = "gpio", "pwm"; diff --git a/arch/arm/boot/dts/armada-39x.dtsi b/arch/arm/boot/dts/armada-39x.dtsi index 923b035a3ab3..1e05208d9f34 100644 --- a/arch/arm/boot/dts/armada-39x.dtsi +++ b/arch/arm/boot/dts/armada-39x.dtsi @@ -213,7 +213,7 @@ }; gpio0: gpio@18100 { - compatible = "marvell,orion-gpio"; + compatible = "marvell,armadaxp-gpio", "marvell,orion-gpio"; reg = <0x18100 0x40>; ngpios = <32>; gpio-controller; @@ -227,7 +227,7 @@ }; gpio1: gpio@18140 { - compatible = "marvell,orion-gpio"; + compatible = "marvell,armadaxp-gpio", "marvell,orion-gpio"; reg = <0x18140 0x40>; ngpios = <28>; gpio-controller; @@ -463,7 +463,7 @@ /* x1 port */ pcie@2,0 { device_type = "pci"; - assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; + assigned-addresses = <0x82001000 0 0x40000 0 0x2000>; reg = <0x1000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; @@ -492,7 +492,7 @@ /* x1 port */ pcie@3,0 { device_type = "pci"; - assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; + assigned-addresses = <0x82001800 0 0x44000 0 0x2000>; reg = <0x1800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; @@ -524,7 +524,7 @@ */ pcie@4,0 { device_type = "pci"; - assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; + assigned-addresses = <0x82002000 0 0x48000 0 0x2000>; reg = <0x2000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; diff --git a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi index b21ffb819b1d..7a7e2066c498 100644 --- a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi +++ b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi @@ -296,6 +296,7 @@ compatible = "marvell,armada-xp-wdt"; clocks = <&coreclk 2>, <&refclk>; clock-names = "nbclk", "fixed"; + interrupts = <93>, <38>; }; &cpurst { diff --git a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts index 622ac40dd164..dbe8dfe236fb 100644 --- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts +++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts @@ -195,7 +195,7 @@ pinctrl-0 = <&power_led_pin>; pinctrl-names = "default"; - power { + led-power { label = "mamba:white:power"; gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; default-state = "on"; diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi index bf9360f41e0a..5ea9d509cd30 100644 --- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi @@ -107,7 +107,7 @@ pcie2: pcie@2,0 { device_type = "pci"; - assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; + assigned-addresses = <0x82001000 0 0x44000 0 0x2000>; reg = <0x1000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; @@ -135,7 +135,7 @@ pcie3: pcie@3,0 { device_type = "pci"; - assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; + assigned-addresses = <0x82001800 0 0x48000 0 0x2000>; reg = <0x1800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; @@ -163,7 +163,7 @@ pcie4: pcie@4,0 { device_type = "pci"; - assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>; + assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>; reg = <0x2000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; @@ -191,7 +191,7 @@ pcie5: pcie@5,0 { device_type = "pci"; - assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; + assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; reg = <0x2800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi index 0714af52e607..6c6fbb9faf5a 100644 --- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi @@ -122,7 +122,7 @@ pcie2: pcie@2,0 { device_type = "pci"; - assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; + assigned-addresses = <0x82001000 0 0x44000 0 0x2000>; reg = <0x1000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; @@ -150,7 +150,7 @@ pcie3: pcie@3,0 { device_type = "pci"; - assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; + assigned-addresses = <0x82001800 0 0x48000 0 0x2000>; reg = <0x1800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; @@ -178,7 +178,7 @@ pcie4: pcie@4,0 { device_type = "pci"; - assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>; + assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>; reg = <0x2000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; @@ -206,7 +206,7 @@ pcie5: pcie@5,0 { device_type = "pci"; - assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; + assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; reg = <0x2800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; @@ -234,7 +234,7 @@ pcie6: pcie@6,0 { device_type = "pci"; - assigned-addresses = <0x82000800 0 0x84000 0 0x2000>; + assigned-addresses = <0x82003000 0 0x84000 0 0x2000>; reg = <0x3000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; @@ -262,7 +262,7 @@ pcie7: pcie@7,0 { device_type = "pci"; - assigned-addresses = <0x82000800 0 0x88000 0 0x2000>; + assigned-addresses = <0x82003800 0 0x88000 0 0x2000>; reg = <0x3800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; @@ -290,7 +290,7 @@ pcie8: pcie@8,0 { device_type = "pci"; - assigned-addresses = <0x82000800 0 0x8c000 0 0x2000>; + assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>; reg = <0x4000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; @@ -318,7 +318,7 @@ pcie9: pcie@9,0 { device_type = "pci"; - assigned-addresses = <0x82000800 0 0x42000 0 0x2000>; + assigned-addresses = <0x82004800 0 0x42000 0 0x2000>; reg = <0x4800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; diff --git a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts index 8ea73587db81..31933f81144e 100644 --- a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts +++ b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts @@ -121,11 +121,11 @@ }; clocks { - g762_clk: g762-oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; + g762_clk: g762-oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; }; gpio-leds { diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi index 6c19984d668e..4297482da62f 100644 --- a/arch/arm/boot/dts/armada-xp.dtsi +++ b/arch/arm/boot/dts/armada-xp.dtsi @@ -260,6 +260,7 @@ compatible = "marvell,armada-xp-wdt"; clocks = <&coreclk 2>, <&refclk>; clock-names = "nbclk", "fixed"; + interrupts = <93>, <38>; }; &cpurst { diff --git a/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts b/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts index d127cbcc7998..0a51d2e32fab 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts @@ -342,6 +342,10 @@ &i2c0 { status = "okay"; + ssif-bmc@10 { + compatible = "ssif-bmc"; + reg = <0x10>; + }; }; &i2c1 { @@ -350,6 +354,14 @@ &i2c2 { status = "okay"; + smpro@4f { + compatible = "ampere,smpro"; + reg = <0x4f>; + }; + smpro@4e { + compatible = "ampere,smpro"; + reg = <0x4e>; + }; }; &i2c3 { diff --git a/arch/arm/boot/dts/aspeed-bmc-ampere-mtmitchell.dts b/arch/arm/boot/dts/aspeed-bmc-ampere-mtmitchell.dts index 606cd4be245a..4b91600eaf62 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ampere-mtmitchell.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ampere-mtmitchell.dts @@ -445,6 +445,10 @@ &i2c11 { status = "okay"; + ssif-bmc@10 { + compatible = "ssif-bmc"; + reg = <0x10>; + }; }; &i2c14 { diff --git a/arch/arm/boot/dts/aspeed-bmc-delta-ahe50dc.dts b/arch/arm/boot/dts/aspeed-bmc-delta-ahe50dc.dts new file mode 100644 index 000000000000..6600f7e9bf5e --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-delta-ahe50dc.dts @@ -0,0 +1,418 @@ +// SPDX-License-Identifier: GPL-2.0+ +/dts-v1/; + +#include "aspeed-g4.dtsi" +#include <dt-bindings/gpio/aspeed-gpio.h> + +#define EFUSE_OUTPUT(n) \ + efuse##n { \ + compatible = "regulator-output"; \ + vout-supply = <&efuse##n>; \ + } + +#define __stringify(x) #x + +#define EFUSE(hexaddr, num) \ + efuse@##hexaddr { \ + compatible = "lm25066"; \ + reg = <0x##hexaddr>; \ + shunt-resistor-micro-ohms = <675>; \ + regulators { \ + efuse##num: vout0 { \ + regulator-name = __stringify(efuse##num##-reg); \ + }; \ + }; \ + } + +/{ + model = "Delta Power AHE-50DC"; + compatible = "delta,ahe50dc-bmc", "aspeed,ast2400"; + + aliases { + serial4 = &uart5; + + /* + * pca9541-arbitrated logical i2c buses are numbered as the + * corresponding physical bus plus 20 + */ + i2c20 = &i2carb0; + i2c21 = &i2carb1; + i2c22 = &i2carb2; + i2c23 = &i2carb3; + i2c24 = &i2carb4; + i2c26 = &i2carb6; + i2c27 = &i2carb7; + i2c28 = &i2carb8; + i2c32 = &i2carb12; + }; + + chosen { + stdout-path = &uart3; + bootargs = "console=ttyS2,115200n8 earlycon"; + }; + + memory@40000000 { + reg = <0x40000000 0x10000000>; + }; + + leds { + compatible = "gpio-leds"; + + heartbeat { + gpios = <&gpio ASPEED_GPIO(P, 0) GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + panic { + gpios = <&gpio ASPEED_GPIO(P, 2) GPIO_ACTIVE_HIGH>; + linux,default-trigger = "panic"; + }; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, <&adc 4>, + <&adc 5>, <&adc 6>, <&adc 7>, <&adc 8>, <&adc 9>; + }; + + EFUSE_OUTPUT(01); + EFUSE_OUTPUT(02); + EFUSE_OUTPUT(03); + EFUSE_OUTPUT(04); + EFUSE_OUTPUT(05); + EFUSE_OUTPUT(06); + EFUSE_OUTPUT(07); + EFUSE_OUTPUT(08); + EFUSE_OUTPUT(09); + EFUSE_OUTPUT(10); + EFUSE_OUTPUT(11); + EFUSE_OUTPUT(12); + EFUSE_OUTPUT(13); + EFUSE_OUTPUT(14); + EFUSE_OUTPUT(15); + EFUSE_OUTPUT(16); + EFUSE_OUTPUT(17); + EFUSE_OUTPUT(18); + EFUSE_OUTPUT(19); + EFUSE_OUTPUT(20); + EFUSE_OUTPUT(21); + EFUSE_OUTPUT(22); + EFUSE_OUTPUT(23); + EFUSE_OUTPUT(24); + EFUSE_OUTPUT(25); + EFUSE_OUTPUT(26); + EFUSE_OUTPUT(27); + EFUSE_OUTPUT(28); + EFUSE_OUTPUT(29); + EFUSE_OUTPUT(30); + EFUSE_OUTPUT(31); + EFUSE_OUTPUT(32); + EFUSE_OUTPUT(33); + EFUSE_OUTPUT(34); + EFUSE_OUTPUT(35); + EFUSE_OUTPUT(36); + EFUSE_OUTPUT(37); + EFUSE_OUTPUT(38); + EFUSE_OUTPUT(39); + EFUSE_OUTPUT(40); + EFUSE_OUTPUT(41); + EFUSE_OUTPUT(42); + EFUSE_OUTPUT(43); + EFUSE_OUTPUT(44); + EFUSE_OUTPUT(45); + EFUSE_OUTPUT(46); + EFUSE_OUTPUT(47); + EFUSE_OUTPUT(48); + EFUSE_OUTPUT(49); + EFUSE_OUTPUT(50); + +}; + +&fmc { + status = "okay"; + + flash@0 { + status = "okay"; + m25p,fast-read; + label = "flash0"; + spi-max-frequency = <50000000>; // 50 MHz +#include "openbmc-flash-layout.dtsi" + }; +}; + +&uart3 { + status = "okay"; +}; + +&mac1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; +}; + +&i2c0 { + status = "okay"; + bus-frequency = <200000>; + + pca9541@79 { + compatible = "nxp,pca9541"; + reg = <0x79>; + + i2carb0: i2c-arb { + #address-cells = <1>; + #size-cells = <0>; + + /* lm25066 efuses @ 10-17, 40-47, 50-57 */ + EFUSE(10, 03); + EFUSE(11, 04); + EFUSE(12, 01); + EFUSE(13, 02); + EFUSE(14, 13); + EFUSE(15, 14); + EFUSE(16, 15); + EFUSE(17, 16); + EFUSE(40, 12); + EFUSE(41, 11); + EFUSE(42, 10); + EFUSE(43, 09); + EFUSE(44, 08); + EFUSE(45, 07); + EFUSE(46, 05); + EFUSE(47, 06); + EFUSE(50, 17); + EFUSE(51, 18); + EFUSE(52, 20); + EFUSE(53, 19); + EFUSE(54, 22); + EFUSE(55, 21); + EFUSE(56, 24); + EFUSE(57, 23); + }; + }; +}; + +&i2c1 { + status = "okay"; + bus-frequency = <200000>; + + pca9541@72 { + compatible = "nxp,pca9541"; + reg = <0x72>; + + i2carb1: i2c-arb { + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&i2c2 { + status = "okay"; + bus-frequency = <200000>; + + pca9541@73 { + compatible = "nxp,pca9541"; + reg = <0x73>; + + i2carb2: i2c-arb { + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&i2c3 { + status = "okay"; + bus-frequency = <200000>; + + pca9541@74 { + compatible = "nxp,pca9541"; + reg = <0x74>; + + i2carb3: i2c-arb { + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&i2c4 { + status = "okay"; + bus-frequency = <200000>; + + pca9541@7a { + compatible = "nxp,pca9541"; + reg = <0x7a>; + + i2carb4: i2c-arb { + #address-cells = <1>; + #size-cells = <0>; + + gpio@20 { + compatible = "nxp,pca9534"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + /* lm25066 efuses @ 10-17, 40-47, 50-57, 59, 5a */ + EFUSE(10, 27); + EFUSE(11, 28); + EFUSE(12, 25); + EFUSE(13, 26); + EFUSE(14, 37); + EFUSE(15, 38); + EFUSE(16, 39); + EFUSE(17, 40); + EFUSE(40, 36); + EFUSE(41, 35); + EFUSE(42, 34); + EFUSE(43, 33); + EFUSE(44, 32); + EFUSE(45, 31); + EFUSE(46, 29); + EFUSE(47, 30); + EFUSE(50, 41); + EFUSE(51, 42); + EFUSE(52, 44); + EFUSE(53, 43); + EFUSE(54, 46); + EFUSE(55, 45); + EFUSE(56, 48); + EFUSE(57, 47); + EFUSE(59, 49); + EFUSE(5a, 50); + }; + }; +}; + +&i2c6 { + status = "okay"; + bus-frequency = <200000>; + + pca9541@75 { + compatible = "nxp,pca9541"; + reg = <0x75>; + + i2carb6: i2c-arb { + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&i2c7 { + status = "okay"; + bus-frequency = <200000>; + + pca9541@76 { + compatible = "nxp,pca9541"; + reg = <0x76>; + + i2carb7: i2c-arb { + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&i2c8 { + status = "okay"; + bus-frequency = <200000>; + + pca9541@7c { + compatible = "nxp,pca9541"; + reg = <0x7c>; + + i2carb8: i2c-arb { + #address-cells = <1>; + #size-cells = <0>; + + fancontrol@30 { + compatible = "delta,ahe50dc-fan"; + reg = <0x30>; + }; + + /* Baseboard FRU eeprom */ + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + }; + }; + }; +}; + +&i2c12 { + status = "okay"; + bus-frequency = <200000>; + + pca9541@71 { + compatible = "nxp,pca9541"; + reg = <0x71>; + + i2carb12: i2c-arb { + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&gpio { + status = "okay"; + gpio-line-names = + /* A */ "", "", "", "", "", "", "", "", + /* B */ "", "", "", "", "", "", "", "", + /* C */ "RESET_PEER_N", "HEARTBEAT_OUT", "", "", "", "", "", "", + /* D */ "", "", "", "", "", "", "", "", + /* E */ "DOOM_N", "", "", "", "", "LED_PWR_BLUE", "", "", + /* F */ "", "", "", "", "", "", "", "", + /* G */ "", "", "", "", "", "", "", "", + /* H */ "", "", "", "", "", "", "", "", + /* I */ "", "", "", "", "", "", "", "", + /* J */ "", "", "BMC_ID", "", "", "", "", "", + /* K */ "", "", "", "", "", "", "", "", + /* L */ "", "", "", "", "", "", "", "", + /* M */ "", "", "", "", "", "", "", "", + /* N */ "", "", "", "", "", "", "", "", + /* O */ "", "", "", "", "", "", "", "", + /* P */ "LED_GREEN", "", "LED_RED", "", "", "", "", "", + /* Q */ "", "", "", "", "", "", "", "", + /* R */ "", "", "", "", "", "", "", "", + /* S */ "", "", "", "", "", "", "", "", + /* T */ "", "", "", "", "", "", "", "", + /* U */ "", "", "", "", "", "", "", "", + /* V */ "", "", "", "", "", "", "", "", + /* W */ "", "", "", "", "", "", "", "", + /* X */ "", "", "", "", "", "", "", "", + /* Y */ "HEARTBEAT_IN", "BOARDREV0", "BOARDREV1", "", + /* Z */ "", "", "", "", "", "", "", "", + /* AA */ "", "", "", "", "", "", "", "", + /* AB */ "", "", "", ""; + + /* + * I don't rightly know what this GPIO really *is*, but setting it to + * zero causes the fans to run at full speed, after which setting it + * back to one causes a power output glitch, so install a hog to keep + * it at one as a failsafe to ensure nothing accidentally touches it. + */ + doom-guardrail { + gpio-hog; + gpios = <ASPEED_GPIO(E, 0) GPIO_ACTIVE_LOW>; + output-low; + }; +}; + +&adc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0_default + &pinctrl_adc1_default + &pinctrl_adc2_default + &pinctrl_adc3_default + &pinctrl_adc4_default + &pinctrl_adc5_default + &pinctrl_adc6_default + &pinctrl_adc7_default + &pinctrl_adc8_default + &pinctrl_adc9_default>; +}; diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts index 1fc3e7cbf0d1..a619eec70633 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts @@ -60,7 +60,7 @@ compatible = "gpio-leds"; sys_log_id { default-state = "off"; - gpios = <&front_leds 0 GPIO_ACTIVE_HIGH>; + gpios = <&front_leds 0 GPIO_ACTIVE_LOW>; }; }; @@ -191,6 +191,95 @@ gpios = <&sled6_leds 1 GPIO_ACTIVE_LOW>; }; }; + + gpio-keys { + compatible = "gpio-keys"; + + presence-sled1 { + label = "presence-sled1"; + gpios = <&gpio0 ASPEED_GPIO(H, 2) GPIO_ACTIVE_LOW>; + linux,code = <ASPEED_GPIO(H, 2)>; + }; + presence-sled2 { + label = "presence-sled2"; + gpios = <&gpio0 ASPEED_GPIO(H, 3) GPIO_ACTIVE_LOW>; + linux,code = <ASPEED_GPIO(H, 3)>; + }; + presence-sled3 { + label = "presence-sled3"; + gpios = <&gpio0 ASPEED_GPIO(H, 4) GPIO_ACTIVE_LOW>; + linux,code = <ASPEED_GPIO(H, 4)>; + }; + presence-sled4 { + label = "presence-sled4"; + gpios = <&gpio0 ASPEED_GPIO(H, 5) GPIO_ACTIVE_LOW>; + linux,code = <ASPEED_GPIO(H, 5)>; + }; + presence-sled5 { + label = "presence-sled5"; + gpios = <&gpio0 ASPEED_GPIO(H, 6) GPIO_ACTIVE_LOW>; + linux,code = <ASPEED_GPIO(H, 6)>; + }; + presence-sled6 { + label = "presence-sled6"; + gpios = <&gpio0 ASPEED_GPIO(H, 7) GPIO_ACTIVE_LOW>; + linux,code = <ASPEED_GPIO(H, 7)>; + }; + }; + + vbus_sled1: vbus_sled1 { + compatible = "regulator-fixed"; + regulator-name = "vbus_sled1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&sled1_ioexp 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vbus_sled2: vbus_sled2 { + compatible = "regulator-fixed"; + regulator-name = "vbus_sled2"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&sled2_ioexp 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vbus_sled3: vbus_sled3 { + compatible = "regulator-fixed"; + regulator-name = "vbus_sled3"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&sled3_ioexp 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vbus_sled4: vbus_sled4 { + compatible = "regulator-fixed"; + regulator-name = "vbus_sled4"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&sled4_ioexp 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vbus_sled5: vbus_sled5 { + compatible = "regulator-fixed"; + regulator-name = "vbus_sled5"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&sled5_ioexp 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vbus_sled6: vbus_sled6 { + compatible = "regulator-fixed"; + regulator-name = "vbus_sled6"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&sled6_ioexp 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; }; &mac2 { @@ -302,17 +391,17 @@ compatible = "fcs,fusb302"; reg = <0x22>; + interrupt-parent = <&gpio0>; + interrupts = <ASPEED_GPIO(B, 0) IRQ_TYPE_LEVEL_LOW>; + vbus-supply = <&vbus_sled1>; + connector { compatible = "usb-c-connector"; label = "USB-C"; - power-role = "dual"; - try-power-role = "sink"; - data-role = "dual"; - source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; - sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) - PDO_VAR(3000, 12000, 3000) - PDO_PPS_APDO(3000, 11000, 3000)>; - op-sink-microwatt = <10000000>; + power-role = "source"; + data-role = "host"; + pd-disable; + typec-power-opmode = "default"; }; }; @@ -388,17 +477,17 @@ compatible = "fcs,fusb302"; reg = <0x22>; + interrupt-parent = <&gpio0>; + interrupts = <ASPEED_GPIO(B, 1) IRQ_TYPE_LEVEL_LOW>; + vbus-supply = <&vbus_sled2>; + connector { compatible = "usb-c-connector"; label = "USB-C"; - power-role = "dual"; - try-power-role = "sink"; - data-role = "dual"; - source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; - sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) - PDO_VAR(3000, 12000, 3000) - PDO_PPS_APDO(3000, 11000, 3000)>; - op-sink-microwatt = <10000000>; + power-role = "source"; + data-role = "host"; + pd-disable; + typec-power-opmode = "default"; }; }; @@ -474,17 +563,17 @@ compatible = "fcs,fusb302"; reg = <0x22>; + interrupt-parent = <&gpio0>; + interrupts = <ASPEED_GPIO(B, 7) IRQ_TYPE_LEVEL_LOW>; + vbus-supply = <&vbus_sled3>; + connector { compatible = "usb-c-connector"; label = "USB-C"; - power-role = "dual"; - try-power-role = "sink"; - data-role = "dual"; - source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; - sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) - PDO_VAR(3000, 12000, 3000) - PDO_PPS_APDO(3000, 11000, 3000)>; - op-sink-microwatt = <10000000>; + power-role = "source"; + data-role = "host"; + pd-disable; + typec-power-opmode = "default"; }; }; @@ -560,17 +649,17 @@ compatible = "fcs,fusb302"; reg = <0x22>; + interrupt-parent = <&gpio0>; + interrupts = <ASPEED_GPIO(S, 7) IRQ_TYPE_LEVEL_LOW>; + vbus-supply = <&vbus_sled4>; + connector { compatible = "usb-c-connector"; label = "USB-C"; - power-role = "dual"; - try-power-role = "sink"; - data-role = "dual"; - source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; - sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) - PDO_VAR(3000, 12000, 3000) - PDO_PPS_APDO(3000, 11000, 3000)>; - op-sink-microwatt = <10000000>; + power-role = "source"; + data-role = "host"; + pd-disable; + typec-power-opmode = "default"; }; }; @@ -646,17 +735,17 @@ compatible = "fcs,fusb302"; reg = <0x22>; + interrupt-parent = <&gpio0>; + interrupts = <ASPEED_GPIO(Y, 3) IRQ_TYPE_LEVEL_LOW>; + vbus-supply = <&vbus_sled5>; + connector { compatible = "usb-c-connector"; label = "USB-C"; - power-role = "dual"; - try-power-role = "sink"; - data-role = "dual"; - source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; - sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) - PDO_VAR(3000, 12000, 3000) - PDO_PPS_APDO(3000, 11000, 3000)>; - op-sink-microwatt = <10000000>; + power-role = "source"; + data-role = "host"; + pd-disable; + typec-power-opmode = "default"; }; }; @@ -732,17 +821,17 @@ compatible = "fcs,fusb302"; reg = <0x22>; + interrupt-parent = <&gpio0>; + interrupts = <ASPEED_GPIO(I, 7) IRQ_TYPE_LEVEL_LOW>; + vbus-supply = <&vbus_sled6>; + connector { compatible = "usb-c-connector"; label = "USB-C"; - power-role = "dual"; - try-power-role = "sink"; - data-role = "dual"; - source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; - sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) - PDO_VAR(3000, 12000, 3000) - PDO_PPS_APDO(3000, 11000, 3000)>; - op-sink-microwatt = <10000000>; + power-role = "source"; + data-role = "host"; + pd-disable; + typec-power-opmode = "default"; }; }; @@ -863,6 +952,9 @@ }; &gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiov2_unbiased_default>; + gpio-line-names = /*A0-A7*/ "","","","","","","","", /*B0-B7*/ "FUSB302_SLED1_INT_N","FUSB302_SLED2_INT_N", @@ -892,11 +984,11 @@ /*M0-M7*/ "ALERT_SLED1_N","ALERT_SLED2_N", "ALERT_SLED3_N","ALERT_SLED4_N", "ALERT_SLED5_N","ALERT_SLED6_N", - "","", + "","USB_DEBUG_PWR_BTN_N", /*N0-N7*/ "LED_POSTCODE_0","LED_POSTCODE_1", "LED_POSTCODE_2","LED_POSTCODE_3", "LED_POSTCODE_4","LED_POSTCODE_5", - "LED_POSTCODE_5","LED_POSTCODE_7", + "LED_POSTCODE_6","LED_POSTCODE_7", /*O0-O7*/ "","","","", "","BOARD_ID0","BOARD_ID1","BOARD_ID2", /*P0-P7*/ "","","","","","","","BMC_HEARTBEAT", @@ -953,3 +1045,22 @@ &ehci0 { status = "okay"; }; + +&ehci1 { + status = "okay"; +}; + +&emmc_controller { + status = "okay"; +}; + +&emmc { + status = "okay"; +}; + +&pinctrl { + pinctrl_gpiov2_unbiased_default: gpiov2 { + pins = "AD14"; + bias-disable; + }; +}; diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-cloudripper.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-cloudripper.dts index 9c6271a17ae8..5cd060029ea9 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-cloudripper.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-cloudripper.dts @@ -77,7 +77,7 @@ i2c55 = &imux55; }; - spi_gpio: spi-gpio { + spi_gpio: spi { num-chipselects = <2>; cs-gpios = <&gpio0 ASPEED_GPIO(X, 0) GPIO_ACTIVE_LOW>, <&gpio0 ASPEED_GPIO(X, 1) GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-elbert.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-elbert.dts index 8e1a1d1b282d..b5cd4c7800b0 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-elbert.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-elbert.dts @@ -44,7 +44,7 @@ stdout-path = &uart5; }; - spi_gpio: spi-gpio { + spi_gpio: spi { num-chipselects = <1>; cs-gpios = <&gpio0 ASPEED_GPIO(X, 0) GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-fuji.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-fuji.dts index af58a73bbc49..6b319f34a9b9 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-fuji.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-fuji.dts @@ -207,7 +207,7 @@ i2c143 = &imux143; }; - spi_gpio: spi-gpio { + spi_gpio: spi { num-chipselects = <3>; cs-gpios = <&gpio0 ASPEED_GPIO(X, 0) GPIO_ACTIVE_LOW>, <0>, /* device reg=<1> does not exist */ diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-wedge400.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-wedge400.dts index a901c8be49b9..ed305948386f 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-wedge400.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-wedge400.dts @@ -67,7 +67,7 @@ * full-duplex SPI transactions are not supported by ASPEED SPI * Controllers. */ - spi_gpio: spi-gpio { + spi_gpio: spi { status = "okay"; compatible = "spi-gpio"; #address-cells = <1>; diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-bonnell.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-bonnell.dts new file mode 100644 index 000000000000..d1971ddf06a5 --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-bonnell.dts @@ -0,0 +1,921 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright 2022 IBM Corp. +/dts-v1/; + +#include "aspeed-g6.dtsi" +#include <dt-bindings/gpio/aspeed-gpio.h> +#include <dt-bindings/i2c/i2c.h> +#include <dt-bindings/leds/leds-pca955x.h> + +/ { + model = "Bonnell"; + compatible = "ibm,bonnell-bmc", "aspeed,ast2600"; + + aliases { + i2c100 = &cfam0_i2c0; + i2c101 = &cfam0_i2c1; + i2c110 = &cfam0_i2c10; + i2c111 = &cfam0_i2c11; + i2c112 = &cfam0_i2c12; + i2c113 = &cfam0_i2c13; + i2c114 = &cfam0_i2c14; + i2c115 = &cfam0_i2c15; + i2c202 = &cfam1_i2c2; + i2c203 = &cfam1_i2c3; + i2c210 = &cfam1_i2c10; + i2c211 = &cfam1_i2c11; + i2c214 = &cfam1_i2c14; + i2c215 = &cfam1_i2c15; + i2c216 = &cfam1_i2c16; + i2c217 = &cfam1_i2c17; + + serial4 = &uart5; + i2c16 = &i2c11mux0chn0; + i2c17 = &i2c11mux0chn1; + i2c18 = &i2c11mux0chn2; + i2c19 = &i2c11mux0chn3; + + spi10 = &cfam0_spi0; + spi11 = &cfam0_spi1; + spi12 = &cfam0_spi2; + spi13 = &cfam0_spi3; + spi20 = &cfam1_spi0; + spi21 = &cfam1_spi1; + spi22 = &cfam1_spi2; + spi23 = &cfam1_spi3; + + }; + + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS4,115200n8 earlycon"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + ramoops@b3e00000 { + compatible = "ramoops"; + reg = <0xb3e00000 0x200000>; /* 16 * (4 * 0x8000) */ + record-size = <0x8000>; + console-size = <0x8000>; + ftrace-size = <0x8000>; + pmsg-size = <0x8000>; + max-reason = <3>; /* KMSG_DUMP_EMERG */ + }; + + /* LPC FW cycle bridge region requires natural alignment */ + flash_memory: region@b4000000 { + no-map; + reg = <0xb4000000 0x04000000>; /* 64M */ + }; + + /* VGA region is dictated by hardware strapping */ + vga_memory: region@bf000000 { + no-map; + compatible = "shared-dma-pool"; + reg = <0xbf000000 0x01000000>; /* 16M */ + }; + }; + + leds { + compatible = "gpio-leds"; + + fan0 { + gpios = <&gpio0 ASPEED_GPIO(G, 0) GPIO_ACTIVE_LOW>; + }; + + fan1 { + gpios = <&gpio0 ASPEED_GPIO(G, 1) GPIO_ACTIVE_LOW>; + }; + + rear-enc-id0 { + gpios = <&gpio0 ASPEED_GPIO(H, 2) GPIO_ACTIVE_LOW>; + }; + + rear-enc-fault0 { + gpios = <&gpio0 ASPEED_GPIO(H, 3) GPIO_ACTIVE_LOW>; + }; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <1000>; + + fan0-presence { + label = "fan0-presence"; + gpios = <&gpio0 ASPEED_GPIO(F, 4) GPIO_ACTIVE_LOW>; + linux,code = <6>; + }; + + fan1-presence { + label = "fan1-presence"; + gpios = <&gpio0 ASPEED_GPIO(F, 5) GPIO_ACTIVE_LOW>; + linux,code = <7>; + }; + }; + + iio-hwmon-battery { + compatible = "iio-hwmon"; + io-channels = <&adc1 7>; + }; +}; + +&adc1 { + status = "okay"; + aspeed,int-vref-microvolt = <2500000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc8_default &pinctrl_adc9_default + &pinctrl_adc10_default &pinctrl_adc11_default + &pinctrl_adc12_default &pinctrl_adc13_default + &pinctrl_adc14_default &pinctrl_adc15_default>; +}; + +&ehci1 { + status = "okay"; +}; + +&uhci { + status = "okay"; +}; + +&gpio0 { + gpio-line-names = + /*A0-A7*/ "","","","","","","","", + /*B0-B7*/ "","","","","","","checkstop","", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "","","","","","","","", + /*E0-E7*/ "","","","","","","","", + /*F0-F7*/ "","","rtc-battery-voltage-read-enable","reset-cause-pinhole","","","","", + /*G0-G7*/ "fan0","fan1","","","","","","", + /*H0-H7*/ "","","rear-enc-id0","rear-enc-fault0","","","","", + /*I0-I7*/ "","","","","","","bmc-secure-boot","", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "","","","","","","","", + /*N0-N7*/ "","","","","","","","", + /*O0-O7*/ "","","","usb-power","","","","", + /*P0-P7*/ "","","","","","","","", + /*Q0-Q7*/ "cfam-reset","","regulator-standby-faulted","","","","","", + /*R0-R7*/ "bmc-tpm-reset","power-chassis-control","power-chassis-good","","","","","", + /*S0-S7*/ "presence-ps0","presence-ps1","","","power-ffs-sync-history","","","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","","","","","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "","","","","","","","", + /*Z0-Z7*/ "","","","","","","",""; + + usb_power { + gpio-hog; + gpios = <ASPEED_GPIO(O, 3) GPIO_ACTIVE_LOW>; + output-high; + }; +}; + +&emmc_controller { + status = "okay"; +}; + +&pinctrl_emmc_default { + bias-disable; +}; + +&emmc { + status = "okay"; + clk-phase-mmc-hs200 = <180>, <180>; +}; + +&fsim0 { + status = "okay"; + + #address-cells = <2>; + #size-cells = <0>; + + cfam-reset-gpios = <&gpio0 ASPEED_GPIO(Q, 0) GPIO_ACTIVE_HIGH>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom@1000 { + compatible = "ibm,fsi2pib"; + reg = <0x1000 0x400>; + }; + + i2c@1800 { + compatible = "ibm,fsi-i2c-master"; + reg = <0x1800 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam0_i2c0: i2c-bus@0 { + reg = <0>; /* OMI01 */ + }; + + cfam0_i2c1: i2c-bus@1 { + reg = <1>; /* OMI23 */ + }; + + cfam0_i2c10: i2c-bus@a { + reg = <10>; /* OP3A */ + }; + + cfam0_i2c11: i2c-bus@b { + reg = <11>; /* OP3B */ + }; + + cfam0_i2c12: i2c-bus@c { + reg = <12>; /* OP4A */ + }; + + cfam0_i2c13: i2c-bus@d { + reg = <13>; /* OP4B */ + }; + + cfam0_i2c14: i2c-bus@e { + reg = <14>; /* OP5A */ + }; + + cfam0_i2c15: i2c-bus@f { + reg = <15>; /* OP5B */ + }; + }; + + fsi2spi@1c00 { + compatible = "ibm,fsi2spi"; + reg = <0x1c00 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam0_spi0: spi@0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam0_spi1: spi@20 { + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam0_spi2: spi@40 { + reg = <0x40>; + compatible = "ibm,fsi2spi-restricted"; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam0_spi3: spi@60 { + reg = <0x60>; + compatible = "ibm,fsi2spi-restricted"; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + }; + + sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + fsi_occ0: occ { + compatible = "ibm,p10-occ"; + + occ-hwmon { + compatible = "ibm,p10-occ-hwmon"; + ibm,no-poll-on-init; + }; + }; + }; + + fsi_hub0: hub@3400 { + compatible = "fsi-master-hub"; + reg = <0x3400 0x400>; + #address-cells = <2>; + #size-cells = <0>; + }; + }; +}; + +&fsi_hub0 { + cfam@1,0 { + reg = <1 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <1>; + + scom@1000 { + compatible = "ibm,fsi2pib"; + reg = <0x1000 0x400>; + }; + + i2c@1800 { + compatible = "ibm,fsi-i2c-master"; + reg = <0x1800 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam1_i2c2: i2c-bus@2 { + reg = <2>; /* OMI45 */ + }; + + cfam1_i2c3: i2c-bus@3 { + reg = <3>; /* OMI67 */ + }; + + cfam1_i2c10: i2c-bus@a { + reg = <10>; /* OP3A */ + }; + + cfam1_i2c11: i2c-bus@b { + reg = <11>; /* OP3B */ + }; + + cfam1_i2c14: i2c-bus@e { + reg = <14>; /* OP5A */ + }; + + cfam1_i2c15: i2c-bus@f { + reg = <15>; /* OP5B */ + }; + + cfam1_i2c16: i2c-bus@10 { + reg = <16>; /* OP6A */ + }; + + cfam1_i2c17: i2c-bus@11 { + reg = <17>; /* OP6B */ + }; + }; + + fsi2spi@1c00 { + compatible = "ibm,fsi2spi"; + reg = <0x1c00 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam1_spi0: spi@0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam1_spi1: spi@20 { + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam1_spi2: spi@40 { + reg = <0x40>; + compatible = "ibm,fsi2spi-restricted"; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam1_spi3: spi@60 { + reg = <0x60>; + compatible = "ibm,fsi2spi-restricted"; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + }; + + sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + fsi_occ1: occ { + compatible = "ibm,p10-occ"; + + occ-hwmon { + compatible = "ibm,p10-occ-hwmon"; + ibm,no-poll-on-init; + }; + }; + }; + + fsi_hub1: hub@3400 { + compatible = "fsi-master-hub"; + reg = <0x3400 0x400>; + #address-cells = <2>; + #size-cells = <0>; + + no-scan-on-init; + }; + }; +}; + +&ibt { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + eeprom@51 { + compatible = "atmel,24c64"; + reg = <0x51>; + }; + + tca9554@20 { + compatible = "ti,tca9554"; + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = "", + "RUSSEL_FW_I2C_ENABLE_N", + "RUSSEL_OPPANEL_PRESENCE_N", + "BLYTH_OPPANEL_PRESENCE_N", + "CPU_TPM_CARD_PRESENT_N", + "", + "", + "DASD_BP_PRESENT_N"; + }; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; + + ucd90160@64 { + compatible = "ti,ucd90160"; + reg = <0x64>; + }; +}; + +&i2c3 { + status = "okay"; + + power-supply@58 { + compatible = "ibm,cffps"; + reg = <0x58>; + }; + + power-supply@59 { + compatible = "ibm,cffps"; + reg = <0x59>; + }; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; +}; + +&i2c7 { + multi-master; + status = "okay"; + + si7021-a20@40 { + compatible = "silabs,si7020"; + reg = <0x40>; + }; + + tmp275@48 { + compatible = "ti,tmp275"; + reg = <0x48>; + }; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + + eeprom@51 { + compatible = "atmel,24c64"; + reg = <0x51>; + }; + + max31785@52 { + compatible = "maxim,max31785a"; + reg = <0x52>; + #address-cells = <1>; + #size-cells = <0>; + + fan0: fan@0 { + compatible = "pmbus-fan"; + reg = <0>; + tach-pulses = <2>; + }; + + fan1: fan@1 { + compatible = "pmbus-fan"; + reg = <1>; + tach-pulses = <2>; + }; + }; + + pca9551@60 { + compatible = "nxp,pca9551"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "front-sys-id0"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@1 { + label = "front-check-log0"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@2 { + label = "front-enc-fault1"; + reg = <2>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@3 { + label = "front-sys-pwron0"; + reg = <3>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + }; + + ibm-panel@62 { + compatible = "ibm,op-panel"; + reg = <(0x62 | I2C_OWN_SLAVE_ADDRESS)>; + }; + + dps: dps310@76 { + compatible = "infineon,dps310"; + reg = <0x76>; + #io-channel-cells = <0>; + }; +}; + +&i2c8 { + status = "okay"; + + rtc@32 { + compatible = "epson,rx8900"; + reg = <0x32>; + }; + + tmp275@48 { + compatible = "ti,tmp275"; + reg = <0x48>; + }; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + + pca9551@60 { + compatible = "nxp,pca9551"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = "", + "APSS_RESET_N", + "", + "N_MODE_CPU_N", + "", + "", + "P10_DCM_PRESENT", + ""; + }; +}; + +&i2c9 { + status = "okay"; + + tmp423a@4c { + compatible = "ti,tmp423"; + reg = <0x4c>; + }; +}; + +&i2c10 { + status = "okay"; +}; + +&i2c11 { + status = "okay"; + + tca9554@20 { + compatible = "ti,tca9554"; + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = "BOOT_RCVRY_TWI", + "BOOT_RCVRY_UART", + "", + "", + "", + "", + "", + "PE_SWITCH_RSTB_N"; + }; + + tmp435@4c { + compatible = "ti,tmp435"; + reg = <0x4c>; + }; + + pca9849@75 { + compatible = "nxp,pca849"; + reg = <0x75>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + i2c-mux-idle-disconnect; + + i2c11mux0chn0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + i2c11mux0chn1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + i2c11mux0chn2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + i2c11mux0chn3: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; +}; + +&i2c12 { + status = "okay"; + + tpm@2e { + compatible = "nuvoton,npct75x"; + reg = <0x2e>; + }; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; +}; + +&i2c13 { + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + + pca9551@60 { + compatible = "nxp,pca9551"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "nvme0"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@1 { + label = "nvme1"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@2 { + label = "nvme2"; + reg = <2>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@3 { + label = "nvme3"; + reg = <3>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + }; +}; + +&i2c14 { + status = "okay"; +}; + +&i2c15 { + status = "okay"; +}; + +&vuart1 { + status = "okay"; +}; + +&vuart2 { + status = "okay"; +}; + +&lpc_ctrl { + status = "okay"; + memory-region = <&flash_memory>; +}; + +&mac2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii3_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC3CLK>, + <&syscon ASPEED_CLK_MAC3RCLK>; + clock-names = "MACCLK", "RCLK"; + use-ncsi; +}; + +&mac3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii4_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC4CLK>, + <&syscon ASPEED_CLK_MAC4RCLK>; + clock-names = "MACCLK", "RCLK"; + use-ncsi; +}; + +&wdt1 { + aspeed,reset-type = "none"; + aspeed,external-signal; + aspeed,ext-push-pull; + aspeed,ext-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdtrst1_default>; +}; + +&wdt2 { + status = "okay"; +}; + +&xdma { + status = "okay"; + memory-region = <&vga_memory>; +}; + +&kcs2 { + status = "okay"; + aspeed,lpc-io-reg = <0xca8 0xcac>; +}; + +&kcs3 { + status = "okay"; + aspeed,lpc-io-reg = <0xca2>; + aspeed,lpc-interrupts = <11 IRQ_TYPE_LEVEL_LOW>; +}; diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts index a6a2bc3b855c..1448ea895be4 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts @@ -162,16 +162,9 @@ #size-cells = <1>; ranges; - /* LPC FW cycle bridge region requires natural alignment */ - flash_memory: region@b8000000 { - no-map; - reg = <0xb8000000 0x04000000>; /* 64M */ - }; - - /* 48MB region from the end of flash to start of vga memory */ - ramoops@bc000000 { + ramoops@b3e00000 { compatible = "ramoops"; - reg = <0xbc000000 0x200000>; /* 16 * (4 * 0x8000) */ + reg = <0xb3e00000 0x200000>; /* 16 * (4 * 0x8000) */ record-size = <0x8000>; console-size = <0x8000>; ftrace-size = <0x8000>; @@ -179,6 +172,12 @@ max-reason = <3>; /* KMSG_DUMP_EMERG */ }; + /* LPC FW cycle bridge region requires natural alignment */ + flash_memory: region@b4000000 { + no-map; + reg = <0xb4000000 0x04000000>; /* 64M */ + }; + /* VGA region is dictated by hardware strapping */ vga_memory: region@bf000000 { no-map; @@ -2551,6 +2550,11 @@ fsi_occ0: occ { compatible = "ibm,p10-occ"; + + occ-hwmon { + compatible = "ibm,p10-occ-hwmon"; + ibm,no-poll-on-init; + }; }; }; @@ -2695,6 +2699,11 @@ fsi_occ1: occ { compatible = "ibm,p10-occ"; + + occ-hwmon { + compatible = "ibm,p10-occ-hwmon"; + ibm,no-poll-on-init; + }; }; }; @@ -2839,6 +2848,11 @@ fsi_occ2: occ { compatible = "ibm,p10-occ"; + + occ-hwmon { + compatible = "ibm,p10-occ-hwmon"; + ibm,no-poll-on-init; + }; }; }; @@ -2983,6 +2997,11 @@ fsi_occ3: occ { compatible = "ibm,p10-occ"; + + occ-hwmon { + compatible = "ibm,p10-occ-hwmon"; + ibm,no-poll-on-init; + }; }; }; @@ -3127,6 +3146,11 @@ fsi_occ4: occ { compatible = "ibm,p10-occ"; + + occ-hwmon { + compatible = "ibm,p10-occ-hwmon"; + ibm,no-poll-on-init; + }; }; }; @@ -3271,6 +3295,11 @@ fsi_occ5: occ { compatible = "ibm,p10-occ"; + + occ-hwmon { + compatible = "ibm,p10-occ-hwmon"; + ibm,no-poll-on-init; + }; }; }; @@ -3415,6 +3444,11 @@ fsi_occ6: occ { compatible = "ibm,p10-occ"; + + occ-hwmon { + compatible = "ibm,p10-occ-hwmon"; + ibm,no-poll-on-init; + }; }; }; @@ -3559,6 +3593,11 @@ fsi_occ7: occ { compatible = "ibm,p10-occ"; + + occ-hwmon { + compatible = "ibm,p10-occ-hwmon"; + ibm,no-poll-on-init; + }; }; }; diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts index bf59a9962379..20ef958698ec 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts @@ -95,14 +95,9 @@ #size-cells = <1>; ranges; - flash_memory: region@b8000000 { - no-map; - reg = <0xb8000000 0x04000000>; /* 64M */ - }; - - ramoops@bc000000 { + ramoops@b3e00000 { compatible = "ramoops"; - reg = <0xbc000000 0x200000>; /* 16 * (4 * 0x8000) */ + reg = <0xb3e00000 0x200000>; /* 16 * (4 * 0x8000) */ record-size = <0x8000>; console-size = <0x8000>; ftrace-size = <0x8000>; @@ -110,6 +105,13 @@ max-reason = <3>; /* KMSG_DUMP_EMERG */ }; + /* LPC FW cycle bridge region requires natural alignment */ + flash_memory: region@b4000000 { + no-map; + reg = <0xb4000000 0x04000000>; /* 64M */ + }; + + /* VGA region is dictated by hardware strapping */ vga_memory: region@bf000000 { no-map; compatible = "shared-dma-pool"; @@ -442,6 +444,11 @@ fsi_occ0: occ { compatible = "ibm,p10-occ"; + + occ-hwmon { + compatible = "ibm,p10-occ-hwmon"; + ibm,no-poll-on-init; + }; }; }; @@ -586,6 +593,11 @@ fsi_occ1: occ { compatible = "ibm,p10-occ"; + + occ-hwmon { + compatible = "ibm,p10-occ-hwmon"; + ibm,no-poll-on-init; + }; }; }; @@ -730,6 +742,11 @@ fsi_occ2: occ { compatible = "ibm,p10-occ"; + + occ-hwmon { + compatible = "ibm,p10-occ-hwmon"; + ibm,no-poll-on-init; + }; }; }; @@ -874,6 +891,11 @@ fsi_occ3: occ { compatible = "ibm,p10-occ"; + + occ-hwmon { + compatible = "ibm,p10-occ-hwmon"; + ibm,no-poll-on-init; + }; }; }; @@ -995,32 +1017,6 @@ reg = <0x4a>; }; - pca9551@60 { - compatible = "nxp,pca9551"; - reg = <0x60>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - led@0 { - label = "cablecard0-cxp-top"; - reg = <0>; - retain-state-shutdown; - default-state = "keep"; - type = <PCA955X_TYPE_LED>; - }; - - led@1 { - label = "cablecard0-cxp-bot"; - reg = <1>; - retain-state-shutdown; - default-state = "keep"; - type = <PCA955X_TYPE_LED>; - }; - }; - pca9546@70 { compatible = "nxp,pca9546"; reg = <0x70>; @@ -1038,6 +1034,32 @@ compatible = "atmel,24c64"; reg = <0x50>; }; + + pca9551@60 { + compatible = "nxp,pca9551"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "cablecard0-cxp-top"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@1 { + label = "cablecard0-cxp-bot"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + }; }; i2c4mux0chn1: i2c@1 { @@ -1077,58 +1099,6 @@ reg = <0x49>; }; - pca9551@60 { - compatible = "nxp,pca9551"; - reg = <0x60>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - led@0 { - label = "cablecard3-cxp-top"; - reg = <0>; - retain-state-shutdown; - default-state = "keep"; - type = <PCA955X_TYPE_LED>; - }; - - led@1 { - label = "cablecard3-cxp-bot"; - reg = <1>; - retain-state-shutdown; - default-state = "keep"; - type = <PCA955X_TYPE_LED>; - }; - }; - - pca9551@61 { - compatible = "nxp,pca9551"; - reg = <0x61>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - led@0 { - label = "cablecard4-cxp-top"; - reg = <0>; - retain-state-shutdown; - default-state = "keep"; - type = <PCA955X_TYPE_LED>; - }; - - led@1 { - label = "cablecard4-cxp-bot"; - reg = <1>; - retain-state-shutdown; - default-state = "keep"; - type = <PCA955X_TYPE_LED>; - }; - }; - pca9546@70 { compatible = "nxp,pca9546"; reg = <0x70>; @@ -1146,6 +1116,32 @@ compatible = "atmel,24c64"; reg = <0x50>; }; + + pca9551@60 { + compatible = "nxp,pca9551"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "cablecard3-cxp-top"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@1 { + label = "cablecard3-cxp-bot"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + }; }; i2c5mux0chn1: i2c@1 { @@ -1157,6 +1153,32 @@ compatible = "atmel,24c64"; reg = <0x51>; }; + + pca9551@61 { + compatible = "nxp,pca9551"; + reg = <0x61>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "cablecard4-cxp-top"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@1 { + label = "cablecard4-cxp-bot"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + }; }; }; }; @@ -2009,32 +2031,6 @@ reg = <0x49>; }; - pca9551@60 { - compatible = "nxp,pca9551"; - reg = <0x60>; - #address-cells = <1>; - #size-cells = <0>; - - gpio-controller; - #gpio-cells = <2>; - - led@0 { - label = "cablecard10-cxp-top"; - reg = <0>; - retain-state-shutdown; - default-state = "keep"; - type = <PCA955X_TYPE_LED>; - }; - - led@1 { - label = "cablecard10-cxp-bot"; - reg = <1>; - retain-state-shutdown; - default-state = "keep"; - type = <PCA955X_TYPE_LED>; - }; - }; - pca9546@70 { compatible = "nxp,pca9546"; reg = <0x70>; @@ -2052,6 +2048,32 @@ compatible = "atmel,24c64"; reg = <0x50>; }; + + pca9551@60 { + compatible = "nxp,pca9551"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + led@0 { + label = "cablecard10-cxp-top"; + reg = <0>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + + led@1 { + label = "cablecard10-cxp-bot"; + reg = <1>; + retain-state-shutdown; + default-state = "keep"; + type = <PCA955X_TYPE_LED>; + }; + }; }; i2c11mux0chn1: i2c@1 { diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts b/arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts deleted file mode 100644 index 48776fb663fb..000000000000 --- a/arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts +++ /dev/null @@ -1,1381 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/dts-v1/; -#include "aspeed-g5.dtsi" -#include <dt-bindings/gpio/aspeed-gpio.h> -#include <dt-bindings/leds/leds-pca955x.h> - -/ { - model = "Mihawk BMC"; - compatible = "ibm,mihawk-bmc", "aspeed,ast2500"; - - aliases { - i2c215 = &bus6_mux215; - i2c216 = &bus6_mux216; - i2c217 = &bus6_mux217; - i2c218 = &bus6_mux218; - i2c219 = &bus6_mux219; - i2c220 = &bus6_mux220; - i2c221 = &bus6_mux221; - i2c222 = &bus6_mux222; - i2c223 = &bus7_mux223; - i2c224 = &bus7_mux224; - i2c225 = &bus7_mux225; - i2c226 = &bus7_mux226; - i2c227 = &bus7_mux227; - i2c228 = &bus7_mux228; - i2c229 = &bus7_mux229; - i2c230 = &bus7_mux230; - i2c231 = &bus9_mux231; - i2c232 = &bus9_mux232; - i2c233 = &bus9_mux233; - i2c234 = &bus9_mux234; - i2c235 = &bus9_mux235; - i2c236 = &bus9_mux236; - i2c237 = &bus9_mux237; - i2c238 = &bus9_mux238; - i2c239 = &bus10_mux239; - i2c240 = &bus10_mux240; - i2c241 = &bus10_mux241; - i2c242 = &bus10_mux242; - i2c243 = &bus10_mux243; - i2c244 = &bus10_mux244; - i2c245 = &bus10_mux245; - i2c246 = &bus10_mux246; - i2c247 = &bus12_mux247; - i2c248 = &bus12_mux248; - i2c249 = &bus12_mux249; - i2c250 = &bus12_mux250; - i2c251 = &bus13_mux251; - i2c252 = &bus13_mux252; - i2c253 = &bus13_mux253; - i2c254 = &bus13_mux254; - i2c255 = &bus13_mux255; - i2c256 = &bus13_mux256; - i2c257 = &bus13_mux257; - i2c258 = &bus13_mux258; - }; - - chosen { - stdout-path = &uart5; - bootargs = "console=ttyS4,115200 earlycon"; - }; - - memory@80000000 { - reg = <0x80000000 0x20000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - flash_memory: region@98000000 { - no-map; - reg = <0x98000000 0x04000000>; /* 64M */ - }; - - gfx_memory: framebuffer { - size = <0x01000000>; - alignment = <0x01000000>; - compatible = "shared-dma-pool"; - reusable; - }; - - video_engine_memory: jpegbuffer { - size = <0x02000000>; - alignment = <0x01000000>; - compatible = "shared-dma-pool"; - reusable; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - event-air-water { - label = "air-water"; - gpios = <&gpio ASPEED_GPIO(F, 6) GPIO_ACTIVE_LOW>; - linux,code = <ASPEED_GPIO(F, 6)>; - }; - - event-checkstop { - label = "checkstop"; - gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>; - linux,code = <ASPEED_GPIO(J, 2)>; - }; - - event-ps0-presence { - label = "ps0-presence"; - gpios = <&gpio ASPEED_GPIO(Z, 2) GPIO_ACTIVE_LOW>; - linux,code = <ASPEED_GPIO(Z, 2)>; - }; - - event-ps1-presence { - label = "ps1-presence"; - gpios = <&gpio ASPEED_GPIO(Z, 0) GPIO_ACTIVE_LOW>; - linux,code = <ASPEED_GPIO(Z, 0)>; - }; - - button-id { - label = "id-button"; - gpios = <&gpio ASPEED_GPIO(F, 1) GPIO_ACTIVE_LOW>; - linux,code = <ASPEED_GPIO(F, 1)>; - }; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - poll-interval = <1000>; - - event-fan0-presence { - label = "fan0-presence"; - gpios = <&pca9552 9 GPIO_ACTIVE_LOW>; - linux,code = <9>; - }; - - event-fan1-presence { - label = "fan1-presence"; - gpios = <&pca9552 10 GPIO_ACTIVE_LOW>; - linux,code = <10>; - }; - - event-fan2-presence { - label = "fan2-presence"; - gpios = <&pca9552 11 GPIO_ACTIVE_LOW>; - linux,code = <11>; - }; - - event-fan3-presence { - label = "fan3-presence"; - gpios = <&pca9552 12 GPIO_ACTIVE_LOW>; - linux,code = <12>; - }; - - event-fan4-presence { - label = "fan4-presence"; - gpios = <&pca9552 13 GPIO_ACTIVE_LOW>; - linux,code = <13>; - }; - - event-fan5-presence { - label = "fan5-presence"; - gpios = <&pca9552 14 GPIO_ACTIVE_LOW>; - linux,code = <14>; - }; - }; - - leds { - compatible = "gpio-leds"; - - front-fault { - retain-state-shutdown; - default-state = "keep"; - gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_LOW>; - }; - - power-button { - retain-state-shutdown; - default-state = "keep"; - gpios = <&gpio ASPEED_GPIO(AA, 1) GPIO_ACTIVE_LOW>; - }; - - front-id { - retain-state-shutdown; - default-state = "keep"; - gpios = <&gpio ASPEED_GPIO(AA, 2) GPIO_ACTIVE_LOW>; - }; - - - fan0 { - retain-state-shutdown; - default-state = "keep"; - gpios = <&pca9552 0 GPIO_ACTIVE_LOW>; - }; - - fan1 { - retain-state-shutdown; - default-state = "keep"; - gpios = <&pca9552 1 GPIO_ACTIVE_LOW>; - }; - - fan2 { - retain-state-shutdown; - default-state = "keep"; - gpios = <&pca9552 2 GPIO_ACTIVE_LOW>; - }; - - fan3 { - retain-state-shutdown; - default-state = "keep"; - gpios = <&pca9552 3 GPIO_ACTIVE_LOW>; - }; - - fan4 { - retain-state-shutdown; - default-state = "keep"; - gpios = <&pca9552 4 GPIO_ACTIVE_LOW>; - }; - - fan5 { - retain-state-shutdown; - default-state = "keep"; - gpios = <&pca9552 5 GPIO_ACTIVE_LOW>; - }; - }; - - fsi: gpio-fsi { - compatible = "fsi-master-gpio", "fsi-master"; - #address-cells = <2>; - #size-cells = <0>; - no-gpio-delays; - - clock-gpios = <&gpio ASPEED_GPIO(E, 6) GPIO_ACTIVE_HIGH>; - data-gpios = <&gpio ASPEED_GPIO(E, 7) GPIO_ACTIVE_HIGH>; - mux-gpios = <&gpio ASPEED_GPIO(E, 5) GPIO_ACTIVE_HIGH>; - enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>; - trans-gpios = <&gpio ASPEED_GPIO(R, 2) GPIO_ACTIVE_HIGH>; - }; - iio-hwmon-12v { - compatible = "iio-hwmon"; - io-channels = <&adc 0>; - }; - - iio-hwmon-5v { - compatible = "iio-hwmon"; - io-channels = <&adc 1>; - }; - - iio-hwmon-3v { - compatible = "iio-hwmon"; - io-channels = <&adc 2>; - }; - - iio-hwmon-vdd0 { - compatible = "iio-hwmon"; - io-channels = <&adc 3>; - }; - - iio-hwmon-vdd1 { - compatible = "iio-hwmon"; - io-channels = <&adc 4>; - }; - - iio-hwmon-vcs0 { - compatible = "iio-hwmon"; - io-channels = <&adc 5>; - }; - - iio-hwmon-vcs1 { - compatible = "iio-hwmon"; - io-channels = <&adc 6>; - }; - - iio-hwmon-vdn0 { - compatible = "iio-hwmon"; - io-channels = <&adc 7>; - }; - - iio-hwmon-vdn1 { - compatible = "iio-hwmon"; - io-channels = <&adc 8>; - }; - - iio-hwmon-vio0 { - compatible = "iio-hwmon"; - io-channels = <&adc 9>; - }; - - iio-hwmon-vio1 { - compatible = "iio-hwmon"; - io-channels = <&adc 10>; - }; - - iio-hwmon-vddra { - compatible = "iio-hwmon"; - io-channels = <&adc 11>; - }; - - iio-hwmon-battery { - compatible = "iio-hwmon"; - io-channels = <&adc 12>; - }; - - iio-hwmon-vddrb { - compatible = "iio-hwmon"; - io-channels = <&adc 13>; - }; - - iio-hwmon-vddrc { - compatible = "iio-hwmon"; - io-channels = <&adc 14>; - }; - - iio-hwmon-vddrd { - compatible = "iio-hwmon"; - io-channels = <&adc 15>; - }; -}; - -&pwm_tacho { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default - &pinctrl_pwm2_default &pinctrl_pwm3_default - &pinctrl_pwm4_default &pinctrl_pwm5_default>; - - fan@0 { - reg = <0x00>; - aspeed,fan-tach-ch = /bits/ 8 <0x00>; - }; - - fan@1 { - reg = <0x01>; - aspeed,fan-tach-ch = /bits/ 8 <0x01>; - }; - - fan@2 { - reg = <0x02>; - aspeed,fan-tach-ch = /bits/ 8 <0x02>; - }; - - fan@3 { - reg = <0x03>; - aspeed,fan-tach-ch = /bits/ 8 <0x03>; - }; - - fan@4 { - reg = <0x04>; - aspeed,fan-tach-ch = /bits/ 8 <0x04>; - }; - - fan@5 { - reg = <0x05>; - aspeed,fan-tach-ch = /bits/ 8 <0x05>; - }; - - fan@6 { - reg = <0x00>; - aspeed,fan-tach-ch = /bits/ 8 <0x06>; - }; - - fan@7 { - reg = <0x01>; - aspeed,fan-tach-ch = /bits/ 8 <0x07>; - }; - - fan@8 { - reg = <0x02>; - aspeed,fan-tach-ch = /bits/ 8 <0x08>; - }; - - fan@9 { - reg = <0x03>; - aspeed,fan-tach-ch = /bits/ 8 <0x09>; - }; - - fan@10 { - reg = <0x04>; - aspeed,fan-tach-ch = /bits/ 8 <0x0a>; - }; - - fan@11 { - reg = <0x05>; - aspeed,fan-tach-ch = /bits/ 8 <0x0b>; - }; -}; - -&gpio { - gpio-line-names = - /*A0-A7*/ "","cfam-reset","","","","","","", - /*B0-B7*/ "","","","","","","","", - /*C0-C7*/ "","","","","","","","", - /*D0-D7*/ "fsi-enable","","","","","","","", - /*E0-E7*/ "","","","","","fsi-mux","fsi-clock","fsi-data", - /*F0-F7*/ "","id-button","","","","","air-water","", - /*G0-G7*/ "","","","","","","","", - /*H0-H7*/ "","","","","","","","", - /*I0-I7*/ "","","","","","","","", - /*J0-J7*/ "","","checkstop","","","","","", - /*K0-K7*/ "","","","","","","","", - /*L0-L7*/ "","","","","","","","", - /*M0-M7*/ "","","","","","","","", - /*N0-N7*/ "","","","","","","","", - /*O0-O7*/ "","","","","","","","", - /*P0-P7*/ "","","","","","","","", - /*Q0-Q7*/ "","","","","","","","", - /*R0-R7*/ "","","fsi-trans","","","","","", - /*S0-S7*/ "","","","","","","","", - /*T0-T7*/ "","","","","","","","", - /*U0-U7*/ "","","","","","","","", - /*V0-V7*/ "","","","","","","","", - /*W0-W7*/ "","","","","","","","", - /*X0-X7*/ "","","","","","","","", - /*Y0-Y7*/ "","","","","","","","", - /*Z0-Z7*/ "presence-ps1","","presence-ps0","","","","","", - /*AA0-AA7*/ "led-front-fault","power-button","led-front-id","","","","","", - /*AB0-AB7*/ "","","","","","","","", - /*AC0-AC7*/ "","","","","","","",""; -}; - -&fmc { - status = "okay"; - flash@0 { - status = "okay"; - label = "bmc"; - m25p,fast-read; - spi-max-frequency = <50000000>; - partitions { - #address-cells = < 1 >; - #size-cells = < 1 >; - compatible = "fixed-partitions"; - u-boot@0 { - reg = < 0 0x60000 >; - label = "u-boot"; - }; - u-boot-env@60000 { - reg = < 0x60000 0x20000 >; - label = "u-boot-env"; - }; - obmc-ubi@80000 { - reg = < 0x80000 0x1F80000 >; - label = "obmc-ubi"; - }; - }; - }; - flash@1 { - status = "okay"; - label = "alt-bmc"; - m25p,fast-read; - spi-max-frequency = <50000000>; - partitions { - #address-cells = < 1 >; - #size-cells = < 1 >; - compatible = "fixed-partitions"; - u-boot@0 { - reg = < 0 0x60000 >; - label = "alt-u-boot"; - }; - u-boot-env@60000 { - reg = < 0x60000 0x20000 >; - label = "alt-u-boot-env"; - }; - obmc-ubi@80000 { - reg = < 0x80000 0x1F80000 >; - label = "alt-obmc-ubi"; - }; - }; - }; -}; - -&spi1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1_default>; - - flash@0 { - status = "okay"; - label = "pnor"; - m25p,fast-read; - spi-max-frequency = <100000000>; - }; -}; - -&lpc_ctrl { - status = "okay"; - memory-region = <&flash_memory>; - flash = <&spi1>; -}; - -&uart1 { - /* Rear RS-232 connector */ - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd1_default - &pinctrl_rxd1_default - &pinctrl_nrts1_default - &pinctrl_ndtr1_default - &pinctrl_ndsr1_default - &pinctrl_ncts1_default - &pinctrl_ndcd1_default - &pinctrl_nri1_default>; -}; - -&uart2 { - /* APSS */ - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_txd2_default &pinctrl_rxd2_default>; -}; - -&uart5 { - status = "okay"; -}; - -&mac0 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rmii1_default>; - clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, - <&syscon ASPEED_CLK_MAC1RCLK>; - clock-names = "MACCLK", "RCLK"; - use-ncsi; -}; - -&mac1 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; -}; - -&i2c0 { - status = "disabled"; -}; - -&i2c1 { - status = "disabled"; -}; - -&i2c2 { - status = "okay"; - - /* SAMTEC P0 */ - /* SAMTEC P1 */ - -}; - -&i2c3 { - status = "okay"; - - /* APSS */ - /* CPLD */ - - /* PCA9516 (repeater) -> - * CLK Buffer 9FGS9092 - * CLK Buffer 9DBL0651BKILFT - * CLK Buffer 9DBL0651BKILFT - * Power Supply 0 - * Power Supply 1 - * PCA 9552 LED - */ - - power-supply@58 { - compatible = "ibm,cffps1"; - reg = <0x58>; - }; - - power-supply@5b { - compatible = "ibm,cffps1"; - reg = <0x5b>; - }; - - pca9552: pca9552@60 { - compatible = "nxp,pca9552"; - reg = <0x60>; - #address-cells = <1>; - #size-cells = <0>; - gpio-controller; - #gpio-cells = <2>; - - gpio@0 { - reg = <0>; - type = <PCA955X_TYPE_GPIO>; - }; - gpio@1 { - reg = <1>; - type = <PCA955X_TYPE_GPIO>; - }; - gpio@2 { - reg = <2>; - type = <PCA955X_TYPE_GPIO>; - }; - gpio@3 { - reg = <3>; - type = <PCA955X_TYPE_GPIO>; - }; - gpio@4 { - reg = <4>; - type = <PCA955X_TYPE_GPIO>; - }; - gpio@5 { - reg = <5>; - type = <PCA955X_TYPE_GPIO>; - }; - gpio@6 { - reg = <6>; - type = <PCA955X_TYPE_GPIO>; - }; - gpio@7 { - reg = <7>; - type = <PCA955X_TYPE_GPIO>; - }; - gpio@8 { - reg = <8>; - type = <PCA955X_TYPE_GPIO>; - }; - gpio@9 { - reg = <9>; - type = <PCA955X_TYPE_GPIO>; - }; - gpio@10 { - reg = <10>; - type = <PCA955X_TYPE_GPIO>; - }; - gpio@11 { - reg = <11>; - type = <PCA955X_TYPE_GPIO>; - }; - gpio@12 { - reg = <12>; - type = <PCA955X_TYPE_GPIO>; - }; - gpio@13 { - reg = <13>; - type = <PCA955X_TYPE_GPIO>; - }; - gpio@14 { - reg = <14>; - type = <PCA955X_TYPE_GPIO>; - }; - gpio@15 { - reg = <15>; - type = <PCA955X_TYPE_GPIO>; - }; - - }; - -}; - -&i2c4 { - status = "okay"; - - /* CP0 VDD & VCS : IR35221 */ - /* CP0 VDN : IR35221 */ - /* CP0 VIO : IR38064 */ - /* CP0 VDDR : PXM1330 */ - - ir35221@70 { - compatible = "infineon,ir35221"; - reg = <0x70>; - }; - - ir35221@72 { - compatible = "infineon,ir35221"; - reg = <0x72>; - }; - -}; - -&i2c5 { - status = "okay"; - - /* CP0 VDD & VCS : IR35221 */ - /* CP0 VDN : IR35221 */ - /* CP0 VIO : IR38064 */ - /* CP0 VDDR : PXM1330 */ - - ir35221@70 { - compatible = "infineon,ir35221"; - reg = <0x70>; - }; - - ir35221@72 { - compatible = "infineon,ir35221"; - reg = <0x72>; - }; - -}; - -&i2c6 { - status = "okay"; - - /* pca9548 -> NVMe1 to 8 */ - - pca9548@70 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - - bus7_mux223: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - bus7_mux224: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - bus7_mux225: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - bus7_mux226: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - bus7_mux227: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - bus7_mux228: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - bus7_mux229: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - bus7_mux230: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; - -}; - -&i2c7 { - status = "okay"; - - /* pca9548 -> NVMe9 to 16 */ - - pca9548@70 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - - bus6_mux215: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - bus6_mux216: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - bus6_mux217: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - bus6_mux218: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - bus6_mux219: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - bus6_mux220: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - bus6_mux221: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - bus6_mux222: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; - -}; - -&i2c8 { - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - }; -}; - -&i2c9 { - status = "okay"; - - /* pca9545 Riser -> - * PCIe x8 Slot3 - * PCIe x16 slot4 - * PCIe x8 slot5 - * I2C BMC RISER PCA9554 - * BMC SCL/SDA PCA9554 - * PCA9554 - */ - - /* pca9545 -> - * PCIe x16 Slot1 - * PCIe x8 slot2 - * PEX8748 - */ - - pca9545riser@70 { - compatible = "nxp,pca9545"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - - i2c-mux-idle-disconnect; - interrupt-controller; - #interrupt-cells = <2>; - - bus9_mux231: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - tca9554@39 { - compatible = "ti,tca9554"; - reg = <0x39>; - gpio-controller; - #gpio-cells = <2>; - - smbus0-hog { - gpio-hog; - gpios = <4 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "smbus0"; - }; - }; - - tmp431@4c { - compatible = "ti,tmp401"; - reg = <0x4c>; - }; - }; - - bus9_mux232: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - tca9554@39 { - compatible = "ti,tca9554"; - reg = <0x39>; - gpio-controller; - #gpio-cells = <2>; - - smbus1-hog { - gpio-hog; - gpios = <4 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "smbus1"; - }; - }; - - tmp431@4c { - compatible = "ti,tmp401"; - reg = <0x4c>; - }; - }; - - bus9_mux233: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - bus9_mux234: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - }; - - pca9545@71 { - compatible = "nxp,pca9545"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x71>; - - i2c-mux-idle-disconnect; - interrupt-controller; - #interrupt-cells = <2>; - - bus9_mux235: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - tca9554@39 { - compatible = "ti,tca9554"; - reg = <0x39>; - gpio-controller; - #gpio-cells = <2>; - - smbus2-hog { - gpio-hog; - gpios = <4 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "smbus2"; - }; - }; - - tmp431@4c { - compatible = "ti,tmp401"; - reg = <0x4c>; - }; - }; - - bus9_mux236: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - tca9554@39 { - compatible = "ti,tca9554"; - reg = <0x39>; - gpio-controller; - #gpio-cells = <2>; - - smbus3-hog { - gpio-hog; - gpios = <4 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "smbus3"; - }; - }; - - tmp431@4c { - compatible = "ti,tmp401"; - reg = <0x4c>; - }; - }; - - bus9_mux237: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - bus9_mux238: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - }; -}; - -&i2c10 { - status = "okay"; - - /* pca9545 Riser -> - * PCIe x8 Slot8 - * PCIe x16 slot9 - * PCIe x8 slot10 - * I2C BMC RISER PCA9554 - * BMC SCL/SDA PCA9554 - * PCA9554 - */ - - /* pca9545 -> - * PCIe x16 Slot1 - * PCIe x8 slot2 - * PEX8748 - */ - - pca9545riser@70 { - compatible = "nxp,pca9545"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - - i2c-mux-idle-disconnect; - interrupt-controller; - #interrupt-cells = <2>; - - bus10_mux239: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - tca9554@39 { - compatible = "ti,tca9554"; - reg = <0x39>; - gpio-controller; - #gpio-cells = <2>; - - smbus4-hog { - gpio-hog; - gpios = <4 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "smbus4"; - }; - }; - - tmp431@4c { - compatible = "ti,tmp401"; - reg = <0x4c>; - }; - }; - - bus10_mux240: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - tca9554@39 { - compatible = "ti,tca9554"; - reg = <0x39>; - gpio-controller; - #gpio-cells = <2>; - - smbus5-hog { - gpio-hog; - gpios = <4 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "smbus5"; - }; - }; - - tmp431@4c { - compatible = "ti,tmp401"; - reg = <0x4c>; - }; - }; - - bus10_mux241: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - bus10_mux242: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - }; - - pca9545@71 { - compatible = "nxp,pca9545"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x71>; - - i2c-mux-idle-disconnect; - interrupt-controller; - #interrupt-cells = <2>; - - bus10_mux243: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - tca9554@39 { - compatible = "ti,tca9554"; - reg = <0x39>; - gpio-controller; - #gpio-cells = <2>; - - smbus6-hog { - gpio-hog; - gpios = <4 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "smbus6"; - }; - }; - - tmp431@4c { - compatible = "ti,tmp401"; - reg = <0x4c>; - }; - }; - - bus10_mux244: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - tca9554@39 { - compatible = "ti,tca9554"; - reg = <0x39>; - gpio-controller; - #gpio-cells = <2>; - - smbus7-hog { - gpio-hog; - gpios = <4 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "smbus7"; - }; - }; - - tmp431@4c { - compatible = "ti,tmp401"; - reg = <0x4c>; - }; - }; - - bus10_mux245: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - bus10_mux246: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - }; -}; - -&i2c11 { - status = "okay"; - - /* TPM */ - /* RTC RX8900CE */ - /* FPGA for power sequence */ - /* TMP275A */ - /* TMP275A */ - /* EMC1462 */ - - tpm@57 { - compatible = "infineon,slb9645tt"; - reg = <0x57>; - }; - - rtc@32 { - compatible = "epson,rx8900"; - reg = <0x32>; - }; - - tmp275@48 { - compatible = "ti,tmp275"; - reg = <0x48>; - }; - - tmp275@49 { - compatible = "ti,tmp275"; - reg = <0x49>; - }; - - /* chip emc1462 use emc1403 driver */ - emc1403@4c { - compatible = "smsc,emc1403"; - reg = <0x4c>; - }; - -}; - -&i2c12 { - status = "okay"; - - /* pca9545 -> - * SAS BP1 - * SAS BP2 - * NVMe BP - * M.2 riser - */ - - pca9545@70 { - compatible = "nxp,pca9545"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - - interrupt-controller; - #interrupt-cells = <2>; - - bus12_mux247: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - }; - }; - - bus12_mux248: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - }; - }; - - bus12_mux249: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - - eeprom@50 { - compatible = "atmel,24c64"; - reg = <0x50>; - }; - }; - - bus12_mux250: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - - tmp275@48 { - compatible = "ti,tmp275"; - reg = <0x48>; - }; - }; - - }; - -}; - -&i2c13 { - status = "okay"; - - /* pca9548 -> - * NVMe BP - * NVMe HDD17 to 24 - */ - - pca9548@70 { - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; - bus13_mux251: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - - bus13_mux252: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - - bus13_mux253: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - }; - - bus13_mux254: i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - }; - - bus13_mux255: i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - }; - - bus13_mux256: i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - }; - - bus13_mux257: i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - }; - - bus13_mux258: i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - }; - }; -}; - -&vuart { - status = "okay"; -}; - -&gfx { - status = "okay"; - memory-region = <&gfx_memory>; -}; - -&adc { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adc0_default - &pinctrl_adc1_default - &pinctrl_adc2_default - &pinctrl_adc3_default - &pinctrl_adc4_default - &pinctrl_adc5_default - &pinctrl_adc6_default - &pinctrl_adc7_default - &pinctrl_adc8_default - &pinctrl_adc9_default - &pinctrl_adc10_default - &pinctrl_adc11_default - &pinctrl_adc12_default - &pinctrl_adc13_default - &pinctrl_adc14_default - &pinctrl_adc15_default>; -}; - -&wdt1 { - aspeed,reset-type = "none"; - aspeed,external-signal; - aspeed,ext-push-pull; - aspeed,ext-active-high; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdtrst1_default>; -}; - -&wdt2 { - aspeed,alt-boot; -}; - -&ibt { - status = "okay"; -}; - -&vhub { - status = "okay"; -}; - -&video { - status = "okay"; - memory-region = <&video_engine_memory>; -}; - -#include "ibm-power9-dual.dtsi" - diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi index ebbcfe445d9c..cc2f8b785917 100644 --- a/arch/arm/boot/dts/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed-g6.dtsi @@ -36,6 +36,10 @@ serial4 = &uart5; serial5 = &vuart1; serial6 = &vuart2; + mdio0 = &mdio0; + mdio1 = &mdio1; + mdio2 = &mdio2; + mdio3 = &mdio3; }; diff --git a/arch/arm/boot/dts/ast2600-facebook-netbmc-common.dtsi b/arch/arm/boot/dts/ast2600-facebook-netbmc-common.dtsi index 051de5bec345..31590d3186a2 100644 --- a/arch/arm/boot/dts/ast2600-facebook-netbmc-common.dtsi +++ b/arch/arm/boot/dts/ast2600-facebook-netbmc-common.dtsi @@ -25,7 +25,7 @@ * full-duplex SPI transactions are not supported by ASPEED SPI * Controllers. */ - spi_gpio: spi-gpio { + spi_gpio: spi { status = "okay"; compatible = "spi-gpio"; #address-cells = <1>; diff --git a/arch/arm/boot/dts/at91-sam9x60ek.dts b/arch/arm/boot/dts/at91-sam9x60ek.dts index 4ba52ba11dc6..d929c1ba5789 100644 --- a/arch/arm/boot/dts/at91-sam9x60ek.dts +++ b/arch/arm/boot/dts/at91-sam9x60ek.dts @@ -76,7 +76,6 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; - status = "okay"; }; vdd_1v15: fixed-regulator-vdd_1v15 { @@ -85,7 +84,6 @@ regulator-min-microvolt = <1150000>; regulator-max-microvolt = <1150000>; regulator-always-on; - status = "okay"; }; vdd1_3v3: fixed-regulator-vdd1_3v3 { @@ -94,7 +92,6 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; - status = "okay"; }; vdd2_3v3: regulator-fixed-vdd2_3v3 { @@ -103,7 +100,6 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; - status = "okay"; }; }; diff --git a/arch/arm/boot/dts/at91-sama7g5ek.dts b/arch/arm/boot/dts/at91-sama7g5ek.dts index 3b25c67795dd..aa5cc0e98bba 100644 --- a/arch/arm/boot/dts/at91-sama7g5ek.dts +++ b/arch/arm/boot/dts/at91-sama7g5ek.dts @@ -764,8 +764,9 @@ &sdmmc0 { bus-width = <8>; non-removable; - no-1-8-v; sdhci-caps-mask = <0x0 0x00200000>; + vmmc-supply = <&vdd_3v3>; + vqmmc-supply = <&vldo1>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdmmc0_default>; status = "okay"; @@ -775,6 +776,8 @@ bus-width = <4>; no-1-8-v; sdhci-caps-mask = <0x0 0x00200000>; + vmmc-supply = <&vdd_3v3>; + vqmmc-supply = <&vdd_3v3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdmmc1_default>; status = "okay"; diff --git a/arch/arm/boot/dts/axp22x.dtsi b/arch/arm/boot/dts/axp22x.dtsi index a020c12b2884..f79650afd0a7 100644 --- a/arch/arm/boot/dts/axp22x.dtsi +++ b/arch/arm/boot/dts/axp22x.dtsi @@ -67,6 +67,12 @@ status = "disabled"; }; + axp_gpio: gpio { + compatible = "x-powers,axp221-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + regulators { /* Default work frequency for buck regulators */ x-powers,dcdc-freq = <3000>; diff --git a/arch/arm/boot/dts/axp809.dtsi b/arch/arm/boot/dts/axp809.dtsi index ab8e5f2d9246..d134d4c00bd8 100644 --- a/arch/arm/boot/dts/axp809.dtsi +++ b/arch/arm/boot/dts/axp809.dtsi @@ -50,4 +50,11 @@ compatible = "x-powers,axp809"; interrupt-controller; #interrupt-cells = <1>; + + axp_gpio: gpio { + compatible = "x-powers,axp809-gpio", + "x-powers,axp221-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; }; diff --git a/arch/arm/boot/dts/axp81x.dtsi b/arch/arm/boot/dts/axp81x.dtsi index b93387b0c1c3..ebaf1c3ce8db 100644 --- a/arch/arm/boot/dts/axp81x.dtsi +++ b/arch/arm/boot/dts/axp81x.dtsi @@ -62,16 +62,6 @@ compatible = "x-powers,axp813-gpio"; gpio-controller; #gpio-cells = <2>; - - gpio0_ldo: gpio0-ldo-pin { - pins = "GPIO0"; - function = "ldo"; - }; - - gpio1_ldo: gpio1-ldo-pin { - pins = "GPIO1"; - function = "ldo"; - }; }; battery_power_supply: battery-power { @@ -144,15 +134,11 @@ }; reg_ldo_io0: ldo-io0 { - pinctrl-names = "default"; - pinctrl-0 = <&gpio0_ldo>; /* Disable by default to avoid conflicts with GPIO */ status = "disabled"; }; reg_ldo_io1: ldo-io1 { - pinctrl-names = "default"; - pinctrl-0 = <&gpio1_ldo>; /* Disable by default to avoid conflicts with GPIO */ status = "disabled"; }; diff --git a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts index 4432412044de..d5f8823230db 100644 --- a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts +++ b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts @@ -2,6 +2,7 @@ /dts-v1/; #include "bcm2711.dtsi" #include "bcm2711-rpi.dtsi" +#include "bcm283x-rpi-led-deprecated.dtsi" #include "bcm283x-rpi-usb-peripheral.dtsi" #include "bcm283x-rpi-wifi-bt.dtsi" @@ -14,20 +15,7 @@ stdout-path = "serial1:115200n8"; }; - leds { - led-act { - gpios = <&gpio 42 GPIO_ACTIVE_HIGH>; - }; - - led-pwr { - label = "PWR"; - gpios = <&expgpio 2 GPIO_ACTIVE_LOW>; - default-state = "keep"; - linux,default-trigger = "default-on"; - }; - }; - - sd_io_1v8_reg: sd_io_1v8_reg { + sd_io_1v8_reg: regulator-sd-io-1v8 { compatible = "regulator-gpio"; regulator-name = "vdd-sd-io"; regulator-min-microvolt = <1800000>; @@ -41,7 +29,7 @@ status = "okay"; }; - sd_vcc_reg: sd_vcc_reg { + sd_vcc_reg: regulator-sd-vcc { compatible = "regulator-fixed"; regulator-name = "vcc-sd"; regulator-min-microvolt = <3300000>; @@ -156,6 +144,19 @@ status = "okay"; }; +&led_act { + gpios = <&gpio 42 GPIO_ACTIVE_HIGH>; +}; + +&leds { + led_pwr: led-pwr { + label = "PWR"; + gpios = <&expgpio 2 GPIO_ACTIVE_LOW>; + default-state = "keep"; + linux,default-trigger = "default-on"; + }; +}; + &pixelvalve0 { status = "okay"; }; diff --git a/arch/arm/boot/dts/bcm2711-rpi-400.dts b/arch/arm/boot/dts/bcm2711-rpi-400.dts index c53d9eb0b802..1ab8184302db 100644 --- a/arch/arm/boot/dts/bcm2711-rpi-400.dts +++ b/arch/arm/boot/dts/bcm2711-rpi-400.dts @@ -11,14 +11,6 @@ stdout-path = "serial1:115200n8"; }; - leds { - /delete-node/ led-act; - - led-pwr { - gpios = <&gpio 42 GPIO_ACTIVE_HIGH>; - }; - }; - gpio-poweroff { compatible = "gpio-poweroff"; gpios = <&expgpio 5 GPIO_ACTIVE_HIGH>; @@ -40,6 +32,14 @@ clock-frequency = <1950000>; }; +&led_pwr { + gpios = <&gpio 42 GPIO_ACTIVE_HIGH>; +}; + +&leds { + /delete-node/ led_act; +}; + &pm { /delete-property/ system-power-controller; }; diff --git a/arch/arm/boot/dts/bcm2711-rpi-cm4-io.dts b/arch/arm/boot/dts/bcm2711-rpi-cm4-io.dts index 19600b629be5..d7ba02f586d3 100644 --- a/arch/arm/boot/dts/bcm2711-rpi-cm4-io.dts +++ b/arch/arm/boot/dts/bcm2711-rpi-cm4-io.dts @@ -1,23 +1,11 @@ // SPDX-License-Identifier: GPL-2.0 /dts-v1/; #include "bcm2711-rpi-cm4.dtsi" +#include "bcm283x-rpi-led-deprecated.dtsi" #include "bcm283x-rpi-usb-host.dtsi" / { model = "Raspberry Pi Compute Module 4 IO Board"; - - leds { - led-act { - gpios = <&gpio 42 GPIO_ACTIVE_HIGH>; - }; - - led-pwr { - label = "PWR"; - gpios = <&expgpio 2 GPIO_ACTIVE_LOW>; - default-state = "keep"; - linux,default-trigger = "default-on"; - }; - }; }; &ddc0 { @@ -113,6 +101,19 @@ status = "okay"; }; +&led_act { + gpios = <&gpio 42 GPIO_ACTIVE_HIGH>; +}; + +&leds { + led-pwr { + label = "PWR"; + gpios = <&expgpio 2 GPIO_ACTIVE_LOW>; + default-state = "keep"; + linux,default-trigger = "default-on"; + }; +}; + &pixelvalve0 { status = "okay"; }; diff --git a/arch/arm/boot/dts/bcm2711-rpi-cm4.dtsi b/arch/arm/boot/dts/bcm2711-rpi-cm4.dtsi index a2954d466a73..48e63ab7848c 100644 --- a/arch/arm/boot/dts/bcm2711-rpi-cm4.dtsi +++ b/arch/arm/boot/dts/bcm2711-rpi-cm4.dtsi @@ -12,7 +12,7 @@ stdout-path = "serial1:115200n8"; }; - sd_io_1v8_reg: sd_io_1v8_reg { + sd_io_1v8_reg: regulator-sd-io-1v8 { compatible = "regulator-gpio"; regulator-name = "vdd-sd-io"; regulator-min-microvolt = <1800000>; @@ -26,7 +26,7 @@ status = "okay"; }; - sd_vcc_reg: sd_vcc_reg { + sd_vcc_reg: regulator-sd-vcc { compatible = "regulator-fixed"; regulator-name = "vcc-sd"; regulator-min-microvolt = <3300000>; diff --git a/arch/arm/boot/dts/bcm2711.dtsi b/arch/arm/boot/dts/bcm2711.dtsi index 941c4d16791b..097e9f252235 100644 --- a/arch/arm/boot/dts/bcm2711.dtsi +++ b/arch/arm/boot/dts/bcm2711.dtsi @@ -48,7 +48,7 @@ * This node is the provider for the enable-method for * bringing up secondary cores. */ - local_intc: local_intc@40000000 { + local_intc: interrupt-controller@40000000 { compatible = "brcm,bcm2836-l1-intc"; reg = <0x40000000 0x100>; }; @@ -536,6 +536,7 @@ */ l2: l2-cache0 { compatible = "cache"; + cache-unified; cache-size = <0x100000>; cache-line-size = <64>; cache-sets = <1024>; // 1MiB(size)/64(line-size)=16384ways/16-way set @@ -647,21 +648,21 @@ gpio-ranges = <&gpio 0 0 58>; - gpclk0_gpio49: gpclk0_gpio49 { + gpclk0_gpio49: gpclk0-gpio49 { pin-gpclk { pins = "gpio49"; function = "alt1"; bias-disable; }; }; - gpclk1_gpio50: gpclk1_gpio50 { + gpclk1_gpio50: gpclk1-gpio50 { pin-gpclk { pins = "gpio50"; function = "alt1"; bias-disable; }; }; - gpclk2_gpio51: gpclk2_gpio51 { + gpclk2_gpio51: gpclk2-gpio51 { pin-gpclk { pins = "gpio51"; function = "alt1"; @@ -669,7 +670,7 @@ }; }; - i2c0_gpio46: i2c0_gpio46 { + i2c0_gpio46: i2c0-gpio46 { pin-sda { function = "alt0"; pins = "gpio46"; @@ -681,7 +682,7 @@ bias-disable; }; }; - i2c1_gpio46: i2c1_gpio46 { + i2c1_gpio46: i2c1-gpio46 { pin-sda { function = "alt1"; pins = "gpio46"; @@ -693,7 +694,7 @@ bias-disable; }; }; - i2c3_gpio2: i2c3_gpio2 { + i2c3_gpio2: i2c3-gpio2 { pin-sda { function = "alt5"; pins = "gpio2"; @@ -705,7 +706,7 @@ bias-disable; }; }; - i2c3_gpio4: i2c3_gpio4 { + i2c3_gpio4: i2c3-gpio4 { pin-sda { function = "alt5"; pins = "gpio4"; @@ -717,7 +718,7 @@ bias-disable; }; }; - i2c4_gpio6: i2c4_gpio6 { + i2c4_gpio6: i2c4-gpio6 { pin-sda { function = "alt5"; pins = "gpio6"; @@ -729,7 +730,7 @@ bias-disable; }; }; - i2c4_gpio8: i2c4_gpio8 { + i2c4_gpio8: i2c4-gpio8 { pin-sda { function = "alt5"; pins = "gpio8"; @@ -741,7 +742,7 @@ bias-disable; }; }; - i2c5_gpio10: i2c5_gpio10 { + i2c5_gpio10: i2c5-gpio10 { pin-sda { function = "alt5"; pins = "gpio10"; @@ -753,7 +754,7 @@ bias-disable; }; }; - i2c5_gpio12: i2c5_gpio12 { + i2c5_gpio12: i2c5-gpio12 { pin-sda { function = "alt5"; pins = "gpio12"; @@ -765,7 +766,7 @@ bias-disable; }; }; - i2c6_gpio0: i2c6_gpio0 { + i2c6_gpio0: i2c6-gpio0 { pin-sda { function = "alt5"; pins = "gpio0"; @@ -777,7 +778,7 @@ bias-disable; }; }; - i2c6_gpio22: i2c6_gpio22 { + i2c6_gpio22: i2c6-gpio22 { pin-sda { function = "alt5"; pins = "gpio22"; @@ -789,7 +790,7 @@ bias-disable; }; }; - i2c_slave_gpio8: i2c_slave_gpio8 { + i2c_slave_gpio8: i2c-slave-gpio8 { pins-i2c-slave { pins = "gpio8", "gpio9", @@ -799,7 +800,7 @@ }; }; - jtag_gpio48: jtag_gpio48 { + jtag_gpio48: jtag-gpio48 { pins-jtag { pins = "gpio48", "gpio49", @@ -811,7 +812,7 @@ }; }; - mii_gpio28: mii_gpio28 { + mii_gpio28: mii-gpio28 { pins-mii { pins = "gpio28", "gpio29", @@ -820,7 +821,7 @@ function = "alt4"; }; }; - mii_gpio36: mii_gpio36 { + mii_gpio36: mii-gpio36 { pins-mii { pins = "gpio36", "gpio37", @@ -830,7 +831,7 @@ }; }; - pcm_gpio50: pcm_gpio50 { + pcm_gpio50: pcm-gpio50 { pins-pcm { pins = "gpio50", "gpio51", @@ -840,63 +841,63 @@ }; }; - pwm0_0_gpio12: pwm0_0_gpio12 { + pwm0_0_gpio12: pwm0-0-gpio12 { pin-pwm { pins = "gpio12"; function = "alt0"; bias-disable; }; }; - pwm0_0_gpio18: pwm0_0_gpio18 { + pwm0_0_gpio18: pwm0-0-gpio18 { pin-pwm { pins = "gpio18"; function = "alt5"; bias-disable; }; }; - pwm1_0_gpio40: pwm1_0_gpio40 { + pwm1_0_gpio40: pwm1-0-gpio40 { pin-pwm { pins = "gpio40"; function = "alt0"; bias-disable; }; }; - pwm0_1_gpio13: pwm0_1_gpio13 { + pwm0_1_gpio13: pwm0-1-gpio13 { pin-pwm { pins = "gpio13"; function = "alt0"; bias-disable; }; }; - pwm0_1_gpio19: pwm0_1_gpio19 { + pwm0_1_gpio19: pwm0-1-gpio19 { pin-pwm { pins = "gpio19"; function = "alt5"; bias-disable; }; }; - pwm1_1_gpio41: pwm1_1_gpio41 { + pwm1_1_gpio41: pwm1-1-gpio41 { pin-pwm { pins = "gpio41"; function = "alt0"; bias-disable; }; }; - pwm0_1_gpio45: pwm0_1_gpio45 { + pwm0_1_gpio45: pwm0-1-gpio45 { pin-pwm { pins = "gpio45"; function = "alt0"; bias-disable; }; }; - pwm0_0_gpio52: pwm0_0_gpio52 { + pwm0_0_gpio52: pwm0-0-gpio52 { pin-pwm { pins = "gpio52"; function = "alt1"; bias-disable; }; }; - pwm0_1_gpio53: pwm0_1_gpio53 { + pwm0_1_gpio53: pwm0-1-gpio53 { pin-pwm { pins = "gpio53"; function = "alt1"; @@ -904,7 +905,7 @@ }; }; - rgmii_gpio35: rgmii_gpio35 { + rgmii_gpio35: rgmii-gpio35 { pin-start-stop { pins = "gpio35"; function = "alt4"; @@ -914,26 +915,26 @@ function = "alt4"; }; }; - rgmii_irq_gpio34: rgmii_irq_gpio34 { + rgmii_irq_gpio34: rgmii-irq-gpio34 { pin-irq { pins = "gpio34"; function = "alt5"; }; }; - rgmii_irq_gpio39: rgmii_irq_gpio39 { + rgmii_irq_gpio39: rgmii-irq-gpio39 { pin-irq { pins = "gpio39"; function = "alt4"; }; }; - rgmii_mdio_gpio28: rgmii_mdio_gpio28 { + rgmii_mdio_gpio28: rgmii-mdio-gpio28 { pins-mdio { pins = "gpio28", "gpio29"; function = "alt5"; }; }; - rgmii_mdio_gpio37: rgmii_mdio_gpio37 { + rgmii_mdio_gpio37: rgmii-mdio-gpio37 { pins-mdio { pins = "gpio37", "gpio38"; @@ -941,7 +942,7 @@ }; }; - spi0_gpio46: spi0_gpio46 { + spi0_gpio46: spi0-gpio46 { pins-spi { pins = "gpio46", "gpio47", @@ -950,7 +951,7 @@ function = "alt2"; }; }; - spi2_gpio46: spi2_gpio46 { + spi2_gpio46: spi2-gpio46 { pins-spi { pins = "gpio46", "gpio47", @@ -960,7 +961,7 @@ function = "alt5"; }; }; - spi3_gpio0: spi3_gpio0 { + spi3_gpio0: spi3-gpio0 { pins-spi { pins = "gpio0", "gpio1", @@ -969,7 +970,7 @@ function = "alt3"; }; }; - spi4_gpio4: spi4_gpio4 { + spi4_gpio4: spi4-gpio4 { pins-spi { pins = "gpio4", "gpio5", @@ -978,7 +979,7 @@ function = "alt3"; }; }; - spi5_gpio12: spi5_gpio12 { + spi5_gpio12: spi5-gpio12 { pins-spi { pins = "gpio12", "gpio13", @@ -987,7 +988,7 @@ function = "alt3"; }; }; - spi6_gpio18: spi6_gpio18 { + spi6_gpio18: spi6-gpio18 { pins-spi { pins = "gpio18", "gpio19", @@ -997,7 +998,7 @@ }; }; - uart2_gpio0: uart2_gpio0 { + uart2_gpio0: uart2-gpio0 { pin-tx { pins = "gpio0"; function = "alt4"; @@ -1009,7 +1010,7 @@ bias-pull-up; }; }; - uart2_ctsrts_gpio2: uart2_ctsrts_gpio2 { + uart2_ctsrts_gpio2: uart2-ctsrts-gpio2 { pin-cts { pins = "gpio2"; function = "alt4"; @@ -1021,7 +1022,7 @@ bias-disable; }; }; - uart3_gpio4: uart3_gpio4 { + uart3_gpio4: uart3-gpio4 { pin-tx { pins = "gpio4"; function = "alt4"; @@ -1033,7 +1034,7 @@ bias-pull-up; }; }; - uart3_ctsrts_gpio6: uart3_ctsrts_gpio6 { + uart3_ctsrts_gpio6: uart3-ctsrts-gpio6 { pin-cts { pins = "gpio6"; function = "alt4"; @@ -1045,7 +1046,7 @@ bias-disable; }; }; - uart4_gpio8: uart4_gpio8 { + uart4_gpio8: uart4-gpio8 { pin-tx { pins = "gpio8"; function = "alt4"; @@ -1057,7 +1058,7 @@ bias-pull-up; }; }; - uart4_ctsrts_gpio10: uart4_ctsrts_gpio10 { + uart4_ctsrts_gpio10: uart4-ctsrts-gpio10 { pin-cts { pins = "gpio10"; function = "alt4"; @@ -1069,7 +1070,7 @@ bias-disable; }; }; - uart5_gpio12: uart5_gpio12 { + uart5_gpio12: uart5-gpio12 { pin-tx { pins = "gpio12"; function = "alt4"; @@ -1081,7 +1082,7 @@ bias-pull-up; }; }; - uart5_ctsrts_gpio14: uart5_ctsrts_gpio14 { + uart5_ctsrts_gpio14: uart5-ctsrts-gpio14 { pin-cts { pins = "gpio14"; function = "alt4"; diff --git a/arch/arm/boot/dts/bcm2835-common.dtsi b/arch/arm/boot/dts/bcm2835-common.dtsi index a037d2bc5b11..bb7e8f7facaf 100644 --- a/arch/arm/boot/dts/bcm2835-common.dtsi +++ b/arch/arm/boot/dts/bcm2835-common.dtsi @@ -152,41 +152,41 @@ }; &gpio { - i2c_slave_gpio18: i2c_slave_gpio18 { + i2c_slave_gpio18: i2c-slave-gpio18 { brcm,pins = <18 19 20 21>; brcm,function = <BCM2835_FSEL_ALT3>; }; - jtag_gpio4: jtag_gpio4 { + jtag_gpio4: jtag-gpio4 { brcm,pins = <4 5 6 12 13>; brcm,function = <BCM2835_FSEL_ALT5>; }; - pwm0_gpio12: pwm0_gpio12 { + pwm0_gpio12: pwm0-gpio12 { brcm,pins = <12>; brcm,function = <BCM2835_FSEL_ALT0>; }; - pwm0_gpio18: pwm0_gpio18 { + pwm0_gpio18: pwm0-gpio18 { brcm,pins = <18>; brcm,function = <BCM2835_FSEL_ALT5>; }; - pwm0_gpio40: pwm0_gpio40 { + pwm0_gpio40: pwm0-gpio40 { brcm,pins = <40>; brcm,function = <BCM2835_FSEL_ALT0>; }; - pwm1_gpio13: pwm1_gpio13 { + pwm1_gpio13: pwm1-gpio13 { brcm,pins = <13>; brcm,function = <BCM2835_FSEL_ALT0>; }; - pwm1_gpio19: pwm1_gpio19 { + pwm1_gpio19: pwm1-gpio19 { brcm,pins = <19>; brcm,function = <BCM2835_FSEL_ALT5>; }; - pwm1_gpio41: pwm1_gpio41 { + pwm1_gpio41: pwm1-gpio41 { brcm,pins = <41>; brcm,function = <BCM2835_FSEL_ALT0>; }; - pwm1_gpio45: pwm1_gpio45 { + pwm1_gpio45: pwm1-gpio45 { brcm,pins = <45>; brcm,function = <BCM2835_FSEL_ALT0>; }; diff --git a/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts index 9b9a18bbb20a..02ce817868ba 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts @@ -2,6 +2,8 @@ /dts-v1/; #include "bcm2835.dtsi" #include "bcm2835-rpi.dtsi" +#include "bcm2835-rpi-common.dtsi" +#include "bcm283x-rpi-led-deprecated.dtsi" #include "bcm283x-rpi-usb-host.dtsi" / { @@ -12,19 +14,6 @@ device_type = "memory"; reg = <0 0x10000000>; }; - - leds { - led-act { - gpios = <&gpio 47 GPIO_ACTIVE_HIGH>; - }; - - led-pwr { - label = "PWR"; - gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - linux,default-trigger = "default-on"; - }; - }; }; &gpio { @@ -107,6 +96,19 @@ status = "okay"; }; +&led_act { + gpios = <&gpio 47 GPIO_ACTIVE_HIGH>; +}; + +&leds { + led-pwr { + label = "PWR"; + gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + linux,default-trigger = "default-on"; + }; +}; + &pwm { pinctrl-names = "default"; pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio45>; diff --git a/arch/arm/boot/dts/bcm2835-rpi-a.dts b/arch/arm/boot/dts/bcm2835-rpi-a.dts index f664e4fced93..3fdf60eb11dc 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-a.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-a.dts @@ -2,6 +2,8 @@ /dts-v1/; #include "bcm2835.dtsi" #include "bcm2835-rpi.dtsi" +#include "bcm2835-rpi-common.dtsi" +#include "bcm283x-rpi-led-deprecated.dtsi" #include "bcm283x-rpi-usb-host.dtsi" / { @@ -12,12 +14,6 @@ device_type = "memory"; reg = <0 0x10000000>; }; - - leds { - led-act { - gpios = <&gpio 16 GPIO_ACTIVE_LOW>; - }; - }; }; &gpio { @@ -102,6 +98,10 @@ status = "okay"; }; +&led_act { + gpios = <&gpio 16 GPIO_ACTIVE_LOW>; +}; + &pwm { pinctrl-names = "default"; pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio45>; diff --git a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts index 248feb2ed23d..9956fd06a4b6 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts @@ -2,6 +2,8 @@ /dts-v1/; #include "bcm2835.dtsi" #include "bcm2835-rpi.dtsi" +#include "bcm2835-rpi-common.dtsi" +#include "bcm283x-rpi-led-deprecated.dtsi" #include "bcm283x-rpi-smsc9514.dtsi" #include "bcm283x-rpi-usb-host.dtsi" @@ -13,19 +15,6 @@ device_type = "memory"; reg = <0 0x20000000>; }; - - leds { - led-act { - gpios = <&gpio 47 GPIO_ACTIVE_HIGH>; - }; - - led-pwr { - label = "PWR"; - gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - linux,default-trigger = "default-on"; - }; - }; }; &gpio { @@ -109,6 +98,19 @@ status = "okay"; }; +&led_act { + gpios = <&gpio 47 GPIO_ACTIVE_HIGH>; +}; + +&leds { + led-pwr { + label = "PWR"; + gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + linux,default-trigger = "default-on"; + }; +}; + &pwm { pinctrl-names = "default"; pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio45>; diff --git a/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts b/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts index f5b66d3f4ff3..4e1770afb145 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts @@ -2,6 +2,8 @@ /dts-v1/; #include "bcm2835.dtsi" #include "bcm2835-rpi.dtsi" +#include "bcm2835-rpi-common.dtsi" +#include "bcm283x-rpi-led-deprecated.dtsi" #include "bcm283x-rpi-smsc9512.dtsi" #include "bcm283x-rpi-usb-host.dtsi" @@ -13,12 +15,6 @@ device_type = "memory"; reg = <0 0x10000000>; }; - - leds { - led-act { - gpios = <&gpio 16 GPIO_ACTIVE_LOW>; - }; - }; }; &gpio { @@ -102,6 +98,10 @@ status = "okay"; }; +&led_act { + gpios = <&gpio 16 GPIO_ACTIVE_LOW>; +}; + &pwm { pinctrl-names = "default"; pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio45>; diff --git a/arch/arm/boot/dts/bcm2835-rpi-b.dts b/arch/arm/boot/dts/bcm2835-rpi-b.dts index f589bede2b11..eec1d0892d33 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-b.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-b.dts @@ -2,6 +2,8 @@ /dts-v1/; #include "bcm2835.dtsi" #include "bcm2835-rpi.dtsi" +#include "bcm2835-rpi-common.dtsi" +#include "bcm283x-rpi-led-deprecated.dtsi" #include "bcm283x-rpi-smsc9512.dtsi" #include "bcm283x-rpi-usb-host.dtsi" @@ -13,12 +15,6 @@ device_type = "memory"; reg = <0 0x10000000>; }; - - leds { - led-act { - gpios = <&gpio 16 GPIO_ACTIVE_LOW>; - }; - }; }; &gpio { @@ -96,6 +92,10 @@ status = "okay"; }; +&led_act { + gpios = <&gpio 16 GPIO_ACTIVE_LOW>; +}; + &pwm { pinctrl-names = "default"; pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio45>; diff --git a/arch/arm/boot/dts/bcm2835-rpi-cm1.dtsi b/arch/arm/boot/dts/bcm2835-rpi-cm1.dtsi index e4e6b6abbfc1..750cd76948e3 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-cm1.dtsi +++ b/arch/arm/boot/dts/bcm2835-rpi-cm1.dtsi @@ -2,6 +2,8 @@ /dts-v1/; #include "bcm2835.dtsi" #include "bcm2835-rpi.dtsi" +#include "bcm2835-rpi-common.dtsi" +#include "bcm283x-rpi-led-deprecated.dtsi" / { leds { @@ -32,6 +34,10 @@ }; }; +&led_act { + gpios = <&gpio 47 GPIO_ACTIVE_LOW>; +}; + &sdhost { non-removable; vmmc-supply = <®_3v3>; diff --git a/arch/arm/boot/dts/bcm2835-rpi-common.dtsi b/arch/arm/boot/dts/bcm2835-rpi-common.dtsi index 8a55b6cded59..4e7b4a592da7 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-common.dtsi +++ b/arch/arm/boot/dts/bcm2835-rpi-common.dtsi @@ -7,6 +7,23 @@ #include <dt-bindings/power/raspberrypi-power.h> +&firmware { + firmware_clocks: clocks { + compatible = "raspberrypi,firmware-clocks"; + #clock-cells = <1>; + }; +}; + +&hdmi { + clocks = <&firmware_clocks 9>, + <&firmware_clocks 13>; + clock-names = "pixel", "hdmi"; +}; + &v3d { power-domains = <&power RPI_POWER_DOMAIN_V3D>; }; + +&vec { + clocks = <&firmware_clocks 15>; +}; diff --git a/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts b/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts index 596bb1ef994e..dbf825985ec0 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts @@ -6,6 +6,8 @@ /dts-v1/; #include "bcm2835.dtsi" #include "bcm2835-rpi.dtsi" +#include "bcm2835-rpi-common.dtsi" +#include "bcm283x-rpi-led-deprecated.dtsi" #include "bcm283x-rpi-usb-otg.dtsi" #include "bcm283x-rpi-wifi-bt.dtsi" @@ -22,12 +24,6 @@ /* 8250 auxiliary UART instead of pl011 */ stdout-path = "serial1:115200n8"; }; - - leds { - led-act { - gpios = <&gpio 47 GPIO_ACTIVE_LOW>; - }; - }; }; &bt { @@ -110,6 +106,10 @@ status = "okay"; }; +&led_act { + gpios = <&gpio 47 GPIO_ACTIVE_LOW>; +}; + &sdhci { pinctrl-0 = <&emmc_gpio34 &gpclk2_gpio43>; }; diff --git a/arch/arm/boot/dts/bcm2835-rpi-zero.dts b/arch/arm/boot/dts/bcm2835-rpi-zero.dts index a65c2bca69ea..f80e65a825fd 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-zero.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-zero.dts @@ -6,6 +6,8 @@ /dts-v1/; #include "bcm2835.dtsi" #include "bcm2835-rpi.dtsi" +#include "bcm2835-rpi-common.dtsi" +#include "bcm283x-rpi-led-deprecated.dtsi" #include "bcm283x-rpi-usb-otg.dtsi" / { @@ -16,12 +18,6 @@ device_type = "memory"; reg = <0 0x20000000>; }; - - leds { - led-act { - gpios = <&gpio 47 GPIO_ACTIVE_HIGH>; - }; - }; }; &gpio { @@ -104,6 +100,10 @@ status = "okay"; }; +&led_act { + gpios = <&gpio 47 GPIO_ACTIVE_HIGH>; +}; + &sdhost { pinctrl-names = "default"; pinctrl-0 = <&sdhost_gpio48>; diff --git a/arch/arm/boot/dts/bcm2835-rpi.dtsi b/arch/arm/boot/dts/bcm2835-rpi.dtsi index 87ddcad76083..ee9ee9d1fe65 100644 --- a/arch/arm/boot/dts/bcm2835-rpi.dtsi +++ b/arch/arm/boot/dts/bcm2835-rpi.dtsi @@ -1,16 +1,6 @@ #include <dt-bindings/power/raspberrypi-power.h> / { - leds { - compatible = "gpio-leds"; - - led-act { - label = "ACT"; - default-state = "keep"; - linux,default-trigger = "heartbeat"; - }; - }; - soc { firmware: firmware { compatible = "raspberrypi,bcm2835-firmware", "simple-mfd"; diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi index 1c90e5a44283..15cb331febbb 100644 --- a/arch/arm/boot/dts/bcm2835.dtsi +++ b/arch/arm/boot/dts/bcm2835.dtsi @@ -1,7 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 #include "bcm283x.dtsi" #include "bcm2835-common.dtsi" -#include "bcm2835-rpi-common.dtsi" / { compatible = "brcm,bcm2835"; diff --git a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts index 3635502b1e0a..6068ec390081 100644 --- a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts +++ b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts @@ -2,6 +2,7 @@ /dts-v1/; #include "bcm2836.dtsi" #include "bcm2836-rpi.dtsi" +#include "bcm283x-rpi-led-deprecated.dtsi" #include "bcm283x-rpi-smsc9514.dtsi" #include "bcm283x-rpi-usb-host.dtsi" @@ -13,19 +14,6 @@ device_type = "memory"; reg = <0 0x40000000>; }; - - leds { - led-act { - gpios = <&gpio 47 GPIO_ACTIVE_HIGH>; - }; - - led-pwr { - label = "PWR"; - gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; - default-state = "keep"; - linux,default-trigger = "default-on"; - }; - }; }; &gpio { @@ -109,6 +97,19 @@ status = "okay"; }; +&led_act { + gpios = <&gpio 47 GPIO_ACTIVE_HIGH>; +}; + +&leds { + led-pwr { + label = "PWR"; + gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + linux,default-trigger = "default-on"; + }; +}; + &pwm { pinctrl-names = "default"; pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio45>; diff --git a/arch/arm/boot/dts/bcm2836-rpi.dtsi b/arch/arm/boot/dts/bcm2836-rpi.dtsi index c4c858b984c6..48b03b55ff56 100644 --- a/arch/arm/boot/dts/bcm2836-rpi.dtsi +++ b/arch/arm/boot/dts/bcm2836-rpi.dtsi @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 #include "bcm2835-rpi.dtsi" +#include "bcm2835-rpi-common.dtsi" &vchiq { compatible = "brcm,bcm2836-vchiq", "brcm,bcm2835-vchiq"; diff --git a/arch/arm/boot/dts/bcm2836.dtsi b/arch/arm/boot/dts/bcm2836.dtsi index 534dacfc4dd5..783fe624ba68 100644 --- a/arch/arm/boot/dts/bcm2836.dtsi +++ b/arch/arm/boot/dts/bcm2836.dtsi @@ -1,7 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 #include "bcm283x.dtsi" #include "bcm2835-common.dtsi" -#include "bcm2835-rpi-common.dtsi" / { compatible = "brcm,bcm2836"; @@ -11,7 +10,7 @@ <0x40000000 0x40000000 0x00001000>; dma-ranges = <0xc0000000 0x00000000 0x3f000000>; - local_intc: local_intc@40000000 { + local_intc: interrupt-controller@40000000 { compatible = "brcm,bcm2836-l1-intc"; reg = <0x40000000 0x100>; interrupt-controller; @@ -113,6 +112,7 @@ */ l2: l2-cache0 { compatible = "cache"; + cache-unified; cache-size = <0x80000>; cache-line-size = <64>; cache-sets = <1024>; // 512KiB(size)/64(line-size)=8192ways/8-way set diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts b/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts index f7222a28903e..3548306dfbcb 100644 --- a/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts +++ b/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts @@ -2,6 +2,7 @@ /dts-v1/; #include "bcm2837.dtsi" #include "bcm2836-rpi.dtsi" +#include "bcm283x-rpi-led-deprecated.dtsi" #include "bcm283x-rpi-usb-host.dtsi" #include "bcm283x-rpi-wifi-bt.dtsi" @@ -18,19 +19,6 @@ device_type = "memory"; reg = <0 0x20000000>; }; - - leds { - led-act { - gpios = <&gpio 29 GPIO_ACTIVE_HIGH>; - }; - - led-pwr { - label = "PWR"; - gpios = <&expgpio 2 GPIO_ACTIVE_LOW>; - default-state = "keep"; - linux,default-trigger = "default-on"; - }; - }; }; &firmware { @@ -124,6 +112,19 @@ status = "okay"; }; +&led_act { + gpios = <&gpio 29 GPIO_ACTIVE_HIGH>; +}; + +&leds { + led-pwr { + label = "PWR"; + gpios = <&expgpio 2 GPIO_ACTIVE_LOW>; + default-state = "keep"; + linux,default-trigger = "default-on"; + }; +}; + &pwm { pinctrl-names = "default"; pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio41>; diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts b/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts index ec721d323ac5..2f1800cbc522 100644 --- a/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts +++ b/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts @@ -3,6 +3,7 @@ #include "bcm2837.dtsi" #include "bcm2836-rpi.dtsi" #include "bcm283x-rpi-lan7515.dtsi" +#include "bcm283x-rpi-led-deprecated.dtsi" #include "bcm283x-rpi-usb-host.dtsi" #include "bcm283x-rpi-wifi-bt.dtsi" @@ -19,19 +20,6 @@ device_type = "memory"; reg = <0 0x40000000>; }; - - leds { - led-act { - gpios = <&gpio 29 GPIO_ACTIVE_HIGH>; - }; - - led-pwr { - label = "PWR"; - gpios = <&expgpio 2 GPIO_ACTIVE_LOW>; - default-state = "keep"; - linux,default-trigger = "default-on"; - }; - }; }; &bt { @@ -130,6 +118,19 @@ status = "okay"; }; +&led_act { + gpios = <&gpio 29 GPIO_ACTIVE_HIGH>; +}; + +&leds { + led-pwr { + label = "PWR"; + gpios = <&expgpio 2 GPIO_ACTIVE_LOW>; + default-state = "keep"; + linux,default-trigger = "default-on"; + }; +}; + &pwm { pinctrl-names = "default"; pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio41>; diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts index fb6a417d73e7..61270340075c 100644 --- a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts +++ b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts @@ -2,6 +2,7 @@ /dts-v1/; #include "bcm2837.dtsi" #include "bcm2836-rpi.dtsi" +#include "bcm283x-rpi-led-deprecated.dtsi" #include "bcm283x-rpi-smsc9514.dtsi" #include "bcm283x-rpi-usb-host.dtsi" #include "bcm283x-rpi-wifi-bt.dtsi" @@ -19,12 +20,6 @@ device_type = "memory"; reg = <0 0x40000000>; }; - - leds { - led-act { - gpios = <&expgpio 2 GPIO_ACTIVE_HIGH>; - }; - }; }; &bt { @@ -129,6 +124,10 @@ status = "okay"; }; +&led_act { + gpios = <&expgpio 2 GPIO_ACTIVE_HIGH>; +}; + /* uart0 communicates with the BT module */ &uart0 { pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi b/arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi index f57b4ca145dd..1e4e4946b6b6 100644 --- a/arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi +++ b/arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi @@ -9,14 +9,6 @@ reg = <0 0x40000000>; }; - leds { - /* - * Since there is no upstream GPIO driver yet, - * remove the incomplete node. - */ - /delete-node/ led-act; - }; - reg_3v3: fixed-regulator { compatible = "regulator-fixed"; regulator-name = "3V3"; diff --git a/arch/arm/boot/dts/bcm2837-rpi-zero-2-w.dts b/arch/arm/boot/dts/bcm2837-rpi-zero-2-w.dts index 4a768562985e..b9cc4594398b 100644 --- a/arch/arm/boot/dts/bcm2837-rpi-zero-2-w.dts +++ b/arch/arm/boot/dts/bcm2837-rpi-zero-2-w.dts @@ -6,6 +6,7 @@ /dts-v1/; #include "bcm2837.dtsi" #include "bcm2836-rpi.dtsi" +#include "bcm283x-rpi-led-deprecated.dtsi" #include "bcm283x-rpi-usb-otg.dtsi" #include "bcm283x-rpi-wifi-bt.dtsi" @@ -22,12 +23,6 @@ /* 8250 auxiliary UART instead of pl011 */ stdout-path = "serial1:115200n8"; }; - - leds { - led-act { - gpios = <&gpio 29 GPIO_ACTIVE_LOW>; - }; - }; }; &bt { @@ -109,6 +104,10 @@ status = "okay"; }; +&led_act { + gpios = <&gpio 29 GPIO_ACTIVE_LOW>; +}; + &sdhci { pinctrl-0 = <&emmc_gpio34 &gpclk2_gpio43>; }; diff --git a/arch/arm/boot/dts/bcm2837.dtsi b/arch/arm/boot/dts/bcm2837.dtsi index 5dbdebc46259..84c08b46519d 100644 --- a/arch/arm/boot/dts/bcm2837.dtsi +++ b/arch/arm/boot/dts/bcm2837.dtsi @@ -1,6 +1,5 @@ #include "bcm283x.dtsi" #include "bcm2835-common.dtsi" -#include "bcm2835-rpi-common.dtsi" / { compatible = "brcm,bcm2837"; @@ -115,6 +114,7 @@ */ l2: l2-cache0 { compatible = "cache"; + cache-unified; cache-size = <0x80000>; cache-line-size = <64>; cache-sets = <512>; // 512KiB(size)/64(line-size)=8192ways/16-way set diff --git a/arch/arm/boot/dts/bcm283x-rpi-led-deprecated.dtsi b/arch/arm/boot/dts/bcm283x-rpi-led-deprecated.dtsi new file mode 100644 index 000000000000..f83e56de1a72 --- /dev/null +++ b/arch/arm/boot/dts/bcm283x-rpi-led-deprecated.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0 + +/ { + /* + * This file provides the now deprecated ACT LED to the + * Raspberry Pi boards. Please don't include this file + * for new boards! + */ + leds: leds { + compatible = "gpio-leds"; + + led_act: led-act { + label = "ACT"; + default-state = "keep"; + linux,default-trigger = "heartbeat"; + }; + }; +}; diff --git a/arch/arm/boot/dts/bcm283x.dtsi b/arch/arm/boot/dts/bcm283x.dtsi index d2d9c6e67f39..c9c52a19ef3b 100644 --- a/arch/arm/boot/dts/bcm283x.dtsi +++ b/arch/arm/boot/dts/bcm283x.dtsi @@ -135,17 +135,17 @@ * groups only make sense to switch to a * particular function together. */ - dpi_gpio0: dpi_gpio0 { + dpi_gpio0: dpi-gpio0 { brcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27>; brcm,function = <BCM2835_FSEL_ALT2>; }; - emmc_gpio22: emmc_gpio22 { + emmc_gpio22: emmc-gpio22 { brcm,pins = <22 23 24 25 26 27>; brcm,function = <BCM2835_FSEL_ALT3>; }; - emmc_gpio34: emmc_gpio34 { + emmc_gpio34: emmc-gpio34 { brcm,pins = <34 35 36 37 38 39>; brcm,function = <BCM2835_FSEL_ALT3>; brcm,pull = <BCM2835_PUD_OFF @@ -155,95 +155,95 @@ BCM2835_PUD_UP BCM2835_PUD_UP>; }; - emmc_gpio48: emmc_gpio48 { + emmc_gpio48: emmc-gpio48 { brcm,pins = <48 49 50 51 52 53>; brcm,function = <BCM2835_FSEL_ALT3>; }; - gpclk0_gpio4: gpclk0_gpio4 { + gpclk0_gpio4: gpclk0-gpio4 { brcm,pins = <4>; brcm,function = <BCM2835_FSEL_ALT0>; }; - gpclk1_gpio5: gpclk1_gpio5 { + gpclk1_gpio5: gpclk1-gpio5 { brcm,pins = <5>; brcm,function = <BCM2835_FSEL_ALT0>; }; - gpclk1_gpio42: gpclk1_gpio42 { + gpclk1_gpio42: gpclk1-gpio42 { brcm,pins = <42>; brcm,function = <BCM2835_FSEL_ALT0>; }; - gpclk1_gpio44: gpclk1_gpio44 { + gpclk1_gpio44: gpclk1-gpio44 { brcm,pins = <44>; brcm,function = <BCM2835_FSEL_ALT0>; }; - gpclk2_gpio6: gpclk2_gpio6 { + gpclk2_gpio6: gpclk2-gpio6 { brcm,pins = <6>; brcm,function = <BCM2835_FSEL_ALT0>; }; - gpclk2_gpio43: gpclk2_gpio43 { + gpclk2_gpio43: gpclk2-gpio43 { brcm,pins = <43>; brcm,function = <BCM2835_FSEL_ALT0>; brcm,pull = <BCM2835_PUD_OFF>; }; - i2c0_gpio0: i2c0_gpio0 { + i2c0_gpio0: i2c0-gpio0 { brcm,pins = <0 1>; brcm,function = <BCM2835_FSEL_ALT0>; }; - i2c0_gpio28: i2c0_gpio28 { + i2c0_gpio28: i2c0-gpio28 { brcm,pins = <28 29>; brcm,function = <BCM2835_FSEL_ALT0>; }; - i2c0_gpio44: i2c0_gpio44 { + i2c0_gpio44: i2c0-gpio44 { brcm,pins = <44 45>; brcm,function = <BCM2835_FSEL_ALT1>; }; - i2c1_gpio2: i2c1_gpio2 { + i2c1_gpio2: i2c1-gpio2 { brcm,pins = <2 3>; brcm,function = <BCM2835_FSEL_ALT0>; }; - i2c1_gpio44: i2c1_gpio44 { + i2c1_gpio44: i2c1-gpio44 { brcm,pins = <44 45>; brcm,function = <BCM2835_FSEL_ALT2>; }; - jtag_gpio22: jtag_gpio22 { + jtag_gpio22: jtag-gpio22 { brcm,pins = <22 23 24 25 26 27>; brcm,function = <BCM2835_FSEL_ALT4>; }; - pcm_gpio18: pcm_gpio18 { + pcm_gpio18: pcm-gpio18 { brcm,pins = <18 19 20 21>; brcm,function = <BCM2835_FSEL_ALT0>; }; - pcm_gpio28: pcm_gpio28 { + pcm_gpio28: pcm-gpio28 { brcm,pins = <28 29 30 31>; brcm,function = <BCM2835_FSEL_ALT2>; }; - sdhost_gpio48: sdhost_gpio48 { + sdhost_gpio48: sdhost-gpio48 { brcm,pins = <48 49 50 51 52 53>; brcm,function = <BCM2835_FSEL_ALT0>; }; - spi0_gpio7: spi0_gpio7 { + spi0_gpio7: spi0-gpio7 { brcm,pins = <7 8 9 10 11>; brcm,function = <BCM2835_FSEL_ALT0>; }; - spi0_gpio35: spi0_gpio35 { + spi0_gpio35: spi0-gpio35 { brcm,pins = <35 36 37 38 39>; brcm,function = <BCM2835_FSEL_ALT0>; }; - spi1_gpio16: spi1_gpio16 { + spi1_gpio16: spi1-gpio16 { brcm,pins = <16 17 18 19 20 21>; brcm,function = <BCM2835_FSEL_ALT4>; }; - spi2_gpio40: spi2_gpio40 { + spi2_gpio40: spi2-gpio40 { brcm,pins = <40 41 42 43 44 45>; brcm,function = <BCM2835_FSEL_ALT4>; }; - uart0_gpio14: uart0_gpio14 { + uart0_gpio14: uart0-gpio14 { brcm,pins = <14 15>; brcm,function = <BCM2835_FSEL_ALT0>; }; @@ -252,50 +252,50 @@ * people often run uart0 on the two pins * without flow control. */ - uart0_ctsrts_gpio16: uart0_ctsrts_gpio16 { + uart0_ctsrts_gpio16: uart0-ctsrts-gpio16 { brcm,pins = <16 17>; brcm,function = <BCM2835_FSEL_ALT3>; }; - uart0_ctsrts_gpio30: uart0_ctsrts_gpio30 { + uart0_ctsrts_gpio30: uart0-ctsrts-gpio30 { brcm,pins = <30 31>; brcm,function = <BCM2835_FSEL_ALT3>; brcm,pull = <BCM2835_PUD_UP BCM2835_PUD_OFF>; }; - uart0_gpio32: uart0_gpio32 { + uart0_gpio32: uart0-gpio32 { brcm,pins = <32 33>; brcm,function = <BCM2835_FSEL_ALT3>; brcm,pull = <BCM2835_PUD_OFF BCM2835_PUD_UP>; }; - uart0_gpio36: uart0_gpio36 { + uart0_gpio36: uart0-gpio36 { brcm,pins = <36 37>; brcm,function = <BCM2835_FSEL_ALT2>; }; - uart0_ctsrts_gpio38: uart0_ctsrts_gpio38 { + uart0_ctsrts_gpio38: uart0-ctsrts-gpio38 { brcm,pins = <38 39>; brcm,function = <BCM2835_FSEL_ALT2>; }; - uart1_gpio14: uart1_gpio14 { + uart1_gpio14: uart1-gpio14 { brcm,pins = <14 15>; brcm,function = <BCM2835_FSEL_ALT5>; }; - uart1_ctsrts_gpio16: uart1_ctsrts_gpio16 { + uart1_ctsrts_gpio16: uart1-ctsrts-gpio16 { brcm,pins = <16 17>; brcm,function = <BCM2835_FSEL_ALT5>; }; - uart1_gpio32: uart1_gpio32 { + uart1_gpio32: uart1-gpio32 { brcm,pins = <32 33>; brcm,function = <BCM2835_FSEL_ALT5>; }; - uart1_ctsrts_gpio30: uart1_ctsrts_gpio30 { + uart1_ctsrts_gpio30: uart1-ctsrts-gpio30 { brcm,pins = <30 31>; brcm,function = <BCM2835_FSEL_ALT5>; }; - uart1_gpio40: uart1_gpio40 { + uart1_gpio40: uart1-gpio40 { brcm,pins = <40 41>; brcm,function = <BCM2835_FSEL_ALT5>; }; - uart1_ctsrts_gpio42: uart1_ctsrts_gpio42 { + uart1_ctsrts_gpio42: uart1-ctsrts-gpio42 { brcm,pins = <42 43>; brcm,function = <BCM2835_FSEL_ALT5>; }; diff --git a/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts b/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts index 09ee3e46c0cc..c80ac16ad949 100644 --- a/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts +++ b/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts @@ -28,40 +28,39 @@ leds { compatible = "gpio-leds"; - usb3 { + led-usb3 { label = "bcm53xx:blue:usb3"; gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; }; - wan { + led-wan { label = "bcm53xx:blue:wan"; gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; }; - lan { + led-lan { label = "bcm53xx:blue:lan"; gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; }; - power { + led-power { label = "bcm53xx:blue:power"; gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; linux,default-trigger = "default-on"; }; - all { + led-all { label = "bcm53xx:blue:all"; gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; linux,default-trigger = "default-on"; }; - 2ghz { + led-2ghz { label = "bcm53xx:blue:2ghz"; gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; }; - - usb2 { + led-usb2 { label = "bcm53xx:blue:usb2"; gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts b/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts index 32619c6045d3..3fe17bd7b86d 100644 --- a/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts +++ b/arch/arm/boot/dts/bcm4708-asus-rt-ac68u.dts @@ -28,24 +28,24 @@ leds { compatible = "gpio-leds"; - usb2 { + led-usb2 { label = "bcm53xx:blue:usb2"; gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; }; - power { + led-power { label = "bcm53xx:blue:power"; gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; linux,default-trigger = "default-on"; }; - logo { + led-logo { label = "bcm53xx:white:logo"; gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; linux,default-trigger = "default-on"; }; - usb3 { + led-usb3 { label = "bcm53xx:blue:usb3"; gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp-common.dtsi b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp-common.dtsi index a658b9b7bcec..e583b9cbf07c 100644 --- a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp-common.dtsi +++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp-common.dtsi @@ -37,7 +37,7 @@ leds { compatible = "gpio-leds"; - usb { + led-usb { /* label = "bcm53xx:blue:usb"; */ function = LED_FUNCTION_USB; color = <LED_COLOR_ID_BLUE>; @@ -48,14 +48,14 @@ linux,default-trigger = "usbport"; }; - power0 { + led-power0 { /* label = "bcm53xx:red:power"; */ function = LED_FUNCTION_FAULT; color = <LED_COLOR_ID_RED>; gpios = <&hc595 1 GPIO_ACTIVE_HIGH>; }; - power1 { + led-power1 { /* label = "bcm53xx:white:power"; */ function = LED_FUNCTION_POWER; color = <LED_COLOR_ID_WHITE>; @@ -63,7 +63,7 @@ linux,default-trigger = "default-on"; }; - router0 { + led-router0 { /* label = "bcm53xx:blue:router"; */ function = LED_FUNCTION_STATUS; color = <LED_COLOR_ID_BLUE>; @@ -71,14 +71,14 @@ linux,default-trigger = "default-on"; }; - router1 { + led-router1 { /* label = "bcm53xx:amber:router"; */ function = LED_FUNCTION_STATUS; color = <LED_COLOR_ID_AMBER>; gpios = <&hc595 4 GPIO_ACTIVE_HIGH>; }; - wan { + led-wan { /* label = "bcm53xx:blue:wan"; */ function = LED_FUNCTION_WAN; color = <LED_COLOR_ID_BLUE>; @@ -86,14 +86,14 @@ linux,default-trigger = "default-on"; }; - wireless0 { + led-wireless0 { /* label = "bcm53xx:blue:wireless"; */ function = LED_FUNCTION_WLAN; color = <LED_COLOR_ID_BLUE>; gpios = <&hc595 6 GPIO_ACTIVE_HIGH>; }; - wireless1 { + led-wireless1 { /* label = "bcm53xx:amber:wireless"; */ function = LED_FUNCTION_WLAN; color = <LED_COLOR_ID_AMBER>; diff --git a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts index f8f53457dd43..43c698a0a7c3 100644 --- a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts +++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts @@ -49,7 +49,7 @@ leds { compatible = "gpio-leds"; - usb { + led-usb { label = "bcm53xx:blue:usb"; gpios = <&hc595 0 GPIO_ACTIVE_HIGH>; trigger-sources = <&ohci_port1>, <&ehci_port1>, @@ -58,40 +58,40 @@ linux,default-trigger = "usbport"; }; - power0 { + led-power0 { label = "bcm53xx:red:power"; gpios = <&hc595 1 GPIO_ACTIVE_HIGH>; }; - power1 { + led-power1 { label = "bcm53xx:white:power"; gpios = <&hc595 2 GPIO_ACTIVE_HIGH>; linux,default-trigger = "default-on"; }; - router0 { + led-router0 { label = "bcm53xx:blue:router"; gpios = <&hc595 3 GPIO_ACTIVE_HIGH>; linux,default-trigger = "default-on"; }; - router1 { + led-router1 { label = "bcm53xx:amber:router"; gpios = <&hc595 4 GPIO_ACTIVE_HIGH>; }; - wan { + led-wan { label = "bcm53xx:blue:wan"; gpios = <&hc595 5 GPIO_ACTIVE_HIGH>; linux,default-trigger = "default-on"; }; - wireless0 { + led-wireless0 { label = "bcm53xx:blue:wireless"; gpios = <&hc595 6 GPIO_ACTIVE_HIGH>; }; - wireless1 { + led-wireless1 { label = "bcm53xx:amber:wireless"; gpios = <&hc595 7 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts b/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts index 14ee410183af..6de7fe204b0c 100644 --- a/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts +++ b/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts @@ -23,19 +23,19 @@ leds { compatible = "gpio-leds"; - 5ghz { + led-5ghz { label = "bcm53xx:blue:5ghz"; gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; linux,default-trigger = "none"; }; - 2ghz { + led-2ghz { label = "bcm53xx:blue:2ghz"; gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; linux,default-trigger = "none"; }; - status { + led-status { label = "bcm53xx:green:status"; gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; linux,default-trigger = "timer"; diff --git a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts b/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts index 600ab087f5e5..f5b75ba93512 100644 --- a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts +++ b/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts @@ -42,7 +42,7 @@ leds { compatible = "gpio-leds"; - status { + led-status { label = "bcm53xx:green:status"; gpios = <&chipcommon 0 GPIO_ACTIVE_HIGH>; linux,default-trigger = "timer"; diff --git a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts index fd6d8d2a4456..89155caf50be 100644 --- a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts +++ b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts @@ -29,24 +29,24 @@ leds { compatible = "gpio-leds"; - logo { + led-logo { label = "bcm53xx:white:logo"; gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>; linux,default-trigger = "default-on"; }; - power0 { + led-power0 { label = "bcm53xx:green:power"; gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; linux,default-trigger = "default-on"; }; - power1 { + led-power1 { label = "bcm53xx:amber:power"; gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; }; - usb { + led-usb { label = "bcm53xx:blue:usb"; gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>; trigger-sources = <&ohci_port1>, <&ehci_port1>, @@ -54,7 +54,7 @@ linux,default-trigger = "usbport"; }; - wireless { + led-wireless { label = "bcm53xx:blue:wireless"; gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts b/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts index 76fc1099d47d..57d00a0b4765 100644 --- a/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts +++ b/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts @@ -28,29 +28,29 @@ leds { compatible = "gpio-leds"; - logo { + led-logo { label = "bcm53xx:white:logo"; gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>; linux,default-trigger = "default-on"; }; - power0 { + led-power0 { label = "bcm53xx:green:power"; gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; }; - power1 { + led-power1 { label = "bcm53xx:amber:power"; gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; linux,default-trigger = "default-on"; }; - usb { + led-usb { label = "bcm53xx:blue:usb"; gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>; }; - wireless { + led-wireless { label = "bcm53xx:blue:wireless"; gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts b/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts index 6bcdfb73cb9e..26cdeb5cc337 100644 --- a/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts +++ b/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts @@ -28,64 +28,64 @@ leds { compatible = "gpio-leds"; - power-white { + led-power-white { label = "bcm53xx:white:power"; gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>; linux,default-trigger = "default-on"; }; - power-amber { + led-power-amber { label = "bcm53xx:amber:power"; gpios = <&chipcommon 2 GPIO_ACTIVE_HIGH>; }; - usb2 { + led-usb2 { label = "bcm53xx:white:usb2"; gpios = <&chipcommon 3 GPIO_ACTIVE_HIGH>; trigger-sources = <&ohci_port2>, <&ehci_port2>; linux,default-trigger = "usbport"; }; - usb3-white { + led-usb3-white { label = "bcm53xx:white:usb3"; gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>; trigger-sources = <&xhci_port1>; linux,default-trigger = "usbport"; }; - usb3-green { + led-usb3-green { label = "bcm53xx:green:usb3"; gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>; trigger-sources = <&ohci_port1>, <&ehci_port1>; linux,default-trigger = "usbport"; }; - wps { + led-wps { label = "bcm53xx:white:wps"; gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>; }; - status-red { + led-status-red { label = "bcm53xx:red:status"; gpios = <&chipcommon 8 GPIO_ACTIVE_HIGH>; }; - status-green { + led-status-green { label = "bcm53xx:green:status"; gpios = <&chipcommon 9 GPIO_ACTIVE_HIGH>; }; - status-blue { + led-status-blue { label = "bcm53xx:blue:status"; gpios = <&chipcommon 10 GPIO_ACTIVE_HIGH>; }; - wan-white { + led-wan-white { label = "bcm53xx:white:wan"; gpios = <&chipcommon 12 GPIO_ACTIVE_HIGH>; }; - wan-red { + led-wan-red { label = "bcm53xx:red:wan"; gpios = <&chipcommon 13 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts b/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts index ca47cc4f2ba1..3854db0118a9 100644 --- a/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts +++ b/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts @@ -28,30 +28,30 @@ leds { compatible = "gpio-leds"; - power { + led-power { label = "bcm53xx:blue:power"; gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; linux,default-trigger = "default-on"; }; - usb2 { + led-usb2 { label = "bcm53xx:blue:usb2"; gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; }; - wan { + led-wan { label = "bcm53xx:blue:wan"; gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; linux,default-trigger = "default-on"; }; - lan { + led-lan { label = "bcm53xx:blue:lan"; gpios = <&chipcommon 9 GPIO_ACTIVE_LOW>; linux,default-trigger = "default-on"; }; - usb3 { + led-usb3 { label = "bcm53xx:blue:usb3"; gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts index 0edc2543e568..407319cb5c0d 100644 --- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts +++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts @@ -49,40 +49,40 @@ leds { compatible = "gpio-leds"; - power0 { + led-power0 { label = "bcm53xx:green:power"; gpios = <&hc595 1 GPIO_ACTIVE_HIGH>; linux,default-trigger = "default-on"; }; - power1 { + led-power1 { label = "bcm53xx:red:power"; gpios = <&hc595 2 GPIO_ACTIVE_HIGH>; }; - router0 { + led-router0 { label = "bcm53xx:green:router"; gpios = <&hc595 3 GPIO_ACTIVE_HIGH>; linux,default-trigger = "default-on"; }; - router1 { + led-router1 { label = "bcm53xx:amber:router"; gpios = <&hc595 4 GPIO_ACTIVE_HIGH>; }; - wan { + led-wan { label = "bcm53xx:green:wan"; gpios = <&hc595 5 GPIO_ACTIVE_HIGH>; linux,default-trigger = "default-on"; }; - wireless0 { + led-wireless0 { label = "bcm53xx:green:wireless"; gpios = <&hc595 6 GPIO_ACTIVE_HIGH>; }; - wireless1 { + led-wireless1 { label = "bcm53xx:amber:wireless"; gpios = <&hc595 7 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts b/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts index 1f0998f34afd..f8622ecce6a2 100644 --- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts +++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts @@ -49,45 +49,45 @@ leds { compatible = "gpio-leds"; - usb { + led-usb { label = "bcm53xx:green:usb"; gpios = <&hc595 0 GPIO_ACTIVE_HIGH>; }; - power0 { + led-power0 { label = "bcm53xx:green:power"; gpios = <&hc595 1 GPIO_ACTIVE_HIGH>; linux,default-trigger = "default-on"; }; - power1 { + led-power1 { label = "bcm53xx:red:power"; gpios = <&hc595 2 GPIO_ACTIVE_HIGH>; }; - router0 { + led-router0 { label = "bcm53xx:green:router"; gpios = <&hc595 3 GPIO_ACTIVE_HIGH>; linux,default-trigger = "default-on"; }; - router1 { + led-router1 { label = "bcm53xx:amber:router"; gpios = <&hc595 4 GPIO_ACTIVE_HIGH>; }; - wan { + led-wan { label = "bcm53xx:green:wan"; gpios = <&hc595 5 GPIO_ACTIVE_HIGH>; linux,default-trigger = "default-on"; }; - wireless0 { + led-wireless0 { label = "bcm53xx:green:wireless"; gpios = <&hc595 6 GPIO_ACTIVE_HIGH>; }; - wireless1 { + led-wireless1 { label = "bcm53xx:amber:wireless"; gpios = <&hc595 7 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts b/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts index c8c02377543b..76c9b30b868d 100644 --- a/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts +++ b/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts @@ -23,19 +23,19 @@ leds { compatible = "gpio-leds"; - 5ghz { + led-5ghz { label = "bcm53xx:blue:5ghz"; gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; linux,default-trigger = "none"; }; - 2ghz { + led-2ghz { label = "bcm53xx:blue:2ghz"; gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; linux,default-trigger = "none"; }; - status { + led-status { label = "bcm53xx:green:status"; gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; linux,default-trigger = "timer"; diff --git a/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts b/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts index 3b35a7af4b1c..6ef0c0788e62 100644 --- a/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts +++ b/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts @@ -29,62 +29,62 @@ leds { compatible = "gpio-leds"; - power { + led-power { label = "bcm53xx:green:power"; gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; linux,default-trigger = "default-on"; }; - lan3 { + led-lan3 { label = "bcm53xx:green:lan3"; gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; linux,default-trigger = "none"; }; - lan4 { + led-lan4 { label = "bcm53xx:green:lan4"; gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; linux,default-trigger = "none"; }; - wan { + led-wan { label = "bcm53xx:green:wan"; gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; linux,default-trigger = "none"; }; - lan2 { + led-lan2 { label = "bcm53xx:green:lan2"; gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; linux,default-trigger = "none"; }; - usb { + led-usb { label = "bcm53xx:green:usb"; gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>; trigger-sources = <&ohci_port2>, <&ehci_port2>; linux,default-trigger = "usbport"; }; - status { + led-status { label = "bcm53xx:green:status"; gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>; linux,default-trigger = "timer"; }; - 2ghz { + led-2ghz { label = "bcm53xx:green:2ghz"; gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; linux,default-trigger = "none"; }; - 5ghz { + led-5ghz { label = "bcm53xx:green:5ghz"; gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; linux,default-trigger = "none"; }; - lan1 { + led-lan1 { label = "bcm53xx:green:lan1"; gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; linux,default-trigger = "none"; diff --git a/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts b/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts index 19a7971b5a00..b6a5886698b2 100644 --- a/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts +++ b/arch/arm/boot/dts/bcm47081-tplink-archer-c5-v2.dts @@ -23,50 +23,50 @@ leds { compatible = "gpio-leds"; - 2ghz { + led-2ghz { label = "bcm53xx:green:2ghz"; gpios = <&chipcommon 0 GPIO_ACTIVE_HIGH>; }; - lan { + led-lan { label = "bcm53xx:green:lan"; gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>; }; - usb2-port1 { + led-usb2-port1 { label = "bcm53xx:green:usb2-port1"; gpios = <&chipcommon 2 GPIO_ACTIVE_HIGH>; trigger-sources = <&ohci_port1>, <&ehci_port1>; linux,default-trigger = "usbport"; }; - power { + led-power { label = "bcm53xx:green:power"; gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>; linux,default-trigger = "default-on"; }; - wan-green { + led-wan-green { label = "bcm53xx:green:wan"; gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>; }; - wps { + led-wps { label = "bcm53xx:green:wps"; gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>; }; - wan-amber { + led-wan-amber { label = "bcm53xx:amber:wan"; gpios = <&chipcommon 8 GPIO_ACTIVE_HIGH>; }; - 5ghz { + led-5ghz { label = "bcm53xx:green:5ghz"; gpios = <&chipcommon 12 GPIO_ACTIVE_HIGH>; }; - usb2-port2 { + led-usb2-port2 { label = "bcm53xx:green:usb2-port2"; gpios = <&chipcommon 13 GPIO_ACTIVE_HIGH>; trigger-sources = <&ohci_port2>, <&ehci_port2>; @@ -95,30 +95,15 @@ status = "okay"; partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot@0 { - label = "boot"; - reg = <0x000000 0x040000>; - read-only; - }; + compatible = "tplink,safeloader-partitions"; + partitions-table-offset = <0xe50000>; - os-image@100000 { - label = "os-image"; - reg = <0x040000 0x200000>; + partition-os-image { compatible = "brcm,trx"; }; - rootfs@240000 { - label = "rootfs"; - reg = <0x240000 0xc00000>; - }; - - nvram@ff0000 { - label = "nvram"; - reg = <0xff0000 0x010000>; + partition-file-system { + linux,rootfs; }; }; }; diff --git a/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts b/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts index f52a75c4ca09..4f44cb4df704 100644 --- a/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts +++ b/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts @@ -28,18 +28,18 @@ leds { compatible = "gpio-leds"; - wps { + led-wps { label = "bcm53xx:blue:wps"; gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; }; - power { + led-power { label = "bcm53xx:blue:power"; gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; linux,default-trigger = "default-on"; }; - wan { + led-wan { label = "bcm53xx:red:wan"; gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts b/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts index 5ff6c588e16e..b7cd2faa30ce 100644 --- a/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts +++ b/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts @@ -28,48 +28,48 @@ leds { compatible = "gpio-leds"; - usb { + led-usb { label = "bcm53xx:green:usb"; gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>; }; - power-amber { + led-power-amber { label = "bcm53xx:amber:power"; gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>; }; - power-white { + led-power-white { label = "bcm53xx:white:power"; gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>; linux,default-trigger = "default-on"; }; - router-amber { + led-router-amber { label = "bcm53xx:amber:router"; gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>; }; - router-white { + led-router-white { label = "bcm53xx:white:router"; gpios = <&chipcommon 8 GPIO_ACTIVE_HIGH>; }; - wan-amber { + led-wan-amber { label = "bcm53xx:amber:wan"; gpios = <&chipcommon 9 GPIO_ACTIVE_HIGH>; }; - wan-white { + led-wan-white { label = "bcm53xx:white:wan"; gpios = <&chipcommon 10 GPIO_ACTIVE_HIGH>; }; - wireless-amber { + led-wireless-amber { label = "bcm53xx:amber:wireless"; gpios = <&chipcommon 11 GPIO_ACTIVE_HIGH>; }; - wireless-white { + led-wireless-white { label = "bcm53xx:white:wireless"; gpios = <&chipcommon 12 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm/boot/dts/bcm4709-netgear-r7000.dts b/arch/arm/boot/dts/bcm4709-netgear-r7000.dts index de961fbb6200..24ba8f8f9bf3 100644 --- a/arch/arm/boot/dts/bcm4709-netgear-r7000.dts +++ b/arch/arm/boot/dts/bcm4709-netgear-r7000.dts @@ -28,43 +28,43 @@ leds { compatible = "gpio-leds"; - power-white { + led-power-white { label = "bcm53xx:white:power"; gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; linux,default-trigger = "default-on"; }; - power-amber { + led-power-amber { label = "bcm53xx:amber:power"; gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; }; - 5ghz { + led-5ghz { label = "bcm53xx:white:5ghz"; gpios = <&chipcommon 12 GPIO_ACTIVE_LOW>; }; - 2ghz { + led-2ghz { label = "bcm53xx:white:2ghz"; gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; }; - wps { + led-wps { label = "bcm53xx:white:wps"; gpios = <&chipcommon 14 GPIO_ACTIVE_HIGH>; }; - wireless { + led-wireless { label = "bcm53xx:white:wireless"; gpios = <&chipcommon 15 GPIO_ACTIVE_HIGH>; }; - usb3 { + led-usb3 { label = "bcm53xx:white:usb3"; gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; }; - usb2 { + led-usb2 { label = "bcm53xx:white:usb2"; gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts index 087f7f60de18..14303ab521ea 100644 --- a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts +++ b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts @@ -39,59 +39,59 @@ leds { compatible = "gpio-leds"; - power-white { + led-power-white { label = "bcm53xx:white:power"; gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; linux,default-trigger = "default-on"; }; - power-amber { + led-power-amber { label = "bcm53xx:amber:power"; gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; }; - wan-white { + led-wan-white { label = "bcm53xx:white:wan"; gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>; linux,default-trigger = "default-on"; }; - wan-amber { + led-wan-amber { label = "bcm53xx:amber:wan"; gpios = <&chipcommon 9 GPIO_ACTIVE_HIGH>; }; - 5ghz-1 { + led-5ghz-1 { label = "bcm53xx:white:5ghz-1"; gpios = <&chipcommon 12 GPIO_ACTIVE_LOW>; }; - 2ghz { + led-2ghz { label = "bcm53xx:white:2ghz"; gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; }; - wireless { + led-wireless { label = "bcm53xx:white:wireless"; gpios = <&chipcommon 14 GPIO_ACTIVE_HIGH>; }; - wps { + led-wps { label = "bcm53xx:white:wps"; gpios = <&chipcommon 15 GPIO_ACTIVE_HIGH>; }; - 5ghz-2 { + led-5ghz-2 { label = "bcm53xx:white:5ghz-2"; gpios = <&chipcommon 16 GPIO_ACTIVE_LOW>; }; - usb3 { + led-usb3 { label = "bcm53xx:white:usb3"; gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; }; - usb2 { + led-usb2 { label = "bcm53xx:white:usb2"; gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts b/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts index 11d1068160da..5a8b2b1567e6 100644 --- a/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts +++ b/arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts @@ -23,27 +23,27 @@ leds { compatible = "gpio-leds"; - lan { + led-lan { label = "bcm53xx:blue:lan"; gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>; }; - wps { + led-wps { label = "bcm53xx:blue:wps"; gpios = <&chipcommon 2 GPIO_ACTIVE_HIGH>; }; - 2ghz { + led-2ghz { label = "bcm53xx:blue:2ghz"; gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>; }; - 5ghz { + led-5ghz { label = "bcm53xx:blue:5ghz"; gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>; }; - usb3 { + led-usb3 { label = "bcm53xx:blue:usb3"; gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>; trigger-sources = <&ohci_port1>, <&ehci_port1>, @@ -51,24 +51,24 @@ linux,default-trigger = "usbport"; }; - usb2 { + led-usb2 { label = "bcm53xx:blue:usb2"; gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>; trigger-sources = <&ohci_port2>, <&ehci_port2>; linux,default-trigger = "usbport"; }; - wan-blue { + led-wan-blue { label = "bcm53xx:blue:wan"; gpios = <&chipcommon 14 GPIO_ACTIVE_HIGH>; }; - wan-amber { + led-wan-amber { label = "bcm53xx:amber:wan"; gpios = <&chipcommon 15 GPIO_ACTIVE_HIGH>; }; - power { + led-power { label = "bcm53xx:blue:power"; gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; linux,default-trigger = "default-on"; @@ -104,30 +104,15 @@ status = "okay"; partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot@0 { - label = "boot"; - reg = <0x000000 0x040000>; - read-only; - }; + compatible = "tplink,safeloader-partitions"; + partitions-table-offset = <0xe50000>; - os-image@100000 { - label = "os-image"; - reg = <0x040000 0x200000>; + partition-os-image { compatible = "brcm,trx"; }; - rootfs@240000 { - label = "rootfs"; - reg = <0x240000 0xc00000>; - }; - - nvram@ff0000 { - label = "nvram"; - reg = <0xff0000 0x010000>; + partition-file-system { + linux,rootfs; }; }; }; diff --git a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts index a5fec56d11c0..a50ff686b557 100644 --- a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts +++ b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts @@ -33,37 +33,37 @@ leds { compatible = "gpio-leds"; - power { + led-power { label = "white:power"; gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; linux,default-trigger = "default-on"; }; - wan-red { + led-wan-red { label = "red:wan"; gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>; }; - lan { + led-lan { label = "white:lan"; gpios = <&chipcommon 21 GPIO_ACTIVE_LOW>; }; - usb2 { + led-usb2 { label = "white:usb2"; gpios = <&chipcommon 16 GPIO_ACTIVE_LOW>; trigger-sources = <&ehci_port2>; linux,default-trigger = "usbport"; }; - usb3 { + led-usb3 { label = "white:usb3"; gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; trigger-sources = <&ehci_port1>, <&xhci_port1>; linux,default-trigger = "usbport"; }; - wps { + led-wps { label = "white:wps"; gpios = <&chipcommon 19 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts index 2c38b642a8b8..555fbe41dd8f 100644 --- a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts +++ b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts @@ -43,28 +43,28 @@ leds { compatible = "gpio-leds"; - power-white { + led-power-white { label = "bcm53xx:white:power"; gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; linux,default-trigger = "default-on"; }; - wan-white { + led-wan-white { label = "bcm53xx:white:wan"; gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; }; - power-amber { + led-power-amber { label = "bcm53xx:amber:power"; gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; }; - wan-amber { + led-wan-amber { label = "bcm53xx:amber:wan"; gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; }; - usb3-white { + led-usb3-white { label = "bcm53xx:white:usb3"; gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>; trigger-sources = <&ohci_port1>, <&ehci_port1>, @@ -72,12 +72,12 @@ linux,default-trigger = "usbport"; }; - 2ghz { + led-2ghz { label = "bcm53xx:white:2ghz"; gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; }; - 5ghz { + led-5ghz { label = "bcm53xx:white:5ghz"; gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/boot/dts/bcm47094-dlink-dir-890l.dts b/arch/arm/boot/dts/bcm47094-dlink-dir-890l.dts new file mode 100644 index 000000000000..d945a20b06e0 --- /dev/null +++ b/arch/arm/boot/dts/bcm47094-dlink-dir-890l.dts @@ -0,0 +1,211 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Device tree for D-Link DIR-890L + * D-Link calls this board "WRGAC36" + * this router has the same looks and form factor as D-Link DIR-885L. + * + * Some differences from DIR-885L include a separate USB2 port, separate LEDs + * for USB2 and USB3, a separate VCC supply for the USB2 slot and no + * router/extender switch is mounted (there is an empty mount point on the + * PCB) so this device is a pure router. Also the LAN ports are in the right + * order. + * + * Based on the device tree for DIR-885L + * Copyright (C) 2016 RafaÅ‚ MiÅ‚ecki <zajec5@gmail.com> + * Copyright (C) 2022 Linus Walleij + */ + +/dts-v1/; + +#include "bcm47094.dtsi" +#include "bcm5301x-nand-cs0-bch1.dtsi" + +/ { + compatible = "dlink,dir-890l", "brcm,bcm47094", "brcm,bcm4708"; + model = "D-Link DIR-890L"; + + chosen { + bootargs = "console=ttyS0,115200 earlycon"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x08000000>, + <0x88000000 0x08000000>; + }; + + leds { + /* + * LED information is derived from the boot log which + * conveniently lists all the LEDs. + */ + compatible = "gpio-leds"; + + led-power-white { + label = "bcm53xx:white:power"; + gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + + led-wan-white { + label = "bcm53xx:white:wan"; + gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; + }; + + led-power-amber { + label = "bcm53xx:amber:power"; + gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; + }; + + led-wan-amber { + label = "bcm53xx:amber:wan"; + gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; + }; + + led-usb3-white { + label = "bcm53xx:white:usb3"; + gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>; + trigger-sources = <&xhci_port1>; + linux,default-trigger = "usbport"; + }; + + led-usb2-white { + label = "bcm53xx:white:usb2"; + gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; + trigger-sources = <&ohci_port1>, <&ehci_port1>; + linux,default-trigger = "usbport"; + }; + + led-2ghz { + label = "bcm53xx:white:2ghz"; + gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; + }; + + led-5ghz { + label = "bcm53xx:white:5ghz"; + gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-wps { + label = "WPS"; + linux,code = <KEY_WPS_BUTTON>; + gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; + }; + + /* Called "factory reset" in the vendor dmesg */ + button-restart { + label = "Reset"; + linux,code = <KEY_RESTART>; + gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; + }; + }; + + /* + * The flash memory is memory mapped at 0x1e000000-0x1fffffff + * 64KB blocks; total size 2MB, same that can be + * found attached to the spi_nor SPI controller. + */ + nvram@1e1f0000 { + compatible = "brcm,nvram"; + reg = <0x1e1f0000 0x00010000>; + + et0macaddr: et0macaddr { + }; + }; +}; + +&gmac2 { + /* + * The NVRAM curiously does not contain a MAC address + * for et2 so since that is the only ethernet interface + * actually in use on the platform, we use this et0 MAC + * address for et2. + */ + nvmem-cells = <&et0macaddr>; + nvmem-cell-names = "mac-address"; +}; + +&spi_nor { + status = "okay"; +}; + +&nandcs { + /* Spansion S34ML01G2, 128MB with 128KB erase blocks */ + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* + * This is called "nflash" in the vendor kernel with + * "upgrade" and "rootfs" (probably using OpenWrt + * splitpart). We call it "firmware" like standard tools + * assume. The CFE loader contains incorrect information + * about TRX partitions, ignore this, there are no TRX + * partitions: this device uses SEAMA. + */ + firmware@0 { + label = "firmware"; + reg = <0x00000000 0x08000000>; + }; + }; +}; + +&usb2 { + vcc-gpios = <&chipcommon 21 GPIO_ACTIVE_HIGH>; +}; + +&usb3 { + vcc-gpios = <&chipcommon 18 GPIO_ACTIVE_HIGH>; +}; + +&usb3_phy { + status = "okay"; +}; + +&srab { + status = "okay"; + + ports { + port@0 { + reg = <0>; + label = "lan1"; + }; + + port@1 { + reg = <1>; + label = "lan2"; + }; + + port@2 { + reg = <2>; + label = "lan3"; + }; + + port@3 { + reg = <3>; + label = "lan4"; + }; + + port@4 { + reg = <4>; + label = "wan"; + }; + + port@8 { + reg = <8>; + label = "cpu"; + ethernet = <&gmac2>; + phy-mode = "rgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts index 86c7cc0fa70e..d9a16a820e7f 100644 --- a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts +++ b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts @@ -52,19 +52,19 @@ leds { compatible = "gpio-leds"; - wps { + led-wps { label = "bcm53xx:white:wps"; gpios = <&chipcommon 22 GPIO_ACTIVE_LOW>; }; - usb2 { + led-usb2 { label = "bcm53xx:green:usb2"; gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; trigger-sources = <&ohci_port2>, <&ehci_port2>; linux,default-trigger = "usbport"; }; - usb3 { + led-usb3 { label = "bcm53xx:green:usb3"; gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; trigger-sources = <&ohci_port1>, <&ehci_port1>, @@ -72,58 +72,58 @@ linux,default-trigger = "usbport"; }; - power { + led-power { label = "bcm53xx:white:power"; gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>; linux,default-trigger = "default-on"; }; - wifi-disabled { + led-wifi-disabled { label = "bcm53xx:amber:wifi-disabled"; gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; }; - wifi-enabled { + led-wifi-enabled { label = "bcm53xx:white:wifi-enabled"; gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>; }; - bluebar1 { + led-bluebar1 { label = "bcm53xx:white:bluebar1"; gpios = <&chipcommon 11 GPIO_ACTIVE_HIGH>; }; - bluebar2 { + led-bluebar2 { label = "bcm53xx:white:bluebar2"; gpios = <&chipcommon 12 GPIO_ACTIVE_HIGH>; }; - bluebar3 { + led-bluebar3 { label = "bcm53xx:white:bluebar3"; gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; }; - bluebar4 { + led-bluebar4 { label = "bcm53xx:white:bluebar4"; gpios = <&chipcommon 18 GPIO_ACTIVE_HIGH>; }; - bluebar5 { + led-bluebar5 { label = "bcm53xx:white:bluebar5"; gpios = <&chipcommon 19 GPIO_ACTIVE_HIGH>; }; - bluebar6 { + led-bluebar6 { label = "bcm53xx:white:bluebar6"; gpios = <&chipcommon 20 GPIO_ACTIVE_HIGH>; }; - bluebar7 { + led-bluebar7 { label = "bcm53xx:white:bluebar7"; gpios = <&chipcommon 21 GPIO_ACTIVE_HIGH>; }; - bluebar8 { + led-bluebar8 { label = "bcm53xx:white:bluebar8"; gpios = <&chipcommon 8 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts b/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts index 9ad15bcae1ca..41a0722fa64a 100644 --- a/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts +++ b/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts @@ -30,13 +30,13 @@ leds { compatible = "gpio-leds"; - status { + led-status { label = "bcm53xx:green:status"; gpios = <&chipcommon 20 GPIO_ACTIVE_LOW>; linux,default-trigger = "timer"; }; - usb3 { + led-usb3 { label = "bcm53xx:green:usb3"; gpios = <&chipcommon 19 GPIO_ACTIVE_LOW>; trigger-sources = <&ohci_port1>, <&ehci_port1>, diff --git a/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts b/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts index ee24d3768536..c56c7e366848 100644 --- a/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts +++ b/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts @@ -23,18 +23,18 @@ leds { compatible = "gpio-leds"; - status { + led-status { label = "bcm53xx:green:status"; gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; linux,default-trigger = "timer"; }; - 2ghz { + led-2ghz { label = "bcm53xx:blue:2ghz"; gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; }; - 5ghz { + led-5ghz { label = "bcm53xx:blue:5ghz"; gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts b/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts index 6549d07b9887..1b5c91a524ac 100644 --- a/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts +++ b/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts @@ -30,13 +30,13 @@ leds { compatible = "gpio-leds"; - status { + led-status { label = "bcm53xx:green:status"; gpios = <&chipcommon 20 GPIO_ACTIVE_HIGH>; linux,default-trigger = "timer"; }; - usb3 { + led-usb3 { label = "bcm53xx:green:usb3"; gpios = <&chipcommon 19 GPIO_ACTIVE_HIGH>; trigger-sources = <&ohci_port1>, <&ehci_port1>, diff --git a/arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts b/arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts index 654fcce9fded..739063b77b1f 100644 --- a/arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts +++ b/arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts @@ -25,7 +25,7 @@ leds { compatible = "gpio-leds"; - status { + led-status { label = "bcm53xx:green:status"; gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; linux,default-trigger = "timer"; diff --git a/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts b/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts index bf053a2fcc7c..7afc68d5d2c2 100644 --- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts +++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts @@ -30,38 +30,38 @@ leds { compatible = "gpio-leds"; - power { + led-power { label = "bcm53xx:green:power"; gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; linux,default-trigger = "default-on"; }; - lan3 { + led-lan3 { label = "bcm53xx:green:lan3"; gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; }; - lan4 { + led-lan4 { label = "bcm53xx:green:lan4"; gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; }; - wan { + led-wan { label = "bcm53xx:green:wan"; gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; }; - lan1 { + led-lan1 { label = "bcm53xx:green:lan1"; gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; }; - lan2 { + led-lan2 { label = "bcm53xx:green:lan2"; gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; }; - usb3 { + led-usb3 { label = "bcm53xx:green:usb3"; gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>; trigger-sources = <&ohci_port1>, <&ehci_port1>, @@ -69,18 +69,18 @@ linux,default-trigger = "usbport"; }; - status { + led-status { label = "bcm53xx:green:status"; gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>; linux,default-trigger = "timer"; }; - 2ghz { + led-2ghz { label = "bcm53xx:green:2ghz"; gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; }; - 5ghz { + led-5ghz { label = "bcm53xx:green:5ghz"; gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts b/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts index 78a90dd57a4e..60a2c441d5bd 100644 --- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts +++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts @@ -33,13 +33,13 @@ leds { compatible = "gpio-leds"; - power { + led-power { label = "bcm53xx:green:power"; gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; linux,default-trigger = "default-on"; }; - usb3 { + led-usb3 { label = "bcm53xx:green:usb3"; gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>; trigger-sources = <&ohci_port1>, <&ehci_port1>, @@ -47,18 +47,18 @@ linux,default-trigger = "usbport"; }; - status { + led-status { label = "bcm53xx:green:status"; gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>; linux,default-trigger = "timer"; }; - 2ghz { + led-2ghz { label = "bcm53xx:green:2ghz"; gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; }; - 5ghz { + led-5ghz { label = "bcm53xx:green:5ghz"; gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/boot/dts/bcm47094-netgear-r8500.dts b/arch/arm/boot/dts/bcm47094-netgear-r8500.dts index f850dce37b20..76d562610654 100644 --- a/arch/arm/boot/dts/bcm47094-netgear-r8500.dts +++ b/arch/arm/boot/dts/bcm47094-netgear-r8500.dts @@ -25,38 +25,38 @@ leds { compatible = "gpio-leds"; - power0 { + led-power0 { label = "bcm53xx:white:power"; gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; linux,default-trigger = "default-on"; }; - power1 { + led-power1 { label = "bcm53xx:amber:power"; gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; }; - 5ghz-1 { + led-5ghz-1 { label = "bcm53xx:white:5ghz-1"; gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; }; - 5ghz-2 { + led-5ghz-2 { label = "bcm53xx:white:5ghz-2"; gpios = <&chipcommon 12 GPIO_ACTIVE_LOW>; }; - 2ghz { + led-2ghz { label = "bcm53xx:white:2ghz"; gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; }; - usb2 { + led-usb2 { label = "bcm53xx:white:usb2"; gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; }; - usb3 { + led-usb3 { label = "bcm53xx:white:usb3"; gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts b/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts index e20b6d2eb274..0734aa249b8e 100644 --- a/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts +++ b/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts @@ -23,13 +23,13 @@ leds { compatible = "gpio-leds"; - wlan { + led-wlan { label = "bcm53xx:blue:wlan"; gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>; linux,default-trigger = "default-off"; }; - system { + led-system { label = "bcm53xx:green:system"; gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; linux,default-trigger = "timer"; diff --git a/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts b/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts index 9d863570fcf3..e6fb6cbe6963 100644 --- a/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts +++ b/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts @@ -20,26 +20,26 @@ reg = <0x00000000 0x08000000>; }; - leds { + leds-0 { compatible = "gpio-leds"; - 5ghz { + led-5ghz { label = "bcm53xx:blue:5ghz"; gpios = <&chipcommon 11 GPIO_ACTIVE_HIGH>; linux,default-trigger = "default-off"; }; - system { + led-system { label = "bcm53xx:green:system"; gpios = <&chipcommon 15 GPIO_ACTIVE_HIGH>; linux,default-trigger = "timer"; }; }; - pcie0_leds { + leds-1 { compatible = "gpio-leds"; - 2ghz { + led-2ghz { label = "bcm53xx:blue:2ghz"; gpios = <&pcie0_chipcommon 3 GPIO_ACTIVE_HIGH>; linux,default-trigger = "default-off"; diff --git a/arch/arm/boot/dts/bcm47189-tenda-ac9.dts b/arch/arm/boot/dts/bcm47189-tenda-ac9.dts index 55b92645b0f1..dab2e5f63a72 100644 --- a/arch/arm/boot/dts/bcm47189-tenda-ac9.dts +++ b/arch/arm/boot/dts/bcm47189-tenda-ac9.dts @@ -20,37 +20,37 @@ reg = <0x00000000 0x08000000>; }; - leds { + leds-0 { compatible = "gpio-leds"; - usb { + led-usb { label = "bcm53xx:blue:usb"; gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>; trigger-sources = <&ohci_port1>, <&ehci_port1>; linux,default-trigger = "usbport"; }; - wps { + led-wps { label = "bcm53xx:blue:wps"; gpios = <&chipcommon 10 GPIO_ACTIVE_HIGH>; }; - 5ghz { + led-5ghz { label = "bcm53xx:blue:5ghz"; gpios = <&chipcommon 11 GPIO_ACTIVE_HIGH>; }; - system { + led-system { label = "bcm53xx:blue:system"; gpios = <&chipcommon 15 GPIO_ACTIVE_HIGH>; linux,default-trigger = "timer"; }; }; - pcie0_leds { + leds-1 { compatible = "gpio-leds"; - 2ghz { + led-2ghz { label = "bcm53xx:blue:2ghz"; gpios = <&pcie0_chipcommon 3 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm/boot/dts/bcm47622.dtsi b/arch/arm/boot/dts/bcm47622.dtsi index 2df04528af82..f4b2db9bc4ab 100644 --- a/arch/arm/boot/dts/bcm47622.dtsi +++ b/arch/arm/boot/dts/bcm47622.dtsi @@ -51,6 +51,7 @@ L2_0: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm/boot/dts/bcm53016-dlink-dwl-8610ap.dts b/arch/arm/boot/dts/bcm53016-dlink-dwl-8610ap.dts new file mode 100644 index 000000000000..c1f54391746f --- /dev/null +++ b/arch/arm/boot/dts/bcm53016-dlink-dwl-8610ap.dts @@ -0,0 +1,131 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/dts-v1/; + +#include "bcm4709.dtsi" +#include "bcm5301x-nand-cs0-bch8.dtsi" +#include <dt-bindings/leds/common.h> +#include <dt-bindings/input/input.h> + +/ { + model = "D-Link DWL-8610AP"; + compatible = "dlink,dwl-8610ap", "brcm,bcm53016", "brcm,bcm4708"; + + memory@0 { + device_type = "memory"; + /* 512 MB RAM in 2 x Macronix D9PSH chips */ + reg = <0x00000000 0x08000000>, + <0x88000000 0x08000000>; + }; + + leds { + compatible = "gpio-leds"; + + led-power { + function = LED_FUNCTION_POWER; + color = <LED_COLOR_ID_GREEN>; + gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + led-diag { + /* Actually "diag" unclear what this means */ + function = LED_FUNCTION_INDICATOR; + color = <LED_COLOR_ID_RED>; + gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + led-wlan-2g { + function = LED_FUNCTION_WLAN; + color = <LED_COLOR_ID_GREEN>; + gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>; + }; + + led-wlan-5g { + function = LED_FUNCTION_WLAN; + color = <LED_COLOR_ID_GREEN>; + gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + button-reset { + debounce-interval = <100>; + wakeup-source; + linux,code = <KEY_RESTART>; + label = "reset"; + /* This GPIO is actually stored in NVRAM, but it's not gonna change */ + gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; + }; + }; + + /* + * Flash memory at 0x1e000000-0x1fffffff + * Macronix 32 64KB blocks; total size 2MB, same that can be + * found attached to the spi_nor SPI controller. + */ + nvram@1e080000 { + compatible = "brcm,nvram"; + reg = <0x1e080000 0x00020000>; + + et0macaddr: et0macaddr { + }; + + et1macaddr: et1macaddr { + }; + }; +}; + +&gmac0 { + nvmem-cells = <&et0macaddr>; + nvmem-cell-names = "mac-address"; +}; + +&gmac1 { + nvmem-cells = <&et1macaddr>; + nvmem-cell-names = "mac-address"; +}; + +&spi_nor { + /* Serial SPI NOR Flash MX 25L1606E */ + status = "okay"; +}; + +&nandcs { + /* + * Spansion S34ML01G100TFI00 128 MB NAND Flash memory + * + * This ECC is a bit unorthodox but it is what the stock firmware + * is using, so to be able to mount the original partitions + * this is necessary. + */ + nand-ecc-strength = <5>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* This is named nflash1.trx in CFE */ + trx@0 { + label = "firmware"; + reg = <0x00000000 0x02800000>; + compatible = "brcm,trx"; + }; + + /* This is named nflash1.trx2 in CFE */ + trx2@2800000 { + label = "firmware2"; + reg = <0x02800000 0x02800000>; + compatible = "brcm,trx"; + }; + + /* This is named nflash1.rwfs in CFE */ + free@5000000 { + label = "free"; + reg = <0x05000000 0x03000000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/bcm53016-meraki-mr32.dts b/arch/arm/boot/dts/bcm53016-meraki-mr32.dts index e678bc03d816..46c2c93b01d8 100644 --- a/arch/arm/boot/dts/bcm53016-meraki-mr32.dts +++ b/arch/arm/boot/dts/bcm53016-meraki-mr32.dts @@ -58,7 +58,7 @@ pwm-leds { compatible = "pwm-leds"; - red { + led-0 { /* SYS-LED 1 - Tricolor */ function = LED_FUNCTION_INDICATOR; color = <LED_COLOR_ID_RED>; @@ -66,7 +66,7 @@ max-brightness = <255>; }; - green { + led-1 { /* SYS-LED 1 - Tricolor */ function = LED_FUNCTION_POWER; color = <LED_COLOR_ID_GREEN>; @@ -74,7 +74,7 @@ max-brightness = <255>; }; - blue { + led-2 { /* SYS-LED 1 - Tricolor */ function = LED_FUNCTION_INDICATOR; color = <LED_COLOR_ID_BLUE>; diff --git a/arch/arm/boot/dts/bcm63148.dtsi b/arch/arm/boot/dts/bcm63148.dtsi index df5307b6b3af..7cd55d64de71 100644 --- a/arch/arm/boot/dts/bcm63148.dtsi +++ b/arch/arm/boot/dts/bcm63148.dtsi @@ -35,6 +35,7 @@ L2_0: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm/boot/dts/bcm63178.dtsi b/arch/arm/boot/dts/bcm63178.dtsi index cbd094dde6d0..043e699cbc27 100644 --- a/arch/arm/boot/dts/bcm63178.dtsi +++ b/arch/arm/boot/dts/bcm63178.dtsi @@ -43,6 +43,7 @@ L2_0: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm/boot/dts/bcm6756.dtsi b/arch/arm/boot/dts/bcm6756.dtsi index ce1b59faf800..5c72219bc194 100644 --- a/arch/arm/boot/dts/bcm6756.dtsi +++ b/arch/arm/boot/dts/bcm6756.dtsi @@ -51,6 +51,7 @@ L2_0: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm/boot/dts/bcm6846.dtsi b/arch/arm/boot/dts/bcm6846.dtsi index 8aa47a2583b2..81513a793815 100644 --- a/arch/arm/boot/dts/bcm6846.dtsi +++ b/arch/arm/boot/dts/bcm6846.dtsi @@ -35,6 +35,7 @@ L2_0: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm/boot/dts/bcm6855.dtsi b/arch/arm/boot/dts/bcm6855.dtsi index 620f51aee1a2..5fa5feac0e29 100644 --- a/arch/arm/boot/dts/bcm6855.dtsi +++ b/arch/arm/boot/dts/bcm6855.dtsi @@ -43,6 +43,7 @@ L2_0: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm/boot/dts/bcm6878.dtsi b/arch/arm/boot/dts/bcm6878.dtsi index 1e8b5fa96c25..4ec836ac4baf 100644 --- a/arch/arm/boot/dts/bcm6878.dtsi +++ b/arch/arm/boot/dts/bcm6878.dtsi @@ -35,6 +35,7 @@ L2_0: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm/boot/dts/bcm947189acdbmr.dts b/arch/arm/boot/dts/bcm947189acdbmr.dts index 16e70a264faf..3709baa2376f 100644 --- a/arch/arm/boot/dts/bcm947189acdbmr.dts +++ b/arch/arm/boot/dts/bcm947189acdbmr.dts @@ -25,17 +25,17 @@ leds { compatible = "gpio-leds"; - wps { + led-wps { label = "bcm53xx:blue:wps"; gpios = <&chipcommon 10 GPIO_ACTIVE_HIGH>; }; - 5ghz { + led-5ghz { label = "bcm53xx:blue:5ghz"; gpios = <&chipcommon 11 GPIO_ACTIVE_HIGH>; }; - 2ghz { + led-2ghz { label = "bcm53xx:blue:2ghz"; gpios = <&chipcommon 12 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi index 00a36fba2fd2..9aee3cfd3e98 100644 --- a/arch/arm/boot/dts/dove.dtsi +++ b/arch/arm/boot/dts/dove.dtsi @@ -139,7 +139,7 @@ pcie1: pcie@2 { device_type = "pci"; status = "disabled"; - assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; + assigned-addresses = <0x82001000 0 0x80000 0 0x2000>; reg = <0x1000 0 0 0 0>; clocks = <&gate_clk 5>; marvell,pcie-port = <1>; diff --git a/arch/arm/boot/dts/dra7-evm-common.dtsi b/arch/arm/boot/dts/dra7-evm-common.dtsi index 68c43eb12c1a..4cdffd6db740 100644 --- a/arch/arm/boot/dts/dra7-evm-common.dtsi +++ b/arch/arm/boot/dts/dra7-evm-common.dtsi @@ -151,7 +151,7 @@ */ partition@0 { label = "QSPI.SPL"; - reg = <0x00000000 0x000010000>; + reg = <0x00000000 0x00010000>; }; partition@1 { label = "QSPI.SPL.backup1"; diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts index 87deb6a76eff..8cbcf55a5a33 100644 --- a/arch/arm/boot/dts/dra7-evm.dts +++ b/arch/arm/boot/dts/dra7-evm.dts @@ -483,7 +483,7 @@ #size-cells = <1>; partition@0 { label = "NAND.SPL"; - reg = <0x00000000 0x000020000>; + reg = <0x00000000 0x00020000>; }; partition@1 { label = "NAND.SPL.backup1"; diff --git a/arch/arm/boot/dts/dra72-evm-common.dtsi b/arch/arm/boot/dts/dra72-evm-common.dtsi index 8948e10dbeb8..c79ba671ec2b 100644 --- a/arch/arm/boot/dts/dra72-evm-common.dtsi +++ b/arch/arm/boot/dts/dra72-evm-common.dtsi @@ -356,7 +356,7 @@ #size-cells = <1>; partition@0 { label = "NAND.SPL"; - reg = <0x00000000 0x000020000>; + reg = <0x00000000 0x00020000>; }; partition@1 { label = "NAND.SPL.backup1"; @@ -490,7 +490,7 @@ */ partition@0 { label = "QSPI.SPL"; - reg = <0x00000000 0x000010000>; + reg = <0x00000000 0x00010000>; }; partition@1 { label = "QSPI.SPL.backup1"; diff --git a/arch/arm/boot/dts/e60k02.dtsi b/arch/arm/boot/dts/e60k02.dtsi index 935e2359f8df..94944cc21931 100644 --- a/arch/arm/boot/dts/e60k02.dtsi +++ b/arch/arm/boot/dts/e60k02.dtsi @@ -104,7 +104,16 @@ clock-frequency = <100000>; status = "okay"; - /* TODO: CYTTSP5 touch controller at 0x24 */ + touchscreen@24 { + compatible = "cypress,tt21000"; + reg = <0x24>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cyttsp5_gpio>; + interrupt-parent = <&gpio5>; + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + vdd-supply = <&ldo5_reg>; + }; /* TODO: TPS65185 PMIC for E Ink at 0x68 */ diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi index 326b9e0ed8d3..a2d6ee7fff08 100644 --- a/arch/arm/boot/dts/exynos3250.dtsi +++ b/arch/arm/boot/dts/exynos3250.dtsi @@ -485,7 +485,7 @@ }; mfc: codec@13400000 { - compatible = "samsung,mfc-v7"; + compatible = "samsung,exynos3250-mfc", "samsung,mfc-v7"; reg = <0x13400000 0x10000>; interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; clock-names = "mfc", "sclk_mfc"; diff --git a/arch/arm/boot/dts/imx6dl-colibri-aster.dts b/arch/arm/boot/dts/imx6dl-colibri-aster.dts index 74e8a6cd8bed..a28e083f29d5 100644 --- a/arch/arm/boot/dts/imx6dl-colibri-aster.dts +++ b/arch/arm/boot/dts/imx6dl-colibri-aster.dts @@ -99,7 +99,6 @@ }; &usbh1 { - vbus-supply = <®_usb_host_vbus>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts index 7272edd85a49..a02981d4a3fc 100644 --- a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts @@ -111,7 +111,6 @@ }; &usbh1 { - vbus-supply = <®_usb_host_vbus>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6dl-colibri-iris.dts b/arch/arm/boot/dts/imx6dl-colibri-iris.dts index cf77d894f6d7..c5797ff35b71 100644 --- a/arch/arm/boot/dts/imx6dl-colibri-iris.dts +++ b/arch/arm/boot/dts/imx6dl-colibri-iris.dts @@ -138,7 +138,6 @@ }; &usbh1 { - vbus-supply = <®_usb_host_vbus>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi index 023e76215064..d8f985f297e4 100644 --- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi +++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi @@ -24,6 +24,13 @@ status = "disabled"; }; + extcon_usbc_det: usbc-det { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; /* SODIMM 137 / USBC_DET */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbc_det>; + }; + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; @@ -105,7 +112,7 @@ reg_usb_host_vbus: regulator-usb-host-vbus { compatible = "regulator-fixed"; - gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; /* USBH_PEN */ + gpio = <&gpio3 31 GPIO_ACTIVE_LOW>; /* SODIMM 129 / USBH_PEN */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_regulator_usbh_pwr>; regulator-max-microvolt = <5000000>; @@ -670,9 +677,16 @@ status = "disabled"; }; +/* Colibri USBH */ +&usbh1 { + vbus-supply = <®_usb_host_vbus>; +}; + +/* Colibri USBC */ &usbotg { disable-over-current; - dr_mode = "peripheral"; + dr_mode = "otg"; + extcon = <0>, <&extcon_usbc_det>; status = "disabled"; }; @@ -986,7 +1000,7 @@ pinctrl_regulator_usbh_pwr: gpioregusbhpwrgrp { fsl,pins = < - /* USBH_EN */ + /* SODIMM 129 / USBH_PEN */ MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x0f058 >; }; @@ -1055,7 +1069,7 @@ pinctrl_usbc_det: usbcdetgrp { fsl,pins = < - /* USBC_DET */ + /* SODIMM 137 / USBC_DET */ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 /* USBC_DET_OVERWRITE */ MX6QDL_PAD_RGMII_RXC__GPIO6_IO30 0x0f058 diff --git a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi index 22f8e2783cdf..12573e1f917c 100644 --- a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi @@ -14,6 +14,11 @@ stdout-path = &uart2; }; + aliases { + mmc0 = &usdhc3; + mmc1 = &usdhc4; + }; + memory@10000000 { device_type = "memory"; reg = <0x10000000 0x40000000>; diff --git a/arch/arm/boot/dts/imx6sl-kobo-aura2.dts b/arch/arm/boot/dts/imx6sl-kobo-aura2.dts new file mode 100644 index 000000000000..657d0f1b6115 --- /dev/null +++ b/arch/arm/boot/dts/imx6sl-kobo-aura2.dts @@ -0,0 +1,555 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device tree for the Kobo Aura 2 ebook reader + * + * Name on mainboard is: 37NB-E60QL0+4B1 + * Serials start with: E60QL2 + * + * Copyright 2022 Andreas Kemnade + */ + +/dts-v1/; + +#include <dt-bindings/input/input.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> +#include "imx6sl.dtsi" + +/ { + model = "Kobo Aura 2"; + compatible = "kobo,aura2", "fsl,imx6sl"; + + aliases { + mmc0 = &usdhc2; + mmc1 = &usdhc3; + }; + + chosen { + stdout-path = &uart1; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + key-cover { + label = "Cover"; + gpios = <&gpio5 12 GPIO_ACTIVE_LOW>; + linux,code = <SW_LID>; + linux,input-type = <EV_SW>; + wakeup-source; + }; + + key-power { + label = "Power"; + gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; + linux,code = <KEY_POWER>; + wakeup-source; + }; + }; + + leds: leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led>; + + led-0 { + label = "koboaura2:white:on"; + gpios = <&gpio5 7 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_WHITE>; + linux,default-trigger = "timer"; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; + }; + + reg_wifi: regulator-wifi { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi_power>; + regulator-name = "SD3_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi_reset>; + post-power-on-delay-ms = <20>; + reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + }; +}; + +&i2c1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_sleep>; + status = "okay"; + + lm3630a: backlight@36 { + compatible = "ti,lm3630a"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lm3630a_bl_gpio>; + reg = <0x36>; + enable-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; + + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + led-sources = <0>; + label = "backlight"; + default-brightness = <0>; + max-brightness = <255>; + }; + }; +}; + +&i2c2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_sleep>; + clock-frequency = <100000>; + status = "okay"; + + /* eKTF2232 at 0x15 */ + /* FP9928 at 0x48 */ +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clock-frequency = <400000>; + status = "okay"; + + ricoh619: pmic@32 { + compatible = "ricoh,rc5t619"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ricoh_gpio>; + reg = <0x32>; + interrupt-parent = <&gpio5>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + system-power-controller; + + regulators { + dcdc1_reg: DCDC1 { + regulator-name = "DCDC1"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-max-microvolt = <900000>; + regulator-suspend-min-microvolt = <900000>; + }; + }; + + /* Core3_3V3 */ + dcdc2_reg: DCDC2 { + regulator-name = "DCDC2"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-max-microvolt = <3100000>; + regulator-suspend-min-microvolt = <3100000>; + }; + }; + + dcdc3_reg: DCDC3 { + regulator-name = "DCDC3"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-max-microvolt = <1140000>; + regulator-suspend-min-microvolt = <1140000>; + }; + }; + + /* Core4_1V2 */ + dcdc4_reg: DCDC4 { + regulator-name = "DCDC4"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-max-microvolt = <1140000>; + regulator-suspend-min-microvolt = <1140000>; + }; + }; + + /* Core4_1V8 */ + dcdc5_reg: DCDC5 { + regulator-name = "DCDC5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-max-microvolt = <1700000>; + regulator-suspend-min-microvolt = <1700000>; + }; + }; + + /* IR_3V3 */ + ldo1_reg: LDO1 { + regulator-name = "LDO1"; + regulator-always-on; + regulator-boot-on; + }; + + /* Core1_3V3 */ + ldo2_reg: LDO2 { + regulator-name = "LDO2"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-max-microvolt = <3000000>; + regulator-suspend-min-microvolt = <3000000>; + }; + }; + + /* Core5_1V2 */ + ldo3_reg: LDO3 { + regulator-name = "LDO3"; + regulator-always-on; + regulator-boot-on; + }; + + ldo4_reg: LDO4 { + regulator-name = "LDO4"; + regulator-boot-on; + }; + + /* SPD_3V3 */ + ldo5_reg: LDO5 { + regulator-name = "LDO5"; + regulator-always-on; + regulator-boot-on; + }; + + /* DDR_0V6 */ + ldo6_reg: LDO6 { + regulator-name = "LDO6"; + regulator-always-on; + regulator-boot-on; + }; + + /* VDD_PWM */ + ldo7_reg: LDO7 { + regulator-name = "LDO7"; + regulator-always-on; + regulator-boot-on; + }; + + /* ldo_1v8 */ + ldo8_reg: LDO8 { + regulator-name = "LDO8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo9_reg: LDO9 { + regulator-name = "LDO9"; + regulator-boot-on; + }; + + ldo10_reg: LDO10 { + regulator-name = "LDO10"; + regulator-boot-on; + }; + + ldortc1_reg: LDORTC1 { + regulator-name = "LDORTC1"; + regulator-always-on; + regulator-boot-on; + }; + }; + }; +}; + +®_vdd1p1 { + vin-supply = <&dcdc2_reg>; +}; + +®_vdd2p5 { + vin-supply = <&dcdc2_reg>; +}; + +®_arm { + vin-supply = <&dcdc3_reg>; +}; + +®_soc { + vin-supply = <&dcdc1_reg>; +}; + +®_pu { + vin-supply = <&dcdc1_reg>; +}; + +&snvs_rtc { + /* + * We are using the RTC in the PMIC, but this one is not disabled + * in imx6sl.dtsi. + */ + status = "disabled"; +}; + +&uart1 { + /* J4, through-holes */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart4 { + /* TP198, next to J4, SMD pads */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + pinctrl-3 = <&pinctrl_usdhc2_sleep>; + non-removable; + status = "okay"; + + /* internal uSD card */ +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + pinctrl-3 = <&pinctrl_usdhc3_sleep>; + vmmc-supply = <®_wifi>; + mmc-pwrseq = <&wifi_pwrseq>; + cap-power-off-card; + non-removable; + status = "okay"; + + /* + * RTL8189F SDIO WiFi + */ +}; + +&usbotg1 { + disable-over-current; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&iomuxc { + pinctrl_gpio_keys: gpio-keysgrp { + fsl,pins = < + MX6SL_PAD_SD1_DAT1__GPIO5_IO08 0x17059 + MX6SL_PAD_SD1_DAT4__GPIO5_IO12 0x17059 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x4001f8b1 + MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x4001f8b1 + >; + }; + + pinctrl_i2c1_sleep: i2c1-sleepgrp { + fsl,pins = < + MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x400108b1 + MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x400108b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x4001f8b1 + MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x4001f8b1 + >; + }; + + pinctrl_i2c2_sleep: i2c2-sleepgrp { + fsl,pins = < + MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x400108b1 + MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x400108b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6SL_PAD_REF_CLK_24M__I2C3_SCL 0x4001f8b1 + MX6SL_PAD_REF_CLK_32K__I2C3_SDA 0x4001f8b1 + >; + }; + + pinctrl_led: ledgrp { + fsl,pins = < + MX6SL_PAD_SD1_DAT6__GPIO5_IO07 0x17059 + >; + }; + + pinctrl_lm3630a_bl_gpio: lm3630a-bl-gpiogrp { + fsl,pins = < + MX6SL_PAD_EPDC_PWRCTRL3__GPIO2_IO10 0x10059 /* HWEN */ + >; + }; + + pinctrl_ricoh_gpio: ricoh-gpiogrp { + fsl,pins = < + MX6SL_PAD_SD1_CLK__GPIO5_IO15 0x1b8b1 /* ricoh619 chg */ + MX6SL_PAD_SD1_DAT0__GPIO5_IO11 0x1b8b1 /* ricoh619 irq */ + MX6SL_PAD_KEY_COL2__GPIO3_IO28 0x1b8b1 /* ricoh619 bat_low_int */ + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1 + MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6SL_PAD_KEY_ROW6__UART4_TX_DATA 0x1b0b1 + MX6SL_PAD_KEY_COL6__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg1: usbotg1grp { + fsl,pins = < + MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6SL_PAD_SD2_CLK__SD2_CLK 0x13059 + MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX6SL_PAD_SD2_CMD__SD2_CMD 0x170b9 + MX6SL_PAD_SD2_CLK__SD2_CLK 0x130b9 + MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 + MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 + MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 + MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX6SL_PAD_SD2_CMD__SD2_CMD 0x170f9 + MX6SL_PAD_SD2_CLK__SD2_CLK 0x130f9 + MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 + MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 + MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 + MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc2_sleep: usdhc2-sleepgrp { + fsl,pins = < + MX6SL_PAD_SD2_CMD__GPIO5_IO04 0x100f9 + MX6SL_PAD_SD2_CLK__GPIO5_IO05 0x100f9 + MX6SL_PAD_SD2_DAT0__GPIO5_IO01 0x100f9 + MX6SL_PAD_SD2_DAT1__GPIO4_IO30 0x100f9 + MX6SL_PAD_SD2_DAT2__GPIO5_IO03 0x100f9 + MX6SL_PAD_SD2_DAT3__GPIO4_IO28 0x100f9 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6SL_PAD_SD3_CMD__SD3_CMD 0x11059 + MX6SL_PAD_SD3_CLK__SD3_CLK 0x11059 + MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x11059 + MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x11059 + MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x11059 + MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x11059 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9 + MX6SL_PAD_SD3_CLK__SD3_CLK 0x170b9 + MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 + MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 + MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 + MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9 + MX6SL_PAD_SD3_CLK__SD3_CLK 0x170f9 + MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 + MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 + MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 + MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc3_sleep: usdhc3-sleepgrp { + fsl,pins = < + MX6SL_PAD_SD3_CMD__GPIO5_IO21 0x100c1 + MX6SL_PAD_SD3_CLK__GPIO5_IO18 0x100c1 + MX6SL_PAD_SD3_DAT0__GPIO5_IO19 0x100c1 + MX6SL_PAD_SD3_DAT1__GPIO5_IO20 0x100c1 + MX6SL_PAD_SD3_DAT2__GPIO5_IO16 0x100c1 + MX6SL_PAD_SD3_DAT3__GPIO5_IO17 0x100c1 + >; + }; + + pinctrl_wifi_power: wifi-powergrp { + fsl,pins = < + MX6SL_PAD_SD2_DAT6__GPIO4_IO29 0x10059 /* WIFI_3V3_ON */ + >; + }; + + pinctrl_wifi_reset: wifi-resetgrp { + fsl,pins = < + MX6SL_PAD_SD2_DAT7__GPIO5_IO00 0x10059 /* WIFI_RST */ + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6sl-tolino-shine2hd.dts b/arch/arm/boot/dts/imx6sl-tolino-shine2hd.dts index 663ee9df79e6..da1399057634 100644 --- a/arch/arm/boot/dts/imx6sl-tolino-shine2hd.dts +++ b/arch/arm/boot/dts/imx6sl-tolino-shine2hd.dts @@ -18,6 +18,21 @@ model = "Tolino Shine 2 HD"; compatible = "kobo,tolino-shine2hd", "fsl,imx6sl"; + backlight { + compatible = "pwm-backlight"; + pwms = <&ec 0 50000>; + power-supply = <&backlight_regulator>; + }; + + backlight_regulator: regulator-backlight { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight_power>; + regulator-name = "backlight"; + gpio = <&gpio2 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + chosen { stdout-path = &uart1; }; @@ -65,6 +80,12 @@ gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; linux,default-trigger = "timer"; }; + + led-1 { + label = "tolinoshine2hd:white:backlightboost"; + gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "off"; + }; }; memory@80000000 { @@ -299,6 +320,12 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog>; + pinctrl_backlight_power: backlight-powergrp { + fsl,pins = < + MX6SL_PAD_EPDC_PWRCTRL3__GPIO2_IO10 0x10059 + >; + }; + pinctrl_gpio_keys: gpio-keysgrp { fsl,pins = < MX6SL_PAD_SD1_DAT1__GPIO5_IO08 0x17059 @@ -383,7 +410,8 @@ pinctrl_led: ledgrp { fsl,pins = < - MX6SL_PAD_SD1_DAT2__GPIO5_IO13 0x17059 + MX6SL_PAD_SD1_DAT2__GPIO5_IO13 0x17059 + MX6SL_PAD_EPDC_SDCE2__GPIO1_IO29 0x17059 >; }; diff --git a/arch/arm/boot/dts/imx6sl-tolino-shine3.dts b/arch/arm/boot/dts/imx6sl-tolino-shine3.dts index e3f1e8d79528..db5d8509935f 100644 --- a/arch/arm/boot/dts/imx6sl-tolino-shine3.dts +++ b/arch/arm/boot/dts/imx6sl-tolino-shine3.dts @@ -52,6 +52,13 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog>; + pinctrl_cyttsp5_gpio: cyttsp5-gpiogrp { + fsl,pins = < + MX6SL_PAD_SD1_DAT3__GPIO5_IO06 0x17059 /* TP_INT */ + MX6SL_PAD_SD1_DAT2__GPIO5_IO13 0x10059 /* TP_RST */ + >; + }; + pinctrl_gpio_keys: gpio-keysgrp { fsl,pins = < MX6SL_PAD_SD1_DAT1__GPIO5_IO08 0x17059 /* PWR_SW */ diff --git a/arch/arm/boot/dts/imx6sll-kobo-clarahd.dts b/arch/arm/boot/dts/imx6sll-kobo-clarahd.dts index 90b32f5eb529..c7cfe0b70f04 100644 --- a/arch/arm/boot/dts/imx6sll-kobo-clarahd.dts +++ b/arch/arm/boot/dts/imx6sll-kobo-clarahd.dts @@ -62,6 +62,13 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog>; + pinctrl_cyttsp5_gpio: cyttsp5-gpiogrp { + fsl,pins = < + MX6SLL_PAD_SD1_DATA3__GPIO5_IO06 0x17059 /* TP_INT */ + MX6SLL_PAD_SD1_DATA2__GPIO5_IO13 0x10059 /* TP_RST */ + >; + }; + pinctrl_gpio_keys: gpio-keysgrp { fsl,pins = < MX6SLL_PAD_SD1_DATA1__GPIO5_IO08 0x17059 /* PWR_SW */ diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index abc3572d699e..80f5efd65c2f 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -1391,7 +1391,7 @@ pwm8: pwm@22b0000 { compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; - reg = <0x0022b0000 0x4000>; + reg = <0x022b0000 0x4000>; interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SX_CLK_PWM8>, <&clks IMX6SX_CLK_PWM8>; diff --git a/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi index 3cddc68917a0..5168ed0ffec3 100644 --- a/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi +++ b/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi @@ -102,6 +102,10 @@ status = "disabled"; }; +&wdog1 { + fsl,suspend-in-wait; +}; + &iomuxc { pinctrl_enet1: enet1grp { fsl,pins = < diff --git a/arch/arm/boot/dts/imx6ull-colibri-aster.dts b/arch/arm/boot/dts/imx6ull-colibri-aster.dts index d3f2fb7c6c1e..3e0897c3a296 100644 --- a/arch/arm/boot/dts/imx6ull-colibri-aster.dts +++ b/arch/arm/boot/dts/imx6ull-colibri-aster.dts @@ -15,6 +15,46 @@ "fsl,imx6ull"; }; +&ad7879_ts { + status = "okay"; +}; + &atmel_mxt_ts { status = "okay"; }; + +&backlight { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&lcdif { + status = "okay"; +}; + +&panel_dpi { + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; + +/* PWM <B> */ +&pwm5 { + /* Pin already used by atmel_mxt_ts touchscreen */ + status = "disabled"; +}; + +/* PWM <C> */ +&pwm6 { + /* Pin already used by atmel_mxt_ts touchscreen */ + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dts b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dts index 9bf7111d7b00..d6da984e518d 100644 --- a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dts @@ -12,3 +12,27 @@ model = "Toradex Colibri iMX6ULL 256/512MB on Colibri Evaluation Board V3"; compatible = "toradex,colibri-imx6ull-eval", "fsl,imx6ull"; }; + +&ad7879_ts { + status = "okay"; +}; + +&backlight { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&lcdif { + status = "okay"; +}; + +&panel_dpi { + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6ull-colibri-iris-v2.dts b/arch/arm/boot/dts/imx6ull-colibri-iris-v2.dts index afc1e0119783..f6b31118be17 100644 --- a/arch/arm/boot/dts/imx6ull-colibri-iris-v2.dts +++ b/arch/arm/boot/dts/imx6ull-colibri-iris-v2.dts @@ -15,13 +15,21 @@ "fsl,imx6ull"; }; +&ad7879_ts { + status = "okay"; +}; + &atmel_mxt_ts { status = "okay"; }; +&backlight { + status = "okay"; +}; + &gpio1 { /* This turns the LVDS transceiver on */ - lvds-power-on { + lvds-power-on-hog { gpio-hog; gpios = <14 GPIO_ACTIVE_HIGH>; /* SODIMM 99 */ line-name = "LVDS_POWER_ON"; @@ -34,7 +42,7 @@ * This switches the LVDS transceiver to the single-channel * output mode. */ - lvds-ch-mode { + lvds-ch-mode-hog { gpio-hog; gpios = <0 GPIO_ACTIVE_HIGH>; /* SODIMM 55 */ line-name = "LVDS_CH_MODE"; @@ -44,7 +52,7 @@ /* * This switches the LVDS transceiver to the 24-bit RGB mode. */ - lvds-rgb-mode { + lvds-rgb-mode-hog { gpio-hog; gpios = <1 GPIO_ACTIVE_HIGH>; /* SODIMM 63 */ line-name = "LVDS_RGB_MODE"; @@ -56,10 +64,42 @@ /* * This switches the LVDS transceiver to VESA color mapping mode. */ - lvds-color-map { + lvds-color-map-hog { gpio-hog; gpios = <3 GPIO_ACTIVE_HIGH>; /* SODIMM 95 */ line-name = "LVDS_COLOR_MAP"; output-low; }; }; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&lcdif { + status = "okay"; +}; + +&panel_dpi { + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; + +/* PWM <B> */ +&pwm5 { + /* Pin already used by atmel_mxt_ts touchscreen */ + status = "disabled"; +}; + +/* PWM <C> */ +&pwm6 { + /* Pin already used by atmel_mxt_ts touchscreen */ + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx6ull-colibri-iris.dts b/arch/arm/boot/dts/imx6ull-colibri-iris.dts index 4fb97b0fe30b..2a0d0fc3b9d6 100644 --- a/arch/arm/boot/dts/imx6ull-colibri-iris.dts +++ b/arch/arm/boot/dts/imx6ull-colibri-iris.dts @@ -15,6 +15,26 @@ "fsl,imx6ull"; }; -&atmel_mxt_ts { +&ad7879_ts { + status = "okay"; +}; + +&backlight { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&lcdif { + status = "okay"; +}; + +&panel_dpi { + status = "okay"; +}; + +&pwm4 { status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6ull-colibri-iris.dtsi b/arch/arm/boot/dts/imx6ull-colibri-iris.dtsi index 7f3b37baba88..166a0aefc869 100644 --- a/arch/arm/boot/dts/imx6ull-colibri-iris.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri-iris.dtsi @@ -59,7 +59,7 @@ * in userspace. * The same applies to uart1_tx_on. */ - uart25_tx_on { + uart25_tx_on-hog { gpio-hog; gpios = <15 0>; output-high; @@ -67,7 +67,7 @@ }; &gpio2 { - uart1_tx_on { + uart1_tx_on-hog { gpio-hog; gpios = <7 0>; output-high; diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi-aster.dts b/arch/arm/boot/dts/imx6ull-colibri-wifi-aster.dts index b4f65e8c5857..c7da5b41966f 100644 --- a/arch/arm/boot/dts/imx6ull-colibri-wifi-aster.dts +++ b/arch/arm/boot/dts/imx6ull-colibri-wifi-aster.dts @@ -15,6 +15,46 @@ "fsl,imx6ull"; }; +&ad7879_ts { + status = "okay"; +}; + &atmel_mxt_ts { status = "okay"; }; + +&backlight { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&lcdif { + status = "okay"; +}; + +&panel_dpi { + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; + +/* PWM <B> */ +&pwm5 { + /* Pin already used by atmel_mxt_ts touchscreen */ + status = "disabled"; +}; + +/* PWM <C> */ +&pwm6 { + /* Pin already used by atmel_mxt_ts touchscreen */ + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi-eval-v3.dts b/arch/arm/boot/dts/imx6ull-colibri-wifi-eval-v3.dts index 1d64d1a5d8a7..917f5dbe64ba 100644 --- a/arch/arm/boot/dts/imx6ull-colibri-wifi-eval-v3.dts +++ b/arch/arm/boot/dts/imx6ull-colibri-wifi-eval-v3.dts @@ -12,3 +12,27 @@ model = "Toradex Colibri iMX6ULL 512MB on Colibri Evaluation Board V3"; compatible = "toradex,colibri-imx6ull-wifi-eval", "fsl,imx6ull"; }; + +&ad7879_ts { + status = "okay"; +}; + +&backlight { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&lcdif { + status = "okay"; +}; + +&panel_dpi { + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi-iris-v2.dts b/arch/arm/boot/dts/imx6ull-colibri-wifi-iris-v2.dts index ce02f8a9ddd3..488da6df56fa 100644 --- a/arch/arm/boot/dts/imx6ull-colibri-wifi-iris-v2.dts +++ b/arch/arm/boot/dts/imx6ull-colibri-wifi-iris-v2.dts @@ -15,13 +15,21 @@ "fsl,imx6ull"; }; +&ad7879_ts { + status = "okay"; +}; + &atmel_mxt_ts { status = "okay"; }; +&backlight { + status = "okay"; +}; + &gpio1 { /* This turns the LVDS transceiver on */ - lvds-power-on { + lvds-power-on-hog { gpio-hog; gpios = <14 GPIO_ACTIVE_HIGH>; /* SODIMM 99 */ line-name = "LVDS_POWER_ON"; @@ -34,7 +42,7 @@ * This switches the LVDS transceiver to the single-channel * output mode. */ - lvds-ch-mode { + lvds-ch-mode-hog { gpio-hog; gpios = <0 GPIO_ACTIVE_HIGH>; /* SODIMM 55 */ line-name = "LVDS_CH_MODE"; @@ -44,7 +52,7 @@ /* * This switches the LVDS transceiver to the 24-bit RGB mode. */ - lvds-rgb-mode { + lvds-rgb-mode-hog { gpio-hog; gpios = <1 GPIO_ACTIVE_HIGH>; /* SODIMM 63 */ line-name = "LVDS_RGB_MODE"; @@ -56,10 +64,26 @@ /* * This switches the LVDS transceiver to VESA color mapping mode. */ - lvds-color-map { + lvds-color-map-hog { gpio-hog; gpios = <3 GPIO_ACTIVE_HIGH>; /* SODIMM 95 */ line-name = "LVDS_COLOR_MAP"; output-low; }; }; + +&i2c2 { + status = "okay"; +}; + +&lcdif { + status = "okay"; +}; + +&panel_dpi { + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi-iris.dts b/arch/arm/boot/dts/imx6ull-colibri-wifi-iris.dts index 5ac1aa298ce7..e63253254754 100644 --- a/arch/arm/boot/dts/imx6ull-colibri-wifi-iris.dts +++ b/arch/arm/boot/dts/imx6ull-colibri-wifi-iris.dts @@ -15,6 +15,26 @@ "fsl,imx6ull"; }; +&ad7879_ts { + status = "okay"; +}; + &atmel_mxt_ts { status = "okay"; }; + +&backlight { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&lcdif { + status = "okay"; +}; + +&panel_dpi { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi index 577a424b0e1d..336ab2e0534c 100644 --- a/arch/arm/boot/dts/imx6ull-colibri.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi @@ -21,7 +21,29 @@ pinctrl-0 = <&pinctrl_gpio_bl_on>; power-supply = <®_3v3>; pwms = <&pwm4 0 5000000 1>; - status = "okay"; + status = "disabled"; + }; + + connector { + compatible = "gpio-usb-b-connector", "usb-b-connector"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_snvs_usbc_det>; + id-gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; /* SODIMM 137 / USBC_DET */ + label = "USBC"; + self-powered; + type = "micro"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usb_dr_connector: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; + }; }; gpio-keys { @@ -42,7 +64,7 @@ compatible = "edt,et057090dhu"; backlight = <&backlight>; power-supply = <®_3v3>; - status = "okay"; + status = "disabled"; port { lcd_panel_in: endpoint { @@ -159,7 +181,7 @@ pinctrl-1 = <&pinctrl_i2c1_gpio>; sda-gpios = <&gpio1 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; scl-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - status = "okay"; + status = "disabled"; /* Atmel maxtouch controller */ atmel_mxt_ts: touchscreen@4a { @@ -202,6 +224,7 @@ adi,median-filter-size = /bits/ 8 <2>; adi,averaging = /bits/ 8 <1>; adi,conversion-interval = /bits/ 8 <255>; + status = "disabled"; }; }; @@ -209,6 +232,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lcdif_dat &pinctrl_lcdif_ctrl>; + status = "disabled"; port { lcdif_out: endpoint { @@ -278,6 +302,13 @@ srp-disable; hnp-disable; adp-disable; + usb-role-switch; + + port { + usb1_drd_sw: endpoint { + remote-endpoint = <&usb_dr_connector>; + }; + }; }; /* Colibri USBH */ diff --git a/arch/arm/boot/dts/imx7-colibri.dtsi b/arch/arm/boot/dts/imx7-colibri.dtsi index a8c31ee65623..f8b8372b6851 100644 --- a/arch/arm/boot/dts/imx7-colibri.dtsi +++ b/arch/arm/boot/dts/imx7-colibri.dtsi @@ -29,7 +29,6 @@ extcon_usbc_det: usbc-det { compatible = "linux,extcon-usb-gpio"; - debounce = <25>; id-gpio = <&gpio7 14 GPIO_ACTIVE_HIGH>; /* SODIMM 137 / USBC_DET */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usbc_det>; @@ -652,7 +651,7 @@ * NOTE: This pin group conflicts with pin groups pinctrl_pwm2/pinctrl_pwm3. * Don't use them simultaneously. */ - pinctrl_atmel_adapter: atmelconnectorgrp { + pinctrl_atmel_adapter: atmeladaptergrp { fsl,pins = < MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x74 /* SODIMM 28 / INT */ MX7D_PAD_GPIO1_IO10__GPIO1_IO10 0x14 /* SODIMM 30 / RST */ @@ -660,7 +659,7 @@ }; /* Atmel MXT touchsceen + boards with built-in Capacitive Touch Connector */ - pinctrl_atmel_connector: atmeladaptergrp { + pinctrl_atmel_connector: atmelconnectorgrp { fsl,pins = < MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x14 /* SODIMM 106 / RST */ MX7D_PAD_EPDC_DATA15__GPIO2_IO15 0x74 /* SODIMM 107 / INT */ diff --git a/arch/arm/boot/dts/imx7d-remarkable2.dts b/arch/arm/boot/dts/imx7d-remarkable2.dts index a2a91bfdd98e..8b2f11e85e05 100644 --- a/arch/arm/boot/dts/imx7d-remarkable2.dts +++ b/arch/arm/boot/dts/imx7d-remarkable2.dts @@ -22,6 +22,28 @@ reg = <0x80000000 0x40000000>; }; + thermal-zones { + epd-thermal { + thermal-sensors = <&sy7636a>; + polling-delay-passive = <30000>; + polling-delay = <30000>; + + trips { + trip0 { + temperature = <49000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip1 { + temperature = <50000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + reg_brcm: regulator-brcm { compatible = "regulator-fixed"; regulator-name = "brcm_reg"; @@ -84,6 +106,32 @@ }; }; +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4>; + status = "okay"; + + sy7636a: pmic@62 { + compatible = "silergy,sy7636a"; + reg = <0x62>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_epdpmic>; + #address-cells = <1>; + #size-cells = <0>; + #thermal-sensor-cells = <0>; + epd-pwr-good-gpios = <&gpio6 21 GPIO_ACTIVE_HIGH>; + + regulators { + reg_epdpmic: vcom { + regulator-name = "vcom"; + regulator-boot-on; + }; + }; + }; +}; + &snvs_pwrkey { status = "okay"; }; @@ -177,6 +225,13 @@ >; }; + pinctrl_epdpmic: epdpmicgrp { + fsl,pins = < + MX7D_PAD_SAI2_RX_DATA__GPIO6_IO21 0x00000074 + MX7D_PAD_ENET1_RGMII_TXC__GPIO7_IO11 0x00000014 + >; + }; + pinctrl_i2c1: i2c1grp { fsl,pins = < MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f @@ -184,6 +239,13 @@ >; }; + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX7D_PAD_I2C4_SDA__I2C4_SDA 0x4000007f + MX7D_PAD_I2C4_SCL__I2C4_SCL 0x4000007f + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 diff --git a/arch/arm/boot/dts/kirkwood-b3.dts b/arch/arm/boot/dts/kirkwood-b3.dts index a7636fe28501..681343c1357a 100644 --- a/arch/arm/boot/dts/kirkwood-b3.dts +++ b/arch/arm/boot/dts/kirkwood-b3.dts @@ -187,7 +187,7 @@ /* Wifi model has Atheros chipset on pcie port */ &pciec { - status = "okay"; + status = "okay"; }; &pcie0 { diff --git a/arch/arm/boot/dts/kirkwood-db-88f6281.dts b/arch/arm/boot/dts/kirkwood-db-88f6281.dts index 2adb17c955aa..a9a8e6b744c7 100644 --- a/arch/arm/boot/dts/kirkwood-db-88f6281.dts +++ b/arch/arm/boot/dts/kirkwood-db-88f6281.dts @@ -18,7 +18,7 @@ }; &pciec { - status = "okay"; + status = "okay"; }; &pcie0 { diff --git a/arch/arm/boot/dts/kirkwood-db-88f6282.dts b/arch/arm/boot/dts/kirkwood-db-88f6282.dts index f84a48539917..6dc6579d4524 100644 --- a/arch/arm/boot/dts/kirkwood-db-88f6282.dts +++ b/arch/arm/boot/dts/kirkwood-db-88f6282.dts @@ -18,7 +18,7 @@ }; &pciec { - status = "okay"; + status = "okay"; }; &pcie0 { diff --git a/arch/arm/boot/dts/kirkwood-dir665.dts b/arch/arm/boot/dts/kirkwood-dir665.dts index c32300611d2c..f9f4b0143ba8 100644 --- a/arch/arm/boot/dts/kirkwood-dir665.dts +++ b/arch/arm/boot/dts/kirkwood-dir665.dts @@ -211,18 +211,18 @@ }; port@1 { - reg = <1>; - label = "lan3"; + reg = <1>; + label = "lan3"; }; port@2 { - reg = <2>; - label = "lan2"; + reg = <2>; + label = "lan2"; }; port@3 { - reg = <3>; - label = "lan1"; + reg = <3>; + label = "lan1"; }; port@4 { @@ -268,7 +268,7 @@ }; &pciec { - status = "okay"; + status = "okay"; }; &pcie0 { diff --git a/arch/arm/boot/dts/kirkwood-ds112.dts b/arch/arm/boot/dts/kirkwood-ds112.dts index f48609e95afe..3912f1b525b6 100644 --- a/arch/arm/boot/dts/kirkwood-ds112.dts +++ b/arch/arm/boot/dts/kirkwood-ds112.dts @@ -43,7 +43,7 @@ }; &pciec { - status = "okay"; + status = "okay"; }; &pcie1 { diff --git a/arch/arm/boot/dts/kirkwood-ds411.dts b/arch/arm/boot/dts/kirkwood-ds411.dts index 86907be70cf9..1d4256ef325d 100644 --- a/arch/arm/boot/dts/kirkwood-ds411.dts +++ b/arch/arm/boot/dts/kirkwood-ds411.dts @@ -47,7 +47,7 @@ }; &pciec { - status = "okay"; + status = "okay"; }; &pcie1 { diff --git a/arch/arm/boot/dts/kirkwood-iconnect.dts b/arch/arm/boot/dts/kirkwood-iconnect.dts index 95af7aa1fdcb..aed20185fd7a 100644 --- a/arch/arm/boot/dts/kirkwood-iconnect.dts +++ b/arch/arm/boot/dts/kirkwood-iconnect.dts @@ -187,7 +187,7 @@ }; &pciec { - status = "okay"; + status = "okay"; }; &pcie0 { diff --git a/arch/arm/boot/dts/kirkwood-km_common.dtsi b/arch/arm/boot/dts/kirkwood-km_common.dtsi index 75dc83914f56..52baffe45f12 100644 --- a/arch/arm/boot/dts/kirkwood-km_common.dtsi +++ b/arch/arm/boot/dts/kirkwood-km_common.dtsi @@ -39,7 +39,7 @@ }; &pciec { - status = "okay"; + status = "okay"; }; &pcie0 { diff --git a/arch/arm/boot/dts/kirkwood-l-50.dts b/arch/arm/boot/dts/kirkwood-l-50.dts index 0d81c43a6a73..60c1e94f5dd3 100644 --- a/arch/arm/boot/dts/kirkwood-l-50.dts +++ b/arch/arm/boot/dts/kirkwood-l-50.dts @@ -223,18 +223,18 @@ }; port@1 { - reg = <1>; - label = "lan1"; + reg = <1>; + label = "lan1"; }; port@2 { - reg = <2>; - label = "lan6"; + reg = <2>; + label = "lan6"; }; port@3 { - reg = <3>; - label = "lan2"; + reg = <3>; + label = "lan2"; }; port@4 { @@ -282,18 +282,18 @@ }; port@1 { - reg = <1>; - label = "lan8"; + reg = <1>; + label = "lan8"; }; port@2 { - reg = <2>; - label = "lan4"; + reg = <2>; + label = "lan4"; }; port@3 { - reg = <3>; - label = "dmz"; + reg = <3>; + label = "dmz"; }; switch1port5: port@5 { diff --git a/arch/arm/boot/dts/kirkwood-laplug.dts b/arch/arm/boot/dts/kirkwood-laplug.dts index 6158214a939a..8c2b540eaf4f 100644 --- a/arch/arm/boot/dts/kirkwood-laplug.dts +++ b/arch/arm/boot/dts/kirkwood-laplug.dts @@ -160,7 +160,7 @@ }; &pciec { - status = "okay"; + status = "okay"; }; &pcie0 { diff --git a/arch/arm/boot/dts/kirkwood-linkstation.dtsi b/arch/arm/boot/dts/kirkwood-linkstation.dtsi index 407d6d8b3a7f..b54c9980f636 100644 --- a/arch/arm/boot/dts/kirkwood-linkstation.dtsi +++ b/arch/arm/boot/dts/kirkwood-linkstation.dtsi @@ -156,7 +156,7 @@ }; &pciec { - status = "okay"; + status = "okay"; }; &pcie0 { diff --git a/arch/arm/boot/dts/kirkwood-mplcec4.dts b/arch/arm/boot/dts/kirkwood-mplcec4.dts index b80d12f6aa49..e87ea7146546 100644 --- a/arch/arm/boot/dts/kirkwood-mplcec4.dts +++ b/arch/arm/boot/dts/kirkwood-mplcec4.dts @@ -8,10 +8,10 @@ model = "MPL CEC4"; compatible = "mpl,cec4-10", "mpl,cec4", "marvell,kirkwood-88f6281", "marvell,kirkwood"; - memory { - device_type = "memory"; - reg = <0x00000000 0x20000000>; - }; + memory { + device_type = "memory"; + reg = <0x00000000 0x20000000>; + }; chosen { bootargs = "console=ttyS0,115200n8 earlyprintk"; @@ -66,8 +66,8 @@ }; }; - i2c@11000 { - status = "okay"; + i2c@11000 { + status = "okay"; rtc@51 { compatible = "nxp,pcf8563"; @@ -79,7 +79,7 @@ reg = <0x57>; }; - }; + }; serial@12000 { status = "okay"; @@ -208,7 +208,7 @@ }; &pciec { - status = "okay"; + status = "okay"; }; &pcie0 { diff --git a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts b/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts index 2e1a75348908..ced576acfb95 100644 --- a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts +++ b/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts @@ -170,7 +170,7 @@ }; &pciec { - status = "okay"; + status = "okay"; }; &pcie0 { diff --git a/arch/arm/boot/dts/kirkwood-nas2big.dts b/arch/arm/boot/dts/kirkwood-nas2big.dts index 6a2934b7d0ce..0b0a15093146 100644 --- a/arch/arm/boot/dts/kirkwood-nas2big.dts +++ b/arch/arm/boot/dts/kirkwood-nas2big.dts @@ -131,7 +131,7 @@ }; &pciec { - status = "okay"; + status = "okay"; }; &pcie0 { diff --git a/arch/arm/boot/dts/kirkwood-net2big.dts b/arch/arm/boot/dts/kirkwood-net2big.dts index 3e3ac289e5b0..d5f6bb50ba11 100644 --- a/arch/arm/boot/dts/kirkwood-net2big.dts +++ b/arch/arm/boot/dts/kirkwood-net2big.dts @@ -46,11 +46,11 @@ }; clocks { - g762_clk: g762-oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; + g762_clk: g762-oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; }; }; diff --git a/arch/arm/boot/dts/kirkwood-net5big.dts b/arch/arm/boot/dts/kirkwood-net5big.dts index cba8a2b6f6d9..2497ad26b5b6 100644 --- a/arch/arm/boot/dts/kirkwood-net5big.dts +++ b/arch/arm/boot/dts/kirkwood-net5big.dts @@ -78,11 +78,11 @@ }; clocks { - g762_clk: g762-oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; + g762_clk: g762-oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; }; netxbig-leds { diff --git a/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts b/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts index b13aee570804..6cf76430cfab 100644 --- a/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts +++ b/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts @@ -78,11 +78,11 @@ }; clocks { - g762_clk: g762-oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <8192>; - }; + g762_clk: g762-oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <8192>; + }; }; i2c@11000 { @@ -266,7 +266,7 @@ /* Connected to NEC uPD720200 USB 3.0 controller */ &pciec { - status = "okay"; + status = "okay"; }; &pcie0 { diff --git a/arch/arm/boot/dts/kirkwood-nsa310.dts b/arch/arm/boot/dts/kirkwood-nsa310.dts index 9b861c2e76c5..c1799a07816e 100644 --- a/arch/arm/boot/dts/kirkwood-nsa310.dts +++ b/arch/arm/boot/dts/kirkwood-nsa310.dts @@ -131,7 +131,7 @@ }; &pciec { - status = "okay"; + status = "okay"; }; &pcie0 { diff --git a/arch/arm/boot/dts/kirkwood-nsa310s.dts b/arch/arm/boot/dts/kirkwood-nsa310s.dts new file mode 100644 index 000000000000..49da633a1bc0 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-nsa310s.dts @@ -0,0 +1,259 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * ZyXEL NSA310S Board Description + * Copyright 2020-2022 Pawel Dembicki <paweldembicki@gmail.com> + * Copyright (c) 2015-2021, Tony Dinh <mibodhi@gmail.com> + * Copyright (c) 2014, Adam Baker <linux@baker-net.org.uk> + * Based upon the board setup file created by Peter Schildmann + */ +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" +#include <dt-bindings/leds/common.h> + +/ { + model = "ZyXEL NSA310S"; + compatible = "zyxel,nsa310s", "marvell,kirkwood-88f6702", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x10000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; + }; + + gpio_poweroff { + compatible = "gpio-poweroff"; + pinctrl-0 = <&pmx_pwr_off>; + pinctrl-names = "default"; + gpios = <&gpio0 27 GPIO_ACTIVE_HIGH>; + }; + + keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_buttons>; + pinctrl-names = "default"; + + power { + label = "Power Button"; + linux,code = <KEY_POWER>; + gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>; + }; + + copy { + label = "Copy Button"; + linux,code = <KEY_COPY>; + gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; + }; + + reset { + label = "Reset Button"; + linux,code = <KEY_RESTART>; + gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_leds>; + pinctrl-names = "default"; + + led-1 { + function = LED_FUNCTION_DISK_ERR; + color = <LED_COLOR_ID_RED>; + gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; + }; + + led-2 { + function = LED_FUNCTION_USB; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "usb-host"; + }; + + led-3 { + function = LED_FUNCTION_DISK; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "ata1"; + }; + + led-4 { + function = LED_FUNCTION_INDICATOR; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>; + }; + + led-5 { + function = LED_FUNCTION_INDICATOR; + color = <LED_COLOR_ID_RED>; + gpios = <&gpio0 23 GPIO_ACTIVE_HIGH>; + }; + + led-6 { + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + led-7 { + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_RED>; + gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; + }; + }; + + usb0_power: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "USB Power"; + + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 21 GPIO_ACTIVE_HIGH>; + }; + + sata1_power: regulator@2 { + compatible = "regulator-fixed"; + regulator-name = "SATA1 Power"; + + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>; + }; + + thermal-zones { + disk-thermal { + polling-delay = <20000>; + polling-delay-passive = <2000>; + + thermal-sensors = <&hdd_temp>; + + trips { + disk_alert: disk-alert { + temperature = <40000>; + hysteresis = <5000>; + type = "active"; + }; + disk_crit: disk-crit { + temperature = <60000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; +}; + + +ð0 { + status = "okay"; + + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; +}; + +&i2c0 { + status = "okay"; + + rtc@68 { + compatible = "htk,ht1382"; + reg = <0x68>; + }; +}; + +&mdio { + status = "okay"; + + ethphy0: ethernet-phy@1 { + reg = <1>; + phy-mode = "rgmii-id"; + marvell,reg-init = <0x1 0x16 0x0 0x3>, + <0x1 0x10 0x0 0x1017>, + <0x1 0x11 0x0 0x4408>, + <0x1 0x16 0x0 0x0>; + }; +}; + +&nand { + status = "okay"; + chip-delay = <35>; + + partition@0 { + label = "uboot"; + reg = <0x0000000 0x00c0000>; + read-only; + }; + partition@c0000 { + label = "uboot_env"; + reg = <0x00c0000 0x0080000>; + }; + partition@140000 { + label = "ubi"; + reg = <0x0140000 0x7ec0000>; + }; +}; + +&pciec { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; + +&pinctrl { + pinctrl-names = "default"; + + pmx_buttons: pmx-buttons { + marvell,pins = "mpp24", "mpp25", "mpp26"; + marvell,function = "gpio"; + }; + + pmx_leds: pmx-leds { + marvell,pins = "mpp13", "mpp15", "mpp16", "mpp22", "mpp23", + "mpp28", "mpp29"; + marvell,function = "gpio"; + }; + + pmx_power: pmx-power { + marvell,pins = "mpp21", "mpp33"; + marvell,function = "gpio"; + }; + + pmx_pwr_off: pmx-pwr-off { + marvell,pins = "mpp27"; + marvell,function = "gpio"; + }; +}; + +&rtc { + status = "disabled"; +}; + +&sata { + status = "okay"; + nr-ports = <1>; + #address-cells = <1>; + #size-cells = <0>; + + hdd_temp: sata-port@0 { + reg = <0>; + #thermal-sensor-cells = <0>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/kirkwood-nsa320.dts b/arch/arm/boot/dts/kirkwood-nsa320.dts index b69b096f267b..652405e65006 100644 --- a/arch/arm/boot/dts/kirkwood-nsa320.dts +++ b/arch/arm/boot/dts/kirkwood-nsa320.dts @@ -211,7 +211,7 @@ }; &pciec { - status = "okay"; + status = "okay"; }; &pcie0 { diff --git a/arch/arm/boot/dts/kirkwood-nsa325.dts b/arch/arm/boot/dts/kirkwood-nsa325.dts index 6f8085dbb1f4..371456de34b2 100644 --- a/arch/arm/boot/dts/kirkwood-nsa325.dts +++ b/arch/arm/boot/dts/kirkwood-nsa325.dts @@ -224,7 +224,7 @@ }; &pciec { - status = "okay"; + status = "okay"; }; &pcie0 { diff --git a/arch/arm/boot/dts/kirkwood-nsa3x0-common.dtsi b/arch/arm/boot/dts/kirkwood-nsa3x0-common.dtsi index 8f73197f251a..ea3d36512e9f 100644 --- a/arch/arm/boot/dts/kirkwood-nsa3x0-common.dtsi +++ b/arch/arm/boot/dts/kirkwood-nsa3x0-common.dtsi @@ -150,7 +150,7 @@ }; &pciec { - status = "okay"; + status = "okay"; }; &pcie0 { diff --git a/arch/arm/boot/dts/kirkwood-rd88f6192.dts b/arch/arm/boot/dts/kirkwood-rd88f6192.dts index 712d6042b132..f00325ffde07 100644 --- a/arch/arm/boot/dts/kirkwood-rd88f6192.dts +++ b/arch/arm/boot/dts/kirkwood-rd88f6192.dts @@ -31,10 +31,10 @@ pinctrl-0 = <&pmx_usb_power>; pinctrl-names = "default"; - pmx_usb_power: pmx-usb-power { - marvell,pins = "mpp10"; - marvell,function = "gpo"; - }; + pmx_usb_power: pmx-usb-power { + marvell,pins = "mpp10"; + marvell,function = "gpo"; + }; }; serial@12000 { @@ -62,43 +62,43 @@ }; regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pmx_usb_power>; - pinctrl-names = "default"; - - usb_power: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "USB VBUS"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 10 GPIO_ACTIVE_HIGH>; - }; + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_usb_power>; + pinctrl-names = "default"; + + usb_power: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "USB VBUS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 10 GPIO_ACTIVE_HIGH>; + }; }; }; &mdio { - status = "okay"; + status = "okay"; - ethphy0: ethernet-phy@8 { - reg = <8>; - }; + ethphy0: ethernet-phy@8 { + reg = <8>; + }; }; ð0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <ðphy0>; - }; + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy0>; + }; }; &pciec { - status = "okay"; + status = "okay"; }; &pcie0 { diff --git a/arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts b/arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts index 9d88301daf0e..72edd47e19ff 100644 --- a/arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts +++ b/arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts @@ -19,7 +19,7 @@ }; ð1 { - status = "disabled"; + status = "disabled"; }; &switch { diff --git a/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi b/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi index f1f8eee132e8..e21aa674945d 100644 --- a/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi +++ b/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi @@ -48,7 +48,7 @@ cd-gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; /* No WP GPIO */ }; - }; + }; }; &nand { @@ -126,7 +126,7 @@ }; &pciec { - status = "okay"; + status = "okay"; }; &pcie0 { diff --git a/arch/arm/boot/dts/kirkwood-rs212.dts b/arch/arm/boot/dts/kirkwood-rs212.dts index c51cea883215..4ad412115a24 100644 --- a/arch/arm/boot/dts/kirkwood-rs212.dts +++ b/arch/arm/boot/dts/kirkwood-rs212.dts @@ -43,7 +43,7 @@ }; &pciec { - status = "okay"; + status = "okay"; }; &pcie1 { diff --git a/arch/arm/boot/dts/kirkwood-synology.dtsi b/arch/arm/boot/dts/kirkwood-synology.dtsi index 8f6c387d3a8b..9b6666020cdd 100644 --- a/arch/arm/boot/dts/kirkwood-synology.dtsi +++ b/arch/arm/boot/dts/kirkwood-synology.dtsi @@ -847,7 +847,7 @@ }; &pciec { - status = "okay"; + status = "okay"; }; &pcie0 { diff --git a/arch/arm/boot/dts/kirkwood-t5325.dts b/arch/arm/boot/dts/kirkwood-t5325.dts index fe63b3a03a72..ad093324e075 100644 --- a/arch/arm/boot/dts/kirkwood-t5325.dts +++ b/arch/arm/boot/dts/kirkwood-t5325.dts @@ -219,7 +219,7 @@ }; &pciec { - status = "okay"; + status = "okay"; }; &pcie0 { diff --git a/arch/arm/boot/dts/kirkwood-ts219.dtsi b/arch/arm/boot/dts/kirkwood-ts219.dtsi index 994cabcf4b51..1939462a5f48 100644 --- a/arch/arm/boot/dts/kirkwood-ts219.dtsi +++ b/arch/arm/boot/dts/kirkwood-ts219.dtsi @@ -86,7 +86,7 @@ status = "okay"; ethphy0: ethernet-phy@X { - /* overwrite reg property in board file */ + /* overwrite reg property in board file */ }; }; @@ -98,7 +98,7 @@ }; &pciec { - status = "okay"; + status = "okay"; }; &pcie0 { diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi index fca31a5d5ac7..815ef7719d13 100644 --- a/arch/arm/boot/dts/kirkwood.dtsi +++ b/arch/arm/boot/dts/kirkwood.dtsi @@ -24,9 +24,9 @@ }; aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - i2c0 = &i2c0; + gpio0 = &gpio0; + gpio1 = &gpio1; + i2c0 = &i2c0; }; mbus@f1000000 { @@ -279,15 +279,15 @@ clocks = <&gate_clk 8>; xor00 { - interrupts = <5>; - dmacap,memcpy; - dmacap,xor; + interrupts = <5>; + dmacap,memcpy; + dmacap,xor; }; xor01 { - interrupts = <6>; - dmacap,memcpy; - dmacap,xor; - dmacap,memset; + interrupts = <6>; + dmacap,memcpy; + dmacap,xor; + dmacap,memset; }; }; @@ -299,15 +299,15 @@ clocks = <&gate_clk 16>; xor00 { - interrupts = <7>; - dmacap,memcpy; - dmacap,xor; + interrupts = <7>; + dmacap,memcpy; + dmacap,xor; }; xor01 { - interrupts = <8>; - dmacap,memcpy; - dmacap,xor; - dmacap,memset; + interrupts = <8>; + dmacap,memcpy; + dmacap,xor; + dmacap,memset; }; }; diff --git a/arch/arm/boot/dts/lan966x-pcb8290.dts b/arch/arm/boot/dts/lan966x-pcb8290.dts index 77187f59f04d..8804e8ba5370 100644 --- a/arch/arm/boot/dts/lan966x-pcb8290.dts +++ b/arch/arm/boot/dts/lan966x-pcb8290.dts @@ -58,41 +58,57 @@ ext_phy0: ethernet-phy@7 { reg = <7>; + interrupts = <24 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>; }; ext_phy1: ethernet-phy@8 { reg = <8>; + interrupts = <24 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>; }; ext_phy2: ethernet-phy@9 { reg = <9>; + interrupts = <24 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>; }; ext_phy3: ethernet-phy@10 { reg = <10>; + interrupts = <24 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>; }; ext_phy4: ethernet-phy@15 { reg = <15>; + interrupts = <24 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>; }; ext_phy5: ethernet-phy@16 { reg = <16>; + interrupts = <24 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>; }; ext_phy6: ethernet-phy@17 { reg = <17>; + interrupts = <24 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>; }; ext_phy7: ethernet-phy@18 { reg = <18>; + interrupts = <24 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; coma-mode-gpios = <&gpio 60 GPIO_OPEN_DRAIN>; }; }; diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi index 0bf818713422..05b73f7cf0c7 100644 --- a/arch/arm/boot/dts/lan966x.dtsi +++ b/arch/arm/boot/dts/lan966x.dtsi @@ -157,6 +157,11 @@ }; }; + otp: otp@e0021000 { + compatible = "microchip,lan9668-otpc", "microchip,lan9662-otpc"; + reg = <0xe0021000 0x300>; + }; + flx0: flexcom@e0040000 { compatible = "atmel,sama5d2-flexcom"; reg = <0xe0040000 0x100>; diff --git a/arch/arm/boot/dts/logicpd-torpedo-baseboard.dtsi b/arch/arm/boot/dts/logicpd-torpedo-baseboard.dtsi index d3da8b1b473b..e0cbac500e17 100644 --- a/arch/arm/boot/dts/logicpd-torpedo-baseboard.dtsi +++ b/arch/arm/boot/dts/logicpd-torpedo-baseboard.dtsi @@ -59,7 +59,7 @@ }; }; - pwm10: dmtimer-pwm { + pwm10: pwm-10 { compatible = "ti,omap-dmtimer-pwm"; pinctrl-names = "default"; pinctrl-0 = <&pwm_pins>; diff --git a/arch/arm/boot/dts/logicpd-torpedo-som.dtsi b/arch/arm/boot/dts/logicpd-torpedo-som.dtsi index 3a5228562b0d..72b5af475d09 100644 --- a/arch/arm/boot/dts/logicpd-torpedo-som.dtsi +++ b/arch/arm/boot/dts/logicpd-torpedo-som.dtsi @@ -20,7 +20,7 @@ leds { compatible = "gpio-leds"; - user0 { + led-user0 { label = "user0"; gpios = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* LEDA */ linux,default-trigger = "none"; diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi index c87066d6c995..974410918f35 100644 --- a/arch/arm/boot/dts/lpc32xx.dtsi +++ b/arch/arm/boot/dts/lpc32xx.dtsi @@ -315,7 +315,7 @@ /* System Control Block */ scb { compatible = "simple-bus"; - ranges = <0x0 0x040004000 0x00001000>; + ranges = <0x0 0x40004000 0x00001000>; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts b/arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts index f3ddea934f1b..d2cae8c7d7a6 100644 --- a/arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts +++ b/arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts @@ -30,11 +30,11 @@ }; reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; }; leds { diff --git a/arch/arm/boot/dts/motorola-mapphone-common.dtsi b/arch/arm/boot/dts/motorola-mapphone-common.dtsi index c7a1f3ffc48c..f7cc8fc678fa 100644 --- a/arch/arm/boot/dts/motorola-mapphone-common.dtsi +++ b/arch/arm/boot/dts/motorola-mapphone-common.dtsi @@ -133,7 +133,7 @@ dais = <&mcbsp2_port>, <&mcbsp3_port>; }; - pwm8: dmtimer-pwm-8 { + pwm8: pwm-8 { pinctrl-names = "default"; pinctrl-0 = <&vibrator_direction_pin>; @@ -143,7 +143,7 @@ ti,clock-source = <0x01>; }; - pwm9: dmtimer-pwm-9 { + pwm9: pwm-9 { pinctrl-names = "default"; pinctrl-0 = <&vibrator_enable_pin>; diff --git a/arch/arm/boot/dts/nuvoton-npcm730-gbs.dts b/arch/arm/boot/dts/nuvoton-npcm730-gbs.dts index d10669fcd527..9e9eba8bad5e 100644 --- a/arch/arm/boot/dts/nuvoton-npcm730-gbs.dts +++ b/arch/arm/boot/dts/nuvoton-npcm730-gbs.dts @@ -366,7 +366,7 @@ spi-max-frequency = <20000000>; spi-rx-bus-width = <2>; label = "bmc"; - partitions@80000000 { + partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/nuvoton-npcm730-gsj.dts b/arch/arm/boot/dts/nuvoton-npcm730-gsj.dts index 491606c4f044..2a394cc15284 100644 --- a/arch/arm/boot/dts/nuvoton-npcm730-gsj.dts +++ b/arch/arm/boot/dts/nuvoton-npcm730-gsj.dts @@ -142,7 +142,7 @@ reg = <0>; spi-rx-bus-width = <2>; - partitions@80000000 { + partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/nuvoton-npcm730-kudo.dts b/arch/arm/boot/dts/nuvoton-npcm730-kudo.dts index a0c2d7652625..f7b38bee039b 100644 --- a/arch/arm/boot/dts/nuvoton-npcm730-kudo.dts +++ b/arch/arm/boot/dts/nuvoton-npcm730-kudo.dts @@ -388,7 +388,7 @@ spi-max-frequency = <5000000>; spi-rx-bus-width = <2>; label = "bmc"; - partitions@80000000 { + partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; @@ -422,7 +422,7 @@ reg = <1>; spi-max-frequency = <5000000>; spi-rx-bus-width = <2>; - partitions@88000000 { + partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; @@ -447,7 +447,7 @@ reg = <0>; spi-max-frequency = <5000000>; spi-rx-bus-width = <2>; - partitions@A0000000 { + partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/nuvoton-npcm750-evb.dts b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts index 3dad32834e5e..f53d45fa1de8 100644 --- a/arch/arm/boot/dts/nuvoton-npcm750-evb.dts +++ b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts @@ -74,7 +74,7 @@ spi-rx-bus-width = <2>; reg = <0>; spi-max-frequency = <5000000>; - partitions@80000000 { + partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; @@ -135,7 +135,7 @@ spi-rx-bus-width = <2>; reg = <0>; spi-max-frequency = <5000000>; - partitions@A0000000 { + partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/nuvoton-npcm750-runbmc-olympus.dts b/arch/arm/boot/dts/nuvoton-npcm750-runbmc-olympus.dts index 132e702281fc..87359ab05db3 100644 --- a/arch/arm/boot/dts/nuvoton-npcm750-runbmc-olympus.dts +++ b/arch/arm/boot/dts/nuvoton-npcm750-runbmc-olympus.dts @@ -107,7 +107,7 @@ reg = <0>; spi-rx-bus-width = <2>; - partitions@80000000 { + partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; @@ -146,7 +146,7 @@ reg = <1>; npcm,fiu-rx-bus-width = <2>; - partitions@88000000 { + partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; @@ -173,7 +173,7 @@ reg = <0>; spi-rx-bus-width = <2>; - partitions@A0000000 { + partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/nuvoton-wpcm450-supermicro-x9sci-ln4f.dts b/arch/arm/boot/dts/nuvoton-wpcm450-supermicro-x9sci-ln4f.dts index 3ee61251a16d..b78c116cbc18 100644 --- a/arch/arm/boot/dts/nuvoton-wpcm450-supermicro-x9sci-ln4f.dts +++ b/arch/arm/boot/dts/nuvoton-wpcm450-supermicro-x9sci-ln4f.dts @@ -15,6 +15,11 @@ model = "Supermicro X9SCi-LN4F BMC"; compatible = "supermicro,x9sci-ln4f-bmc", "nuvoton,wpcm450"; + aliases { + serial0 = &serial0; + serial1 = &serial1; + }; + chosen { stdout-path = "serial0:115200n8"; }; @@ -53,6 +58,33 @@ }; }; +&fiu { + status = "okay"; + + flash@0 { + reg = <0>; + compatible = "jedec,spi-nor"; + }; +}; + +&gpio0 { + gpio-line-names = + /* 0 */ "", "host-reset-control-n", "", "", "", "", "", "", + /* 8 */ "", "", "", "", "power-chassis-control-n", "", "uid-button", ""; +}; + +&gpio1 { + gpio-line-names = + /* 0 */ "", "", "", "", "led-heartbeat", "", "", "led-uid", + /* 8 */ "", "", "", "", "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + /* 0 */ "", "", "", "", "", "", "", "", + /* 8 */ "", "", "", "", "", "", "", "power-chassis-good"; +}; + &pinctrl { key_pins: mux-keys { groups = "gspi", "sspi"; @@ -77,7 +109,3 @@ /* "Serial over LAN" port. Connected to ttyS2 of the host system. */ status = "okay"; }; - -&watchdog0 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/nuvoton-wpcm450.dtsi b/arch/arm/boot/dts/nuvoton-wpcm450.dtsi index 93595850a4c3..b637241316bb 100644 --- a/arch/arm/boot/dts/nuvoton-wpcm450.dtsi +++ b/arch/arm/boot/dts/nuvoton-wpcm450.dtsi @@ -37,6 +37,14 @@ #clock-cells = <0>; }; + refclk: clock-48mhz { + /* 48 MHz reference oscillator */ + compatible = "fixed-clock"; + clock-output-names = "ref"; + clock-frequency = <48000000>; + #clock-cells = <0>; + }; + soc { compatible = "simple-bus"; #address-cells = <1>; @@ -49,6 +57,15 @@ reg = <0xb0000000 0x200>; }; + clk: clock-controller@b0000200 { + compatible = "nuvoton,wpcm450-clk"; + reg = <0xb0000200 0x100>; + clocks = <&refclk>; + clock-names = "ref"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + serial0: serial@b8000000 { compatible = "nuvoton,wpcm450-uart"; reg = <0xb8000000 0x20>; @@ -81,7 +98,6 @@ interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; reg = <0xb800101c 0x4>; clocks = <&clk24m>; - status = "disabled"; }; aic: interrupt-controller@b8002000 { @@ -456,5 +472,21 @@ function = "hg7"; }; }; + + fiu: spi-controller@c8000000 { + compatible = "nuvoton,wpcm450-fiu"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xc8000000 0x1000>, <0xc0000000 0x4000000>; + reg-names = "control", "memory"; + clocks = <&clk 0>; + status = "disabled"; + }; + + shm: syscon@c8001000 { + compatible = "nuvoton,wpcm450-shm", "syscon"; + reg = <0xc8001000 0x1000>; + reg-io-width = <1>; + }; }; }; diff --git a/arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi b/arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi index ce6c235f68ec..3046ec572632 100644 --- a/arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi +++ b/arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi @@ -8,9 +8,9 @@ / { vddvario: regulator-vddvario { - compatible = "regulator-fixed"; - regulator-name = "vddvario"; - regulator-always-on; + compatible = "regulator-fixed"; + regulator-name = "vddvario"; + regulator-always-on; }; vdd33a: regulator-vdd33a { diff --git a/arch/arm/boot/dts/omap-gpmc-smsc9221.dtsi b/arch/arm/boot/dts/omap-gpmc-smsc9221.dtsi index e7534fe9c53c..bc8961f3690f 100644 --- a/arch/arm/boot/dts/omap-gpmc-smsc9221.dtsi +++ b/arch/arm/boot/dts/omap-gpmc-smsc9221.dtsi @@ -12,9 +12,9 @@ / { vddvario: regulator-vddvario { - compatible = "regulator-fixed"; - regulator-name = "vddvario"; - regulator-always-on; + compatible = "regulator-fixed"; + regulator-name = "vddvario"; + regulator-always-on; }; vdd33a: regulator-vdd33a { diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts index 0548b391334f..47ff1ffddfc5 100644 --- a/arch/arm/boot/dts/omap3-beagle.dts +++ b/arch/arm/boot/dts/omap3-beagle.dts @@ -28,18 +28,18 @@ leds { compatible = "gpio-leds"; - pmu_stat { + led-pmu-stat { label = "beagleboard::pmu_stat"; gpios = <&twl_gpio 19 GPIO_ACTIVE_HIGH>; /* LEDB */ }; - heartbeat { + led-heartbeat { label = "beagleboard::usr0"; gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* 150 -> D6 LED */ linux,default-trigger = "heartbeat"; }; - mmc { + led-mmc { label = "beagleboard::usr1"; gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; /* 149 -> D7 LED */ linux,default-trigger = "mmc0"; diff --git a/arch/arm/boot/dts/omap3-cm-t3517.dts b/arch/arm/boot/dts/omap3-cm-t3517.dts index 3b8349094baa..f25c0a84a190 100644 --- a/arch/arm/boot/dts/omap3-cm-t3517.dts +++ b/arch/arm/boot/dts/omap3-cm-t3517.dts @@ -11,12 +11,12 @@ model = "CompuLab CM-T3517"; compatible = "compulab,omap3-cm-t3517", "ti,am3517", "ti,omap3"; - vmmc: regulator-vmmc { - compatible = "regulator-fixed"; - regulator-name = "vmmc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; + vmmc: regulator-vmmc { + compatible = "regulator-fixed"; + regulator-name = "vmmc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; wl12xx_vmmc2: wl12xx_vmmc2 { compatible = "regulator-fixed"; diff --git a/arch/arm/boot/dts/omap3-devkit8000-common.dtsi b/arch/arm/boot/dts/omap3-devkit8000-common.dtsi index 54cd37336be7..38aa1febc33f 100644 --- a/arch/arm/boot/dts/omap3-devkit8000-common.dtsi +++ b/arch/arm/boot/dts/omap3-devkit8000-common.dtsi @@ -15,28 +15,28 @@ leds { compatible = "gpio-leds"; - heartbeat { + led-heartbeat { label = "devkit8000::led1"; gpios = <&gpio6 26 GPIO_ACTIVE_HIGH>; /* 186 -> LED1 */ default-state = "on"; linux,default-trigger = "heartbeat"; }; - mmc { + led-mmc { label = "devkit8000::led2"; gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; /* 163 -> LED2 */ default-state = "on"; linux,default-trigger = "none"; }; - usr { + led-usr { label = "devkit8000::led3"; gpios = <&gpio6 4 GPIO_ACTIVE_HIGH>; /* 164 -> LED3 */ default-state = "on"; linux,default-trigger = "usr"; }; - pmu_stat { + led-pmu-stat { label = "devkit8000::pmu_stat"; gpios = <&twl_gpio 19 GPIO_ACTIVE_HIGH>; /* LEDB */ }; diff --git a/arch/arm/boot/dts/omap3-echo.dts b/arch/arm/boot/dts/omap3-echo.dts index 8f02ff5e7da6..06d2377d28ad 100644 --- a/arch/arm/boot/dts/omap3-echo.dts +++ b/arch/arm/boot/dts/omap3-echo.dts @@ -146,7 +146,7 @@ label = "q1"; reg = <0x32>; clock-mode = /bits/ 8 <0>; /* LP55XX_CLOCK_AUTO */ - enable-gpio = <&gpio4 13 GPIO_ACTIVE_HIGH>; /* GPIO_109 */ + enable-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; /* GPIO_109 */ multi-led@0 { #address-cells = <1>; diff --git a/arch/arm/boot/dts/omap3-gta04.dtsi b/arch/arm/boot/dts/omap3-gta04.dtsi index 28a6a9345be5..87e0ab1bbe95 100644 --- a/arch/arm/boot/dts/omap3-gta04.dtsi +++ b/arch/arm/boot/dts/omap3-gta04.dtsi @@ -147,7 +147,7 @@ pinctrl-0 = <&backlight_pins>; }; - pwm11: dmtimer-pwm { + pwm11: pwm-11 { compatible = "ti,omap-dmtimer-pwm"; ti,timers = <&timer11>; #pwm-cells = <3>; @@ -332,7 +332,7 @@ OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ >; - }; + }; gps_pins: pinmux_gps_pins { pinctrl-single,pins = < @@ -853,8 +853,8 @@ }; &hdqw1w { - pinctrl-names = "default"; - pinctrl-0 = <&hdq_pins>; + pinctrl-names = "default"; + pinctrl-0 = <&hdq_pins>; }; /* image signal processor within OMAP3 SoC */ diff --git a/arch/arm/boot/dts/omap3-ldp.dts b/arch/arm/boot/dts/omap3-ldp.dts index 36fc8805e0c1..85f33bbb566f 100644 --- a/arch/arm/boot/dts/omap3-ldp.dts +++ b/arch/arm/boot/dts/omap3-ldp.dts @@ -301,5 +301,5 @@ &vaux1 { /* Needed for ads7846 */ - regulator-name = "vcc"; + regulator-name = "vcc"; }; diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts index dd7971556449..6ba2e8f81973 100644 --- a/arch/arm/boot/dts/omap3-n900.dts +++ b/arch/arm/boot/dts/omap3-n900.dts @@ -49,7 +49,7 @@ leds { compatible = "gpio-leds"; - heartbeat { + led-heartbeat { label = "debug::sleep"; gpios = <&gpio6 2 GPIO_ACTIVE_HIGH>; /* 162 */ linux,default-trigger = "default-on"; @@ -156,7 +156,7 @@ io-channel-names = "temp", "bsi", "vbat"; }; - pwm9: dmtimer-pwm { + pwm9: pwm-9 { compatible = "ti,omap-dmtimer-pwm"; #pwm-cells = <3>; ti,timers = <&timer9>; @@ -236,27 +236,27 @@ pinctrl-single,pins = < /* address lines */ - OMAP3_CORE1_IOPAD(0x207a, PIN_OUTPUT | MUX_MODE0) /* gpmc_a1.gpmc_a1 */ - OMAP3_CORE1_IOPAD(0x207c, PIN_OUTPUT | MUX_MODE0) /* gpmc_a2.gpmc_a2 */ - OMAP3_CORE1_IOPAD(0x207e, PIN_OUTPUT | MUX_MODE0) /* gpmc_a3.gpmc_a3 */ + OMAP3_CORE1_IOPAD(0x207a, PIN_OUTPUT | MUX_MODE0) /* gpmc_a1.gpmc_a1 */ + OMAP3_CORE1_IOPAD(0x207c, PIN_OUTPUT | MUX_MODE0) /* gpmc_a2.gpmc_a2 */ + OMAP3_CORE1_IOPAD(0x207e, PIN_OUTPUT | MUX_MODE0) /* gpmc_a3.gpmc_a3 */ /* data lines, gpmc_d0..d7 not muxable according to TRM */ - OMAP3_CORE1_IOPAD(0x209e, PIN_INPUT | MUX_MODE0) /* gpmc_d8.gpmc_d8 */ - OMAP3_CORE1_IOPAD(0x20a0, PIN_INPUT | MUX_MODE0) /* gpmc_d9.gpmc_d9 */ - OMAP3_CORE1_IOPAD(0x20a2, PIN_INPUT | MUX_MODE0) /* gpmc_d10.gpmc_d10 */ - OMAP3_CORE1_IOPAD(0x20a4, PIN_INPUT | MUX_MODE0) /* gpmc_d11.gpmc_d11 */ - OMAP3_CORE1_IOPAD(0x20a6, PIN_INPUT | MUX_MODE0) /* gpmc_d12.gpmc_d12 */ - OMAP3_CORE1_IOPAD(0x20a8, PIN_INPUT | MUX_MODE0) /* gpmc_d13.gpmc_d13 */ - OMAP3_CORE1_IOPAD(0x20aa, PIN_INPUT | MUX_MODE0) /* gpmc_d14.gpmc_d14 */ - OMAP3_CORE1_IOPAD(0x20ac, PIN_INPUT | MUX_MODE0) /* gpmc_d15.gpmc_d15 */ + OMAP3_CORE1_IOPAD(0x209e, PIN_INPUT | MUX_MODE0) /* gpmc_d8.gpmc_d8 */ + OMAP3_CORE1_IOPAD(0x20a0, PIN_INPUT | MUX_MODE0) /* gpmc_d9.gpmc_d9 */ + OMAP3_CORE1_IOPAD(0x20a2, PIN_INPUT | MUX_MODE0) /* gpmc_d10.gpmc_d10 */ + OMAP3_CORE1_IOPAD(0x20a4, PIN_INPUT | MUX_MODE0) /* gpmc_d11.gpmc_d11 */ + OMAP3_CORE1_IOPAD(0x20a6, PIN_INPUT | MUX_MODE0) /* gpmc_d12.gpmc_d12 */ + OMAP3_CORE1_IOPAD(0x20a8, PIN_INPUT | MUX_MODE0) /* gpmc_d13.gpmc_d13 */ + OMAP3_CORE1_IOPAD(0x20aa, PIN_INPUT | MUX_MODE0) /* gpmc_d14.gpmc_d14 */ + OMAP3_CORE1_IOPAD(0x20ac, PIN_INPUT | MUX_MODE0) /* gpmc_d15.gpmc_d15 */ /* * gpmc_ncs0, gpmc_nadv_ale, gpmc_noe, gpmc_nwe, gpmc_wait0 not muxable * according to TRM. OneNAND seems to require PIN_INPUT on clock. */ - OMAP3_CORE1_IOPAD(0x20b0, PIN_OUTPUT | MUX_MODE0) /* gpmc_ncs1.gpmc_ncs1 */ - OMAP3_CORE1_IOPAD(0x20be, PIN_INPUT | MUX_MODE0) /* gpmc_clk.gpmc_clk */ - >; + OMAP3_CORE1_IOPAD(0x20b0, PIN_OUTPUT | MUX_MODE0) /* gpmc_ncs1.gpmc_ncs1 */ + OMAP3_CORE1_IOPAD(0x20be, PIN_INPUT | MUX_MODE0) /* gpmc_clk.gpmc_clk */ + >; }; i2c1_pins: pinmux_i2c1_pins { @@ -738,12 +738,12 @@ si4713: si4713@63 { compatible = "silabs,si4713"; - reg = <0x63>; + reg = <0x63>; - interrupts-extended = <&gpio2 21 IRQ_TYPE_EDGE_FALLING>; /* 53 */ - reset-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; /* 163 */ - vio-supply = <&vio>; - vdd-supply = <&vaux1>; + interrupts-extended = <&gpio2 21 IRQ_TYPE_EDGE_FALLING>; /* 53 */ + reset-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; /* 163 */ + vio-supply = <&vio>; + vdd-supply = <&vaux1>; }; bq24150a: bq24150a@6b { diff --git a/arch/arm/boot/dts/omap3-overo-alto35-common.dtsi b/arch/arm/boot/dts/omap3-overo-alto35-common.dtsi index bb932913c9e3..a6dbbba799b2 100644 --- a/arch/arm/boot/dts/omap3-overo-alto35-common.dtsi +++ b/arch/arm/boot/dts/omap3-overo-alto35-common.dtsi @@ -17,19 +17,19 @@ compatible = "gpio-leds"; pinctrl-names = "default"; pinctrl-0 = <&led_pins>; - gpio148 { + led-gpio148 { label = "overo:red:gpio148"; gpios = <&gpio5 20 GPIO_ACTIVE_HIGH>; /* gpio 148 */ }; - gpio150 { + led-gpio150 { label = "overo:yellow:gpio150"; gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* gpio 150 */ }; - gpio151 { + led-gpio151 { label = "overo:blue:gpio151"; gpios = <&gpio5 23 GPIO_ACTIVE_HIGH>; /* gpio 151 */ }; - gpio170 { + led-gpio170 { label = "overo:green:gpio170"; gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>; /* gpio 170 */ }; diff --git a/arch/arm/boot/dts/omap3-overo-chestnut43-common.dtsi b/arch/arm/boot/dts/omap3-overo-chestnut43-common.dtsi index 2d2c61d7aa86..0d0e62c00916 100644 --- a/arch/arm/boot/dts/omap3-overo-chestnut43-common.dtsi +++ b/arch/arm/boot/dts/omap3-overo-chestnut43-common.dtsi @@ -17,12 +17,12 @@ compatible = "gpio-leds"; pinctrl-names = "default"; pinctrl-0 = <&led_pins>; - heartbeat { + led-heartbeat { label = "overo:red:gpio21"; gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; /* gpio_21 */ linux,default-trigger = "heartbeat"; }; - gpio22 { + led-gpio22 { label = "overo:blue:gpio22"; gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; /* gpio_22 */ }; diff --git a/arch/arm/boot/dts/omap3-overo-gallop43-common.dtsi b/arch/arm/boot/dts/omap3-overo-gallop43-common.dtsi index 155aec121400..5f6721326f86 100644 --- a/arch/arm/boot/dts/omap3-overo-gallop43-common.dtsi +++ b/arch/arm/boot/dts/omap3-overo-gallop43-common.dtsi @@ -17,12 +17,12 @@ compatible = "gpio-leds"; pinctrl-names = "default"; pinctrl-0 = <&led_pins>; - heartbeat { + led-heartbeat { label = "overo:red:gpio21"; gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; /* gpio_21 */ linux,default-trigger = "heartbeat"; }; - gpio22 { + led-gpio22 { label = "overo:blue:gpio22"; gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; /* gpio_22 */ }; diff --git a/arch/arm/boot/dts/omap3-overo-palo35-common.dtsi b/arch/arm/boot/dts/omap3-overo-palo35-common.dtsi index 82a04466747a..4b66f622ac13 100644 --- a/arch/arm/boot/dts/omap3-overo-palo35-common.dtsi +++ b/arch/arm/boot/dts/omap3-overo-palo35-common.dtsi @@ -17,12 +17,12 @@ compatible = "gpio-leds"; pinctrl-names = "default"; pinctrl-0 = <&led_pins>; - heartbeat { + led-heartbeat { label = "overo:red:gpio21"; gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; /* gpio_21 */ linux,default-trigger = "heartbeat"; }; - gpio22 { + led-gpio22 { label = "overo:blue:gpio22"; gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; /* gpio_22 */ }; diff --git a/arch/arm/boot/dts/omap3-overo-palo43-common.dtsi b/arch/arm/boot/dts/omap3-overo-palo43-common.dtsi index 453a55324fa1..a8f163a899f0 100644 --- a/arch/arm/boot/dts/omap3-overo-palo43-common.dtsi +++ b/arch/arm/boot/dts/omap3-overo-palo43-common.dtsi @@ -17,12 +17,12 @@ compatible = "gpio-leds"; pinctrl-names = "default"; pinctrl-0 = <&led_pins>; - heartbeat { + led-heartbeat { label = "overo:red:gpio21"; gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; /* gpio_21 */ linux,default-trigger = "heartbeat"; }; - gpio22 { + led-gpio22 { label = "overo:blue:gpio22"; gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; /* gpio_22 */ }; diff --git a/arch/arm/boot/dts/omap3-overo-summit-common.dtsi b/arch/arm/boot/dts/omap3-overo-summit-common.dtsi index df7450f17ffd..ec03ca17e98b 100644 --- a/arch/arm/boot/dts/omap3-overo-summit-common.dtsi +++ b/arch/arm/boot/dts/omap3-overo-summit-common.dtsi @@ -15,7 +15,7 @@ compatible = "gpio-leds"; pinctrl-names = "default"; pinctrl-0 = <&led_pins>; - heartbeat { + led-heartbeat { label = "overo:red:gpio21"; gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; /* gpio_21 */ linux,default-trigger = "heartbeat"; diff --git a/arch/arm/boot/dts/omap3-overo-tobi-common.dtsi b/arch/arm/boot/dts/omap3-overo-tobi-common.dtsi index 9bf4b88a4b50..5432e4e16ab5 100644 --- a/arch/arm/boot/dts/omap3-overo-tobi-common.dtsi +++ b/arch/arm/boot/dts/omap3-overo-tobi-common.dtsi @@ -13,7 +13,7 @@ / { leds { compatible = "gpio-leds"; - heartbeat { + led-heartbeat { label = "overo:red:gpio21"; gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; linux,default-trigger = "heartbeat"; diff --git a/arch/arm/boot/dts/omap3-zoom3.dts b/arch/arm/boot/dts/omap3-zoom3.dts index 0482676d1830..ce58b1f208e8 100644 --- a/arch/arm/boot/dts/omap3-zoom3.dts +++ b/arch/arm/boot/dts/omap3-zoom3.dts @@ -23,9 +23,9 @@ }; vddvario: regulator-vddvario { - compatible = "regulator-fixed"; - regulator-name = "vddvario"; - regulator-always-on; + compatible = "regulator-fixed"; + regulator-name = "vddvario"; + regulator-always-on; }; vdd33a: regulator-vdd33a { @@ -84,28 +84,28 @@ uart1_pins: pinmux_uart1_pins { pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT | MUX_MODE0) /* uart1_cts.uart1_cts */ - OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE0) /* uart1_rts.uart1_rts */ - OMAP3_CORE1_IOPAD(0x2182, WAKEUP_EN | PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */ - OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_tx */ + OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT | MUX_MODE0) /* uart1_cts.uart1_cts */ + OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE0) /* uart1_rts.uart1_rts */ + OMAP3_CORE1_IOPAD(0x2182, WAKEUP_EN | PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */ + OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_tx */ >; }; uart2_pins: pinmux_uart2_pins { pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts.uart2_cts */ - OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts.uart2_rts */ - OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ - OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ + OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts.uart2_cts */ + OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts.uart2_rts */ + OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ + OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ >; }; uart3_pins: pinmux_uart3_pins { pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x219a, PIN_INPUT_PULLDOWN | MUX_MODE0) /* uart3_cts_rctx.uart3_cts_rctx */ - OMAP3_CORE1_IOPAD(0x219c, PIN_OUTPUT | MUX_MODE0) /* uart3_rts_sd.uart3_rts_sd */ - OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ - OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ + OMAP3_CORE1_IOPAD(0x219a, PIN_INPUT_PULLDOWN | MUX_MODE0) /* uart3_cts_rctx.uart3_cts_rctx */ + OMAP3_CORE1_IOPAD(0x219c, PIN_OUTPUT | MUX_MODE0) /* uart3_rts_sd.uart3_rts_sd */ + OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ + OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ >; }; @@ -205,22 +205,22 @@ }; &uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; }; &uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; }; &uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; }; &uart4 { - status = "disabled"; + status = "disabled"; }; &usb_otg_hs { diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi index 825075ff0e34..92cd4c99dae7 100644 --- a/arch/arm/boot/dts/omap3.dtsi +++ b/arch/arm/boot/dts/omap3.dtsi @@ -893,15 +893,37 @@ #gpio-cells = <2>; }; - usb_otg_hs: usb_otg_hs@480ab000 { - compatible = "ti,omap3-musb"; - reg = <0x480ab000 0x1000>; - interrupts = <92>, <93>; - interrupt-names = "mc", "dma"; - ti,hwmods = "usb_otg_hs"; - multipoint = <1>; - num-eps = <16>; - ram-bits = <12>; + usb_otg_target: target-module@480ab000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x480ab400 0x4>, + <0x480ab404 0x4>, + <0x480ab408 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-midle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>; + ti,syss-mask = <1>; + /* Clock defined in the SoC specific dtsi file */ + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x480ab000 0x1000>; + + usb_otg_hs: usb@0 { + compatible = "ti,omap3-musb"; + reg = <0 0x1000>; + interrupts = <92>, <93>; + interrupt-names = "mc", "dma"; + multipoint = <1>; + num-eps = <16>; + ram-bits = <12>; + }; }; dss: dss@48050000 { diff --git a/arch/arm/boot/dts/omap34xx.dtsi b/arch/arm/boot/dts/omap34xx.dtsi index 2eb73ae7ef3e..9dbf62797f0f 100644 --- a/arch/arm/boot/dts/omap34xx.dtsi +++ b/arch/arm/boot/dts/omap34xx.dtsi @@ -189,6 +189,10 @@ "ssi_ick"; }; +&usb_otg_target { + clocks = <&hsotgusb_ick_3430es2>; +}; + /include/ "omap34xx-omap36xx-clocks.dtsi" /include/ "omap36xx-omap3430es2plus-clocks.dtsi" /include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi" diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi index 32ac7924a130..fff9c3d34193 100644 --- a/arch/arm/boot/dts/omap36xx.dtsi +++ b/arch/arm/boot/dts/omap36xx.dtsi @@ -240,6 +240,10 @@ "ssi_ick"; }; +&usb_otg_target { + clocks = <&hsotgusb_ick_3430es2>; +}; + /include/ "omap34xx-omap36xx-clocks.dtsi" /include/ "omap36xx-omap3430es2plus-clocks.dtsi" /include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi" diff --git a/arch/arm/boot/dts/omap4-cpu-thermal.dtsi b/arch/arm/boot/dts/omap4-cpu-thermal.dtsi index 4d7eeb133dad..801b4f10350c 100644 --- a/arch/arm/boot/dts/omap4-cpu-thermal.dtsi +++ b/arch/arm/boot/dts/omap4-cpu-thermal.dtsi @@ -13,20 +13,20 @@ cpu_thermal: cpu_thermal { polling-delay = <1000>; /* milliseconds */ /* sensor ID */ - thermal-sensors = <&bandgap 0>; + thermal-sensors = <&bandgap 0>; cpu_trips: trips { - cpu_alert0: cpu_alert { - temperature = <100000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_crit: cpu_crit { - temperature = <125000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; + cpu_alert0: cpu_alert { + temperature = <100000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + cpu_crit: cpu_crit { + temperature = <125000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; cpu_cooling_maps: cooling-maps { map0 { diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi index 518652a599bd..0269424350aa 100644 --- a/arch/arm/boot/dts/omap4-panda-common.dtsi +++ b/arch/arm/boot/dts/omap4-panda-common.dtsi @@ -49,13 +49,13 @@ &led_wkgpio_pins >; - heartbeat { + led-heartbeat { label = "pandaboard::status1"; gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; - mmc { + led-mmc { label = "pandaboard::status2"; gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; linux,default-trigger = "mmc0"; diff --git a/arch/arm/boot/dts/omap4-panda-es.dts b/arch/arm/boot/dts/omap4-panda-es.dts index 7c6886cd738f..7631029e4d7a 100644 --- a/arch/arm/boot/dts/omap4-panda-es.dts +++ b/arch/arm/boot/dts/omap4-panda-es.dts @@ -79,10 +79,10 @@ &led_wkgpio_pins >; - heartbeat { + led-heartbeat { gpios = <&gpio4 14 GPIO_ACTIVE_HIGH>; }; - mmc { + led-mmc { gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; }; }; diff --git a/arch/arm/boot/dts/omap5-cm-t54.dts b/arch/arm/boot/dts/omap5-cm-t54.dts index ca759b7b8a58..2d87b9fc230e 100644 --- a/arch/arm/boot/dts/omap5-cm-t54.dts +++ b/arch/arm/boot/dts/omap5-cm-t54.dts @@ -84,36 +84,36 @@ }; lcd0: display { - compatible = "startek,startek-kd050c", "panel-dpi"; - label = "lcd"; - - pinctrl-names = "default"; - pinctrl-0 = <&lcd_pins>; - - enable-gpios = <&gpio8 3 GPIO_ACTIVE_HIGH>; - - panel-timing { - clock-frequency = <33000000>; - hactive = <800>; - vactive = <480>; - hfront-porch = <40>; - hback-porch = <40>; - hsync-len = <43>; - vback-porch = <29>; - vfront-porch = <13>; - vsync-len = <3>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - - port { - lcd_in: endpoint { - remote-endpoint = <&dpi_lcd_out>; - }; - }; - }; + compatible = "startek,startek-kd050c", "panel-dpi"; + label = "lcd"; + + pinctrl-names = "default"; + pinctrl-0 = <&lcd_pins>; + + enable-gpios = <&gpio8 3 GPIO_ACTIVE_HIGH>; + + panel-timing { + clock-frequency = <33000000>; + hactive = <800>; + vactive = <480>; + hfront-porch = <40>; + hback-porch = <40>; + hsync-len = <43>; + vback-porch = <29>; + vfront-porch = <13>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + + port { + lcd_in: endpoint { + remote-endpoint = <&dpi_lcd_out>; + }; + }; + }; hdmi0: connector0 { compatible = "hdmi-connector"; @@ -644,8 +644,8 @@ }; &usb3 { - extcon = <&extcon_usb3>; - vbus-supply = <&smps10_out1_reg>; + extcon = <&extcon_usb3>; + vbus-supply = <&smps10_out1_reg>; }; &cpu0 { diff --git a/arch/arm/boot/dts/pxa168.dtsi b/arch/arm/boot/dts/pxa168.dtsi index 4fe7735c7c58..16212b912b94 100644 --- a/arch/arm/boot/dts/pxa168.dtsi +++ b/arch/arm/boot/dts/pxa168.dtsi @@ -53,6 +53,8 @@ compatible = "mrvl,mmp-timer"; reg = <0xd4014000 0x100>; interrupts = <13>; + clocks = <&soc_clocks PXA168_CLK_TIMER>; + resets = <&soc_clocks PXA168_CLK_TIMER>; }; uart1: serial@d4017000 { diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi index 758a1bf02fae..73be346001cb 100644 --- a/arch/arm/boot/dts/r8a7742.dtsi +++ b/arch/arm/boot/dts/r8a7742.dtsi @@ -1298,7 +1298,7 @@ dma-names = "rx", "tx", "rxu", "txu"; }; ssi1: ssi-1 { - interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>; dma-names = "rx", "tx", "rxu", "txu"; diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index db171e3c62f2..111a6d23159e 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -1252,7 +1252,7 @@ dma-names = "rx", "tx", "rxu", "txu"; }; ssi1: ssi-1 { - interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>; dma-names = "rx", "tx", "rxu", "txu"; diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index d8f91d9f42ae..777b672b59cc 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -1365,7 +1365,7 @@ dma-names = "rx", "tx", "rxu", "txu"; }; ssi1: ssi-1 { - interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>; dma-names = "rx", "tx", "rxu", "txu"; diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi index 9ebe7bfaf0ed..3e0be1b58931 100644 --- a/arch/arm/boot/dts/r8a7793.dtsi +++ b/arch/arm/boot/dts/r8a7793.dtsi @@ -1111,7 +1111,7 @@ dma-names = "rx", "tx", "rxu", "txu"; }; ssi1: ssi-1 { - interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>; dma-names = "rx", "tx", "rxu", "txu"; diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi index 563024c9a4ae..41e19c0986ce 100644 --- a/arch/arm/boot/dts/r9a06g032.dtsi +++ b/arch/arm/boot/dts/r9a06g032.dtsi @@ -199,7 +199,7 @@ reg-io-width = <4>; clocks = <&sysctrl R9A06G032_CLK_UART3>, <&sysctrl R9A06G032_HCLK_UART3>; clock-names = "baudclk", "apb_pclk"; - dmas = <&dmamux 0 0 0 0 0 1>, <&dmamux 1 0 0 0 1 1>; + dmas = <&dmamux 0 0 0 0 0 1>, <&dmamux 1 0 0 0 1 1>; dma-names = "rx", "tx"; status = "disabled"; }; @@ -212,7 +212,7 @@ reg-io-width = <4>; clocks = <&sysctrl R9A06G032_CLK_UART4>, <&sysctrl R9A06G032_HCLK_UART4>; clock-names = "baudclk", "apb_pclk"; - dmas = <&dmamux 2 0 0 0 2 1>, <&dmamux 3 0 0 0 3 1>; + dmas = <&dmamux 2 0 0 0 2 1>, <&dmamux 3 0 0 0 3 1>; dma-names = "rx", "tx"; status = "disabled"; }; @@ -225,7 +225,7 @@ reg-io-width = <4>; clocks = <&sysctrl R9A06G032_CLK_UART5>, <&sysctrl R9A06G032_HCLK_UART5>; clock-names = "baudclk", "apb_pclk"; - dmas = <&dmamux 4 0 0 0 4 1>, <&dmamux 5 0 0 0 5 1>; + dmas = <&dmamux 4 0 0 0 4 1>, <&dmamux 5 0 0 0 5 1>; dma-names = "rx", "tx"; status = "disabled"; }; @@ -238,7 +238,7 @@ reg-io-width = <4>; clocks = <&sysctrl R9A06G032_CLK_UART6>, <&sysctrl R9A06G032_HCLK_UART6>; clock-names = "baudclk", "apb_pclk"; - dmas = <&dmamux 6 0 0 0 6 1>, <&dmamux 7 0 0 0 7 1>; + dmas = <&dmamux 6 0 0 0 6 1>, <&dmamux 7 0 0 0 7 1>; dma-names = "rx", "tx"; status = "disabled"; }; @@ -251,7 +251,7 @@ reg-io-width = <4>; clocks = <&sysctrl R9A06G032_CLK_UART7>, <&sysctrl R9A06G032_HCLK_UART7>; clock-names = "baudclk", "apb_pclk"; - dmas = <&dmamux 4 0 0 0 20 1>, <&dmamux 5 0 0 0 21 1>; + dmas = <&dmamux 4 0 0 0 20 1>, <&dmamux 5 0 0 0 21 1>; dma-names = "rx", "tx"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/sama7g5-pinfunc.h b/arch/arm/boot/dts/sama7g5-pinfunc.h index 4eb30445d205..6875cf46937e 100644 --- a/arch/arm/boot/dts/sama7g5-pinfunc.h +++ b/arch/arm/boot/dts/sama7g5-pinfunc.h @@ -673,7 +673,7 @@ #define PIN_PD8__GPIO PINMUX_PIN(PIN_PD8, 0, 0) #define PIN_PD8__SDMMC2_DAT3 PINMUX_PIN(PIN_PD8, 1, 1) #define PIN_PD8__I2SMCC0_DIN0 PINMUX_PIN(PIN_PD8, 3, 1) -#define PIN_PD8__A11_NANDCLE PINMUX_PIN(PIN_PD8, 4, 2) +#define PIN_PD8__A22_NANDCLE PINMUX_PIN(PIN_PD8, 4, 2) #define PIN_PD8__TIOA2 PINMUX_PIN(PIN_PD8, 5, 2) #define PIN_PD8__FLEXCOM11_IO0 PINMUX_PIN(PIN_PD8, 6, 5) #define PIN_PD9 105 diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi index 7bd8ae8e8d38..ab131762ecb5 100644 --- a/arch/arm/boot/dts/sama7g5.dtsi +++ b/arch/arm/boot/dts/sama7g5.dtsi @@ -9,12 +9,15 @@ * */ +#include <dt-bindings/iio/adc/at91-sama5d2_adc.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/at91.h> #include <dt-bindings/dma/at91.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/mfd/at91-usart.h> +#include <dt-bindings/nvmem/microchip,sama7g5-otpc.h> +#include <dt-bindings/thermal/thermal.h> / { model = "Microchip SAMA7G5 family SoC"; @@ -34,6 +37,7 @@ clocks = <&pmc PMC_TYPE_CORE PMC_CPUPLL>; clock-names = "cpu"; operating-points-v2 = <&cpu_opp_table>; + #cooling-cells = <2>; /* min followed by max */ }; }; @@ -72,6 +76,46 @@ }; }; + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&thermal_sensor>; + + trips { + cpu_normal: cpu-alert0 { + temperature = <90000>; + hysteresis = <0>; + type = "passive"; + }; + + cpu_hot: cpu-alert1 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + cpu_critical: cpu-critical { + temperature = <100000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_normal>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + + map1 { + trip = <&cpu_hot>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + clocks { slow_xtal: slow_xtal { compatible = "fixed-clock"; @@ -108,6 +152,13 @@ ranges; }; + thermal_sensor: thermal-sensor { + compatible = "generic-adc-thermal"; + #thermal-sensor-cells = <0>; + io-channels = <&adc AT91_SAMA7G5_ADC_TEMP_CHANNEL>; + io-channel-names = "sensor-channel"; + }; + soc { compatible = "simple-bus"; #address-cells = <1>; @@ -153,7 +204,7 @@ }; }; - securam: securam@e0000000 { + securam: sram@e0000000 { compatible = "microchip,sama7g5-securam", "atmel,sama5d2-securam", "mmio-sram"; reg = <0xe0000000 0x4000>; clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; @@ -420,6 +471,9 @@ atmel,min-sample-rate-hz = <200000>; atmel,max-sample-rate-hz = <20000000>; atmel,startup-time-ms = <4>; + #io-channel-cells = <1>; + nvmem-cells = <&temperature_calib>; + nvmem-cell-names = "temperature_calib"; status = "disabled"; }; @@ -888,6 +942,17 @@ reg = <0xe3804000 0x1000>; }; + otpc: efuse@e8c00000 { + compatible = "microchip,sama7g5-otpc", "syscon"; + reg = <0xe8c00000 0x100>; + #address-cells = <1>; + #size-cells = <1>; + + temperature_calib: calib@1 { + reg = <OTP_PKT(1) 76>; + }; + }; + gic: interrupt-controller@e8c11000 { compatible = "arm,cortex-a7-gic"; #interrupt-cells = <3>; diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 2459f3cd7dd9..6eda6fdc101b 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -453,7 +453,6 @@ compatible = "altr,socfpga-gate-clk"; clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; clk-gate = <0xa0 8>; - clk-phase = <0 135>; }; sdmmc_clk_divided: sdmmc_clk_divided { @@ -755,7 +754,7 @@ reg = <0xff800000 0x1000>; }; - mmc: dwmmc0@ff704000 { + mmc: mmc@ff704000 { compatible = "altr,socfpga-dw-mshc"; reg = <0xff704000 0x1000>; interrupts = <0 139 4>; @@ -765,6 +764,7 @@ clocks = <&l4_mp_clk>, <&sdmmc_clk_divided>; clock-names = "biu", "ciu"; resets = <&rst SDMMC_RESET>; + altr,sysmgr-syscon = <&sysmgr 0x108 3>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index 4370e3cbbb4b..3b2a2c9c6547 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -365,7 +365,6 @@ compatible = "altr,socfpga-a10-gate-clk"; clocks = <&sdmmc_free_clk>; clk-gate = <0xC8 5>; - clk-phase = <0 135>; }; qspi_clk: qspi_clk { @@ -656,7 +655,7 @@ arm,shared-override; }; - mmc: dwmmc0@ff808000 { + mmc: mmc@ff808000 { #address-cells = <1>; #size-cells = <0>; compatible = "altr,socfpga-dw-mshc"; @@ -666,6 +665,7 @@ clocks = <&l4_mp_clk>, <&sdmmc_clk>; clock-names = "biu", "ciu"; resets = <&rst SDMMC_RESET>; + altr,sysmgr-syscon = <&sysmgr 0x28 4>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi b/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi index ad7cd14de6b6..41f865c8c098 100644 --- a/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi @@ -73,6 +73,7 @@ cap-sd-highspeed; broken-cd; bus-width = <4>; + clk-phase-sd-hs = <0>, <135>; }; &osc1 { diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk_nand.dts b/arch/arm/boot/dts/socfpga_arria10_socdk_nand.dts index 9aa897b79544..a662df319a84 100644 --- a/arch/arm/boot/dts/socfpga_arria10_socdk_nand.dts +++ b/arch/arm/boot/dts/socfpga_arria10_socdk_nand.dts @@ -16,11 +16,11 @@ partition@0 { label = "Boot and fpga data"; - reg = <0x0 0x02000000>; + reg = <0x0 0x02500000>; }; partition@1c00000 { label = "Root Filesystem - JFFS2"; - reg = <0x02000000 0x06000000>; + reg = <0x02500000 0x05500000>; }; }; }; diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts b/arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts index 64dc0799f3d7..d3969367f4b5 100644 --- a/arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts +++ b/arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts @@ -12,6 +12,7 @@ cap-mmc-highspeed; broken-cd; bus-width = <4>; + clk-phase-sd-hs = <0>, <135>; }; &eccmgr { diff --git a/arch/arm/boot/dts/socfpga_arria5.dtsi b/arch/arm/boot/dts/socfpga_arria5.dtsi index 22dbf07afcff..40fecde65c54 100644 --- a/arch/arm/boot/dts/socfpga_arria5.dtsi +++ b/arch/arm/boot/dts/socfpga_arria5.dtsi @@ -18,11 +18,12 @@ }; }; - mmc0: dwmmc0@ff704000 { + mmc0: mmc@ff704000 { broken-cd; bus-width = <4>; cap-mmc-highspeed; cap-sd-highspeed; + clk-phase-sd-hs = <0>, <135>; }; sysmgr@ffd08000 { diff --git a/arch/arm/boot/dts/socfpga_arria5_socdk.dts b/arch/arm/boot/dts/socfpga_arria5_socdk.dts index 7f5458d8fccc..c48385702a85 100644 --- a/arch/arm/boot/dts/socfpga_arria5_socdk.dts +++ b/arch/arm/boot/dts/socfpga_arria5_socdk.dts @@ -29,22 +29,22 @@ leds { compatible = "gpio-leds"; - hps0 { + led-hps0 { label = "hps_led0"; gpios = <&porta 0 1>; }; - hps1 { + led-hps1 { label = "hps_led1"; gpios = <&portb 11 1>; }; - hps2 { + led-hps2 { label = "hps_led2"; gpios = <&porta 17 1>; }; - hps3 { + led-hps3 { label = "hps_led3"; gpios = <&porta 18 1>; }; diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dtsi b/arch/arm/boot/dts/socfpga_cyclone5.dtsi index 319a71e41ea4..305fe207b237 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5.dtsi +++ b/arch/arm/boot/dts/socfpga_cyclone5.dtsi @@ -18,11 +18,12 @@ }; }; - mmc0: dwmmc0@ff704000 { + mmc0: mmc@ff704000 { broken-cd; bus-width = <4>; cap-mmc-highspeed; cap-sd-highspeed; + clk-phase-sd-hs = <0>, <135>; }; sysmgr@ffd08000 { diff --git a/arch/arm/boot/dts/socfpga_cyclone5_de0_nano_soc.dts b/arch/arm/boot/dts/socfpga_cyclone5_de0_nano_soc.dts index c8f051fb2bf6..bedf577cb056 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_de0_nano_soc.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_de0_nano_soc.dts @@ -33,7 +33,7 @@ leds { compatible = "gpio-leds"; - hps0 { + led-hps0 { label = "hps_led0"; gpios = <&portb 24 0>; linux,default-trigger = "heartbeat"; diff --git a/arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi b/arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi index bd92806ffc12..3b9daddf91cd 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi +++ b/arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi @@ -18,5 +18,6 @@ &mmc0 { /* On-SoM eMMC */ bus-width = <8>; + clk-phase-sd-hs = <0>, <135>; status = "okay"; }; diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts index b2241205c7a9..c7f5fa0ba0f2 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts @@ -29,22 +29,22 @@ leds { compatible = "gpio-leds"; - hps0 { + led-hps0 { label = "hps_led0"; gpios = <&portb 15 1>; }; - hps1 { + led-hps1 { label = "hps_led1"; gpios = <&portb 14 1>; }; - hps2 { + led-hps2 { label = "hps_led2"; gpios = <&portb 13 1>; }; - hps3 { + led-hps3 { label = "hps_led3"; gpios = <&portb 12 1>; }; diff --git a/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts b/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts index f24f17c2f5ee..e0630b0eed03 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts @@ -141,7 +141,7 @@ reg = <0x50>; }; - i2cswitch@70 { + i2c-mux@70 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/socfpga_vt.dts index a77846f73b34..3d0d806888b7 100644 --- a/arch/arm/boot/dts/socfpga_vt.dts +++ b/arch/arm/boot/dts/socfpga_vt.dts @@ -29,7 +29,7 @@ }; }; - dwmmc0@ff704000 { + mmc@ff704000 { broken-cd; bus-width = <4>; cap-mmc-highspeed; diff --git a/arch/arm/boot/dts/spear600.dtsi b/arch/arm/boot/dts/spear600.dtsi index fd41243a0b2c..6b67c0ceaed9 100644 --- a/arch/arm/boot/dts/spear600.dtsi +++ b/arch/arm/boot/dts/spear600.dtsi @@ -47,7 +47,7 @@ compatible = "arm,pl110", "arm,primecell"; reg = <0xfc200000 0x1000>; interrupt-parent = <&vic1>; - interrupts = <12>; + interrupts = <13>; status = "disabled"; }; @@ -207,6 +207,36 @@ interrupts = <6>; status = "disabled"; }; + + ssp1: spi@d0100000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0xd0100000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&vic0>; + interrupts = <26>; + status = "disabled"; + }; + + ssp2: spi@d0180000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0xd0180000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&vic0>; + interrupts = <27>; + status = "disabled"; + }; + + ssp3: spi@d8180000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0xd8180000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&vic1>; + interrupts = <5>; + status = "disabled"; + }; }; }; }; diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi index 9afe8301bd47..a42a4fd69299 100644 --- a/arch/arm/boot/dts/ste-dbx5x0.dtsi +++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi @@ -1149,17 +1149,15 @@ compatible = "stericsson,ux500-cryp"; reg = <0xa03cb000 0x1000>; interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; - - v-ape-supply = <&db8500_vape_reg>; clocks = <&prcc_pclk 6 1>; + power-domains = <&pm_domains DOMAIN_VAPE>; }; hash@a03c2000 { compatible = "stericsson,ux500-hash"; reg = <0xa03c2000 0x1000>; - - v-ape-supply = <&db8500_vape_reg>; clocks = <&prcc_pclk 6 2>; + power-domains = <&pm_domains DOMAIN_VAPE>; }; }; }; diff --git a/arch/arm/boot/dts/ste-ux500-samsung-codina-tmo.dts b/arch/arm/boot/dts/ste-ux500-samsung-codina-tmo.dts index d6940e0afa86..17dff403f77a 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-codina-tmo.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-codina-tmo.dts @@ -239,7 +239,7 @@ }; }; - spi-gpio-0 { + spi { compatible = "spi-gpio"; /* Clock on GPIO220, pin SCL */ sck-gpios = <&gpio6 28 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/ste-ux500-samsung-codina.dts b/arch/arm/boot/dts/ste-ux500-samsung-codina.dts index 5f41256d7f4b..9db490cc395b 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-codina.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-codina.dts @@ -325,7 +325,7 @@ }; }; - spi-gpio-0 { + spi { compatible = "spi-gpio"; /* Clock on GPIO220, pin SCL */ sck-gpios = <&gpio6 28 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/ste-ux500-samsung-gavini.dts b/arch/arm/boot/dts/ste-ux500-samsung-gavini.dts index 806da3fc33cd..79d43fc68cd8 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-gavini.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-gavini.dts @@ -269,7 +269,7 @@ /* * TODO: See if we can use the PL023 for this instead. */ - spi-gpio-0 { + spi { compatible = "spi-gpio"; /* Clock on GPIO220, pin SCL */ sck-gpios = <&gpio6 28 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/ste-ux500-samsung-janice.dts b/arch/arm/boot/dts/ste-ux500-samsung-janice.dts index ed5c79c3d04b..04cd3c3757d6 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-janice.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-janice.dts @@ -263,7 +263,7 @@ * this derivative is 3wire support, so it cannot be used to drive * this panel interface. We have to use GPIO bit-banging instead. */ - spi-gpio-0 { + spi { compatible = "spi-gpio"; /* Clock on GPIO220 */ sck-gpios = <&gpio6 28 GPIO_ACTIVE_HIGH>; @@ -365,9 +365,13 @@ #address-cells = <1>; #size-cells = <0>; - nfc@30 { - compatible = "nxp,pn547", "nxp,nxp-nci-i2c"; - reg = <0x30>; + /* This is only mounted on the GT-I9070P */ + nfc@2b { /* 0x30? */ + /* NXP NFC circuit PN544 C1 marked NXP 44501 */ + compatible = "nxp,pn544-i2c"; + /* IF0, IF1 high, gives I2C address 0x2B */ + reg = <0x2b>; + clock-frequency = <400000>; /* NFC IRQ on GPIO32 */ interrupt-parent = <&gpio1>; interrupts = <0 IRQ_TYPE_EDGE_FALLING>; @@ -376,7 +380,7 @@ /* GPIO88 */ enable-gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; - pinctrl-0 = <&pn547_janice_default>; + pinctrl-0 = <&pn544_janice_default>; }; }; @@ -951,7 +955,7 @@ }; }; nfc { - pn547_janice_default: pn547_janice { + pn544_janice_default: pn544_janice { /* Interrupt line */ janice_cfg1 { pins = "GPIO32_V2"; diff --git a/arch/arm/boot/dts/ste-ux500-samsung-kyle.dts b/arch/arm/boot/dts/ste-ux500-samsung-kyle.dts index c57676faf181..e6a7d608e326 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-kyle.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-kyle.dts @@ -307,6 +307,21 @@ pinctrl-names = "default", "sleep"; pinctrl-0 = <&u1rxtx_a_1_default &u1ctsrts_a_1_default>; pinctrl-1 = <&u1rxtx_a_1_sleep &u1ctsrts_a_1_sleep>; + + gnss { + /* The CSRG05TA03-ICJE-R is a SirfStarV 5t chip */ + compatible = "csr,csrg05ta03-icje-r"; + /* GPS_RSTN on GPIO21 */ + reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; + /* GPS_ON_OFF on GPIO86 */ + sirf,onoff-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; + /* GPS_1V8 (VSMPS2) */ + vcc-supply = <&db8500_vsmps2_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&g05ta03_kyle_default>; + /* According to /etc/sirfgps.conf */ + current-speed = <460800>; + }; }; /* Debugging console UART connected to AB8505 USB */ @@ -666,6 +681,20 @@ }; }; }; + g05ta03 { + g05ta03_kyle_default: g05ta03 { + /* Reset line, start out de-asserted */ + kyle_cfg1 { + pins = "GPIO21_AB3"; + ste,config = <&gpio_out_hi>; + }; + /* GPS_ON_OFF, start out deasserted (off) */ + kyle_cfg2 { + pins = "GPIO86_C6"; + ste,config = <&gpio_out_lo>; + }; + }; + }; }; &ab8505_gpio { diff --git a/arch/arm/boot/dts/stih410-b2260.dts b/arch/arm/boot/dts/stih410-b2260.dts index 26d93f26f6d0..240b62040000 100644 --- a/arch/arm/boot/dts/stih410-b2260.dts +++ b/arch/arm/boot/dts/stih410-b2260.dts @@ -27,26 +27,26 @@ leds { compatible = "gpio-leds"; - user_green_1 { + led-user-green-1 { label = "User_green_1"; gpios = <&pio1 3 GPIO_ACTIVE_LOW>; linux,default-trigger = "heartbeat"; default-state = "off"; }; - user_green_2 { + led-user-green-2 { label = "User_green_2"; gpios = <&pio4 1 GPIO_ACTIVE_LOW>; default-state = "off"; }; - user_green_3 { + led-user-green-3 { label = "User_green_3"; gpios = <&pio2 1 GPIO_ACTIVE_LOW>; default-state = "off"; }; - user_green_4 { + led-user-green-4 { label = "User_green_4"; gpios = <&pio2 5 GPIO_ACTIVE_LOW>; default-state = "off"; diff --git a/arch/arm/boot/dts/stih418-b2199.dts b/arch/arm/boot/dts/stih418-b2199.dts index d21bcc7c1271..53ac6c2b7b7d 100644 --- a/arch/arm/boot/dts/stih418-b2199.dts +++ b/arch/arm/boot/dts/stih418-b2199.dts @@ -26,12 +26,12 @@ leds { compatible = "gpio-leds"; - red { + led-red { label = "Front Panel LED"; gpios = <&pio4 1 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; - green { + led-green { gpios = <&pio1 3 GPIO_ACTIVE_HIGH>; default-state = "off"; }; diff --git a/arch/arm/boot/dts/stih418-b2264.dts b/arch/arm/boot/dts/stih418-b2264.dts index a99604bebf8c..34a518b037ab 100644 --- a/arch/arm/boot/dts/stih418-b2264.dts +++ b/arch/arm/boot/dts/stih418-b2264.dts @@ -76,7 +76,7 @@ soc { leds { compatible = "gpio-leds"; - green { + led-green { gpios = <&pio1 3 GPIO_ACTIVE_HIGH>; default-state = "off"; }; diff --git a/arch/arm/boot/dts/stihxxx-b2120.dtsi b/arch/arm/boot/dts/stihxxx-b2120.dtsi index 2aa94605d3d4..920a0bad7494 100644 --- a/arch/arm/boot/dts/stihxxx-b2120.dtsi +++ b/arch/arm/boot/dts/stihxxx-b2120.dtsi @@ -9,12 +9,12 @@ / { leds { compatible = "gpio-leds"; - red { + led-red { label = "Front Panel LED"; gpios = <&pio4 1 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; - green { + led-green { gpios = <&pio1 3 GPIO_ACTIVE_HIGH>; default-state = "off"; }; diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi index 2059593da21d..28e3deb20e1e 100644 --- a/arch/arm/boot/dts/stm32h743.dtsi +++ b/arch/arm/boot/dts/stm32h743.dtsi @@ -375,7 +375,6 @@ arm,primecell-periphid = <0x10153180>; reg = <0x52007000 0x1000>; interrupts = <49>; - interrupt-names = "cmd_irq"; clocks = <&rcc SDMMC1_CK>; clock-names = "apb_pclk"; resets = <&rcc STM32H7_AHB3_RESET(SDMMC1)>; @@ -389,7 +388,6 @@ arm,primecell-periphid = <0x10153180>; reg = <0x48022400 0x400>; interrupts = <124>; - interrupt-names = "cmd_irq"; clocks = <&rcc SDMMC2_CK>; clock-names = "apb_pclk"; resets = <&rcc STM32H7_AHB2_RESET(SDMMC2)>; diff --git a/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi index efdd163eba30..d377d4c0bef5 100644 --- a/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi @@ -6,6 +6,13 @@ #include <dt-bindings/pinctrl/stm32-pinfunc.h> &pinctrl { + adc1_usb_cc_pins_a: adc1-usb-cc-pins-0 { + pins { + pinmux = <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */ + <STM32_PINMUX('A', 3, ANALOG)>; /* ADC1 in12 */ + }; + }; + i2c1_pins_a: i2c1-0 { pins { pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */ @@ -40,6 +47,13 @@ }; }; + mcp23017_pins_a: mcp23017-0 { + pins { + pinmux = <STM32_PINMUX('G', 12, GPIO)>; + bias-pull-up; + }; + }; + sdmmc1_b4_pins_a: sdmmc1-b4-0 { pins { pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ @@ -165,6 +179,13 @@ }; }; + stm32g0_intn_pins_a: stm32g0-intn-0 { + pins { + pinmux = <STM32_PINMUX('I', 2, GPIO)>; + bias-pull-up; + }; + }; + uart4_pins_a: uart4-0 { pins1 { pinmux = <STM32_PINMUX('D', 6, AF8)>; /* UART4_TX */ diff --git a/arch/arm/boot/dts/stm32mp131.dtsi b/arch/arm/boot/dts/stm32mp131.dtsi index dd35a607073d..accc3824f7e9 100644 --- a/arch/arm/boot/dts/stm32mp131.dtsi +++ b/arch/arm/boot/dts/stm32mp131.dtsi @@ -77,6 +77,28 @@ always-on; }; + /* PWR 1v1, 1v8 and 3v3 regulators defined as fixed, waiting for SCMI */ + reg11: reg11 { + compatible = "regulator-fixed"; + regulator-name = "reg11"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + }; + + reg18: reg18 { + compatible = "regulator-fixed"; + regulator-name = "reg18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + usb33: usb33 { + compatible = "regulator-fixed"; + regulator-name = "usb33"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + soc { compatible = "simple-bus"; #address-cells = <1>; @@ -231,6 +253,66 @@ dma-channels = <16>; }; + adc_2: adc@48004000 { + compatible = "st,stm32mp13-adc-core"; + reg = <0x48004000 0x400>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc ADC2>, <&rcc ADC2_K>; + clock-names = "bus", "adc"; + interrupt-controller; + #interrupt-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + adc2: adc@0 { + compatible = "st,stm32mp13-adc"; + #io-channel-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + interrupt-parent = <&adc_2>; + interrupts = <0>; + dmas = <&dmamux1 10 0x400 0x80000001>; + dma-names = "rx"; + status = "disabled"; + + channel@13 { + reg = <13>; + label = "vrefint"; + }; + channel@14 { + reg = <14>; + label = "vddcore"; + }; + channel@16 { + reg = <16>; + label = "vddcpu"; + }; + channel@17 { + reg = <17>; + label = "vddq_ddr"; + }; + }; + }; + + usbotg_hs: usb@49000000 { + compatible = "st,stm32mp15-hsotg", "snps,dwc2"; + reg = <0x49000000 0x40000>; + clocks = <&rcc USBO_K>; + clock-names = "otg"; + resets = <&rcc USBO_R>; + reset-names = "dwc2"; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + g-rx-fifo-size = <512>; + g-np-tx-fifo-size = <32>; + g-tx-fifo-size = <256 16 16 16 16 16 16 16>; + dr_mode = "otg"; + otg-rev = <0x200>; + usb33d-supply = <&usb33>; + status = "disabled"; + }; + spi4: spi@4c002000 { compatible = "st,stm32h7-spi"; reg = <0x4c002000 0x400>; @@ -354,7 +436,6 @@ arm,primecell-periphid = <0x20253180>; reg = <0x58005000 0x1000>, <0x58006000 0x1000>; interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "cmd_irq"; clocks = <&rcc SDMMC1_K>; clock-names = "apb_pclk"; resets = <&rcc SDMMC1_R>; @@ -369,7 +450,6 @@ arm,primecell-periphid = <0x20253180>; reg = <0x58007000 0x1000>, <0x58008000 0x1000>; interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "cmd_irq"; clocks = <&rcc SDMMC2_K>; clock-names = "apb_pclk"; resets = <&rcc SDMMC2_R>; @@ -379,6 +459,25 @@ status = "disabled"; }; + usbh_ohci: usb@5800c000 { + compatible = "generic-ohci"; + reg = <0x5800c000 0x1000>; + clocks = <&usbphyc>, <&rcc USBH>; + resets = <&rcc USBH_R>; + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + usbh_ehci: usb@5800d000 { + compatible = "generic-ehci"; + reg = <0x5800d000 0x1000>; + clocks = <&usbphyc>, <&rcc USBH>; + resets = <&rcc USBH_R>; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; + companion = <&usbh_ohci>; + status = "disabled"; + }; + iwdg2: watchdog@5a002000 { compatible = "st,stm32mp1-iwdg"; reg = <0x5a002000 0x400>; @@ -387,6 +486,29 @@ status = "disabled"; }; + usbphyc: usbphyc@5a006000 { + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <0>; + compatible = "st,stm32mp1-usbphyc"; + reg = <0x5a006000 0x1000>; + clocks = <&rcc USBPHY_K>; + resets = <&rcc USBPHY_R>; + vdda1v1-supply = <®11>; + vdda1v8-supply = <®18>; + status = "disabled"; + + usbphyc_port0: usb-phy@0 { + #phy-cells = <0>; + reg = <0>; + }; + + usbphyc_port1: usb-phy@1 { + #phy-cells = <1>; + reg = <1>; + }; + }; + rtc: rtc@5c004000 { compatible = "st,stm32mp1-rtc"; reg = <0x5c004000 0x400>; diff --git a/arch/arm/boot/dts/stm32mp133.dtsi b/arch/arm/boot/dts/stm32mp133.dtsi index 531c263c9f46..df451c3c2a26 100644 --- a/arch/arm/boot/dts/stm32mp133.dtsi +++ b/arch/arm/boot/dts/stm32mp133.dtsi @@ -33,5 +33,36 @@ bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>; status = "disabled"; }; + + adc_1: adc@48003000 { + compatible = "st,stm32mp13-adc-core"; + reg = <0x48003000 0x400>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc ADC1>, <&rcc ADC1_K>; + clock-names = "bus", "adc"; + interrupt-controller; + #interrupt-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + adc1: adc@0 { + compatible = "st,stm32mp13-adc"; + #io-channel-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + interrupt-parent = <&adc_1>; + interrupts = <0>; + dmas = <&dmamux1 9 0x400 0x80000001>; + dma-names = "rx"; + status = "disabled"; + + channel@18 { + reg = <18>; + label = "vrefint"; + }; + }; + }; }; }; diff --git a/arch/arm/boot/dts/stm32mp135f-dk.dts b/arch/arm/boot/dts/stm32mp135f-dk.dts index de341d17e87d..9ff5a3eaf55b 100644 --- a/arch/arm/boot/dts/stm32mp135f-dk.dts +++ b/arch/arm/boot/dts/stm32mp135f-dk.dts @@ -59,6 +59,22 @@ }; }; + v3v3_sw: v3v3-sw { + compatible = "regulator-fixed"; + regulator-name = "v3v3_sw"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_adc: vdd-adc { + compatible = "regulator-fixed"; + regulator-name = "vdd_adc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + vdd_sd: vdd-sd { compatible = "regulator-fixed"; regulator-name = "vdd_sd"; @@ -66,6 +82,39 @@ regulator-max-microvolt = <2900000>; regulator-always-on; }; + + vdd_usb: vdd-usb { + compatible = "regulator-fixed"; + regulator-name = "vdd_usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; +}; + +&adc_1 { + pinctrl-names = "default"; + pinctrl-0 = <&adc1_usb_cc_pins_a>; + vdda-supply = <&vdd_adc>; + vref-supply = <&vdd_adc>; + status = "okay"; + adc1: adc@0 { + status = "okay"; + /* + * Type-C USB_PWR_CC1 & USB_PWR_CC2 on in6 & in12. + * Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C: + * 5 * (5.1 + 47kOhms) * 5pF => 1.3us. + * Use arbitrary margin here (e.g. 5us). + */ + channel@6 { + reg = <6>; + st,min-sample-time-ns = <5000>; + }; + channel@12 { + reg = <12>; + st,min-sample-time-ns = <5000>; + }; + }; }; &i2c1 { @@ -79,6 +128,42 @@ /* spare dmas for other usage */ /delete-property/dmas; /delete-property/dma-names; + + mcp23017: pinctrl@21 { + compatible = "microchip,mcp23017"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpiog>; + pinctrl-names = "default"; + pinctrl-0 = <&mcp23017_pins_a>; + interrupt-controller; + #interrupt-cells = <2>; + microchip,irq-mirror; + }; + + typec@53 { + compatible = "st,stm32g0-typec"; + reg = <0x53>; + /* Alert pin on PI2 */ + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&gpioi>; + /* Internal pull-up on PI2 */ + pinctrl-names = "default"; + pinctrl-0 = <&stm32g0_intn_pins_a>; + firmware-name = "stm32g0-ucsi.mp135f-dk.fw"; + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + + port { + con_usb_c_g0_ep: endpoint { + remote-endpoint = <&usbotg_hs_ep>; + }; + }; + }; + }; }; &i2c5 { @@ -108,7 +193,7 @@ pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_clk_pins_a>; pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_clk_pins_a>; pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; - broken-cd; + cd-gpios = <&gpioh 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; disable-wp; st,neg-edge; bus-width = <4>; @@ -128,3 +213,60 @@ pinctrl-0 = <&uart4_pins_a>; status = "okay"; }; + +&usbh_ehci { + phys = <&usbphyc_port0>; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + /* onboard HUB */ + hub@1 { + compatible = "usb424,2514"; + reg = <1>; + vdd-supply = <&v3v3_sw>; + }; +}; + +&usbotg_hs { + phys = <&usbphyc_port1 0>; + phy-names = "usb2-phy"; + usb-role-switch; + status = "okay"; + port { + usbotg_hs_ep: endpoint { + remote-endpoint = <&con_usb_c_g0_ep>; + }; + }; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; + st,current-boost-microamp = <1000>; + st,decrease-hs-slew-rate; + st,tune-hs-dc-level = <2>; + st,enable-hs-rftime-reduction; + st,trim-hs-current = <11>; + st,trim-hs-impedance = <2>; + st,tune-squelch-level = <1>; + st,enable-hs-rx-gain-eq; + st,no-hs-ftime-ctrl; + st,no-lsfs-sc; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; + st,current-boost-microamp = <1000>; + st,decrease-hs-slew-rate; + st,tune-hs-dc-level = <2>; + st,enable-hs-rftime-reduction; + st,trim-hs-current = <11>; + st,trim-hs-impedance = <2>; + st,tune-squelch-level = <1>; + st,enable-hs-rx-gain-eq; + st,no-hs-ftime-ctrl; + st,no-lsfs-sc; +}; diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index e02b3f5d44cb..5491b6c4dec2 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -1118,7 +1118,6 @@ arm,primecell-periphid = <0x00253180>; reg = <0x48004000 0x400>; interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "cmd_irq"; clocks = <&rcc SDMMC3_K>; clock-names = "apb_pclk"; resets = <&rcc SDMMC3_R>; @@ -1439,7 +1438,6 @@ arm,primecell-periphid = <0x00253180>; reg = <0x58005000 0x1000>; interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "cmd_irq"; clocks = <&rcc SDMMC1_K>; clock-names = "apb_pclk"; resets = <&rcc SDMMC1_R>; @@ -1454,7 +1452,6 @@ arm,primecell-periphid = <0x00253180>; reg = <0x58007000 0x1000>; interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "cmd_irq"; clocks = <&rcc SDMMC2_K>; clock-names = "apb_pclk"; resets = <&rcc SDMMC2_R>; diff --git a/arch/arm/boot/dts/stm32mp151a-dhcor-testbench.dts b/arch/arm/boot/dts/stm32mp151a-dhcor-testbench.dts new file mode 100644 index 000000000000..e0f828ecc2fa --- /dev/null +++ b/arch/arm/boot/dts/stm32mp151a-dhcor-testbench.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (C) 2022 Marek Vasut <marex@denx.de> + */ + +/dts-v1/; + +#include "stm32mp151.dtsi" +#include "stm32mp15xx-dhcor-som.dtsi" +#include "stm32mp15xx-dhcor-testbench.dtsi" + +/ { + model = "DH electronics STM32MP151A DHCOR Testbench"; + compatible = "dh,stm32mp151a-dhcor-testbench", + "dh,stm32mp151a-dhcor-som", + "st,stm32mp151"; +}; diff --git a/arch/arm/boot/dts/stm32mp157a-dhcor-avenger96.dts b/arch/arm/boot/dts/stm32mp157a-dhcor-avenger96.dts index 2e3c9fbb4eb3..275167f26fd9 100644 --- a/arch/arm/boot/dts/stm32mp157a-dhcor-avenger96.dts +++ b/arch/arm/boot/dts/stm32mp157a-dhcor-avenger96.dts @@ -13,7 +13,6 @@ /dts-v1/; #include "stm32mp157.dtsi" -#include "stm32mp15xc.dtsi" #include "stm32mp15xx-dhcor-som.dtsi" #include "stm32mp15xx-dhcor-avenger96.dtsi" diff --git a/arch/arm/boot/dts/stm32mp157c-emstamp-argon.dtsi b/arch/arm/boot/dts/stm32mp157c-emstamp-argon.dtsi index 30156b7546ed..aef02e6421a3 100644 --- a/arch/arm/boot/dts/stm32mp157c-emstamp-argon.dtsi +++ b/arch/arm/boot/dts/stm32mp157c-emstamp-argon.dtsi @@ -173,7 +173,7 @@ phy-handle = <&phy0>; st,eth-ref-clk-sel; - mdio0 { + mdio { #address-cells = <1>; #size-cells = <0>; compatible = "snps,dwmac-mdio"; diff --git a/arch/arm/boot/dts/stm32mp157c-ev1.dts b/arch/arm/boot/dts/stm32mp157c-ev1.dts index 050c3c27a420..a665189fe621 100644 --- a/arch/arm/boot/dts/stm32mp157c-ev1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ev1.dts @@ -144,7 +144,7 @@ max-speed = <1000>; phy-handle = <&phy0>; - mdio0 { + mdio { #address-cells = <1>; #size-cells = <0>; compatible = "snps,dwmac-mdio"; @@ -370,6 +370,14 @@ &usbh_ehci { phys = <&usbphyc_port0>; status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + /* onboard HUB */ + hub@1 { + compatible = "usb424,2514"; + reg = <1>; + vdd-supply = <&v3v3>; + }; }; &usbotg_hs { @@ -393,6 +401,11 @@ st,tune-squelch-level = <3>; st,tune-hs-rx-offset = <2>; st,no-lsfs-sc; + + connector { + compatible = "usb-a-connector"; + vbus-supply = <&vbus_sw>; + }; }; &usbphyc_port1 { diff --git a/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts b/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts index e8d2ec41d537..cb00ce7cec8b 100644 --- a/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts +++ b/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts @@ -112,7 +112,7 @@ phy-handle = <ðphy>; status = "okay"; - mdio0 { + mdio { compatible = "snps,dwmac-mdio"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/stm32mp157c-odyssey.dts b/arch/arm/boot/dts/stm32mp157c-odyssey.dts index ed66d25b8bf3..a8b3f7a54703 100644 --- a/arch/arm/boot/dts/stm32mp157c-odyssey.dts +++ b/arch/arm/boot/dts/stm32mp157c-odyssey.dts @@ -41,7 +41,7 @@ assigned-clock-rates = <125000000>; /* Clock PLL4 to 750Mhz in ATF/U-Boot */ st,eth-clk-sel; - mdio0 { + mdio { #address-cells = <1>; #size-cells = <0>; compatible = "snps,dwmac-mdio"; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi index 5f586f024060..4709677151aa 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi @@ -242,7 +242,7 @@ sai2a_port: port { sai2a_endpoint: endpoint { remote-endpoint = <&sgtl5000_tx_endpoint>; - format = "i2s"; + dai-format = "i2s"; mclk-fs = <512>; dai-tdm-slot-num = <2>; dai-tdm-slot-width = <16>; @@ -260,7 +260,7 @@ sai2b_port: port { sai2b_endpoint: endpoint { remote-endpoint = <&sgtl5000_rx_endpoint>; - format = "i2s"; + dai-format = "i2s"; mclk-fs = <512>; dai-tdm-slot-num = <2>; dai-tdm-slot-width = <16>; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi index 238a611192e7..002f221f1694 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi @@ -125,7 +125,7 @@ max-speed = <100>; phy-handle = <&phy0>; - mdio0 { + mdio { #address-cells = <1>; #size-cells = <0>; compatible = "snps,dwmac-mdio"; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi index 90933077d66d..50af4a27d6be 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi @@ -66,7 +66,6 @@ led4 { label = "green:user3"; gpios = <&gpiog 1 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "none"; default-state = "off"; panic-indicator; }; @@ -100,7 +99,7 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - gpios = <&gpioz 3 GPIO_ACTIVE_HIGH>; + gpio = <&gpioz 3 GPIO_ACTIVE_HIGH>; enable-active-high; }; }; @@ -151,7 +150,7 @@ max-speed = <1000>; phy-handle = <&phy0>; - mdio0 { + mdio { #address-cells = <1>; #size-cells = <0>; compatible = "snps,dwmac-mdio"; @@ -359,7 +358,7 @@ sai2a_port: port { sai2a_endpoint: endpoint { remote-endpoint = <&adv7513_i2s0>; - format = "i2s"; + dai-format = "i2s"; mclk-fs = <256>; }; }; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-drc-compact.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-drc-compact.dtsi index 27477bb219de..c32c160f97f2 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcor-drc-compact.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-drc-compact.dtsi @@ -78,7 +78,7 @@ max-speed = <1000>; phy-handle = <&phy0>; - mdio0 { + mdio { #address-cells = <1>; #size-cells = <0>; compatible = "snps,dwmac-mdio"; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-testbench.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-testbench.dtsi new file mode 100644 index 000000000000..5fdb74b652ac --- /dev/null +++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-testbench.dtsi @@ -0,0 +1,171 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (C) 2022 Marek Vasut <marex@denx.de> + */ + +/ { + aliases { + ethernet0 = ðernet0; + mmc0 = &sdmmc1; + mmc1 = &sdmmc2; + serial0 = &uart4; + serial1 = &uart7; + spi0 = &qspi; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + sd_switch: regulator-sd_switch { + compatible = "regulator-gpio"; + regulator-name = "sd_switch"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2900000>; + regulator-type = "voltage"; + regulator-always-on; + + gpios = <&gpioi 5 GPIO_ACTIVE_HIGH>; + gpios-states = <0>; + states = <1800000 0x1>, + <2900000 0x0>; + }; +}; + +&adc { + pinctrl-names = "default"; + pinctrl-0 = <&adc12_ain_pins_b>; + vdd-supply = <&vdd>; + vdda-supply = <&vdda>; + vref-supply = <&vdda>; + status = "okay"; + + adc1: adc@0 { + st,adc-channels = <0 1 6>; + st,min-sample-time-nsecs = <5000>; + status = "okay"; + }; + + adc2: adc@100 { + st,adc-channels = <0 1 2>; + st,min-sample-time-nsecs = <5000>; + status = "okay"; + }; +}; + +ðernet0 { + status = "okay"; + pinctrl-0 = <ðernet0_rgmii_pins_c>; + pinctrl-1 = <ðernet0_rgmii_sleep_pins_c>; + pinctrl-names = "default", "sleep"; + phy-mode = "rgmii"; + max-speed = <1000>; + phy-handle = <&phy0>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>; + reset-delay-us = <1000>; + reset-post-delay-us = <1000>; + + phy0: ethernet-phy@7 { + reg = <7>; + + rxc-skew-ps = <1500>; + rxdv-skew-ps = <540>; + rxd0-skew-ps = <420>; + rxd1-skew-ps = <420>; + rxd2-skew-ps = <420>; + rxd3-skew-ps = <420>; + + txc-skew-ps = <1440>; + txen-skew-ps = <540>; + txd0-skew-ps = <420>; + txd1-skew-ps = <420>; + txd2-skew-ps = <420>; + txd3-skew-ps = <420>; + }; + }; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_b>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_b>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_b>; + cd-gpios = <&gpioi 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + disable-wp; + st,sig-dir; + st,neg-edge; + st,use-ckin; + bus-width = <4>; + vmmc-supply = <&vdd_sd>; + vqmmc-supply = <&sd_switch>; + status = "okay"; +}; + +&sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_c>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_c>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_c>; + bus-width = <8>; + mmc-ddr-1_8v; + no-sd; + no-sdio; + non-removable; + st,neg-edge; + vmmc-supply = <&v3v3>; + vqmmc-supply = <&v3v3>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins_b>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&uart7_pins_a>; + uart-has-rtscts; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&usbh_ehci { + phys = <&usbphyc_port0>; + status = "okay"; +}; + +&usbh_ohci { + phys = <&usbphyc_port0>; + status = "okay"; +}; + +&usbotg_hs { + pinctrl-0 = <&usbotg_hs_pins_a>; + pinctrl-names = "default"; + phy-names = "usb2-phy"; + phys = <&usbphyc_port1 0>; + status = "okay"; + vbus-supply = <&vbus_otg>; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; +}; diff --git a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi index 8b48d3c89a04..7798a2e17c5c 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi @@ -141,7 +141,7 @@ max-speed = <1000>; phy-handle = <&phy0>; - mdio0 { + mdio { #address-cells = <1>; #size-cells = <0>; compatible = "snps,dwmac-mdio"; @@ -508,7 +508,7 @@ sai2a_port: port { sai2a_endpoint: endpoint { remote-endpoint = <&cs42l51_tx_endpoint>; - format = "i2s"; + dai-format = "i2s"; mclk-fs = <256>; dai-tdm-slot-num = <2>; dai-tdm-slot-width = <32>; @@ -526,7 +526,7 @@ sai2b_port: port { sai2b_endpoint: endpoint { remote-endpoint = <&cs42l51_rx_endpoint>; - format = "i2s"; + dai-format = "i2s"; mclk-fs = <256>; dai-tdm-slot-num = <2>; dai-tdm-slot-width = <32>; diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi index 0edc1724407b..9455d27e516e 100644 --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi @@ -166,6 +166,12 @@ drive-strength = <30>; }; + /omit-if-no-ref/ + i2c0_pd_pins: i2c0-pd-pins { + pins = "PD0", "PD12"; + function = "i2c0"; + }; + spi0_pc_pins: spi0-pc-pins { pins = "PC0", "PC1", "PC2", "PC3"; function = "spi0"; @@ -177,6 +183,42 @@ }; }; + i2c0: i2c@1c27000 { + compatible = "allwinner,suniv-f1c100s-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x01c27000 0x400>; + interrupts = <7>; + clocks = <&ccu CLK_BUS_I2C0>; + resets = <&ccu RST_BUS_I2C0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@1c27400 { + compatible = "allwinner,suniv-f1c100s-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x01c27400 0x400>; + interrupts = <8>; + clocks = <&ccu CLK_BUS_I2C1>; + resets = <&ccu RST_BUS_I2C1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@1c27800 { + compatible = "allwinner,suniv-f1c100s-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x01c27800 0x400>; + interrupts = <9>; + clocks = <&ccu CLK_BUS_I2C2>; + resets = <&ccu RST_BUS_I2C2>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + timer@1c20c00 { compatible = "allwinner,suniv-f1c100s-timer"; reg = <0x01c20c00 0x90>; @@ -192,6 +234,34 @@ clocks = <&osc32k>; }; + pwm: pwm@1c21000 { + compatible = "allwinner,suniv-f1c100s-pwm", + "allwinner,sun7i-a20-pwm"; + reg = <0x01c21000 0x400>; + clocks = <&osc24M>; + #pwm-cells = <3>; + status = "disabled"; + }; + + ir: ir@1c22c00 { + compatible = "allwinner,suniv-f1c100s-ir", + "allwinner,sun6i-a31-ir"; + reg = <0x01c22c00 0x400>; + clocks = <&ccu CLK_BUS_IR>, <&ccu CLK_IR>; + clock-names = "apb", "ir"; + resets = <&ccu RST_BUS_IR>; + interrupts = <6>; + status = "disabled"; + }; + + lradc: lradc@1c23400 { + compatible = "allwinner,suniv-f1c100s-lradc", + "allwinner,sun8i-a83t-r-lradc"; + reg = <0x01c23400 0x400>; + interrupts = <22>; + status = "disabled"; + }; + uart0: serial@1c25000 { compatible = "snps,dw-apb-uart"; reg = <0x01c25000 0x400>; diff --git a/arch/arm/boot/dts/sunplus-sp7021.dtsi b/arch/arm/boot/dts/sunplus-sp7021.dtsi index 7dc4ce3619c7..ae9bbe0320b8 100644 --- a/arch/arm/boot/dts/sunplus-sp7021.dtsi +++ b/arch/arm/boot/dts/sunplus-sp7021.dtsi @@ -211,7 +211,6 @@ interrupt-names = "dma_w", "master_risc", "slave_risc"; clocks = <&clkc CLK_SPI_COMBO_1>; resets = <&rstc RST_SPI_COMBO_1>; - spi-max-frequency = <25000000>; status = "disabled"; }; @@ -225,7 +224,6 @@ interrupt-names = "dma_w", "master_risc", "slave_risc"; clocks = <&clkc CLK_SPI_COMBO_2>; resets = <&rstc RST_SPI_COMBO_2>; - spi-max-frequency = <25000000>; status = "disabled"; }; @@ -239,7 +237,6 @@ interrupt-names = "dma_w", "master_risc", "slave_risc"; clocks = <&clkc CLK_SPI_COMBO_3>; resets = <&rstc RST_SPI_COMBO_3>; - spi-max-frequency = <25000000>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi b/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi index e899d14f38c3..1d1d127cf38f 100644 --- a/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi +++ b/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi @@ -89,13 +89,13 @@ }; reg_gmac_3v3: gmac-3v3 { - compatible = "regulator-fixed"; - regulator-name = "gmac-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - enable-active-high; - gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; + compatible = "regulator-fixed"; + regulator-name = "gmac-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + enable-active-high; + gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; }; wifi_pwrseq: wifi_pwrseq { diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index 09aefb4e90f8..686193bd6bd9 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -302,6 +302,8 @@ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>; resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>; + phys = <&usbphy 0>; + phy-names = "usb"; status = "disabled"; }; @@ -312,6 +314,8 @@ clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>, <&ccu CLK_USB_OHCI0>; resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>; + phys = <&usbphy 0>; + phy-names = "usb"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/tegra114-asus-tf701t.dts b/arch/arm/boot/dts/tegra114-asus-tf701t.dts index 284209b0bd96..9279d24db009 100644 --- a/arch/arm/boot/dts/tegra114-asus-tf701t.dts +++ b/arch/arm/boot/dts/tegra114-asus-tf701t.dts @@ -80,7 +80,7 @@ }; pinmux@70000868 { - asus_pad_ec_default: asus-pad-ec-default { + asus_pad_ec_default: pinmux-asus-pad-ec-default { ec-interrupt { nvidia,pins = "kb_col5_pq5"; nvidia,function = "kbc"; @@ -98,7 +98,7 @@ }; }; - backlight_default: backlight-default { + backlight_default: pinmux-backlight-default { backlight-enable { nvidia,pins = "gmi_ad10_ph2"; nvidia,function = "gmi"; @@ -108,7 +108,7 @@ }; }; - codec_default: codec-default { + codec_default: pinmux-codec-default { ldo1-en { nvidia,pins = "sdmmc1_wp_n_pv3"; nvidia,function = "sdmmc1"; @@ -127,7 +127,7 @@ }; }; - gpio_keys_default: gpio-keys-default { + gpio_keys_default: pinmux-gpio-keys-default { power { nvidia,pins = "kb_col0_pq0"; nvidia,function = "kbc"; @@ -146,7 +146,7 @@ }; }; - gpio_hall_sensor_default: gpio-hall-sensor-default { + gpio_hall_sensor_default: pinmux-gpio-hall-sensor-default { ulpi_data4_po5 { nvidia,pins = "ulpi_data4_po5"; nvidia,function = "spi2"; @@ -156,7 +156,7 @@ }; }; - hp_det_default: hp-det-default { + hp_det_default: pinmux-hp-det-default { gmi_iordy_pi5 { nvidia,pins = "kb_row7_pr7"; nvidia,function = "rsvd2"; @@ -166,7 +166,7 @@ }; }; - imu_default: imu-default { + imu_default: pinmux-imu-default { kb_row3_pr3 { nvidia,pins = "kb_row3_pr3"; nvidia,function = "rsvd3"; @@ -176,7 +176,7 @@ }; }; - pwm_default: pwm-default { + pwm_default: pinmux-pwm-default { gmi_ad9_ph1 { nvidia,pins = "gmi_ad9_ph1"; nvidia,function = "pwm1"; @@ -187,7 +187,7 @@ }; /* XXX make this something more sensible */ - pwm_sleep: pwm-sleep { + pwm_sleep: pinmux-pwm-sleep { gmi_ad9_ph1 { nvidia,pins = "gmi_ad9_ph1"; nvidia,function = "pwm1"; @@ -197,7 +197,7 @@ }; }; - sdmmc3_default: sdmmc3-default { + sdmmc3_default: pinmux-sdmmc3-default { sdmmc3_clk_pa6 { nvidia,pins = "sdmmc3_clk_pa6"; nvidia,function = "sdmmc3"; @@ -233,7 +233,7 @@ }; }; - sdmmc3_vdd_default: sdmmc3-vdd-default { + sdmmc3_vdd_default: pinmux-sdmmc3-vdd-default { gmi_clk_pk1 { nvidia,pins = "gmi_clk_pk1"; nvidia,function = "gmi"; @@ -243,7 +243,7 @@ }; }; - vdd_lcd_default: vdd-lcd-default { + vdd_lcd_default: pinmux-vdd-lcd-default { sdmmc4_clk_pcc4 { nvidia,pins = "sdmmc4_clk_pcc4"; nvidia,function = "sdmmc4"; diff --git a/arch/arm/boot/dts/tegra124-nyan-big.dts b/arch/arm/boot/dts/tegra124-nyan-big.dts index fdc1d64dfff9..9a01dfed1379 100644 --- a/arch/arm/boot/dts/tegra124-nyan-big.dts +++ b/arch/arm/boot/dts/tegra124-nyan-big.dts @@ -18,6 +18,7 @@ aux-bus { panel: panel { compatible = "auo,b133xtn01"; + power-supply = <&vdd_3v3_panel>; backlight = <&backlight>; }; }; @@ -39,7 +40,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinmux_default>; - pinmux_default: common { + pinmux_default: pinmux { clk_32k_out_pa0 { nvidia,pins = "clk_32k_out_pa0"; nvidia,pull = <TEGRA_PIN_PULL_NONE>; diff --git a/arch/arm/boot/dts/tegra124-nyan-blaze.dts b/arch/arm/boot/dts/tegra124-nyan-blaze.dts index abdf4456826f..0beef1c03ff3 100644 --- a/arch/arm/boot/dts/tegra124-nyan-blaze.dts +++ b/arch/arm/boot/dts/tegra124-nyan-blaze.dts @@ -20,6 +20,7 @@ aux-bus { panel: panel { compatible = "samsung,ltn140at29-301"; + power-supply = <&vdd_3v3_panel>; backlight = <&backlight>; }; }; @@ -37,7 +38,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinmux_default>; - pinmux_default: common { + pinmux_default: pinmux { clk_32k_out_pa0 { nvidia,pins = "clk_32k_out_pa0"; nvidia,pull = <TEGRA_PIN_PULL_NONE>; diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index 8f40fcfc11b0..7e739879c00c 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -52,6 +52,7 @@ aux-bus { panel: panel { compatible = "lg,lp129qe"; + power-supply = <&vdd_3v3_panel>; backlight = <&backlight>; }; }; @@ -70,7 +71,7 @@ pinctrl-names = "boot"; pinctrl-0 = <&pinmux_boot>; - pinmux_boot: common { + pinmux_boot: pinmux { dap_mclk1_pw4 { nvidia,pins = "dap_mclk1_pw4"; nvidia,function = "extperiph1"; diff --git a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts index dac6d02a1b15..17afc2c7cb37 100644 --- a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts +++ b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts @@ -342,7 +342,7 @@ }; }; - state_i2cmux_ddc: pinmux_i2cmux_ddc { + state_i2cmux_ddc: pinmux-i2cmux-ddc { ddc { nvidia,pins = "ddc"; nvidia,function = "i2c2"; @@ -353,7 +353,7 @@ }; }; - state_i2cmux_pta: pinmux_i2cmux_pta { + state_i2cmux_pta: pinmux-i2cmux-pta { ddc { nvidia,pins = "ddc"; nvidia,function = "rsvd4"; @@ -364,7 +364,7 @@ }; }; - state_i2cmux_idle: pinmux_i2cmux_idle { + state_i2cmux_idle: pinmux-i2cmux-idle { ddc { nvidia,pins = "ddc"; nvidia,function = "rsvd4"; diff --git a/arch/arm/boot/dts/tegra20-asus-tf101.dts b/arch/arm/boot/dts/tegra20-asus-tf101.dts index bf797a1f27ea..c39ddb462ad0 100644 --- a/arch/arm/boot/dts/tegra20-asus-tf101.dts +++ b/arch/arm/boot/dts/tegra20-asus-tf101.dts @@ -399,7 +399,7 @@ }; }; - state_i2cmux_ddc: pinmux_i2cmux_ddc { + state_i2cmux_ddc: pinmux-i2cmux-ddc { ddc { nvidia,pins = "ddc"; nvidia,function = "i2c2"; @@ -411,7 +411,7 @@ }; }; - state_i2cmux_pta: pinmux_i2cmux_pta { + state_i2cmux_pta: pinmux-i2cmux-pta { ddc { nvidia,pins = "ddc"; nvidia,function = "rsvd4"; @@ -423,7 +423,7 @@ }; }; - state_i2cmux_idle: pinmux_i2cmux_idle { + state_i2cmux_idle: pinmux-i2cmux-idle { ddc { nvidia,pins = "ddc"; nvidia,function = "rsvd4"; @@ -1019,7 +1019,7 @@ }; display-panel { - compatible = "panel-lvds"; + compatible = "auo,b101ew05", "panel-lvds"; /* AUO B101EW05 using custom timings */ diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts index 5b4c5ef30996..ab33ff67fdb9 100644 --- a/arch/arm/boot/dts/tegra20-seaboard.dts +++ b/arch/arm/boot/dts/tegra20-seaboard.dts @@ -285,7 +285,7 @@ }; }; - state_i2cmux_ddc: pinmux_i2cmux_ddc { + state_i2cmux_ddc: pinmux-i2cmux-ddc { ddc { nvidia,pins = "ddc"; nvidia,function = "i2c2"; @@ -296,7 +296,7 @@ }; }; - state_i2cmux_pta: pinmux_i2cmux_pta { + state_i2cmux_pta: pinmux-i2cmux-pta { ddc { nvidia,pins = "ddc"; nvidia,function = "rsvd4"; @@ -307,7 +307,7 @@ }; }; - state_i2cmux_idle: pinmux_i2cmux_idle { + state_i2cmux_idle: pinmux-i2cmux-idle { ddc { nvidia,pins = "ddc"; nvidia,function = "rsvd4"; diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi index 0e19bd0a847c..980272ad59a4 100644 --- a/arch/arm/boot/dts/tegra20-tamonten.dtsi +++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi @@ -249,7 +249,7 @@ }; }; - state_i2cmux_ddc: pinmux_i2cmux_ddc { + state_i2cmux_ddc: pinmux-i2cmux-ddc { ddc { nvidia,pins = "ddc"; nvidia,function = "i2c2"; @@ -260,7 +260,7 @@ }; }; - state_i2cmux_pta: pinmux_i2cmux_pta { + state_i2cmux_pta: pinmux-i2cmux-pta { ddc { nvidia,pins = "ddc"; nvidia,function = "rsvd4"; @@ -271,7 +271,7 @@ }; }; - state_i2cmux_idle: pinmux_i2cmux_idle { + state_i2cmux_idle: pinmux-i2cmux-idle { ddc { nvidia,pins = "ddc"; nvidia,function = "rsvd4"; diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts index caa17e876e41..2d7bb442d6b6 100644 --- a/arch/arm/boot/dts/tegra20-ventana.dts +++ b/arch/arm/boot/dts/tegra20-ventana.dts @@ -284,7 +284,7 @@ }; }; - state_i2cmux_ddc: pinmux_i2cmux_ddc { + state_i2cmux_ddc: pinmux-i2cmux-ddc { ddc { nvidia,pins = "ddc"; nvidia,function = "i2c2"; @@ -295,7 +295,7 @@ }; }; - state_i2cmux_pta: pinmux_i2cmux_pta { + state_i2cmux_pta: pinmux-i2cmux-pta { ddc { nvidia,pins = "ddc"; nvidia,function = "rsvd4"; @@ -306,7 +306,7 @@ }; }; - state_i2cmux_idle: pinmux_i2cmux_idle { + state_i2cmux_idle: pinmux-i2cmux-idle { ddc { nvidia,pins = "ddc"; nvidia,function = "rsvd4"; diff --git a/arch/arm/boot/dts/tegra30-asus-transformer-common.dtsi b/arch/arm/boot/dts/tegra30-asus-transformer-common.dtsi index c27e70d8bf2b..08ea9cb32d0e 100644 --- a/arch/arm/boot/dts/tegra30-asus-transformer-common.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-transformer-common.dtsi @@ -168,7 +168,7 @@ nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; nvidia,lock = <0>; - nvidia,ioreset = <0>; + nvidia,io-reset = <0>; }; /* SDMMC3 pinmux */ @@ -711,7 +711,7 @@ nvidia,tristate = <TEGRA_PIN_ENABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; nvidia,lock = <0>; - nvidia,ioreset = <0>; + nvidia,io-reset = <0>; }; /* GPIO keys pinmux */ @@ -805,7 +805,7 @@ nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; nvidia,lock = <0>; - nvidia,ioreset = <0>; + nvidia,io-reset = <0>; }; vi_d10_pt2 { @@ -937,7 +937,7 @@ nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_DISABLE>; nvidia,lock = <0>; - nvidia,ioreset = <0>; + nvidia,io-reset = <0>; }; vi_mclk_pt1 { @@ -1509,7 +1509,6 @@ extcon-keys { compatible = "gpio-keys"; - interrupt-parent = <&gpio>; switch-dock-hall-sensor { label = "Lid sensor"; @@ -1542,7 +1541,6 @@ gpio-keys { compatible = "gpio-keys"; - interrupt-parent = <&gpio>; key-power { label = "Power"; diff --git a/arch/arm/boot/dts/tegra30-pegatron-chagall.dts b/arch/arm/boot/dts/tegra30-pegatron-chagall.dts index 7c81f0205549..d9408a90653a 100644 --- a/arch/arm/boot/dts/tegra30-pegatron-chagall.dts +++ b/arch/arm/boot/dts/tegra30-pegatron-chagall.dts @@ -134,7 +134,7 @@ nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; nvidia,lock = <0>; - nvidia,ioreset = <0>; + nvidia,io-reset = <0>; }; /* SDMMC3 pinmux */ @@ -150,7 +150,6 @@ nvidia,pins = "sdmmc3_cmd_pa7", "sdmmc3_dat3_pb4", "sdmmc3_dat2_pb5", - "sdmmc3_dat2_pb5", "sdmmc3_dat1_pb6", "sdmmc3_dat0_pb7", "sdmmc3_dat5_pd0", @@ -622,7 +621,7 @@ nvidia,tristate = <TEGRA_PIN_ENABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; nvidia,lock = <0>; - nvidia,ioreset = <0>; + nvidia,io-reset = <0>; }; pu1 { @@ -689,7 +688,7 @@ nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; nvidia,lock = <0>; - nvidia,ioreset = <0>; + nvidia,io-reset = <0>; }; vi_d10_pt2 { @@ -864,7 +863,7 @@ nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_DISABLE>; nvidia,lock = <0>; - nvidia,ioreset = <0>; + nvidia,io-reset = <0>; }; vi_mclk_pt1 { @@ -2653,7 +2652,6 @@ extcon-keys { compatible = "gpio-keys"; - interrupt-parent = <&gpio>; switch-dock-insert { label = "Chagall Dock"; @@ -2686,7 +2684,6 @@ gpio-keys { compatible = "gpio-keys"; - interrupt-parent = <&gpio>; key-power { label = "Power"; diff --git a/arch/arm/boot/dts/uniphier-pro5-epcore.dts b/arch/arm/boot/dts/uniphier-pro5-epcore.dts new file mode 100644 index 000000000000..ed759dcc3216 --- /dev/null +++ b/arch/arm/boot/dts/uniphier-pro5-epcore.dts @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Device Tree Source for UniPhier Pro5 EP-CORE Board (Pro5-PCIe_EP-CORE) + * + * Copyright (C) 2021 Socionext Inc. + * Author: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> + */ + +/dts-v1/; +#include "uniphier-pro5.dtsi" +#include "uniphier-support-card.dtsi" + +/ { + model = "UniPhier Pro5 EP-CORE Board"; + compatible = "socionext,uniphier-pro5-epcore", "socionext,uniphier-pro5"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + serial0 = &serial0; + serial1 = &serial1; + serial2 = &serial2; + i2c0 = &i2c0; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; +}; + +ðsc { + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; +}; + +&serialsc { + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; +}; + +&serial0 { + status = "okay"; +}; + +&serial1 { + status = "okay"; +}; + +&serial2 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +&emmc { + status = "okay"; +}; + +&sd { + status = "okay"; +}; + +&pcie_ep { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/uniphier-pro5-proex.dts b/arch/arm/boot/dts/uniphier-pro5-proex.dts new file mode 100644 index 000000000000..2cfb84f73cc0 --- /dev/null +++ b/arch/arm/boot/dts/uniphier-pro5-proex.dts @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Device Tree Source for UniPhier Pro5 ProEX Board + * + * Copyright (C) 2021 Socionext Inc. + * Author: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> + */ + +/dts-v1/; +#include "uniphier-pro5.dtsi" + +/ { + model = "UniPhier Pro5 ProEX Board"; + compatible = "socionext,uniphier-pro5-proex", "socionext,uniphier-pro5"; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + aliases { + serial1 = &serial1; + serial2 = &serial2; + i2c0 = &i2c0; + i2c1 = &i2c3; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; +}; + +&serial1 { + status = "okay"; +}; + +&serial2 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +&emmc { + status = "okay"; +}; + +&pcie_ep { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/vexpress-v2m.dtsi b/arch/arm/boot/dts/vexpress-v2m.dtsi index f434fe5cf4a1..def538ce8769 100644 --- a/arch/arm/boot/dts/vexpress-v2m.dtsi +++ b/arch/arm/boot/dts/vexpress-v2m.dtsi @@ -383,49 +383,49 @@ leds { compatible = "gpio-leds"; - user1 { + led-user1 { label = "v2m:green:user1"; gpios = <&v2m_led_gpios 0 0>; linux,default-trigger = "heartbeat"; }; - user2 { + led-user2 { label = "v2m:green:user2"; gpios = <&v2m_led_gpios 1 0>; linux,default-trigger = "mmc0"; }; - user3 { + led-user3 { label = "v2m:green:user3"; gpios = <&v2m_led_gpios 2 0>; linux,default-trigger = "cpu0"; }; - user4 { + led-user4 { label = "v2m:green:user4"; gpios = <&v2m_led_gpios 3 0>; linux,default-trigger = "cpu1"; }; - user5 { + led-user5 { label = "v2m:green:user5"; gpios = <&v2m_led_gpios 4 0>; linux,default-trigger = "cpu2"; }; - user6 { + led-user6 { label = "v2m:green:user6"; gpios = <&v2m_led_gpios 5 0>; linux,default-trigger = "cpu3"; }; - user7 { + led-user7 { label = "v2m:green:user7"; gpios = <&v2m_led_gpios 6 0>; linux,default-trigger = "cpu4"; }; - user8 { + led-user8 { label = "v2m:green:user8"; gpios = <&v2m_led_gpios 7 0>; linux,default-trigger = "cpu5"; diff --git a/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts b/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts index de79dcfd32e6..f892977da9e4 100644 --- a/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts +++ b/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts @@ -259,7 +259,7 @@ xtal-trim = /bits/ 8 <0x06>; sleep-gpio = <&gpio0 24 GPIO_ACTIVE_HIGH>; - reset-gpio = <&gpio6 10 GPIO_ACTIVE_HIGH>; + reset-gpio = <&gpio6 10 GPIO_ACTIVE_LOW>; fsl,spi-cs-sck-delay = <180>; fsl,spi-sck-cs-delay = <250>; diff --git a/arch/arm/mach-mvebu/pm-board.c b/arch/arm/mach-mvebu/pm-board.c index 7fa1806acd65..beec22e17e89 100644 --- a/arch/arm/mach-mvebu/pm-board.c +++ b/arch/arm/mach-mvebu/pm-board.c @@ -8,19 +8,19 @@ */ #include <linux/delay.h> -#include <linux/gpio.h> +#include <linux/err.h> +#include <linux/gpio/consumer.h> #include <linux/init.h> #include <linux/io.h> #include <linux/of.h> #include <linux/of_address.h> -#include <linux/of_gpio.h> #include <linux/slab.h> #include "common.h" #define ARMADA_PIC_NR_GPIOS 3 static void __iomem *gpio_ctrl; -static int pic_gpios[ARMADA_PIC_NR_GPIOS]; +static struct gpio_desc *pic_gpios[ARMADA_PIC_NR_GPIOS]; static int pic_raw_gpios[ARMADA_PIC_NR_GPIOS]; static void mvebu_armada_pm_enter(void __iomem *sdram_reg, u32 srcmd) @@ -90,27 +90,17 @@ static int __init mvebu_armada_pm_init(void) char *name; struct of_phandle_args args; - pic_gpios[i] = of_get_named_gpio(np, "ctrl-gpios", i); - if (pic_gpios[i] < 0) { - ret = -ENODEV; - goto out; - } - name = kasprintf(GFP_KERNEL, "pic-pin%d", i); if (!name) { ret = -ENOMEM; goto out; } - ret = gpio_request(pic_gpios[i], name); - if (ret < 0) { - kfree(name); - goto out; - } - - ret = gpio_direction_output(pic_gpios[i], 0); - if (ret < 0) { - gpio_free(pic_gpios[i]); + pic_gpios[i] = fwnode_gpiod_get_index(of_fwnode_handle(np), + "ctrl", i, GPIOD_OUT_HIGH, + name); + ret = PTR_ERR_OR_ZERO(pic_gpios[i]); + if (ret) { kfree(name); goto out; } @@ -118,7 +108,7 @@ static int __init mvebu_armada_pm_init(void) ret = of_parse_phandle_with_fixed_args(np, "ctrl-gpios", 2, i, &args); if (ret < 0) { - gpio_free(pic_gpios[i]); + gpiod_put(pic_gpios[i]); kfree(name); goto out; } diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index b6c7d98a9eff..4d46c56db38b 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -1135,65 +1135,6 @@ static struct omap_hwmod omap34xx_mcspi4 = { .class = &omap34xx_mcspi_class, }; -/* usbhsotg */ -static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = { - .rev_offs = 0x0400, - .sysc_offs = 0x0404, - .syss_offs = 0x0408, - .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE| - SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | - SYSC_HAS_AUTOIDLE), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, -}; - -static struct omap_hwmod_class usbotg_class = { - .name = "usbotg", - .sysc = &omap3xxx_usbhsotg_sysc, -}; - -/* usb_otg_hs */ - -static struct omap_hwmod omap3xxx_usbhsotg_hwmod = { - .name = "usb_otg_hs", - .main_clk = "hsotgusb_ick", - .prcm = { - .omap2 = { - .module_offs = CORE_MOD, - .idlest_reg_id = 1, - .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT, - }, - }, - .class = &usbotg_class, - - /* - * Erratum ID: i479 idle_req / idle_ack mechanism potentially - * broken when autoidle is enabled - * workaround is to disable the autoidle bit at module level. - * - * Enabling the device in any other MIDLEMODE setting but force-idle - * causes core_pwrdm not enter idle states at least on OMAP3630. - * Note that musb has OTG_FORCESTDBY register that controls MSTANDBY - * signal when MIDLEMODE is set to force-idle. - */ - .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE | - HWMOD_FORCE_MSTANDBY | HWMOD_RECONFIG_IO_CHAIN, -}; - -/* usb_otg_hs */ - -static struct omap_hwmod_class am35xx_usbotg_class = { - .name = "am35xx_usbotg", -}; - -static struct omap_hwmod am35xx_usbhsotg_hwmod = { - .name = "am35x_otg_hs", - .main_clk = "hsotgusb_fck", - .class = &am35xx_usbotg_class, - .flags = HWMOD_NO_IDLEST, -}; - /* MMC/SD/SDIO common */ static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = { .rev_offs = 0x1fc, @@ -1561,22 +1502,6 @@ static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* l3_core -> usbhsotg interface */ -static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = { - .master = &omap3xxx_usbhsotg_hwmod, - .slave = &omap3xxx_l3_main_hwmod, - .clk = "core_l3_ick", - .user = OCP_USER_MPU, -}; - -/* l3_core -> am35xx_usbhsotg interface */ -static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = { - .master = &am35xx_usbhsotg_hwmod, - .slave = &omap3xxx_l3_main_hwmod, - .clk = "hsotgusb_ick", - .user = OCP_USER_MPU, -}; - /* l3_core -> sad2d interface */ static struct omap_hwmod_ocp_if omap3xxx_sad2d__l3 = { .master = &omap3xxx_sad2d_hwmod, @@ -1758,24 +1683,6 @@ static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = { .user = OCP_USER_MPU, }; - -/* l4_core -> usbhsotg */ -static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &omap3xxx_usbhsotg_hwmod, - .clk = "l4_ick", - .user = OCP_USER_MPU, -}; - - -/* l4_core -> usbhsotg */ -static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = { - .master = &omap3xxx_l4_core_hwmod, - .slave = &am35xx_usbhsotg_hwmod, - .clk = "hsotgusb_ick", - .user = OCP_USER_MPU, -}; - /* L4_WKUP -> L4_SEC interface */ static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec = { .master = &omap3xxx_l4_wkup_hwmod, @@ -2465,8 +2372,6 @@ static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = { static struct omap_hwmod_ocp_if *omap3430es2plus_hwmod_ocp_ifs[] __initdata = { &omap3xxx_dss__l3, &omap3xxx_l4_core__dss, - &omap3xxx_usbhsotg__l3, - &omap3xxx_l4_core__usbhsotg, &omap3xxx_usb_host_hs__l3_main_2, &omap3xxx_l4_core__usb_host_hs, &omap3xxx_l4_core__usb_tll_hs, @@ -2509,8 +2414,6 @@ static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = { &omap3xxx_l4_core__dss, &omap36xx_l4_core__sr1, &omap36xx_l4_core__sr2, - &omap3xxx_usbhsotg__l3, - &omap3xxx_l4_core__usbhsotg, &omap3xxx_l4_core__mailbox, &omap3xxx_usb_host_hs__l3_main_2, &omap3xxx_l4_core__usb_host_hs, @@ -2528,8 +2431,6 @@ static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = { static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = { &omap3xxx_dss__l3, &omap3xxx_l4_core__dss, - &am35xx_usbhsotg__l3, - &am35xx_l4_core__usbhsotg, &am35xx_l4_core__uart4, &omap3xxx_usb_host_hs__l3_main_2, &omap3xxx_l4_core__usb_host_hs, diff --git a/arch/arm64/boot/dts/allwinner/axp803.dtsi b/arch/arm64/boot/dts/allwinner/axp803.dtsi index 578ef368e2b4..a6b4b87f185d 100644 --- a/arch/arm64/boot/dts/allwinner/axp803.dtsi +++ b/arch/arm64/boot/dts/allwinner/axp803.dtsi @@ -25,16 +25,6 @@ compatible = "x-powers,axp803-gpio", "x-powers,axp813-gpio"; gpio-controller; #gpio-cells = <2>; - - gpio0_ldo: gpio0-ldo-pin { - pins = "GPIO0"; - function = "ldo"; - }; - - gpio1_ldo: gpio1-ldo-pin { - pins = "GPIO1"; - function = "ldo"; - }; }; battery_power_supply: battery-power { diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts index 620cb3ef5f6c..50ed2e9f10ed 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts @@ -406,6 +406,20 @@ status = "okay"; }; +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "realtek,rtl8723cs-bt"; + device-wake-gpios = <&r_pio 0 5 GPIO_ACTIVE_LOW>; /* PL5 */ + enable-gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */ + host-wake-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ + }; +}; + &usb_otg { dr_mode = "host"; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts index 02893f3ac99d..cb8600d0ea1e 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts @@ -49,8 +49,24 @@ regulator-max-microvolt = <5000000>; regulator-always-on; }; + + reg_usb1_vbus: regulator-usb1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb1-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_vcc5v>; + enable-active-high; + gpio = <&pio 2 16 GPIO_ACTIVE_HIGH>; /* PC16 */ + }; }; +&ehci1 { + status = "okay"; +}; + +/* USB 2 & 3 are on headers only. */ + &emac0 { pinctrl-names = "default"; pinctrl-0 = <&ext_rgmii_pins>; @@ -76,6 +92,10 @@ status = "okay"; }; +&ohci1 { + status = "okay"; +}; + &r_rsb { status = "okay"; @@ -211,3 +231,24 @@ pinctrl-0 = <&uart0_ph_pins>; status = "okay"; }; + +&usbotg { + /* + * PHY0 pins are connected to a USB-C socket, but a role switch + * is not implemented: both CC pins are pulled to GND. + * The VBUS pins power the device, so a fixed peripheral mode + * is the best choice. + * The board can be powered via GPIOs, in this case port0 *can* + * act as a host (with a cable/adapter ignoring CC), as VBUS is + * then provided by the GPIOs. Any user of this setup would + * need to adjust the DT accordingly: dr_mode set to "host", + * enabling OHCI0 and EHCI0. + */ + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts index 6619db34714a..07424c28b696 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts @@ -32,6 +32,14 @@ }; }; +&ehci0 { + status = "okay"; +}; + +&ehci2 { + status = "okay"; +}; + &ir { status = "okay"; }; @@ -54,6 +62,14 @@ status = "okay"; }; +&ohci0 { + status = "okay"; +}; + +&ohci2 { + status = "okay"; +}; + &r_rsb { status = "okay"; @@ -175,3 +191,12 @@ pinctrl-0 = <&uart0_ph_pins>; status = "okay"; }; + +&usbotg { + dr_mode = "host"; /* USB A type receptable */ + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi index 622a1f7d1641..74aed0d232a9 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi @@ -504,6 +504,166 @@ }; }; + usbotg: usb@5100000 { + compatible = "allwinner,sun50i-h616-musb", + "allwinner,sun8i-h3-musb"; + reg = <0x05100000 0x0400>; + clocks = <&ccu CLK_BUS_OTG>; + resets = <&ccu RST_BUS_OTG>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mc"; + phys = <&usbphy 0>; + phy-names = "usb"; + extcon = <&usbphy 0>; + status = "disabled"; + }; + + usbphy: phy@5100400 { + compatible = "allwinner,sun50i-h616-usb-phy"; + reg = <0x05100400 0x24>, + <0x05101800 0x14>, + <0x05200800 0x14>, + <0x05310800 0x14>, + <0x05311800 0x14>; + reg-names = "phy_ctrl", + "pmu0", + "pmu1", + "pmu2", + "pmu3"; + clocks = <&ccu CLK_USB_PHY0>, + <&ccu CLK_USB_PHY1>, + <&ccu CLK_USB_PHY2>, + <&ccu CLK_USB_PHY3>, + <&ccu CLK_BUS_EHCI2>; + clock-names = "usb0_phy", + "usb1_phy", + "usb2_phy", + "usb3_phy", + "pmu2_clk"; + resets = <&ccu RST_USB_PHY0>, + <&ccu RST_USB_PHY1>, + <&ccu RST_USB_PHY2>, + <&ccu RST_USB_PHY3>; + reset-names = "usb0_reset", + "usb1_reset", + "usb2_reset", + "usb3_reset"; + status = "disabled"; + #phy-cells = <1>; + }; + + ehci0: usb@5101000 { + compatible = "allwinner,sun50i-h616-ehci", + "generic-ehci"; + reg = <0x05101000 0x100>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_OHCI0>, + <&ccu CLK_BUS_EHCI0>, + <&ccu CLK_USB_OHCI0>; + resets = <&ccu RST_BUS_OHCI0>, + <&ccu RST_BUS_EHCI0>; + phys = <&usbphy 0>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci0: usb@5101400 { + compatible = "allwinner,sun50i-h616-ohci", + "generic-ohci"; + reg = <0x05101400 0x100>; + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_OHCI0>, + <&ccu CLK_USB_OHCI0>; + resets = <&ccu RST_BUS_OHCI0>; + phys = <&usbphy 0>; + phy-names = "usb"; + status = "disabled"; + }; + + ehci1: usb@5200000 { + compatible = "allwinner,sun50i-h616-ehci", + "generic-ehci"; + reg = <0x05200000 0x100>; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_OHCI1>, + <&ccu CLK_BUS_EHCI1>, + <&ccu CLK_USB_OHCI1>; + resets = <&ccu RST_BUS_OHCI1>, + <&ccu RST_BUS_EHCI1>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci1: usb@5200400 { + compatible = "allwinner,sun50i-h616-ohci", + "generic-ohci"; + reg = <0x05200400 0x100>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_OHCI1>, + <&ccu CLK_USB_OHCI1>; + resets = <&ccu RST_BUS_OHCI1>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ehci2: usb@5310000 { + compatible = "allwinner,sun50i-h616-ehci", + "generic-ehci"; + reg = <0x05310000 0x100>; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_OHCI2>, + <&ccu CLK_BUS_EHCI2>, + <&ccu CLK_USB_OHCI2>; + resets = <&ccu RST_BUS_OHCI2>, + <&ccu RST_BUS_EHCI2>; + phys = <&usbphy 2>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci2: usb@5310400 { + compatible = "allwinner,sun50i-h616-ohci", + "generic-ohci"; + reg = <0x05310400 0x100>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_OHCI2>, + <&ccu CLK_USB_OHCI2>; + resets = <&ccu RST_BUS_OHCI2>; + phys = <&usbphy 2>; + phy-names = "usb"; + status = "disabled"; + }; + + ehci3: usb@5311000 { + compatible = "allwinner,sun50i-h616-ehci", + "generic-ehci"; + reg = <0x05311000 0x100>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_OHCI3>, + <&ccu CLK_BUS_EHCI3>, + <&ccu CLK_USB_OHCI3>; + resets = <&ccu RST_BUS_OHCI3>, + <&ccu RST_BUS_EHCI3>; + phys = <&usbphy 3>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci3: usb@5311400 { + compatible = "allwinner,sun50i-h616-ohci", + "generic-ohci"; + reg = <0x05311400 0x100>; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_OHCI3>, + <&ccu CLK_USB_OHCI3>; + resets = <&ccu RST_BUS_OHCI3>; + phys = <&usbphy 3>; + phy-names = "usb"; + status = "disabled"; + }; + rtc: rtc@7000000 { compatible = "allwinner,sun50i-h616-rtc"; reg = <0x07000000 0x400>; diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi index 14c220d87807..55c5e1fdddc7 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi @@ -309,6 +309,7 @@ <&clkmgr STRATIX10_SDMMC_CLK>; clock-names = "biu", "ciu"; iommus = <&smmu 5>; + altr,sysmgr-syscon = <&sysmgr 0x28 4>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts index 48424e459f12..17752ca743e5 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts @@ -22,17 +22,17 @@ leds { compatible = "gpio-leds"; - hps0 { + led-hps0 { label = "hps_led0"; gpios = <&portb 20 GPIO_ACTIVE_HIGH>; }; - hps1 { + led-hps1 { label = "hps_led1"; gpios = <&portb 19 GPIO_ACTIVE_HIGH>; }; - hps2 { + led-hps2 { label = "hps_led2"; gpios = <&portb 21 GPIO_ACTIVE_HIGH>; }; @@ -105,6 +105,7 @@ cap-mmc-highspeed; broken-cd; bus-width = <4>; + clk-phase-sd-hs = <0>, <135>; }; &osc1 { diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts index 847a7c01f5af..ede99dcc0558 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts @@ -22,17 +22,17 @@ leds { compatible = "gpio-leds"; - hps0 { + led-hps0 { label = "hps_led0"; gpios = <&portb 20 GPIO_ACTIVE_HIGH>; }; - hps1 { + led-hps1 { label = "hps_led1"; gpios = <&portb 19 GPIO_ACTIVE_HIGH>; }; - hps2 { + led-hps2 { label = "hps_led2"; gpios = <&portb 21 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile index e213aeebb774..97b42e2100e0 100644 --- a/arch/arm64/boot/dts/amlogic/Makefile +++ b/arch/arm64/boot/dts/amlogic/Makefile @@ -12,6 +12,7 @@ dtb-$(CONFIG_ARCH_MESON) += meson-g12b-a311d-khadas-vim3.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12b-gsking-x.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12b-gtking-pro.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12b-gtking.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-g12b-odroid-go-ultra.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12b-odroid-n2-plus.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12b-odroid-n2.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12b-s922x-khadas-vim3.dtb diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi index b4000cf65a9a..d2f7cb4e5375 100644 --- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi @@ -36,6 +36,7 @@ l2: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index 04f797b5a012..1648e67afbb6 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -105,6 +105,7 @@ l2: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi index 45947c1031c4..9dbd50820b1c 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi @@ -1705,6 +1705,12 @@ }; }; + pmu: pmu@ff638000 { + reg = <0x0 0xff638000 0x0 0x100>, + <0x0 0xff638c00 0x0 0x100>; + interrupts = <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>; + }; + aobus: bus@ff800000 { compatible = "simple-bus"; reg = <0x0 0xff800000 0x0 0x100000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi index fb0ab27d1f64..7677764eeee6 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi @@ -50,6 +50,7 @@ l2: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; }; @@ -133,3 +134,7 @@ }; }; }; + +&pmu { + compatible = "amlogic,g12a-ddr-pmu"; +}; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-go-ultra.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-go-ultra.dts new file mode 100644 index 000000000000..1e40709610c5 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-go-ultra.dts @@ -0,0 +1,722 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Neil Armstrong <neil.armstrong@linaro.org> + */ + +/dts-v1/; + +#include "meson-g12b-s922x.dtsi" +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/gpio/meson-g12a-gpio.h> +#include <dt-bindings/sound/meson-g12a-toacodec.h> +#include <dt-bindings/sound/meson-g12a-tohdmitx.h> + +/ { + compatible = "hardkernel,odroid-go-ultra", "amlogic,s922x", "amlogic,g12b"; + model = "Hardkernel ODROID-GO-Ultra"; + + aliases { + serial0 = &uart_AO; + rtc0 = &vrtc; + }; + + adc-joystick-left { + compatible = "adc-joystick"; + io-channels = <&saradc 2>, <&saradc 3>; + poll-interval = <10>; + #address-cells = <1>; + #size-cells = <0>; + + axis@0 { + reg = <0>; + linux,code = <ABS_Y>; + abs-range = <3150 950>; + abs-fuzz = <32>; + abs-flat = <64>; + }; + axis@1 { + reg = <1>; + linux,code = <ABS_X>; + abs-range = <700 2900>; + abs-fuzz = <32>; + abs-flat = <64>; + }; + }; + + adc-joystick-right { + compatible = "adc-joystick"; + io-channels = <&saradc 0>, <&saradc 1>; + poll-interval = <10>; + #address-cells = <1>; + #size-cells = <0>; + + axis@0 { + reg = <0>; + linux,code = <ABS_RY>; + abs-range = <3150 950>; + abs-fuzz = <32>; + abs-flat = <64>; + }; + axis@1 { + reg = <1>; + linux,code = <ABS_RX>; + abs-range = <800 3000>; + abs-fuzz = <32>; + abs-flat = <64>; + }; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + codec_clk: codec-clk { + compatible = "fixed-clock"; + clock-frequency = <12288000>; + clock-output-names = "codec_clk"; + #clock-cells = <0>; + }; + + gpio-keys { + compatible = "gpio-keys-polled"; + poll-interval = <10>; + pinctrl-0 = <&keypad_gpio_pins>; + pinctrl-names = "default"; + + volume-up-button { + label = "VOLUME-UP"; + linux,code = <KEY_VOLUMEUP>; + gpios = <&gpio GPIOX_8 GPIO_ACTIVE_LOW>; + }; + volume-down-button { + label = "VOLUME-DOWN"; + linux,code = <KEY_VOLUMEDOWN>; + gpios = <&gpio GPIOX_9 GPIO_ACTIVE_LOW>; + }; + dpad-up-button { + label = "DPAD-UP"; + linux,code = <BTN_DPAD_UP>; + gpios = <&gpio GPIOX_0 GPIO_ACTIVE_LOW>; + }; + dpad-down-button { + label = "DPAD-DOWN"; + linux,code = <BTN_DPAD_DOWN>; + gpios = <&gpio GPIOX_1 GPIO_ACTIVE_LOW>; + }; + dpad-left-button { + label = "DPAD-LEFT"; + linux,code = <BTN_DPAD_LEFT>; + gpios = <&gpio GPIOX_2 GPIO_ACTIVE_LOW>; + }; + dpad-right-button { + label = "DPAD-RIGHT"; + linux,code = <BTN_DPAD_RIGHT>; + gpios = <&gpio GPIOX_3 GPIO_ACTIVE_LOW>; + }; + a-button { + label = "A"; + linux,code = <BTN_EAST>; + gpios = <&gpio GPIOX_4 GPIO_ACTIVE_LOW>; + }; + b-button { + label = "B"; + linux,code = <BTN_SOUTH>; + gpios = <&gpio GPIOX_5 GPIO_ACTIVE_LOW>; + }; + y-button { + label = "Y"; + linux,code = <BTN_WEST>; + gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; + }; + x-button { + label = "X"; + linux,code = <BTN_NORTH>; + gpios = <&gpio GPIOX_7 GPIO_ACTIVE_LOW>; + }; + f1-button { + label = "F1"; + linux,code = <BTN_TRIGGER_HAPPY1>; + gpios = <&gpio GPIOX_17 GPIO_ACTIVE_LOW>; + }; + f2-button { + label = "F2"; + linux,code = <BTN_TRIGGER_HAPPY2>; + gpios = <&gpio GPIOX_10 GPIO_ACTIVE_LOW>; + }; + f3-button { + label = "F3"; + linux,code = <BTN_TRIGGER_HAPPY3>; + gpios = <&gpio GPIOX_11 GPIO_ACTIVE_LOW>; + }; + f4-button { + label = "F4"; + linux,code = <BTN_TRIGGER_HAPPY4>; + gpios = <&gpio GPIOX_12 GPIO_ACTIVE_LOW>; + }; + f5-button { + label = "F5"; + linux,code = <BTN_TRIGGER_HAPPY5>; + gpios = <&gpio GPIOX_13 GPIO_ACTIVE_LOW>; + }; + f6-button { + label = "F6"; + linux,code = <BTN_TRIGGER_HAPPY6>; + gpios = <&gpio GPIOX_16 GPIO_ACTIVE_LOW>; + }; + top-left-button { + label = "TOP Left"; + linux,code = <BTN_TL>; + gpios = <&gpio GPIOX_14 GPIO_ACTIVE_LOW>; + }; + top-left2-button { + label = "TOP Left 2"; + linux,code = <BTN_TL2>; + gpios = <&gpio GPIOX_19 GPIO_ACTIVE_LOW>; + }; + top-right-button { + label = "TOP Right"; + linux,code = <BTN_TR>; + gpios = <&gpio GPIOX_15 GPIO_ACTIVE_LOW>; + }; + top-right2-button { + label = "TOP Right 2"; + linux,code = <BTN_TR2>; + gpios = <&gpio GPIOX_18 GPIO_ACTIVE_LOW>; + }; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x40000000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; + }; + + leds { + compatible = "gpio-leds"; + + led-blue { + color = <LED_COLOR_ID_BLUE>; + gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + vdd_sys: regulator-vdd-sys { + compatible = "regulator-fixed"; + regulator-name = "VDD_SYS"; + regulator-min-microvolt = <3800000>; + regulator-max-microvolt = <3800000>; + regulator-always-on; + }; + + sound { + compatible = "amlogic,axg-sound-card"; + model = "Odroid GO Ultra"; + audio-widgets = "Microphone", "Mic Jack", + "Headphone", "Headphones", + "Speaker", "Internal Speakers"; + audio-aux-devs = <&tdmout_b>, <&tdmin_b>, <&speaker_amp>; + audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", + "TDM_B Playback", "TDMOUT_B OUT", + "TDMIN_B IN 1", "TDM_B Capture", + "TDMIN_B IN 4", "TDM_B Loopback", + "TODDR_A IN 1", "TDMIN_B OUT", + "MICL", "Mic Jack", + "Headphones", "HPOL", + "Headphones", "HPOR", + "Speaker Amplifier INL", "HPOL", + "Speaker Amplifier INR", "HPOR", + "Internal Speakers", "Speaker Amplifier OUTL", + "Internal Speakers", "Speaker Amplifier OUTR"; + + assigned-clocks = <&clkc CLKID_MPLL2>, + <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>; + assigned-clock-parents = <0>, <0>, <0>; + assigned-clock-rates = <294912000>, + <270950400>, + <393216000>; + + dai-link-0 { + sound-dai = <&frddr_a>; + }; + + dai-link-1 { + sound-dai = <&toddr_a>; + }; + + dai-link-2 { + sound-dai = <&tdmif_b>; + dai-format = "i2s"; + dai-tdm-slot-tx-mask-0 = <1 1>; + mclk-fs = <256>; + + codec-0 { + sound-dai = <&rk817>; + }; + }; + }; + + speaker_amp: speaker-amplifier { + compatible = "simple-audio-amplifier"; + sound-name-prefix = "Speaker Amplifier"; + VCC-supply = <&hp_5v>; + }; +}; + +&arb { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vddcpu_b>; + operating-points-v2 = <&cpu_opp_table_0>; + clocks = <&clkc CLKID_CPU_CLK>; + clock-latency = <50000>; +}; + +&cpu1 { + cpu-supply = <&vddcpu_b>; + operating-points-v2 = <&cpu_opp_table_0>; + clocks = <&clkc CLKID_CPU_CLK>; + clock-latency = <50000>; +}; + +&cpu100 { + cpu-supply = <&vddcpu_a>; + operating-points-v2 = <&cpub_opp_table_1>; + clocks = <&clkc CLKID_CPUB_CLK>; + clock-latency = <50000>; +}; + +&cpu101 { + cpu-supply = <&vddcpu_a>; + operating-points-v2 = <&cpub_opp_table_1>; + clocks = <&clkc CLKID_CPUB_CLK>; + clock-latency = <50000>; +}; + +&cpu102 { + cpu-supply = <&vddcpu_a>; + operating-points-v2 = <&cpub_opp_table_1>; + clocks = <&clkc CLKID_CPUB_CLK>; + clock-latency = <50000>; +}; + +&cpu103 { + cpu-supply = <&vddcpu_a>; + operating-points-v2 = <&cpub_opp_table_1>; + clocks = <&clkc CLKID_CPUB_CLK>; + clock-latency = <50000>; +}; + +/* RK817 only supports 12.5mV steps, round up the values */ +&cpu_opp_table_0 { + opp-1000000000 { + opp-microvolt = <737500>; + }; + opp-1200000000 { + opp-microvolt = <737500>; + }; + opp-1398000000 { + opp-microvolt = <762500>; + }; + opp-1512000000 { + opp-microvolt = <800000>; + }; + opp-1608000000 { + opp-microvolt = <837500>; + }; + opp-1704000000 { + opp-microvolt = <862500>; + }; + opp-1896000000 { + opp-microvolt = <987500>; + }; + opp-1992000000 { + opp-microvolt = <1012500>; + }; +}; + +/* RK818 only supports 12.5mV steps, round up the values */ +&cpub_opp_table_1 { + opp-1000000000 { + opp-microvolt = <775000>; + }; + opp-1200000000 { + opp-microvolt = <775000>; + }; + opp-1398000000 { + opp-microvolt = <800000>; + }; + opp-1512000000 { + opp-microvolt = <825000>; + }; + opp-1608000000 { + opp-microvolt = <862500>; + }; + opp-1704000000 { + opp-microvolt = <900000>; + }; + opp-1800000000 { + opp-microvolt = <987500>; + }; + opp-1908000000 { + opp-microvolt = <1025000>; + }; +}; + +&i2c_AO { + status = "okay"; + pinctrl-0 = <&i2c_ao_sck_pins>, <&i2c_ao_sda_pins>; + pinctrl-names = "default"; + + rk818: pmic@1c { + compatible = "rockchip,rk818"; + reg = <0x1c>; + interrupt-parent = <&gpio_intc>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; /* GPIOAO_7 */ + + vcc1-supply = <&vdd_sys>; + vcc2-supply = <&vdd_sys>; + vcc3-supply = <&vdd_sys>; + vcc4-supply = <&vdd_sys>; + vcc6-supply = <&vdd_sys>; + vcc7-supply = <&vcc_2v3>; + vcc8-supply = <&vcc_2v3>; + vcc9-supply = <&vddao_3v3>; + boost-supply = <&vdd_sys>; + switch-supply = <&vdd_sys>; + + regulators { + vddcpu_a: DCDC_REG1 { + regulator-name = "vddcpu_a"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <775000>; + regulator-max-microvolt = <1025000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <775000>; + }; + }; + + vdd_ee: DCDC_REG2 { + regulator-name = "vdd_ee"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <875000>; + regulator-max-microvolt = <1250000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <875000>; + }; + }; + + vddq_1v1: DCDC_REG3 { + regulator-name = "vddq_1v1"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vddao_3v3: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vddao_3v3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + hp_5v: DCDC_BOOST { + regulator-always-on; + regulator-boot-on; + regulator-name = "hp_5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vddio_ao1v8: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vddio_ao1v8"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vddq_1v8: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vddq_1v8"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vddio_c: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vddio_c"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_sd: SWITCH_REG { + regulator-name = "vcc_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + OTG_SWITCH { + regulator-name = "otg_switch"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&i2c3 { + status = "okay"; + pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>; + pinctrl-names = "default"; + + rk817: pmic@20 { + compatible = "rockchip,rk817"; + reg = <0x20>; + interrupt-parent = <&gpio_intc>; + + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; /* GPIOAO_5 */ + + vcc1-supply = <&vdd_sys>; + vcc2-supply = <&vdd_sys>; + vcc3-supply = <&vdd_sys>; + vcc4-supply = <&vdd_sys>; + vcc5-supply = <&vdd_sys>; + vcc6-supply = <&vdd_sys>; + vcc7-supply = <&vdd_sys>; + vcc8-supply = <&vdd_sys>; + vcc9-supply = <&rk817_boost>; + + #sound-dai-cells = <0>; + clocks = <&codec_clk>; + clock-names = "mclk"; + + #clock-cells = <1>; + + regulators { + vddcpu_b: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <737500>; + regulator-max-microvolt = <1012500>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vddcpu_b"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_2v3: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2300000>; + regulator-max-microvolt = <2400000>; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_2v3"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vdd_codec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_lcd: LDO_REG8 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_lcd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk817_boost: BOOST { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5400000>; + regulator-name = "rk817_boost"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + usb_host: OTG_SWITCH { + regulator-name = "usb_host"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&clkc_audio { + status = "okay"; +}; + +ð_phy { + status = "disabled"; +}; + +&frddr_a { + status = "okay"; +}; + +&periphs_pinctrl { + keypad_gpio_pins: keypad-gpio { + mux { + groups = "GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", + "GPIOX_4", "GPIOX_5", "GPIOX_6", "GPIOX_7", + "GPIOX_8", "GPIOX_9", "GPIOX_10", "GPIOX_11", + "GPIOX_12", "GPIOX_13", "GPIOX_14", "GPIOX_15", + "GPIOX_16", "GPIOX_17", "GPIOX_18", "GPIOX_19"; + function = "gpio_periphs"; + bias-pull-up; + output-disable; + }; + }; +}; + +&saradc { + status = "okay"; + vref-supply = <&vddio_ao1v8>; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_c_pins>; + pinctrl-1 = <&sdcard_clk_gate_c_pins>; + pinctrl-names = "default", "clk-gate"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <50000000>; + disable-wp; + + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; + vmmc-supply = <&vcc_sd>; + vqmmc-supply = <&vddio_c>; + +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; + pinctrl-1 = <&emmc_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; + + bus-width = <8>; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + max-frequency = <200000000>; + disable-wp; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_sd>; + vqmmc-supply = <&vddio_ao1v8>; +}; + + +&tdmif_b { + pinctrl-0 = <&tdm_b_dout0_pins>, <&tdm_b_fs_pins>, <&tdm_b_sclk_pins>, <&tdm_b_din1_pins>; + pinctrl-names = "default"; + status = "okay"; + + assigned-clocks = <&clkc_audio AUD_CLKID_TDM_SCLK_PAD1>, + <&clkc_audio AUD_CLKID_TDM_LRCLK_PAD1>; + assigned-clock-parents = <&clkc_audio AUD_CLKID_MST_B_SCLK>, + <&clkc_audio AUD_CLKID_MST_B_LRCLK>; + assigned-clock-rates = <0>, <0>; +}; + +&tdmin_b { + status = "okay"; +}; + +&tdmout_b { + status = "okay"; +}; + +&toddr_a { + status = "okay"; +}; + +&uart_AO { + status = "okay"; + pinctrl-0 = <&uart_ao_a_pins>; + pinctrl-names = "default"; +}; + +&usb { + status = "okay"; + dr_mode = "peripheral"; +}; + +&usb2_phy0 { + status = "okay"; +}; + +&usb2_phy1 { + status = "okay"; + phy-supply = <&usb_host>; +}; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi index fd3fa82e4c33..667d2b774924 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi @@ -39,6 +39,14 @@ reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; }; + fan: gpio-fan { + compatible = "gpio-fan"; + gpios = <&gpio_ao GPIOAO_10 GPIO_ACTIVE_HIGH>; + /* Using Dummy Speed */ + gpio-fan,speed-map = <0 0>, <1 1>; + #cooling-cells = <2>; + }; + leds { compatible = "gpio-leds"; @@ -410,6 +418,40 @@ clock-latency = <50000>; }; +&cpu_thermal { + trips { + cpu_active: cpu-active { + temperature = <60000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + }; + + cooling-maps { + map { + trip = <&cpu_active>; + cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; +}; + +&ddr_thermal { + trips { + ddr_active: ddr-active { + temperature = <60000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + }; + + cooling-maps { + map { + trip = <&ddr_active>; + cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; +}; + &ext_mdio { external_phy: ethernet-phy@0 { /* Realtek RTL8211F (0x001cc916) */ diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi index ee8fcae9f9f0..75ff00fb2e4c 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi @@ -105,6 +105,7 @@ l2: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; }; }; @@ -139,3 +140,7 @@ &mali { dma-coherent; }; + +&pmu { + compatible = "amlogic,g12b-ddr-pmu"; +}; diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi index 023a52005494..e3c12e0be99d 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi @@ -132,6 +132,7 @@ l2: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi index 7c029f552a23..923d2d8bbb9c 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi @@ -427,6 +427,20 @@ }; }; + spi_idle_high_pins: spi-idle-high-pins { + mux { + groups = "spi_sclk"; + bias-pull-up; + }; + }; + + spi_idle_low_pins: spi-idle-low-pins { + mux { + groups = "spi_sclk"; + bias-pull-down; + }; + }; + spi_ss0_pins: spi-ss0 { mux { groups = "spi_ss0"; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts index 6ab1cc125b96..202deb4e2d63 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts @@ -140,7 +140,6 @@ compatible = "haoyu,hym8563"; reg = <0x51>; #clock-cells = <0>; - clock-frequency = <32768>; clock-output-names = "xin32k"; }; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi index c3ac531c4f84..04e9d0f1bde0 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi @@ -429,6 +429,20 @@ }; }; + spi_idle_high_pins: spi-idle-high-pins { + mux { + groups = "spi_sclk"; + bias-pull-up; + }; + }; + + spi_idle_low_pins: spi-idle-low-pins { + mux { + groups = "spi_sclk"; + bias-pull-down; + }; + }; + spi_ss0_pins: spi-ss0 { mux { groups = "spi_ss0"; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts index f43c45daf7eb..b21172ece1fa 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts @@ -270,7 +270,6 @@ compatible = "haoyu,hym8563"; reg = <0x51>; #clock-cells = <0>; - clock-frequency = <32768>; clock-output-names = "xin32k"; }; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-minix-neo-u9h.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-minix-neo-u9h.dts index b8ef3bd8b840..1703da3235ea 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxm-minix-neo-u9h.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxm-minix-neo-u9h.dts @@ -89,7 +89,6 @@ compatible = "haoyu,hym8563"; reg = <0x51>; #clock-cells = <0>; - clock-frequency = <32768>; clock-output-names = "xin32k"; wakeup-source; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi index 80737731af3f..56ca0ba2241e 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi @@ -88,6 +88,7 @@ l2: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; }; @@ -520,6 +521,10 @@ power-domains = <&pwrc PWRC_SM1_PCIE_ID>; }; +&pmu { + compatible = "amlogic,sm1-ddr-pmu"; +}; + &pwrc { compatible = "amlogic,meson-sm1-pwrc"; }; diff --git a/arch/arm64/boot/dts/apple/Makefile b/arch/arm64/boot/dts/apple/Makefile index c0510c25ca6a..5a7506ff5ea3 100644 --- a/arch/arm64/boot/dts/apple/Makefile +++ b/arch/arm64/boot/dts/apple/Makefile @@ -4,3 +4,9 @@ dtb-$(CONFIG_ARCH_APPLE) += t8103-j293.dtb dtb-$(CONFIG_ARCH_APPLE) += t8103-j313.dtb dtb-$(CONFIG_ARCH_APPLE) += t8103-j456.dtb dtb-$(CONFIG_ARCH_APPLE) += t8103-j457.dtb +dtb-$(CONFIG_ARCH_APPLE) += t6000-j314s.dtb +dtb-$(CONFIG_ARCH_APPLE) += t6001-j314c.dtb +dtb-$(CONFIG_ARCH_APPLE) += t6000-j316s.dtb +dtb-$(CONFIG_ARCH_APPLE) += t6001-j316c.dtb +dtb-$(CONFIG_ARCH_APPLE) += t6001-j375c.dtb +dtb-$(CONFIG_ARCH_APPLE) += t6002-j375d.dtb diff --git a/arch/arm64/boot/dts/apple/multi-die-cpp.h b/arch/arm64/boot/dts/apple/multi-die-cpp.h new file mode 100644 index 000000000000..39e8953bf809 --- /dev/null +++ b/arch/arm64/boot/dts/apple/multi-die-cpp.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0+ OR MIT + * + * C preprocessor macros for t600x multi die support. + */ + +#ifndef __DTS_APPLE_MULTI_DIE_CPP_H +#define __DTS_APPLE_MULTI_DIE_CPP_H + +#ifndef __stringify +#define __stringify_1(x...) #x +#define __stringify(x...) __stringify_1(x) +#endif + +#ifndef __concat +#define __concat_1(x, y...) x ## y +#define __concat(x, y...) __concat_1(x, y) +#endif + +#define DIE_NODE(a) __concat(a, DIE) +#define DIE_LABEL(a) __stringify(__concat(a, DIE)) + +#endif /* !__DTS_APPLE_MULTI_DIE_CPP_H */ diff --git a/arch/arm64/boot/dts/apple/t6000-j314s.dts b/arch/arm64/boot/dts/apple/t6000-j314s.dts new file mode 100644 index 000000000000..c9e192848fe3 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t6000-j314s.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * MacBook Pro (14-inch, M1 Pro, 2021) + * + * target-type: J314s + * + * Copyright The Asahi Linux Contributors + */ + +/dts-v1/; + +#include "t6000.dtsi" +#include "t600x-j314-j316.dtsi" + +/ { + compatible = "apple,j314s", "apple,t6000", "apple,arm-platform"; + model = "Apple MacBook Pro (14-inch, M1 Pro, 2021)"; +}; diff --git a/arch/arm64/boot/dts/apple/t6000-j316s.dts b/arch/arm64/boot/dts/apple/t6000-j316s.dts new file mode 100644 index 000000000000..ff1803ce2300 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t6000-j316s.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * MacBook Pro (16-inch, M1 Pro, 2021) + * + * target-type: J316s + * + * Copyright The Asahi Linux Contributors + */ + +/dts-v1/; + +#include "t6000.dtsi" +#include "t600x-j314-j316.dtsi" + +/ { + compatible = "apple,j316s", "apple,t6000", "apple,arm-platform"; + model = "Apple MacBook Pro (16-inch, M1 Pro, 2021)"; +}; diff --git a/arch/arm64/boot/dts/apple/t6000.dtsi b/arch/arm64/boot/dts/apple/t6000.dtsi new file mode 100644 index 000000000000..89c3b211b116 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t6000.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T6000 "M1 Pro" SoC + * + * Other names: H13J, "Jade Chop" + * + * Copyright The Asahi Linux Contributors + */ + +/* This chip is just a cut down version of t6001, so include it and disable the missing parts */ + +#include "t6001.dtsi" + +/ { + compatible = "apple,t6000", "apple,arm-platform"; +}; + +/delete-node/ &pmgr_south; diff --git a/arch/arm64/boot/dts/apple/t6001-j314c.dts b/arch/arm64/boot/dts/apple/t6001-j314c.dts new file mode 100644 index 000000000000..1761d15b98c1 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t6001-j314c.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * MacBook Pro (14-inch, M1 Max, 2021) + * + * target-type: J314c + * + * Copyright The Asahi Linux Contributors + */ + +/dts-v1/; + +#include "t6001.dtsi" +#include "t600x-j314-j316.dtsi" + +/ { + compatible = "apple,j314c", "apple,t6001", "apple,arm-platform"; + model = "Apple MacBook Pro (14-inch, M1 Max, 2021)"; +}; diff --git a/arch/arm64/boot/dts/apple/t6001-j316c.dts b/arch/arm64/boot/dts/apple/t6001-j316c.dts new file mode 100644 index 000000000000..750e9beeffc0 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t6001-j316c.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * MacBook Pro (16-inch, M1 Max, 2021) + * + * target-type: J316c + * + * Copyright The Asahi Linux Contributors + */ + +/dts-v1/; + +#include "t6001.dtsi" +#include "t600x-j314-j316.dtsi" + +/ { + compatible = "apple,j316c", "apple,t6001", "apple,arm-platform"; + model = "Apple MacBook Pro (16-inch, M1 Max, 2021)"; +}; diff --git a/arch/arm64/boot/dts/apple/t6001-j375c.dts b/arch/arm64/boot/dts/apple/t6001-j375c.dts new file mode 100644 index 000000000000..62ea437b58b2 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t6001-j375c.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Mac Studio (M1 Max, 2022) + * + * target-type: J375c + * + * Copyright The Asahi Linux Contributors + */ + +/dts-v1/; + +#include "t6001.dtsi" +#include "t600x-j375.dtsi" + +/ { + compatible = "apple,j375c", "apple,t6001", "apple,arm-platform"; + model = "Apple Mac Studio (M1 Max, 2022)"; +}; diff --git a/arch/arm64/boot/dts/apple/t6001.dtsi b/arch/arm64/boot/dts/apple/t6001.dtsi new file mode 100644 index 000000000000..620b17e4031f --- /dev/null +++ b/arch/arm64/boot/dts/apple/t6001.dtsi @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T6001 "M1 Max" SoC + * + * Other names: H13J, "Jade" + * + * Copyright The Asahi Linux Contributors + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/apple-aic.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pinctrl/apple.h> + +#include "multi-die-cpp.h" + +#include "t600x-common.dtsi" + +/ { + compatible = "apple,t6001", "apple,arm-platform"; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + + ranges; + nonposted-mmio; + + // filled via templated includes at the end of the file + }; +}; + +#define DIE +#define DIE_NO 0 + +&{/soc} { + #include "t600x-die0.dtsi" + #include "t600x-dieX.dtsi" + #include "t600x-nvme.dtsi" +}; + +#include "t600x-gpio-pins.dtsi" +#include "t600x-pmgr.dtsi" + +#undef DIE +#undef DIE_NO + + +&aic { + affinities { + e-core-pmu-affinity { + apple,fiq-index = <AIC_CPU_PMU_E>; + cpus = <&cpu_e00 &cpu_e01>; + }; + + p-core-pmu-affinity { + apple,fiq-index = <AIC_CPU_PMU_P>; + cpus = <&cpu_p00 &cpu_p01 &cpu_p02 &cpu_p03 + &cpu_p10 &cpu_p11 &cpu_p12 &cpu_p13>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/apple/t6002-j375d.dts b/arch/arm64/boot/dts/apple/t6002-j375d.dts new file mode 100644 index 000000000000..3365429bdc8b --- /dev/null +++ b/arch/arm64/boot/dts/apple/t6002-j375d.dts @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Mac Studio (M1 Ultra, 2022) + * + * target-type: J375d + * + * Copyright The Asahi Linux Contributors + */ + +/dts-v1/; + +#include "t6002.dtsi" +#include "t600x-j375.dtsi" + +/ { + compatible = "apple,j375d", "apple,t6002", "apple,arm-platform"; + model = "Apple Mac Studio (M1 Ultra, 2022)"; +}; + +/* USB Type C */ +&i2c0 { + /* front-right */ + hpm4: usb-pd@39 { + compatible = "apple,cd321x"; + reg = <0x39>; + interrupt-parent = <&pinctrl_ap>; + interrupts = <174 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "irq"; + }; + + /* front-left */ + hpm5: usb-pd@3a { + compatible = "apple,cd321x"; + reg = <0x3a>; + interrupt-parent = <&pinctrl_ap>; + interrupts = <174 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "irq"; + }; +}; + +/* delete unused always-on power-domains on die 1 */ + +/delete-node/ &ps_atc2_usb_aon_die1; +/delete-node/ &ps_atc2_usb_die1; + +/delete-node/ &ps_atc3_usb_aon_die1; +/delete-node/ &ps_atc3_usb_die1; + +/delete-node/ &ps_disp0_cpu0_die1; +/delete-node/ &ps_disp0_fe_die1; diff --git a/arch/arm64/boot/dts/apple/t6002.dtsi b/arch/arm64/boot/dts/apple/t6002.dtsi new file mode 100644 index 000000000000..15da2c7eb1fe --- /dev/null +++ b/arch/arm64/boot/dts/apple/t6002.dtsi @@ -0,0 +1,296 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T6002 "M1 Ultra" SoC + * + * Other names: H13J, "Jade 2C" + * + * Copyright The Asahi Linux Contributors + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/apple-aic.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pinctrl/apple.h> + +#include "multi-die-cpp.h" + +#include "t600x-common.dtsi" + +/ { + compatible = "apple,t6002", "apple,arm-platform"; + + #address-cells = <2>; + #size-cells = <2>; + + cpus { + cpu-map { + cluster3 { + core0 { + cpu = <&cpu_e10>; + }; + core1 { + cpu = <&cpu_e11>; + }; + }; + + cluster4 { + core0 { + cpu = <&cpu_p20>; + }; + core1 { + cpu = <&cpu_p21>; + }; + core2 { + cpu = <&cpu_p22>; + }; + core3 { + cpu = <&cpu_p23>; + }; + }; + + cluster5 { + core0 { + cpu = <&cpu_p30>; + }; + core1 { + cpu = <&cpu_p31>; + }; + core2 { + cpu = <&cpu_p32>; + }; + core3 { + cpu = <&cpu_p33>; + }; + }; + }; + + cpu_e10: cpu@800 { + compatible = "apple,icestorm"; + device_type = "cpu"; + reg = <0x0 0x800>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_3>; + i-cache-size = <0x20000>; + d-cache-size = <0x10000>; + operating-points-v2 = <&icestorm_opp>; + capacity-dmips-mhz = <714>; + performance-domains = <&cpufreq_e_die1>; + }; + + cpu_e11: cpu@801 { + compatible = "apple,icestorm"; + device_type = "cpu"; + reg = <0x0 0x801>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_3>; + i-cache-size = <0x20000>; + d-cache-size = <0x10000>; + operating-points-v2 = <&icestorm_opp>; + capacity-dmips-mhz = <714>; + performance-domains = <&cpufreq_e_die1>; + }; + + cpu_p20: cpu@10900 { + compatible = "apple,firestorm"; + device_type = "cpu"; + reg = <0x0 0x10900>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_4>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + operating-points-v2 = <&firestorm_opp>; + capacity-dmips-mhz = <1024>; + performance-domains = <&cpufreq_p0_die1>; + }; + + cpu_p21: cpu@10901 { + compatible = "apple,firestorm"; + device_type = "cpu"; + reg = <0x0 0x10901>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_4>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + operating-points-v2 = <&firestorm_opp>; + capacity-dmips-mhz = <1024>; + performance-domains = <&cpufreq_p0_die1>; + }; + + cpu_p22: cpu@10902 { + compatible = "apple,firestorm"; + device_type = "cpu"; + reg = <0x0 0x10902>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_4>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + operating-points-v2 = <&firestorm_opp>; + capacity-dmips-mhz = <1024>; + performance-domains = <&cpufreq_p0_die1>; + }; + + cpu_p23: cpu@10903 { + compatible = "apple,firestorm"; + device_type = "cpu"; + reg = <0x0 0x10903>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_4>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + operating-points-v2 = <&firestorm_opp>; + capacity-dmips-mhz = <1024>; + performance-domains = <&cpufreq_p0_die1>; + }; + + cpu_p30: cpu@10a00 { + compatible = "apple,firestorm"; + device_type = "cpu"; + reg = <0x0 0x10a00>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_5>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + operating-points-v2 = <&firestorm_opp>; + capacity-dmips-mhz = <1024>; + performance-domains = <&cpufreq_p1_die1>; + }; + + cpu_p31: cpu@10a01 { + compatible = "apple,firestorm"; + device_type = "cpu"; + reg = <0x0 0x10a01>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_5>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + operating-points-v2 = <&firestorm_opp>; + capacity-dmips-mhz = <1024>; + performance-domains = <&cpufreq_p1_die1>; + }; + + cpu_p32: cpu@10a02 { + compatible = "apple,firestorm"; + device_type = "cpu"; + reg = <0x0 0x10a02>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_5>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + operating-points-v2 = <&firestorm_opp>; + capacity-dmips-mhz = <1024>; + performance-domains = <&cpufreq_p1_die1>; + }; + + cpu_p33: cpu@10a03 { + compatible = "apple,firestorm"; + device_type = "cpu"; + reg = <0x0 0x10a03>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_5>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + operating-points-v2 = <&firestorm_opp>; + capacity-dmips-mhz = <1024>; + performance-domains = <&cpufreq_p1_die1>; + }; + + l2_cache_3: l2-cache-3 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x400000>; + }; + + l2_cache_4: l2-cache-4 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0xc00000>; + }; + + l2_cache_5: l2-cache-5 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0xc00000>; + }; + }; + + die0: soc@200000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x2 0x0 0x2 0x0 0x4 0x0>, + <0x5 0x80000000 0x5 0x80000000 0x1 0x80000000>, + <0x7 0x0 0x7 0x0 0xf 0x80000000>; + nonposted-mmio; + + // filled via templated includes at the end of the file + }; + + die1: soc@2200000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x2 0x0 0x22 0x0 0x4 0x0>, + <0x7 0x0 0x27 0x0 0xf 0x80000000>; + nonposted-mmio; + + // filled via templated includes at the end of the file + }; +}; + +#define DIE +#define DIE_NO 0 + +&die0 { + #include "t600x-die0.dtsi" + #include "t600x-dieX.dtsi" +}; + +#include "t600x-pmgr.dtsi" +#include "t600x-gpio-pins.dtsi" + +#undef DIE +#undef DIE_NO + +#define DIE _die1 +#define DIE_NO 1 + +&die1 { + #include "t600x-dieX.dtsi" + #include "t600x-nvme.dtsi" +}; + +#include "t600x-pmgr.dtsi" + +#undef DIE +#undef DIE_NO + +&aic { + affinities { + e-core-pmu-affinity { + apple,fiq-index = <AIC_CPU_PMU_E>; + cpus = <&cpu_e00 &cpu_e01 + &cpu_e10 &cpu_e11>; + }; + + p-core-pmu-affinity { + apple,fiq-index = <AIC_CPU_PMU_P>; + cpus = <&cpu_p00 &cpu_p01 &cpu_p02 &cpu_p03 + &cpu_p10 &cpu_p11 &cpu_p12 &cpu_p13 + &cpu_p20 &cpu_p21 &cpu_p22 &cpu_p23 + &cpu_p30 &cpu_p31 &cpu_p32 &cpu_p33>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/apple/t600x-common.dtsi b/arch/arm64/boot/dts/apple/t600x-common.dtsi new file mode 100644 index 000000000000..fa8ead699363 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t600x-common.dtsi @@ -0,0 +1,374 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Common Apple T6000 / T6001 / T6002 "M1 Pro/Max/Ultra" SoC + * + * Other names: H13J, "Jade Chop", "Jade", "Jade 2C" + * + * Copyright The Asahi Linux Contributors + */ + +/ { + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu_e00>; + }; + core1 { + cpu = <&cpu_e01>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu_p00>; + }; + core1 { + cpu = <&cpu_p01>; + }; + core2 { + cpu = <&cpu_p02>; + }; + core3 { + cpu = <&cpu_p03>; + }; + }; + + cluster2 { + core0 { + cpu = <&cpu_p10>; + }; + core1 { + cpu = <&cpu_p11>; + }; + core2 { + cpu = <&cpu_p12>; + }; + core3 { + cpu = <&cpu_p13>; + }; + }; + }; + + cpu_e00: cpu@0 { + compatible = "apple,icestorm"; + device_type = "cpu"; + reg = <0x0 0x0>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_0>; + i-cache-size = <0x20000>; + d-cache-size = <0x10000>; + operating-points-v2 = <&icestorm_opp>; + capacity-dmips-mhz = <714>; + performance-domains = <&cpufreq_e>; + }; + + cpu_e01: cpu@1 { + compatible = "apple,icestorm"; + device_type = "cpu"; + reg = <0x0 0x1>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_0>; + i-cache-size = <0x20000>; + d-cache-size = <0x10000>; + operating-points-v2 = <&icestorm_opp>; + capacity-dmips-mhz = <714>; + performance-domains = <&cpufreq_e>; + }; + + cpu_p00: cpu@10100 { + compatible = "apple,firestorm"; + device_type = "cpu"; + reg = <0x0 0x10100>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_1>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + operating-points-v2 = <&firestorm_opp>; + capacity-dmips-mhz = <1024>; + performance-domains = <&cpufreq_p0>; + }; + + cpu_p01: cpu@10101 { + compatible = "apple,firestorm"; + device_type = "cpu"; + reg = <0x0 0x10101>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_1>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + operating-points-v2 = <&firestorm_opp>; + capacity-dmips-mhz = <1024>; + performance-domains = <&cpufreq_p0>; + }; + + cpu_p02: cpu@10102 { + compatible = "apple,firestorm"; + device_type = "cpu"; + reg = <0x0 0x10102>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_1>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + operating-points-v2 = <&firestorm_opp>; + capacity-dmips-mhz = <1024>; + performance-domains = <&cpufreq_p0>; + }; + + cpu_p03: cpu@10103 { + compatible = "apple,firestorm"; + device_type = "cpu"; + reg = <0x0 0x10103>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_1>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + operating-points-v2 = <&firestorm_opp>; + capacity-dmips-mhz = <1024>; + performance-domains = <&cpufreq_p0>; + }; + + cpu_p10: cpu@10200 { + compatible = "apple,firestorm"; + device_type = "cpu"; + reg = <0x0 0x10200>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_2>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + operating-points-v2 = <&firestorm_opp>; + capacity-dmips-mhz = <1024>; + performance-domains = <&cpufreq_p1>; + }; + + cpu_p11: cpu@10201 { + compatible = "apple,firestorm"; + device_type = "cpu"; + reg = <0x0 0x10201>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_2>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + operating-points-v2 = <&firestorm_opp>; + capacity-dmips-mhz = <1024>; + performance-domains = <&cpufreq_p1>; + }; + + cpu_p12: cpu@10202 { + compatible = "apple,firestorm"; + device_type = "cpu"; + reg = <0x0 0x10202>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_2>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + operating-points-v2 = <&firestorm_opp>; + capacity-dmips-mhz = <1024>; + performance-domains = <&cpufreq_p1>; + }; + + cpu_p13: cpu@10203 { + compatible = "apple,firestorm"; + device_type = "cpu"; + reg = <0x0 0x10203>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_2>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + operating-points-v2 = <&firestorm_opp>; + capacity-dmips-mhz = <1024>; + performance-domains = <&cpufreq_p1>; + }; + + l2_cache_0: l2-cache-0 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x400000>; + }; + + l2_cache_1: l2-cache-1 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0xc00000>; + }; + + l2_cache_2: l2-cache-2 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0xc00000>; + }; + }; + + icestorm_opp: opp-table-0 { + compatible = "operating-points-v2"; + + opp01 { + opp-hz = /bits/ 64 <600000000>; + opp-level = <1>; + clock-latency-ns = <7500>; + }; + opp02 { + opp-hz = /bits/ 64 <972000000>; + opp-level = <2>; + clock-latency-ns = <23000>; + }; + opp03 { + opp-hz = /bits/ 64 <1332000000>; + opp-level = <3>; + clock-latency-ns = <29000>; + }; + opp04 { + opp-hz = /bits/ 64 <1704000000>; + opp-level = <4>; + clock-latency-ns = <40000>; + }; + opp05 { + opp-hz = /bits/ 64 <2064000000>; + opp-level = <5>; + clock-latency-ns = <50000>; + }; + }; + + firestorm_opp: opp-table-1 { + compatible = "operating-points-v2"; + + opp01 { + opp-hz = /bits/ 64 <600000000>; + opp-level = <1>; + clock-latency-ns = <8000>; + }; + opp02 { + opp-hz = /bits/ 64 <828000000>; + opp-level = <2>; + clock-latency-ns = <18000>; + }; + opp03 { + opp-hz = /bits/ 64 <1056000000>; + opp-level = <3>; + clock-latency-ns = <19000>; + }; + opp04 { + opp-hz = /bits/ 64 <1296000000>; + opp-level = <4>; + clock-latency-ns = <23000>; + }; + opp05 { + opp-hz = /bits/ 64 <1524000000>; + opp-level = <5>; + clock-latency-ns = <24000>; + }; + opp06 { + opp-hz = /bits/ 64 <1752000000>; + opp-level = <6>; + clock-latency-ns = <28000>; + }; + opp07 { + opp-hz = /bits/ 64 <1980000000>; + opp-level = <7>; + clock-latency-ns = <31000>; + }; + opp08 { + opp-hz = /bits/ 64 <2208000000>; + opp-level = <8>; + clock-latency-ns = <45000>; + }; + opp09 { + opp-hz = /bits/ 64 <2448000000>; + opp-level = <9>; + clock-latency-ns = <49000>; + }; + opp10 { + opp-hz = /bits/ 64 <2676000000>; + opp-level = <10>; + clock-latency-ns = <53000>; + }; + opp11 { + opp-hz = /bits/ 64 <2904000000>; + opp-level = <11>; + clock-latency-ns = <56000>; + }; + opp12 { + opp-hz = /bits/ 64 <3036000000>; + opp-level = <12>; + clock-latency-ns = <56000>; + }; + /* Not available until CPU deep sleep is implemented + opp13 { + opp-hz = /bits/ 64 <3132000000>; + opp-level = <13>; + clock-latency-ns = <56000>; + turbo-mode; + }; + opp14 { + opp-hz = /bits/ 64 <3168000000>; + opp-level = <14>; + clock-latency-ns = <56000>; + turbo-mode; + }; + opp15 { + opp-hz = /bits/ 64 <3228000000>; + opp-level = <15>; + clock-latency-ns = <56000>; + turbo-mode; + }; + */ + }; + + pmu-e { + compatible = "apple,icestorm-pmu"; + interrupt-parent = <&aic>; + interrupts = <AIC_FIQ 0 AIC_CPU_PMU_E IRQ_TYPE_LEVEL_HIGH>; + }; + + pmu-p { + compatible = "apple,firestorm-pmu"; + interrupt-parent = <&aic>; + interrupts = <AIC_FIQ 0 AIC_CPU_PMU_P IRQ_TYPE_LEVEL_HIGH>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&aic>; + interrupt-names = "phys", "virt", "hyp-phys", "hyp-virt"; + interrupts = <AIC_FIQ 0 AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>, + <AIC_FIQ 0 AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>, + <AIC_FIQ 0 AIC_TMR_HV_PHYS IRQ_TYPE_LEVEL_HIGH>, + <AIC_FIQ 0 AIC_TMR_HV_VIRT IRQ_TYPE_LEVEL_HIGH>; + }; + + clkref: clock-ref { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "clkref"; + }; + + /* + * This is a fabulated representation of the input clock + * to NCO since we don't know the true clock tree. + */ + nco_clkref: clock-ref-nco { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "nco_ref"; + }; +}; diff --git a/arch/arm64/boot/dts/apple/t600x-die0.dtsi b/arch/arm64/boot/dts/apple/t600x-die0.dtsi new file mode 100644 index 000000000000..0b8958a8db77 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t600x-die0.dtsi @@ -0,0 +1,361 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Devices used on die 0 on the Apple T6002 "M1 Ultra" SoC and present on + * Apple T6000 / T6001 "M1 Pro" / "M1 Max". + * + * Copyright The Asahi Linux Contributors + */ + + + nco: clock-controller@28e03c000 { + compatible = "apple,t6000-nco", "apple,nco"; + reg = <0x2 0x8e03c000 0x0 0x14000>; + clocks = <&nco_clkref>; + #clock-cells = <1>; + }; + + aic: interrupt-controller@28e100000 { + compatible = "apple,t6000-aic", "apple,aic2"; + #interrupt-cells = <4>; + interrupt-controller; + reg = <0x2 0x8e100000 0x0 0xc000>, + <0x2 0x8e10c000 0x0 0x4>; + reg-names = "core", "event"; + power-domains = <&ps_aic>; + }; + + pinctrl_smc: pinctrl@290820000 { + compatible = "apple,t6000-pinctrl", "apple,pinctrl"; + reg = <0x2 0x90820000 0x0 0x4000>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_smc 0 0 30>; + apple,npins = <30>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 0 743 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 0 744 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 0 745 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 0 746 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 0 747 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 0 748 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 0 749 IRQ_TYPE_LEVEL_HIGH>; + }; + + wdt: watchdog@2922b0000 { + compatible = "apple,t6000-wdt", "apple,wdt"; + reg = <0x2 0x922b0000 0x0 0x4000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 0 631 IRQ_TYPE_LEVEL_HIGH>; + }; + + dart_sio_0: iommu@39b004000 { + compatible = "apple,t6000-dart"; + reg = <0x3 0x9b004000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 0 1130 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + power-domains = <&ps_sio_cpu>; + }; + + dart_sio_1: iommu@39b008000 { + compatible = "apple,t6000-dart"; + reg = <0x3 0x9b008000 0x0 0x8000>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 0 1130 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + power-domains = <&ps_sio_cpu>; + }; + + i2c0: i2c@39b040000 { + compatible = "apple,t6000-i2c", "apple,i2c"; + reg = <0x3 0x9b040000 0x0 0x4000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 0 1119 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c0>; + #address-cells = <0x1>; + #size-cells = <0x0>; + }; + + i2c1: i2c@39b044000 { + compatible = "apple,t6000-i2c", "apple,i2c"; + reg = <0x3 0x9b044000 0x0 0x4000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 0 1120 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c1>; + #address-cells = <0x1>; + #size-cells = <0x0>; + status = "disabled"; + }; + + i2c2: i2c@39b048000 { + compatible = "apple,t6000-i2c", "apple,i2c"; + reg = <0x3 0x9b048000 0x0 0x4000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 0 1121 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c2>; + #address-cells = <0x1>; + #size-cells = <0x0>; + status = "disabled"; + }; + + i2c3: i2c@39b04c000 { + compatible = "apple,t6000-i2c", "apple,i2c"; + reg = <0x3 0x9b04c000 0x0 0x4000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 0 1122 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c3>; + #address-cells = <0x1>; + #size-cells = <0x0>; + status = "disabled"; + }; + + i2c4: i2c@39b050000 { + compatible = "apple,t6000-i2c", "apple,i2c"; + reg = <0x3 0x9b050000 0x0 0x4000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 0 1123 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&i2c4_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c4>; + #address-cells = <0x1>; + #size-cells = <0x0>; + status = "disabled"; + }; + + i2c5: i2c@39b054000 { + compatible = "apple,t6000-i2c", "apple,i2c"; + reg = <0x3 0x9b054000 0x0 0x4000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 0 1124 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&i2c5_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c5>; + #address-cells = <0x1>; + #size-cells = <0x0>; + status = "disabled"; + }; + + serial0: serial@39b200000 { + compatible = "apple,s5l-uart"; + reg = <0x3 0x9b200000 0x0 0x1000>; + reg-io-width = <4>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 0 1097 IRQ_TYPE_LEVEL_HIGH>; + /* + * TODO: figure out the clocking properly, there may + * be a third selectable clock. + */ + clocks = <&clkref>, <&clkref>; + clock-names = "uart", "clk_uart_baud0"; + power-domains = <&ps_uart0>; + status = "disabled"; + }; + + admac: dma-controller@39b400000 { + compatible = "apple,t6000-admac", "apple,admac"; + reg = <0x3 0x9b400000 0x0 0x34000>; + #dma-cells = <1>; + dma-channels = <16>; + interrupts-extended = <0>, + <&aic AIC_IRQ 0 1118 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <0>; + iommus = <&dart_sio_0 2>, <&dart_sio_1 2>; + power-domains = <&ps_sio_adma>; + resets = <&ps_audio_p>; + }; + + mca: mca@39b600000 { + compatible = "apple,t6000-mca", "apple,mca"; + reg = <0x3 0x9b600000 0x0 0x10000>, + <0x3 0x9b500000 0x0 0x20000>; + clocks = <&nco 0>, <&nco 1>, <&nco 2>, <&nco 3>; + dmas = <&admac 0>, <&admac 1>, <&admac 2>, <&admac 3>, + <&admac 4>, <&admac 5>, <&admac 6>, <&admac 7>, + <&admac 8>, <&admac 9>, <&admac 10>, <&admac 11>, + <&admac 12>, <&admac 13>, <&admac 14>, <&admac 15>; + dma-names = "tx0a", "rx0a", "tx0b", "rx0b", + "tx1a", "rx1a", "tx1b", "rx1b", + "tx2a", "rx2a", "tx2b", "rx2b", + "tx3a", "rx3a", "tx3b", "rx3b"; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 0 1112 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 0 1113 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 0 1114 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 0 1115 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&ps_audio_p>, <&ps_mca0>, <&ps_mca1>, + <&ps_mca2>, <&ps_mca3>; + resets = <&ps_audio_p>; + #sound-dai-cells = <1>; + }; + + pcie0_dart_0: dart@581008000 { + compatible = "apple,t6000-dart"; + reg = <0x5 0x81008000 0x0 0x4000>; + #iommu-cells = <1>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 0 1271 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&ps_apcie_gp_sys>; + }; + + pcie0_dart_1: dart@582008000 { + compatible = "apple,t6000-dart"; + reg = <0x5 0x82008000 0x0 0x4000>; + #iommu-cells = <1>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 0 1274 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&ps_apcie_gp_sys>; + }; + + pcie0_dart_2: dart@583008000 { + compatible = "apple,t6000-dart"; + reg = <0x5 0x83008000 0x0 0x4000>; + #iommu-cells = <1>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 0 1277 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&ps_apcie_gp_sys>; + }; + + pcie0_dart_3: dart@584008000 { + compatible = "apple,t6000-dart"; + reg = <0x5 0x84008000 0x0 0x4000>; + #iommu-cells = <1>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 0 1280 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&ps_apcie_gp_sys>; + }; + + pcie0: pcie@590000000 { + compatible = "apple,t6000-pcie", "apple,pcie"; + device_type = "pci"; + + reg = <0x5 0x90000000 0x0 0x1000000>, + <0x5 0x80000000 0x0 0x100000>, + <0x5 0x81000000 0x0 0x4000>, + <0x5 0x82000000 0x0 0x4000>, + <0x5 0x83000000 0x0 0x4000>, + <0x5 0x84000000 0x0 0x4000>; + reg-names = "config", "rc", "port0", "port1", "port2", "port3"; + + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 0 1270 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 0 1273 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 0 1276 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 0 1279 IRQ_TYPE_LEVEL_HIGH>; + + msi-controller; + msi-parent = <&pcie0>; + msi-ranges = <&aic AIC_IRQ 0 1581 IRQ_TYPE_EDGE_RISING 32>; + + + iommu-map = <0x100 &pcie0_dart_0 1 1>, + <0x200 &pcie0_dart_1 1 1>, + <0x300 &pcie0_dart_2 1 1>, + <0x400 &pcie0_dart_3 1 1>; + iommu-map-mask = <0xff00>; + + bus-range = <0 4>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x43000000 0x5 0xa0000000 0x5 0xa0000000 0x0 0x20000000>, + <0x02000000 0x0 0xc0000000 0x5 0xc0000000 0x0 0x40000000>; + + power-domains = <&ps_apcie_gp_sys>; + pinctrl-0 = <&pcie_pins>; + pinctrl-names = "default"; + + port00: pci@0,0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + reset-gpios = <&pinctrl_ap 4 GPIO_ACTIVE_LOW>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &port00 0 0 0 0>, + <0 0 0 2 &port00 0 0 0 1>, + <0 0 0 3 &port00 0 0 0 2>, + <0 0 0 4 &port00 0 0 0 3>; + }; + + port01: pci@1,0 { + device_type = "pci"; + reg = <0x800 0x0 0x0 0x0 0x0>; + reset-gpios = <&pinctrl_ap 5 GPIO_ACTIVE_LOW>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &port01 0 0 0 0>, + <0 0 0 2 &port01 0 0 0 1>, + <0 0 0 3 &port01 0 0 0 2>, + <0 0 0 4 &port01 0 0 0 3>; + }; + + port02: pci@2,0 { + device_type = "pci"; + reg = <0x1000 0x0 0x0 0x0 0x0>; + reset-gpios = <&pinctrl_ap 6 GPIO_ACTIVE_LOW>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &port02 0 0 0 0>, + <0 0 0 2 &port02 0 0 0 1>, + <0 0 0 3 &port02 0 0 0 2>, + <0 0 0 4 &port02 0 0 0 3>; + }; + + port03: pci@3,0 { + device_type = "pci"; + reg = <0x1800 0x0 0x0 0x0 0x0>; + reset-gpios = <&pinctrl_ap 7 GPIO_ACTIVE_LOW>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &port03 0 0 0 0>, + <0 0 0 2 &port03 0 0 0 1>, + <0 0 0 3 &port03 0 0 0 2>, + <0 0 0 4 &port03 0 0 0 3>; + }; + }; diff --git a/arch/arm64/boot/dts/apple/t600x-dieX.dtsi b/arch/arm64/boot/dts/apple/t600x-dieX.dtsi new file mode 100644 index 000000000000..a32ff0c9d7b0 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t600x-dieX.dtsi @@ -0,0 +1,121 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Devices used on both dies on the Apple T6002 "M1 Ultra" and present on + * Apple T6000/T6001 "M1 Pro/Max". + * + * Copyright The Asahi Linux Contributors + */ + + DIE_NODE(cpufreq_e): cpufreq@210e20000 { + compatible = "apple,t6000-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq"; + reg = <0x2 0x10e20000 0 0x1000>; + #performance-domain-cells = <0>; + }; + + DIE_NODE(cpufreq_p0): cpufreq@211e20000 { + compatible = "apple,t6000-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq"; + reg = <0x2 0x11e20000 0 0x1000>; + #performance-domain-cells = <0>; + }; + + DIE_NODE(cpufreq_p1): cpufreq@212e20000 { + compatible = "apple,t6000-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq"; + reg = <0x2 0x12e20000 0 0x1000>; + #performance-domain-cells = <0>; + }; + + DIE_NODE(pmgr): power-management@28e080000 { + compatible = "apple,t6000-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x2 0x8e080000 0 0x4000>; + }; + + DIE_NODE(pmgr_east): power-management@28e580000 { + compatible = "apple,t6000-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x2 0x8e580000 0 0xc000>; + }; + + DIE_NODE(pmgr_south): power-management@28e680000 { + compatible = "apple,t6000-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x2 0x8e680000 0 0xc000>; + }; + + DIE_NODE(pinctrl_nub): pinctrl@2921f0000 { + compatible = "apple,t6000-pinctrl", "apple,pinctrl"; + reg = <0x2 0x921f0000 0x0 0x4000>; + power-domains = <&DIE_NODE(ps_nub_gpio)>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&DIE_NODE(pinctrl_nub) 0 0 16>; + apple,npins = <16>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ DIE_NO 623 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ DIE_NO 624 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ DIE_NO 625 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ DIE_NO 626 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ DIE_NO 627 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ DIE_NO 628 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ DIE_NO 629 IRQ_TYPE_LEVEL_HIGH>; + }; + + DIE_NODE(pmgr_mini): power-management@292280000 { + compatible = "apple,t6000-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x2 0x92280000 0 0x4000>; + }; + + DIE_NODE(pinctrl_aop): pinctrl@293820000 { + compatible = "apple,t6000-pinctrl", "apple,pinctrl"; + reg = <0x2 0x93820000 0x0 0x4000>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&DIE_NODE(pinctrl_aop) 0 0 63>; + apple,npins = <63>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ DIE_NO 567 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ DIE_NO 568 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ DIE_NO 569 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ DIE_NO 570 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ DIE_NO 571 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ DIE_NO 572 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ DIE_NO 573 IRQ_TYPE_LEVEL_HIGH>; + }; + + DIE_NODE(pinctrl_ap): pinctrl@39b028000 { + compatible = "apple,t6000-pinctrl", "apple,pinctrl"; + reg = <0x3 0x9b028000 0x0 0x4000>; + + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ DIE_NO 427 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ DIE_NO 428 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ DIE_NO 429 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ DIE_NO 430 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ DIE_NO 431 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ DIE_NO 432 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ DIE_NO 433 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&clkref>; + power-domains = <&DIE_NODE(ps_gpio)>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&DIE_NODE(pinctrl_ap) 0 0 255>; + apple,npins = <255>; + + interrupt-controller; + #interrupt-cells = <2>; + }; diff --git a/arch/arm64/boot/dts/apple/t600x-gpio-pins.dtsi b/arch/arm64/boot/dts/apple/t600x-gpio-pins.dtsi new file mode 100644 index 000000000000..b31f1a7a2b3f --- /dev/null +++ b/arch/arm64/boot/dts/apple/t600x-gpio-pins.dtsi @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * GPIO pin mappings for Apple T600x SoCs. + * + * Copyright The Asahi Linux Contributors + */ + +&pinctrl_ap { + i2c0_pins: i2c0-pins { + pinmux = <APPLE_PINMUX(92, 1)>, + <APPLE_PINMUX(93, 1)>; + }; + + i2c1_pins: i2c1-pins { + pinmux = <APPLE_PINMUX(94, 1)>, + <APPLE_PINMUX(95, 1)>; + }; + + i2c2_pins: i2c2-pins { + pinmux = <APPLE_PINMUX(96, 1)>, + <APPLE_PINMUX(97, 1)>; + }; + + i2c3_pins: i2c3-pins { + pinmux = <APPLE_PINMUX(98, 1)>, + <APPLE_PINMUX(99, 1)>; + }; + + i2c4_pins: i2c4-pins { + pinmux = <APPLE_PINMUX(8, 1)>, + <APPLE_PINMUX(9, 1)>; + }; + + i2c5_pins: i2c5-pins { + pinmux = <APPLE_PINMUX(100, 1)>, + <APPLE_PINMUX(101, 1)>; + }; + + pcie_pins: pcie-pins { + pinmux = <APPLE_PINMUX(0, 1)>, + <APPLE_PINMUX(1, 1)>, + <APPLE_PINMUX(2, 1)>, + <APPLE_PINMUX(3, 1)>; + }; +}; diff --git a/arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi b/arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi new file mode 100644 index 000000000000..34906d522f0a --- /dev/null +++ b/arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * MacBook Pro (14/16-inch, 2021) + * + * This file contains the parts common to J314 and J316 devices with both t6000 and t6001. + * + * target-type: J314s / J314c / J316s / J316c + * + * Copyright The Asahi Linux Contributors + */ + +/ { + aliases { + serial0 = &serial0; + wifi0 = &wifi0; + }; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + stdout-path = "serial0"; + + framebuffer0: framebuffer@0 { + compatible = "apple,simple-framebuffer", "simple-framebuffer"; + reg = <0 0 0 0>; /* To be filled by loader */ + /* Format properties will be added by loader */ + status = "disabled"; + }; + }; + + memory@10000000000 { + device_type = "memory"; + reg = <0x100 0 0x2 0>; /* To be filled by loader */ + }; +}; + +&serial0 { + status = "okay"; +}; + +/* USB Type C */ +&i2c0 { + hpm0: usb-pd@38 { + compatible = "apple,cd321x"; + reg = <0x38>; + interrupt-parent = <&pinctrl_ap>; + interrupts = <174 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "irq"; + }; + + hpm1: usb-pd@3f { + compatible = "apple,cd321x"; + reg = <0x3f>; + interrupt-parent = <&pinctrl_ap>; + interrupts = <174 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "irq"; + }; + + hpm2: usb-pd@3b { + compatible = "apple,cd321x"; + reg = <0x3b>; + interrupt-parent = <&pinctrl_ap>; + interrupts = <174 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "irq"; + }; + + /* MagSafe port */ + hpm5: usb-pd@3a { + compatible = "apple,cd321x"; + reg = <0x3a>; + interrupt-parent = <&pinctrl_ap>; + interrupts = <174 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "irq"; + }; +}; + +&nco_clkref { + clock-frequency = <1068000000>; +}; + +/* PCIe devices */ +&port00 { + /* WLAN */ + bus-range = <1 1>; + wifi0: wifi@0,0 { + reg = <0x10000 0x0 0x0 0x0 0x0>; + /* To be filled by the loader */ + local-mac-address = [00 10 18 00 00 10]; + }; +}; + +&port01 { + /* SD card reader */ + bus-range = <2 2>; + sdhci0: mmc@0,0 { + compatible = "pci17a0,9755"; + reg = <0x20000 0x0 0x0 0x0 0x0>; + cd-inverted; + wp-inverted; + }; +}; + +&pcie0_dart_2 { + status = "disabled"; +}; + +&pcie0_dart_3 { + status = "disabled"; +}; + +/delete-node/ &port02; +/delete-node/ &port03; diff --git a/arch/arm64/boot/dts/apple/t600x-j375.dtsi b/arch/arm64/boot/dts/apple/t600x-j375.dtsi new file mode 100644 index 000000000000..00d3a9447c89 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t600x-j375.dtsi @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Mac Studio (2022) + * + * This file contains the parts common to J375 devices with both t6001 and t6002. + * + * target-type: J375c / J375d + * + * Copyright The Asahi Linux Contributors + */ + +/ { + aliases { + serial0 = &serial0; + wifi0 = &wifi0; + }; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + stdout-path = "serial0"; + + framebuffer0: framebuffer@0 { + compatible = "apple,simple-framebuffer", "simple-framebuffer"; + reg = <0 0 0 0>; /* To be filled by loader */ + /* Format properties will be added by loader */ + status = "disabled"; + }; + }; + + memory@10000000000 { + device_type = "memory"; + reg = <0x100 0 0x2 0>; /* To be filled by loader */ + }; +}; + +&serial0 { + status = "okay"; +}; + +/* USB Type C */ +&i2c0 { + hpm0: usb-pd@38 { + compatible = "apple,cd321x"; + reg = <0x38>; + interrupt-parent = <&pinctrl_ap>; + interrupts = <174 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "irq"; + }; + + hpm1: usb-pd@3f { + compatible = "apple,cd321x"; + reg = <0x3f>; + interrupt-parent = <&pinctrl_ap>; + interrupts = <174 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "irq"; + }; + + hpm2: usb-pd@3b { + compatible = "apple,cd321x"; + reg = <0x3b>; + interrupt-parent = <&pinctrl_ap>; + interrupts = <174 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "irq"; + }; + + hpm3: usb-pd@3c { + compatible = "apple,cd321x"; + reg = <0x3c>; + interrupt-parent = <&pinctrl_ap>; + interrupts = <174 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "irq"; + }; +}; + +&nco_clkref { + clock-frequency = <1068000000>; +}; + +/* PCIe devices */ +&port00 { + /* WLAN */ + bus-range = <1 1>; + wifi0: wifi@0,0 { + reg = <0x10000 0x0 0x0 0x0 0x0>; + /* To be filled by the loader */ + local-mac-address = [00 10 18 00 00 10]; + }; +}; + +&port01 { + /* SD card reader */ + bus-range = <2 2>; + sdhci0: mmc@0,0 { + compatible = "pci17a0,9755"; + reg = <0x20000 0x0 0x0 0x0 0x0>; + cd-inverted; + wp-inverted; + }; +}; + +&port02 { + /* 10 Gbit Ethernet */ + bus-range = <3 3>; + ethernet0: ethernet@0,0 { + reg = <0x30000 0x0 0x0 0x0 0x0>; + /* To be filled by the loader */ + local-mac-address = [00 10 18 00 00 00]; + }; +}; + +&port03 { + /* USB xHCI */ + bus-range = <4 4>; +}; diff --git a/arch/arm64/boot/dts/apple/t600x-nvme.dtsi b/arch/arm64/boot/dts/apple/t600x-nvme.dtsi new file mode 100644 index 000000000000..7dff738d317e --- /dev/null +++ b/arch/arm64/boot/dts/apple/t600x-nvme.dtsi @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * NVMe related devices for Apple T600x SoCs. + * + * Copyright The Asahi Linux Contributors + */ + + DIE_NODE(ans_mbox): mbox@38f408000 { + compatible = "apple,t6000-asc-mailbox", "apple,asc-mailbox-v4"; + reg = <0x3 0x8f408000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ DIE_NO 1069 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ DIE_NO 1070 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ DIE_NO 1071 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ DIE_NO 1072 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "send-empty", "send-not-empty", + "recv-empty", "recv-not-empty"; + power-domains = <&DIE_NODE(ps_ans2)>; + #mbox-cells = <0>; + }; + + DIE_NODE(sart): sart@393c50000 { + compatible = "apple,t6000-sart"; + reg = <0x3 0x93c50000 0x0 0x10000>; + power-domains = <&DIE_NODE(ps_ans2)>; + }; + + DIE_NODE(nvme): nvme@393cc0000 { + compatible = "apple,t6000-nvme-ans2", "apple,nvme-ans2"; + reg = <0x3 0x93cc0000 0x0 0x40000>, <0x3 0x8f400000 0x0 0x4000>; + reg-names = "nvme", "ans"; + interrupt-parent = <&aic>; + /* The NVME interrupt is always routed to die */ + interrupts = <AIC_IRQ 0 1613 IRQ_TYPE_LEVEL_HIGH>; + mboxes = <&DIE_NODE(ans_mbox)>; + apple,sart = <&DIE_NODE(sart)>; + power-domains = <&DIE_NODE(ps_ans2)>, + <&DIE_NODE(ps_apcie_st_sys)>, + <&DIE_NODE(ps_apcie_st1_sys)>; + power-domain-names = "ans", "apcie0", "apcie1"; + resets = <&DIE_NODE(ps_ans2)>; + }; diff --git a/arch/arm64/boot/dts/apple/t600x-pmgr.dtsi b/arch/arm64/boot/dts/apple/t600x-pmgr.dtsi new file mode 100644 index 000000000000..b8daeb0368d5 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t600x-pmgr.dtsi @@ -0,0 +1,2012 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * PMGR Power domains for the Apple T6001 "M1 Max" SoC + * + * Copyright The Asahi Linux Contributors + */ + +&DIE_NODE(pmgr) { + DIE_NODE(ps_pms_bridge): power-controller@100 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x100 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(pms_bridge); + apple,always-on; /* Core device */ + }; + + DIE_NODE(ps_aic): power-controller@108 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x108 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(aic); + apple,always-on; /* Core device */ + }; + + DIE_NODE(ps_dwi): power-controller@110 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x110 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dwi); + apple,always-on; /* Core device */ + }; + + DIE_NODE(ps_pms): power-controller@118 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x118 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(pms); + apple,always-on; /* Core device */ + }; + + DIE_NODE(ps_gpio): power-controller@120 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x120 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(gpio); + power-domains = <&DIE_NODE(ps_pms)>, <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_soc_dpe): power-controller@128 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x128 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(soc_dpe); + apple,always-on; /* Core device */ + }; + + DIE_NODE(ps_pmgr_soc_ocla): power-controller@130 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x130 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(pmgr_soc_ocla); + power-domains = <&DIE_NODE(ps_pms)>; + }; + + DIE_NODE(ps_pcie0_ref): power-controller@138 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x138 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(pcie0_ref); + }; + + DIE_NODE(ps_pcie1_ref): power-controller@140 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x140 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(pcie1_ref); + }; + + DIE_NODE(ps_apcie_st): power-controller@148 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x148 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(apcie_st); + power-domains = <&DIE_NODE(ps_pcie1_ref)>; + }; + + DIE_NODE(ps_apcie_gp): power-controller@150 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x150 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(apcie_gp); + power-domains = <&DIE_NODE(ps_pcie0_ref)>; + }; + + DIE_NODE(ps_devc0_ivdmc): power-controller@180 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x180 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(devc0_ivdmc); + }; + + DIE_NODE(ps_amcc0): power-controller@188 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x188 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(amcc0); + apple,always-on; /* Memory controller */ + }; + + DIE_NODE(ps_amcc2): power-controller@190 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x190 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(amcc2); + apple,always-on; /* Memory controller */ + }; + + DIE_NODE(ps_dcs_00): power-controller@198 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x198 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_00); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_01): power-controller@1a0 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_01); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_02): power-controller@1a8 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_02); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_03): power-controller@1b0 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_03); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_08): power-controller@1b8 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_08); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_09): power-controller@1c0 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1c0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_09); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_10): power-controller@1c8 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1c8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_10); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_11): power-controller@1d0 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1d0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_11); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_afi): power-controller@1d8 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1d8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afi); + apple,always-on; /* Apple Fabric, CPU interface is here */ + }; + + DIE_NODE(ps_afc): power-controller@1e0 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1e0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afc); + apple,always-on; /* Apple Fabric, CPU interface is here */ + }; + + DIE_NODE(ps_afr): power-controller@1e8 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1e8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afr); + /* Apple Fabric, media DIE_NODE(stuff): this can power down */ + }; + + DIE_NODE(ps_afnc1_ioa): power-controller@1f0 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc1_ioa); + apple,always-on; /* Apple Fabric */ + power-domains = <&DIE_NODE(ps_afi)>; + }; + + DIE_NODE(ps_afnc0_ioa): power-controller@1f8 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1f8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc0_ioa); + apple,always-on; /* Apple Fabric */ + power-domains = <&DIE_NODE(ps_afi)>; + }; + + DIE_NODE(ps_afnc1_ls): power-controller@200 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x200 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc1_ls); + apple,always-on; /* Apple Fabric */ + power-domains = <&DIE_NODE(ps_afnc1_ioa)>; + }; + + DIE_NODE(ps_afnc0_ls): power-controller@208 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x208 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc0_ls); + apple,always-on; /* Apple Fabric */ + power-domains = <&DIE_NODE(ps_afnc0_ioa)>; + }; + + DIE_NODE(ps_afnc1_lw0): power-controller@210 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x210 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc1_lw0); + apple,always-on; /* Apple Fabric */ + power-domains = <&DIE_NODE(ps_afnc1_ls)>; + }; + + DIE_NODE(ps_afnc1_lw1): power-controller@218 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x218 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc1_lw1); + apple,always-on; /* Apple Fabric */ + power-domains = <&DIE_NODE(ps_afnc1_ls)>; + }; + + DIE_NODE(ps_afnc1_lw2): power-controller@220 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x220 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc1_lw2); + apple,always-on; /* Apple Fabric */ + power-domains = <&DIE_NODE(ps_afnc1_ls)>; + }; + + DIE_NODE(ps_afnc0_lw0): power-controller@228 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x228 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc0_lw0); + apple,always-on; /* Apple Fabric */ + power-domains = <&DIE_NODE(ps_afnc0_ls)>; + }; + + DIE_NODE(ps_scodec): power-controller@230 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x230 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(scodec); + power-domains = <&DIE_NODE(ps_afnc1_lw0)>; + }; + + DIE_NODE(ps_atc0_common): power-controller@238 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x238 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc0_common); + power-domains = <&DIE_NODE(ps_afnc1_lw1)>; + }; + + DIE_NODE(ps_atc1_common): power-controller@240 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x240 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc1_common); + power-domains = <&DIE_NODE(ps_afnc1_lw1)>; + }; + + DIE_NODE(ps_c0_usb31drd): power-controller@248 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x248 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(c0_usb31drd); + power-domains = <&DIE_NODE(ps_usb)>; + }; + + DIE_NODE(ps_c1_usb31drd): power-controller@250 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x250 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(c1_usb31drd); + power-domains = <&DIE_NODE(ps_usb)>; + }; + + DIE_NODE(ps_dispext0_fe): power-controller@258 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x258 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dispext0_fe); + power-domains = <&DIE_NODE(ps_afi)>; + }; + + DIE_NODE(ps_dispext1_fe): power-controller@260 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x260 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dispext1_fe); + power-domains = <&DIE_NODE(ps_afi)>; + }; + + DIE_NODE(ps_ane_sys): power-controller@268 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x268 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(ane_sys); + power-domains = <&DIE_NODE(ps_afr)>; + }; + + DIE_NODE(ps_avd_sys): power-controller@270 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x270 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(avd_sys); + power-domains = <&DIE_NODE(ps_afr)>; + }; + + DIE_NODE(ps_dispext0_cpu0): power-controller@280 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x280 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dispext0_cpu0); + power-domains = <&DIE_NODE(ps_dispext0_fe)>; + }; + + DIE_NODE(ps_dispext1_cpu0): power-controller@2a8 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x2a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dispext1_cpu0); + power-domains = <&DIE_NODE(ps_dispext1_fe)>; + }; + + DIE_NODE(ps_ane_sys_cpu): power-controller@2c8 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x2c8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(ane_sys_cpu); + power-domains = <&DIE_NODE(ps_ane_sys)>; + }; + +#if DIE_NO == 0 + /* PMP is only present on die 0 of the M1 Ultra */ + DIE_NODE(ps_pmp): power-controller@2d8 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x2d8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(pmp); + }; +#endif + + DIE_NODE(ps_pms_sram): power-controller@2e0 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x2e0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(pms_sram); + }; + + DIE_NODE(ps_apcie_st_sys): power-controller@2e8 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x2e8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(apcie_st_sys); + power-domains = <&DIE_NODE(ps_apcie_st)>, <&DIE_NODE(ps_ans2)>; + }; + + DIE_NODE(ps_apcie_st1_sys): power-controller@2f0 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x2f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(apcie_st1_sys); + power-domains = <&DIE_NODE(ps_apcie_st)>, <&DIE_NODE(ps_ans2)>; + }; + + DIE_NODE(ps_atc2_common): power-controller@2f8 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x2f8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc2_common); + power-domains = <&DIE_NODE(ps_afnc1_lw1)>; + }; + + DIE_NODE(ps_atc3_common): power-controller@300 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x300 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc3_common); + power-domains = <&DIE_NODE(ps_afnc1_lw1)>; + }; + + DIE_NODE(ps_usb): power-controller@318 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x318 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(usb); + power-domains = <&DIE_NODE(ps_afnc1_lw2)>; + }; + + DIE_NODE(ps_apcie_gp_sys): power-controller@320 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x320 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(apcie_gp_sys); + power-domains = <&DIE_NODE(ps_afnc1_lw2)>, <&DIE_NODE(ps_apcie_gp)>; + apple,always-on; /* Breaks things if shut down */ + }; + + DIE_NODE(ps_atc0_cio): power-controller@328 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x328 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc0_cio); + power-domains = <&DIE_NODE(ps_atc0_common)>; + }; + + DIE_NODE(ps_atc0_pcie): power-controller@330 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x330 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc0_pcie); + power-domains = <&DIE_NODE(ps_atc0_common)>; + }; + + DIE_NODE(ps_atc1_cio): power-controller@338 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x338 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc1_cio); + power-domains = <&DIE_NODE(ps_atc1_common)>; + }; + + DIE_NODE(ps_atc1_pcie): power-controller@340 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x340 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc1_pcie); + power-domains = <&DIE_NODE(ps_atc1_common)>; + }; + + DIE_NODE(ps_atc2_cio): power-controller@348 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x348 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc2_cio); + power-domains = <&DIE_NODE(ps_atc2_common)>; + }; + + DIE_NODE(ps_atc2_pcie): power-controller@350 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x350 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc2_pcie); + power-domains = <&DIE_NODE(ps_atc2_common)>; + }; + + DIE_NODE(ps_atc3_cio): power-controller@358 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x358 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc3_cio); + power-domains = <&DIE_NODE(ps_atc3_common)>; + }; + + DIE_NODE(ps_atc3_pcie): power-controller@360 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x360 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc3_pcie); + power-domains = <&DIE_NODE(ps_atc3_common)>; + }; + + DIE_NODE(ps_c0_usbctl): power-controller@368 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x368 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(c0_usbctl); + power-domains = <&DIE_NODE(ps_usb)>; + }; + + DIE_NODE(ps_c1_usbctl): power-controller@370 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x370 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(c1_usbctl); + power-domains = <&DIE_NODE(ps_usb)>; + }; + + DIE_NODE(ps_atc0_cio_pcie): power-controller@378 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x378 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc0_cio_pcie); + power-domains = <&DIE_NODE(ps_atc0_cio)>; + }; + + DIE_NODE(ps_atc0_cio_usb): power-controller@380 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x380 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc0_cio_usb); + power-domains = <&DIE_NODE(ps_atc0_cio)>; + }; + + DIE_NODE(ps_atc1_cio_pcie): power-controller@388 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x388 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc1_cio_pcie); + power-domains = <&DIE_NODE(ps_atc1_cio)>; + }; + + DIE_NODE(ps_atc1_cio_usb): power-controller@390 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x390 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc1_cio_usb); + power-domains = <&DIE_NODE(ps_atc1_cio)>; + }; + + DIE_NODE(ps_atc2_cio_pcie): power-controller@398 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x398 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc2_cio_pcie); + power-domains = <&DIE_NODE(ps_atc2_cio)>; + }; + + DIE_NODE(ps_atc2_cio_usb): power-controller@3a0 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x3a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc2_cio_usb); + power-domains = <&DIE_NODE(ps_atc2_cio)>; + }; + + DIE_NODE(ps_atc3_cio_pcie): power-controller@3a8 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x3a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc3_cio_pcie); + power-domains = <&DIE_NODE(ps_atc3_cio)>; + }; + + DIE_NODE(ps_atc3_cio_usb): power-controller@3b0 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x3b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc3_cio_usb); + power-domains = <&DIE_NODE(ps_atc3_cio)>; + }; + + DIE_NODE(ps_trace_fab): power-controller@3b8 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x3b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(trace_fab); + }; +}; + +&DIE_NODE(pmgr_east) { + DIE_NODE(ps_clvr_spmi0): power-controller@100 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x100 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(clvr_spmi0); + apple,always-on; /* PCPU voltage regulator interface (used by SMC) */ + }; + + DIE_NODE(ps_clvr_spmi1): power-controller@108 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x108 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(clvr_spmi1); + apple,always-on; /* GPU voltage regulator interface (used by SMC) */ + }; + + DIE_NODE(ps_clvr_spmi2): power-controller@110 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x110 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(clvr_spmi2); + apple,always-on; /* ANE, fabric, AFR voltage regulator interface (used by SMC) */ + }; + + DIE_NODE(ps_clvr_spmi3): power-controller@118 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x118 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(clvr_spmi3); + apple,always-on; /* Additional voltage regulator, probably used on T6001 (SMC) */ + }; + + DIE_NODE(ps_clvr_spmi4): power-controller@120 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x120 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(clvr_spmi4); + apple,always-on; /* Additional voltage regulator, probably used on T6001 (SMC) */ + }; + + DIE_NODE(ps_ispsens0): power-controller@128 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x128 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(ispsens0); + }; + + DIE_NODE(ps_ispsens1): power-controller@130 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x130 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(ispsens1); + }; + + DIE_NODE(ps_ispsens2): power-controller@138 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x138 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(ispsens2); + }; + + DIE_NODE(ps_ispsens3): power-controller@140 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x140 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(ispsens3); + }; + + DIE_NODE(ps_afnc2_ioa): power-controller@148 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x148 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc2_ioa); + apple,always-on; /* Apple Fabric */ + power-domains = <&DIE_NODE(ps_afi)>; + }; + + DIE_NODE(ps_afnc2_ls): power-controller@150 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x150 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc2_ls); + apple,always-on; /* Apple Fabric */ + power-domains = <&DIE_NODE(ps_afnc2_ioa)>; + }; + + DIE_NODE(ps_afnc2_lw0): power-controller@158 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x158 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc2_lw0); + apple,always-on; /* Apple Fabric */ + power-domains = <&DIE_NODE(ps_afnc2_ls)>; + }; + + DIE_NODE(ps_afnc2_lw1): power-controller@160 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x160 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc2_lw1); + apple,always-on; /* Apple Fabric */ + power-domains = <&DIE_NODE(ps_afnc2_ls)>; + }; + + DIE_NODE(ps_afnc3_ioa): power-controller@168 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x168 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc3_ioa); + apple,always-on; /* Apple Fabric */ + power-domains = <&DIE_NODE(ps_afi)>; + }; + + DIE_NODE(ps_afnc3_ls): power-controller@170 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x170 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc3_ls); + apple,always-on; /* Apple Fabric */ + power-domains = <&DIE_NODE(ps_afnc3_ioa)>; + }; + + DIE_NODE(ps_afnc3_lw0): power-controller@178 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x178 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc3_lw0); + apple,always-on; /* Apple Fabric */ + power-domains = <&DIE_NODE(ps_afnc3_ls)>; + }; + + DIE_NODE(ps_sio): power-controller@180 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x180 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(sio); + power-domains = <&DIE_NODE(ps_afnc2_lw1)>; + }; + + DIE_NODE(ps_sio_cpu): power-controller@188 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x188 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(sio_cpu); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_fpwm0): power-controller@190 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x190 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(fpwm0); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_fpwm1): power-controller@198 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x198 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(fpwm1); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_fpwm2): power-controller@1a0 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(fpwm2); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_i2c0): power-controller@1a8 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(i2c0); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_i2c1): power-controller@1b0 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(i2c1); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_i2c2): power-controller@1b8 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(i2c2); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_i2c3): power-controller@1c0 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1c0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(i2c3); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_i2c4): power-controller@1c8 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1c8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(i2c4); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_i2c5): power-controller@1d0 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1d0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(i2c5); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_i2c6): power-controller@1d8 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1d8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(i2c6); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_i2c7): power-controller@1e0 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1e0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(i2c7); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_spi_p): power-controller@1e8 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1e8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(spi_p); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_spi0): power-controller@1f0 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(spi0); + power-domains = <&DIE_NODE(ps_spi_p)>; + }; + + DIE_NODE(ps_spi1): power-controller@1f8 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1f8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(spi1); + power-domains = <&DIE_NODE(ps_spi_p)>; + }; + + DIE_NODE(ps_spi2): power-controller@200 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x200 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(spi2); + power-domains = <&DIE_NODE(ps_spi_p)>; + }; + + DIE_NODE(ps_spi3): power-controller@208 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x208 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(spi3); + power-domains = <&DIE_NODE(ps_spi_p)>; + }; + + DIE_NODE(ps_spi4): power-controller@210 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x210 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(spi4); + power-domains = <&DIE_NODE(ps_spi_p)>; + }; + + DIE_NODE(ps_sio_spmi0): power-controller@218 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x218 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(sio_spmi0); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_sio_spmi1): power-controller@220 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x220 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(sio_spmi1); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_sio_spmi2): power-controller@228 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x228 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(sio_spmi2); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_uart_p): power-controller@230 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x230 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(uart_p); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_uart_n): power-controller@238 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x238 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(uart_n); + power-domains = <&DIE_NODE(ps_uart_p)>; + }; + + DIE_NODE(ps_uart0): power-controller@240 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x240 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(uart0); + power-domains = <&DIE_NODE(ps_uart_p)>; + }; + + DIE_NODE(ps_uart1): power-controller@248 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x248 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(uart1); + power-domains = <&DIE_NODE(ps_uart_p)>; + }; + + DIE_NODE(ps_uart2): power-controller@250 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x250 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(uart2); + power-domains = <&DIE_NODE(ps_uart_p)>; + }; + + DIE_NODE(ps_uart3): power-controller@258 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x258 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(uart3); + power-domains = <&DIE_NODE(ps_uart_p)>; + }; + + DIE_NODE(ps_uart4): power-controller@260 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x260 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(uart4); + power-domains = <&DIE_NODE(ps_uart_p)>; + }; + + DIE_NODE(ps_uart6): power-controller@268 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x268 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(uart6); + power-domains = <&DIE_NODE(ps_uart_p)>; + }; + + DIE_NODE(ps_uart7): power-controller@270 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x270 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(uart7); + power-domains = <&DIE_NODE(ps_uart_p)>; + }; + + DIE_NODE(ps_audio_p): power-controller@278 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x278 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(audio_p); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_sio_adma): power-controller@280 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x280 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(sio_adma); + power-domains = <&DIE_NODE(ps_audio_p)>, <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_mca0): power-controller@288 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x288 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(mca0); + power-domains = <&DIE_NODE(ps_audio_p)>, <&DIE_NODE(ps_sio_adma)>; + }; + + DIE_NODE(ps_mca1): power-controller@290 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x290 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(mca1); + power-domains = <&DIE_NODE(ps_audio_p)>, <&DIE_NODE(ps_sio_adma)>; + }; + + DIE_NODE(ps_mca2): power-controller@298 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x298 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(mca2); + power-domains = <&DIE_NODE(ps_audio_p)>, <&DIE_NODE(ps_sio_adma)>; + }; + + DIE_NODE(ps_mca3): power-controller@2a0 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x2a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(mca3); + power-domains = <&DIE_NODE(ps_audio_p)>, <&DIE_NODE(ps_sio_adma)>; + }; + + DIE_NODE(ps_dpa0): power-controller@2a8 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x2a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dpa0); + power-domains = <&DIE_NODE(ps_audio_p)>; + }; + + DIE_NODE(ps_dpa1): power-controller@2b0 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x2b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dpa1); + power-domains = <&DIE_NODE(ps_audio_p)>; + }; + + DIE_NODE(ps_dpa2): power-controller@2b8 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x2b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dpa2); + power-domains = <&DIE_NODE(ps_audio_p)>; + }; + + DIE_NODE(ps_dpa3): power-controller@2c0 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x2c0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dpa3); + power-domains = <&DIE_NODE(ps_audio_p)>; + }; + + DIE_NODE(ps_dpa4): power-controller@2c8 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x2c8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dpa4); + power-domains = <&DIE_NODE(ps_audio_p)>; + }; + + DIE_NODE(ps_aes): power-controller@2d0 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x2d0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(aes); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_amcc1): power-controller@2d8 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x2d8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(amcc1); + apple,always-on; /* Memory controller */ + }; + + DIE_NODE(ps_amcc3): power-controller@2e0 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x2e0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(amcc3); + apple,always-on; /* Memory controller */ + }; + + DIE_NODE(ps_dcs_04): power-controller@2e8 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x2e8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_04); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_05): power-controller@2f0 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x2f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_05); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_06): power-controller@2f8 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x2f8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_06); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_07): power-controller@300 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x300 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_07); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_12): power-controller@308 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x308 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_12); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_13): power-controller@310 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x310 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_13); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_14): power-controller@318 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x318 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_14); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_15): power-controller@320 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x320 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_15); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_disp0_fe): power-controller@328 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x328 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(disp0_fe); + power-domains = <&DIE_NODE(ps_afnc2_lw0)>; + apple,always-on; /* TODO: figure out if we can enable PM here */ + }; + + DIE_NODE(ps_disp0_cpu0): power-controller@350 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x350 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(disp0_cpu0); + power-domains = <&DIE_NODE(ps_disp0_fe)>; + apple,always-on; /* TODO: figure out if we can enable PM here */ + apple,min-state = <4>; + }; + + DIE_NODE(ps_dispdfr_fe): power-controller@378 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x378 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dispdfr_fe); + power-domains = <&DIE_NODE(ps_afnc2_lw1)>; + }; + + DIE_NODE(ps_dispdfr_be): power-controller@380 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x380 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dispdfr_be); + power-domains = <&DIE_NODE(ps_dispdfr_fe)>; + }; + + DIE_NODE(ps_mipi_dsi): power-controller@388 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x388 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(mipi_dsi); + power-domains = <&DIE_NODE(ps_dispdfr_be)>; + }; + + DIE_NODE(ps_jpg): power-controller@390 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x390 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(jpg); + power-domains = <&DIE_NODE(ps_afr)>; + }; + + DIE_NODE(ps_msr0): power-controller@398 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x398 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(msr0); + power-domains = <&DIE_NODE(ps_afr)>; + }; + + DIE_NODE(ps_msr0_ase_core): power-controller@3a0 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x3a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(msr0_ase_core); + power-domains = <&DIE_NODE(ps_msr0)>; + }; + + DIE_NODE(ps_isp_sys): power-controller@3a8 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x3a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(isp_sys); + power-domains = <&DIE_NODE(ps_afnc2_lw1)>; + }; + + DIE_NODE(ps_venc_sys): power-controller@3b0 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x3b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(venc_sys); + power-domains = <&DIE_NODE(ps_afr)>; + }; + + DIE_NODE(ps_ans2): power-controller@3b8 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x3b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(ans2); + /* + * The ADT makes ps_apcie_st[1]_sys depend on ps_ans2 instead, + * but we'd rather have a single power domain for the downstream + * device to depend on, so use this node as the child. + * This makes more sense anyway (since ANS2 uses APCIE_ST). + */ + power-domains = <&DIE_NODE(ps_afnc2_lw0)>; + }; + + DIE_NODE(ps_gfx): power-controller@3c0 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x3c0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(gfx); + power-domains = <&DIE_NODE(ps_afr)>; + }; + + DIE_NODE(ps_sep): power-controller@c00 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0xc00 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(sep); + apple,always-on; /* Locked on */ + }; + + DIE_NODE(ps_venc_dma): power-controller@8000 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x8000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(venc_dma); + power-domains = <&DIE_NODE(ps_venc_sys)>; + }; + + DIE_NODE(ps_venc_pipe4): power-controller@8008 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x8008 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(venc_pipe4); + power-domains = <&DIE_NODE(ps_venc_dma)>; + }; + + DIE_NODE(ps_venc_pipe5): power-controller@8010 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x8010 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(venc_pipe5); + power-domains = <&DIE_NODE(ps_venc_dma)>; + }; + + DIE_NODE(ps_venc_me0): power-controller@8018 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x8018 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(venc_me0); + power-domains = <&DIE_NODE(ps_venc_pipe5)>, <&DIE_NODE(ps_venc_pipe4)>; + }; + + DIE_NODE(ps_venc_me1): power-controller@8020 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x8020 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(venc_me1); + power-domains = <&DIE_NODE(ps_venc_me0)>; + }; +}; + +&DIE_NODE(pmgr_south) { + DIE_NODE(ps_amcc4): power-controller@100 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x100 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(amcc4); + apple,always-on; /* Memory controller */ + }; + + DIE_NODE(ps_amcc5): power-controller@108 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x108 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(amcc5); + apple,always-on; /* Memory controller */ + }; + + DIE_NODE(ps_amcc6): power-controller@110 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x110 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(amcc6); + apple,always-on; /* Memory controller */ + }; + + DIE_NODE(ps_amcc7): power-controller@118 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x118 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(amcc7); + apple,always-on; /* Memory controller */ + }; + + DIE_NODE(ps_dcs_16): power-controller@120 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x120 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_16); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_17): power-controller@128 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x128 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_17); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_18): power-controller@130 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x130 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_18); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_19): power-controller@138 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x138 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_19); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_20): power-controller@140 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x140 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_20); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_21): power-controller@148 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x148 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_21); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_22): power-controller@150 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x150 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_22); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_23): power-controller@158 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x158 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_23); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_24): power-controller@160 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x160 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_24); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_25): power-controller@168 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x168 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_25); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_26): power-controller@170 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x170 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_26); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_27): power-controller@178 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x178 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_27); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_28): power-controller@180 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x180 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_28); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_29): power-controller@188 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x188 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_29); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_30): power-controller@190 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x190 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_30); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_dcs_31): power-controller@198 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x198 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_31); + apple,always-on; /* LPDDR5 interface */ + }; + + DIE_NODE(ps_afnc4_ioa): power-controller@1a0 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc4_ioa); + apple,always-on; /* Apple Fabric */ + power-domains = <&DIE_NODE(ps_afi)>; + }; + + DIE_NODE(ps_afnc4_ls): power-controller@1a8 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc4_ls); + apple,always-on; /* Apple Fabric */ + power-domains = <&DIE_NODE(ps_afnc4_ioa)>; + }; + + DIE_NODE(ps_afnc4_lw0): power-controller@1b0 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc4_lw0); + apple,always-on; /* Apple Fabric */ + power-domains = <&DIE_NODE(ps_afnc4_ls)>; + }; + + DIE_NODE(ps_afnc5_ioa): power-controller@1b8 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc5_ioa); + apple,always-on; /* Apple Fabric */ + power-domains = <&DIE_NODE(ps_afi)>; + }; + + DIE_NODE(ps_afnc5_ls): power-controller@1c0 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1c0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc5_ls); + apple,always-on; /* Apple Fabric */ + power-domains = <&DIE_NODE(ps_afnc5_ioa)>; + }; + + DIE_NODE(ps_afnc5_lw0): power-controller@1c8 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1c8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc5_lw0); + apple,always-on; /* Apple Fabric */ + power-domains = <&DIE_NODE(ps_afnc5_ls)>; + }; + + DIE_NODE(ps_dispext2_fe): power-controller@1d0 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1d0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dispext2_fe); + power-domains = <&DIE_NODE(ps_afnc4_lw0)>; + }; + + DIE_NODE(ps_dispext2_cpu0): power-controller@1e8 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1e8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dispext2_cpu0); + power-domains = <&DIE_NODE(ps_dispext2_fe)>; + }; + + DIE_NODE(ps_dispext3_fe): power-controller@210 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x210 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dispext3_fe); + power-domains = <&DIE_NODE(ps_afnc4_lw0)>; + }; + + DIE_NODE(ps_dispext3_cpu0): power-controller@228 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x228 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dispext3_cpu0); + power-domains = <&DIE_NODE(ps_dispext3_fe)>; + }; + + DIE_NODE(ps_msr1): power-controller@250 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x250 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(msr1); + power-domains = <&DIE_NODE(ps_afnc5_lw0)>, <&DIE_NODE(ps_afr)>; + }; + + DIE_NODE(ps_msr1_ase_core): power-controller@258 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x258 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(msr1_ase_core); + power-domains = <&DIE_NODE(ps_msr1)>; + }; + + DIE_NODE(ps_venc1_sys): power-controller@260 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x260 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(venc1_sys); + power-domains = <&DIE_NODE(ps_afnc5_lw0)>, <&DIE_NODE(ps_afr)>; + }; + + /* Seems to be disabled on shipping hardware */ +#if 0 + DIE_NODE(ps_ane1_sys): power-controller@268 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x268 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(ane1_sys); + power-domains = <&DIE_NODE(ps_afnc5_lw0)>; + }; + + DIE_NODE(ps_ane1_sys_cpu): power-controller@270 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x270 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(ane1_sys_cpu); + power-domains = <&DIE_NODE(ps_ane1_sys)>; + }; +#endif + + DIE_NODE(ps_venc1_dma): power-controller@8000 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x8000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(venc1_dma); + power-domains = <&DIE_NODE(ps_venc1_sys)>; + }; + + DIE_NODE(ps_venc1_pipe4): power-controller@8008 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x8008 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(venc1_pipe4); + power-domains = <&DIE_NODE(ps_venc1_dma)>; + }; + + DIE_NODE(ps_venc1_pipe5): power-controller@8010 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x8010 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(venc1_pipe5); + power-domains = <&DIE_NODE(ps_venc1_dma)>; + }; + + DIE_NODE(ps_venc1_me0): power-controller@8018 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x8018 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(venc1_me0); + power-domains = <&DIE_NODE(ps_venc1_pipe4)>, <&DIE_NODE(ps_venc1_pipe5)>; + }; + + DIE_NODE(ps_venc1_me1): power-controller@8020 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x8020 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(venc1_me1); + power-domains = <&DIE_NODE(ps_venc1_me0)>; + }; + + DIE_NODE(ps_prores): power-controller@c000 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0xc000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(prores); + power-domains = <&DIE_NODE(ps_afnc4_lw0)>; + }; +}; + +&DIE_NODE(pmgr_mini) { + DIE_NODE(ps_debug): power-controller@58 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x58 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(debug); + apple,always-on; /* Core AON device */ + }; + + DIE_NODE(ps_nub_spmi0): power-controller@60 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x60 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(nub_spmi0); + apple,always-on; /* Core AON device */ + }; + + DIE_NODE(ps_nub_spmi1): power-controller@68 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x68 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(nub_spmi1); + apple,always-on; /* Core AON device */ + }; + + DIE_NODE(ps_nub_aon): power-controller@70 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x70 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(nub_aon); + apple,always-on; /* Core AON device */ + }; + + DIE_NODE(ps_msg): power-controller@78 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x78 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(msg); + }; + + DIE_NODE(ps_nub_gpio): power-controller@80 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(nub_gpio); + apple,always-on; /* Core AON device */ + }; + + DIE_NODE(ps_atc0_usb_aon): power-controller@88 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x88 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc0_usb_aon); + apple,always-on; /* Needs to stay on for dwc3 to work */ + }; + + DIE_NODE(ps_atc1_usb_aon): power-controller@90 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x90 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc1_usb_aon); + apple,always-on; /* Needs to stay on for dwc3 to work */ + }; + + DIE_NODE(ps_atc2_usb_aon): power-controller@98 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x98 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc2_usb_aon); + apple,always-on; /* Needs to stay on for dwc3 to work */ + }; + + DIE_NODE(ps_atc3_usb_aon): power-controller@a0 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0xa0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc3_usb_aon); + apple,always-on; /* Needs to stay on for dwc3 to work */ + }; + + DIE_NODE(ps_gp_usb_aon): power-controller@a8 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0xa8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(gp_usb_aon); + }; + + DIE_NODE(ps_nub_fabric): power-controller@b0 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0xb0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(nub_fabric); + apple,always-on; /* Core AON device */ + }; + + DIE_NODE(ps_nub_sram): power-controller@b8 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0xb8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(nub_sram); + apple,always-on; /* Core AON device */ + }; + + DIE_NODE(ps_debug_usb): power-controller@c0 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0xc0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(debug_usb); + apple,always-on; /* Core AON device */ + power-domains = <&DIE_NODE(ps_debug)>; + }; + + DIE_NODE(ps_debug_auth): power-controller@c8 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0xc8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(debug_auth); + apple,always-on; /* Core AON device */ + power-domains = <&DIE_NODE(ps_debug)>; + }; + + DIE_NODE(ps_atc0_usb): power-controller@d0 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0xd0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc0_usb); + power-domains = <&DIE_NODE(ps_atc0_usb_aon)>, <&DIE_NODE(ps_atc0_common)>; + }; + + DIE_NODE(ps_atc1_usb): power-controller@d8 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0xd8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc1_usb); + power-domains = <&DIE_NODE(ps_atc1_usb_aon)>, <&DIE_NODE(ps_atc1_common)>; + }; + + DIE_NODE(ps_atc2_usb): power-controller@e0 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0xe0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc2_usb); + power-domains = <&DIE_NODE(ps_atc2_usb_aon)>, <&DIE_NODE(ps_atc2_common)>; + }; + + DIE_NODE(ps_atc3_usb): power-controller@e8 { + compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0xe8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc3_usb); + power-domains = <&DIE_NODE(ps_atc3_usb_aon)>, <&DIE_NODE(ps_atc3_common)>; + }; +}; diff --git a/arch/arm64/boot/dts/apple/t8103-j456.dts b/arch/arm64/boot/dts/apple/t8103-j456.dts index 8c6bf9592510..83bb4dc32af9 100644 --- a/arch/arm64/boot/dts/apple/t8103-j456.dts +++ b/arch/arm64/boot/dts/apple/t8103-j456.dts @@ -14,7 +14,7 @@ / { compatible = "apple,j456", "apple,t8103", "apple,arm-platform"; - model = "Apple iMac (24-inch, 4x USB-C, M1, 2020)"; + model = "Apple iMac (24-inch, 4x USB-C, M1, 2021)"; aliases { ethernet0 = ðernet0; diff --git a/arch/arm64/boot/dts/apple/t8103-j457.dts b/arch/arm64/boot/dts/apple/t8103-j457.dts index fe7c0aaf7d62..67e433d5f8ba 100644 --- a/arch/arm64/boot/dts/apple/t8103-j457.dts +++ b/arch/arm64/boot/dts/apple/t8103-j457.dts @@ -14,7 +14,7 @@ / { compatible = "apple,j457", "apple,t8103", "apple,arm-platform"; - model = "Apple iMac (24-inch, 2x USB-C, M1, 2020)"; + model = "Apple iMac (24-inch, 2x USB-C, M1, 2021)"; aliases { ethernet0 = ðernet0; diff --git a/arch/arm64/boot/dts/apple/t8103-jxxx.dtsi b/arch/arm64/boot/dts/apple/t8103-jxxx.dtsi index 3d15b8e2a6c1..9706d26f9c64 100644 --- a/arch/arm64/boot/dts/apple/t8103-jxxx.dtsi +++ b/arch/arm64/boot/dts/apple/t8103-jxxx.dtsi @@ -78,3 +78,7 @@ apple,antenna-sku = "XX"; }; }; + +&nco_clkref { + clock-frequency = <900000000>; +}; diff --git a/arch/arm64/boot/dts/apple/t8103-pmgr.dtsi b/arch/arm64/boot/dts/apple/t8103-pmgr.dtsi index a6dbb1f485d8..9645861a858c 100644 --- a/arch/arm64/boot/dts/apple/t8103-pmgr.dtsi +++ b/arch/arm64/boot/dts/apple/t8103-pmgr.dtsi @@ -339,7 +339,7 @@ #power-domain-cells = <0>; #reset-cells = <0>; label = "sio_adma"; - power-domains = <&ps_sio>, <&ps_pms>; + power-domains = <&ps_sio>, <&ps_pms>, <&ps_audio_p>; }; ps_aes: power-controller@238 { diff --git a/arch/arm64/boot/dts/apple/t8103.dtsi b/arch/arm64/boot/dts/apple/t8103.dtsi index 51a63b29d404..6f5a2334e5b1 100644 --- a/arch/arm64/boot/dts/apple/t8103.dtsi +++ b/arch/arm64/boot/dts/apple/t8103.dtsi @@ -22,69 +22,241 @@ #address-cells = <2>; #size-cells = <0>; - cpu0: cpu@0 { + cpu-map { + cluster0 { + core0 { + cpu = <&cpu_e0>; + }; + core1 { + cpu = <&cpu_e1>; + }; + core2 { + cpu = <&cpu_e2>; + }; + core3 { + cpu = <&cpu_e3>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu_p0>; + }; + core1 { + cpu = <&cpu_p1>; + }; + core2 { + cpu = <&cpu_p2>; + }; + core3 { + cpu = <&cpu_p3>; + }; + }; + }; + + cpu_e0: cpu@0 { compatible = "apple,icestorm"; device_type = "cpu"; reg = <0x0 0x0>; enable-method = "spin-table"; cpu-release-addr = <0 0>; /* To be filled by loader */ + operating-points-v2 = <&ecluster_opp>; + capacity-dmips-mhz = <714>; + performance-domains = <&cpufreq_e>; }; - cpu1: cpu@1 { + cpu_e1: cpu@1 { compatible = "apple,icestorm"; device_type = "cpu"; reg = <0x0 0x1>; enable-method = "spin-table"; cpu-release-addr = <0 0>; /* To be filled by loader */ + operating-points-v2 = <&ecluster_opp>; + capacity-dmips-mhz = <714>; + performance-domains = <&cpufreq_e>; }; - cpu2: cpu@2 { + cpu_e2: cpu@2 { compatible = "apple,icestorm"; device_type = "cpu"; reg = <0x0 0x2>; enable-method = "spin-table"; cpu-release-addr = <0 0>; /* To be filled by loader */ + operating-points-v2 = <&ecluster_opp>; + capacity-dmips-mhz = <714>; + performance-domains = <&cpufreq_e>; }; - cpu3: cpu@3 { + cpu_e3: cpu@3 { compatible = "apple,icestorm"; device_type = "cpu"; reg = <0x0 0x3>; enable-method = "spin-table"; cpu-release-addr = <0 0>; /* To be filled by loader */ + operating-points-v2 = <&ecluster_opp>; + capacity-dmips-mhz = <714>; + performance-domains = <&cpufreq_e>; }; - cpu4: cpu@10100 { + cpu_p0: cpu@10100 { compatible = "apple,firestorm"; device_type = "cpu"; reg = <0x0 0x10100>; enable-method = "spin-table"; cpu-release-addr = <0 0>; /* To be filled by loader */ + operating-points-v2 = <&pcluster_opp>; + capacity-dmips-mhz = <1024>; + performance-domains = <&cpufreq_p>; }; - cpu5: cpu@10101 { + cpu_p1: cpu@10101 { compatible = "apple,firestorm"; device_type = "cpu"; reg = <0x0 0x10101>; enable-method = "spin-table"; cpu-release-addr = <0 0>; /* To be filled by loader */ + operating-points-v2 = <&pcluster_opp>; + capacity-dmips-mhz = <1024>; + performance-domains = <&cpufreq_p>; }; - cpu6: cpu@10102 { + cpu_p2: cpu@10102 { compatible = "apple,firestorm"; device_type = "cpu"; reg = <0x0 0x10102>; enable-method = "spin-table"; cpu-release-addr = <0 0>; /* To be filled by loader */ + operating-points-v2 = <&pcluster_opp>; + capacity-dmips-mhz = <1024>; + performance-domains = <&cpufreq_p>; }; - cpu7: cpu@10103 { + cpu_p3: cpu@10103 { compatible = "apple,firestorm"; device_type = "cpu"; reg = <0x0 0x10103>; enable-method = "spin-table"; cpu-release-addr = <0 0>; /* To be filled by loader */ + operating-points-v2 = <&pcluster_opp>; + capacity-dmips-mhz = <1024>; + performance-domains = <&cpufreq_p>; + }; + }; + + ecluster_opp: opp-table-0 { + compatible = "operating-points-v2"; + + opp01 { + opp-hz = /bits/ 64 <600000000>; + opp-level = <1>; + clock-latency-ns = <7500>; + }; + opp02 { + opp-hz = /bits/ 64 <972000000>; + opp-level = <2>; + clock-latency-ns = <22000>; + }; + opp03 { + opp-hz = /bits/ 64 <1332000000>; + opp-level = <3>; + clock-latency-ns = <27000>; + }; + opp04 { + opp-hz = /bits/ 64 <1704000000>; + opp-level = <4>; + clock-latency-ns = <33000>; + }; + opp05 { + opp-hz = /bits/ 64 <2064000000>; + opp-level = <5>; + clock-latency-ns = <50000>; + }; + }; + + pcluster_opp: opp-table-1 { + compatible = "operating-points-v2"; + + opp01 { + opp-hz = /bits/ 64 <600000000>; + opp-level = <1>; + clock-latency-ns = <8000>; + }; + opp02 { + opp-hz = /bits/ 64 <828000000>; + opp-level = <2>; + clock-latency-ns = <19000>; + }; + opp03 { + opp-hz = /bits/ 64 <1056000000>; + opp-level = <3>; + clock-latency-ns = <21000>; + }; + opp04 { + opp-hz = /bits/ 64 <1284000000>; + opp-level = <4>; + clock-latency-ns = <23000>; + }; + opp05 { + opp-hz = /bits/ 64 <1500000000>; + opp-level = <5>; + clock-latency-ns = <24000>; + }; + opp06 { + opp-hz = /bits/ 64 <1728000000>; + opp-level = <6>; + clock-latency-ns = <29000>; }; + opp07 { + opp-hz = /bits/ 64 <1956000000>; + opp-level = <7>; + clock-latency-ns = <31000>; + }; + opp08 { + opp-hz = /bits/ 64 <2184000000>; + opp-level = <8>; + clock-latency-ns = <34000>; + }; + opp09 { + opp-hz = /bits/ 64 <2388000000>; + opp-level = <9>; + clock-latency-ns = <36000>; + }; + opp10 { + opp-hz = /bits/ 64 <2592000000>; + opp-level = <10>; + clock-latency-ns = <51000>; + }; + opp11 { + opp-hz = /bits/ 64 <2772000000>; + opp-level = <11>; + clock-latency-ns = <54000>; + }; + opp12 { + opp-hz = /bits/ 64 <2988000000>; + opp-level = <12>; + clock-latency-ns = <55000>; + }; +#if 0 + /* Not available until CPU deep sleep is implemented */ + opp13 { + opp-hz = /bits/ 64 <3096000000>; + opp-level = <13>; + clock-latency-ns = <55000>; + turbo-mode; + }; + opp14 { + opp-hz = /bits/ 64 <3144000000>; + opp-level = <14>; + clock-latency-ns = <56000>; + turbo-mode; + }; + opp15 { + opp-hz = /bits/ 64 <3204000000>; + opp-level = <15>; + clock-latency-ns = <56000>; + turbo-mode; + }; +#endif }; timer { @@ -116,6 +288,16 @@ clock-output-names = "clkref"; }; + /* + * This is a fabulated representation of the input clock + * to NCO since we don't know the true clock tree. + */ + nco_clkref: clock-ref-nco { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "nco_ref"; + }; + soc { compatible = "simple-bus"; #address-cells = <2>; @@ -124,6 +306,27 @@ ranges; nonposted-mmio; + cpufreq_e: performance-controller@210e20000 { + compatible = "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq"; + reg = <0x2 0x10e20000 0 0x1000>; + #performance-domain-cells = <0>; + }; + + cpufreq_p: performance-controller@211e20000 { + compatible = "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq"; + reg = <0x2 0x11e20000 0 0x1000>; + #performance-domain-cells = <0>; + }; + + dart_sio: iommu@235004000 { + compatible = "apple,t8103-dart"; + reg = <0x2 0x35004000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 635 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + power-domains = <&ps_sio_cpu>; + }; + i2c0: i2c@235010000 { compatible = "apple,t8103-i2c", "apple,i2c"; reg = <0x2 0x35010000 0x0 0x4000>; @@ -219,6 +422,61 @@ status = "disabled"; }; + admac: dma-controller@238200000 { + compatible = "apple,t8103-admac", "apple,admac"; + reg = <0x2 0x38200000 0x0 0x34000>; + dma-channels = <24>; + interrupts-extended = <0>, + <&aic AIC_IRQ 626 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <0>; + #dma-cells = <1>; + iommus = <&dart_sio 2>; + power-domains = <&ps_sio_adma>; + resets = <&ps_audio_p>; + }; + + mca: i2s@238400000 { + compatible = "apple,t8103-mca", "apple,mca"; + reg = <0x2 0x38400000 0x0 0x18000>, + <0x2 0x38300000 0x0 0x30000>; + + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 619 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 620 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 621 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 622 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 623 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 624 IRQ_TYPE_LEVEL_HIGH>; + + resets = <&ps_audio_p>; + clocks = <&nco 0>, <&nco 1>, <&nco 2>, + <&nco 3>, <&nco 4>, <&nco 4>; + power-domains = <&ps_audio_p>, <&ps_mca0>, <&ps_mca1>, + <&ps_mca2>, <&ps_mca3>, <&ps_mca4>, <&ps_mca5>; + dmas = <&admac 0>, <&admac 1>, <&admac 2>, <&admac 3>, + <&admac 4>, <&admac 5>, <&admac 6>, <&admac 7>, + <&admac 8>, <&admac 9>, <&admac 10>, <&admac 11>, + <&admac 12>, <&admac 13>, <&admac 14>, <&admac 15>, + <&admac 16>, <&admac 17>, <&admac 18>, <&admac 19>, + <&admac 20>, <&admac 21>, <&admac 22>, <&admac 23>; + dma-names = "tx0a", "rx0a", "tx0b", "rx0b", + "tx1a", "rx1a", "tx1b", "rx1b", + "tx2a", "rx2a", "tx2b", "rx2b", + "tx3a", "rx3a", "tx3b", "rx3b", + "tx4a", "rx4a", "tx4b", "rx4b", + "tx5a", "rx5a", "tx5b", "rx5b"; + + #sound-dai-cells = <1>; + }; + + nco: clock-controller@23b044000 { + compatible = "apple,t8103-nco", "apple,nco"; + reg = <0x2 0x3b044000 0x0 0x14000>; + clocks = <&nco_clkref>; + #clock-cells = <1>; + }; + aic: interrupt-controller@23b100000 { compatible = "apple,t8103-aic", "apple,aic"; #interrupt-cells = <3>; @@ -229,12 +487,12 @@ affinities { e-core-pmu-affinity { apple,fiq-index = <AIC_CPU_PMU_E>; - cpus = <&cpu0 &cpu1 &cpu2 &cpu3>; + cpus = <&cpu_e0 &cpu_e1 &cpu_e2 &cpu_e3>; }; p-core-pmu-affinity { apple,fiq-index = <AIC_CPU_PMU_P>; - cpus = <&cpu4 &cpu5 &cpu6 &cpu7>; + cpus = <&cpu_p0 &cpu_p1 &cpu_p2 &cpu_p3>; }; }; }; diff --git a/arch/arm64/boot/dts/arm/corstone1000.dtsi b/arch/arm64/boot/dts/arm/corstone1000.dtsi index 4e46826f883a..21f1f952e985 100644 --- a/arch/arm64/boot/dts/arm/corstone1000.dtsi +++ b/arch/arm64/boot/dts/arm/corstone1000.dtsi @@ -53,6 +53,7 @@ L2_0: l2-cache0 { compatible = "cache"; + cache-unified; cache-level = <2>; cache-size = <0x80000>; cache-line-size = <64>; diff --git a/arch/arm64/boot/dts/arm/foundation-v8.dtsi b/arch/arm64/boot/dts/arm/foundation-v8.dtsi index 83e3e7e3984f..029578072d8f 100644 --- a/arch/arm64/boot/dts/arm/foundation-v8.dtsi +++ b/arch/arm64/boot/dts/arm/foundation-v8.dtsi @@ -58,6 +58,7 @@ L2_0: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; }; @@ -84,6 +85,11 @@ <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; }; + spe-pmu { + compatible = "arm,statistical-profiling-extension-v1"; + interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; + }; + watchdog@2a440000 { compatible = "arm,sbsa-gwdt"; reg = <0x0 0x2a440000 0 0x1000>, diff --git a/arch/arm64/boot/dts/arm/fvp-base-revc.dts b/arch/arm64/boot/dts/arm/fvp-base-revc.dts index 5f6f30c801a7..60472d65a355 100644 --- a/arch/arm64/boot/dts/arm/fvp-base-revc.dts +++ b/arch/arm64/boot/dts/arm/fvp-base-revc.dts @@ -47,48 +47,121 @@ compatible = "arm,armv8"; reg = <0x0 0x000>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&C0_L2>; }; cpu1: cpu@100 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x100>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&C0_L2>; }; cpu2: cpu@200 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x200>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&C0_L2>; }; cpu3: cpu@300 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x300>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&C0_L2>; }; cpu4: cpu@10000 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x10000>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&C1_L2>; }; cpu5: cpu@10100 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x10100>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&C1_L2>; }; cpu6: cpu@10200 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x10200>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&C1_L2>; }; cpu7: cpu@10300 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x10300>; enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&C1_L2>; + }; + C0_L2: l2-cache0 { + compatible = "cache"; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <512>; + cache-level = <2>; + cache-unified; + }; + + C1_L2: l2-cache1 { + compatible = "cache"; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <512>; + cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi index 2f27619d8abd..8b4d280b1e7e 100644 --- a/arch/arm64/boot/dts/arm/juno-base.dtsi +++ b/arch/arm64/boot/dts/arm/juno-base.dtsi @@ -751,12 +751,26 @@ polling-delay = <1000>; polling-delay-passive = <100>; thermal-sensors = <&scpi_sensors0 0>; + trips { + pmic_crit0: trip0 { + temperature = <90000>; + hysteresis = <2000>; + type = "critical"; + }; + }; }; soc { polling-delay = <1000>; polling-delay-passive = <100>; thermal-sensors = <&scpi_sensors0 3>; + trips { + soc_crit0: trip0 { + temperature = <80000>; + hysteresis = <2000>; + type = "critical"; + }; + }; }; big_cluster_thermal_zone: big-cluster { diff --git a/arch/arm64/boot/dts/arm/juno-r1.dts b/arch/arm64/boot/dts/arm/juno-r1.dts index 6451c62146fd..1d90eeebb37d 100644 --- a/arch/arm64/boot/dts/arm/juno-r1.dts +++ b/arch/arm64/boot/dts/arm/juno-r1.dts @@ -189,6 +189,7 @@ A57_L2: l2-cache0 { compatible = "cache"; + cache-unified; cache-size = <0x200000>; cache-line-size = <64>; cache-sets = <2048>; @@ -197,6 +198,7 @@ A53_L2: l2-cache1 { compatible = "cache"; + cache-unified; cache-size = <0x100000>; cache-line-size = <64>; cache-sets = <1024>; diff --git a/arch/arm64/boot/dts/arm/juno-r2.dts b/arch/arm64/boot/dts/arm/juno-r2.dts index 438cd1ff4bd0..d2ada69b0a43 100644 --- a/arch/arm64/boot/dts/arm/juno-r2.dts +++ b/arch/arm64/boot/dts/arm/juno-r2.dts @@ -195,6 +195,7 @@ A72_L2: l2-cache0 { compatible = "cache"; + cache-unified; cache-size = <0x200000>; cache-line-size = <64>; cache-sets = <2048>; @@ -203,6 +204,7 @@ A53_L2: l2-cache1 { compatible = "cache"; + cache-unified; cache-size = <0x100000>; cache-line-size = <64>; cache-sets = <1024>; diff --git a/arch/arm64/boot/dts/arm/juno.dts b/arch/arm64/boot/dts/arm/juno.dts index cf4a58211399..5e48a01a5b9f 100644 --- a/arch/arm64/boot/dts/arm/juno.dts +++ b/arch/arm64/boot/dts/arm/juno.dts @@ -194,6 +194,7 @@ A57_L2: l2-cache0 { compatible = "cache"; + cache-unified; cache-size = <0x200000>; cache-line-size = <64>; cache-sets = <2048>; @@ -202,6 +203,7 @@ A53_L2: l2-cache1 { compatible = "cache"; + cache-unified; cache-size = <0x100000>; cache-line-size = <64>; cache-sets = <1024>; diff --git a/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts b/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts index 258991ad7cc0..ef68f5aae7dd 100644 --- a/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts +++ b/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts @@ -71,6 +71,7 @@ L2_0: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts b/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts index 5b6d9d8e934d..796cd7d02eb5 100644 --- a/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts +++ b/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts @@ -57,6 +57,7 @@ L2_0: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi index dac9d3b4e91d..eb2a78f4e033 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi @@ -63,6 +63,7 @@ l2: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; }; @@ -283,6 +284,11 @@ #address-cells = <1>; #size-cells = <1>; + timer@0 { + compatible = "brcm,bcm63138-timer"; + reg = <0x0 0x28>; + }; + watchdog@28 { compatible = "brcm,bcm6345-wdt"; reg = <0x28 0x8>; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi index 3d016c2ce675..d5bc31980f03 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi @@ -51,6 +51,7 @@ L2_0: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi index 04de96bd0a03..6f805266d3c9 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi @@ -35,6 +35,7 @@ L2_0: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi index 13629702f70b..b982249b80a2 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi @@ -51,6 +51,7 @@ L2_0: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi index c3e6197be808..a996d436e977 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi @@ -51,6 +51,7 @@ L2_0: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi index 0bce6497219f..62c530d4b103 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi @@ -35,6 +35,7 @@ L2_0: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi index 29a880c6c858..34c7b513d363 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi @@ -50,6 +50,7 @@ }; L2_0: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; }; @@ -109,6 +110,25 @@ #size-cells = <1>; ranges = <0x0 0x0 0xff800000 0x62000>; + twd: timer-mfd@400 { + compatible = "brcm,bcm4908-twd", "simple-mfd", "syscon"; + reg = <0x400 0x4c>; + ranges = <0x0 0x400 0x4c>; + + #address-cells = <1>; + #size-cells = <1>; + + timer@0 { + compatible = "brcm,bcm63138-timer"; + reg = <0x0 0x28>; + }; + + watchdog@28 { + compatible = "brcm,bcm6345-wdt"; + reg = <0x28 0x8>; + }; + }; + uart0: serial@640 { compatible = "brcm,bcm6345-uart"; reg = <0x640 0x18>; diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts b/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts index e34172e3117e..fbf0392b8371 100644 --- a/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts +++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts @@ -52,7 +52,7 @@ memory { device_type = "memory"; - reg = <0x000000000 0x80000000 0x00000000 0x40000000>; + reg = <0x00000000 0x80000000 0x00000000 0x40000000>; }; }; diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts b/arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts index 7bf26f3e36bf..699f7742ce7f 100644 --- a/arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts +++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts @@ -49,7 +49,7 @@ memory { device_type = "memory"; - reg = <0x000000000 0x80000000 0x00000001 0x00000000>; + reg = <0x00000000 0x80000000 0x00000001 0x00000000>; }; }; diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi index fda97c47f4e9..18cdbc20f03f 100644 --- a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi +++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi @@ -79,6 +79,7 @@ CLUSTER0_L2: l2-cache@0 { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi index 8f8c25e51194..e05901abe957 100644 --- a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi +++ b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi @@ -108,18 +108,22 @@ CLUSTER0_L2: l2-cache@0 { compatible = "cache"; + cache-level = <2>; }; CLUSTER1_L2: l2-cache@100 { compatible = "cache"; + cache-level = <2>; }; CLUSTER2_L2: l2-cache@200 { compatible = "cache"; + cache-level = <2>; }; CLUSTER3_L2: l2-cache@300 { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 3ea9edc87909..ef6f364eaa18 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -57,10 +57,12 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-emcon-avari.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-ctouch2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-edimm2.2.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-innocomm-wb15-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-bl.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-bl-osm-s.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-mx8menlo.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-nitrogen-r2.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-phg.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-phyboard-polis-rdk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-tqma8mqml-mba8mx.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dtso index f826392c23fa..f826392c23fa 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dtso diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dtso index b949cac03742..b949cac03742 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dtso diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dtso index 1dff68d7484b..1dff68d7484b 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dtso diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dtso index 19424d349713..19424d349713 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dtso diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dtso index fb85847f778f..fb85847f778f 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dtso diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dtso index 63e46fad22bd..63e46fad22bd 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dtso diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index ac1c3a7e5f7a..1b33cabb4e14 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -46,6 +46,7 @@ l2: l2-cache { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index 704f72caddd3..b9fd24cdc919 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -84,6 +84,7 @@ l2: l2-cache { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi index 3d9e29824bb2..a01e3cfec77f 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi @@ -79,6 +79,7 @@ l2: l2-cache { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi index a2cadf757148..1e5d76c4d83d 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi @@ -95,18 +95,22 @@ cluster0_l2: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; cluster1_l2: l2-cache1 { compatible = "cache"; + cache-level = <2>; }; cluster2_l2: l2-cache2 { compatible = "cache"; + cache-level = <2>; }; cluster3_l2: l2-cache3 { compatible = "cache"; + cache-level = <2>; }; CPU_PW20: cpu-pw20 { diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi index c3dc38188c17..c12c86915ec8 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi @@ -95,18 +95,22 @@ cluster0_l2: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; cluster1_l2: l2-cache1 { compatible = "cache"; + cache-level = <2>; }; cluster2_l2: l2-cache2 { compatible = "cache"; + cache-level = <2>; }; cluster3_l2: l2-cache3 { compatible = "cache"; + cache-level = <2>; }; CPU_PW20: cpu-pw20 { diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi index 6680fb2a6dc9..e5215ed0975e 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -300,6 +300,7 @@ cluster0_l2: l2-cache0 { compatible = "cache"; + cache-unified; cache-size = <0x100000>; cache-line-size = <64>; cache-sets = <1024>; @@ -308,6 +309,7 @@ cluster1_l2: l2-cache1 { compatible = "cache"; + cache-unified; cache-size = <0x100000>; cache-line-size = <64>; cache-sets = <1024>; @@ -316,6 +318,7 @@ cluster2_l2: l2-cache2 { compatible = "cache"; + cache-unified; cache-size = <0x100000>; cache-line-size = <64>; cache-sets = <1024>; @@ -324,6 +327,7 @@ cluster3_l2: l2-cache3 { compatible = "cache"; + cache-unified; cache-size = <0x100000>; cache-line-size = <64>; cache-sets = <1024>; @@ -332,6 +336,7 @@ cluster4_l2: l2-cache4 { compatible = "cache"; + cache-unified; cache-size = <0x100000>; cache-line-size = <64>; cache-sets = <1024>; @@ -340,6 +345,7 @@ cluster5_l2: l2-cache5 { compatible = "cache"; + cache-unified; cache-size = <0x100000>; cache-line-size = <64>; cache-sets = <1024>; @@ -348,6 +354,7 @@ cluster6_l2: l2-cache6 { compatible = "cache"; + cache-unified; cache-size = <0x100000>; cache-line-size = <64>; cache-sets = <1024>; @@ -356,6 +363,7 @@ cluster7_l2: l2-cache7 { compatible = "cache"; + cache-unified; cache-size = <0x100000>; cache-line-size = <64>; cache-sets = <1024>; diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi index 82a1c4488378..bf72732e311a 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi @@ -34,6 +34,35 @@ conn_subsys: bus@5b000000 { clock-output-names = "conn_ipg_clk"; }; + usbotg1: usb@5b0d0000 { + compatible = "fsl,imx7ulp-usb"; + reg = <0x5b0d0000 0x200>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; + fsl,usbphy = <&usbphy1>; + fsl,usbmisc = <&usbmisc1 0>; + clocks = <&usb2_lpcg 0>; + ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x10>; + rx-burst-size-dword = <0x10>; + power-domains = <&pd IMX_SC_R_USB_0>; + status = "disabled"; + }; + + usbmisc1: usbmisc@5b0d0200 { + #index-cells = <1>; + compatible = "fsl,imx7ulp-usbmisc", "fsl,imx6q-usbmisc"; + reg = <0x5b0d0200 0x200>; + }; + + usbphy1: usbphy@5b100000 { + compatible = "fsl,imx7ulp-usbphy"; + reg = <0x5b100000 0x1000>; + clocks = <&usb2_lpcg 1>; + power-domains = <&pd IMX_SC_R_USB_0_PHY>; + status = "disabled"; + }; + usdhc1: mmc@5b010000 { interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; reg = <0x5b010000 0x10000>; @@ -195,4 +224,14 @@ conn_subsys: bus@5b000000 { "enet1_lpcg_ipg_s_clk"; power-domains = <&pd IMX_SC_R_ENET_1>; }; + + usb2_lpcg: clock-controller@5b270000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5b270000 0x10000>; + #clock-cells = <1>; + clocks = <&conn_ahb_clk>, <&conn_ipg_clk>; + clock-indices = <IMX_LPCG_CLK_6>, <IMX_LPCG_CLK_7>; + clock-output-names = "usboh3_ahb_clk", "usboh3_phy_ipg_clk"; + power-domains = <&pd IMX_SC_R_USB_0_PHY>; + }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi index d7b4229bb4a2..a943a1e2797f 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi @@ -20,6 +20,70 @@ dma_subsys: bus@5a000000 { clock-output-names = "dma_ipg_clk"; }; + lpspi0: spi@5a000000 { + compatible = "fsl,imx7ulp-spi"; + reg = <0x5a000000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&spi0_lpcg 0>, + <&spi0_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_SPI_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <20000000>; + power-domains = <&pd IMX_SC_R_SPI_0>; + status = "disabled"; + }; + + lpspi1: spi@5a010000 { + compatible = "fsl,imx7ulp-spi"; + reg = <0x5a010000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&spi1_lpcg 0>, + <&spi1_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_SPI_1 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <60000000>; + power-domains = <&pd IMX_SC_R_SPI_1>; + status = "disabled"; + }; + + lpspi2: spi@5a020000 { + compatible = "fsl,imx7ulp-spi"; + reg = <0x5a020000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&spi2_lpcg 0>, + <&spi2_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_SPI_2 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <60000000>; + power-domains = <&pd IMX_SC_R_SPI_2>; + status = "disabled"; + }; + + lpspi3: spi@5a030000 { + compatible = "fsl,imx7ulp-spi"; + reg = <0x5a030000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&spi3_lpcg 0>, + <&spi3_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_SPI_3 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <60000000>; + power-domains = <&pd IMX_SC_R_SPI_3>; + status = "disabled"; + }; + lpuart0: serial@5a060000 { reg = <0x5a060000 0x1000>; interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; @@ -60,6 +124,54 @@ dma_subsys: bus@5a000000 { status = "disabled"; }; + spi0_lpcg: clock-controller@5a400000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5a400000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_SPI_0 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>; + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; + clock-output-names = "spi0_lpcg_clk", + "spi0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SPI_0>; + }; + + spi1_lpcg: clock-controller@5a410000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5a410000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_SPI_1 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>; + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; + clock-output-names = "spi1_lpcg_clk", + "spi1_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SPI_1>; + }; + + spi2_lpcg: clock-controller@5a420000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5a420000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_SPI_2 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>; + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; + clock-output-names = "spi2_lpcg_clk", + "spi2_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SPI_2>; + }; + + spi3_lpcg: clock-controller@5a430000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5a430000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_SPI_3 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>; + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; + clock-output-names = "spi3_lpcg_clk", + "spi3_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SPI_3>; + }; + uart0_lpcg: clock-controller@5a460000 { compatible = "fsl,imx8qxp-lpcg"; reg = <0x5a460000 0x10000>; @@ -156,6 +268,34 @@ dma_subsys: bus@5a000000 { status = "disabled"; }; + adc0: adc@5a880000 { + compatible = "nxp,imx8qxp-adc"; + reg = <0x5a880000 0x10000>; + interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&adc0_lpcg 0>, + <&adc0_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_ADC_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_ADC_0>; + status = "disabled"; + }; + + adc1: adc@5a890000 { + compatible = "nxp,imx8qxp-adc"; + reg = <0x5a890000 0x10000>; + interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&adc1_lpcg 0>, + <&adc1_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_ADC_1 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_ADC_1>; + status = "disabled"; + }; + i2c0_lpcg: clock-controller@5ac00000 { compatible = "fsl,imx8qxp-lpcg"; reg = <0x5ac00000 0x10000>; @@ -203,4 +343,28 @@ dma_subsys: bus@5a000000 { "i2c3_lpcg_ipg_clk"; power-domains = <&pd IMX_SC_R_I2C_3>; }; + + adc0_lpcg: clock-controller@5ac80000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5ac80000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_ADC_0 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>; + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; + clock-output-names = "adc0_lpcg_clk", + "adc0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_ADC_0>; + }; + + adc1_lpcg: clock-controller@5ac90000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5ac90000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_ADC_1 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>; + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; + clock-output-names = "adc1_lpcg_clk", + "adc1_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_ADC_1>; + }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi index 6446e6df7a9a..1f3d225e64ec 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi @@ -11,7 +11,8 @@ lsio_subsys: bus@5d000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; - ranges = <0x5d000000 0x0 0x5d000000 0x1000000>; + ranges = <0x5d000000 0x0 0x5d000000 0x1000000>, + <0x08000000 0x0 0x08000000 0x10000000>; lsio_mem_clk: clock-lsio-mem { compatible = "fixed-clock"; @@ -107,6 +108,20 @@ lsio_subsys: bus@5d000000 { power-domains = <&pd IMX_SC_R_GPIO_7>; }; + flexspi0: spi@5d120000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,imx8qxp-fspi"; + reg = <0x5d120000 0x10000>, <0x08000000 0x10000000>; + reg-names = "fspi_base", "fspi_mmap"; + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX_SC_R_FSPI_0 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_FSPI_0 IMX_SC_PM_CLK_PER>; + clock-names = "fspi", "fspi_en"; + power-domains = <&pd IMX_SC_R_FSPI_0>; + status = "disabled"; + }; + lsio_mu0: mailbox@5d1b0000 { reg = <0x5d1b0000 0x10000>; interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts index ca2a43e0cbf6..280a9c9d8bd9 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts @@ -90,6 +90,28 @@ enable-active-high; off-on-delay-us = <3480>; }; + + reg_vref_1v8: regulator-adc-vref { + compatible = "regulator-fixed"; + regulator-name = "vref_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + mii_select: regulator-4 { + compatible = "regulator-fixed"; + regulator-name = "mii-select"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&scu_gpio 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; +}; + +&adc0 { + vref-supply = <®_vref_1v8>; + status = "okay"; }; &eqos { @@ -159,6 +181,23 @@ }; }; +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + nxp,fspi-dll-slvdly = <4>; + status = "okay"; + + mt35xu512aba0: flash@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <133000000>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + }; +}; + &i2c2 { #address-cells = <1>; #size-cells = <0>; @@ -266,6 +305,40 @@ }; }; +&usbphy1 { + /* USB eye diagram tests result */ + fsl,tx-d-cal = <114>; + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + srp-disable; + hnp-disable; + adp-disable; + power-active-high; + disable-over-current; + status = "okay"; +}; + +&usbphy2 { + /* USB eye diagram tests result */ + fsl,tx-d-cal = <111>; + status = "okay"; +}; + +&usbotg2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg2>; + srp-disable; + hnp-disable; + adp-disable; + power-active-high; + disable-over-current; + status = "okay"; +}; + &usdhc1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc1>; @@ -286,6 +359,21 @@ status = "okay"; }; +&lpspi3 { + fsl,spi-num-chipselects = <1>; + fsl,spi-only-use-cs1-sel; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi3>; + pinctrl-assert-gpios = <&pca6416_1 7 GPIO_ACTIVE_HIGH>; + status = "okay"; + + spidev0: spi@0 { + reg = <0>; + compatible = "rohm,dh2228fv"; + spi-max-frequency = <30000000>; + }; +}; + &iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog>; @@ -330,6 +418,25 @@ >; }; + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + IMX8DXL_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 + IMX8DXL_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 + IMX8DXL_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 + IMX8DXL_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 + IMX8DXL_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 + IMX8DXL_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 + IMX8DXL_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 + IMX8DXL_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021 + IMX8DXL_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021 + IMX8DXL_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021 + IMX8DXL_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021 + IMX8DXL_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021 + IMX8DXL_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021 + IMX8DXL_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021 + >; + }; + pinctrl_fec1: fec1grp { fsl,pins = < IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi index 795d1d472fae..6881330ab4c6 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi @@ -11,6 +11,10 @@ clock-frequency = <160000000>; }; +&adc0 { + interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; +}; + &i2c0 { compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; @@ -50,3 +54,19 @@ compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; }; + +&lpspi0 { + interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>; +}; + +&lpspi1 { + interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>; +}; + +&lpspi2 { + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; +}; + +&lpspi3 { + interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi index 69c4849f2132..6b416fb760d5 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi @@ -140,3 +140,13 @@ compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc"; interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; }; + +&usbotg1 { + interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; + /* + * usbotg1 and usbotg2 share one clock + * scfw disable clock access and keep it always on + * in case other core (M4) use one of these. + */ + clocks = <&clk_dummy>; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi index 815bd987b09b..5f4f789e4a73 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi @@ -3,44 +3,90 @@ * Copyright 2019~2020, 2022 NXP */ +&flexspi0 { + compatible = "nxp,imx8dxl-fspi"; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; +}; + &lsio_gpio0 { compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; + gpio-ranges = <&iomuxc 0 47 13>, + <&iomuxc 13 61 4>, + <&iomuxc 19 67 4>, + <&iomuxc 24 72 1>; }; &lsio_gpio1 { compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; + gpio-ranges = <&iomuxc 4 74 5>, + <&iomuxc 9 80 16>; }; &lsio_gpio2 { compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; + gpio-ranges = <&iomuxc 1 98 2>, + <&iomuxc 3 101 1>, + <&iomuxc 5 107 8>; }; &lsio_gpio3 { compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; + gpio-ranges = <&iomuxc 0 115 4>, + <&iomuxc 9 121 1>, + <&iomuxc 10 120 1>, + <&iomuxc 11 123 1>, + <&iomuxc 12 122 1>, + <&iomuxc 13 125 1>, + <&iomuxc 14 124 1>, + <&iomuxc 16 126 1>, + <&iomuxc 17 128 1>, + <&iomuxc 18 131 1>, + <&iomuxc 19 130 1>, + <&iomuxc 20 133 1>, + <&iomuxc 21 132 1>, + <&iomuxc 22 129 1>, + <&iomuxc 23 134 1>; }; &lsio_gpio4 { compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; + gpio-ranges = <&iomuxc 0 0 3>, + <&iomuxc 3 4 4>, + <&iomuxc 7 9 12>, + <&iomuxc 19 22 2>, + <&iomuxc 21 25 2>, + <&iomuxc 29 29 3>; }; &lsio_gpio5 { compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + gpio-ranges = <&iomuxc 0 32 3>, + <&iomuxc 3 36 6>, + <&iomuxc 9 43 3>; }; &lsio_gpio6 { compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; + gpio-ranges = <&iomuxc 0 53 7>, + <&iomuxc 8 86 10>, + <&iomuxc 19 107 8>; }; &lsio_gpio7 { compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + gpio-ranges = <&iomuxc 0 0 3>, + <&iomuxc 3 4 4>, + <&iomuxc 8 22 2>, + <&iomuxc 10 25 2>, + <&iomuxc 16 44 2>; }; &lsio_mu0 { diff --git a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi index 5ddbda0b4def..0c64b9194621 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi @@ -59,6 +59,7 @@ A35_L2: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; }; @@ -133,6 +134,12 @@ clock-names = "xtal_32KHz", "xtal_24Mhz"; }; + scu_gpio: gpio { + compatible = "fsl,imx8qxp-sc-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + iomuxc: pinctrl { compatible = "fsl,imx8dxl-iomuxc"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi index cf07987ccc10..201325f566cb 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi @@ -47,15 +47,15 @@ ddrc_opp_table: opp-table { compatible = "operating-points-v2"; - opp-25M { + opp-25000000 { opp-hz = /bits/ 64 <25000000>; }; - opp-100M { + opp-100000000 { opp-hz = /bits/ 64 <100000000>; }; - opp-750M { + opp-750000000 { opp-hz = /bits/ 64 <750000000>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts index 778bdbe228d3..24f61db33eba 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts @@ -46,6 +46,12 @@ clock-frequency = <25000000>; }; + clk_xtal32k: clk-xtal32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + panel: panel { backlight = <&backlight>; power-supply = <®_panel_vcc>; @@ -77,12 +83,11 @@ enable-active-high; }; - watchdog-gpio { + watchdog { /* TPS3813 */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_watchdog_gpio>; compatible = "linux,wdt-gpio"; - always-enabled; gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; hw_algo = "level"; /* Reset triggers in 2..3 seconds */ @@ -114,15 +119,15 @@ ddrc_opp_table: opp-table { compatible = "operating-points-v2"; - opp-25M { + opp-25000000 { opp-hz = /bits/ 64 <25000000>; }; - opp-100M { + opp-100000000 { opp-hz = /bits/ 64 <100000000>; }; - opp-750M { + opp-750000000 { opp-hz = /bits/ 64 <750000000>; }; }; @@ -183,8 +188,6 @@ reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; reset-assert-us = <10000>; reset-deassert-us = <10000>; - qca,clk-out-frequency = <125000000>; - qca,clk-out-strength = <AR803X_STRENGTH_FULL>; qca,keep-pll-enabled; vddio-supply = <&vddio>; @@ -271,6 +274,9 @@ pmic: pmic@4b { compatible = "rohm,bd71847"; reg = <0x4b>; + #clock-cells = <0>; + clocks = <&clk_xtal32k 0>; + clock-output-names = "clk-32k-out"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pmic>; interrupt-parent = <&gpio1>; @@ -928,6 +934,10 @@ status = "disabled"; }; +&snvs_rtc { + clocks = <&pmic>; +}; + &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts index a2b24d4d4e3e..b68954bcc383 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts @@ -23,15 +23,15 @@ ddrc_opp_table: opp-table { compatible = "operating-points-v2"; - opp-25M { + opp-25000000 { opp-hz = /bits/ 64 <25000000>; }; - opp-100M { + opp-100000000 { opp-hz = /bits/ 64 <100000000>; }; - opp-750M { + opp-750000000 { opp-hz = /bits/ 64 <750000000>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi index 7d6317d95b13..e0b604ac0da4 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi @@ -56,6 +56,7 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <20000>; enable-active-high; }; @@ -343,6 +344,7 @@ reg = <0x20>; gpio-controller; #gpio-cells = <2>; + vcc-supply = <&buck4_reg>; }; }; @@ -399,6 +401,10 @@ status = "okay"; }; +&usbphynop1 { + wakeup-source; +}; + &usbotg1 { dr_mode = "otg"; hnp-disable; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15-evk.dts b/arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15-evk.dts new file mode 100644 index 000000000000..055faae79930 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15-evk.dts @@ -0,0 +1,146 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2018 Bang & Olufsen + * Copyright 2022 Pengutronix + */ + +/dts-v1/; + +#include "imx8mm-innocomm-wb15.dtsi" + +/ { + model = "InnoComm WB15-EVK"; + compatible = "innocomm,wb15-evk", "fsl,imx8mm"; + + chosen { + stdout-path = &uart2; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led-0 { + label = "debug"; + gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + reg_vsd_3v3: regulator-vsd-3v3 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_vsd_3v3>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_ethphy: regulator-eth-phy { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec_phy_reg>; + regulator-name = "PHY_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec_phy>; + reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; + phy-supply = <®_ethphy>; + }; + }; +}; + +&uart2 { + status = "okay"; +}; + +&usbotg1 { + dr_mode = "otg"; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + disable-over-current; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + disable-over-current; + status = "okay"; +}; + +&usdhc2 { + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_vsd_3v3>; + status = "okay"; +}; + +&iomuxc { + pinctrl_fec: fec-grp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x03 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x03 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + >; + }; + + pinctrl_fec_phy: fec-phy-grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 + >; + }; + + pinctrl_fec_phy_reg: fec-phy-reg-grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x16 + >; + }; + + pinctrl_gpio_leds: led-grp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0xd6 + >; + }; + + pinctrl_reg_vsd_3v3: reg-vsd-3v3-grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi new file mode 100644 index 000000000000..44e87b1568e7 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-innocomm-wb15.dtsi @@ -0,0 +1,480 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2018 Bang & Olufsen + */ + +#include "imx8mm.dtsi" +#include <dt-bindings/phy/phy-imx8-pcie.h> + +/ { + reg_modem: regulator-modem { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_modem_regulator>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "epdev_on"; + gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_3v3_out: regulator-3v3-out { + compatible = "regulator-fixed"; + regulator-name = "3V3_OUT"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&cpu_alert0 { + temperature = <95000>; +}; + +&cpu_crit0 { + temperature = <105000>; +}; + +&ddrc { + operating-points-v2 = <&ddrc_opp_table>; + + ddrc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-25000000 { + opp-hz = /bits/ 64 <25000000>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pmic@4b { + compatible = "rohm,bd71847"; + reg = <0x4b>; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + rohm,reset-snvs-powered; + + regulators { + buck1_reg: BUCK1 { + regulator-name = "buck1"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + rohm,dvs-run-voltage = <850000>; + rohm,dvs-idle-voltage = <850000>; + rohm,dvs-suspend-voltage = <850000>; + }; + + buck2_reg: BUCK2 { + regulator-name = "buck2"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + rohm,dvs-run-voltage = <1000000>; + rohm,dvs-idle-voltage = <900000>; + }; + + buck3_reg: BUCK3 { + // buck5 in datasheet + regulator-name = "buck3"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + buck4_reg: BUCK4 { + // buck6 in datasheet + regulator-name = "buck4"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5_reg: BUCK5 { + // buck7 in datasheet + regulator-name = "buck5"; + regulator-min-microvolt = <1605000>; + regulator-max-microvolt = <1995000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6_reg: BUCK6 { + // buck8 in datasheet + regulator-name = "buck6"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: LDO1 { + regulator-name = "ldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: LDO2 { + regulator-name = "ldo2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: LDO3 { + regulator-name = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: LDO4 { + regulator-name = "ldo4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5_reg: LDO5 { + regulator-name = "ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + ldo6_reg: LDO6 { + regulator-name = "ldo6"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&i2c3 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +}; + +&pcie_phy { + fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>; + fsl,tx-deemph-gen1 = <0x2d>; + fsl,tx-deemph-gen2 = <0xf>; + status = "okay"; +}; + +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + reset-gpio = <&gpio5 21 GPIO_ACTIVE_LOW>; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_PHY>, + <&clk IMX8MM_CLK_PCIE1_AUX>; + clock-names = "pcie", "pcie_bus", "pcie_aux"; + fsl,max-link-speed = <1>; + assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, <&clk IMX8MM_CLK_PCIE1_CTRL>; + assigned-clock-rates = <10000000>, <250000000>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, <&clk IMX8MM_SYS_PLL2_250M>; + status = "okay"; +}; + +&uart1 { /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MM_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm4349-bt"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_modem_bt>; + device-wakeup-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; + vbat-supply = <®_3v3_out>; + vddio-supply = <®_3v3_out>; + clocks = <&osc_32k>; + max-speed = <3000000>; + clock-names = "extclk"; + }; +}; + +&uart2 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + bus-width = <8>; + no-sd; + no-sdio; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&A53_0 { + cpu-supply = <&buck2_reg>; +}; + +&A53_1 { + cpu-supply = <&buck2_reg>; +}; + +&A53_2 { + cpu-supply = <&buck2_reg>; +}; + +&A53_3 { + cpu-supply = <&buck2_reg>; +}; + +/delete-node/ &sec_jr1; /* Job ring in use by OP-TEE */ + +&iomuxc { + pinctrl_i2c1: i2c1-grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_i2c1_gpio: i2c1-gpio-grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3 + >; + }; + + pinctrl_i2c2: i2c2-grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_i2c2_gpio: i2c2-gpio-grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3 + MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3 + >; + }; + + pinctrl_i2c3: i2c3-grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_i2c3_gpio: i2c3-gpio-grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3 + MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3 + >; + }; + + pinctrl_pcie0: pcie0-grp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x61 + MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x6 + >; + }; + + pinctrl_modem_bt: modem-bt-grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 0x19 + MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x19 + MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x19 + MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x19 + MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141 + >; + }; + + pinctrl_modem_regulator: modem-reg-grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x41 + >; + }; + + pinctrl_pmic: pmic-irq-grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 + >; + }; + + pinctrl_uart1: uart1-grp { + fsl,pins = < + MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 + MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 + MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140 + MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140 + >; + }; + + pinctrl_uart2: uart2-grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + >; + }; + + pinctrl_usdhc1: usdhc1-grp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000190 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0 + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0 + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0 + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0 + MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190 + MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d0 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000194 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4 + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4 + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4 + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4 + MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194 + MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d4 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000196 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6 + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6 + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6 + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6 + MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196 + MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d6 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2-gpio-grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x1d0 + >; + }; + + pinctrl_usdhc2: usdhc2-grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_wdog: wdog-grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi index 8d10f5b41297..5172883717d1 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi @@ -47,11 +47,11 @@ ddrc_opp_table: opp-table { compatible = "operating-points-v2"; - opp-100M { + opp-100000000 { opp-hz = /bits/ 64 <100000000>; }; - opp-750M { + opp-750000000 { opp-hz = /bits/ 64 <750000000>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-sl.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-kontron-sl.dtsi index 0679728d2489..1f8326613ee9 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-sl.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-sl.dtsi @@ -46,11 +46,11 @@ ddrc_opp_table: opp-table { compatible = "operating-points-v2"; - opp-100M { + opp-100000000 { opp-hz = /bits/ 64 <100000000>; }; - opp-750M { + opp-750000000 { opp-hz = /bits/ 64 <750000000>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phg.dts b/arch/arm64/boot/dts/freescale/imx8mm-phg.dts new file mode 100644 index 000000000000..e9447738b104 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-phg.dts @@ -0,0 +1,266 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Fabio Estevam <festevam@denx.de> + */ + +/dts-v1/; + +#include "imx8mm-tqma8mqml.dtsi" + +/ { + model = "Cloos i.MX8MM PHG board"; + compatible = "cloos,imx8mm-phg", "tq,imx8mm-tqma8mqml", "fsl,imx8mm"; + + aliases { + mmc0 = &usdhc3; + mmc1 = &usdhc2; + }; + + chosen { + stdout-path = &uart2; + }; + + beeper { + compatible = "gpio-beeper"; + pinctrl-0 = <&pinctrl_beeper>; + gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_led>; + + led-0 { + label = "status1"; + gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + }; + + led-1 { + label = "status2"; + gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + }; + + led-2 { + label = "status3"; + gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; + }; + + led-3 { + label = "run"; + gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + }; + + led-4 { + label = "powerled"; + gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + }; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_otg_vbus_ctrl>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio2 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: regulator-vmmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + off-on-delay-us = <12000>; + }; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + reg = <0>; + compatible = "ethernet-phy-ieee802.3-c22"; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usbphynop1 { + power-domains = <&pgc_otg1>; +}; + +&usbphynop2 { + power-domains = <&pgc_otg2>; +}; + +&usbotg1 { + dr_mode = "host"; + vbus-supply = <®_usb_otg_vbus>; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + status = "okay"; +}; + +&usdhc2 { + assigned-clocks = <&clk IMX8MM_CLK_USDHC2>; + assigned-clock-rates = <400000000>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_400M>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + disable-wp; + no-mmc; + no-sdio; + sd-uhs-sdr104; + sd-uhs-ddr50; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&iomuxc { + pinctrl_beeper: beepergrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x19 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 + MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 + MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 + MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x40000002 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x40000002 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x14 + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x14 + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x14 + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x14 + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x90 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x90 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x90 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x90 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x14 + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x90 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x90 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x14 + MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x10 + >; + }; + + pinctrl_gpio_led: gpioledgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19 + MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 + MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x19 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_otg_vbus_ctrl: otgvbusctrlgrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2 0x119 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpiogrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi index 995b44efb1b6..92616bc4f71f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi @@ -53,15 +53,15 @@ ddrc_opp_table: opp-table { compatible = "operating-points-v2"; - opp-25M { + opp-25000000 { opp-hz = /bits/ 64 <25000000>; }; - opp-100M { + opp-100000000 { opp-hz = /bits/ 64 <100000000>; }; - opp-750M { + opp-750000000 { opp-hz = /bits/ 64 <750000000>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi index a0bd540f27d3..ae0721b807e1 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi @@ -53,15 +53,15 @@ ddrc_opp_table: opp-table { compatible = "operating-points-v2"; - opp-25M { + opp-25000000 { opp-hz = /bits/ 64 <25000000>; }; - opp-100M { + opp-100000000 { opp-hz = /bits/ 64 <100000000>; }; - opp-750M { + opp-750000000 { opp-hz = /bits/ 64 <750000000>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi index 66a0d103c90f..9e7d38872157 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi @@ -81,15 +81,15 @@ ddrc_opp_table: opp-table { compatible = "operating-points-v2"; - opp-25M { + opp-25000000 { opp-hz = /bits/ 64 <25000000>; }; - opp-100M { + opp-100000000 { opp-hz = /bits/ 64 <100000000>; }; - opp-750M { + opp-750000000 { opp-hz = /bits/ 64 <750000000>; }; }; @@ -119,8 +119,11 @@ &i2c1 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; gsc: gsc@20 { @@ -365,8 +368,11 @@ &i2c2 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; eeprom@52 { @@ -435,6 +441,13 @@ >; }; + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3 + >; + }; + pinctrl_i2c2: i2c2grp { fsl,pins = < MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 @@ -442,6 +455,13 @@ >; }; + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3 + MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3 + >; + }; + pinctrl_uart2: uart2grp { fsl,pins = < MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-imx219.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-imx219.dtso index 4eaf8aabcbff..4eaf8aabcbff 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-imx219.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-imx219.dtso diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs232-rts.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs232-rts.dtso index 3ea73a6886ff..3ea73a6886ff 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs232-rts.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs232-rts.dtso diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs422.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs422.dtso index c3cd9f2b0db3..c3cd9f2b0db3 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs422.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs422.dtso diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs485.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs485.dtso index cc0a287226ab..cc0a287226ab 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs485.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs485.dtso diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-imx219.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-imx219.dtso index f3ece4b7fbbd..f3ece4b7fbbd 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-imx219.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-imx219.dtso diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs232-rts.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs232-rts.dtso index 2fa635e1c1a8..2fa635e1c1a8 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs232-rts.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs232-rts.dtso diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs422.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs422.dtso index 3e6404340d52..3e6404340d52 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs422.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs422.dtso diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs485.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs485.dtso index 2c71ab9854cb..2c71ab9854cb 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs485.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs485.dtso diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts index d3ee6fc4baab..750a1f07ecb7 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts @@ -248,15 +248,15 @@ ddrc_opp_table: opp-table { compatible = "operating-points-v2"; - opp-25M { + opp-25000000 { opp-hz = /bits/ 64 <25000000>; }; - opp-100M { + opp-100000000 { opp-hz = /bits/ 64 <100000000>; }; - opp-750M { + opp-750000000 { opp-hz = /bits/ 64 <750000000>; }; }; @@ -326,8 +326,11 @@ &i2c1 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; gsc: gsc@20 { @@ -477,8 +480,11 @@ &i2c2 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; pmic@4b { @@ -600,8 +606,11 @@ &i2c3 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; leds_gpio: gpio@20 { @@ -673,8 +682,11 @@ &i2c4 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; }; @@ -852,6 +864,13 @@ >; }; + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3 + >; + }; + pinctrl_i2c2: i2c2grp { fsl,pins = < MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 @@ -859,6 +878,13 @@ >; }; + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3 + MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3 + >; + }; + pinctrl_i2c3: i2c3grp { fsl,pins = < MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 @@ -866,6 +892,13 @@ >; }; + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3 + MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3 + >; + }; + pinctrl_i2c4: i2c4grp { fsl,pins = < MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 @@ -873,6 +906,13 @@ >; }; + pinctrl_i2c4_gpio: i2c4gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x400001c3 + MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x400001c3 + >; + }; + pinctrl_ksz: kszgrp { fsl,pins = < MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x41 diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts index 31f4c735fe4f..32872b0b1aaf 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts @@ -198,15 +198,15 @@ ddrc_opp_table: opp-table { compatible = "operating-points-v2"; - opp-25M { + opp-25000000 { opp-hz = /bits/ 64 <25000000>; }; - opp-100M { + opp-100000000 { opp-hz = /bits/ 64 <100000000>; }; - opp-750M { + opp-750000000 { opp-hz = /bits/ 64 <750000000>; }; }; @@ -261,7 +261,7 @@ &gpio1 { gpio-line-names = "", "", "", "", "", "", "", "", - "", "", "", "", "", "m2_reset", "", "m2_wdis#", + "m2_pwr_en", "", "", "", "", "m2_reset", "", "m2_wdis#", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; @@ -283,7 +283,8 @@ &gpio4 { gpio-line-names = "", "", "", "", "", "", "", "", "", "", "", "amp_gpio3", "amp_gpio2", "", "amp_gpio1", "", - "", "", "", "", "amp_gpio4", "app_gpio1", "", "uart1_rs485", + "lte_pwr#", "lte_rst", "lte_int", "", + "amp_gpio4", "app_gpio1", "vdd_4p0_en", "uart1_rs485", "", "uart1_term", "uart1_half", "app_gpio2", "mipi_gpio1", "", "", ""; }; @@ -298,8 +299,11 @@ &i2c1 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; gsc: gsc@20 { @@ -566,8 +570,11 @@ &i2c2 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; accelerometer@19 { @@ -585,16 +592,22 @@ /* off-board header */ &i2c3 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; }; /* off-board header */ &i2c4 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; }; @@ -738,14 +751,19 @@ pinctrl_hog: hoggrp { fsl,pins = < MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000159 /* M2_GDIS# */ + MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x40000041 /* M2_PWR_EN */ MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RESET */ MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */ MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */ + MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x40000041 /* LTE_INT */ + MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x40000041 /* LTE_RST# */ + MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x40000041 /* LTE_PWR */ MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x40000041 /* AMP GPIO1 */ MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x40000041 /* AMP GPIO2 */ MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x40000041 /* AMP GPIO3 */ MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x40000041 /* AMP_GPIO4 */ MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 /* APP GPIO1 */ + MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x40000041 /* VDD_4P0_EN */ MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* APP GPIO2 */ MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* UART2_EN# */ MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x40000041 /* MIPI_GPIO1 */ @@ -779,8 +797,6 @@ MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* RST# */ MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /* IRQ# */ - MX8MM_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x141 - MX8MM_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x141 >; }; @@ -797,6 +813,13 @@ >; }; + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3 + >; + }; + pinctrl_i2c2: i2c2grp { fsl,pins = < MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 @@ -804,6 +827,13 @@ >; }; + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3 + MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3 + >; + }; + pinctrl_i2c3: i2c3grp { fsl,pins = < MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 @@ -811,6 +841,13 @@ >; }; + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3 + MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3 + >; + }; + pinctrl_i2c4: i2c4grp { fsl,pins = < MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 @@ -818,6 +855,13 @@ >; }; + pinctrl_i2c4_gpio: i2c4gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x400001c3 + MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x400001c3 + >; + }; + pinctrl_gpio_leds: gpioledgrp { fsl,pins = < MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19 diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts index 19f6d2943d26..8ce562246a08 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts @@ -207,15 +207,15 @@ ddrc_opp_table: opp-table { compatible = "operating-points-v2"; - opp-25M { + opp-25000000 { opp-hz = /bits/ 64 <25000000>; }; - opp-100M { + opp-100000000 { opp-hz = /bits/ 64 <100000000>; }; - opp-750M { + opp-750000000 { opp-hz = /bits/ 64 <750000000>; }; }; @@ -265,8 +265,11 @@ &i2c1 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; gsc: gsc@20 { @@ -397,8 +400,11 @@ &i2c2 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; pmic@4b { @@ -520,8 +526,11 @@ &i2c3 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; accelerometer@19 { @@ -681,6 +690,13 @@ >; }; + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3 + >; + }; + pinctrl_i2c2: i2c2grp { fsl,pins = < MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 @@ -688,6 +704,13 @@ >; }; + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3 + MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3 + >; + }; + pinctrl_i2c3: i2c3grp { fsl,pins = < MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 @@ -695,6 +718,13 @@ >; }; + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3 + MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3 + >; + }; + pinctrl_gpio_leds: gpioledgrp { fsl,pins = < MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19 diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts index a67771d02146..eceed9816f5d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts @@ -266,15 +266,15 @@ ddrc_opp_table: opp-table { compatible = "operating-points-v2"; - opp-25M { + opp-25000000 { opp-hz = /bits/ 64 <25000000>; }; - opp-100M { + opp-100000000 { opp-hz = /bits/ 64 <100000000>; }; - opp-750M { + opp-750000000 { opp-hz = /bits/ 64 <750000000>; }; }; @@ -315,8 +315,11 @@ &i2c1 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; gsc: gsc@20 { @@ -441,8 +444,11 @@ &i2c2 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; pmic@4b { @@ -564,8 +570,11 @@ &i2c3 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; accelerometer@19 { @@ -582,8 +591,11 @@ &i2c4 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; gpioled: gpio@27 { @@ -738,6 +750,13 @@ >; }; + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3 + >; + }; + pinctrl_i2c2: i2c2grp { fsl,pins = < MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 @@ -745,6 +764,13 @@ >; }; + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3 + MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3 + >; + }; + pinctrl_i2c3: i2c3grp { fsl,pins = < MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 @@ -752,6 +778,13 @@ >; }; + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3 + MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3 + >; + }; + pinctrl_i2c4: i2c4grp { fsl,pins = < MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 @@ -759,6 +792,13 @@ >; }; + pinctrl_i2c4_gpio: i2c4gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x400001c3 + MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x400001c3 + >; + }; + pinctrl_pcie0: pciegrp { fsl,pins = < MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x41 diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi index bcab830c6e95..0d454e0e2f7c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi @@ -3,8 +3,8 @@ * Copyright 2022 Toradex */ -#include "dt-bindings/phy/phy-imx8-pcie.h" -#include "dt-bindings/pwm/pwm.h" +#include <dt-bindings/phy/phy-imx8-pcie.h> +#include <dt-bindings/pwm/pwm.h> #include "imx8mm.dtsi" / { @@ -183,15 +183,15 @@ ddrc_opp_table: opp-table { compatible = "operating-points-v2"; - opp-25M { + opp-25000000 { opp-hz = /bits/ 64 <25000000>; }; - opp-100M { + opp-100000000 { opp-hz = /bits/ 64 <100000000>; }; - opp-750M { + opp-750000000 { opp-hz = /bits/ 64 <750000000>; }; }; @@ -610,7 +610,7 @@ compatible = "atmel,maxtouch"; /* * Verdin GPIO_9_DSI - * (TOUCH_INT#, SODIMM 17, also routed to SN65DSI83 IRQ albeit currently unused) + * (TOUCH_INT#, SODIMM 17, also routed to SN65DSI84 IRQ albeit currently unused) */ interrupt-parent = <&gpio3>; interrupts = <15 IRQ_TYPE_EDGE_FALLING>; @@ -653,7 +653,8 @@ assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, <&clk IMX8MM_SYS_PLL2_250M>; assigned-clock-rates = <10000000>, <250000000>; - clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, + <&clk IMX8MM_CLK_PCIE1_AUX>, <&clk IMX8MM_CLK_PCIE1_PHY>; clock-names = "pcie", "pcie_aux", "pcie_bus"; pinctrl-names = "default"; @@ -664,6 +665,7 @@ &pcie_phy { clocks = <&clk IMX8MM_CLK_PCIE1_PHY>; + clock-names = "ref"; fsl,clkreq-unsupported; fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>; fsl,tx-deemph-gen1 = <0x2d>; diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index afb90f59c83c..fae0e1a31147 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -139,6 +139,7 @@ A53_L2: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; cache-size = <0x80000>; cache-line-size = <64>; cache-sets = <512>; @@ -573,9 +574,10 @@ }; }; - anatop: anatop@30360000 { - compatible = "fsl,imx8mm-anatop", "syscon"; + anatop: clock-controller@30360000 { + compatible = "fsl,imx8mm-anatop"; reg = <0x30360000 0x10000>; + #clock-cells = <1>; }; snvs: snvs@30370000 { diff --git a/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi index 1133cded9be2..8a4369d38903 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi @@ -55,15 +55,15 @@ ddrc_opp_table: opp-table { compatible = "operating-points-v2"; - opp-25M { + opp-25000000 { opp-hz = /bits/ 64 <25000000>; }; - opp-100M { + opp-100000000 { opp-hz = /bits/ 64 <100000000>; }; - opp-800M { + opp-800000000 { opp-hz = /bits/ 64 <800000000>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts index d8ce217c6016..5110d59b719f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts @@ -35,15 +35,15 @@ ddrc_opp_table: opp-table { compatible = "operating-points-v2"; - opp-25M { + opp-25000000 { opp-hz = /bits/ 64 <25000000>; }; - opp-100M { + opp-100000000 { opp-hz = /bits/ 64 <100000000>; }; - opp-600M { + opp-600000000 { opp-hz = /bits/ 64 <600000000>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-evk.dts index 4eb467df5ba7..4839a962a170 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dts @@ -47,6 +47,7 @@ regulator-boot-on; regulator-always-on; regulator-ramp-delay = <3125>; + nxp,dvs-standby-voltage = <750000>; }; buck2: BUCK2 { @@ -56,8 +57,6 @@ regulator-boot-on; regulator-always-on; regulator-ramp-delay = <3125>; - nxp,dvs-run-voltage = <950000>; - nxp,dvs-standby-voltage = <850000>; }; buck4: BUCK4{ diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi index 261c36540079..8fef980c4ab2 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi @@ -36,6 +36,7 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <12000>; enable-active-high; }; @@ -159,8 +160,11 @@ &i2c2 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; status = "okay"; ptn5110: tcpc@50 { @@ -195,8 +199,11 @@ &i2c3 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>; status = "okay"; pca6416: gpio@20 { @@ -240,6 +247,15 @@ status = "okay"; }; +&uart1 { /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MN_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>; + uart-has-rtscts; + status = "okay"; +}; + &uart2 { /* console */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; @@ -255,6 +271,10 @@ status = "okay"; }; +&usbphynop1 { + wakeup-source; +}; + &usbotg1 { dr_mode = "otg"; hnp-disable; @@ -369,6 +389,13 @@ >; }; + pinctrl_i2c2_gpio: i2c2grp-gpio { + fsl,pins = < + MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1c3 + MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1c3 + >; + }; + pinctrl_i2c3: i2c3grp { fsl,pins = < MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 @@ -376,6 +403,13 @@ >; }; + pinctrl_i2c3_gpio: i2c3grp-gpio { + fsl,pins = < + MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1c3 + MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1c3 + >; + }; + pinctrl_pmic: pmicirqgrp { fsl,pins = < MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 @@ -419,6 +453,15 @@ >; }; + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 + MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 + MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140 + MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140 + >; + }; + pinctrl_uart2: uart2grp { fsl,pins = < MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 diff --git a/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts b/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts index dd4302ac1de4..b9444e4a3d2d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts @@ -189,15 +189,15 @@ ddrc_opp_table: opp-table { compatible = "operating-points-v2"; - opp-25M { + opp-25000000 { opp-hz = /bits/ 64 <25000000>; }; - opp-100M { + opp-100000000 { opp-hz = /bits/ 64 <100000000>; }; - opp-750M { + opp-750000000 { opp-hz = /bits/ 64 <750000000>; }; }; @@ -256,7 +256,7 @@ &gpio1 { gpio-line-names = "", "", "", "", "", "", "", "", - "", "", "", "", "", "m2_reset", "", "m2_wdis#", + "m2_pwr_en", "", "", "", "", "m2_reset", "", "m2_wdis#", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; @@ -278,7 +278,7 @@ &gpio4 { gpio-line-names = "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", - "", "", "", "", "", "app_gpio1", "", "uart1_rs485", + "", "", "", "", "", "app_gpio1", "vdd_4p0_en", "uart1_rs485", "", "uart1_term", "uart1_half", "app_gpio2", "mipi_gpio1", "", "", ""; }; @@ -297,8 +297,11 @@ &i2c1 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; gsc: gsc@20 { @@ -565,8 +568,11 @@ &i2c2 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; accelerometer@19 { @@ -584,16 +590,22 @@ /* off-board header */ &i2c3 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; }; /* off-board header */ &i2c4 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; }; @@ -689,10 +701,12 @@ pinctrl_hog: hoggrp { fsl,pins = < MX8MN_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000159 /* M2_GDIS# */ + MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x40000041 /* M2_PWR_EN */ MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RESET */ MX8MN_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */ MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */ MX8MN_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 /* APP GPIO1 */ + MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x40000041 /* VDD_4P0_EN */ MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* APP GPIO2 */ MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* UART2_EN# */ MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x40000041 /* MIPI_GPIO1 */ @@ -726,8 +740,6 @@ MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* RST# */ MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /* IRQ# */ - MX8MN_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x141 - MX8MN_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x141 >; }; @@ -744,6 +756,13 @@ >; }; + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX8MN_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3 + MX8MN_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3 + >; + }; + pinctrl_i2c2: i2c2grp { fsl,pins = < MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 @@ -751,6 +770,13 @@ >; }; + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3 + MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3 + >; + }; + pinctrl_i2c3: i2c3grp { fsl,pins = < MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 @@ -758,6 +784,13 @@ >; }; + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3 + MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3 + >; + }; + pinctrl_i2c4: i2c4grp { fsl,pins = < MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 @@ -765,6 +798,13 @@ >; }; + pinctrl_i2c4_gpio: i2c4gpiogrp { + fsl,pins = < + MX8MN_IOMUXC_I2C4_SCL_GPIO5_IO20 0x400001c3 + MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21 0x400001c3 + >; + }; + pinctrl_gpio_leds: gpioledgrp { fsl,pins = < MX8MN_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19 diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index cb2836bfbd95..3c8ff12ab14d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -139,6 +139,7 @@ A53_L2: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; cache-size = <0x80000>; cache-line-size = <64>; cache-sets = <512>; @@ -576,10 +577,10 @@ }; }; - anatop: anatop@30360000 { - compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop", - "syscon"; + anatop: clock-controller@30360000 { + compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop"; reg = <0x30360000 0x10000>; + #clock-cells = <1>; }; snvs: snvs@30370000 { diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi index 0f13ee362771..6e1192e751f8 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi @@ -427,6 +427,24 @@ pinctrl-0 = <&pinctrl_uart2>; uart-has-rtscts; status = "okay"; + + /* + * PLL3 at 320 MHz supplies UART2 root with 64 MHz clock, + * which with 16x oversampling yields 4 Mbdps baud base, + * which is exactly the maximum rate supported by muRata + * 2AE bluetooth UART. + */ + assigned-clocks = <&clk IMX8MP_SYS_PLL3>, <&clk IMX8MP_CLK_UART2>; + assigned-clock-parents = <0>, <&clk IMX8MP_SYS_PLL3_OUT>; + assigned-clock-rates = <320000000>, <64000000>; + + bluetooth { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2_bt>; + compatible = "cypress,cyw4373a0-bt"; + shutdown-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; + max-speed = <4000000>; + }; }; &uart3 { @@ -849,6 +867,13 @@ >; }; + pinctrl_uart2_bt: dhcom-uart2-bt-grp { + fsl,pins = < + /* BT_REG_EN */ + MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x144 + >; + }; + pinctrl_uart3: dhcom-uart3-grp { fsl,pins = < MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x49 @@ -886,8 +911,6 @@ MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 - /* BT_REG_EN */ - MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x144 /* WL_REG_EN */ MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x144 >; @@ -901,8 +924,6 @@ MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4 - /* BT_REG_EN */ - MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x144 /* WL_REG_EN */ MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x144 >; @@ -916,8 +937,6 @@ MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6 - /* BT_REG_EN */ - MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x144 /* WL_REG_EN */ MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x144 >; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index 9f1469db554d..e2e1898d3d12 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -85,6 +85,20 @@ }; }; +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + }; +}; + &A53_0 { cpu-supply = <®_arm>; }; @@ -317,6 +331,13 @@ }; }; +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + &i2c3 { clock-frequency = <400000>; pinctrl-names = "default"; @@ -390,10 +411,37 @@ status = "okay"; }; +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + &snvs_pwrkey { status = "okay"; }; +&uart1 { /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MP_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + uart-has-rtscts; + status = "okay"; +}; + &uart2 { /* console */ pinctrl-names = "default"; @@ -416,6 +464,15 @@ status = "okay"; }; +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clk IMX8MP_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + uart-has-rtscts; + status = "okay"; +}; + &usdhc2 { assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; assigned-clock-rates = <400000000>; @@ -515,6 +572,17 @@ >; }; + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2 + MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 + MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 + MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 + MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 + MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 + >; + }; + pinctrl_gpio_led: gpioledgrp { fsl,pins = < MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x140 @@ -528,6 +596,13 @@ >; }; + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 + >; + }; + pinctrl_i2c3: i2c3grp { fsl,pins = < MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 @@ -567,12 +642,39 @@ >; }; + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x116 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x116 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXFS__PWM4_OUT 0x116 + >; + }; + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { fsl,pins = < MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 >; }; + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 + MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140 + MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140 + >; + }; + pinctrl_uart2: uart2grp { fsl,pins = < MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 @@ -586,6 +688,15 @@ >; }; + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140 + MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140 + MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x140 + MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140 + >; + }; + pinctrl_usdhc2: usdhc2grp { fsl,pins = < MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts index 7bf6f81e87b4..6357f3d96ccd 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts @@ -8,6 +8,7 @@ #include <dt-bindings/leds/common.h> #include <dt-bindings/net/ti-dp83867.h> +#include <dt-bindings/phy/phy-imx8-pcie.h> #include <dt-bindings/pwm/pwm.h> #include "imx8mp-tqma8mpql.dtsi" @@ -48,6 +49,27 @@ status = "disabled"; }; + clk_xtal25: clk-xtal25 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + fan0: pwm-fan { + compatible = "pwm-fan"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwmfan>; + fan-supply = <®_pwm_fan>; + #cooling-cells = <2>; + /* typical 25 kHz -> 40.000 nsec */ + pwms = <&pwm3 0 40000 PWM_POLARITY_INVERTED>; + cooling-levels = <0 32 64 128 196 240>; + pulses-per-revolution = <2>; + interrupt-parent = <&gpio5>; + interrupts = <18 IRQ_TYPE_EDGE_FALLING>; + status = "disabled"; + }; + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; @@ -108,6 +130,18 @@ status = "disabled"; }; + reg_pwm_fan: regulator-pwm-fan { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_regpwmfan>; + regulator-name = "FAN_PWR"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_vcc_12v0>; + }; + reg_usdhc2_vmmc: regulator-usdhc2 { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -165,6 +199,47 @@ linux,cma-default; }; }; + + thermal-zones { + soc-thermal { + trips { + soc_active0: trip-active0 { + temperature = <40000>; + hysteresis = <5000>; + type = "active"; + }; + + soc_active1: trip-active1 { + temperature = <48000>; + hysteresis = <3000>; + type = "active"; + }; + + soc_active2: trip-active2 { + temperature = <60000>; + hysteresis = <10000>; + type = "active"; + }; + }; + + cooling-maps { + map1 { + trip = <&soc_active0>; + cooling-device = <&fan0 1 1>; + }; + + map2 { + trip = <&soc_active1>; + cooling-device = <&fan0 2 2>; + }; + + map3 { + trip = <&soc_active2>; + cooling-device = <&fan0 3 3>; + }; + }; + }; + }; }; &ecspi1 { @@ -340,9 +415,16 @@ "", "", "", "", "", "", "", "", "", "", "DP_IRQ", "DSI_EN", - "HDMI_OC#", "TEMP_EVENT#", "PCIE_CLK_OE#", "", + "HDMI_OC#", "TEMP_EVENT#", "PCIE_REFCLK_OE#", "", "", "", "", "FAN_PWR", "RTC_EVENT#", "CODEC_RST#", "", ""; + + pcie-refclkreq-hog { + gpio-hog; + gpios = <22 0>; + output-high; + line-name = "PCIE_REFCLK_OE#"; + }; }; &gpio5 { @@ -377,6 +459,13 @@ pagesize = <16>; vcc-supply = <®_vcc_3v3>; }; + + pcieclk: clock-generator@6a { + compatible = "renesas,9fgv0241"; + reg = <0x6a>; + clocks = <&clk_xtal25>; + #clock-cells = <1>; + }; }; &i2c4 { @@ -407,6 +496,25 @@ interrupts = <28 IRQ_TYPE_EDGE_FALLING>; }; +&pcie_phy { + fsl,clkreq-unsupported; + fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; + clocks = <&pcieclk 0>; + clock-names = "ref"; + status = "okay"; +}; + +&pcie { + clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, + <&clk IMX8MP_CLK_HSIO_AXI>, + <&clk IMX8MP_CLK_PCIE_ROOT>; + clock-names = "pcie", "pcie_bus", "pcie_aux"; + assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>; + assigned-clock-rates = <10000000>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; + status = "okay"; +}; + &pwm2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm2>; @@ -461,11 +569,23 @@ status = "okay"; }; +&usb3_1 { + fsl,disable-port-power-control; + fsl,permanently-attached; + dr_mode = "host"; + status = "okay"; +}; + &usb3_phy0 { vbus-supply = <®_vcc_5v0>; status = "okay"; }; +&usb3_phy1 { + vbus-supply = <®_vcc_5v0>; + status = "okay"; +}; + &usb_dwc3_0 { /* dual role is implemented, but not a full featured OTG */ hnp-disable; @@ -486,6 +606,31 @@ }; }; +&usb_dwc3_1 { + dr_mode = "host"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbhub>; + status = "okay"; + + hub_2_0: hub@1 { + compatible = "usb451,8142"; + reg = <1>; + peer-hub = <&hub_3_0>; + reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; + vdd-supply = <®_vcc_3v3>; + }; + + hub_3_0: hub@2 { + compatible = "usb451,8140"; + reg = <2>; + peer-hub = <&hub_2_0>; + reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; + vdd-supply = <®_vcc_3v3>; + }; +}; + &usdhc2 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; @@ -685,10 +830,18 @@ fsl,pins = <MX8MP_IOMUXC_I2C3_SDA__PWM3_OUT 0x14>; }; + pinctrl_pwmfan: pwmfangrp { + fsl,pins = <MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x80>; /* FAN RPM */ + }; + pinctrl_reg12v0: reg12v0grp { fsl,pins = <MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x140>; /* VCC12V enable */ }; + pinctrl_regpwmfan: regpwmfangrp { + fsl,pins = <MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x80>; + }; + /* X61 */ pinctrl_uart1: uart1grp { fsl,pins = <MX8MP_IOMUXC_SD1_CLK__UART1_DCE_TX 0x140>, @@ -720,6 +873,10 @@ fsl,pins = <MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x1c0>; }; + pinctrl_usbhub: usbhubgrp { + fsl,pins = <MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x10>; + }; + pinctrl_usdhc2: usdhc2grp { fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x192>, <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d2>, diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts index 06b4c93c5876..ceeca4966fc5 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts @@ -253,8 +253,11 @@ &i2c1 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; gsc: gsc@20 { @@ -477,8 +480,11 @@ &i2c2 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; accelerometer@19 { @@ -556,16 +562,22 @@ /* off-board header */ &i2c3 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; }; /* off-board header */ &i2c4 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; }; @@ -800,6 +812,13 @@ >; }; + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c2 + MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c2 + >; + }; + pinctrl_i2c2: i2c2grp { fsl,pins = < MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 @@ -807,6 +826,13 @@ >; }; + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001c3 + MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001c3 + >; + }; + pinctrl_i2c3: i2c3grp { fsl,pins = < MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 @@ -814,6 +840,13 @@ >; }; + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x400001c3 + MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001c3 + >; + }; + pinctrl_i2c4: i2c4grp { fsl,pins = < MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c2 @@ -821,6 +854,13 @@ >; }; + pinctrl_i2c4_gpio: i2c4gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x400001c3 + MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x400001c3 + >; + }; + pinctrl_ksz: kszgrp { fsl,pins = < MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x150 /* IRQ# */ diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi index 4b8f86f63081..80db1ad7c230 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi @@ -116,6 +116,7 @@ /* Verdin USB_2 */ &usb3_1 { + fsl,permanently-attached; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi index 7b712d1888ea..b31af0d1f386 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi @@ -3,7 +3,8 @@ * Copyright 2022 Toradex */ -#include "dt-bindings/pwm/pwm.h" +#include <dt-bindings/phy/phy-imx8-pcie.h> +#include <dt-bindings/pwm/pwm.h> #include "imx8mp.dtsi" / { @@ -678,8 +679,8 @@ status = "disabled"; }; - lvds_ti_sn65dsi83: bridge@2c { - compatible = "ti,sn65dsi83"; + lvds_ti_sn65dsi84: bridge@2c { + compatible = "ti,sn65dsi84"; /* Verdin GPIO_9_DSI (SN65DSI84 IRQ, SODIMM 17, unused) */ /* Verdin GPIO_10_DSI (SODIMM 21) */ enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; @@ -712,7 +713,7 @@ compatible = "atmel,maxtouch"; /* * Verdin GPIO_9_DSI - * (TOUCH_INT#, SODIMM 17, also routed to SN65DSI83 IRQ albeit currently unused) + * (TOUCH_INT#, SODIMM 17, also routed to SN65DSI84 IRQ albeit currently unused) */ interrupt-parent = <&gpio4>; interrupts = <25 IRQ_TYPE_EDGE_FALLING>; @@ -806,28 +807,45 @@ }; /* Verdin USB_1 */ -&usb3_phy0 { - vbus-supply = <®_usb1_vbus>; +&usb3_0 { + fsl,disable-port-power-control; + fsl,over-current-active-low; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_1_oc_n>; }; &usb_dwc3_0 { + /* dual role only, not full featured OTG */ adp-disable; dr_mode = "otg"; hnp-disable; maximum-speed = "high-speed"; - over-current-active-low; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_1_id>; + role-switch-default-mode = "peripheral"; srp-disable; + usb-role-switch; + + connector { + compatible = "gpio-usb-b-connector", "usb-b-connector"; + id-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; + label = "Type-C"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_1_id>; + self-powered; + type = "micro"; + vbus-supply = <®_usb1_vbus>; + }; }; /* Verdin USB_2 */ +&usb3_1 { + fsl,disable-port-power-control; +}; + &usb3_phy1 { vbus-supply = <®_usb2_vbus>; }; &usb_dwc3_1 { - disable-over-current; dr_mode = "host"; }; @@ -1045,7 +1063,6 @@ pinctrl_gpio_hog3: gpiohog3grp { fsl,pins = - <MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x1c4>, /* SODIMM 157 */ /* CSI_1_MCLK */ <MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x1c4>; /* SODIMM 91 */ }; @@ -1220,7 +1237,7 @@ pinctrl_usb1_vbus: usb1vbusgrp { fsl,pins = - <MX8MP_IOMUXC_GPIO1_IO12__USB1_OTG_PWR 0x19>; /* SODIMM 155 */ + <MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x106>; /* SODIMM 155 */ }; /* USB_1_ID */ @@ -1229,9 +1246,15 @@ <MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x1c4>; /* SODIMM 161 */ }; + /* USB_1_OC# */ + pinctrl_usb_1_oc_n: usb1ocngrp { + fsl,pins = + <MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x1c4>; /* SODIMM 157 */ + }; + pinctrl_usb2_vbus: usb2vbusgrp { fsl,pins = - <MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x19>; /* SODIMM 185 */ + <MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x106>; /* SODIMM 185 */ }; /* On-module Wi-Fi */ diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index bb916a0948a8..7a6e6221f421 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -123,6 +123,7 @@ A53_L2: l2-cache0 { compatible = "cache"; + cache-unified; cache-level = <2>; cache-size = <0x80000>; cache-line-size = <64>; @@ -441,10 +442,10 @@ }; }; - anatop: anatop@30360000 { - compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop", - "syscon"; + anatop: clock-controller@30360000 { + compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop"; reg = <0x30360000 0x10000>; + #clock-cells = <1>; }; snvs: snvs@30370000 { @@ -631,6 +632,14 @@ reg = <IMX8MP_POWER_DOMAIN_VPU_VC8000E>; clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; }; + + pgc_mlmix: power-domain@24 { + #power-domain-cells = <0>; + reg = <IMX8MP_POWER_DOMAIN_MLMIX>; + clocks = <&clk IMX8MP_CLK_ML_AXI>, + <&clk IMX8MP_CLK_ML_AHB>, + <&clk IMX8MP_CLK_NPU_ROOT>; + }; }; }; }; @@ -705,12 +714,15 @@ ecspi1: spi@30820000 { #address-cells = <1>; #size-cells = <0>; - compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi"; + compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; reg = <0x30820000 0x10000>; interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>, <&clk IMX8MP_CLK_ECSPI1_ROOT>; clock-names = "ipg", "per"; + assigned-clock-rates = <80000000>; + assigned-clocks = <&clk IMX8MP_CLK_ECSPI1>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; dma-names = "rx", "tx"; status = "disabled"; @@ -719,12 +731,15 @@ ecspi2: spi@30830000 { #address-cells = <1>; #size-cells = <0>; - compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi"; + compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; reg = <0x30830000 0x10000>; interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>, <&clk IMX8MP_CLK_ECSPI2_ROOT>; clock-names = "ipg", "per"; + assigned-clock-rates = <80000000>; + assigned-clocks = <&clk IMX8MP_CLK_ECSPI2>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; dma-names = "rx", "tx"; status = "disabled"; @@ -733,12 +748,15 @@ ecspi3: spi@30840000 { #address-cells = <1>; #size-cells = <0>; - compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi"; + compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; reg = <0x30840000 0x10000>; interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>, <&clk IMX8MP_CLK_ECSPI3_ROOT>; clock-names = "ipg", "per"; + assigned-clock-rates = <80000000>; + assigned-clocks = <&clk IMX8MP_CLK_ECSPI3>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; dma-names = "rx", "tx"; status = "disabled"; @@ -1063,11 +1081,11 @@ noc_opp_table: opp-table { compatible = "operating-points-v2"; - opp-200M { + opp-200000000 { opp-hz = /bits/ 64 <200000000>; }; - opp-1000M { + opp-1000000000 { opp-hz = /bits/ 64 <1000000000>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts index 82387b9cb800..78937910f403 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts @@ -46,6 +46,7 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <20000>; enable-active-high; }; @@ -163,22 +164,22 @@ ddrc_opp_table: opp-table { compatible = "operating-points-v2"; - opp-25M { + opp-25000000 { opp-hz = /bits/ 64 <25000000>; }; - opp-100M { + opp-100000000 { opp-hz = /bits/ 64 <100000000>; }; /* * On imx8mq B0 PLL can't be bypassed so low bus is 166M */ - opp-166M { + opp-166000000 { opp-hz = /bits/ 64 <166935483>; }; - opp-800M { + opp-800000000 { opp-hz = /bits/ 64 <800000000>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts index 6445c6b90b5b..4c8904fba1c1 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts @@ -7,6 +7,7 @@ #include "dt-bindings/input/input.h" #include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/leds/common.h> #include "dt-bindings/pwm/pwm.h" #include "dt-bindings/usb/pd.h" #include "imx8mq.dtsi" @@ -61,14 +62,13 @@ }; leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; + compatible = "pwm-leds"; led1 { - label = "LED 1"; - gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; - default-state = "off"; + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_RED>; + max-brightness = <248>; + pwms = <&pwm2 0 50000 0>; }; }; @@ -615,9 +615,9 @@ >; }; - pinctrl_gpio_leds: gpioledgrp { + pinctrl_pwm_led: pwmledgrp { fsl,pins = < - MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x16 + MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT 0x16 >; }; @@ -920,6 +920,12 @@ status = "okay"; }; +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_led>; + status = "okay"; +}; + &snvs_pwrkey { status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index ae08556b2ef2..ddf0e330dc7c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -311,15 +311,15 @@ ddrc_opp_table: opp-table { compatible = "operating-points-v2"; - opp-25M { + opp-25000000 { opp-hz = /bits/ 64 <25000000>; }; - opp-100M { + opp-100000000 { opp-hz = /bits/ 64 <100000000>; }; - opp-800M { + opp-800000000 { opp-hz = /bits/ 64 <800000000>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi index 802ad6e5cef6..9a95e30fb42d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi @@ -220,12 +220,14 @@ reg = <0x53>; pagesize = <16>; read-only; + vcc-supply = <®_vcc3v3>; }; eeprom0: eeprom@57 { compatible = "atmel,24c64"; reg = <0x57>; pagesize = <32>; + vcc-supply = <®_vcc3v3>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 19eaa523564d..7ce99c084e54 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -179,6 +179,7 @@ A53_L2: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; cache-size = <0x100000>; cache-line-size = <64>; cache-sets = <1024>; @@ -605,10 +606,11 @@ }; }; - anatop: syscon@30360000 { - compatible = "fsl,imx8mq-anatop", "syscon"; + anatop: clock-controller@30360000 { + compatible = "fsl,imx8mq-anatop"; reg = <0x30360000 0x10000>; interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; + #clock-cells = <1>; }; snvs: snvs@30370000 { @@ -1184,7 +1186,7 @@ }; csi1: csi@30a90000 { - compatible = "fsl,imx8mq-csi", "fsl,imx7-csi"; + compatible = "fsl,imx8mq-csi"; reg = <0x30a90000 0x10000>; interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MQ_CLK_CSI1_ROOT>; @@ -1236,7 +1238,7 @@ }; csi2: csi@30b80000 { - compatible = "fsl,imx8mq-csi", "fsl,imx7-csi"; + compatible = "fsl,imx8mq-csi"; reg = <0x30b80000 0x10000>; interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MQ_CLK_CSI2_ROOT>; @@ -1356,15 +1358,15 @@ noc_opp_table: opp-table { compatible = "operating-points-v2"; - opp-133M { + opp-133000000 { opp-hz = /bits/ 64 <133333333>; }; - opp-400M { + opp-400000000 { opp-hz = /bits/ 64 <400000000>; }; - opp-800M { + opp-800000000 { opp-hz = /bits/ 64 <800000000>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi index 669aa14ce9f7..b483134f84d1 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi @@ -6,30 +6,68 @@ &lsio_gpio0 { compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + gpio-ranges = <&iomuxc 0 0 6>, + <&iomuxc 6 7 22>, + <&iomuxc 28 36 4>; }; &lsio_gpio1 { compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + gpio-ranges = <&iomuxc 0 40 4>, + <&iomuxc 4 50 12>, + <&iomuxc 16 63 8>, + <&iomuxc 24 72 8>; }; &lsio_gpio2 { compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + gpio-ranges = <&iomuxc 0 80 4>, + <&iomuxc 4 85 18>, + <&iomuxc 22 104 10>; }; &lsio_gpio3 { compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + gpio-ranges = <&iomuxc 0 114 2>, + <&iomuxc 2 117 16>, + <&iomuxc 18 141 1>, + <&iomuxc 19 140 1>, + <&iomuxc 20 139 1>, + <&iomuxc 21 138 1>, + <&iomuxc 22 137 1>, + <&iomuxc 23 136 1>, + <&iomuxc 24 135 1>, + <&iomuxc 25 134 1>, + <&iomuxc 26 142 3>, + <&iomuxc 29 146 3>; }; &lsio_gpio4 { compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + gpio-ranges = <&iomuxc 0 149 3>, + <&iomuxc 3 153 4>, + <&iomuxc 7 158 6>, + <&iomuxc 13 165 6>, + <&iomuxc 19 172 8>, + <&iomuxc 27 198 5>; }; &lsio_gpio5 { compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + gpio-ranges = <&iomuxc 0 203 1>, + <&iomuxc 1 205 2>, + <&iomuxc 3 210 11>, + <&iomuxc 14 223 3>, + <&iomuxc 17 227 2>, + <&iomuxc 19 230 5>, + <&iomuxc 24 236 6>, + <&iomuxc 30 243 2>; }; &lsio_gpio6 { compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + gpio-ranges = <&iomuxc 0 245 10>, + <&iomuxc 10 256 12>; }; &lsio_gpio7 { diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi index c9c2b6536233..41ce8336f29e 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi @@ -136,6 +136,7 @@ A53_L2: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; cache-size = <0x100000>; cache-line-size = <64>; cache-sets = <1024>; @@ -144,6 +145,7 @@ A72_L2: l2-cache1 { compatible = "cache"; cache-level = <2>; + cache-unified; cache-size = <0x100000>; cache-line-size = <64>; cache-sets = <1024>; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dtsi index a08e70fb7c7a..7c334b93db3b 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dtsi @@ -3,7 +3,7 @@ * Copyright 2019 Toradex */ -#include "dt-bindings/input/linux-event-codes.h" +#include <dt-bindings/input/linux-event-codes.h> / { aliases { diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi index 8e2152c6eb88..8f722b1dd078 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi @@ -6,26 +6,51 @@ &lsio_gpio0 { compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; + gpio-ranges = <&iomuxc 1 56 12>, + <&iomuxc 13 69 4>, + <&iomuxc 19 75 4>, + <&iomuxc 24 80 1>, + <&iomuxc 25 82 7>; }; &lsio_gpio1 { compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; + gpio-ranges = <&iomuxc 0 89 9>, + <&iomuxc 9 99 16>, + <&iomuxc 25 116 7>; }; &lsio_gpio2 { compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; + gpio-ranges = <&iomuxc 0 123 1>, + <&iomuxc 1 126 2>, + <&iomuxc 3 129 1>; }; &lsio_gpio3 { compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; + gpio-ranges = <&iomuxc 0 146 4>, + <&iomuxc 4 151 13>, + <&iomuxc 17 165 8>; }; &lsio_gpio4 { compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; + gpio-ranges = <&iomuxc 0 0 3>, + <&iomuxc 3 4 4>, + <&iomuxc 7 9 6>, + <&iomuxc 13 16 6>, + <&iomuxc 19 23 2>, + <&iomuxc 21 26 2>, + <&iomuxc 23 30 6>, + <&iomuxc 29 37 3>; }; &lsio_gpio5 { compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; + gpio-ranges = <&iomuxc 0 40 3>, + <&iomuxc 3 44 6>, + <&iomuxc 9 51 3>; }; &lsio_gpio6 { diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi index f4ea18bb95ab..85c0b1d2bac5 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi @@ -127,6 +127,7 @@ A35_L2: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; cache-size = <0x80000>; cache-line-size = <64>; cache-sets = <1024>; diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi index 06ce5f19aa8a..32193a43ff49 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi @@ -51,6 +51,7 @@ A35_L2: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi index 3a5713bb4880..db5e3ae308e9 100644 --- a/arch/arm64/boot/dts/freescale/imx93.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi @@ -17,6 +17,10 @@ #size-cells = <2>; aliases { + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; i2c0 = &lpi2c1; i2c1 = &lpi2c2; i2c2 = &lpi2c3; @@ -135,6 +139,7 @@ compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu"; reg = <0x44230000 0x10000>; interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_MU1_B_GATE>; #mbox-cells = <2>; status = "disabled"; }; @@ -145,6 +150,15 @@ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; clocks = <&osc_24m>; clock-names = "per"; + nxp,no-divider; + }; + + tpm2: pwm@44320000 { + compatible = "fsl,imx7ulp-pwm"; + reg = <0x44320000 0x10000>; + clocks = <&clk IMX93_CLK_TPM2_GATE>; + #pwm-cells = <3>; + status = "disabled"; }; lpi2c1: i2c@44340000 { @@ -270,10 +284,35 @@ compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu"; reg = <0x42440000 0x10000>; interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_MU2_B_GATE>; #mbox-cells = <2>; status = "disabled"; }; + tpm4: pwm@424f0000 { + compatible = "fsl,imx7ulp-pwm"; + reg = <0x424f0000 0x10000>; + clocks = <&clk IMX93_CLK_TPM4_GATE>; + #pwm-cells = <3>; + status = "disabled"; + }; + + tpm5: pwm@42500000 { + compatible = "fsl,imx7ulp-pwm"; + reg = <0x42500000 0x10000>; + clocks = <&clk IMX93_CLK_TPM5_GATE>; + #pwm-cells = <3>; + status = "disabled"; + }; + + tpm6: pwm@42510000 { + compatible = "fsl,imx7ulp-pwm"; + reg = <0x42510000 0x10000>; + clocks = <&clk IMX93_CLK_TPM6_GATE>; + #pwm-cells = <3>; + status = "disabled"; + }; + lpi2c3: i2c@42530000 { compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; reg = <0x42530000 0x10000>; @@ -294,6 +333,30 @@ status = "disabled"; }; + lpspi3: spi@42550000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; + reg = <0x42550000 0x10000>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPSPI3_GATE>, + <&clk IMX93_CLK_BUS_WAKEUP>; + clock-names = "per", "ipg"; + status = "disabled"; + }; + + lpspi4: spi@42560000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; + reg = <0x42560000 0x10000>; + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPSPI4_GATE>, + <&clk IMX93_CLK_BUS_WAKEUP>; + clock-names = "per", "ipg"; + status = "disabled"; + }; + lpuart3: serial@42570000 { compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; reg = <0x42570000 0x1000>; @@ -388,6 +451,54 @@ status = "disabled"; }; + lpspi5: spi@426f0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; + reg = <0x426f0000 0x10000>; + interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPSPI5_GATE>, + <&clk IMX93_CLK_BUS_WAKEUP>; + clock-names = "per", "ipg"; + status = "disabled"; + }; + + lpspi6: spi@42700000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; + reg = <0x42700000 0x10000>; + interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPSPI6_GATE>, + <&clk IMX93_CLK_BUS_WAKEUP>; + clock-names = "per", "ipg"; + status = "disabled"; + }; + + lpspi7: spi@42710000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; + reg = <0x42710000 0x10000>; + interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPSPI7_GATE>, + <&clk IMX93_CLK_BUS_WAKEUP>; + clock-names = "per", "ipg"; + status = "disabled"; + }; + + lpspi8: spi@42720000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; + reg = <0x42720000 0x10000>; + interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_LPSPI8_GATE>, + <&clk IMX93_CLK_BUS_WAKEUP>; + clock-names = "per", "ipg"; + status = "disabled"; + }; + }; aips3: bus@42800000 { diff --git a/arch/arm64/boot/dts/freescale/mba8mx.dtsi b/arch/arm64/boot/dts/freescale/mba8mx.dtsi index 104bdd4e437a..daa37adeff3b 100644 --- a/arch/arm64/boot/dts/freescale/mba8mx.dtsi +++ b/arch/arm64/boot/dts/freescale/mba8mx.dtsi @@ -215,6 +215,7 @@ compatible = "nxp,se97b", "atmel,24c02"; reg = <0x57>; pagesize = <16>; + vcc-supply = <®_vcc_3v3>; }; }; diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi index 824d401e7a2c..d8c82da88ca0 100644 --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi @@ -52,10 +52,12 @@ cluster0_l2: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; cluster1_l2: l2-cache1 { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/freescale/s32v234.dtsi b/arch/arm64/boot/dts/freescale/s32v234.dtsi index ba0b5305d481..3e306218d533 100644 --- a/arch/arm64/boot/dts/freescale/s32v234.dtsi +++ b/arch/arm64/boot/dts/freescale/s32v234.dtsi @@ -61,10 +61,12 @@ cluster0_l2_cache: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; cluster1_l2_cache: l2-cache1 { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index 8343d0cedde3..a57f35eb5ef6 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -203,10 +203,12 @@ A53_L2: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; A73_L2: l2-cache1 { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index ae0a7cfeeb47..f6d3202b0d1a 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -186,10 +186,12 @@ CLUSTER0_L2: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; CLUSTER1_L2: l2-cache1 { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi index 7b2abd10d3d6..5b2b1bfd0d2a 100644 --- a/arch/arm64/boot/dts/hisilicon/hip05.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi @@ -211,18 +211,22 @@ cluster0_l2: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; cluster1_l2: l2-cache1 { compatible = "cache"; + cache-level = <2>; }; cluster2_l2: l2-cache2 { compatible = "cache"; + cache-level = <2>; }; cluster3_l2: l2-cache3 { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi index 2f8b03b0d365..291c2ee38288 100644 --- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi @@ -211,18 +211,22 @@ cluster0_l2: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; cluster1_l2: l2-cache1 { compatible = "cache"; + cache-level = <2>; }; cluster2_l2: l2-cache2 { compatible = "cache"; + cache-level = <2>; }; cluster3_l2: l2-cache3 { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi b/arch/arm64/boot/dts/hisilicon/hip07.dtsi index 1a16662f8867..b8746fb959b5 100644 --- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi @@ -842,66 +842,82 @@ cluster0_l2: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; cluster1_l2: l2-cache1 { compatible = "cache"; + cache-level = <2>; }; cluster2_l2: l2-cache2 { compatible = "cache"; + cache-level = <2>; }; cluster3_l2: l2-cache3 { compatible = "cache"; + cache-level = <2>; }; cluster4_l2: l2-cache4 { compatible = "cache"; + cache-level = <2>; }; cluster5_l2: l2-cache5 { compatible = "cache"; + cache-level = <2>; }; cluster6_l2: l2-cache6 { compatible = "cache"; + cache-level = <2>; }; cluster7_l2: l2-cache7 { compatible = "cache"; + cache-level = <2>; }; cluster8_l2: l2-cache8 { compatible = "cache"; + cache-level = <2>; }; cluster9_l2: l2-cache9 { compatible = "cache"; + cache-level = <2>; }; cluster10_l2: l2-cache10 { compatible = "cache"; + cache-level = <2>; }; cluster11_l2: l2-cache11 { compatible = "cache"; + cache-level = <2>; }; cluster12_l2: l2-cache12 { compatible = "cache"; + cache-level = <2>; }; cluster13_l2: l2-cache13 { compatible = "cache"; + cache-level = <2>; }; cluster14_l2: l2-cache14 { compatible = "cache"; + cache-level = <2>; }; cluster15_l2: l2-cache15 { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi index 7bbec8aafa62..849b46dd8098 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi @@ -313,6 +313,7 @@ <&clkmgr AGILEX_SDMMC_CLK>; clock-names = "biu", "ciu"; iommus = <&smmu 5>; + altr,sysmgr-syscon = <&sysmgr 0x28 4>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts index 26cd3c121757..07c3f8876613 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts @@ -83,6 +83,7 @@ cap-sd-highspeed; broken-cd; bus-width = <4>; + clk-phase-sd-hs = <0>, <135>; }; &osc1 { diff --git a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts index 62c66e52b656..08c088571270 100644 --- a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts +++ b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts @@ -74,6 +74,7 @@ cap-sd-highspeed; broken-cd; bus-width = <4>; + clk-phase-sd-hs = <0>, <135>; }; &osc1 { diff --git a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi index 44ed6f963b75..7308f7b6b22c 100644 --- a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi +++ b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi @@ -49,6 +49,7 @@ l2: l2-cache { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts index ada164d423f3..cd0988317623 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts @@ -125,9 +125,12 @@ /delete-property/ mrvl,i2c-fast-mode; status = "okay"; + /* MCP7940MT-I/MNY RTC */ rtc@6f { compatible = "microchip,mcp7940x"; reg = <0x6f>; + interrupt-parent = <&gpiosb>; + interrupts = <5 0>; /* GPIO2_5 */ }; }; @@ -136,6 +139,7 @@ pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>; status = "okay"; reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>; + slot-power-limit-milliwatt = <10000>; /* * U-Boot port for Turris Mox has a bug which always expects that "ranges" DT property * contains exactly 2 ranges with 3 (child) address cells, 2 (parent) address cells and diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi index df152c72276b..e300145ad1a6 100644 --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi @@ -35,6 +35,11 @@ reg = <0 0x4000000 0 0x200000>; no-map; }; + + tee@4400000 { + reg = <0 0x4400000 0 0x1000000>; + no-map; + }; }; cpus { diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi index fcab5173fe67..990f70303fe6 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi @@ -51,6 +51,7 @@ cache-size = <0x80000>; cache-line-size = <64>; cache-sets = <512>; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi index 3db427122f9e..a7b8e001cc9c 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi @@ -81,6 +81,7 @@ cache-size = <0x80000>; cache-line-size = <64>; cache-sets = <512>; + cache-level = <2>; }; l2_1: l2-cache1 { @@ -88,6 +89,7 @@ cache-size = <0x80000>; cache-line-size = <64>; cache-sets = <512>; + cache-level = <2>; }; }; }; diff --git a/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi b/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi index 68782f161f12..7740098fd108 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi @@ -81,6 +81,7 @@ cache-size = <0x80000>; cache-line-size = <64>; cache-sets = <512>; + cache-level = <2>; }; l2_1: l2-cache1 { @@ -88,6 +89,7 @@ cache-size = <0x80000>; cache-line-size = <64>; cache-sets = <512>; + cache-level = <2>; }; }; }; diff --git a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi index a06a0a889c43..4e6d29ad32eb 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi @@ -41,6 +41,11 @@ reg = <0x0 0x4000000 0x0 0x200000>; no-map; }; + + tee@4400000 { + reg = <0 0x4400000 0 0x1000000>; + no-map; + }; }; AP_NAME { diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index 0ec90cb3ef28..813e735c5b96 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -3,6 +3,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt6779-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-sony-xperia-m5.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts index 9b1af9c80130..d31a194124c9 100644 --- a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts @@ -26,14 +26,14 @@ stdout-path = "serial0:921600n8"; }; - cpus_fixed_vproc0: fixedregulator@0 { + cpus_fixed_vproc0: regulator-vproc-buck0 { compatible = "regulator-fixed"; regulator-name = "vproc_buck0"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; }; - cpus_fixed_vproc1: fixedregulator@1 { + cpus_fixed_vproc1: regulator-vproc-buck1 { compatible = "regulator-fixed"; regulator-name = "vproc_buck1"; regulator-min-microvolt = <1000000>; @@ -50,7 +50,7 @@ id-gpio = <&pio 14 GPIO_ACTIVE_HIGH>; }; - usb_p0_vbus: regulator@2 { + usb_p0_vbus: regulator-usb-p0-vbus { compatible = "regulator-fixed"; regulator-name = "p0_vbus"; regulator-min-microvolt = <5000000>; @@ -59,7 +59,7 @@ enable-active-high; }; - usb_p1_vbus: regulator@3 { + usb_p1_vbus: regulator-usb-p1-vbus { compatible = "regulator-fixed"; regulator-name = "p1_vbus"; regulator-min-microvolt = <5000000>; @@ -68,7 +68,7 @@ enable-active-high; }; - usb_p2_vbus: regulator@4 { + usb_p2_vbus: regulator-usb-p2-vbus { compatible = "regulator-fixed"; regulator-name = "p2_vbus"; regulator-min-microvolt = <5000000>; @@ -77,7 +77,7 @@ enable-active-high; }; - usb_p3_vbus: regulator@5 { + usb_p3_vbus: regulator-usb-p3-vbus { compatible = "regulator-fixed"; regulator-name = "p3_vbus"; regulator-min-microvolt = <5000000>; diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi index e6d7453e56e0..92212cddd37e 100644 --- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi @@ -160,70 +160,70 @@ #clock-cells = <0>; }; - clk26m: oscillator@0 { + clk26m: oscillator-26m { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; clock-output-names = "clk26m"; }; - clk32k: oscillator@1 { + clk32k: oscillator-32k { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; clock-output-names = "clk32k"; }; - clkfpc: oscillator@2 { + clkfpc: oscillator-50m { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <50000000>; clock-output-names = "clkfpc"; }; - clkaud_ext_i_0: oscillator@3 { + clkaud_ext_i_0: oscillator-aud0 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <6500000>; clock-output-names = "clkaud_ext_i_0"; }; - clkaud_ext_i_1: oscillator@4 { + clkaud_ext_i_1: oscillator-aud1 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <196608000>; clock-output-names = "clkaud_ext_i_1"; }; - clkaud_ext_i_2: oscillator@5 { + clkaud_ext_i_2: oscillator-aud2 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <180633600>; clock-output-names = "clkaud_ext_i_2"; }; - clki2si0_mck_i: oscillator@6 { + clki2si0_mck_i: oscillator-i2s0 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <30000000>; clock-output-names = "clki2si0_mck_i"; }; - clki2si1_mck_i: oscillator@7 { + clki2si1_mck_i: oscillator-i2s1 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <30000000>; clock-output-names = "clki2si1_mck_i"; }; - clki2si2_mck_i: oscillator@8 { + clki2si2_mck_i: oscillator-i2s2 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <30000000>; clock-output-names = "clki2si2_mck_i"; }; - clktdmin_mclk_i: oscillator@9 { + clktdmin_mclk_i: oscillator-mclk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <30000000>; @@ -266,7 +266,7 @@ reg = <0 0x10005000 0 0x1000>; }; - pio: pinctrl@10005000 { + pio: pinctrl@1000b000 { compatible = "mediatek,mt2712-pinctrl"; reg = <0 0x1000b000 0 0x1000>; mediatek,pctl-regmap = <&syscfg_pctl_a>; @@ -766,9 +766,9 @@ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; clocks = <&pericfg CLK_PERI_MSDC30_0>, <&pericfg CLK_PERI_MSDC50_0_HCLK_EN>, - <&pericfg CLK_PERI_MSDC30_0_QTR_EN>, - <&pericfg CLK_PERI_MSDC50_0_EN>; - clock-names = "source", "hclk", "bus_clk", "source_cg"; + <&pericfg CLK_PERI_MSDC50_0_EN>, + <&pericfg CLK_PERI_MSDC30_0_QTR_EN>; + clock-names = "source", "hclk", "source_cg", "bus_clk"; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt6779.dtsi b/arch/arm64/boot/dts/mediatek/mt6779.dtsi index 9bdf5145966c..5c579e88e749 100644 --- a/arch/arm64/boot/dts/mediatek/mt6779.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6779.dtsi @@ -88,14 +88,14 @@ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW 0>; }; - clk26m: oscillator@0 { + clk26m: oscillator-26m { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; clock-output-names = "clk26m"; }; - clk32k: oscillator@1 { + clk32k: oscillator-32k { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; @@ -117,7 +117,7 @@ compatible = "simple-bus"; ranges; - gic: interrupt-controller@0c000000 { + gic: interrupt-controller@c000000 { compatible = "arm,gic-v3"; #interrupt-cells = <4>; interrupt-parent = <&gic>; @@ -138,7 +138,7 @@ }; - sysirq: intpol-controller@0c53a650 { + sysirq: intpol-controller@c53a650 { compatible = "mediatek,mt6779-sysirq", "mediatek,mt6577-sysirq"; interrupt-controller; @@ -160,7 +160,7 @@ }; pio: pinctrl@10005000 { - compatible = "mediatek,mt6779-pinctrl", "syscon"; + compatible = "mediatek,mt6779-pinctrl"; reg = <0 0x10005000 0 0x1000>, <0 0x11c20000 0 0x1000>, <0 0x11d10000 0 0x1000>, diff --git a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts new file mode 100644 index 000000000000..d3415527d389 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022, Collabora Ltd + * Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> + */ + +/dts-v1/; +#include "mt6795.dtsi" + +/ { + model = "Sony Xperia M5"; + compatible = "sony,xperia-m5", "mediatek,mt6795"; + chassis-type = "handset"; + + aliases { + mmc0 = &mmc0; + mmc1 = &mmc1; + serial0 = &uart0; + serial1 = &uart1; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x1e800000>; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* 128 KiB reserved for ARM Trusted Firmware (BL31) */ + bl31_secmon_reserved: secmon@43000000 { + reg = <0 0x43000000 0 0x30000>; + no-map; + }; + + /* preloader and bootloader regions cannot be touched */ + preloader-region@44800000 { + reg = <0 0x44800000 0 0x100000>; + no-map; + }; + + bootloader-region@46000000 { + reg = <0 0x46000000 0 0x400000>; + no-map; + }; + }; +}; + +&pio { + uart0_pins: uart0-pins { + pins-rx { + pinmux = <PINMUX_GPIO113__FUNC_URXD0>; + bias-pull-up; + input-enable; + }; + pins-tx { + pinmux = <PINMUX_GPIO114__FUNC_UTXD0>; + output-high; + }; + }; + + uart2_pins: uart2-pins { + pins-rx { + pinmux = <PINMUX_GPIO31__FUNC_URXD2>; + bias-pull-up; + input-enable; + }; + pins-tx { + pinmux = <PINMUX_GPIO32__FUNC_UTXD2>; + }; + }; +}; + +&uart0 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; +}; + +&uart2 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi index 46f0e54be766..bb575837e4ce 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi @@ -6,7 +6,9 @@ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/mediatek,mt6795-clk.h> #include <dt-bindings/pinctrl/mt6795-pinfunc.h> +#include <dt-bindings/reset/mediatek,mt6795-resets.h> / { compatible = "mediatek,mt6795"; @@ -192,6 +194,26 @@ compatible = "simple-bus"; ranges; + topckgen: syscon@10000000 { + compatible = "mediatek,mt6795-topckgen", "syscon"; + reg = <0 0x10000000 0 0x1000>; + #clock-cells = <1>; + }; + + infracfg: syscon@10001000 { + compatible = "mediatek,mt6795-infracfg", "syscon"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + pericfg: syscon@10003000 { + compatible = "mediatek,mt6795-pericfg", "syscon"; + reg = <0 0x10003000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + pio: pinctrl@10005000 { compatible = "mediatek,mt6795-pinctrl"; reg = <0 0x10005000 0 0x1000>, <0 0x1000b000 0 0x1000>; @@ -292,7 +314,10 @@ "mediatek,mt6577-uart"; reg = <0 0x11002000 0 0x400>; interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; - clocks = <&clk26m>; + clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; + clock-names = "baud", "bus"; + dmas = <&apdma 0>, <&apdma 1>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -301,16 +326,48 @@ "mediatek,mt6577-uart"; reg = <0 0x11003000 0 0x400>; interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; - clocks = <&clk26m>; + clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; + clock-names = "baud", "bus"; + dmas = <&apdma 2>, <&apdma 3>; + dma-names = "tx", "rx"; status = "disabled"; }; + apdma: dma-controller@11000380 { + compatible = "mediatek,mt6795-uart-dma", + "mediatek,mt6577-uart-dma"; + reg = <0 0x11000380 0 0x60>, + <0 0x11000400 0 0x60>, + <0 0x11000480 0 0x60>, + <0 0x11000500 0 0x60>, + <0 0x11000580 0 0x60>, + <0 0x11000600 0 0x60>, + <0 0x11000680 0 0x60>, + <0 0x11000700 0 0x60>; + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 107 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>; + dma-requests = <8>; + clocks = <&pericfg CLK_PERI_AP_DMA>; + clock-names = "apdma"; + mediatek,dma-33bits; + #dma-cells = <1>; + }; + uart2: serial@11004000 { compatible = "mediatek,mt6795-uart", "mediatek,mt6577-uart"; reg = <0 0x11004000 0 0x400>; interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; - clocks = <&clk26m>; + clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; + clock-names = "baud", "bus"; + dmas = <&apdma 4>, <&apdma 5>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -319,7 +376,51 @@ "mediatek,mt6577-uart"; reg = <0 0x11005000 0 0x400>; interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>; - clocks = <&clk26m>; + clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; + clock-names = "baud", "bus"; + dmas = <&apdma 6>, <&apdma 7>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + mmc0: mmc@11230000 { + compatible = "mediatek,mt6795-mmc"; + reg = <0 0x11230000 0 0x1000>; + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; + clocks = <&pericfg CLK_PERI_MSDC30_0>, + <&topckgen CLK_TOP_MSDC50_0_H_SEL>, + <&topckgen CLK_TOP_MSDC50_0_SEL>; + clock-names = "source", "hclk", "source_cg"; + status = "disabled"; + }; + + mmc1: mmc@11240000 { + compatible = "mediatek,mt6795-mmc"; + reg = <0 0x11240000 0 0x1000>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>; + clocks = <&pericfg CLK_PERI_MSDC30_1>, + <&topckgen CLK_TOP_AXI_SEL>; + clock-names = "source", "hclk"; + status = "disabled"; + }; + + mmc2: mmc@11250000 { + compatible = "mediatek,mt6795-mmc"; + reg = <0 0x11250000 0 0x1000>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; + clocks = <&pericfg CLK_PERI_MSDC30_2>, + <&topckgen CLK_TOP_AXI_SEL>; + clock-names = "source", "hclk"; + status = "disabled"; + }; + + mmc3: mmc@11260000 { + compatible = "mediatek,mt6795-mmc"; + reg = <0 0x11260000 0 0x1000>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; + clocks = <&pericfg CLK_PERI_MSDC30_3>, + <&topckgen CLK_TOP_AXI_SEL>; + clock-names = "source", "hclk"; status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt6797.dtsi b/arch/arm64/boot/dts/mediatek/mt6797.dtsi index 15616231022a..c3677d77e0a4 100644 --- a/arch/arm64/boot/dts/mediatek/mt6797.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6797.dtsi @@ -95,7 +95,7 @@ }; }; - clk26m: oscillator@0 { + clk26m: oscillator-26m { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; diff --git a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts index d3f9eab2b784..af3fe61e4093 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts @@ -235,7 +235,6 @@ bus-width = <4>; max-frequency = <50000000>; cap-sd-highspeed; - r_smpl = <1>; cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>; vmmc-supply = <®_3p3v>; vqmmc-supply = <®_3p3v>; diff --git a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts index 36722cabe626..b74e774c6eba 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts @@ -208,7 +208,6 @@ bus-width = <4>; max-frequency = <50000000>; cap-sd-highspeed; - r_smpl = <1>; cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>; vmmc-supply = <®_3p3v>; vqmmc-supply = <®_3p3v>; diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts index afe37b702eef..9b83925893b7 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts +++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts @@ -9,7 +9,7 @@ / { model = "MediaTek MT7986a RFB"; - compatible = "mediatek,mt7986a-rfb"; + compatible = "mediatek,mt7986a-rfb", "mediatek,mt7986a"; aliases { serial0 = &uart0; @@ -25,6 +25,10 @@ }; }; +&crypto { + status = "okay"; +}; + ð { status = "okay"; @@ -54,6 +58,88 @@ }; }; +&pio { + spi_flash_pins: spi-flash-pins { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + }; + + spic_pins: spic-pins { + mux { + function = "spi"; + groups = "spi1_2"; + }; + }; + + uart1_pins: uart1-pins { + mux { + function = "uart"; + groups = "uart1"; + }; + }; + + uart2_pins: uart2-pins { + mux { + function = "uart"; + groups = "uart2"; + }; + }; + + wf_2g_5g_pins: wf-2g-5g-pins { + mux { + function = "wifi"; + groups = "wf_2g", "wf_5g"; + }; + conf { + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", + "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", + "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", + "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", + "WF1_TOP_CLK", "WF1_TOP_DATA"; + drive-strength = <4>; + }; + }; + + wf_dbdc_pins: wf-dbdc-pins { + mux { + function = "wifi"; + groups = "wf_dbdc"; + }; + conf { + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", + "WF0_TOP_CLK", "WF0_TOP_DATA"; + drive-strength = <4>; + }; + }; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi_flash_pins>; + cs-gpios = <0>, <0>; + status = "okay"; + spi_nand: spi_nand@0 { + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <10000000>; + spi-tx-buswidth = <4>; + spi-rx-buswidth = <4>; + }; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spic_pins>; + cs-gpios = <0>, <0>; + status = "okay"; +}; + &switch { ports { #address-cells = <1>; @@ -121,50 +207,3 @@ pinctrl-0 = <&wf_2g_5g_pins>; pinctrl-1 = <&wf_dbdc_pins>; }; - -&pio { - uart1_pins: uart1-pins { - mux { - function = "uart"; - groups = "uart1"; - }; - }; - - uart2_pins: uart2-pins { - mux { - function = "uart"; - groups = "uart2"; - }; - }; - - wf_2g_5g_pins: wf-2g-5g-pins { - mux { - function = "wifi"; - groups = "wf_2g", "wf_5g"; - }; - conf { - pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", - "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", - "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", - "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", - "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", - "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", - "WF1_TOP_CLK", "WF1_TOP_DATA"; - drive-strength = <4>; - }; - }; - - wf_dbdc_pins: wf-dbdc-pins { - mux { - function = "wifi"; - groups = "wf_dbdc"; - }; - conf { - pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", - "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", - "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", - "WF0_TOP_CLK", "WF0_TOP_DATA"; - drive-strength = <4>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi index 72e0d9722e07..ed703025a7cc 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi @@ -10,11 +10,12 @@ #include <dt-bindings/reset/mt7986-resets.h> / { + compatible = "mediatek,mt7986a"; interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; - clk40m: oscillator@0 { + clk40m: oscillator-40m { compatible = "fixed-clock"; clock-frequency = <40000000>; #clock-cells = <0>; @@ -112,6 +113,12 @@ #clock-cells = <1>; }; + wed_pcie: wed-pcie@10003000 { + compatible = "mediatek,mt7986-wed-pcie", + "syscon"; + reg = <0 0x10003000 0 0x10>; + }; + topckgen: topckgen@1001b000 { compatible = "mediatek,mt7986-topckgen", "syscon"; reg = <0 0x1001B000 0 0x1000>; @@ -168,7 +175,7 @@ #clock-cells = <1>; }; - trng: trng@1020f000 { + trng: rng@1020f000 { compatible = "mediatek,mt7986-rng", "mediatek,mt7623-rng"; reg = <0 0x1020f000 0 0x100>; @@ -177,6 +184,21 @@ status = "disabled"; }; + crypto: crypto@10320000 { + compatible = "inside-secure,safexcel-eip97"; + reg = <0 0x10320000 0 0x40000>; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ring0", "ring1", "ring2", "ring3"; + clocks = <&infracfg CLK_INFRA_EIP97_CK>; + clock-names = "infra_eip97_ck"; + assigned-clocks = <&topckgen CLK_TOP_EIP_B_SEL>; + assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>; + status = "disabled"; + }; + uart0: serial@11002000 { compatible = "mediatek,mt7986-uart", "mediatek,mt6577-uart"; @@ -218,6 +240,48 @@ status = "disabled"; }; + i2c0: i2c@11008000 { + compatible = "mediatek,mt7986-i2c"; + reg = <0 0x11008000 0 0x90>, + <0 0x10217080 0 0x80>; + interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; + clock-div = <5>; + clocks = <&infracfg CLK_INFRA_I2C0_CK>, + <&infracfg CLK_INFRA_AP_DMA_CK>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi0: spi@1100a000 { + compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x1100a000 0 0x100>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&topckgen CLK_TOP_MPLL_D2>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_SPI0_CK>, + <&infracfg CLK_INFRA_SPI0_HCK_CK>; + clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; + status = "disabled"; + }; + + spi1: spi@1100b000 { + compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x1100b000 0 0x100>; + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&topckgen CLK_TOP_MPLL_D2>, + <&topckgen CLK_TOP_SPIM_MST_SEL>, + <&infracfg CLK_INFRA_SPI1_CK>, + <&infracfg CLK_INFRA_SPI1_HCK_CK>; + clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; + status = "disabled"; + }; + ethsys: syscon@15000000 { #address-cells = <1>; #size-cells = <1>; @@ -228,12 +292,6 @@ #reset-cells = <1>; }; - wed_pcie: wed-pcie@10003000 { - compatible = "mediatek,mt7986-wed-pcie", - "syscon"; - reg = <0 0x10003000 0 0x10>; - }; - wed0: wed@15010000 { compatible = "mediatek,mt7986-wed", "syscon"; diff --git a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts index 3443013b5971..243760cd3011 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts +++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts @@ -9,7 +9,7 @@ / { model = "MediaTek MT7986b RFB"; - compatible = "mediatek,mt7986b-rfb"; + compatible = "mediatek,mt7986b-rfb", "mediatek,mt7986b"; aliases { serial0 = &uart0; @@ -25,7 +25,7 @@ }; }; -&uart0 { +&crypto { status = "okay"; }; @@ -99,14 +99,21 @@ }; }; -&wifi { - status = "okay"; - pinctrl-names = "default", "dbdc"; - pinctrl-0 = <&wf_2g_5g_pins>; - pinctrl-1 = <&wf_dbdc_pins>; -}; - &pio { + spi_flash_pins: spi-flash-pins { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + }; + + spic_pins: spic-pins { + mux { + function = "spi"; + groups = "spi1_2"; + }; + }; + wf_2g_5g_pins: wf-2g-5g-pins { mux { function = "wifi"; @@ -138,3 +145,35 @@ }; }; }; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi_flash_pins>; + cs-gpios = <0>, <0>; + status = "okay"; + spi_nand: spi_nand@0 { + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <10000000>; + spi-tx-buswidth = <4>; + spi-rx-buswidth = <4>; + }; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spic_pins>; + cs-gpios = <0>, <0>; + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&wifi { + status = "okay"; + pinctrl-names = "default", "dbdc"; + pinctrl-0 = <&wf_2g_5g_pins>; + pinctrl-1 = <&wf_dbdc_pins>; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt7986b.dtsi b/arch/arm64/boot/dts/mediatek/mt7986b.dtsi index 23923b9f8944..db5189664c29 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986b.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7986b.dtsi @@ -5,6 +5,9 @@ */ #include "mt7986a.dtsi" +/ { + compatible = "mediatek,mt7986b"; +}; &pio { compatible = "mediatek,mt7986b-pinctrl"; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi index b4b86bb1f1a7..7fc4c592a908 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi @@ -221,11 +221,6 @@ }; }; -&afe { - i2s3-share = "I2S2"; - i2s0-share = "I2S5"; -}; - &auxadc { status = "okay"; }; @@ -378,7 +373,6 @@ mmc-pwrseq = <&wifi_pwrseq>; bus-width = <4>; max-frequency = <200000000>; - drv-type = <2>; cap-sd-highspeed; sd-uhs-sdr50; sd-uhs-sdr104; diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi index 64693c17af9e..c326aeb33a10 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -198,16 +198,19 @@ l2_0: l2-cache0 { compatible = "cache"; + cache-level = <2>; next-level-cache = <&l3_0>; }; l2_1: l2-cache1 { compatible = "cache"; + cache-level = <2>; next-level-cache = <&l3_0>; }; l3_0: l3-cache { compatible = "cache"; + cache-level = <3>; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 6b20376191a7..424fc89cc6f7 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -169,16 +169,19 @@ l2_0: l2-cache0 { compatible = "cache"; + cache-level = <2>; next-level-cache = <&l3_0>; }; l2_1: l2-cache1 { compatible = "cache"; + cache-level = <2>; next-level-cache = <&l3_0>; }; l3_0: l3-cache { compatible = "cache"; + cache-level = <3>; }; idle-states { diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi index 9b62e161db26..560103e29017 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -120,6 +120,78 @@ }; }; +&dp_intf0 { + status = "okay"; + + port { + dp_intf0_out: endpoint { + remote-endpoint = <&edp_in>; + }; + }; +}; + +&dp_intf1 { + status = "okay"; + + port { + dp_intf1_out: endpoint { + remote-endpoint = <&dptx_in>; + }; + }; +}; + +&edp_tx { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&edptx_pins_default>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + edp_in: endpoint { + remote-endpoint = <&dp_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + edp_out: endpoint { + data-lanes = <0 1 2 3>; + }; + }; + }; +}; + +&dp_tx { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&dptx_pin>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dptx_in: endpoint { + remote-endpoint = <&dp_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dptx_out: endpoint { + data-lanes = <0 1 2 3>; + }; + }; + }; +}; + &i2c0 { status = "okay"; @@ -479,6 +551,20 @@ }; }; + edptx_pins_default: edptx-default-pins { + pins-cmd-dat { + pinmux = <PINMUX_GPIO7__FUNC_EDP_TX_HPD>; + bias-pull-up; + }; + }; + + dptx_pin: dptx-default-pins { + pins-cmd-dat { + pinmux = <PINMUX_GPIO18__FUNC_DP_TX_HPD>; + bias-pull-up; + }; + }; + i2c0_pins: i2c0-default-pins { pins-bus { pinmux = <PINMUX_GPIO8__FUNC_SDA0>, diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 905d1a90b406..5d31536f4c48 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -13,6 +13,7 @@ #include <dt-bindings/phy/phy.h> #include <dt-bindings/pinctrl/mt8195-pinfunc.h> #include <dt-bindings/power/mt8195-power.h> +#include <dt-bindings/reset/mt8195-resets.h> / { compatible = "mediatek,mt8195"; @@ -36,7 +37,7 @@ enable-method = "psci"; performance-domains = <&performance 0>; clock-frequency = <1701000000>; - capacity-dmips-mhz = <578>; + capacity-dmips-mhz = <308>; cpu-idle-states = <&cpu_off_l &cluster_off_l>; next-level-cache = <&l2_0>; #cooling-cells = <2>; @@ -49,7 +50,7 @@ enable-method = "psci"; performance-domains = <&performance 0>; clock-frequency = <1701000000>; - capacity-dmips-mhz = <578>; + capacity-dmips-mhz = <308>; cpu-idle-states = <&cpu_off_l &cluster_off_l>; next-level-cache = <&l2_0>; #cooling-cells = <2>; @@ -62,7 +63,7 @@ enable-method = "psci"; performance-domains = <&performance 0>; clock-frequency = <1701000000>; - capacity-dmips-mhz = <578>; + capacity-dmips-mhz = <308>; cpu-idle-states = <&cpu_off_l &cluster_off_l>; next-level-cache = <&l2_0>; #cooling-cells = <2>; @@ -75,7 +76,7 @@ enable-method = "psci"; performance-domains = <&performance 0>; clock-frequency = <1701000000>; - capacity-dmips-mhz = <578>; + capacity-dmips-mhz = <308>; cpu-idle-states = <&cpu_off_l &cluster_off_l>; next-level-cache = <&l2_0>; #cooling-cells = <2>; @@ -213,16 +214,19 @@ l2_0: l2-cache0 { compatible = "cache"; + cache-level = <2>; next-level-cache = <&l3_0>; }; l2_1: l2-cache1 { compatible = "cache"; + cache-level = <2>; next-level-cache = <&l3_0>; }; l3_0: l3-cache { compatible = "cache"; + cache-level = <3>; }; }; @@ -1182,6 +1186,110 @@ status = "disabled"; }; + pcie0: pcie@112f0000 { + compatible = "mediatek,mt8195-pcie", + "mediatek,mt8192-pcie"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + reg = <0 0x112f0000 0 0x4000>; + reg-names = "pcie-mac"; + interrupts = <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH 0>; + bus-range = <0x00 0xff>; + ranges = <0x81000000 0 0x20000000 + 0x0 0x20000000 0 0x200000>, + <0x82000000 0 0x20200000 + 0x0 0x20200000 0 0x3e00000>; + + iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE0 0x2>; + iommu-map-mask = <0x0>; + + clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P0>, + <&infracfg_ao CLK_INFRA_AO_PCIE_TL_26M>, + <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>, + <&infracfg_ao CLK_INFRA_AO_PCIE_TL_32K>, + <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>, + <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>; + clock-names = "pl_250m", "tl_26m", "tl_96m", + "tl_32k", "peri_26m", "peri_mem"; + assigned-clocks = <&topckgen CLK_TOP_TL>; + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>; + + phys = <&pciephy>; + phy-names = "pcie-phy"; + + power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P0>; + + resets = <&infracfg_ao MT8195_INFRA_RST2_PCIE_P0_SWRST>; + reset-names = "mac"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc0 0>, + <0 0 0 2 &pcie_intc0 1>, + <0 0 0 3 &pcie_intc0 2>, + <0 0 0 4 &pcie_intc0 3>; + status = "disabled"; + + pcie_intc0: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + + pcie1: pcie@112f8000 { + compatible = "mediatek,mt8195-pcie", + "mediatek,mt8192-pcie"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + reg = <0 0x112f8000 0 0x4000>; + reg-names = "pcie-mac"; + interrupts = <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH 0>; + bus-range = <0x00 0xff>; + ranges = <0x81000000 0 0x24000000 + 0x0 0x24000000 0 0x200000>, + <0x82000000 0 0x24200000 + 0x0 0x24200000 0 0x3e00000>; + + iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE1 0x2>; + iommu-map-mask = <0x0>; + + clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P1>, + <&clk26m>, + <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>, + <&clk26m>, + <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>, + /* Designer has connect pcie1 with peri_mem_p0 clock */ + <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>; + clock-names = "pl_250m", "tl_26m", "tl_96m", + "tl_32k", "peri_26m", "peri_mem"; + assigned-clocks = <&topckgen CLK_TOP_TL_P1>; + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>; + + phys = <&u3port1 PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P1>; + + resets = <&infracfg_ao MT8195_INFRA_RST2_PCIE_P1_SWRST>; + reset-names = "mac"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc1 0>, + <0 0 0 2 &pcie_intc1 1>, + <0 0 0 3 &pcie_intc1 2>, + <0 0 0 4 &pcie_intc1 3>; + status = "disabled"; + + pcie_intc1: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + nor_flash: spi@1132c000 { compatible = "mediatek,mt8195-nor", "mediatek,mt8173-nor"; @@ -1241,6 +1349,37 @@ reg = <0x189 0x2>; bits = <7 5>; }; + pciephy_rx_ln1: pciephy-rx-ln1@190,1 { + reg = <0x190 0x1>; + bits = <0 4>; + }; + pciephy_tx_ln1_nmos: pciephy-tx-ln1-nmos@190,2 { + reg = <0x190 0x1>; + bits = <4 4>; + }; + pciephy_tx_ln1_pmos: pciephy-tx-ln1-pmos@191,1 { + reg = <0x191 0x1>; + bits = <0 4>; + }; + pciephy_rx_ln0: pciephy-rx-ln0@191,2 { + reg = <0x191 0x1>; + bits = <4 4>; + }; + pciephy_tx_ln0_nmos: pciephy-tx-ln0-nmos@192,1 { + reg = <0x192 0x1>; + bits = <0 4>; + }; + pciephy_tx_ln0_pmos: pciephy-tx-ln0-pmos@192,2 { + reg = <0x192 0x1>; + bits = <4 4>; + }; + pciephy_glb_intr: pciephy-glb-intr@193 { + reg = <0x193 0x1>; + bits = <0 4>; + }; + dp_calibration: dp-data@1ac { + reg = <0x1ac 0x10>; + }; }; u3phy2: t-phy@11c40000 { @@ -1461,6 +1600,23 @@ }; }; + pciephy: phy@11e80000 { + compatible = "mediatek,mt8195-pcie-phy"; + reg = <0 0x11e80000 0 0x10000>; + reg-names = "sif"; + nvmem-cells = <&pciephy_glb_intr>, <&pciephy_tx_ln0_pmos>, + <&pciephy_tx_ln0_nmos>, <&pciephy_rx_ln0>, + <&pciephy_tx_ln1_pmos>, <&pciephy_tx_ln1_nmos>, + <&pciephy_rx_ln1>; + nvmem-cell-names = "glb_intr", "tx_ln0_pmos", + "tx_ln0_nmos", "rx_ln0", + "tx_ln1_pmos", "tx_ln1_nmos", + "rx_ln1"; + power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_PHY>; + #phy-cells = <0>; + status = "disabled"; + }; + ufsphy: ufs-phy@11fa0000 { compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy"; reg = <0 0x11fa0000 0 0xc000>; @@ -1959,6 +2115,30 @@ power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; }; + venc: video-codec@1a020000 { + compatible = "mediatek,mt8195-vcodec-enc"; + reg = <0 0x1a020000 0 0x10000>; + iommus = <&iommu_vdo M4U_PORT_L19_VENC_RCPU>, + <&iommu_vdo M4U_PORT_L19_VENC_REC>, + <&iommu_vdo M4U_PORT_L19_VENC_BSDMA>, + <&iommu_vdo M4U_PORT_L19_VENC_SV_COMV>, + <&iommu_vdo M4U_PORT_L19_VENC_RD_COMV>, + <&iommu_vdo M4U_PORT_L19_VENC_CUR_LUMA>, + <&iommu_vdo M4U_PORT_L19_VENC_CUR_CHROMA>, + <&iommu_vdo M4U_PORT_L19_VENC_REF_LUMA>, + <&iommu_vdo M4U_PORT_L19_VENC_REF_CHROMA>; + interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 0>; + mediatek,scp = <&scp>; + clocks = <&vencsys CLK_VENC_VENC>; + clock-names = "venc_sel"; + assigned-clocks = <&topckgen CLK_TOP_VENC>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; + power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; + #address-cells = <2>; + #size-cells = <2>; + dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; + }; + vencsys_core1: clock-controller@1b000000 { compatible = "mediatek,mt8195-vencsys_core1"; reg = <0 0x1b000000 0 0x1000>; @@ -2067,6 +2247,17 @@ mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>; }; + dp_intf0: dp-intf@1c015000 { + compatible = "mediatek,mt8195-dp-intf"; + reg = <0 0x1c015000 0 0x1000>; + interrupts = <GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&vdosys0 CLK_VDO0_DP_INTF0>, + <&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>, + <&apmixedsys CLK_APMIXED_TVDPLL1>; + clock-names = "engine", "pixel", "pll"; + status = "disabled"; + }; + mutex: mutex@1c016000 { compatible = "mediatek,mt8195-disp-mutex"; reg = <0 0x1c016000 0 0x1000>; @@ -2155,5 +2346,39 @@ clock-names = "apb", "smi", "gals"; power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; }; + + dp_intf1: dp-intf@1c113000 { + compatible = "mediatek,mt8195-dp-intf"; + reg = <0 0x1c113000 0 0x1000>; + interrupts = <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + clocks = <&vdosys1 CLK_VDO1_DP_INTF0_MM>, + <&vdosys1 CLK_VDO1_DPINTF>, + <&apmixedsys CLK_APMIXED_TVDPLL2>; + clock-names = "engine", "pixel", "pll"; + status = "disabled"; + }; + + edp_tx: edp-tx@1c500000 { + compatible = "mediatek,mt8195-edp-tx"; + reg = <0 0x1c500000 0 0x8000>; + nvmem-cells = <&dp_calibration>; + nvmem-cell-names = "dp_calibration_data"; + power-domains = <&spm MT8195_POWER_DOMAIN_EPD_TX>; + interrupts = <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH 0>; + max-linkrate-mhz = <8100>; + status = "disabled"; + }; + + dp_tx: dp-tx@1c600000 { + compatible = "mediatek,mt8195-dp-tx"; + reg = <0 0x1c600000 0 0x8000>; + nvmem-cells = <&dp_calibration>; + nvmem-cell-names = "dp_calibration_data"; + power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>; + interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0>; + max-linkrate-mhz = <8100>; + status = "disabled"; + }; }; }; diff --git a/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi b/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi index 8ee1529683a3..ec8dfb3d1c6d 100644 --- a/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi +++ b/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi @@ -17,7 +17,7 @@ }; firmware { - optee: optee@4fd00000 { + optee: optee { compatible = "linaro,optee-tz"; method = "smc"; }; @@ -209,7 +209,7 @@ }; }; - i2c0_pins_a: i2c0@0 { + i2c0_pins_a: i2c0 { pins1 { pinmux = <MT8516_PIN_58_SDA0__FUNC_SDA0_0>, <MT8516_PIN_59_SCL0__FUNC_SCL0_0>; @@ -217,7 +217,7 @@ }; }; - i2c2_pins_a: i2c2@0 { + i2c2_pins_a: i2c2 { pins1 { pinmux = <MT8516_PIN_60_SDA2__FUNC_SDA2_0>, <MT8516_PIN_61_SCL2__FUNC_SCL2_0>; diff --git a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts index d461da0b8049..3e8dee85d55f 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts +++ b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts @@ -62,7 +62,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinmux_default>; - pinmux_default: pinmux@0 { + pinmux_default: pinmux { dap_mclk1_pw4 { nvidia,pins = "dap_mclk1_pw4"; nvidia,function = "extperiph1"; diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi index 3673f79adf1a..858fc01cecb6 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi @@ -393,7 +393,6 @@ reg = <0x0 0x7000a000 0x0 0x100>; #pwm-cells = <2>; clocks = <&tegra_car TEGRA124_CLK_PWM>; - clock-names = "pwm"; resets = <&tegra_car 17>; reset-names = "pwm"; status = "disabled"; diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 6602fe421ee8..b3f1494c02c1 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -78,7 +78,8 @@ reg = <0x0 0x2600000 0x0 0x210000>; resets = <&bpmp TEGRA186_RESET_GPCDMA>; reset-names = "gpcdma"; - interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, @@ -112,6 +113,7 @@ #dma-cells = <1>; iommus = <&smmu TEGRA186_SID_GPCDMA_0>; dma-coherent; + dma-channel-mask = <0xfffffffe>; status = "okay"; }; @@ -790,7 +792,6 @@ compatible = "nvidia,tegra186-pwm"; reg = <0x0 0x3280000 0x0 0x10000>; clocks = <&bpmp TEGRA186_CLK_PWM1>; - clock-names = "pwm"; resets = <&bpmp TEGRA186_RESET_PWM1>; reset-names = "pwm"; status = "disabled"; @@ -801,7 +802,6 @@ compatible = "nvidia,tegra186-pwm"; reg = <0x0 0x3290000 0x0 0x10000>; clocks = <&bpmp TEGRA186_CLK_PWM2>; - clock-names = "pwm"; resets = <&bpmp TEGRA186_RESET_PWM2>; reset-names = "pwm"; status = "disabled"; @@ -812,7 +812,6 @@ compatible = "nvidia,tegra186-pwm"; reg = <0x0 0x32a0000 0x0 0x10000>; clocks = <&bpmp TEGRA186_CLK_PWM3>; - clock-names = "pwm"; resets = <&bpmp TEGRA186_RESET_PWM3>; reset-names = "pwm"; status = "disabled"; @@ -823,7 +822,6 @@ compatible = "nvidia,tegra186-pwm"; reg = <0x0 0x32c0000 0x0 0x10000>; clocks = <&bpmp TEGRA186_CLK_PWM5>; - clock-names = "pwm"; resets = <&bpmp TEGRA186_RESET_PWM5>; reset-names = "pwm"; status = "disabled"; @@ -834,7 +832,6 @@ compatible = "nvidia,tegra186-pwm"; reg = <0x0 0x32d0000 0x0 0x10000>; clocks = <&bpmp TEGRA186_CLK_PWM6>; - clock-names = "pwm"; resets = <&bpmp TEGRA186_RESET_PWM6>; reset-names = "pwm"; status = "disabled"; @@ -845,7 +842,6 @@ compatible = "nvidia,tegra186-pwm"; reg = <0x0 0x32e0000 0x0 0x10000>; clocks = <&bpmp TEGRA186_CLK_PWM7>; - clock-names = "pwm"; resets = <&bpmp TEGRA186_RESET_PWM7>; reset-names = "pwm"; status = "disabled"; @@ -856,7 +852,6 @@ compatible = "nvidia,tegra186-pwm"; reg = <0x0 0x32f0000 0x0 0x10000>; clocks = <&bpmp TEGRA186_CLK_PWM8>; - clock-names = "pwm"; resets = <&bpmp TEGRA186_RESET_PWM8>; reset-names = "pwm"; status = "disabled"; @@ -1274,7 +1269,6 @@ compatible = "nvidia,tegra186-pwm"; reg = <0x0 0xc340000 0x0 0x10000>; clocks = <&bpmp TEGRA186_CLK_PWM4>; - clock-names = "pwm"; resets = <&bpmp TEGRA186_RESET_PWM4>; reset-names = "pwm"; status = "disabled"; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi index b0f9393dd39c..cd272d407e01 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi @@ -23,7 +23,7 @@ }; chosen { - bootargs = "console=ttyS0,115200n8"; + bootargs = "console=ttyTCU0,115200n8"; stdout-path = "serial0:115200n8"; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi index 273a1ef716b6..f212f6aced04 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi @@ -2117,8 +2117,8 @@ "usb-b-connector"; label = "micro-USB"; type = "micro"; - vbus-gpio = <&gpio TEGRA194_MAIN_GPIO(Z, 1) - GPIO_ACTIVE_LOW>; + vbus-gpios = <&gpio TEGRA194_MAIN_GPIO(Z, 1) + GPIO_ACTIVE_LOW>; }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p3668.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p3668.dtsi index 0bd66f9c620b..0751edddf7d5 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p3668.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p3668.dtsi @@ -20,7 +20,7 @@ }; chosen { - bootargs = "console=ttyS0,115200n8"; + bootargs = "console=ttyTCU0,115200n8"; stdout-path = "serial0:115200n8"; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 41f3a7e188d0..4afcbd60e144 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -86,6 +86,7 @@ interrupt-controller; #gpio-cells = <2>; gpio-controller; + gpio-ranges = <&pinmux 0 0 169>; }; cbb-noc@2300000 { @@ -142,7 +143,8 @@ reg = <0x2600000 0x210000>; resets = <&bpmp TEGRA194_RESET_GPCDMA>; reset-names = "gpcdma"; - interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, @@ -176,6 +178,7 @@ #dma-cells = <1>; iommus = <&smmu TEGRA194_SID_GPCDMA_0>; dma-coherent; + dma-channel-mask = <0xfffffffe>; status = "okay"; }; @@ -626,12 +629,10 @@ pinmux: pinmux@2430000 { compatible = "nvidia,tegra194-pinmux"; - reg = <0x2430000 0x17000>, - <0xc300000 0x4000>; - + reg = <0x2430000 0x17000>; status = "okay"; - pex_rst_c5_out_state: pex_rst_c5_out { + pex_rst_c5_out_state: pinmux-pex-rst-c5-out { pex_rst { nvidia,pins = "pex_l5_rst_n_pgg1"; nvidia,schmitt = <TEGRA_PIN_DISABLE>; @@ -642,7 +643,7 @@ }; }; - clkreq_c5_bi_dir_state: clkreq_c5_bi_dir { + clkreq_c5_bi_dir_state: pinmux-clkreq-c5-bi-dir { clkreq { nvidia,pins = "pex_l5_clkreq_n_pgg0"; nvidia,schmitt = <TEGRA_PIN_DISABLE>; @@ -935,7 +936,6 @@ <&bpmp TEGRA194_CLK_QSPI0_PM>; clock-names = "qspi", "qspi_out"; resets = <&bpmp TEGRA194_RESET_QSPI0>; - reset-names = "qspi"; status = "disabled"; }; @@ -949,7 +949,6 @@ <&bpmp TEGRA194_CLK_QSPI1_PM>; clock-names = "qspi", "qspi_out"; resets = <&bpmp TEGRA194_RESET_QSPI1>; - reset-names = "qspi"; status = "disabled"; }; @@ -958,7 +957,6 @@ "nvidia,tegra186-pwm"; reg = <0x3280000 0x10000>; clocks = <&bpmp TEGRA194_CLK_PWM1>; - clock-names = "pwm"; resets = <&bpmp TEGRA194_RESET_PWM1>; reset-names = "pwm"; status = "disabled"; @@ -970,7 +968,6 @@ "nvidia,tegra186-pwm"; reg = <0x3290000 0x10000>; clocks = <&bpmp TEGRA194_CLK_PWM2>; - clock-names = "pwm"; resets = <&bpmp TEGRA194_RESET_PWM2>; reset-names = "pwm"; status = "disabled"; @@ -982,7 +979,6 @@ "nvidia,tegra186-pwm"; reg = <0x32a0000 0x10000>; clocks = <&bpmp TEGRA194_CLK_PWM3>; - clock-names = "pwm"; resets = <&bpmp TEGRA194_RESET_PWM3>; reset-names = "pwm"; status = "disabled"; @@ -994,7 +990,6 @@ "nvidia,tegra186-pwm"; reg = <0x32c0000 0x10000>; clocks = <&bpmp TEGRA194_CLK_PWM5>; - clock-names = "pwm"; resets = <&bpmp TEGRA194_RESET_PWM5>; reset-names = "pwm"; status = "disabled"; @@ -1006,7 +1001,6 @@ "nvidia,tegra186-pwm"; reg = <0x32d0000 0x10000>; clocks = <&bpmp TEGRA194_CLK_PWM6>; - clock-names = "pwm"; resets = <&bpmp TEGRA194_RESET_PWM6>; reset-names = "pwm"; status = "disabled"; @@ -1018,7 +1012,6 @@ "nvidia,tegra186-pwm"; reg = <0x32e0000 0x10000>; clocks = <&bpmp TEGRA194_CLK_PWM7>; - clock-names = "pwm"; resets = <&bpmp TEGRA194_RESET_PWM7>; reset-names = "pwm"; status = "disabled"; @@ -1030,7 +1023,6 @@ "nvidia,tegra186-pwm"; reg = <0x32f0000 0x10000>; clocks = <&bpmp TEGRA194_CLK_PWM8>; - clock-names = "pwm"; resets = <&bpmp TEGRA194_RESET_PWM8>; reset-names = "pwm"; status = "disabled"; @@ -1154,7 +1146,7 @@ }; hda@3510000 { - compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda"; + compatible = "nvidia,tegra194-hda"; reg = <0x3510000 0x10000>; interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA194_CLK_HDA>, @@ -1366,6 +1358,16 @@ status = "disabled"; }; + hte_lic: hardware-timestamp@3aa0000 { + compatible = "nvidia,tegra194-gte-lic"; + reg = <0x3aa0000 0x10000>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + nvidia,int-threshold = <1>; + nvidia,slices = <11>; + #timestamp-cells = <1>; + status = "okay"; + }; + hsp_top0: hsp@3c00000 { compatible = "nvidia,tegra194-hsp"; reg = <0x03c00000 0xa0000>; @@ -1579,6 +1581,16 @@ #mbox-cells = <2>; }; + hte_aon: hardware-timestamp@c1e0000 { + compatible = "nvidia,tegra194-gte-aon"; + reg = <0xc1e0000 0x10000>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + nvidia,int-threshold = <1>; + nvidia,slices = <3>; + #timestamp-cells = <1>; + status = "okay"; + }; + gen2_i2c: i2c@c240000 { compatible = "nvidia,tegra194-i2c"; reg = <0x0c240000 0x10000>; @@ -1660,6 +1672,14 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-range = <&pinmux_aon 0 0 30>; + }; + + pinmux_aon: pinmux@c300000 { + compatible = "nvidia,tegra194-pinmux-aon"; + reg = <0xc300000 0x4000>; + + status = "okay"; }; pwm4: pwm@c340000 { @@ -1667,7 +1687,6 @@ "nvidia,tegra186-pwm"; reg = <0xc340000 0x10000>; clocks = <&bpmp TEGRA194_CLK_PWM4>; - clock-names = "pwm"; resets = <&bpmp TEGRA194_RESET_PWM4>; reset-names = "pwm"; status = "disabled"; @@ -1895,7 +1914,7 @@ #address-cells = <1>; #size-cells = <1>; - ranges = <0x15000000 0x15000000 0x01000000>; + ranges = <0x14800000 0x14800000 0x02800000>; interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>; interconnect-names = "dma-mem"; iommus = <&smmu TEGRA194_SID_HOST1X>; @@ -3029,36 +3048,51 @@ }; l2c_0: l2-cache0 { + compatible = "cache"; + cache-unified; cache-size = <2097152>; cache-line-size = <64>; cache-sets = <2048>; + cache-level = <2>; next-level-cache = <&l3c>; }; l2c_1: l2-cache1 { + compatible = "cache"; + cache-unified; cache-size = <2097152>; cache-line-size = <64>; cache-sets = <2048>; + cache-level = <2>; next-level-cache = <&l3c>; }; l2c_2: l2-cache2 { + compatible = "cache"; + cache-unified; cache-size = <2097152>; cache-line-size = <64>; cache-sets = <2048>; + cache-level = <2>; next-level-cache = <&l3c>; }; l2c_3: l2-cache3 { + compatible = "cache"; + cache-unified; cache-size = <2097152>; cache-line-size = <64>; cache-sets = <2048>; + cache-level = <2>; next-level-cache = <&l3c>; }; l3c: l3-cache { + compatible = "cache"; + cache-unified; cache-size = <4194304>; cache-line-size = <64>; + cache-level = <3>; cache-sets = <4096>; }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi index a44c56c1e56e..dd9a17922fe5 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi @@ -1293,14 +1293,14 @@ }; }; - dvfs_pwm_active_state: dvfs_pwm_active { + dvfs_pwm_active_state: pinmux-dvfs-pwm-active { dvfs_pwm_pbb1 { nvidia,pins = "dvfs_pwm_pbb1"; nvidia,tristate = <TEGRA_PIN_DISABLE>; }; }; - dvfs_pwm_inactive_state: dvfs_pwm_inactive { + dvfs_pwm_inactive_state: pinmux-dvfs-pwm-inactive { dvfs_pwm_pbb1 { nvidia,pins = "dvfs_pwm_pbb1"; nvidia,tristate = <TEGRA_PIN_ENABLE>; @@ -1368,6 +1368,7 @@ #size-cells = <0>; ethernet@1 { + compatible = "usb955,9ff"; reg = <1>; }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index 37678c337a34..2041371ea7ff 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -109,14 +109,14 @@ }; pinmux@700008d4 { - dvfs_pwm_active_state: dvfs_pwm_active { + dvfs_pwm_active_state: pinmux-dvfs-pwm-active { dvfs_pwm_pbb1 { nvidia,pins = "dvfs_pwm_pbb1"; nvidia,tristate = <TEGRA_PIN_DISABLE>; }; }; - dvfs_pwm_inactive_state: dvfs_pwm_inactive { + dvfs_pwm_inactive_state: pinmux-dvfs-pwm-inactive { dvfs_pwm_pbb1 { nvidia,pins = "dvfs_pwm_pbb1"; nvidia,tristate = <TEGRA_PIN_ENABLE>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 724e87450605..bc0cacb20d7a 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -554,42 +554,48 @@ compatible = "nvidia,tegra210-pinmux"; reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */ <0x0 0x70003000 0x0 0x294>; /* Mux registers */ - sdmmc1_3v3_drv: sdmmc1-3v3-drv { + + sdmmc1_3v3_drv: pinmux-sdmmc1-3v3-drv { sdmmc1 { nvidia,pins = "drive_sdmmc1"; nvidia,pull-down-strength = <0x8>; nvidia,pull-up-strength = <0x8>; }; }; - sdmmc1_1v8_drv: sdmmc1-1v8-drv { + + sdmmc1_1v8_drv: pinmux-sdmmc1-1v8-drv { sdmmc1 { nvidia,pins = "drive_sdmmc1"; nvidia,pull-down-strength = <0x4>; nvidia,pull-up-strength = <0x3>; }; }; - sdmmc2_1v8_drv: sdmmc2-1v8-drv { + + sdmmc2_1v8_drv: pinmux-sdmmc2-1v8-drv { sdmmc2 { nvidia,pins = "drive_sdmmc2"; nvidia,pull-down-strength = <0x10>; nvidia,pull-up-strength = <0x10>; }; }; - sdmmc3_3v3_drv: sdmmc3-3v3-drv { + + sdmmc3_3v3_drv: pinmux-sdmmc3-3v3-drv { sdmmc3 { nvidia,pins = "drive_sdmmc3"; nvidia,pull-down-strength = <0x8>; nvidia,pull-up-strength = <0x8>; }; }; - sdmmc3_1v8_drv: sdmmc3-1v8-drv { + + sdmmc3_1v8_drv: pinmux-sdmmc3-1v8-drv { sdmmc3 { nvidia,pins = "drive_sdmmc3"; nvidia,pull-down-strength = <0x4>; nvidia,pull-up-strength = <0x3>; }; }; - sdmmc4_1v8_drv: sdmmc4-1v8-drv { + + sdmmc4_1v8_drv: pinmux-sdmmc4-1v8-drv { sdmmc4 { nvidia,pins = "drive_sdmmc4"; nvidia,pull-down-strength = <0x10>; @@ -667,7 +673,6 @@ reg = <0x0 0x7000a000 0x0 0x100>; #pwm-cells = <2>; clocks = <&tegra_car TEGRA210_CLK_PWM>; - clock-names = "pwm"; resets = <&tegra_car 17>; reset-names = "pwm"; status = "disabled"; @@ -912,35 +917,33 @@ }; }; - sdmmc1_3v3: sdmmc1-3v3 { - pins = "sdmmc1"; - power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; - }; + pinmux { + sdmmc1_3v3: sdmmc1-3v3 { + pins = "sdmmc1"; + power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; + }; - sdmmc1_1v8: sdmmc1-1v8 { - pins = "sdmmc1"; - power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; - }; + sdmmc1_1v8: sdmmc1-1v8 { + pins = "sdmmc1"; + power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; + }; - sdmmc3_3v3: sdmmc3-3v3 { - pins = "sdmmc3"; - power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; - }; + sdmmc3_3v3: sdmmc3-3v3 { + pins = "sdmmc3"; + power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; + }; - sdmmc3_1v8: sdmmc3-1v8 { - pins = "sdmmc3"; - power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; - }; + sdmmc3_1v8: sdmmc3-1v8 { + pins = "sdmmc3"; + power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; + }; - pex_dpd_disable: pex_en { - pex-dpd-disable { + pex_dpd_disable: pex-dpd-disable { pins = "pex-bias", "pex-clk1", "pex-clk2"; low-power-disable; }; - }; - pex_dpd_enable: pex_dis { - pex-dpd-enable { + pex_dpd_enable: pex-dpd-enable { pins = "pex-bias", "pex-clk1", "pex-clk2"; low-power-enable; }; @@ -1865,7 +1868,6 @@ <&tegra_car TEGRA210_CLK_QSPI_PM>; clock-names = "qspi", "qspi_out"; resets = <&tegra_car 211>; - reset-names = "qspi"; dmas = <&apbdma 5>, <&apbdma 5>; dma-names = "rx", "tx"; status = "disabled"; @@ -2005,6 +2007,7 @@ L2: l2-cache { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi index 9e4d72cfa69f..8b86ea9cb50c 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi @@ -39,7 +39,6 @@ regulator-max-microvolt = <12000000>; gpio = <&gpio TEGRA234_MAIN_GPIO(A, 1) GPIO_ACTIVE_LOW>; regulator-boot-on; - enable-active-low; }; bus@0 { @@ -55,6 +54,13 @@ }; }; + mmc@3400000 { + status = "okay"; + bus-width = <4>; + cd-gpios = <&gpio TEGRA234_MAIN_GPIO(G, 7) GPIO_ACTIVE_LOW>; + disable-wp; + }; + mmc@3460000 { status = "okay"; bus-width = <8>; diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts index 57ab75328814..96aa2267b06d 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts @@ -2007,6 +2007,17 @@ status = "okay"; }; + serial@31d0000 { + current-speed = <115200>; + status = "okay"; + }; + + pwm@32a0000 { + assigned-clocks = <&bpmp TEGRA234_CLK_PWM3>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; + status = "okay"; + }; + hda@3510000 { nvidia,model = "NVIDIA Jetson AGX Orin HDA"; status = "okay"; @@ -2014,7 +2025,7 @@ }; chosen { - bootargs = "console=ttyS0,115200n8"; + bootargs = "console=ttyTCU0,115200n8"; stdout-path = "serial0:115200n8"; }; @@ -2184,4 +2195,12 @@ phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4", "p2u-5", "p2u-6", "p2u-7"; }; + + pwm-fan { + compatible = "pwm-fan"; + pwms = <&pwm3 0 45334>; + + cooling-levels = <0 95 178 255>; + #cooling-cells = <2>; + }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000.dtsi index a85993c85e45..e76894574d32 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000.dtsi @@ -2,4 +2,18 @@ / { compatible = "nvidia,p3737-0000"; + + bus@0 { + pwm@3280000 { + status = "okay"; + }; + + pwm@32c0000 { + status = "okay"; + }; + + pwm@32f0000 { + status = "okay"; + }; + }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 0170bfa8a467..eaf05ee9acd1 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -7,6 +7,7 @@ #include <dt-bindings/memory/tegra234-mc.h> #include <dt-bindings/power/tegra234-powergate.h> #include <dt-bindings/reset/tegra234-reset.h> +#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> / { compatible = "nvidia,tegra234"; @@ -27,7 +28,8 @@ reg = <0x2600000 0x210000>; resets = <&bpmp TEGRA234_RESET_GPCDMA>; reset-names = "gpcdma"; - interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, @@ -60,6 +62,7 @@ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; #dma-cells = <1>; iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; + dma-channel-mask = <0xfffffffe>; dma-coherent; }; @@ -564,7 +567,7 @@ #address-cells = <1>; #size-cells = <1>; - ranges = <0x15000000 0x15000000 0x01000000>; + ranges = <0x14800000 0x14800000 0x02000000>; interconnects = <&mc TEGRA234_MEMORY_CLIENT_HOST1XDMAR &emc>; interconnect-names = "dma-mem"; iommus = <&smmu_niso1 TEGRA234_SID_HOST1X>; @@ -603,6 +606,42 @@ iommus = <&smmu_niso1 TEGRA234_SID_VIC>; dma-coherent; }; + + nvdec@15480000 { + compatible = "nvidia,tegra234-nvdec"; + reg = <0x15480000 0x00040000>; + clocks = <&bpmp TEGRA234_CLK_NVDEC>, + <&bpmp TEGRA234_CLK_FUSE>, + <&bpmp TEGRA234_CLK_TSEC_PKA>; + clock-names = "nvdec", "fuse", "tsec_pka"; + resets = <&bpmp TEGRA234_RESET_NVDEC>; + reset-names = "nvdec"; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVDEC>; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVDECSRD &emc>, + <&mc TEGRA234_MEMORY_CLIENT_NVDECSWR &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu_niso1 TEGRA234_SID_NVDEC>; + dma-coherent; + + nvidia,memory-controller = <&mc>; + + /* + * Placeholder values that firmware needs to update with the real + * offsets parsed from the microcode headers. + */ + nvidia,bl-manifest-offset = <0>; + nvidia,bl-data-offset = <0>; + nvidia,bl-code-offset = <0>; + nvidia,os-manifest-offset = <0>; + nvidia,os-data-offset = <0>; + nvidia,os-code-offset = <0>; + + /* + * Firmware needs to set this to "okay" once the above values have + * been updated. + */ + status = "disabled"; + }; }; gpio: gpio@2200000 { @@ -836,6 +875,13 @@ dma-names = "rx", "tx"; }; + uarti: serial@31d0000 { + compatible = "arm,sbsa-uart"; + reg = <0x31d0000 0x10000>; + interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + dp_aux_ch3_i2c: i2c@31e0000 { compatible = "nvidia,tegra194-i2c"; reg = <0x31e0000 0x100>; @@ -865,22 +911,79 @@ <&bpmp TEGRA234_CLK_QSPI0_PM>; clock-names = "qspi", "qspi_out"; resets = <&bpmp TEGRA234_RESET_QSPI0>; - reset-names = "qspi"; status = "disabled"; }; pwm1: pwm@3280000 { - compatible = "nvidia,tegra194-pwm", - "nvidia,tegra186-pwm"; + compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; reg = <0x3280000 0x10000>; clocks = <&bpmp TEGRA234_CLK_PWM1>; - clock-names = "pwm"; resets = <&bpmp TEGRA234_RESET_PWM1>; reset-names = "pwm"; status = "disabled"; #pwm-cells = <2>; }; + pwm2: pwm@3290000 { + compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; + reg = <0x3290000 0x10000>; + clocks = <&bpmp TEGRA234_CLK_PWM2>; + resets = <&bpmp TEGRA234_RESET_PWM2>; + reset-names = "pwm"; + status = "disabled"; + #pwm-cells = <2>; + }; + + pwm3: pwm@32a0000 { + compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; + reg = <0x32a0000 0x10000>; + clocks = <&bpmp TEGRA234_CLK_PWM3>; + resets = <&bpmp TEGRA234_RESET_PWM3>; + reset-names = "pwm"; + status = "disabled"; + #pwm-cells = <2>; + }; + + pwm5: pwm@32c0000 { + compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; + reg = <0x32c0000 0x10000>; + clocks = <&bpmp TEGRA234_CLK_PWM5>; + resets = <&bpmp TEGRA234_RESET_PWM5>; + reset-names = "pwm"; + status = "disabled"; + #pwm-cells = <2>; + }; + + pwm6: pwm@32d0000 { + compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; + reg = <0x32d0000 0x10000>; + clocks = <&bpmp TEGRA234_CLK_PWM6>; + resets = <&bpmp TEGRA234_RESET_PWM6>; + reset-names = "pwm"; + status = "disabled"; + #pwm-cells = <2>; + }; + + pwm7: pwm@32e0000 { + compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; + reg = <0x32e0000 0x10000>; + clocks = <&bpmp TEGRA234_CLK_PWM7>; + resets = <&bpmp TEGRA234_RESET_PWM7>; + reset-names = "pwm"; + status = "disabled"; + #pwm-cells = <2>; + }; + + pwm8: pwm@32f0000 { + compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; + reg = <0x32f0000 0x10000>; + clocks = <&bpmp TEGRA234_CLK_PWM8>; + resets = <&bpmp TEGRA234_RESET_PWM8>; + reset-names = "pwm"; + status = "disabled"; + #pwm-cells = <2>; + }; + spi@3300000 { compatible = "nvidia,tegra234-qspi"; reg = <0x3300000 0x1000>; @@ -891,7 +994,41 @@ <&bpmp TEGRA234_CLK_QSPI1_PM>; clock-names = "qspi", "qspi_out"; resets = <&bpmp TEGRA234_RESET_QSPI1>; - reset-names = "qspi"; + status = "disabled"; + }; + + mmc@3400000 { + compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; + reg = <0x03400000 0x20000>; + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&bpmp TEGRA234_CLK_SDMMC1>, + <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>; + clock-names = "sdhci", "tmclk"; + assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC1>, + <&bpmp TEGRA234_CLK_PLLC4_MUXED>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4_MUXED>, + <&bpmp TEGRA234_CLK_PLLC4_VCO_DIV2>; + resets = <&bpmp TEGRA234_RESET_SDMMC1>; + reset-names = "sdhci"; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRA &emc>, + <&mc TEGRA234_MEMORY_CLIENT_SDMMCWA &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu_niso1 TEGRA234_SID_SDMMC1A>; + pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; + pinctrl-0 = <&sdmmc1_3v3>; + pinctrl-1 = <&sdmmc1_1v8>; + nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; + nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x07>; + nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; + nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; + nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; + nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; + nvidia,default-tap = <14>; + nvidia,default-trim = <0x8>; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-ddr50; + sd-uhs-sdr104; status = "disabled"; }; @@ -925,7 +1062,7 @@ }; hda@3510000 { - compatible = "nvidia,tegra234-hda", "nvidia,tegra30-hda"; + compatible = "nvidia,tegra234-hda"; reg = <0x3510000 0x10000>; interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA234_CLK_AZA_BIT>, @@ -967,6 +1104,198 @@ #mbox-cells = <2>; }; + p2u_hsio_0: phy@3e00000 { + compatible = "nvidia,tegra234-p2u"; + reg = <0x03e00000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_hsio_1: phy@3e10000 { + compatible = "nvidia,tegra234-p2u"; + reg = <0x03e10000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_hsio_2: phy@3e20000 { + compatible = "nvidia,tegra234-p2u"; + reg = <0x03e20000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_hsio_3: phy@3e30000 { + compatible = "nvidia,tegra234-p2u"; + reg = <0x03e30000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_hsio_4: phy@3e40000 { + compatible = "nvidia,tegra234-p2u"; + reg = <0x03e40000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_hsio_5: phy@3e50000 { + compatible = "nvidia,tegra234-p2u"; + reg = <0x03e50000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_hsio_6: phy@3e60000 { + compatible = "nvidia,tegra234-p2u"; + reg = <0x03e60000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_hsio_7: phy@3e70000 { + compatible = "nvidia,tegra234-p2u"; + reg = <0x03e70000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_nvhs_0: phy@3e90000 { + compatible = "nvidia,tegra234-p2u"; + reg = <0x03e90000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_nvhs_1: phy@3ea0000 { + compatible = "nvidia,tegra234-p2u"; + reg = <0x03ea0000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_nvhs_2: phy@3eb0000 { + compatible = "nvidia,tegra234-p2u"; + reg = <0x03eb0000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_nvhs_3: phy@3ec0000 { + compatible = "nvidia,tegra234-p2u"; + reg = <0x03ec0000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_nvhs_4: phy@3ed0000 { + compatible = "nvidia,tegra234-p2u"; + reg = <0x03ed0000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_nvhs_5: phy@3ee0000 { + compatible = "nvidia,tegra234-p2u"; + reg = <0x03ee0000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_nvhs_6: phy@3ef0000 { + compatible = "nvidia,tegra234-p2u"; + reg = <0x03ef0000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_nvhs_7: phy@3f00000 { + compatible = "nvidia,tegra234-p2u"; + reg = <0x03f00000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_gbe_0: phy@3f20000 { + compatible = "nvidia,tegra234-p2u"; + reg = <0x03f20000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_gbe_1: phy@3f30000 { + compatible = "nvidia,tegra234-p2u"; + reg = <0x03f30000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_gbe_2: phy@3f40000 { + compatible = "nvidia,tegra234-p2u"; + reg = <0x03f40000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_gbe_3: phy@3f50000 { + compatible = "nvidia,tegra234-p2u"; + reg = <0x03f50000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_gbe_4: phy@3f60000 { + compatible = "nvidia,tegra234-p2u"; + reg = <0x03f60000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_gbe_5: phy@3f70000 { + compatible = "nvidia,tegra234-p2u"; + reg = <0x03f70000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_gbe_6: phy@3f80000 { + compatible = "nvidia,tegra234-p2u"; + reg = <0x03f80000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + + p2u_gbe_7: phy@3f90000 { + compatible = "nvidia,tegra234-p2u"; + reg = <0x03f90000 0x10000>; + reg-names = "ctl"; + + #phy-cells = <0>; + }; + ethernet@6800000 { compatible = "nvidia,tegra234-mgbe"; reg = <0x06800000 0x10000>, @@ -1259,198 +1588,6 @@ status = "okay"; }; - p2u_hsio_0: phy@3e00000 { - compatible = "nvidia,tegra234-p2u"; - reg = <0x03e00000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_hsio_1: phy@3e10000 { - compatible = "nvidia,tegra234-p2u"; - reg = <0x03e10000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_hsio_2: phy@3e20000 { - compatible = "nvidia,tegra234-p2u"; - reg = <0x03e20000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_hsio_3: phy@3e30000 { - compatible = "nvidia,tegra234-p2u"; - reg = <0x03e30000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_hsio_4: phy@3e40000 { - compatible = "nvidia,tegra234-p2u"; - reg = <0x03e40000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_hsio_5: phy@3e50000 { - compatible = "nvidia,tegra234-p2u"; - reg = <0x03e50000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_hsio_6: phy@3e60000 { - compatible = "nvidia,tegra234-p2u"; - reg = <0x03e60000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_hsio_7: phy@3e70000 { - compatible = "nvidia,tegra234-p2u"; - reg = <0x03e70000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_nvhs_0: phy@3e90000 { - compatible = "nvidia,tegra234-p2u"; - reg = <0x03e90000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_nvhs_1: phy@3ea0000 { - compatible = "nvidia,tegra234-p2u"; - reg = <0x03ea0000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_nvhs_2: phy@3eb0000 { - compatible = "nvidia,tegra234-p2u"; - reg = <0x03eb0000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_nvhs_3: phy@3ec0000 { - compatible = "nvidia,tegra234-p2u"; - reg = <0x03ec0000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_nvhs_4: phy@3ed0000 { - compatible = "nvidia,tegra234-p2u"; - reg = <0x03ed0000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_nvhs_5: phy@3ee0000 { - compatible = "nvidia,tegra234-p2u"; - reg = <0x03ee0000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_nvhs_6: phy@3ef0000 { - compatible = "nvidia,tegra234-p2u"; - reg = <0x03ef0000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_nvhs_7: phy@3f00000 { - compatible = "nvidia,tegra234-p2u"; - reg = <0x03f00000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_gbe_0: phy@3f20000 { - compatible = "nvidia,tegra234-p2u"; - reg = <0x03f20000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_gbe_1: phy@3f30000 { - compatible = "nvidia,tegra234-p2u"; - reg = <0x03f30000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_gbe_2: phy@3f40000 { - compatible = "nvidia,tegra234-p2u"; - reg = <0x03f40000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_gbe_3: phy@3f50000 { - compatible = "nvidia,tegra234-p2u"; - reg = <0x03f50000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_gbe_4: phy@3f60000 { - compatible = "nvidia,tegra234-p2u"; - reg = <0x03f60000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_gbe_5: phy@3f70000 { - compatible = "nvidia,tegra234-p2u"; - reg = <0x03f70000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_gbe_6: phy@3f80000 { - compatible = "nvidia,tegra234-p2u"; - reg = <0x03f80000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - - p2u_gbe_7: phy@3f90000 { - compatible = "nvidia,tegra234-p2u"; - reg = <0x03f90000 0x10000>; - reg-names = "ctl"; - - #phy-cells = <0>; - }; - hsp_aon: hsp@c150000 { compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; reg = <0x0c150000 0x90000>; @@ -1488,7 +1625,6 @@ gen8_i2c: i2c@c250000 { compatible = "nvidia,tegra194-i2c"; reg = <0xc250000 0x100>; - nvidia,hw-instance-id = <0x7>; interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; clock-frequency = <400000>; @@ -1530,6 +1666,16 @@ gpio-controller; }; + pwm4: pwm@c340000 { + compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; + reg = <0xc340000 0x10000>; + clocks = <&bpmp TEGRA234_CLK_PWM4>; + resets = <&bpmp TEGRA234_RESET_PWM4>; + reset-names = "pwm"; + status = "disabled"; + #pwm-cells = <2>; + }; + pmc: pmc@c360000 { compatible = "nvidia,tegra234-pmc"; reg = <0x0c360000 0x10000>, @@ -1541,6 +1687,26 @@ #interrupt-cells = <2>; interrupt-controller; + + sdmmc1_3v3: sdmmc1-3v3 { + pins = "sdmmc1-hv"; + power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; + }; + + sdmmc1_1v8: sdmmc1-1v8 { + pins = "sdmmc1-hv"; + power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; + }; + + sdmmc3_3v3: sdmmc3-3v3 { + pins = "sdmmc3-hv"; + power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; + }; + + sdmmc3_1v8: sdmmc3-1v8 { + pins = "sdmmc3-hv"; + power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; + }; }; aon-fabric@c600000 { @@ -1576,7 +1742,7 @@ interrupt-controller; }; - smmu_iso: iommu@10000000{ + smmu_iso: iommu@10000000 { compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; reg = <0x10000000 0x1000000>; interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, @@ -1879,8 +2045,9 @@ reg = <0x00 0x140a0000 0x0 0x00020000>, /* appl registers (128K) */ <0x00 0x2a000000 0x0 0x00040000>, /* configuration space (256K) */ <0x00 0x2a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x2a080000 0x0 0x00040000>; /* DBI reg space (256K) */ - reg-names = "appl", "config", "atu_dma", "dbi"; + <0x00 0x2a080000 0x0 0x00040000>, /* DBI reg space (256K) */ + <0x35 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ + reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; #address-cells = <3>; #size-cells = <2>; @@ -1932,8 +2099,9 @@ reg = <0x00 0x140c0000 0x0 0x00020000>, /* appl registers (128K) */ <0x00 0x2c000000 0x0 0x00040000>, /* configuration space (256K) */ <0x00 0x2c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x2c080000 0x0 0x00040000>; /* DBI reg space (256K) */ - reg-names = "appl", "config", "atu_dma", "dbi"; + <0x00 0x2c080000 0x0 0x00040000>, /* DBI reg space (256K) */ + <0x38 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ + reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; #address-cells = <3>; #size-cells = <2>; @@ -1965,7 +2133,7 @@ bus-range = <0x0 0xff>; - ranges = <0x43000000 0x35 0x40000000 0x35 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ + ranges = <0x43000000 0x35 0x40000000 0x35 0x40000000 0x2 0xc0000000>, /* prefetchable memory (11264 MB) */ <0x02000000 0x0 0x40000000 0x38 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ <0x01000000 0x0 0x2c100000 0x00 0x2c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ @@ -1985,8 +2153,9 @@ reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */ <0x00 0x2e000000 0x0 0x00040000>, /* configuration space (256K) */ <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x2e080000 0x0 0x00040000>; /* DBI reg space (256K) */ - reg-names = "appl", "config", "atu_dma", "dbi"; + <0x00 0x2e080000 0x0 0x00040000>, /* DBI reg space (256K) */ + <0x3b 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ + reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; #address-cells = <3>; #size-cells = <2>; @@ -2038,8 +2207,9 @@ reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ - reg-names = "appl", "config", "atu_dma", "dbi"; + <0x00 0x30080000 0x0 0x00040000>, /* DBI reg space (256K) */ + <0x20 0xb0000000 0x0 0x10000000>; /* ECAM (256MB) */ + reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; #address-cells = <3>; #size-cells = <2>; @@ -2091,8 +2261,9 @@ reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ - reg-names = "appl", "config", "atu_dma", "dbi"; + <0x00 0x32080000 0x0 0x00040000>, /* DBI reg space (256K) */ + <0x20 0xf0000000 0x0 0x10000000>; /* ECAM (256MB) */ + reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; #address-cells = <3>; #size-cells = <2>; @@ -2144,8 +2315,9 @@ reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ - reg-names = "appl", "config", "atu_dma", "dbi"; + <0x00 0x34080000 0x0 0x00040000>, /* DBI reg space (256K) */ + <0x21 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ + reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; #address-cells = <3>; #size-cells = <2>; @@ -2178,7 +2350,7 @@ bus-range = <0x0 0xff>; ranges = <0x43000000 0x21 0x00000000 0x21 0x00000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ - <0x02000000 0x0 0x40000000 0x21 0xe8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ + <0x02000000 0x0 0x40000000 0x21 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ <0x01000000 0x0 0x34100000 0x00 0x34100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE3R &emc>, @@ -2197,8 +2369,9 @@ reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ - reg-names = "appl", "config", "atu_dma", "dbi"; + <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ + <0x24 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ + reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; #address-cells = <3>; #size-cells = <2>; @@ -2250,8 +2423,9 @@ reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ - reg-names = "appl", "config", "atu_dma", "dbi"; + <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ + <0x27 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ + reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; #address-cells = <3>; #size-cells = <2>; @@ -2303,8 +2477,9 @@ reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ - reg-names = "appl", "config", "atu_dma", "dbi"; + <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ + <0x2b 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ + reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; #address-cells = <3>; #size-cells = <2>; @@ -2336,7 +2511,7 @@ bus-range = <0x0 0xff>; - ranges = <0x43000000 0x27 0x40000000 0x27 0x40000000 0x3 0xe8000000>, /* prefetchable memory (16000 MB) */ + ranges = <0x43000000 0x28 0x00000000 0x28 0x00000000 0x3 0x28000000>, /* prefetchable memory (12928 MB) */ <0x02000000 0x0 0x40000000 0x2b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ <0x01000000 0x0 0x3a100000 0x00 0x3a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ @@ -2356,8 +2531,9 @@ reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */ <0x00 0x3c000000 0x0 0x00040000>, /* configuration space (256K) */ <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x3c080000 0x0 0x00040000>; /* DBI reg space (256K) */ - reg-names = "appl", "config", "atu_dma", "dbi"; + <0x00 0x3c080000 0x0 0x00040000>, /* DBI reg space (256K) */ + <0x2e 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ + reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; #address-cells = <3>; #size-cells = <2>; @@ -2409,8 +2585,9 @@ reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */ <0x00 0x3e000000 0x0 0x00040000>, /* configuration space (256K) */ <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ - <0x00 0x3e080000 0x0 0x00040000>; /* DBI reg space (256K) */ - reg-names = "appl", "config", "atu_dma", "dbi"; + <0x00 0x3e080000 0x0 0x00040000>, /* DBI reg space (256K) */ + <0x32 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ + reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; #address-cells = <3>; #size-cells = <2>; @@ -2442,7 +2619,7 @@ bus-range = <0x0 0xff>; - ranges = <0x43000000 0x2e 0x40000000 0x2e 0x40000000 0x3 0xe8000000>, /* prefetchable memory (16000 MB) */ + ranges = <0x43000000 0x30 0x00000000 0x30 0x00000000 0x2 0x28000000>, /* prefetchable memory (8832 MB) */ <0x02000000 0x0 0x40000000 0x32 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ <0x01000000 0x0 0x3e100000 0x00 0x3e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ @@ -2905,117 +3082,150 @@ }; l2c0_0: l2-cache00 { + compatible = "cache"; cache-size = <262144>; cache-line-size = <64>; cache-sets = <512>; cache-unified; + cache-level = <2>; next-level-cache = <&l3c0>; }; l2c0_1: l2-cache01 { + compatible = "cache"; cache-size = <262144>; cache-line-size = <64>; cache-sets = <512>; cache-unified; + cache-level = <2>; next-level-cache = <&l3c0>; }; l2c0_2: l2-cache02 { + compatible = "cache"; cache-size = <262144>; cache-line-size = <64>; cache-sets = <512>; cache-unified; + cache-level = <2>; next-level-cache = <&l3c0>; }; l2c0_3: l2-cache03 { + compatible = "cache"; cache-size = <262144>; cache-line-size = <64>; cache-sets = <512>; cache-unified; + cache-level = <2>; next-level-cache = <&l3c0>; }; l2c1_0: l2-cache10 { + compatible = "cache"; cache-size = <262144>; cache-line-size = <64>; cache-sets = <512>; cache-unified; + cache-level = <2>; next-level-cache = <&l3c1>; }; l2c1_1: l2-cache11 { + compatible = "cache"; cache-size = <262144>; cache-line-size = <64>; cache-sets = <512>; cache-unified; + cache-level = <2>; next-level-cache = <&l3c1>; }; l2c1_2: l2-cache12 { + compatible = "cache"; cache-size = <262144>; cache-line-size = <64>; cache-sets = <512>; cache-unified; + cache-level = <2>; next-level-cache = <&l3c1>; }; l2c1_3: l2-cache13 { + compatible = "cache"; cache-size = <262144>; cache-line-size = <64>; cache-sets = <512>; cache-unified; + cache-level = <2>; next-level-cache = <&l3c1>; }; l2c2_0: l2-cache20 { + compatible = "cache"; cache-size = <262144>; cache-line-size = <64>; cache-sets = <512>; cache-unified; + cache-level = <2>; next-level-cache = <&l3c2>; }; l2c2_1: l2-cache21 { + compatible = "cache"; cache-size = <262144>; cache-line-size = <64>; cache-sets = <512>; cache-unified; + cache-level = <2>; next-level-cache = <&l3c2>; }; l2c2_2: l2-cache22 { + compatible = "cache"; cache-size = <262144>; cache-line-size = <64>; cache-sets = <512>; cache-unified; + cache-level = <2>; next-level-cache = <&l3c2>; }; l2c2_3: l2-cache23 { + compatible = "cache"; cache-size = <262144>; cache-line-size = <64>; cache-sets = <512>; cache-unified; + cache-level = <2>; next-level-cache = <&l3c2>; }; l3c0: l3-cache0 { + compatible = "cache"; + cache-unified; cache-size = <2097152>; cache-line-size = <64>; cache-sets = <2048>; + cache-level = <3>; }; l3c1: l3-cache1 { + compatible = "cache"; + cache-unified; cache-size = <2097152>; cache-line-size = <64>; cache-sets = <2048>; + cache-level = <3>; }; l3c2: l3-cache2 { + compatible = "cache"; + cache-unified; cache-size = <2097152>; cache-line-size = <64>; cache-sets = <2048>; + cache-level = <3>; }; }; diff --git a/arch/arm64/boot/dts/renesas/condor-common.dtsi b/arch/arm64/boot/dts/renesas/condor-common.dtsi index dfbe35bf46e0..7c34d14dcd7e 100644 --- a/arch/arm64/boot/dts/renesas/condor-common.dtsi +++ b/arch/arm64/boot/dts/renesas/condor-common.dtsi @@ -21,6 +21,7 @@ chosen { stdout-path = "serial0:115200n8"; + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; }; d1_8v: regulator-2 { diff --git a/arch/arm64/boot/dts/renesas/draak-ebisu-panel-aa104xd12.dts b/arch/arm64/boot/dts/renesas/draak-ebisu-panel-aa104xd12.dtso index 258f8668ca36..258f8668ca36 100644 --- a/arch/arm64/boot/dts/renesas/draak-ebisu-panel-aa104xd12.dts +++ b/arch/arm64/boot/dts/renesas/draak-ebisu-panel-aa104xd12.dtso diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi index ed9400f903c9..41fbb9998cf8 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -656,7 +656,7 @@ avb0: ethernet@e6800000 { compatible = "renesas,etheravb-r8a779a0", - "renesas,etheravb-rcar-gen3"; + "renesas,etheravb-rcar-gen4"; reg = <0 0xe6800000 0 0x800>; interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, @@ -704,7 +704,7 @@ avb1: ethernet@e6810000 { compatible = "renesas,etheravb-r8a779a0", - "renesas,etheravb-rcar-gen3"; + "renesas,etheravb-rcar-gen4"; reg = <0 0xe6810000 0 0x800>; interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, @@ -752,7 +752,7 @@ avb2: ethernet@e6820000 { compatible = "renesas,etheravb-r8a779a0", - "renesas,etheravb-rcar-gen3"; + "renesas,etheravb-rcar-gen4"; reg = <0 0xe6820000 0 0x1000>; interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, @@ -800,7 +800,7 @@ avb3: ethernet@e6830000 { compatible = "renesas,etheravb-r8a779a0", - "renesas,etheravb-rcar-gen3"; + "renesas,etheravb-rcar-gen4"; reg = <0 0xe6830000 0 0x1000>; interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, @@ -848,7 +848,7 @@ avb4: ethernet@e6840000 { compatible = "renesas,etheravb-r8a779a0", - "renesas,etheravb-rcar-gen3"; + "renesas,etheravb-rcar-gen4"; reg = <0 0xe6840000 0 0x1000>; interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>, @@ -896,7 +896,7 @@ avb5: ethernet@e6850000 { compatible = "renesas,etheravb-r8a779a0", - "renesas,etheravb-rcar-gen3"; + "renesas,etheravb-rcar-gen4"; reg = <0 0xe6850000 0 0x1000>; interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, @@ -1019,7 +1019,7 @@ msiof0: spi@e6e90000 { compatible = "renesas,msiof-r8a779a0", - "renesas,rcar-gen3-msiof"; + "renesas,rcar-gen4-msiof"; reg = <0 0xe6e90000 0 0x0064>; interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 618>; @@ -1034,7 +1034,7 @@ msiof1: spi@e6ea0000 { compatible = "renesas,msiof-r8a779a0", - "renesas,rcar-gen3-msiof"; + "renesas,rcar-gen4-msiof"; reg = <0 0xe6ea0000 0 0x0064>; interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 619>; @@ -1049,7 +1049,7 @@ msiof2: spi@e6c00000 { compatible = "renesas,msiof-r8a779a0", - "renesas,rcar-gen3-msiof"; + "renesas,rcar-gen4-msiof"; reg = <0 0xe6c00000 0 0x0064>; interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 620>; @@ -1064,7 +1064,7 @@ msiof3: spi@e6c10000 { compatible = "renesas,msiof-r8a779a0", - "renesas,rcar-gen3-msiof"; + "renesas,rcar-gen4-msiof"; reg = <0 0xe6c10000 0 0x0064>; interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 621>; @@ -1079,7 +1079,7 @@ msiof4: spi@e6c20000 { compatible = "renesas,msiof-r8a779a0", - "renesas,rcar-gen3-msiof"; + "renesas,rcar-gen4-msiof"; reg = <0 0xe6c20000 0 0x0064>; interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 622>; @@ -1094,7 +1094,7 @@ msiof5: spi@e6c28000 { compatible = "renesas,msiof-r8a779a0", - "renesas,rcar-gen3-msiof"; + "renesas,rcar-gen4-msiof"; reg = <0 0xe6c28000 0 0x0064>; interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 623>; diff --git a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi index a45df1041705..045d70535519 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi @@ -12,13 +12,13 @@ compatible = "renesas,spider-cpu", "renesas,r8a779f0"; aliases { - serial0 = &scif3; + serial0 = &hscif0; serial1 = &scif0; }; chosen { bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; - stdout-path = "serial0:115200n8"; + stdout-path = "serial0:1843200n8"; }; memory@48000000 { @@ -59,6 +59,14 @@ clock-frequency = <32768>; }; +&hscif0 { + pinctrl-0 = <&hscif0_pins>; + pinctrl-names = "default"; + + uart-has-rtscts; + status = "okay"; +}; + &i2c4 { pinctrl-0 = <&i2c4_pins>; pinctrl-names = "default"; @@ -99,6 +107,11 @@ pinctrl-0 = <&scif_clk_pins>; pinctrl-names = "default"; + hscif0_pins: hscif0 { + groups = "hscif0_data", "hscif0_ctrl"; + function = "hscif0"; + }; + i2c4_pins: i2c4 { groups = "i2c4"; function = "i2c4"; @@ -115,11 +128,6 @@ function = "scif0"; }; - scif3_pins: scif3 { - groups = "scif3_data", "scif3_ctrl"; - function = "scif3"; - }; - scif_clk_pins: scif_clk { groups = "scif_clk"; function = "scif_clk"; @@ -139,14 +147,6 @@ status = "okay"; }; -&scif3 { - pinctrl-0 = <&scif3_pins>; - pinctrl-names = "default"; - - uart-has-rtscts; - status = "okay"; -}; - &scif_clk { clock-frequency = <24000000>; }; diff --git a/arch/arm64/boot/dts/renesas/r8a779f0-spider-ethernet.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0-spider-ethernet.dtsi index 15e8d1ebf575..33c1015e9ab3 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0-spider-ethernet.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider-ethernet.dtsi @@ -5,6 +5,10 @@ * Copyright (C) 2021 Renesas Electronics Corp. */ +ð_serdes { + status = "okay"; +}; + &i2c4 { eeprom@52 { compatible = "rohm,br24g01", "atmel,24c01"; @@ -13,3 +17,89 @@ pagesize = <8>; }; }; + +&pfc { + tsn0_pins: tsn0 { + groups = "tsn0_mdio_b", "tsn0_link_b"; + function = "tsn0"; + power-source = <1800>; + }; + + tsn1_pins: tsn1 { + groups = "tsn1_mdio_b", "tsn1_link_b"; + function = "tsn1"; + power-source = <1800>; + }; + + tsn2_pins: tsn2 { + groups = "tsn2_mdio_b", "tsn2_link_b"; + function = "tsn2"; + power-source = <1800>; + }; +}; + +&rswitch { + pinctrl-0 = <&tsn0_pins>, <&tsn1_pins>, <&tsn2_pins>; + pinctrl-names = "default"; + status = "okay"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + phy-handle = <&u101>; + phy-mode = "sgmii"; + phys = <ð_serdes 0>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + u101: ethernet-phy@1 { + reg = <1>; + compatible = "ethernet-phy-ieee802.3-c45"; + interrupt-parent = <&gpio3>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; + }; + }; + }; + port@1 { + reg = <1>; + phy-handle = <&u201>; + phy-mode = "sgmii"; + phys = <ð_serdes 1>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + u201: ethernet-phy@2 { + reg = <2>; + compatible = "ethernet-phy-ieee802.3-c45"; + interrupt-parent = <&gpio3>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + }; + }; + }; + port@2 { + reg = <2>; + phy-handle = <&u301>; + phy-mode = "sgmii"; + phys = <ð_serdes 2>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + u301: ethernet-phy@3 { + reg = <3>; + compatible = "ethernet-phy-ieee802.3-c45"; + interrupt-parent = <&gpio3>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi index c2f152bcf10e..67a4f2d4480d 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi @@ -469,6 +469,16 @@ status = "disabled"; }; + eth_serdes: phy@e6444000 { + compatible = "renesas,r8a779f0-ether-serdes"; + reg = <0 0xe6444000 0 0x2800>; + clocks = <&cpg CPG_MOD 1506>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 1506>; + #phy-cells = <1>; + status = "disabled"; + }; + i2c0: i2c@e6500000 { compatible = "renesas,i2c-r8a779f0", "renesas,rcar-gen4-i2c"; @@ -577,7 +587,7 @@ reg = <0 0xe6540000 0 0x60>; interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 514>, - <&cpg CPG_CORE R8A779F0_CLK_S0D3>, + <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x31>, <&dmac0 0x30>, @@ -594,7 +604,7 @@ reg = <0 0xe6550000 0 0x60>; interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 515>, - <&cpg CPG_CORE R8A779F0_CLK_S0D3>, + <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x33>, <&dmac0 0x32>, @@ -611,7 +621,7 @@ reg = <0 0xe6560000 0 0x60>; interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 516>, - <&cpg CPG_CORE R8A779F0_CLK_S0D3>, + <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x35>, <&dmac0 0x34>, @@ -628,7 +638,7 @@ reg = <0 0xe66a0000 0 0x60>; interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 517>, - <&cpg CPG_CORE R8A779F0_CLK_S0D3>, + <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x37>, <&dmac0 0x36>, @@ -651,13 +661,113 @@ status = "disabled"; }; + rswitch: ethernet@e6880000 { + compatible = "renesas,r8a779f0-ether-switch"; + reg = <0 0xe6880000 0 0x20000>, <0 0xe68c0000 0 0x20000>; + reg-names = "base", "secure_base"; + interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mfwd_error", "race_error", + "coma_error", "gwca0_error", + "gwca1_error", "etha0_error", + "etha1_error", "etha2_error", + "gptp0_status", "gptp1_status", + "mfwd_status", "race_status", + "coma_status", "gwca0_status", + "gwca1_status", "etha0_status", + "etha1_status", "etha2_status", + "rmac0_status", "rmac1_status", + "rmac2_status", + "gwca0_rxtx0", "gwca0_rxtx1", + "gwca0_rxtx2", "gwca0_rxtx3", + "gwca0_rxtx4", "gwca0_rxtx5", + "gwca0_rxtx6", "gwca0_rxtx7", + "gwca1_rxtx0", "gwca1_rxtx1", + "gwca1_rxtx2", "gwca1_rxtx3", + "gwca1_rxtx4", "gwca1_rxtx5", + "gwca1_rxtx6", "gwca1_rxtx7", + "gwca0_rxts0", "gwca0_rxts1", + "gwca1_rxts0", "gwca1_rxts1", + "rmac0_mdio", "rmac1_mdio", + "rmac2_mdio", + "rmac0_phy", "rmac1_phy", + "rmac2_phy"; + clocks = <&cpg CPG_MOD 1505>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 1505>; + status = "disabled"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + phys = <ð_serdes 0>; + }; + port@1 { + reg = <1>; + phys = <ð_serdes 1>; + }; + port@2 { + reg = <2>; + phys = <ð_serdes 2>; + }; + }; + }; + scif0: serial@e6e60000 { compatible = "renesas,scif-r8a779f0", "renesas,rcar-gen4-scif", "renesas,scif"; reg = <0 0xe6e60000 0 64>; interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 702>, - <&cpg CPG_CORE R8A779F0_CLK_S0D3_PER>, + <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x51>, <&dmac0 0x50>, @@ -674,7 +784,7 @@ reg = <0 0xe6e68000 0 64>; interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 703>, - <&cpg CPG_CORE R8A779F0_CLK_S0D3_PER>, + <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x53>, <&dmac0 0x52>, @@ -691,7 +801,7 @@ reg = <0 0xe6c50000 0 64>; interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 704>, - <&cpg CPG_CORE R8A779F0_CLK_S0D3_PER>, + <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x57>, <&dmac0 0x56>, @@ -708,7 +818,7 @@ reg = <0 0xe6c40000 0 64>; interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 705>, - <&cpg CPG_CORE R8A779F0_CLK_S0D3_PER>, + <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x59>, <&dmac0 0x58>, diff --git a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi index 895f0bd9f754..c10740aee9f6 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi @@ -96,6 +96,24 @@ device_type = "memory"; reg = <0x6 0x00000000 0x1 0x00000000>; }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; }; &avb0 { @@ -135,6 +153,17 @@ status = "okay"; clock-frequency = <400000>; + io_expander_a: gpio@20 { + compatible = "onnn,pca9654"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + eeprom@50 { compatible = "rohm,br24g01", "atmel,24c01"; label = "cpu-board"; @@ -143,6 +172,23 @@ }; }; +&mmc0 { + pinctrl-0 = <&mmc_pins>; + pinctrl-1 = <&mmc_pins>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + bus-width = <8>; + no-sd; + no-sdio; + non-removable; + full-pwr-cycle-in-suspend; + status = "okay"; +}; + &pfc { pinctrl-0 = <&scif_clk_pins>; pinctrl-names = "default"; @@ -180,17 +226,56 @@ bias-pull-up; }; + mmc_pins: mmc { + groups = "mmc_data8", "mmc_ctrl", "mmc_ds"; + function = "mmc"; + power-source = <1800>; + }; + + qspi0_pins: qspi0 { + groups = "qspi0_ctrl", "qspi0_data4"; + function = "qspi0"; + }; + scif_clk_pins: scif_clk { groups = "scif_clk"; function = "scif_clk"; }; }; -&scif_clk { - clock-frequency = <24000000>; +&rpc { + pinctrl-0 = <&qspi0_pins>; + pinctrl-names = "default"; + + status = "okay"; + + flash@0 { + compatible = "spansion,s25fs512s", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <40000000>; + spi-rx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot@0 { + reg = <0x0 0x1200000>; + read-only; + }; + user@1200000 { + reg = <0x1200000 0x2e00000>; + }; + }; + }; }; &rwdt { timeout-sec = <60>; status = "okay"; }; + +&scif_clk { + clock-frequency = <24000000>; +}; diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi index d70f0600ae5a..45d8d927ad26 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi @@ -14,18 +14,138 @@ #address-cells = <2>; #size-cells = <2>; + cluster0_opp: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <825000>; + clock-latency-ns = <500000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <825000>; + clock-latency-ns = <500000>; + }; + opp-1500000000 { + opp-hz = /bits/ 64 <1500000000>; + opp-microvolt = <825000>; + clock-latency-ns = <500000>; + }; + opp-1700000000 { + opp-hz = /bits/ 64 <1700000000>; + opp-microvolt = <825000>; + clock-latency-ns = <500000>; + opp-suspend; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; + cpu-map { + cluster0 { + core0 { + cpu = <&a76_0>; + }; + core1 { + cpu = <&a76_1>; + }; + }; + + cluster1 { + core0 { + cpu = <&a76_2>; + }; + core1 { + cpu = <&a76_3>; + }; + }; + }; + a76_0: cpu@0 { compatible = "arm,cortex-a76"; reg = <0>; device_type = "cpu"; power-domains = <&sysc R8A779G0_PD_A1E0D0C0>; + next-level-cache = <&L3_CA76_0>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>; + operating-points-v2 = <&cluster0_opp>; + }; + + a76_1: cpu@100 { + compatible = "arm,cortex-a76"; + reg = <0x100>; + device_type = "cpu"; + power-domains = <&sysc R8A779G0_PD_A1E0D0C1>; + next-level-cache = <&L3_CA76_0>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>; + operating-points-v2 = <&cluster0_opp>; + }; + + a76_2: cpu@10000 { + compatible = "arm,cortex-a76"; + reg = <0x10000>; + device_type = "cpu"; + power-domains = <&sysc R8A779G0_PD_A1E0D1C0>; + next-level-cache = <&L3_CA76_1>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>; + operating-points-v2 = <&cluster0_opp>; + }; + + a76_3: cpu@10100 { + compatible = "arm,cortex-a76"; + reg = <0x10100>; + device_type = "cpu"; + power-domains = <&sysc R8A779G0_PD_A1E0D1C1>; + next-level-cache = <&L3_CA76_1>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; + clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>; + operating-points-v2 = <&cluster0_opp>; + }; + + idle-states { + entry-method = "psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + local-timer-stop; + entry-latency-us = <400>; + exit-latency-us = <500>; + min-residency-us = <4000>; + }; + }; + + L3_CA76_0: cache-controller-0 { + compatible = "cache"; + power-domains = <&sysc R8A779G0_PD_A2E0D0>; + cache-unified; + cache-level = <3>; + }; + + L3_CA76_1: cache-controller-1 { + compatible = "cache"; + power-domains = <&sysc R8A779G0_PD_A2E0D1>; + cache-unified; + cache-level = <3>; }; }; + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + extal_clk: extal { compatible = "fixed-clock"; #clock-cells = <0>; @@ -214,6 +334,76 @@ #interrupt-cells = <2>; }; + cmt0: timer@e60f0000 { + compatible = "renesas,r8a779g0-cmt0", + "renesas,rcar-gen4-cmt0"; + reg = <0 0xe60f0000 0 0x1004>; + interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 910>; + clock-names = "fck"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 910>; + status = "disabled"; + }; + + cmt1: timer@e6130000 { + compatible = "renesas,r8a779g0-cmt1", + "renesas,rcar-gen4-cmt1"; + reg = <0 0xe6130000 0 0x1004>; + interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 911>; + clock-names = "fck"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 911>; + status = "disabled"; + }; + + cmt2: timer@e6140000 { + compatible = "renesas,r8a779g0-cmt1", + "renesas,rcar-gen4-cmt1"; + reg = <0 0xe6140000 0 0x1004>; + interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 912>; + clock-names = "fck"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 912>; + status = "disabled"; + }; + + cmt3: timer@e6148000 { + compatible = "renesas,r8a779g0-cmt1", + "renesas,rcar-gen4-cmt1"; + reg = <0 0xe6148000 0 0x1004>; + interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 913>; + clock-names = "fck"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 913>; + status = "disabled"; + }; + cpg: clock-controller@e6150000 { compatible = "renesas,r8a779g0-cpg-mssr"; reg = <0 0xe6150000 0 0x4000>; @@ -235,12 +425,96 @@ #power-domain-cells = <1>; }; + intc_ex: interrupt-controller@e61c0000 { + compatible = "renesas,intc-ex-r8a779g0", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 611>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 611>; + }; + + tmu0: timer@e61e0000 { + compatible = "renesas,tmu-r8a779g0", "renesas,tmu"; + reg = <0 0xe61e0000 0 0x30>; + interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 713>; + clock-names = "fck"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 713>; + status = "disabled"; + }; + + tmu1: timer@e6fc0000 { + compatible = "renesas,tmu-r8a779g0", "renesas,tmu"; + reg = <0 0xe6fc0000 0 0x30>; + interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 714>; + clock-names = "fck"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 714>; + status = "disabled"; + }; + + tmu2: timer@e6fd0000 { + compatible = "renesas,tmu-r8a779g0", "renesas,tmu"; + reg = <0 0xe6fd0000 0 0x30>; + interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 715>; + clock-names = "fck"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 715>; + status = "disabled"; + }; + + tmu3: timer@e6fe0000 { + compatible = "renesas,tmu-r8a779g0", "renesas,tmu"; + reg = <0 0xe6fe0000 0 0x30>; + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 716>; + clock-names = "fck"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 716>; + status = "disabled"; + }; + + tmu4: timer@ffc00000 { + compatible = "renesas,tmu-r8a779g0", "renesas,tmu"; + reg = <0 0xffc00000 0 0x30>; + interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 717>; + clock-names = "fck"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 717>; + status = "disabled"; + }; + i2c0: i2c@e6500000 { compatible = "renesas,i2c-r8a779g0", "renesas,rcar-gen4-i2c"; reg = <0 0xe6500000 0 0x40>; interrupts = <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 518>; + dmas = <&dmac0 0x91>, <&dmac0 0x90>, + <&dmac1 0x91>, <&dmac1 0x90>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; resets = <&cpg 518>; i2c-scl-internal-delay-ns = <110>; @@ -255,6 +529,9 @@ reg = <0 0xe6508000 0 0x40>; interrupts = <GIC_SPI 611 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 519>; + dmas = <&dmac0 0x93>, <&dmac0 0x92>, + <&dmac1 0x93>, <&dmac1 0x92>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; resets = <&cpg 519>; i2c-scl-internal-delay-ns = <110>; @@ -269,6 +546,9 @@ reg = <0 0xe6510000 0 0x40>; interrupts = <GIC_SPI 612 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 520>; + dmas = <&dmac0 0x95>, <&dmac0 0x94>, + <&dmac1 0x95>, <&dmac1 0x94>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; resets = <&cpg 520>; i2c-scl-internal-delay-ns = <110>; @@ -283,6 +563,9 @@ reg = <0 0xe66d0000 0 0x40>; interrupts = <GIC_SPI 613 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 521>; + dmas = <&dmac0 0x97>, <&dmac0 0x96>, + <&dmac1 0x97>, <&dmac1 0x96>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; resets = <&cpg 521>; i2c-scl-internal-delay-ns = <110>; @@ -297,6 +580,9 @@ reg = <0 0xe66d8000 0 0x40>; interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 522>; + dma-names = "tx", "rx", "tx", "rx"; + dmas = <&dmac0 0x99>, <&dmac0 0x98>, + <&dmac1 0x99>, <&dmac1 0x98>; power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; resets = <&cpg 522>; i2c-scl-internal-delay-ns = <110>; @@ -311,6 +597,9 @@ reg = <0 0xe66e0000 0 0x40>; interrupts = <GIC_SPI 615 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 523>; + dmas = <&dmac0 0x9b>, <&dmac0 0x9a>, + <&dmac1 0x9b>, <&dmac1 0x9a>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; resets = <&cpg 523>; i2c-scl-internal-delay-ns = <110>; @@ -321,19 +610,72 @@ hscif0: serial@e6540000 { compatible = "renesas,hscif-r8a779g0", - "renesas,rcar-gen4-hscif", - "renesas,hscif"; - reg = <0 0xe6540000 0 96>; + "renesas,rcar-gen4-hscif", "renesas,hscif"; + reg = <0 0xe6540000 0 0x60>; interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 514>, - <&cpg CPG_CORE R8A779G0_CLK_S0D3_PER>, + <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x31>, <&dmac0 0x30>, + <&dmac1 0x31>, <&dmac1 0x30>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; resets = <&cpg 514>; status = "disabled"; }; + hscif1: serial@e6550000 { + compatible = "renesas,hscif-r8a779g0", + "renesas,rcar-gen4-hscif", "renesas,hscif"; + reg = <0 0xe6550000 0 0x60>; + interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 515>, + <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x33>, <&dmac0 0x32>, + <&dmac1 0x33>, <&dmac1 0x32>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 515>; + status = "disabled"; + }; + + hscif2: serial@e6560000 { + compatible = "renesas,hscif-r8a779g0", + "renesas,rcar-gen4-hscif", "renesas,hscif"; + reg = <0 0xe6560000 0 0x60>; + interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 516>, + <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x35>, <&dmac0 0x34>, + <&dmac1 0x35>, <&dmac1 0x34>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 516>; + status = "disabled"; + }; + + hscif3: serial@e66a0000 { + compatible = "renesas,hscif-r8a779g0", + "renesas,rcar-gen4-hscif", "renesas,hscif"; + reg = <0 0xe66a0000 0 0x60>; + interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 517>, + <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x37>, <&dmac0 0x36>, + <&dmac1 0x37>, <&dmac1 0x36>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 517>; + status = "disabled"; + }; + avb0: ethernet@e6800000 { compatible = "renesas,etheravb-r8a779g0", "renesas,etheravb-rcar-gen4"; @@ -475,6 +817,381 @@ status = "disabled"; }; + pwm0: pwm@e6e30000 { + compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar"; + reg = <0 0xe6e30000 0 0x10>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 628>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 628>; + status = "disabled"; + }; + + pwm1: pwm@e6e31000 { + compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar"; + reg = <0 0xe6e31000 0 0x10>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 628>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 628>; + status = "disabled"; + }; + + pwm2: pwm@e6e32000 { + compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar"; + reg = <0 0xe6e32000 0 0x10>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 628>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 628>; + status = "disabled"; + }; + + pwm3: pwm@e6e33000 { + compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar"; + reg = <0 0xe6e33000 0 0x10>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 628>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 628>; + status = "disabled"; + }; + + pwm4: pwm@e6e34000 { + compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar"; + reg = <0 0xe6e34000 0 0x10>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 628>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 628>; + status = "disabled"; + }; + + pwm5: pwm@e6e35000 { + compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar"; + reg = <0 0xe6e35000 0 0x10>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 628>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 628>; + status = "disabled"; + }; + + pwm6: pwm@e6e36000 { + compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar"; + reg = <0 0xe6e36000 0 0x10>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 628>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 628>; + status = "disabled"; + }; + + pwm7: pwm@e6e37000 { + compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar"; + reg = <0 0xe6e37000 0 0x10>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 628>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 628>; + status = "disabled"; + }; + + pwm8: pwm@e6e38000 { + compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar"; + reg = <0 0xe6e38000 0 0x10>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 628>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 628>; + status = "disabled"; + }; + + pwm9: pwm@e6e39000 { + compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar"; + reg = <0 0xe6e39000 0 0x10>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 628>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 628>; + status = "disabled"; + }; + + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a779g0", + "renesas,rcar-gen4-scif", "renesas,scif"; + reg = <0 0xe6e60000 0 64>; + interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 702>, + <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x51>, <&dmac0 0x50>, + <&dmac1 0x51>, <&dmac1 0x50>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 702>; + status = "disabled"; + }; + + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a779g0", + "renesas,rcar-gen4-scif", "renesas,scif"; + reg = <0 0xe6e68000 0 64>; + interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 703>, + <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x53>, <&dmac0 0x52>, + <&dmac1 0x53>, <&dmac1 0x52>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + }; + + scif3: serial@e6c50000 { + compatible = "renesas,scif-r8a779g0", + "renesas,rcar-gen4-scif", "renesas,scif"; + reg = <0 0xe6c50000 0 64>; + interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 704>, + <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x57>, <&dmac0 0x56>, + <&dmac1 0x57>, <&dmac1 0x56>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 704>; + status = "disabled"; + }; + + scif4: serial@e6c40000 { + compatible = "renesas,scif-r8a779g0", + "renesas,rcar-gen4-scif", "renesas,scif"; + reg = <0 0xe6c40000 0 64>; + interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 705>, + <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x59>, <&dmac0 0x58>, + <&dmac1 0x59>, <&dmac1 0x58>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 705>; + status = "disabled"; + }; + + tpu: pwm@e6e80000 { + compatible = "renesas,tpu-r8a779g0", "renesas,tpu"; + reg = <0 0xe6e80000 0 0x148>; + interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 718>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 718>; + #pwm-cells = <3>; + status = "disabled"; + }; + + msiof0: spi@e6e90000 { + compatible = "renesas,msiof-r8a779g0", + "renesas,rcar-gen4-msiof"; + reg = <0 0xe6e90000 0 0x0064>; + interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 618>; + dmas = <&dmac0 0x41>, <&dmac0 0x40>, + <&dmac1 0x41>, <&dmac1 0x40>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 618>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof1: spi@e6ea0000 { + compatible = "renesas,msiof-r8a779g0", + "renesas,rcar-gen4-msiof"; + reg = <0 0xe6ea0000 0 0x0064>; + interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 619>; + dmas = <&dmac0 0x43>, <&dmac0 0x42>, + <&dmac1 0x43>, <&dmac1 0x42>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 619>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof2: spi@e6c00000 { + compatible = "renesas,msiof-r8a779g0", + "renesas,rcar-gen4-msiof"; + reg = <0 0xe6c00000 0 0x0064>; + interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 620>; + dmas = <&dmac0 0x45>, <&dmac0 0x44>, + <&dmac1 0x45>, <&dmac1 0x44>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 620>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof3: spi@e6c10000 { + compatible = "renesas,msiof-r8a779g0", + "renesas,rcar-gen4-msiof"; + reg = <0 0xe6c10000 0 0x0064>; + interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 621>; + dmas = <&dmac0 0x47>, <&dmac0 0x46>, + <&dmac1 0x47>, <&dmac1 0x46>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 621>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof4: spi@e6c20000 { + compatible = "renesas,msiof-r8a779g0", + "renesas,rcar-gen4-msiof"; + reg = <0 0xe6c20000 0 0x0064>; + interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 622>; + dmas = <&dmac0 0x49>, <&dmac0 0x48>, + <&dmac1 0x49>, <&dmac1 0x48>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 622>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof5: spi@e6c28000 { + compatible = "renesas,msiof-r8a779g0", + "renesas,rcar-gen4-msiof"; + reg = <0 0xe6c28000 0 0x0064>; + interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 623>; + dmas = <&dmac0 0x4b>, <&dmac0 0x4a>, + <&dmac1 0x4b>, <&dmac1 0x4a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 623>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + dmac0: dma-controller@e7350000 { + compatible = "renesas,dmac-r8a779g0", + "renesas,rcar-gen4-dmac"; + reg = <0 0xe7350000 0 0x1000>, + <0 0xe7300000 0 0x10000>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", "ch4", + "ch5", "ch6", "ch7", "ch8", "ch9", + "ch10", "ch11", "ch12", "ch13", + "ch14", "ch15"; + clocks = <&cpg CPG_MOD 709>; + clock-names = "fck"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 709>; + #dma-cells = <1>; + dma-channels = <16>; + }; + + dmac1: dma-controller@e7351000 { + compatible = "renesas,dmac-r8a779g0", + "renesas,rcar-gen4-dmac"; + reg = <0 0xe7351000 0 0x1000>, + <0 0xe7310000 0 0x10000>; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", "ch4", + "ch5", "ch6", "ch7", "ch8", "ch9", + "ch10", "ch11", "ch12", "ch13", + "ch14", "ch15"; + clocks = <&cpg CPG_MOD 710>; + clock-names = "fck"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 710>; + #dma-cells = <1>; + dma-channels = <16>; + }; + + mmc0: mmc@ee140000 { + compatible = "renesas,sdhi-r8a779g0", + "renesas,rcar-gen4-sdhi"; + reg = <0 0xee140000 0 0x2000>; + interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 706>, + <&cpg CPG_CORE R8A779G0_CLK_SD0H>; + clock-names = "core", "clkh"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 706>; + max-frequency = <200000000>; + status = "disabled"; + }; + + rpc: spi@ee200000 { + compatible = "renesas,r8a779g0-rpc-if", + "renesas,rcar-gen4-rpc-if"; + reg = <0 0xee200000 0 0x200>, + <0 0x08000000 0 0x04000000>, + <0 0xee208000 0 0x100>; + reg-names = "regs", "dirmap", "wbuf"; + interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 629>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 629>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + gic: interrupt-controller@f1000000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; @@ -483,7 +1200,7 @@ reg = <0x0 0xf1000000 0 0x20000>, <0x0 0xf1060000 0 0x110000>; interrupts = <GIC_PPI 9 - (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; prr: chipid@fff00044 { @@ -494,9 +1211,9 @@ timer { compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; }; }; diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi index 689aa4ba416b..3f7d451b1199 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -1,11 +1,10 @@ // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) /* - * Device Tree Source for the RZ/G2UL SoC + * Device Tree Source for the RZ/Five and RZ/G2UL SoCs * * Copyright (C) 2022 Renesas Electronics Corp. */ -#include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/r9a07g043-cpg.h> / { @@ -69,36 +68,8 @@ }; }; - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a55"; - reg = <0>; - device_type = "cpu"; - #cooling-cells = <2>; - next-level-cache = <&L3_CA55>; - enable-method = "psci"; - clocks = <&cpg CPG_CORE R9A07G043_CLK_I>; - operating-points-v2 = <&cluster0_opp>; - }; - - L3_CA55: cache-controller-0 { - compatible = "cache"; - cache-unified; - cache-size = <0x40000>; - }; - }; - - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; - }; - soc: soc { compatible = "simple-bus"; - interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; ranges; @@ -107,10 +78,10 @@ compatible = "renesas,r9a07g043-ssi", "renesas,rz-ssi"; reg = <0 0x10049c00 0 0x400>; - interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 327 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 329 IRQ_TYPE_EDGE_RISING>; + interrupts = <SOC_PERIPHERAL_IRQ(326) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(327) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(328) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(329) IRQ_TYPE_EDGE_RISING>; interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; clocks = <&cpg CPG_MOD R9A07G043_SSI0_PCLK2>, <&cpg CPG_MOD R9A07G043_SSI0_PCLK_SFR>, @@ -128,10 +99,10 @@ compatible = "renesas,r9a07g043-ssi", "renesas,rz-ssi"; reg = <0 0x1004a000 0 0x400>; - interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 331 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 332 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 333 IRQ_TYPE_EDGE_RISING>; + interrupts = <SOC_PERIPHERAL_IRQ(330) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(331) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(332) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(333) IRQ_TYPE_EDGE_RISING>; interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; clocks = <&cpg CPG_MOD R9A07G043_SSI1_PCLK2>, <&cpg CPG_MOD R9A07G043_SSI1_PCLK_SFR>, @@ -149,10 +120,10 @@ compatible = "renesas,r9a07g043-ssi", "renesas,rz-ssi"; reg = <0 0x1004a400 0 0x400>; - interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 335 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 336 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 337 IRQ_TYPE_EDGE_RISING>; + interrupts = <SOC_PERIPHERAL_IRQ(334) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(335) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(336) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(337) IRQ_TYPE_EDGE_RISING>; interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; clocks = <&cpg CPG_MOD R9A07G043_SSI2_PCLK2>, <&cpg CPG_MOD R9A07G043_SSI2_PCLK_SFR>, @@ -170,10 +141,10 @@ compatible = "renesas,r9a07g043-ssi", "renesas,rz-ssi"; reg = <0 0x1004a800 0 0x400>; - interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 339 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 341 IRQ_TYPE_EDGE_RISING>; + interrupts = <SOC_PERIPHERAL_IRQ(338) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(339) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(340) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(341) IRQ_TYPE_EDGE_RISING>; interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; clocks = <&cpg CPG_MOD R9A07G043_SSI3_PCLK2>, <&cpg CPG_MOD R9A07G043_SSI3_PCLK_SFR>, @@ -190,9 +161,9 @@ spi0: spi@1004ac00 { compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz"; reg = <0 0x1004ac00 0 0x400>; - interrupts = <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <SOC_PERIPHERAL_IRQ(415) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(413) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(414) IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "error", "rx", "tx"; clocks = <&cpg CPG_MOD R9A07G043_RSPI0_CLKB>; resets = <&cpg R9A07G043_RSPI0_RST>; @@ -208,9 +179,9 @@ spi1: spi@1004b000 { compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz"; reg = <0 0x1004b000 0 0x400>; - interrupts = <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <SOC_PERIPHERAL_IRQ(418) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(416) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(417) IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "error", "rx", "tx"; clocks = <&cpg CPG_MOD R9A07G043_RSPI1_CLKB>; resets = <&cpg R9A07G043_RSPI1_RST>; @@ -226,9 +197,9 @@ spi2: spi@1004b400 { compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz"; reg = <0 0x1004b400 0 0x400>; - interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <SOC_PERIPHERAL_IRQ(421) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(419) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(420) IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "error", "rx", "tx"; clocks = <&cpg CPG_MOD R9A07G043_RSPI2_CLKB>; resets = <&cpg R9A07G043_RSPI2_RST>; @@ -245,12 +216,12 @@ compatible = "renesas,scif-r9a07g043", "renesas,scif-r9a07g044"; reg = <0 0x1004b800 0 0x400>; - interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <SOC_PERIPHERAL_IRQ(380) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(382) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(383) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(381) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(384) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(384) IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "eri", "rxi", "txi", "bri", "dri", "tei"; clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>; @@ -264,12 +235,12 @@ compatible = "renesas,scif-r9a07g043", "renesas,scif-r9a07g044"; reg = <0 0x1004bc00 0 0x400>; - interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <SOC_PERIPHERAL_IRQ(385) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(387) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(388) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(386) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(389) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(389) IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "eri", "rxi", "txi", "bri", "dri", "tei"; clocks = <&cpg CPG_MOD R9A07G043_SCIF1_CLK_PCK>; @@ -283,12 +254,12 @@ compatible = "renesas,scif-r9a07g043", "renesas,scif-r9a07g044"; reg = <0 0x1004c000 0 0x400>; - interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <SOC_PERIPHERAL_IRQ(390) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(392) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(393) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(391) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(394) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(394) IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "eri", "rxi", "txi", "bri", "dri", "tei"; clocks = <&cpg CPG_MOD R9A07G043_SCIF2_CLK_PCK>; @@ -302,12 +273,12 @@ compatible = "renesas,scif-r9a07g043", "renesas,scif-r9a07g044"; reg = <0 0x1004c400 0 0x400>; - interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <SOC_PERIPHERAL_IRQ(395) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(397) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(398) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(396) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(399) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(399) IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "eri", "rxi", "txi", "bri", "dri", "tei"; clocks = <&cpg CPG_MOD R9A07G043_SCIF3_CLK_PCK>; @@ -321,12 +292,12 @@ compatible = "renesas,scif-r9a07g043", "renesas,scif-r9a07g044"; reg = <0 0x1004c800 0 0x400>; - interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <SOC_PERIPHERAL_IRQ(400) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(402) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(403) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(401) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(404) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(404) IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "eri", "rxi", "txi", "bri", "dri", "tei"; clocks = <&cpg CPG_MOD R9A07G043_SCIF4_CLK_PCK>; @@ -339,10 +310,10 @@ sci0: serial@1004d000 { compatible = "renesas,r9a07g043-sci", "renesas,sci"; reg = <0 0x1004d000 0 0x400>; - interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 406 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 407 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <SOC_PERIPHERAL_IRQ(405) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(406) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(407) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(408) IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "eri", "rxi", "txi", "tei"; clocks = <&cpg CPG_MOD R9A07G043_SCI0_CLKP>; clock-names = "fck"; @@ -354,10 +325,10 @@ sci1: serial@1004d400 { compatible = "renesas,r9a07g043-sci", "renesas,sci"; reg = <0 0x1004d400 0 0x400>; - interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 410 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 411 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <SOC_PERIPHERAL_IRQ(409) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(410) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(411) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(412) IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "eri", "rxi", "txi", "tei"; clocks = <&cpg CPG_MOD R9A07G043_SCI1_CLKP>; clock-names = "fck"; @@ -369,14 +340,14 @@ canfd: can@10050000 { compatible = "renesas,r9a07g043-canfd", "renesas,rzg2l-canfd"; reg = <0 0x10050000 0 0x8000>; - interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <SOC_PERIPHERAL_IRQ(426) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(427) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(422) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(424) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(428) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(423) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(425) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(429) IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "g_err", "g_recc", "ch0_err", "ch0_rec", "ch0_trx", "ch1_err", "ch1_rec", "ch1_trx"; @@ -405,14 +376,14 @@ #size-cells = <0>; compatible = "renesas,riic-r9a07g043", "renesas,riic-rz"; reg = <0 0x10058000 0 0x400>; - interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 348 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 349 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <SOC_PERIPHERAL_IRQ(350) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(348) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(349) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(352) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(353) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(351) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(354) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(355) IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "tei", "ri", "ti", "spi", "sti", "naki", "ali", "tmoi"; clocks = <&cpg CPG_MOD R9A07G043_I2C0_PCLK>; @@ -427,14 +398,14 @@ #size-cells = <0>; compatible = "renesas,riic-r9a07g043", "renesas,riic-rz"; reg = <0 0x10058400 0 0x400>; - interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 356 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 357 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <SOC_PERIPHERAL_IRQ(358) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(356) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(357) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(360) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(361) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(359) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(362) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(363) IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "tei", "ri", "ti", "spi", "sti", "naki", "ali", "tmoi"; clocks = <&cpg CPG_MOD R9A07G043_I2C1_PCLK>; @@ -449,14 +420,14 @@ #size-cells = <0>; compatible = "renesas,riic-r9a07g043", "renesas,riic-rz"; reg = <0 0x10058800 0 0x400>; - interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <SOC_PERIPHERAL_IRQ(366) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(364) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(365) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(368) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(369) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(367) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(370) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(371) IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "tei", "ri", "ti", "spi", "sti", "naki", "ali", "tmoi"; clocks = <&cpg CPG_MOD R9A07G043_I2C2_PCLK>; @@ -471,14 +442,14 @@ #size-cells = <0>; compatible = "renesas,riic-r9a07g043", "renesas,riic-rz"; reg = <0 0x10058c00 0 0x400>; - interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 372 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <SOC_PERIPHERAL_IRQ(374) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(372) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(373) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(376) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(377) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(375) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(378) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(379) IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "tei", "ri", "ti", "spi", "sti", "naki", "ali", "tmoi"; clocks = <&cpg CPG_MOD R9A07G043_I2C3_PCLK>; @@ -491,7 +462,7 @@ adc: adc@10059000 { compatible = "renesas,r9a07g043-adc", "renesas,rzg2l-adc"; reg = <0 0x10059000 0 0x400>; - interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE_RISING>; + interrupts = <SOC_PERIPHERAL_IRQ(347) IRQ_TYPE_EDGE_RISING>; clocks = <&cpg CPG_MOD R9A07G043_ADC_ADCLK>, <&cpg CPG_MOD R9A07G043_ADC_PCLK>; clock-names = "adclk", "pclk"; @@ -551,12 +522,6 @@ sysc: system-controller@11020000 { compatible = "renesas,r9a07g043-sysc"; reg = <0 0x11020000 0 0x10000>; - interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "lpm_int", "ca55stbydone_int", - "cm33stbyr_int", "ca55_deny"; status = "disabled"; }; @@ -578,23 +543,23 @@ "renesas,rz-dmac"; reg = <0 0x11820000 0 0x10000>, <0 0x11830000 0 0x10000>; - interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>; + interrupts = <SOC_PERIPHERAL_IRQ(141) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(125) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(126) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(127) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(128) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(129) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(130) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(131) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(132) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(133) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(134) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(135) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(136) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(137) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(138) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(139) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(140) IRQ_TYPE_EDGE_RISING>; interrupt-names = "error", "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6", "ch7", @@ -609,22 +574,12 @@ dma-channels = <16>; }; - gic: interrupt-controller@11900000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x0 0x11900000 0 0x40000>, - <0x0 0x11940000 0 0x60000>; - interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; - }; - sdhi0: mmc@11c00000 { compatible = "renesas,sdhi-r9a07g043", "renesas,rcar-gen3-sdhi"; reg = <0x0 0x11c00000 0 0x10000>; - interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <SOC_PERIPHERAL_IRQ(104) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(105) IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD R9A07G043_SDHI0_IMCLK>, <&cpg CPG_MOD R9A07G043_SDHI0_CLK_HS>, <&cpg CPG_MOD R9A07G043_SDHI0_IMCLK2>, @@ -639,8 +594,8 @@ compatible = "renesas,sdhi-r9a07g043", "renesas,rcar-gen3-sdhi"; reg = <0x0 0x11c10000 0 0x10000>; - interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <SOC_PERIPHERAL_IRQ(106) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(107) IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD R9A07G043_SDHI1_IMCLK>, <&cpg CPG_MOD R9A07G043_SDHI1_CLK_HS>, <&cpg CPG_MOD R9A07G043_SDHI1_IMCLK2>, @@ -655,9 +610,9 @@ compatible = "renesas,r9a07g043-gbeth", "renesas,rzg2l-gbeth"; reg = <0 0x11c20000 0 0x10000>; - interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <SOC_PERIPHERAL_IRQ(84) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(85) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(86) IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "mux", "fil", "arp_ns"; phy-mode = "rgmii"; clocks = <&cpg CPG_MOD R9A07G043_ETH0_CLK_AXI>, @@ -675,9 +630,9 @@ compatible = "renesas,r9a07g043-gbeth", "renesas,rzg2l-gbeth"; reg = <0 0x11c30000 0 0x10000>; - interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <SOC_PERIPHERAL_IRQ(87) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(88) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(89) IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "mux", "fil", "arp_ns"; phy-mode = "rgmii"; clocks = <&cpg CPG_MOD R9A07G043_ETH1_CLK_AXI>, @@ -705,7 +660,7 @@ ohci0: usb@11c50000 { compatible = "generic-ohci"; reg = <0 0x11c50000 0 0x100>; - interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <SOC_PERIPHERAL_IRQ(91) IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, <&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>; resets = <&phyrst 0>, @@ -719,7 +674,7 @@ ohci1: usb@11c70000 { compatible = "generic-ohci"; reg = <0 0x11c70000 0 0x100>; - interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <SOC_PERIPHERAL_IRQ(96) IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, <&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>; resets = <&phyrst 1>, @@ -733,7 +688,7 @@ ehci0: usb@11c50100 { compatible = "generic-ehci"; reg = <0 0x11c50100 0 0x100>; - interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <SOC_PERIPHERAL_IRQ(92) IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, <&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>; resets = <&phyrst 0>, @@ -748,7 +703,7 @@ ehci1: usb@11c70100 { compatible = "generic-ehci"; reg = <0 0x11c70100 0 0x100>; - interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <SOC_PERIPHERAL_IRQ(97) IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, <&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>; resets = <&phyrst 1>, @@ -764,7 +719,7 @@ compatible = "renesas,usb2-phy-r9a07g043", "renesas,rzg2l-usb2-phy"; reg = <0 0x11c50200 0 0x700>; - interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <SOC_PERIPHERAL_IRQ(94) IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, <&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>; resets = <&phyrst 0>; @@ -777,7 +732,7 @@ compatible = "renesas,usb2-phy-r9a07g043", "renesas,rzg2l-usb2-phy"; reg = <0 0x11c70200 0 0x700>; - interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <SOC_PERIPHERAL_IRQ(99) IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, <&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>; resets = <&phyrst 1>; @@ -790,10 +745,10 @@ compatible = "renesas,usbhs-r9a07g043", "renesas,rza2-usbhs"; reg = <0 0x11c60000 0 0x10000>; - interrupts = <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <SOC_PERIPHERAL_IRQ(100) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(101) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(102) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(103) IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, <&cpg CPG_MOD R9A07G043_USB_U2P_EXR_CPUCLK>; resets = <&phyrst 0>, @@ -812,34 +767,19 @@ clocks = <&cpg CPG_MOD R9A07G043_WDT0_PCLK>, <&cpg CPG_MOD R9A07G043_WDT0_CLK>; clock-names = "pclk", "oscclk"; - interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <SOC_PERIPHERAL_IRQ(49) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(50) IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "wdt", "perrout"; resets = <&cpg R9A07G043_WDT0_PRESETN>; power-domains = <&cpg>; status = "disabled"; }; - wdt2: watchdog@12800400 { - compatible = "renesas,r9a07g043-wdt", - "renesas,rzg2l-wdt"; - reg = <0 0x12800400 0 0x400>; - clocks = <&cpg CPG_MOD R9A07G043_WDT2_PCLK>, - <&cpg CPG_MOD R9A07G043_WDT2_CLK>; - clock-names = "pclk", "oscclk"; - interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "wdt", "perrout"; - resets = <&cpg R9A07G043_WDT2_PRESETN>; - power-domains = <&cpg>; - status = "disabled"; - }; - ostm0: timer@12801000 { compatible = "renesas,r9a07g043-ostm", "renesas,ostm"; reg = <0x0 0x12801000 0x0 0x400>; - interrupts = <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>; + interrupts = <SOC_PERIPHERAL_IRQ(46) IRQ_TYPE_EDGE_RISING>; clocks = <&cpg CPG_MOD R9A07G043_OSTM0_PCLK>; resets = <&cpg R9A07G043_OSTM0_PRESETZ>; power-domains = <&cpg>; @@ -850,7 +790,7 @@ compatible = "renesas,r9a07g043-ostm", "renesas,ostm"; reg = <0x0 0x12801400 0x0 0x400>; - interrupts = <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>; + interrupts = <SOC_PERIPHERAL_IRQ(47) IRQ_TYPE_EDGE_RISING>; clocks = <&cpg CPG_MOD R9A07G043_OSTM1_PCLK>; resets = <&cpg R9A07G043_OSTM1_PRESETZ>; power-domains = <&cpg>; @@ -861,7 +801,7 @@ compatible = "renesas,r9a07g043-ostm", "renesas,ostm"; reg = <0x0 0x12801800 0x0 0x400>; - interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>; + interrupts = <SOC_PERIPHERAL_IRQ(48) IRQ_TYPE_EDGE_RISING>; clocks = <&cpg CPG_MOD R9A07G043_OSTM2_PCLK>; resets = <&cpg R9A07G043_OSTM2_PRESETZ>; power-domains = <&cpg>; @@ -899,12 +839,4 @@ }; }; }; - - timer { - compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; - }; }; diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi new file mode 100644 index 000000000000..6af5f3bca2d1 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G2UL SoC + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> + +#define SOC_PERIPHERAL_IRQ(nr) GIC_SPI nr + +#include "r9a07g043.dtsi" + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a55"; + reg = <0>; + device_type = "cpu"; + #cooling-cells = <2>; + next-level-cache = <&L3_CA55>; + enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A07G043_CLK_I>; + operating-points-v2 = <&cluster0_opp>; + }; + + L3_CA55: cache-controller-0 { + compatible = "cache"; + cache-unified; + cache-size = <0x40000>; + cache-level = <3>; + }; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + }; +}; + +&soc { + interrupt-parent = <&gic>; + + gic: interrupt-controller@11900000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0x11900000 0 0x40000>, + <0x0 0x11940000 0 0x60000>; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&sysc { + interrupts = <SOC_PERIPHERAL_IRQ(42) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(43) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(44) IRQ_TYPE_LEVEL_HIGH>, + <SOC_PERIPHERAL_IRQ(45) IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "lpm_int", "ca55stbydone_int", + "cm33stbyr_int", "ca55_deny"; +}; diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts index 059885a01ede..01483b4302c2 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts @@ -17,7 +17,7 @@ #define SW_SW0_DEV_SEL 1 #define SW_ET0_EN_N 1 -#include "r9a07g043.dtsi" +#include "r9a07g043u.dtsi" #include "rzg2ul-smarc-som.dtsi" #include "rzg2ul-smarc.dtsi" diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 2283d4fb8736..487536696d90 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -109,6 +109,7 @@ compatible = "cache"; cache-unified; cache-size = <0x40000>; + cache-level = <3>; }; }; @@ -644,7 +645,6 @@ reg = <0 0x11030000 0 0x10000>; gpio-controller; #gpio-cells = <2>; - #address-cells = <2>; #interrupt-cells = <2>; interrupt-parent = <&irqc>; interrupt-controller; @@ -994,21 +994,6 @@ status = "disabled"; }; - wdt2: watchdog@12800400 { - compatible = "renesas,r9a07g044-wdt", - "renesas,rzg2l-wdt"; - reg = <0 0x12800400 0 0x400>; - clocks = <&cpg CPG_MOD R9A07G044_WDT2_PCLK>, - <&cpg CPG_MOD R9A07G044_WDT2_CLK>; - clock-names = "pclk", "oscclk"; - interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "wdt", "perrout"; - resets = <&cpg R9A07G044_WDT2_PRESETN>; - power-domains = <&cpg>; - status = "disabled"; - }; - ostm0: timer@12801000 { compatible = "renesas,r9a07g044-ostm", "renesas,ostm"; diff --git a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts index fc34058002e2..f67a6f125d9c 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts @@ -6,7 +6,37 @@ */ /dts-v1/; + +/* + * DIP-Switch SW1 setting on SoM + * 1 : High; 0: Low + * SW1-2 : SW_SD0_DEV_SEL (1: eMMC; 0: uSD) + * SW1-3 : SW_SCIF_CAN (1: CAN1; 0: SCIF1) + * SW1-4 : SW_RSPI_CAN (1: CAN1; 0: RSPI1) + * SW1-5 : SW_I2S0_I2S1 (1: I2S2 (HDMI audio); 0: I2S0) + * Please change below macros according to SW1 setting + */ + +#define SW_SD0_DEV_SEL 1 + +#define SW_SCIF_CAN 0 +#if (SW_SCIF_CAN) +/* Due to HW routing, SW_RSPI_CAN is always 0 when SW_SCIF_CAN is set to 1 */ +#define SW_RSPI_CAN 0 +#else +/* Please set SW_RSPI_CAN. Default value is 1 */ +#define SW_RSPI_CAN 1 +#endif + +#if (SW_SCIF_CAN && SW_RSPI_CAN) +#error "Can not set 1 to both SW_SCIF_CAN and SW_RSPI_CAN due to HW routing" +#endif + +/* comment the #define statement to disable SCIF1 (SER0) on PMOD1 (CN7) */ +#define PMOD1_SER0 1 + #include "r9a07g044c2.dtsi" +#include "rzg2lc-smarc-som.dtsi" #include "rzg2lc-smarc.dtsi" / { diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index 358d4c34465f..304ade54425b 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -109,6 +109,7 @@ compatible = "cache"; cache-unified; cache-size = <0x40000>; + cache-level = <3>; }; }; @@ -650,7 +651,6 @@ reg = <0 0x11030000 0 0x10000>; gpio-controller; #gpio-cells = <2>; - #address-cells = <2>; #interrupt-cells = <2>; interrupt-parent = <&irqc>; interrupt-controller; @@ -1000,21 +1000,6 @@ status = "disabled"; }; - wdt2: watchdog@12800400 { - compatible = "renesas,r9a07g054-wdt", - "renesas,rzg2l-wdt"; - reg = <0 0x12800400 0 0x400>; - clocks = <&cpg CPG_MOD R9A07G054_WDT2_PCLK>, - <&cpg CPG_MOD R9A07G054_WDT2_CLK>; - clock-names = "pclk", "oscclk"; - interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "wdt", "perrout"; - resets = <&cpg R9A07G054_WDT2_PRESETN>; - power-domains = <&cpg>; - status = "disabled"; - }; - ostm0: timer@12801000 { compatible = "renesas,r9a07g054-ostm", "renesas,ostm"; diff --git a/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts b/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts index 5c15d73d059f..11e1d51c7c0e 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts @@ -83,3 +83,7 @@ &uart0 { status = "okay"; }; + +&wdt0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/renesas/r9a09g011.dtsi b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi index fb1a97202c38..0373ec409d54 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g011.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi @@ -37,8 +37,15 @@ compatible = "arm,cortex-a53"; reg = <0>; device_type = "cpu"; + next-level-cache = <&L2_CA53>; clocks = <&cpg CPG_MOD R9A09G011_CA53_CLK>; }; + + L2_CA53: cache-controller-0 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + }; }; soc: soc { @@ -48,7 +55,7 @@ #size-cells = <2>; ranges; - gic: interrupt-controller@82000000 { + gic: interrupt-controller@82010000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; #address-cells = <0>; @@ -123,10 +130,15 @@ #power-domain-cells = <0>; }; + sys: system-controller@a3f03000 { + compatible = "renesas,r9a09g011-sys"; + reg = <0 0xa3f03000 0 0x400>; + }; + i2c0: i2c@a4030000 { #address-cells = <1>; #size-cells = <0>; - compatible = "renesas,i2c-r9a09g011", "renesas,rzv2m-i2c"; + compatible = "renesas,r9a09g011-i2c", "renesas,rzv2m-i2c"; reg = <0 0xa4030000 0 0x80>; interrupts = <GIC_SPI 232 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 236 IRQ_TYPE_EDGE_RISING>; @@ -140,7 +152,7 @@ i2c2: i2c@a4030100 { #address-cells = <1>; #size-cells = <0>; - compatible = "renesas,i2c-r9a09g011", "renesas,rzv2m-i2c"; + compatible = "renesas,r9a09g011-i2c", "renesas,rzv2m-i2c"; reg = <0 0xa4030100 0 0x80>; interrupts = <GIC_SPI 234 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 238 IRQ_TYPE_EDGE_RISING>; @@ -161,6 +173,19 @@ status = "disabled"; }; + wdt0: watchdog@a4050000 { + compatible = "renesas,r9a09g011-wdt", + "renesas,rzv2m-wdt"; + reg = <0 0xa4050000 0 0x80>; + clocks = <&cpg CPG_MOD R9A09G011_WDT0_PCLK>, + <&cpg CPG_MOD R9A09G011_WDT0_CLK>; + clock-names = "pclk", "oscclk"; + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; + resets = <&cpg R9A09G011_WDT0_PRESETN>; + power-domains = <&cpg>; + status = "disabled"; + }; + pinctrl: pinctrl@b6250000 { compatible = "renesas,r9a09g011-pinctrl"; reg = <0 0xb6250000 0 0x800>; diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi index c4faff092380..fbbb4f03440b 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi @@ -351,8 +351,3 @@ status = "okay"; timeout-sec = <60>; }; - -&wdt2 { - status = "okay"; - timeout-sec = <60>; -}; diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi index 78e6e2376b01..8a0d56872de7 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi @@ -276,8 +276,3 @@ status = "okay"; timeout-sec = <60>; }; - -&wdt2 { - status = "okay"; - timeout-sec = <60>; -}; diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi index 6be25a8a28db..b6bd27196d88 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi @@ -8,37 +8,9 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/pinctrl/rzg2l-pinctrl.h> -/* - * DIP-Switch SW1 setting on SoM - * 1 : High; 0: Low - * SW1-2 : SW_SD0_DEV_SEL (1: eMMC; 0: uSD) - * SW1-3 : SW_SCIF_CAN (1: CAN1; 0: SCIF1) - * SW1-4 : SW_RSPI_CAN (1: CAN1; 0: RSPI1) - * SW1-5 : SW_I2S0_I2S1 (1: I2S2 (HDMI audio); 0: I2S0) - * Please change below macros according to SW1 setting - */ - -#define SW_SD0_DEV_SEL 1 - -#define SW_SCIF_CAN 0 -#if (SW_SCIF_CAN) -/* Due to HW routing, SW_RSPI_CAN is always 0 when SW_SCIF_CAN is set to 1 */ -#define SW_RSPI_CAN 0 -#else -/* Please set SW_RSPI_CAN. Default value is 1 */ -#define SW_RSPI_CAN 1 -#endif - -#if (SW_SCIF_CAN && SW_RSPI_CAN) -#error "Can not set 1 to both SW_SCIF_CAN and SW_RSPI_CAN due to HW routing" -#endif - -#include "rzg2lc-smarc-som.dtsi" #include "rzg2lc-smarc-pinfunction.dtsi" #include "rz-smarc-common.dtsi" -/* comment the #define statement to disable SCIF1 (SER0) on PMOD1 (CN7) */ -#define PMOD1_SER0 1 / { aliases { diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi index bd8bc858c28c..58923dc83faa 100644 --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi @@ -99,6 +99,13 @@ input-enable; }; + spi1_pins: spi1 { + pinmux = <RZG2L_PORT_PINMUX(4, 0, 2)>, /* CK */ + <RZG2L_PORT_PINMUX(4, 1, 2)>, /* MOSI */ + <RZG2L_PORT_PINMUX(4, 2, 2)>, /* MISO */ + <RZG2L_PORT_PINMUX(4, 3, 2)>; /* SSL */ + }; + ssi1_pins: ssi1 { pinmux = <RZG2L_PORT_PINMUX(3, 0, 2)>, /* BCK */ <RZG2L_PORT_PINMUX(3, 1, 2)>, /* RCK */ diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi index 2a0feb53f0dc..931efc07d6fb 100644 --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi @@ -221,13 +221,6 @@ pinmux = <RZG2L_PORT_PINMUX(0, 0, 1)>; /* SD0_CD */ }; }; - - spi1_pins: rspi1 { - pinmux = <RZG2L_PORT_PINMUX(4, 0, 2)>, /* CK */ - <RZG2L_PORT_PINMUX(4, 1, 2)>, /* MOSI */ - <RZG2L_PORT_PINMUX(4, 2, 2)>, /* MISO */ - <RZG2L_PORT_PINMUX(4, 3, 2)>; /* SSL */ - }; }; #if (SW_SW0_DEV_SEL) diff --git a/arch/arm64/boot/dts/renesas/salvator-panel-aa104xd12.dts b/arch/arm64/boot/dts/renesas/salvator-panel-aa104xd12.dtso index c83a30adc6ad..c83a30adc6ad 100644 --- a/arch/arm64/boot/dts/renesas/salvator-panel-aa104xd12.dts +++ b/arch/arm64/boot/dts/renesas/salvator-panel-aa104xd12.dtso diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 8c15593c0ca4..0a76a2ebb5f6 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -3,11 +3,15 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-engicam-px30-core-ctouch2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-engicam-px30-core-ctouch2-of10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-engicam-px30-core-edimm2.2.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-ringneck-haikou.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-evb.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-roc-cc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-rock-pi-s.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3318-a95x-z2.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-anbernic-rg351m.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-odroid-go2.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-odroid-go2-v11.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-odroid-go3.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb @@ -62,13 +66,19 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg353p.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg353v.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg353vs.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg503.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-b.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-roc-pc.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-blade.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-cm4.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-model-a.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-box-demo.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-odroid-m1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb diff --git a/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts b/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts new file mode 100644 index 000000000000..08a3ad3e7ae9 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts @@ -0,0 +1,232 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Theobroma Systems Design und Consulting GmbH + */ + +/dts-v1/; +#include "px30-ringneck.dtsi" +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> + +/ { + model = "Theobroma Systems PX30-uQ7 SoM on Haikou devkit"; + compatible = "tsd,px30-ringneck-haikou", "rockchip,px30"; + + aliases { + mmc2 = &sdmmc; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&haikou_keys_pin>; + pinctrl-names = "default"; + + button-batlow-n { + label = "BATLOW#"; + linux,code = <KEY_BATTERY>; + gpios = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>; + }; + + button-slp-btn-n { + label = "SLP_BTN#"; + linux,code = <KEY_SLEEP>; + gpios = <&gpio1 RK_PB7 GPIO_ACTIVE_LOW>; + }; + + button-wake-n { + label = "WAKE#"; + linux,code = <KEY_WAKEUP>; + gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + switch-lid-btn-n { + label = "LID_BTN#"; + linux,code = <SW_LID>; + linux,input-type = <EV_SW>; + gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + pinctrl-0 = <&module_led_pin>, <&sd_card_led_pin>; + + sd_card_led: led-1 { + gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc2"; + function = LED_FUNCTION_SD; + color = <LED_COLOR_ID_BLUE>; + }; + }; + + i2s0-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "Haikou,I2S-codec"; + simple-audio-card,mclk-fs = <512>; + + simple-audio-card,codec { + clocks = <&sgtl5000_clk>; + sound-dai = <&sgtl5000>; + }; + + simple-audio-card,cpu { + bitclock-master; + frame-master; + sound-dai = <&i2s0_8ch>; + }; + }; + + sgtl5000_clk: sgtl5000-oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + }; + + dc_12v: dc-12v-regulator { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc3v3_baseboard: vcc3v3-baseboard-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_baseboard"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_baseboard: vcc5v0-baseboard-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_baseboard"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vdda_codec: vdda-codec-regulator { + compatible = "regulator-fixed"; + regulator-name = "vdda_codec"; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_baseboard>; + }; + + vddd_codec: vddd-codec-regulator { + compatible = "regulator-fixed"; + regulator-name = "vddd_codec"; + regulator-boot-on; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1600000>; + vin-supply = <&vcc5v0_baseboard>; + }; +}; + +&i2c2 { + status = "okay"; + clock-frequency = <400000>; + + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&sgtl5000_clk>; + #sound-dai-cells = <0>; + VDDA-supply = <&vdda_codec>; + VDDIO-supply = <&vcc3v3_baseboard>; + VDDD-supply = <&vddd_codec>; + }; +}; + +&i2c3 { + eeprom@50 { + reg = <0x50>; + compatible = "atmel,24c01"; + pagesize = <8>; + size = <128>; + vcc-supply = <&vcc3v3_baseboard>; + }; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&gmac { + status = "okay"; +}; + +&pinctrl { + haikou { + haikou_keys_pin: haikou-keys-pin { + rockchip,pins = + /* WAKE# */ + <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>, + /* SLP_BTN# */ + <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>, + /* LID_BTN */ + <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>, + /* BATLOW# */ + <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>, + /* BIOS_DISABLE# */ + <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + leds { + sd_card_led_pin: sd-card-led-pin { + rockchip,pins = + <3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm0 { + status = "okay"; +}; + +&sdmmc { + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_LOW>; + disable-wp; + vmmc-supply = <&vcc3v3_baseboard>; + status = "okay"; +}; + +&spi1 { + status = "okay"; +}; + +&u2phy_otg { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart5 { + pinctrl-0 = <&uart5_xfer>; + status = "okay"; +}; + +&usb20_otg { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi b/arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi new file mode 100644 index 000000000000..12397755830b --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi @@ -0,0 +1,382 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Theobroma Systems Design und Consulting GmbH + */ + +/dts-v1/; +#include "px30.dtsi" +#include <dt-bindings/leds/common.h> + +/ { + aliases { + mmc0 = &emmc; + mmc1 = &sdio; + rtc0 = &rtc_twi; + rtc1 = &rk809; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + pinctrl-0 = <&emmc_reset>; + pinctrl-names = "default"; + reset-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&module_led_pin>; + status = "okay"; + + module_led: led-0 { + gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; + function = LED_FUNCTION_HEARTBEAT; + linux,default-trigger = "heartbeat"; + color = <LED_COLOR_ID_AMBER>; + }; + }; + + vcc5v0_sys: vccsys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + supports-emmc; + mmc-pwrseq = <&emmc_pwrseq>; + non-removable; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_emmc>; + + status = "okay"; +}; + +/* On-module TI DP83825I PHY but no connector, enable in carrierboard */ +&gmac { + snps,reset-gpio = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 50000 50000>; + phy-supply = <&vcc_3v3>; + clock_in_out = "output"; +}; + +&gpio2 { + /* + * The Qseven BIOS_DISABLE signal on the PX30-µQ7 keeps the on-module + * eMMC powered-down initially (in fact it keeps the reset signal + * asserted). BIOS_DISABLE_OVERRIDE pin allows to re-enable eMMC after + * the SPL has been booted from SD Card. + */ + bios-disable-override-hog { + gpios = <RK_PB5 GPIO_ACTIVE_LOW>; + output-high; + line-name = "bios_disable_override"; + gpio-hog; + }; + + /* + * The BIOS_DISABLE hog is a feedback pin for the actual status of the + * signal, ignoring the BIOS_DISABLE_OVERRIDE logic. This usually + * represents the state of a switch on the baseboard. + */ + bios-disable-n-hog { + gpios = <RK_PC2 GPIO_ACTIVE_LOW>; + line-name = "bios_disable"; + input; + gpio-hog; + }; +}; + +&gpu { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pmic_int>; + pinctrl-names = "default"; + #clock-cells = <0>; + clock-output-names = "xin32k"; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc_3v3>; + vcc6-supply = <&vcc_3v3>; + vcc7-supply = <&vcc_3v3>; + vcc9-supply = <&vcc5v0_sys>; + + regulators { + vdd_log: DCDC_REG1 { + regulator-name = "vdd_log"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v0_1v8: vcc_emmc: DCDC_REG4 { + regulator-name = "vcc_3v0_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc_3v3: DCDC_REG5 { + regulator-name = "vcc_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_1v8: LDO_REG2 { + regulator-name = "vcc_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_1v0: LDO_REG3 { + regulator-name = "vcc_1v0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_lcd: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vcc_lcd"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_1v8_lcd: LDO_REG8 { + regulator-name = "vcc_1v8_lcd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca_1v8: LDO_REG9 { + regulator-name = "vcca_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + }; + }; +}; + +&i2c1 { + status = "okay"; + + /* SE05x is limited to Fast Mode */ + clock-frequency = <400000>; + + fan: fan@18 { + compatible = "ti,amc6821"; + reg = <0x18>; + #cooling-cells = <2>; + }; + + rtc_twi: rtc@6f { + compatible = "isil,isl1208"; + reg = <0x6f>; + }; +}; + +&i2c3 { + status = "okay"; +}; + +&i2s0_8ch { + rockchip,trcm-sync-tx-only; + + pinctrl-0 = <&i2s0_8ch_sclktx &i2s0_8ch_lrcktx + &i2s0_8ch_sdo0 &i2s0_8ch_sdi0>; +}; + +&io_domains { + vccio1-supply = <&vcc_3v3>; + vccio2-supply = <&vccio_sd>; + vccio3-supply = <&vcc_3v3>; + vccio4-supply = <&vcc_3v3>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_emmc>; + vccio-oscgpi-supply = <&vcc_3v3>; + + status = "okay"; +}; + +&pinctrl { + emmc { + emmc_reset: emmc-reset { + rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + module_led_pin: module-led-pin { + rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic-int { + rockchip,pins = + <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&saradc { + vref-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdmmc { + vqmmc-supply = <&vccio_sd>; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy { + status = "okay"; +}; + +&u2phy_host { + status = "okay"; +}; + +/* Mule UCAN */ +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&wdt { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi index 2dfa67f1cd67..dd228a256a32 100644 --- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi @@ -96,6 +96,7 @@ l2: l2-cache { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3326-anbernic-rg351m.dts b/arch/arm64/boot/dts/rockchip/rk3326-anbernic-rg351m.dts new file mode 100644 index 000000000000..61b31688b469 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3326-anbernic-rg351m.dts @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Hardkernel Co., Ltd + * Copyright (c) 2020 Theobroma Systems Design und Consulting GmbH + * Copyright (c) 2022 Maya Matuszczyk <maccraft123mc@gmail.com> + */ + +/dts-v1/; +#include "rk3326-odroid-go.dtsi" + +/ { + model = "Anbernic RG351M"; + compatible = "anbernic,rg351m", "rockchip,rk3326"; + + vibrator { + compatible = "pwm-vibrator"; + pwms = <&pwm0 0 1000000 0>; + pwm-names = "enable"; + }; +}; + +/delete-node/ &builtin_gamepad; +/delete-node/ &vcc_host; /* conflicts with pwm vibration motor */ + +&internal_display { + compatible = "elida,kd35t133"; +}; + +&pwm0 { + status = "okay"; +}; + +/delete-node/ &rk817_charger; diff --git a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go.dtsi b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go.dtsi new file mode 100644 index 000000000000..fbc6bfbaa5c1 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go.dtsi @@ -0,0 +1,600 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Hardkernel Co., Ltd + * Copyright (c) 2020 Theobroma Systems Design und Consulting GmbH + * Copyright (c) 2022 Maya Matuszczyk <maccraft123mc@gmail.com> + */ + +/dts-v1/; +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include "rk3326.dtsi" + +/ { + aliases { + mmc0 = &sdmmc; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + power-supply = <&vcc_bl>; + pwms = <&pwm1 0 25000 0>; + }; + + builtin_gamepad: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&btn_pins>; + + button-sw1 { + gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_LOW>; + label = "DPAD-UP"; + linux,code = <BTN_DPAD_UP>; + }; + button-sw2 { + gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_LOW>; + label = "DPAD-DOWN"; + linux,code = <BTN_DPAD_DOWN>; + }; + button-sw3 { + gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_LOW>; + label = "DPAD-LEFT"; + linux,code = <BTN_DPAD_LEFT>; + }; + button-sw4 { + gpios = <&gpio1 RK_PB7 GPIO_ACTIVE_LOW>; + label = "DPAD-RIGHT"; + linux,code = <BTN_DPAD_RIGHT>; + }; + button-sw5 { + gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_LOW>; + label = "BTN-A"; + linux,code = <BTN_EAST>; + }; + button-sw6 { + gpios = <&gpio1 RK_PA5 GPIO_ACTIVE_LOW>; + label = "BTN-B"; + linux,code = <BTN_SOUTH>; + }; + button-sw7 { + gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_LOW>; + label = "BTN-Y"; + linux,code = <BTN_WEST>; + }; + button-sw8 { + gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_LOW>; + label = "BTN-X"; + linux,code = <BTN_NORTH>; + }; + btn_f1: button-sw9 { + gpios = <&gpio2 RK_PA0 GPIO_ACTIVE_LOW>; + label = "F1"; + linux,code = <BTN_TRIGGER_HAPPY1>; + }; + btn_f2: button-sw10 { + gpios = <&gpio2 RK_PA1 GPIO_ACTIVE_LOW>; + label = "F2"; + linux,code = <BTN_TRIGGER_HAPPY2>; + }; + btn_f3: button-sw11 { + gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>; + label = "F3"; + linux,code = <BTN_TRIGGER_HAPPY3>; + }; + btn_f4: button-sw12 { + gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_LOW>; + label = "F4"; + linux,code = <BTN_TRIGGER_HAPPY4>; + }; + btn_f5: button-sw13 { + gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_LOW>; + label = "F5"; + linux,code = <BTN_TRIGGER_HAPPY5>; + }; + btn_f6: button-sw14 { + gpios = <&gpio2 RK_PA5 GPIO_ACTIVE_LOW>; + label = "F6"; + linux,code = <BTN_TRIGGER_HAPPY6>; + }; + button-sw15 { + gpios = <&gpio2 RK_PA6 GPIO_ACTIVE_LOW>; + label = "TOP-LEFT"; + linux,code = <BTN_TL>; + }; + button-sw16 { + gpios = <&gpio2 RK_PA7 GPIO_ACTIVE_LOW>; + label = "TOP-RIGHT"; + linux,code = <BTN_TR>; + }; + }; + + leds: gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&blue_led_pin>; + + blue_led: led-0 { + label = "blue:heartbeat"; + gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + rk817-sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "Analog"; + simple-audio-card,format = "i2s"; + simple-audio-card,hp-det-gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Headphone", "Headphones", + "Speaker", "Speaker"; + simple-audio-card,routing = + "MICL", "Mic Jack", + "Headphones", "HPOL", + "Headphones", "HPOR", + "Speaker", "SPKO"; + + simple-audio-card,codec { + sound-dai = <&rk817>; + }; + + simple-audio-card,cpu { + sound-dai = <&i2s1_2ch>; + }; + }; + + vccsys: vccsys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v8_sys"; + regulator-always-on; + regulator-min-microvolt = <3800000>; + regulator-max-microvolt = <3800000>; + }; + + vcc_host: vcc_host { + compatible = "regulator-fixed"; + regulator-name = "vcc_host"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + vin-supply = <&usb_midu>; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; + +&cru { + assigned-clocks = <&cru PLL_NPLL>, + <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, + <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>, + <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>, + <&cru PLL_CPLL>; + + assigned-clock-rates = <1188000000>, + <200000000>, <200000000>, + <150000000>, <150000000>, + <100000000>, <200000000>, + <17000000>; +}; + +&display_subsystem { + status = "okay"; +}; + +&dsi { + status = "okay"; + + ports { + mipi_out: port@1 { + reg = <1>; + + mipi_out_panel: endpoint { + remote-endpoint = <&mipi_in_panel>; + }; + }; + }; + + internal_display: panel@0 { + reg = <0>; + backlight = <&backlight>; + iovcc-supply = <&vcc_lcd>; + reset-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>; + rotation = <270>; + vdd-supply = <&vcc_lcd>; + + port { + mipi_in_panel: endpoint { + remote-endpoint = <&mipi_out_panel>; + }; + }; + }; +}; + +&dsi_dphy { + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_logic>; + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + i2c-scl-falling-time-ns = <16>; + i2c-scl-rising-time-ns = <280>; + status = "okay"; + + rk817: pmic@20 { + compatible = "rockchip,rk817"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>; + clock-output-names = "rk808-clkout1", "xin32k"; + clock-names = "mclk"; + clocks = <&cru SCLK_I2S1_OUT>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>, <&i2s1_2ch_mclk>; + wakeup-source; + #clock-cells = <1>; + #sound-dai-cells = <0>; + + vcc1-supply = <&vccsys>; + vcc2-supply = <&vccsys>; + vcc3-supply = <&vccsys>; + vcc4-supply = <&vccsys>; + vcc5-supply = <&vccsys>; + vcc6-supply = <&vccsys>; + vcc7-supply = <&vccsys>; + vcc8-supply = <&vccsys>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1150000>; + regulator-ramp-delay = <6001>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v3: DCDC_REG4 { + regulator-name = "vcc_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_1v8: LDO_REG2 { + regulator-name = "vcc_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_1v0: LDO_REG3 { + regulator-name = "vdd_1v0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc3v3_pmu: LDO_REG4 { + regulator-name = "vcc3v3_pmu"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_sd: LDO_REG6 { + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_bl: LDO_REG7 { + regulator-name = "vcc_bl"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_lcd: LDO_REG8 { + regulator-name = "vcc_lcd"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <2800000>; + }; + }; + + LDO_REG9 { + /* unused */ + }; + + usb_midu: BOOST { + regulator-name = "usb_midu"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5400000>; + regulator-always-on; + regulator-boot-on; + }; + }; + + rk817_charger: charger { + rockchip,resistor-sense-micro-ohms = <10000>; + rockchip,sleep-enter-current-microamp = <300000>; + rockchip,sleep-filter-current-microamp = <100000>; + }; + + rk817_codec: codec { + rockchip,mic-in-differential; + }; + }; +}; + +/* EXT Header(P2): 7(SCL:GPIO0.C2), 8(SDA:GPIO0.C3) */ +&i2c1 { + clock-frequency = <400000>; + status = "okay"; +}; + +/* I2S 1 Channel Used */ +&i2s1_2ch { + status = "okay"; +}; + +&io_domains { + vccio1-supply = <&vcc_3v3>; + vccio2-supply = <&vccio_sd>; + vccio3-supply = <&vcc_3v3>; + vccio4-supply = <&vcc_3v3>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_3v3>; + status = "okay"; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdmmc { + cap-sd-highspeed; + card-detect-delay = <200>; + cd-gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_LOW>; /*[> CD GPIO <]*/ + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + vmmc-supply = <&vcc_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&sfc { + pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus2>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <108000000>; + spi-rx-bus-width = <2>; + spi-tx-bus-width = <1>; + }; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy { + status = "okay"; + + u2phy_host: host-port { + status = "okay"; + }; + + u2phy_otg: otg-port { + status = "disabled"; + }; +}; + +&usb20_otg { + status = "okay"; +}; + +/* EXT Header(P2): 2(RXD:GPIO1.C0),3(TXD:.C1),4(CTS:.C2),5(RTS:.C3) */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer &uart1_cts>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2m1_xfer>; + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&pinctrl { + btns { + btn_pins: btn-pins { + rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>, + <2 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>, + <2 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>, + <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>, + <2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>, + <2 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>, + <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>, + <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>, + <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + leds { + blue_led_pin: blue-led-pin { + rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + dc_det: dc-det { + rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pmic_int: pmic-int { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + soc_slppin_gpio: soc_slppin_gpio { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>; + }; + + soc_slppin_rst: soc_slppin_rst { + rockchip,pins = <0 RK_PA4 2 &pcfg_pull_none>; + }; + + soc_slppin_slp: soc_slppin_slp { + rockchip,pins = <0 RK_PA4 1 &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2-v11.dts b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2-v11.dts new file mode 100644 index 000000000000..139c898e590e --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2-v11.dts @@ -0,0 +1,156 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Hardkernel Co., Ltd + * Copyright (c) 2020 Theobroma Systems Design und Consulting GmbH + * Copyright (c) 2022 Maya Matuszczyk <maccraft123mc@gmail.com> + */ + +/dts-v1/; +#include "rk3326-odroid-go.dtsi" + +/ { + model = "ODROID-GO Advance Black Edition"; + compatible = "hardkernel,rk3326-odroid-go2-v11", "rockchip,rk3326"; + + aliases { + mmc1 = &sdio; + }; + + analog_sticks: adc-joystick { + compatible = "adc-joystick"; + io-channels = <&saradc 1>, + <&saradc 2>; + poll-interval = <60>; + #address-cells = <1>; + #size-cells = <0>; + + axis@0 { + reg = <0>; + abs-flat = <10>; + abs-fuzz = <10>; + abs-range = <172 772>; + linux,code = <ABS_X>; + }; + + axis@1 { + reg = <1>; + abs-flat = <10>; + abs-fuzz = <10>; + abs-range = <278 815>; + linux,code = <ABS_Y>; + }; + }; + + battery: battery { + compatible = "simple-battery"; + charge-full-design-microamp-hours = <3000000>; + charge-term-current-microamp = <300000>; + constant-charge-current-max-microamp = <2000000>; + constant-charge-voltage-max-microvolt = <4200000>; + factory-internal-resistance-micro-ohms = <180000>; + voltage-max-design-microvolt = <4100000>; + voltage-min-design-microvolt = <3500000>; + + ocv-capacity-celsius = <20>; + ocv-capacity-table-0 = <4046950 100>, <4001920 95>, <3967900 90>, <3919950 85>, + <3888450 80>, <3861850 75>, <3831540 70>, <3799130 65>, + <3768190 60>, <3745650 55>, <3726610 50>, <3711630 45>, + <3696720 40>, <3685660 35>, <3674950 30>, <3663050 25>, + <3649470 20>, <3635260 15>, <3616920 10>, <3592440 5>, + <3574170 0>; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_pwrseq_pins>; + reset-gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_LOW>; + }; +}; + +&builtin_gamepad { + button-sw20 { + gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + label = "TOP-LEFT 2"; + linux,code = <BTN_TL2>; + }; + button-sw21 { + gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>; + label = "TOP-RIGHT 2"; + linux,code = <BTN_TR2>; + }; +}; + +&internal_display { + compatible = "elida,kd35t133"; +}; + +&rk817 { + regulators { + vcc_wifi: LDO_REG9 { + regulator-name = "vcc_wifi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + }; +}; + +&rk817_charger { + monitored-battery = <&battery>; +}; + +&sdio { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + disable-wp; + keep-power-in-suspend; + mmc-pwrseq = <&wifi_pwrseq>; + non-removable; + vmmc-supply = <&vcc_wifi>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + esp8089: wifi@1 { + compatible = "esp,esp8089"; + reg = <1>; + }; +}; + +&pinctrl { + btns { + btn_pins: btn-pins { + rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>, + <2 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>, + <2 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>, + <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>, + <2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>, + <2 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>, + <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>, + <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>, + <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + wifi { + wifi_pwrseq_pins: wifi-pwrseq-pins { + rockchip,pins = <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PB6 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts index 72899a714310..4702183b673c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts +++ b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts @@ -2,30 +2,21 @@ /* * Copyright (c) 2019 Hardkernel Co., Ltd * Copyright (c) 2020 Theobroma Systems Design und Consulting GmbH + * Copyright (c) 2022 Maya Matuszczyk <maccraft123mc@gmail.com> */ /dts-v1/; -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/pinctrl/rockchip.h> -#include "rk3326.dtsi" +#include "rk3326-odroid-go.dtsi" / { model = "ODROID-GO Advance"; compatible = "hardkernel,rk3326-odroid-go2", "rockchip,rk3326"; - aliases { - mmc0 = &sdmmc; - }; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - adc-joystick { + analog_sticks: adc-joystick { compatible = "adc-joystick"; io-channels = <&saradc 1>, <&saradc 2>; + poll-interval = <60>; #address-cells = <1>; #size-cells = <0>; @@ -46,12 +37,6 @@ }; }; - backlight: backlight { - compatible = "pwm-backlight"; - power-supply = <&vcc_bl>; - pwms = <&pwm1 0 25000 0>; - }; - battery: battery { compatible = "simple-battery"; charge-full-design-microamp-hours = <3000000>; @@ -63,606 +48,19 @@ voltage-min-design-microvolt = <3500000>; ocv-capacity-celsius = <20>; - ocv-capacity-table-0 = <4046950 100>, <4001920 95>, <3967900 90>, <3919950 85>, + ocv-capacity-table-0 = <4046950 100>, <4001920 95>, <3967900 90>, <3919950 85>, <3888450 80>, <3861850 75>, <3831540 70>, <3799130 65>, <3768190 60>, <3745650 55>, <3726610 50>, <3711630 45>, <3696720 40>, <3685660 35>, <3674950 30>, <3663050 25>, <3649470 20>, <3635260 15>, <3616920 10>, <3592440 5>, <3574170 0>; }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&btn_pins>; - - /* - * *** ODROIDGO2-Advance Switch layout *** - * |------------------------------------------------| - * | sw15 sw16 | - * |------------------------------------------------| - * | sw1 |-------------------| sw8 | - * | sw3 sw4 | | sw7 sw5 | - * | sw2 | LCD Display | sw6 | - * | | | | - * | |-------------------| | - * | sw9 sw10 sw11 sw12 sw13 sw14 | - * |------------------------------------------------| - */ - - button-sw1 { - gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_LOW>; - label = "DPAD-UP"; - linux,code = <BTN_DPAD_UP>; - }; - button-sw2 { - gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_LOW>; - label = "DPAD-DOWN"; - linux,code = <BTN_DPAD_DOWN>; - }; - button-sw3 { - gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_LOW>; - label = "DPAD-LEFT"; - linux,code = <BTN_DPAD_LEFT>; - }; - button-sw4 { - gpios = <&gpio1 RK_PB7 GPIO_ACTIVE_LOW>; - label = "DPAD-RIGHT"; - linux,code = <BTN_DPAD_RIGHT>; - }; - button-sw5 { - gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_LOW>; - label = "BTN-A"; - linux,code = <BTN_EAST>; - }; - button-sw6 { - gpios = <&gpio1 RK_PA5 GPIO_ACTIVE_LOW>; - label = "BTN-B"; - linux,code = <BTN_SOUTH>; - }; - button-sw7 { - gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_LOW>; - label = "BTN-Y"; - linux,code = <BTN_WEST>; - }; - button-sw8 { - gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_LOW>; - label = "BTN-X"; - linux,code = <BTN_NORTH>; - }; - button-sw9 { - gpios = <&gpio2 RK_PA0 GPIO_ACTIVE_LOW>; - label = "F1"; - linux,code = <BTN_TRIGGER_HAPPY1>; - }; - button-sw10 { - gpios = <&gpio2 RK_PA1 GPIO_ACTIVE_LOW>; - label = "F2"; - linux,code = <BTN_TRIGGER_HAPPY2>; - }; - button-sw11 { - gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>; - label = "F3"; - linux,code = <BTN_TRIGGER_HAPPY3>; - }; - button-sw12 { - gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_LOW>; - label = "F4"; - linux,code = <BTN_TRIGGER_HAPPY4>; - }; - button-sw13 { - gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_LOW>; - label = "F5"; - linux,code = <BTN_TRIGGER_HAPPY5>; - }; - button-sw14 { - gpios = <&gpio2 RK_PA5 GPIO_ACTIVE_LOW>; - label = "F6"; - linux,code = <BTN_TRIGGER_HAPPY6>; - }; - button-sw15 { - gpios = <&gpio2 RK_PA6 GPIO_ACTIVE_LOW>; - label = "TOP-LEFT"; - linux,code = <BTN_TL>; - }; - button-sw16 { - gpios = <&gpio2 RK_PA7 GPIO_ACTIVE_LOW>; - label = "TOP-RIGHT"; - linux,code = <BTN_TR>; - }; - }; - - leds: gpio-leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&blue_led_pin>; - - blue_led: led-0 { - label = "blue:heartbeat"; - gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - - rk817-sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "Analog"; - simple-audio-card,format = "i2s"; - simple-audio-card,hp-det-gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,widgets = - "Microphone", "Mic Jack", - "Headphone", "Headphones", - "Speaker", "Speaker"; - simple-audio-card,routing = - "MICL", "Mic Jack", - "Headphones", "HPOL", - "Headphones", "HPOR", - "Speaker", "SPKO"; - - simple-audio-card,codec { - sound-dai = <&rk817>; - }; - - simple-audio-card,cpu { - sound-dai = <&i2s1_2ch>; - }; - }; - - vccsys: vccsys { - compatible = "regulator-fixed"; - regulator-name = "vcc3v8_sys"; - regulator-always-on; - regulator-min-microvolt = <3800000>; - regulator-max-microvolt = <3800000>; - }; - - vcc_host: vcc_host { - compatible = "regulator-fixed"; - regulator-name = "vcc_host"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - vin-supply = <&usb_midu>; - }; -}; - -&cpu0 { - cpu-supply = <&vdd_arm>; -}; - -&cpu1 { - cpu-supply = <&vdd_arm>; -}; - -&cpu2 { - cpu-supply = <&vdd_arm>; -}; - -&cpu3 { - cpu-supply = <&vdd_arm>; -}; - -&cru { - assigned-clocks = <&cru PLL_NPLL>, - <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, - <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>, - <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>, - <&cru PLL_CPLL>; - - assigned-clock-rates = <1188000000>, - <200000000>, <200000000>, - <150000000>, <150000000>, - <100000000>, <200000000>, - <17000000>; }; -&display_subsystem { - status = "okay"; +&internal_display { + compatible = "elida,kd35t133"; }; -&dsi { - status = "okay"; - - ports { - mipi_out: port@1 { - reg = <1>; - - mipi_out_panel: endpoint { - remote-endpoint = <&mipi_in_panel>; - }; - }; - }; - - panel@0 { - compatible = "elida,kd35t133"; - reg = <0>; - backlight = <&backlight>; - iovcc-supply = <&vcc_lcd>; - reset-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>; - rotation = <270>; - vdd-supply = <&vcc_lcd>; - - port { - mipi_in_panel: endpoint { - remote-endpoint = <&mipi_out_panel>; - }; - }; - }; -}; - -&dsi_dphy { - status = "okay"; -}; - -&gpu { - mali-supply = <&vdd_logic>; - status = "okay"; -}; - -&i2c0 { - clock-frequency = <400000>; - i2c-scl-falling-time-ns = <16>; - i2c-scl-rising-time-ns = <280>; - status = "okay"; - - rk817: pmic@20 { - compatible = "rockchip,rk817"; - reg = <0x20>; - interrupt-parent = <&gpio0>; - interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>; - clock-output-names = "rk808-clkout1", "xin32k"; - clock-names = "mclk"; - clocks = <&cru SCLK_I2S1_OUT>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int>, <&i2s1_2ch_mclk>; - wakeup-source; - #clock-cells = <1>; - #sound-dai-cells = <0>; - - vcc1-supply = <&vccsys>; - vcc2-supply = <&vccsys>; - vcc3-supply = <&vccsys>; - vcc4-supply = <&vccsys>; - vcc5-supply = <&vccsys>; - vcc6-supply = <&vccsys>; - vcc7-supply = <&vccsys>; - vcc8-supply = <&vccsys>; - - regulators { - vdd_logic: DCDC_REG1 { - regulator-name = "vdd_logic"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1150000>; - regulator-ramp-delay = <6001>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <950000>; - }; - }; - - vdd_arm: DCDC_REG2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <950000>; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_3v3: DCDC_REG4 { - regulator-name = "vcc_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_1v8: LDO_REG2 { - regulator-name = "vcc_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd_1v0: LDO_REG3 { - regulator-name = "vdd_1v0"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc3v3_pmu: LDO_REG4 { - regulator-name = "vcc3v3_pmu"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vccio_sd: LDO_REG5 { - regulator-name = "vccio_sd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_sd: LDO_REG6 { - regulator-name = "vcc_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_bl: LDO_REG7 { - regulator-name = "vcc_bl"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_lcd: LDO_REG8 { - regulator-name = "vcc_lcd"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <2800000>; - }; - }; - - vcc_cam: LDO_REG9 { - regulator-name = "vcc_cam"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - - usb_midu: BOOST { - regulator-name = "usb_midu"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5400000>; - regulator-always-on; - regulator-boot-on; - }; - }; - - rk817_charger: charger { - monitored-battery = <&battery>; - rockchip,resistor-sense-micro-ohms = <10000>; - rockchip,sleep-enter-current-microamp = <300000>; - rockchip,sleep-filter-current-microamp = <100000>; - }; - - rk817_codec: codec { - rockchip,mic-in-differential; - }; - }; -}; - -/* EXT Header(P2): 7(SCL:GPIO0.C2), 8(SDA:GPIO0.C3) */ -&i2c1 { - clock-frequency = <400000>; - status = "okay"; -}; - -/* I2S 1 Channel Used */ -&i2s1_2ch { - status = "okay"; -}; - -&io_domains { - vccio1-supply = <&vcc_3v3>; - vccio2-supply = <&vccio_sd>; - vccio3-supply = <&vcc_3v3>; - vccio4-supply = <&vcc_3v3>; - vccio5-supply = <&vcc_3v3>; - vccio6-supply = <&vcc_3v3>; - status = "okay"; -}; - -&pmu_io_domains { - pmuio1-supply = <&vcc3v3_pmu>; - pmuio2-supply = <&vcc3v3_pmu>; - status = "okay"; -}; - -&pwm1 { - status = "okay"; -}; - -&saradc { - vref-supply = <&vcc_1v8>; - status = "okay"; -}; - -&sdmmc { - cap-sd-highspeed; - card-detect-delay = <200>; - cd-gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_LOW>; /*[> CD GPIO <]*/ - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; - vmmc-supply = <&vcc_sd>; - vqmmc-supply = <&vccio_sd>; - status = "okay"; -}; - -&sfc { - pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus2>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <108000000>; - spi-rx-bus-width = <2>; - spi-tx-bus-width = <1>; - }; -}; - -&tsadc { - status = "okay"; -}; - -&u2phy { - status = "okay"; - - u2phy_host: host-port { - status = "okay"; - }; - - u2phy_otg: otg-port { - status = "disabled"; - }; -}; - -&usb20_otg { - status = "okay"; -}; - -/* EXT Header(P2): 2(RXD:GPIO1.C0),3(TXD:.C1),4(CTS:.C2),5(RTS:.C3) */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_xfer &uart1_cts>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2m1_xfer>; - status = "okay"; -}; - -&vopb { - status = "okay"; -}; - -&vopb_mmu { - status = "okay"; -}; - -&pinctrl { - btns { - btn_pins: btn-pins { - rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>, - <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>, - <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>, - <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>, - <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>, - <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>, - <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>, - <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>, - <2 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>, - <2 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>, - <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>, - <2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>, - <2 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>, - <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>, - <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>, - <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - headphone { - hp_det: hp-det { - rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_down>; - }; - }; - - leds { - blue_led_pin: blue-led-pin { - rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - - pmic { - dc_det: dc-det { - rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - pmic_int: pmic-int { - rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - soc_slppin_gpio: soc_slppin_gpio { - rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>; - }; - - soc_slppin_rst: soc_slppin_rst { - rockchip,pins = <0 RK_PA4 2 &pcfg_pull_none>; - }; - - soc_slppin_slp: soc_slppin_slp { - rockchip,pins = <0 RK_PA4 1 &pcfg_pull_none>; - }; - }; +&rk817_charger { + monitored-battery = <&battery>; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go3.dts b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go3.dts new file mode 100644 index 000000000000..842efbaf1a6a --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go3.dts @@ -0,0 +1,185 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Hardkernel Co., Ltd + * Copyright (c) 2020 Theobroma Systems Design und Consulting GmbH + * Copyright (c) 2022 Maya Matuszczyk <maccraft123mc@gmail.com> + */ + +/dts-v1/; +#include "rk3326-odroid-go.dtsi" + +/ { + model = "ODROID-GO Super"; + compatible = "hardkernel,rk3326-odroid-go3", "rockchip,rk3326"; + + joystick_mux_controller: mux-controller { + compatible = "gpio-mux"; + pinctrl = <&mux_en_pins>; + #mux-control-cells = <0>; + + mux-gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_LOW>, + <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; + }; + + joystick_mux: adc-mux { + compatible = "io-channel-mux"; + io-channels = <&saradc 1>; + io-channel-names = "parent"; + #io-channel-cells = <1>; + + mux-controls = <&joystick_mux_controller>; + channels = "0", "1", "2", "3"; + }; + + analog_sticks: adc-joystick { + compatible = "adc-joystick"; + io-channels = <&joystick_mux 0>, + <&joystick_mux 1>, + <&joystick_mux 2>, + <&joystick_mux 3>; + poll-interval = <60>; + #address-cells = <1>; + #size-cells = <0>; + + axis@0 { + reg = <0>; + abs-flat = <10>; + abs-fuzz = <10>; + abs-range = <180 800>; + linux,code = <ABS_X>; + }; + + axis@1 { + reg = <1>; + abs-flat = <10>; + abs-fuzz = <10>; + abs-range = <180 800>; + linux,code = <ABS_RX>; + }; + + axis@2 { + reg = <2>; + abs-flat = <10>; + abs-fuzz = <10>; + abs-range = <180 800>; + linux,code = <ABS_Y>; + }; + + axis@3 { + reg = <3>; + abs-flat = <10>; + abs-fuzz = <10>; + abs-range = <180 800>; + linux,code = <ABS_RY>; + }; + }; + + battery: battery { + compatible = "simple-battery"; + charge-full-design-microamp-hours = <4000000>; + charge-term-current-microamp = <300000>; + constant-charge-current-max-microamp = <2000000>; + constant-charge-voltage-max-microvolt = <4200000>; + factory-internal-resistance-micro-ohms = <180000>; + voltage-max-design-microvolt = <4100000>; + voltage-min-design-microvolt = <3500000>; + + ocv-capacity-celsius = <20>; + ocv-capacity-table-0 = <4046950 100>, <4001920 95>, <3967900 90>, <3919950 85>, + <3888450 80>, <3861850 75>, <3831540 70>, <3799130 65>, + <3768190 60>, <3745650 55>, <3726610 50>, <3711630 45>, + <3696720 40>, <3685660 35>, <3674950 30>, <3663050 25>, + <3649470 20>, <3635260 15>, <3616920 10>, <3592440 5>, + <3574170 0>; + }; + + gpio-keys-vol { + compatible = "gpio-keys"; + autorepeat; + pinctrl-0 = <&btn_pins_vol>; + pinctrl-names = "default"; + + button-vol-down { + gpios = <&gpio2 RK_PA1 GPIO_ACTIVE_LOW>; + label = "VOLUMEDOWN"; + linux,code = <KEY_VOLUMEDOWN>; + }; + + button-volume-up { + gpios = <&gpio2 RK_PA0 GPIO_ACTIVE_LOW>; + label = "VOLUMEUP"; + linux,code = <KEY_VOLUMEUP>; + }; + }; +}; + +/* f1 and f2 conflict with volume buttons */ +/delete-node/ &btn_f1; +/delete-node/ &btn_f2; + +&builtin_gamepad { + button-sw19 { + gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_LOW>; + label = "SELECT"; + linux,code = <BTN_SELECT>; + }; + /* note that TR2 and TL2 are swapped */ + button-sw20 { + gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + label = "TOP-RIGHT 2"; + linux,code = <BTN_TR2>; + }; + button-sw21 { + gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>; + label = "TOP-LEFT 2"; + linux,code = <BTN_TL2>; + }; + button-sw22 { + gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_LOW>; + label = "START"; + linux,code = <BTN_START>; + }; +}; + +&internal_display { + status = "disabled"; +}; + +&rk817_charger { + monitored-battery = <&battery>; +}; + +&pinctrl { + btns { + btn_pins: btn-pins { + rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>, + <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>, + <2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>, + <2 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>, + <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>, + <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>, + <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + btn_pins_vol: btn-pins-vol { + rockchip,pins = <2 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>, + <2 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + joystick { + mux_en_pins: mux-pins { + rockchip,pins = <3 RK_PB5 RK_FUNC_GPIO &pcfg_output_low>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi index 49ae15708a0b..6d7a7bf72ac7 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi @@ -102,6 +102,7 @@ l2: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; }; @@ -1025,6 +1026,17 @@ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; + crypto: crypto@ff060000 { + compatible = "rockchip,rk3328-crypto"; + reg = <0x0 0xff060000 0x0 0x4000>; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_CRYPTO_MST>, <&cru HCLK_CRYPTO_SLV>, + <&cru SCLK_CRYPTO>; + clock-names = "hclk_master", "hclk_slave", "sclk"; + resets = <&cru SRST_CRYPTO>; + reset-names = "crypto-rst"; + }; + pinctrl: pinctrl { compatible = "rockchip,rk3328-pinctrl"; rockchip,grf = <&grf>; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts index 2e058c315025..04403a76238b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts @@ -81,6 +81,27 @@ regulator-max-microvolt = <1800000>; vin-supply = <&vcc3v3_sys>; }; + + wifi_pwrseq: sdio-wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk818 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h_pin>; + /* + * Wait between power-on and SDIO access for CYP43455 + * POR circuit. + */ + post-power-on-delay-ms = <110>; + /* + * Wait between consecutive toggles for CYP43455 CBUCK + * regulator discharge. + */ + power-off-delay-us = <10000>; + + /* WL_REG_ON on module */ + reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; + }; }; &cpu_l0 { @@ -360,11 +381,45 @@ }; }; + sdio-pwrseq { + wifi_enable_h_pin: wifi-enable-h-pin { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + sound { vcc1v8_codec_en: vcc1v8-codec-en { rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>; }; }; + + wireless-bluetooth { + bt_wake_pin: bt-wake-pin { + rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_host_wake_pin: bt-host-wake-pin { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_reset_pin: bt-reset-pin { + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdio0 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + disable-wp; + keep-power-in-suspend; + mmc-pwrseq = <&wifi_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + sd-uhs-sdr104; + status = "okay"; }; &sdmmc { @@ -393,6 +448,27 @@ status = "okay"; }; +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm4345c5"; + clocks = <&rk818 1>; + clock-names = "lpo"; + device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; + max-speed = <1500000>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_pin &bt_wake_pin &bt_reset_pin>; + shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; + vbat-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_1v8>; + }; +}; + &uart2 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts index f9884902f874..309c35d7fca8 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts @@ -601,6 +601,12 @@ status = "okay"; }; +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <1>; + status = "okay"; +}; + &u2phy0 { status = "okay"; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi index 94e39ed63397..c920ddf44baf 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi @@ -128,6 +128,8 @@ }; &hdmi { + avdd-0v9-supply = <&vcca0v9_hdmi>; + avdd-1v8-supply = <&vcca1v8_hdmi>; ddc-i2c-bus = <&i2c3>; pinctrl-names = "default"; pinctrl-0 = <&hdmi_cec>; diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 92c2207e686c..4391aea25984 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -582,6 +582,26 @@ status = "disabled"; }; + crypto0: crypto@ff8b0000 { + compatible = "rockchip,rk3399-crypto"; + reg = <0x0 0xff8b0000 0x0 0x4000>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru HCLK_M_CRYPTO0>, <&cru HCLK_S_CRYPTO0>, <&cru SCLK_CRYPTO0>; + clock-names = "hclk_master", "hclk_slave", "sclk"; + resets = <&cru SRST_CRYPTO0>, <&cru SRST_CRYPTO0_S>, <&cru SRST_CRYPTO0_M>; + reset-names = "master", "lave", "crypto"; + }; + + crypto1: crypto@ff8b8000 { + compatible = "rockchip,rk3399-crypto"; + reg = <0x0 0xff8b8000 0x0 0x4000>; + interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru HCLK_M_CRYPTO1>, <&cru HCLK_S_CRYPTO1>, <&cru SCLK_CRYPTO1>; + clock-names = "hclk_master", "hclk_slave", "sclk"; + resets = <&cru SRST_CRYPTO1>, <&cru SRST_CRYPTO1_S>, <&cru SRST_CRYPTO1_M>; + reset-names = "master", "slave", "crypto"; + }; + i2c1: i2c@ff110000 { compatible = "rockchip,rk3399-i2c"; reg = <0x0 0xff110000 0x0 0x1000>; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353p.dts b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353p.dts index 7a20e2d6876a..63cff402f3a8 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353p.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353p.dts @@ -5,7 +5,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/linux-event-codes.h> #include <dt-bindings/pinctrl/rockchip.h> -#include "rk3566-anbernic-rgxx3.dtsi" +#include "rk3566-anbernic-rg353x.dtsi" / { model = "RG353P"; @@ -18,26 +18,66 @@ mmc3 = &sdmmc2; }; - backlight: backlight { - compatible = "pwm-backlight"; - power-supply = <&vcc_sys>; - pwms = <&pwm4 0 25000 0>; + battery: battery { + compatible = "simple-battery"; + charge-full-design-microamp-hours = <3472000>; + charge-term-current-microamp = <300000>; + constant-charge-current-max-microamp = <2000000>; + constant-charge-voltage-max-microvolt = <4200000>; + factory-internal-resistance-micro-ohms = <117000>; + voltage-max-design-microvolt = <4172000>; + voltage-min-design-microvolt = <3400000>; + + ocv-capacity-celsius = <20>; + ocv-capacity-table-0 = <4172000 100>, <4054000 95>, <3984000 90>, <3926000 85>, + <3874000 80>, <3826000 75>, <3783000 70>, <3746000 65>, + <3714000 60>, <3683000 55>, <3650000 50>, <3628000 45>, + <3612000 40>, <3600000 35>, <3587000 30>, <3571000 25>, + <3552000 20>, <3525000 15>, <3492000 10>, <3446000 5>, + <3400000 0>; }; -}; -&gpio_keys_control { - button-a { - gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>; - label = "EAST"; - linux,code = <BTN_EAST>; + /* Channels reversed for both headphones and speakers. */ + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "rk817_ext"; + simple-audio-card,aux-devs = <&spk_amp>; + simple-audio-card,format = "i2s"; + simple-audio-card,hp-det-gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Headphone", "Headphones", + "Speaker", "Internal Speakers"; + simple-audio-card,routing = + "MICL", "Mic Jack", + "Headphones", "HPOL", + "Headphones", "HPOR", + "Internal Speakers", "Speaker Amp OUTL", + "Internal Speakers", "Speaker Amp OUTR", + "Speaker Amp INL", "HPOL", + "Speaker Amp INR", "HPOR"; + simple-audio-card,pin-switches = "Internal Speakers"; + + simple-audio-card,codec { + sound-dai = <&rk817>; + }; + + simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; }; - button-left { - gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>; - label = "DPAD-LEFT"; - linux,code = <BTN_DPAD_LEFT>; + spk_amp: audio-amplifier { + compatible = "simple-audio-amplifier"; + enable-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&spk_amp_enable_h>; + pinctrl-names = "default"; + sound-name-prefix = "Speaker Amp"; }; +}; +&gpio_keys_control { button-r1 { gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_LOW>; label = "TR"; @@ -49,27 +89,6 @@ label = "TR2"; linux,code = <BTN_TR2>; }; - - button-right { - gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_LOW>; - label = "DPAD-RIGHT"; - linux,code = <BTN_DPAD_RIGHT>; - }; - - button-y { - gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_LOW>; - label = "WEST"; - linux,code = <BTN_WEST>; - }; -}; - -&i2c0 { - /* This hardware is physically present but unused. */ - power-monitor@62 { - compatible = "cellwise,cw2015"; - reg = <0x62>; - status = "disabled"; - }; }; &i2c2 { @@ -78,8 +97,22 @@ status = "okay"; }; -&pwm4 { - status = "okay"; +&pinctrl { + audio-amplifier { + spk_amp_enable_h: spk-amp-enable-h { + rockchip,pins = + <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&rk817 { + rk817_charger: charger { + monitored-battery = <&battery>; + rockchip,resistor-sense-micro-ohms = <10000>; + rockchip,sleep-enter-current-microamp = <300000>; + rockchip,sleep-filter-current-microamp = <100000>; + }; }; &sdhci { diff --git a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353v.dts b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353v.dts new file mode 100644 index 000000000000..885234a023e1 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353v.dts @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/linux-event-codes.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include "rk3566-anbernic-rg353x.dtsi" + +/ { + model = "RG353V"; + compatible = "anbernic,rg353v", "rockchip,rk3566"; + + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc0; + mmc2 = &sdmmc1; + mmc3 = &sdmmc2; + }; + + battery: battery { + compatible = "simple-battery"; + charge-full-design-microamp-hours = <3151000>; + charge-term-current-microamp = <300000>; + constant-charge-current-max-microamp = <2000000>; + constant-charge-voltage-max-microvolt = <4200000>; + factory-internal-resistance-micro-ohms = <117000>; + voltage-max-design-microvolt = <4172000>; + voltage-min-design-microvolt = <3400000>; + + ocv-capacity-celsius = <20>; + ocv-capacity-table-0 = <4172000 100>, <4054000 95>, <3984000 90>, <3926000 85>, + <3874000 80>, <3826000 75>, <3783000 70>, <3746000 65>, + <3714000 60>, <3683000 55>, <3650000 50>, <3628000 45>, + <3612000 40>, <3600000 35>, <3587000 30>, <3571000 25>, + <3552000 20>, <3525000 15>, <3492000 10>, <3446000 5>, + <3400000 0>; + }; + + /* Channels reversed for headphones. */ + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "rk817_int"; + simple-audio-card,format = "i2s"; + simple-audio-card,hp-det-gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Headphone", "Headphones", + "Speaker", "Internal Speakers"; + simple-audio-card,routing = + "MICL", "Mic Jack", + "Headphones", "HPOL", + "Headphones", "HPOR", + "Internal Speakers", "SPKO"; + + simple-audio-card,codec { + sound-dai = <&rk817>; + }; + + simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; + }; +}; + +&gpio_keys_control { + button-r1 { + gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_LOW>; + label = "TR"; + linux,code = <BTN_TR>; + }; + + button-r2 { + gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_LOW>; + label = "TR2"; + linux,code = <BTN_TR2>; + }; +}; + +&i2c2 { + pintctrl-names = "default"; + pinctrl-0 = <&i2c2m1_xfer>; + status = "okay"; +}; + +&pinctrl { + touch { + touch_rst: touch-rst { + rockchip,pins = + <4 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&rk817 { + rk817_charger: charger { + monitored-battery = <&battery>; + rockchip,resistor-sense-micro-ohms = <10000>; + rockchip,sleep-enter-current-microamp = <300000>; + rockchip,sleep-filter-current-microamp = <100000>; + }; +}; + +&sdhci { + pinctrl-0 = <&emmc_bus8>, <&emmc_clk>, <&emmc_cmd>, <&emmc_datastrobe>, <&emmc_rstnout>; + pinctrl-names = "default"; + bus-width = <8>; + mmc-hs200-1_8v; + non-removable; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353vs.dts b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353vs.dts new file mode 100644 index 000000000000..a7dc462fe21f --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353vs.dts @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/linux-event-codes.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include "rk3566-anbernic-rg353x.dtsi" + +/ { + model = "RG353VS"; + compatible = "anbernic,rg353vs", "rockchip,rk3566"; + + aliases { + mmc0 = &sdmmc0; + mmc1 = &sdmmc1; + mmc2 = &sdmmc2; + }; + + battery: battery { + compatible = "simple-battery"; + charge-full-design-microamp-hours = <3151000>; + charge-term-current-microamp = <300000>; + constant-charge-current-max-microamp = <2000000>; + constant-charge-voltage-max-microvolt = <4200000>; + factory-internal-resistance-micro-ohms = <117000>; + voltage-max-design-microvolt = <4172000>; + voltage-min-design-microvolt = <3400000>; + + ocv-capacity-celsius = <20>; + ocv-capacity-table-0 = <4172000 100>, <4054000 95>, <3984000 90>, <3926000 85>, + <3874000 80>, <3826000 75>, <3783000 70>, <3746000 65>, + <3714000 60>, <3683000 55>, <3650000 50>, <3628000 45>, + <3612000 40>, <3600000 35>, <3587000 30>, <3571000 25>, + <3552000 20>, <3525000 15>, <3492000 10>, <3446000 5>, + <3400000 0>; + }; + + /* Channels reversed for headphones. */ + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "rk817_int"; + simple-audio-card,format = "i2s"; + simple-audio-card,hp-det-gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Headphone", "Headphones", + "Speaker", "Internal Speakers"; + simple-audio-card,routing = + "MICL", "Mic Jack", + "Headphones", "HPOL", + "Headphones", "HPOR", + "Internal Speakers", "SPKO"; + + simple-audio-card,codec { + sound-dai = <&rk817>; + }; + + simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; + }; +}; + +&gpio_keys_control { + button-r1 { + gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_LOW>; + label = "TR"; + linux,code = <BTN_TR>; + }; + + button-r2 { + gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_LOW>; + label = "TR2"; + linux,code = <BTN_TR2>; + }; +}; + +&rk817 { + rk817_charger: charger { + monitored-battery = <&battery>; + rockchip,resistor-sense-micro-ohms = <10000>; + rockchip,sleep-enter-current-microamp = <300000>; + rockchip,sleep-filter-current-microamp = <100000>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353x.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353x.dtsi new file mode 100644 index 000000000000..65a80d1f6d91 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353x.dtsi @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/linux-event-codes.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include "rk3566-anbernic-rgxx3.dtsi" + +/ { + backlight: backlight { + compatible = "pwm-backlight"; + power-supply = <&vcc_sys>; + pwms = <&pwm4 0 25000 0>; + }; +}; + +&cru { + assigned-clocks = <&cru PLL_GPLL>, <&pmucru PLL_PPLL>, <&cru PLL_VPLL>; + assigned-clock-rates = <1200000000>, <200000000>, <241500000>; +}; + +&gpio_keys_control { + button-a { + gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>; + label = "EAST"; + linux,code = <BTN_EAST>; + }; + + button-left { + gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>; + label = "DPAD-LEFT"; + linux,code = <BTN_DPAD_LEFT>; + }; + + button-right { + gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_LOW>; + label = "DPAD-RIGHT"; + linux,code = <BTN_DPAD_RIGHT>; + }; + + button-y { + gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_LOW>; + label = "WEST"; + linux,code = <BTN_WEST>; + }; +}; + +&i2c0 { + /* This hardware is physically present but unused. */ + power-monitor@62 { + compatible = "cellwise,cw2015"; + reg = <0x62>; + status = "disabled"; + }; +}; + +&pwm4 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg503.dts b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg503.dts index 3dc01549a5b4..5dafcc86296b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg503.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg503.dts @@ -17,6 +17,25 @@ mmc2 = &sdmmc2; }; + battery: battery { + compatible = "simple-battery"; + charge-full-design-microamp-hours = <3472000>; + charge-term-current-microamp = <300000>; + constant-charge-current-max-microamp = <2000000>; + constant-charge-voltage-max-microvolt = <4200000>; + factory-internal-resistance-micro-ohms = <117000>; + voltage-max-design-microvolt = <4172000>; + voltage-min-design-microvolt = <3400000>; + + ocv-capacity-celsius = <20>; + ocv-capacity-table-0 = <4172000 100>, <4054000 95>, <3984000 90>, <3926000 85>, + <3874000 80>, <3826000 75>, <3783000 70>, <3746000 65>, + <3714000 60>, <3683000 55>, <3650000 50>, <3628000 45>, + <3612000 40>, <3600000 35>, <3587000 30>, <3571000 25>, + <3552000 20>, <3525000 15>, <3492000 10>, <3446000 5>, + <3400000 0>; + }; + gpio_spi: spi { compatible = "spi-gpio"; pinctrl-names = "default"; @@ -29,6 +48,50 @@ cs-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; num-chipselects = <0>; }; + + /* Channels reversed for both headphones and speakers. */ + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "rk817_ext"; + simple-audio-card,aux-devs = <&spk_amp>; + simple-audio-card,format = "i2s"; + simple-audio-card,hp-det-gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Headphone", "Headphones", + "Speaker", "Internal Speakers"; + simple-audio-card,routing = + "MICL", "Mic Jack", + "Headphones", "HPOL", + "Headphones", "HPOR", + "Internal Speakers", "Speaker Amp OUTL", + "Internal Speakers", "Speaker Amp OUTR", + "Speaker Amp INL", "HPOL", + "Speaker Amp INR", "HPOR"; + simple-audio-card,pin-switches = "Internal Speakers"; + + simple-audio-card,codec { + sound-dai = <&rk817>; + }; + + simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; + }; + + spk_amp: audio-amplifier { + compatible = "simple-audio-amplifier"; + enable-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&spk_amp_enable_h>; + pinctrl-names = "default"; + sound-name-prefix = "Speaker Amp"; + }; +}; + +&cru { + assigned-clocks = <&cru PLL_GPLL>, <&pmucru PLL_PPLL>, <&cru PLL_VPLL>; + assigned-clock-rates = <1200000000>, <200000000>, <500000000>; }; &gpio_keys_control { @@ -76,6 +139,13 @@ }; &pinctrl { + audio-amplifier { + spk_amp_enable_h: spk-amp-enable-h { + rockchip,pins = + <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + gpio-spi { spi_pins: spi-pins { rockchip,pins = @@ -85,3 +155,12 @@ }; }; }; + +&rk817 { + rk817_charger: charger { + monitored-battery = <&battery>; + rockchip,resistor-sense-micro-ohms = <10000>; + rockchip,sleep-enter-current-microamp = <300000>; + rockchip,sleep-filter-current-microamp = <100000>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rgxx3.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rgxx3.dtsi index 2b455143b86d..41262a69d33e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rgxx3.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rgxx3.dtsi @@ -22,6 +22,7 @@ <&adc_mux 3>; pinctrl-0 = <&joy_mux_en>; pinctrl-names = "default"; + poll-interval = <60>; #address-cells = <1>; #size-cells = <0>; @@ -217,37 +218,6 @@ }; }; - /* Channels reversed for both headphones and speakers. */ - sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "anbernic_rk817"; - simple-audio-card,aux-devs = <&spk_amp>; - simple-audio-card,format = "i2s"; - simple-audio-card,hp-det-gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,widgets = - "Microphone", "Mic Jack", - "Headphone", "Headphones", - "Speaker", "Internal Speakers"; - simple-audio-card,routing = - "MICL", "Mic Jack", - "Headphones", "HPOL", - "Headphones", "HPOR", - "Internal Speakers", "Speaker Amp OUTL", - "Internal Speakers", "Speaker Amp OUTR", - "Speaker Amp INL", "HPOL", - "Speaker Amp INR", "HPOR"; - simple-audio-card,pin-switches = "Internal Speakers"; - - simple-audio-card,codec { - sound-dai = <&rk817>; - }; - - simple-audio-card,cpu { - sound-dai = <&i2s1_8ch>; - }; - }; - sdio_pwrseq: sdio-pwrseq { compatible = "mmc-pwrseq-simple"; clocks = <&rk817 1>; @@ -258,14 +228,6 @@ reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_LOW>; }; - spk_amp: audio-amplifier { - compatible = "simple-audio-amplifier"; - enable-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&spk_amp_enable_h>; - pinctrl-names = "default"; - sound-name-prefix = "Speaker Amp"; - }; - vcc3v3_lcd0_n: regulator-vcc3v3-lcd0 { compatible = "regulator-fixed"; gpio = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>; @@ -607,13 +569,6 @@ }; &pinctrl { - audio-amplifier { - spk_amp_enable_h: spk-amp-enable-h { - rockchip,pins = - <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - gpio-btns { btn_pins_ctrl: btn-pins-ctrl { rockchip,pins = diff --git a/arch/arm64/boot/dts/rockchip/rk3566-box-demo.dts b/arch/arm64/boot/dts/rockchip/rk3566-box-demo.dts new file mode 100644 index 000000000000..4c7f9abd594f --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-box-demo.dts @@ -0,0 +1,503 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/* + * Author: Piotr Oniszczuk piotr.oniszczuk@gmail.com + * Based on Quartz64 DT by: Peter Geis pgwipeout@gmail.com + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/soc/rockchip,vop2.h> +#include "rk3566.dtsi" + +/ { + model = "Rockchip RK3566 BOX DEMO Board"; + compatible = "rockchip,rk3566-box-demo", "rockchip,rk3566"; + + aliases { + ethernet0 = &gmac1; + mmc0 = &sdmmc0; + mmc1 = &sdmmc1; + mmc2 = &sdhci; + }; + + chosen: chosen { + stdout-path = "serial2:1500000n8"; + }; + + gmac1_clkin: external-gmac1-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac1_clkin"; + #clock-cells = <0>; + }; + + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio4 RK_PC3 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&ir_int>; + linux,rc-map-name = "rc-beelink-gs1"; + status = "okay"; + }; + + leds { + compatible = "gpio-leds"; + + led_work: led-0 { + gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>; + function = LED_FUNCTION_HEARTBEAT; + color = <LED_COLOR_ID_BLUE>; + linux,default-trigger = "heartbeat"; + pinctrl-names = "default"; + pinctrl-0 = <&led_work_en>; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + status = "okay"; + compatible = "mmc-pwrseq-simple"; + clocks = <&pmucru CLK_RTC_32K>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h &wifi_32k>; + reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; + }; + + spdif_dit: spdif-dit { + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + spdif_sound: spdif-sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "SPDIF"; + + simple-audio-card,cpu { + sound-dai = <&spdif>; + }; + + simple-audio-card,codec { + sound-dai = <&spdif_dit>; + }; + }; + + vcc12v0_dcin: regulator-vcc12v0-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v0_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: regulator-vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v0_dcin>; + }; + + vcc3v3_sys: regulator-vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc12v0_dcin>; + }; + + vcc_3v3: regulator-vcc-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc5v0_usb_host: regulator-vcc5v0-usb-host { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb_host_en>; + regulator-name = "vcc5v0_usb_host"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_usb2_otg: regulator-vcc5v0-usb2-otg { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb2_otg_en>; + regulator-name = "vcc5v0_usb_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcca_1v8: regulator-vcca-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_sys>; + }; + + vdda_0v9: regulator-vdda-0v9 { + compatible = "regulator-fixed"; + regulator-name = "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc3v3_sys>; + }; + + vdd_fixed: regulator-vdd-fixed { + compatible = "regulator-fixed"; + regulator-name = "vdd_fixed"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + }; + + vdd_cpu: regulator-vdd-cpu { + compatible = "pwm-regulator"; + pwms = <&pwm0 0 5000 1>; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + regulator-settling-time-up-us = <250>; + pwm-supply = <&vcc5v0_sys>; + }; + + vdd_logic: regulator-vdd-logic { + compatible = "pwm-regulator"; + pwms = <&pwm1 0 5000 1>; + regulator-name = "vdd_logic"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + regulator-settling-time-up-us = <250>; + pwm-supply = <&vcc5v0_sys>; + }; +}; + +&combphy1 { + status = "okay"; +}; + +&combphy2 { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&gmac1 { + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>; + phy-mode = "rgmii"; + clock_in_out = "input"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_rgmii_bus + &gmac1m1_clkinout>; + snps,reset-gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + tx_delay = <0x4f>; + rx_delay = <0x2d>; + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&hdmi { + assigned-clocks = <&cru CLK_HDMI_CEC>; + assigned-clock-rates = <32768>; + avdd-0v9-supply = <&vdda_0v9>; + avdd-1v8-supply = <&vcca_1v8>; + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status = "okay"; +}; + +&gpu { + status = "okay"; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&i2s1_8ch { + rockchip,trcm-sync-tx-only; + status = "okay"; +}; + +&pinctrl { + bt { + bt_enable_h: bt-enable-h { + rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_host_wake_l: bt-host-wake-l { + rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + bt_wake_l: bt-wake-l { + rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_32k: wifi-32k { + rockchip,pins = <0 RK_PB0 2 &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_usb_host_en: vcc5v0_usb_host_en { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_usb2_otg_en: vcc5v0_usb2_otg_en { + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + }; + + ir { + ir_int: ir-int { + rockchip,pins = <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + led { + led_work_en: led_work_en { + rockchip,pins = <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs200-1_8v; + non-removable; + status = "okay"; +}; + +&sdmmc0 { + bus-width = <4>; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + vmmc-supply = <&vcc_3v3>; + status = "okay"; +}; + +&sdmmc1 { + bus-width = <4>; + cap-sd-highspeed; + disable-wp; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcca_1v8>; + status = "okay"; +}; + +&spdif { + status = "okay"; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1m1_cs0 &spi1m1_pins>; +}; + +&tsadc { + /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-mode = <1>; + /* tshut polarity 0:LOW 1:HIGH */ + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>; + status = "okay"; + uart-has-rtscts; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&pmucru CLK_RTC_32K>; + clock-names = "ext_clock"; + device-wake-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + host-wake-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; + vbat-supply = <&vcc3v3_sys>; + vddio-supply = <&vcca_1v8>; + }; +}; + +&uart2 { + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = <ROCKCHIP_VOP2_EP_HDMI0>; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; + +&vpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&usb2phy0_host { + phy-supply = <&vcc5v0_usb_host>; + status = "okay"; +}; + +&usb2phy0_otg { + vbus-supply = <&vcc5v0_usb2_otg>; + status = "okay"; +}; + +&usb2phy1_host { + phy-supply = <&vcc5v0_usb_host>; + status = "okay"; +}; + +&usb2phy1_otg { + phy-supply = <&vcc5v0_usb_host>; + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host1_xhci { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts b/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts index dba648c2f57e..ab177c4f9284 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts @@ -82,6 +82,18 @@ vin-supply = <&usb_5v>; }; + vcc3v3_pcie: vcc3v3-pcie-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_enable_h>; + regulator-name = "vcc3v3_pcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + vcc3v3_sys: vcc3v3-sys-regulator { compatible = "regulator-fixed"; regulator-name = "vcc3v3_sys"; @@ -122,6 +134,10 @@ status = "okay"; }; +&combphy2 { + status = "okay"; +}; + &cpu0 { cpu-supply = <&vdd_cpu>; }; @@ -447,6 +463,14 @@ }; }; +&pcie2x1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_reset_h>; + reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + &pinctrl { bt { bt_enable_h: bt-enable-h { @@ -468,6 +492,16 @@ }; }; + pcie { + pcie_enable_h: pcie-enable-h { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie_reset_h: pcie-reset-h { + rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + pmic { pmic_int: pmic_int { rockchip,pins = diff --git a/arch/arm64/boot/dts/rockchip/rk3566-soquartz-blade.dts b/arch/arm64/boot/dts/rockchip/rk3566-soquartz-blade.dts new file mode 100644 index 000000000000..4e49bebf548b --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-soquartz-blade.dts @@ -0,0 +1,194 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/rockchip.h> + +#include "rk3566-soquartz.dtsi" + +/ { + model = "PINE64 RK3566 SOQuartz on Blade carrier board"; + compatible = "pine64,soquartz-blade", "pine64,soquartz", "rockchip,rk3566"; + + /* labeled VCC3V0_SD in schematic to not conflict with PMIC regulator */ + vcc3v0_sd: vcc3v0-sd-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v0_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + }; + + /* labeled VCC_SSD in schematic */ + vcc3v3_pcie_p: vcc3v3-pcie-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie_p"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vbus>; + }; + + vcc5v_dcin: vcc5v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&combphy2 { + phy-supply = <&vcc3v3_sys>; + status = "okay"; +}; + +&gmac1 { + status = "okay"; +}; + +/* + * i2c1 is exposed on CM1 / Module1A + * pin 80 - SCL0 - i2c1_scl_m0, pullup to vcc3v3_pmu + * pin 82 - SDA0 - i2c1_sda_m0, pullup to vcc3v3_pmu + */ +&i2c1 { + status = "okay"; + +}; + +/* + * i2c2 is exposed on CM1 / Module1A - to PI40 + * pin 56 - GPIO3 - i2c2_scl_m1, pullup to vcc_3v3, shared with i2s1_8ch + * pin 58 - GPIO2 - i2c2_sda_m1, pullup to vcc_3v3 + */ +&i2c2 { + status = "disabled"; +}; + +/* + * i2c3 is exposed on CM1 / Module1A - to PI40 + * pin 35 - ID_SC(GPIO28) - i2c3_scl_m0, pullup to vcc_3v3 + * pin 36 - ID_SD(GPIO27) - i2c3_sda_m0, pullup to vcc_3v3 + */ +&i2c3 { + status = "disabled"; +}; + +/* + * i2c4 is exposed on CM2 / Module1B - to PI40 + * pin 45 - GPIO24 - i2c4_scl_m1 + * pin 47 - GPIO23 - i2c4_sda_m1 + */ +&i2c4 { + status = "disabled"; +}; + +/* + * i2s1_8ch is exposed on CM1 / Module1A - to PI40 + * pin 24 - GPIO26 - i2s1_sdi1_m1 + * pin 25 - GPIO21 - i2s1_sdo0_m1 + * pin 26 - GPIO19 - i2s1_lrck_tx_m1 + * pin 27 - GPIO20 - i2s1_sdi0_m1 + * pin 29 - GPIO16 - i2s1_sdi3_m1 + * pin 30 - GPIO6 - i2s1_sdi2_m1 + * pin 40 - GPIO9 - i2s1_sdo1_m1, shared with spi3 + * pin 41 - GPIO25 - i2s1_sdo2_m1 + * pin 49 - GPIO18 - i2s1_sclk_tx_m1 + * pin 50 - GPIO17 - i2s1_mclk_m1 + * pin 56 - GPIO3 - i2s1_sdo3_m1, shared with i2c2 + */ +&i2s1_8ch { + status = "disabled"; +}; + +&led_diy { + color = <LED_COLOR_ID_RED>; + function = LED_FUNCTION_DISK_ACTIVITY; + linux,default-trigger = "disk-activity"; + status = "okay"; +}; + +&led_work { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_STATUS; + linux,default-trigger = "heartbeat"; + status = "okay"; +}; + +&pcie2x1 { + vpcie3v3-supply = <&vcc3v3_pcie_p>; + status = "okay"; +}; + +&rgmii_phy1 { + status = "okay"; +}; + +/* + * saradc is exposed on CM1 / Module1A - to J2 + * pin 94 - AIN1 - saradc_vin3 + * pin 96 - AIN0 - saradc_vin2 + */ +&saradc { + status = "disabled"; +}; + +&sdmmc0 { + vmmc-supply = <&vcc3v0_sd>; + status = "okay"; +}; + +/* + * spi3 is exposed on CM1 / Module1A - to PI40 + * pin 37 - GPIO7 - spi3_cs1_m0 + * pin 38 - GPIO11 - spi3_clk_m0 + * pin 39 - GPIO8 - spi3_cs0_m0 + * pin 40 - GPIO9 - spi3_miso_m0, shared with i2s1_8ch + * pin 44 - GPIO10 - spi3_mosi_m0 + */ +&spi3 { + status = "disabled"; +}; + +/* + * uart2 is exposed on CM1 / Module1A - to PI40 + * pin 51 - GPIO15 - uart2_rx_m0 + * pin 55 - GPIO14 - uart2_tx_m0 + */ +&uart2 { + status = "okay"; +}; + +/* + * uart7 is exposed on CM1 / Module1A - to PI40 + * pin 46 - GPIO22 - uart7_tx_m2 + * pin 47 - GPIO23 - uart7_rx_m2 + */ +&uart7 { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_otg { + phy-supply = <&vbus>; + status = "okay"; +}; + +&usb_host0_xhci { + status = "okay"; +}; + +&vbus { + vin-supply = <&vcc5v_dcin>; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts b/arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts index e00568a6be5c..263ce40770dd 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts @@ -30,6 +30,12 @@ }; }; +/* phy for pcie */ +&combphy2 { + phy-supply = <&vcc3v3_sys>; + status = "okay"; +}; + &gmac1 { status = "okay"; }; @@ -105,6 +111,11 @@ status = "okay"; }; +&pcie2x1 { + vpcie3v3-supply = <&vcc_3v3>; + status = "okay"; +}; + &rgmii_phy1 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-soquartz-model-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-soquartz-model-a.dts new file mode 100644 index 000000000000..2208dbfb7f0a --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-soquartz-model-a.dts @@ -0,0 +1,232 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk3566-soquartz.dtsi" + +/ { + model = "PINE64 RK3566 SOQuartz on Model A carrier board"; + compatible = "pine64,soquartz-model-a", "pine64,soquartz", "rockchip,rk3566"; + + /* labeled DCIN_12V in schematic */ + vcc12v_dcin: vcc12v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_usb: vcc5v0-usb-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + /* + * Labelled VCC3V0_SD in schematic to not conflict with PMIC + * regulator, it's 3.3v in actuality + */ + vcc3v0_sd: vcc3v0-sd-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v0_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc3v3_pcie: vcc3v3-pcie-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc12v_pcie: vcc12v-pcie-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_pcie"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + vin-supply = <&vcc12v_dcin>; + }; +}; + +/* phy for pcie */ +&combphy2 { + phy-supply = <&vcc3v3_sys>; + status = "okay"; +}; + +&gmac1 { + status = "okay"; +}; + +/* + * i2c1 is exposed on CM1 / Module1A + * pin 80 - SCL0 - i2c1_scl_m0, pullup to vcc3v3_pmu + * pin 82 - SDA0 - i2c1_sda_m0, pullup to vcc3v3_pmu + */ +&i2c1 { + status = "okay"; + + /* + * the rtc interrupt is tied to PMIC_PWRON, + * it will force reset the board if triggered. + */ + pcf85063: rtc@51 { + compatible = "nxp,pcf85063"; + reg = <0x51>; + }; +}; + +/* + * i2c2 is exposed on CM1 / Module1A - to PI40 + * pin 56 - GPIO3 - i2c2_scl_m1, pullup to vcc_3v3, shared with i2s1_8ch + * pin 58 - GPIO2 - i2c2_sda_m1, pullup to vcc_3v3 + */ +&i2c2 { + status = "disabled"; +}; + +/* + * i2c3 is exposed on CM1 / Module1A - to PI40 + * pin 35 - ID_SC(GPIO28) - i2c3_scl_m0, pullup to vcc_3v3 + * pin 36 - ID_SD(GPIO27) - i2c3_sda_m0, pullup to vcc_3v3 + */ +&i2c3 { + status = "disabled"; +}; + +/* + * i2c4 is exposed on CM2 / Module1B - to PI40 + * pin 45 - GPIO24 - i2c4_scl_m1 + * pin 47 - GPIO23 - i2c4_sda_m1 + */ +&i2c4 { + status = "disabled"; +}; + +/* + * i2s1_8ch is exposed on CM1 / Module1A - to PI40 + * pin 24 - GPIO26 - i2s1_sdi1_m1 + * pin 25 - GPIO21 - i2s1_sdo0_m1 + * pin 26 - GPIO19 - i2s1_lrck_tx_m1 + * pin 27 - GPIO20 - i2s1_sdi0_m1 + * pin 29 - GPIO16 - i2s1_sdi3_m1 + * pin 30 - GPIO6 - i2s1_sdi2_m1 + * pin 40 - GPIO9 - i2s1_sdo1_m1, shared with spi3 + * pin 41 - GPIO25 - i2s1_sdo2_m1 + * pin 49 - GPIO18 - i2s1_sclk_tx_m1 + * pin 50 - GPIO17 - i2s1_mclk_m1 + * pin 56 - GPIO3 - i2s1_sdo3_m1, shared with i2c2 + */ +&i2s1_8ch { + status = "disabled"; +}; + +&led_diy { + status = "okay"; +}; + +&led_work { + status = "okay"; +}; + +&pcie2x1 { + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&rgmii_phy1 { + status = "okay"; +}; + +&rgmii_phy1 { + status = "okay"; +}; + +/* + * saradc is exposed on CM1 / Module1A - to J2 + * pin 94 - AIN1 - saradc_vin3 + * pin 96 - AIN0 - saradc_vin2 + */ +&saradc { + status = "disabled"; +}; + +/* + * vmmc-supply is vcc3v3_sd on v1.0 and vcc3v0_sd on v1.1+ + * the soquartz SoM has SDMMC_PWR (CM1 pin 75) hardwired to vcc3v3_sys, + * so we use vcc3v3_sd here to ensure the regulator is enabled on older boards. + */ +&sdmmc0 { + vmmc-supply = <&vcc3v3_sd>; + status = "okay"; +}; + +/* + * spi3 is exposed on CM1 / Module1A - to PI40 + * pin 37 - GPIO7 - spi3_cs1_m0 + * pin 38 - GPIO11 - spi3_clk_m0 + * pin 39 - GPIO8 - spi3_cs0_m0 + * pin 40 - GPIO9 - spi3_miso_m0, shared with i2s1_8ch + * pin 44 - GPIO10 - spi3_mosi_m0 + */ +&spi3 { + status = "disabled"; +}; + +/* + * uart2 is exposed on CM1 / Module1A - to PI40 + * pin 51 - GPIO15 - uart2_rx_m0 + * pin 55 - GPIO14 - uart2_tx_m0 + */ +&uart2 { + status = "okay"; +}; + +/* + * uart7 is exposed on CM1 / Module1A - to PI40 + * pin 46 - GPIO22 - uart7_tx_m2 + * pin 47 - GPIO23 - uart7_rx_m2 + */ +&uart7 { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_otg { + phy-supply = <&vcc5v0_usb>; + status = "okay"; +}; + +&usb_host0_xhci { + status = "okay"; +}; + +&vbus { + vin-supply = <&vcc5v0_usb>; +}; + +&vcc3v3_sd { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi index 5bcd4be32964..ce7165d7f1a1 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi @@ -4,6 +4,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/soc/rockchip,vop2.h> #include "rk3566.dtsi" / { @@ -28,6 +29,17 @@ #clock-cells = <0>; }; + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; @@ -143,6 +155,33 @@ status = "disabled"; }; +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + avdd-0v9-supply = <&vdda0v9_image>; + avdd-1v8-supply = <&vcca1v8_image>; + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status = "okay"; +}; + &i2c0 { status = "okay"; @@ -411,6 +450,10 @@ status = "disabled"; }; +&i2s0_8ch { + status = "okay"; +}; + /* * i2s1_8ch is exposed on CM1 / Module1A * pin 24 - i2s1_sdi1_m1 @@ -444,6 +487,12 @@ }; }; +&pcie2x1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_reset_h>; + reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; +}; + &pinctrl { bt { bt_enable_h: bt-enable-h { @@ -469,6 +518,15 @@ }; }; + pcie { + pcie_clkreq_h: pcie-clkreq-h { + rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + pcie_reset_h: pcie-reset-h { + rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + pmic { pmic_int_l: pmic-int-l { rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; @@ -614,3 +672,20 @@ &usb_host0_xhci { status = "disabled"; }; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = <ROCKCHIP_VOP2_EP_HDMI0>; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts new file mode 100644 index 000000000000..59ecf868dbd0 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts @@ -0,0 +1,744 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Hardkernel Co., Ltd. + * + */ + +/dts-v1/; +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/soc/rockchip,vop2.h> +#include "rk3568.dtsi" + +/ { + model = "Hardkernel ODROID-M1"; + compatible = "rockchip,rk3568-odroid-m1", "rockchip,rk3568"; + + aliases { + ethernet0 = &gmac0; + i2c0 = &i2c3; + i2c3 = &i2c0; + mmc0 = &sdhci; + mmc1 = &sdmmc0; + serial0 = &uart1; + serial1 = &uart0; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + dc_12v: dc-12v-regulator { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&ir_receiver_pin>; + }; + + leds { + compatible = "gpio-leds"; + + led_power: led-0 { + gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + function = LED_FUNCTION_POWER; + color = <LED_COLOR_ID_RED>; + default-state = "keep"; + linux,default-trigger = "default-on"; + pinctrl-names = "default"; + pinctrl-0 = <&led_power_pin>; + }; + led_work: led-1 { + gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + function = LED_FUNCTION_HEARTBEAT; + color = <LED_COLOR_ID_BLUE>; + linux,default-trigger = "heartbeat"; + pinctrl-names = "default"; + pinctrl-0 = <&led_work_pin>; + }; + }; + + rk809-sound { + compatible = "simple-audio-card"; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det_pin>; + simple-audio-card,name = "Analog RK817"; + simple-audio-card,format = "i2s"; + simple-audio-card,hp-det-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,widgets = + "Headphone", "Headphones", + "Speaker", "Speaker"; + simple-audio-card,routing = + "Headphones", "HPOL", + "Headphones", "HPOR", + "Speaker", "SPKO"; + + simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; + + simple-audio-card,codec { + sound-dai = <&rk809>; + }; + }; + + vcc3v3_pcie: vcc3v3-pcie-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie"; + enable-active-high; + gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc3v3_pcie_en_pin>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <5000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc3v3_sys: vcc3v3-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_usb_host: vcc5v0-usb-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb_host"; + enable-active-high; + gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb_host_en_pin>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_usb_otg: vcc5v0-usb-otg-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb_otg"; + enable-active-high; + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb_otg_en_pin>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&combphy0 { + /* Used for USB3 */ + phy-supply = <&vcc5v0_usb_host>; + status = "okay"; +}; + +&combphy1 { + /* Used for USB3 */ + phy-supply = <&vcc5v0_usb_otg>; + status = "okay"; +}; + +&combphy2 { + /* used for SATA */ + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&gmac0 { + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; + assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>; + assigned-clock-rates = <0>, <125000000>; + clock_in_out = "output"; + phy-handle = <&rgmii_phy0>; + phy-mode = "rgmii"; + phy-supply = <&vcc3v3_sys>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + status = "okay"; + + tx_delay = <0x4f>; + rx_delay = <0x2d>; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + avdd-0v9-supply = <&vdda0v9_image>; + avdd-1v8-supply = <&vcca1v8_image>; + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: regulator@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc3v3_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>; + assigned-clocks = <&cru I2S1_MCLKOUT_TX>; + assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; + #clock-cells = <1>; + clock-names = "mclk"; + clocks = <&cru I2S1_MCLKOUT_TX>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>, <&i2s1m0_mclk>; + rockchip,system-power-controller; + #sound-dai-cells = <0>; + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + wakeup-source; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-always-on; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-name = "vdd_npu"; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-name = "vdda0v9_image"; + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-name = "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-name = "vdda0v9_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-name = "vccio_acodec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-name = "vcc3v3_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-name = "vcca1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-name = "vcca1v8_image"; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-name = "vcc3v3_sd"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&i2s1_8ch { + rockchip,trcm-sync-tx-only; + status = "okay"; +}; + +&mdio0 { + rgmii_phy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + }; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x2 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_reset_pin>; + reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pinctrl { + fspi { + fspi_dual_io_pins: fspi-dual-io-pins { + rockchip,pins = + /* fspi_clk */ + <1 RK_PD0 1 &pcfg_pull_none>, + /* fspi_cs0n */ + <1 RK_PD3 1 &pcfg_pull_none>, + /* fspi_d0 */ + <1 RK_PD1 1 &pcfg_pull_none>, + /* fspi_d1 */ + <1 RK_PD2 1 &pcfg_pull_none>; + }; + }; + + ir-receiver { + ir_receiver_pin: ir-receiver-pin { + /* external pullup to VCC3V3_SYS */ + rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + led_power_pin: led-power-pin { + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + led_work_pin: led-work-pin { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + pcie_reset_pin: pcie-reset-pin { + rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + vcc3v3_pcie_en_pin: vcc3v3-pcie-en-pin { + rockchip,pins = <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + rk809 { + hp_det_pin: hp-det-pin { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_usb_host_en_pin: vcc5v0-usb-host-en-pin { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + vcc5v0_usb_otg_en_pin: vcc5v0-usb-dr-en-pin { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_3v3>; + vccio7-supply = <&vcc_3v3>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca_1v8>; + status = "okay"; +}; + +&sata2 { + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + max-frequency = <200000000>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe &emmc_rstnout>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdmmc0 { + bus-width = <4>; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + sd-uhs-sdr50; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&sfc { + /* Dual I/O mode as the D2 pin conflicts with the eMMC */ + pinctrl-0 = <&fspi_dual_io_pins>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <100000000>; + spi-rx-bus-width = <2>; + spi-tx-bus-width = <1>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "SPL"; + reg = <0x0 0xe0000>; + }; + partition@e0000 { + label = "U-Boot Env"; + reg = <0xe0000 0x20000>; + }; + partition@100000 { + label = "U-Boot"; + reg = <0x100000 0x200000>; + }; + partition@300000 { + label = "splash"; + reg = <0x300000 0x100000>; + }; + partition@400000 { + label = "Filesystem"; + reg = <0x400000 0xc00000>; + }; + }; + }; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host0_xhci { + dr_mode = "host"; + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host1_xhci { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_host { + phy-supply = <&vcc5v0_usb_host>; + status = "okay"; +}; + +&usb2phy0_otg { + phy-supply = <&vcc5v0_usb_otg>; + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb2phy1_host { + phy-supply = <&vcc5v0_usb_host>; + status = "okay"; +}; + +&usb2phy1_otg { + phy-supply = <&vcc5v0_usb_host>; + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = <ROCKCHIP_VOP2_EP_HDMI0>; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts index fb87a168fe96..0b6d23a0de01 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts @@ -32,6 +32,13 @@ }; }; + gmac1_clkin: external-gmac1-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac1_clkin"; + #clock-cells = <0>; + }; + leds { compatible = "gpio-leds"; @@ -60,13 +67,55 @@ }; }; - vcc12v_dcin: vcc12v-dcin { + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable>; + post-power-on-delay-ms = <100>; + power-off-delay-us = <5000000>; + reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>; + }; + + vcc12v_dcin: vcc12v-dcin-regulator { compatible = "regulator-fixed"; regulator-name = "vcc12v_dcin"; regulator-always-on; regulator-boot-on; }; + pcie30_avdd0v9: pcie30-avdd0v9-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc3v3_sys>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_sys>; + }; + + /* pi6c pcie clock generator */ + vcc3v3_pi6c_03: vcc3v3-pi6c-03-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pi6c_03"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + vcc3v3_pcie: vcc3v3-pcie-regulator { compatible = "regulator-fixed"; enable-active-high; @@ -79,7 +128,7 @@ vin-supply = <&vcc5v0_sys>; }; - vcc3v3_sys: vcc3v3-sys { + vcc3v3_sys: vcc3v3-sys-regulator { compatible = "regulator-fixed"; regulator-name = "vcc3v3_sys"; regulator-always-on; @@ -89,7 +138,7 @@ vin-supply = <&vcc12v_dcin>; }; - vcc5v0_sys: vcc5v0-sys { + vcc5v0_sys: vcc5v0-sys-regulator { compatible = "regulator-fixed"; regulator-name = "vcc5v0_sys"; regulator-always-on; @@ -99,7 +148,7 @@ vin-supply = <&vcc12v_dcin>; }; - vcc5v0_usb: vcc5v0-usb { + vcc5v0_usb: vcc5v0-usb-regulator { compatible = "regulator-fixed"; regulator-name = "vcc5v0_usb"; regulator-always-on; @@ -109,7 +158,7 @@ vin-supply = <&vcc12v_dcin>; }; - vcc5v0_usb_host: vcc5v0-usb-host { + vcc5v0_usb_host: vcc5v0-usb-host-regulator { compatible = "regulator-fixed"; enable-active-high; gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; @@ -144,7 +193,7 @@ vin-supply = <&vcc5v0_usb>; }; - vcc_cam: vcc-cam { + vcc_cam: vcc-cam-regulator { compatible = "regulator-fixed"; enable-active-high; gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; @@ -160,7 +209,7 @@ }; }; - vcc_mipi: vcc-mipi { + vcc_mipi: vcc-mipi-regulator { compatible = "regulator-fixed"; enable-active-high; gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; @@ -207,16 +256,17 @@ &gmac1 { assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; - assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>; - assigned-clock-rates = <0>, <125000000>; - clock_in_out = "output"; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>; + clock_in_out = "input"; phy-handle = <&rgmii_phy1>; phy-mode = "rgmii-id"; + phy-supply = <&vcc_3v3>; pinctrl-names = "default"; pinctrl-0 = <&gmac1m1_miim &gmac1m1_tx_bus2 &gmac1m1_rx_bus2 &gmac1m1_rgmii_clk + &gmac1m1_clkinout &gmac1m1_rgmii_bus>; status = "okay"; }; @@ -526,6 +576,11 @@ status = "okay"; }; +&i2s2_2ch { + rockchip,trcm-sync-tx-only; + status = "okay"; +}; + &mdio1 { rgmii_phy1: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; @@ -546,6 +601,19 @@ status = "okay"; }; +&pcie30phy { + phy-supply = <&vcc3v3_pi6c_03>; + status = "okay"; +}; + +&pcie3x2 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie30x2m1_pins>; + reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + &pinctrl { cam { vcc_cam_en: vcc_cam_en { @@ -605,6 +673,26 @@ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; }; }; + + bt { + bt_enable: bt-enable { + rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_host_wake: bt-host-wake { + rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + bt_wake: bt-wake { + rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable: wifi-enable { + rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; }; &pmu_io_domains { @@ -649,12 +737,50 @@ status = "okay"; }; +&sdmmc2 { + supports-sdio; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sys>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + &tsadc { rockchip,hw-tshut-mode = <1>; rockchip,hw-tshut-polarity = <0>; status = "okay"; }; +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&rk809 1>; + clock-names = "lpo"; + device-wakeup-gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake &bt_wake &bt_enable>; + vbat-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_1v8>; + /* vddio comes from regulator on module, use IO bank voltage instead */ + }; +}; + &uart2 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index 164708f1eb67..5706c3e24f0a 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -1049,20 +1049,6 @@ status = "disabled"; }; - spdif: spdif@fe460000 { - compatible = "rockchip,rk3568-spdif"; - reg = <0x0 0xfe460000 0x0 0x1000>; - interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "mclk", "hclk"; - clocks = <&cru MCLK_SPDIF_8CH>, <&cru HCLK_SPDIF_8CH>; - dmas = <&dmac1 1>; - dma-names = "tx"; - pinctrl-names = "default"; - pinctrl-0 = <&spdifm0_tx>; - #sound-dai-cells = <0>; - status = "disabled"; - }; - i2s0_8ch: i2s@fe400000 { compatible = "rockchip,rk3568-i2s-tdm"; reg = <0x0 0xfe400000 0x0 0x1000>; @@ -1105,6 +1091,28 @@ status = "disabled"; }; + i2s2_2ch: i2s@fe420000 { + compatible = "rockchip,rk3568-i2s-tdm"; + reg = <0x0 0xfe420000 0x0 0x1000>; + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; + assigned-clocks = <&cru CLK_I2S2_2CH_SRC>; + assigned-clock-rates = <1188000000>; + clocks = <&cru MCLK_I2S2_2CH>, <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + dmas = <&dmac1 4>, <&dmac1 5>; + dma-names = "tx", "rx"; + resets = <&cru SRST_M_I2S2_2CH>; + reset-names = "m"; + rockchip,grf = <&grf>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s2m0_sclktx + &i2s2m0_lrcktx + &i2s2m0_sdi + &i2s2m0_sdo>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + i2s3_2ch: i2s@fe430000 { compatible = "rockchip,rk3568-i2s-tdm"; reg = <0x0 0xfe430000 0x0 0x1000>; @@ -1142,6 +1150,20 @@ status = "disabled"; }; + spdif: spdif@fe460000 { + compatible = "rockchip,rk3568-spdif"; + reg = <0x0 0xfe460000 0x0 0x1000>; + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "mclk", "hclk"; + clocks = <&cru MCLK_SPDIF_8CH>, <&cru HCLK_SPDIF_8CH>; + dmas = <&dmac1 1>; + dma-names = "tx"; + pinctrl-names = "default"; + pinctrl-0 = <&spdifm0_tx>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + dmac0: dma-controller@fe530000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x0 0xfe530000 0x0 0x4000>; diff --git a/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi index d0abb9aa0e9e..e3852c946352 100644 --- a/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi +++ b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi @@ -55,14 +55,14 @@ samsung,pins = "gpf5-0"; samsung,pin-function = <FSD_PIN_FUNC_2>; samsung,pin-pud = <FSD_PIN_PULL_NONE>; - samsung,pin-drv = <FSD_PIN_DRV_LV2>; + samsung,pin-drv = <FSD_PIN_DRV_LV4>; }; ufs_refclk_out: ufs-refclk-out-pins { samsung,pins = "gpf5-1"; samsung,pin-function = <FSD_PIN_FUNC_2>; samsung,pin-pud = <FSD_PIN_PULL_NONE>; - samsung,pin-drv = <FSD_PIN_DRV_LV2>; + samsung,pin-drv = <FSD_PIN_DRV_LV4>; }; }; @@ -239,105 +239,105 @@ samsung,pins = "gpb6-1"; samsung,pin-function = <FSD_PIN_FUNC_2>; samsung,pin-pud = <FSD_PIN_PULL_UP>; - samsung,pin-drv = <FSD_PIN_DRV_LV2>; + samsung,pin-drv = <FSD_PIN_DRV_LV4>; }; pwm1_out: pwm1-out-pins { samsung,pins = "gpb6-5"; samsung,pin-function = <FSD_PIN_FUNC_2>; samsung,pin-pud = <FSD_PIN_PULL_UP>; - samsung,pin-drv = <FSD_PIN_DRV_LV2>; + samsung,pin-drv = <FSD_PIN_DRV_LV4>; }; hs_i2c0_bus: hs-i2c0-bus-pins { samsung,pins = "gpb0-0", "gpb0-1"; samsung,pin-function = <FSD_PIN_FUNC_2>; samsung,pin-pud = <FSD_PIN_PULL_UP>; - samsung,pin-drv = <FSD_PIN_DRV_LV1>; + samsung,pin-drv = <FSD_PIN_DRV_LV4>; }; hs_i2c1_bus: hs-i2c1-bus-pins { samsung,pins = "gpb0-2", "gpb0-3"; samsung,pin-function = <FSD_PIN_FUNC_2>; samsung,pin-pud = <FSD_PIN_PULL_UP>; - samsung,pin-drv = <FSD_PIN_DRV_LV1>; + samsung,pin-drv = <FSD_PIN_DRV_LV4>; }; hs_i2c2_bus: hs-i2c2-bus-pins { samsung,pins = "gpb0-4", "gpb0-5"; samsung,pin-function = <FSD_PIN_FUNC_2>; samsung,pin-pud = <FSD_PIN_PULL_UP>; - samsung,pin-drv = <FSD_PIN_DRV_LV1>; + samsung,pin-drv = <FSD_PIN_DRV_LV4>; }; hs_i2c3_bus: hs-i2c3-bus-pins { samsung,pins = "gpb0-6", "gpb0-7"; samsung,pin-function = <FSD_PIN_FUNC_2>; samsung,pin-pud = <FSD_PIN_PULL_UP>; - samsung,pin-drv = <FSD_PIN_DRV_LV1>; + samsung,pin-drv = <FSD_PIN_DRV_LV4>; }; hs_i2c4_bus: hs-i2c4-bus-pins { samsung,pins = "gpb1-0", "gpb1-1"; samsung,pin-function = <FSD_PIN_FUNC_2>; samsung,pin-pud = <FSD_PIN_PULL_UP>; - samsung,pin-drv = <FSD_PIN_DRV_LV1>; + samsung,pin-drv = <FSD_PIN_DRV_LV4>; }; hs_i2c5_bus: hs-i2c5-bus-pins { samsung,pins = "gpb1-2", "gpb1-3"; samsung,pin-function = <FSD_PIN_FUNC_2>; samsung,pin-pud = <FSD_PIN_PULL_UP>; - samsung,pin-drv = <FSD_PIN_DRV_LV1>; + samsung,pin-drv = <FSD_PIN_DRV_LV4>; }; hs_i2c6_bus: hs-i2c6-bus-pins { samsung,pins = "gpb1-4", "gpb1-5"; samsung,pin-function = <FSD_PIN_FUNC_2>; samsung,pin-pud = <FSD_PIN_PULL_UP>; - samsung,pin-drv = <FSD_PIN_DRV_LV1>; + samsung,pin-drv = <FSD_PIN_DRV_LV4>; }; hs_i2c7_bus: hs-i2c7-bus-pins { samsung,pins = "gpb1-6", "gpb1-7"; samsung,pin-function = <FSD_PIN_FUNC_2>; samsung,pin-pud = <FSD_PIN_PULL_UP>; - samsung,pin-drv = <FSD_PIN_DRV_LV1>; + samsung,pin-drv = <FSD_PIN_DRV_LV4>; }; uart0_data: uart0-data-pins { samsung,pins = "gpb7-0", "gpb7-1"; samsung,pin-function = <FSD_PIN_FUNC_2>; samsung,pin-pud = <FSD_PIN_PULL_NONE>; - samsung,pin-drv = <FSD_PIN_DRV_LV1>; + samsung,pin-drv = <FSD_PIN_DRV_LV4>; }; uart1_data: uart1-data-pins { samsung,pins = "gpb7-4", "gpb7-5"; samsung,pin-function = <FSD_PIN_FUNC_2>; samsung,pin-pud = <FSD_PIN_PULL_NONE>; - samsung,pin-drv = <FSD_PIN_DRV_LV1>; + samsung,pin-drv = <FSD_PIN_DRV_LV4>; }; spi0_bus: spi0-bus-pins { samsung,pins = "gpb4-0", "gpb4-2", "gpb4-3"; samsung,pin-function = <FSD_PIN_FUNC_2>; samsung,pin-pud = <FSD_PIN_PULL_UP>; - samsung,pin-drv = <FSD_PIN_DRV_LV1>; + samsung,pin-drv = <FSD_PIN_DRV_LV4>; }; spi1_bus: spi1-bus-pins { samsung,pins = "gpb4-4", "gpb4-6", "gpb4-7"; samsung,pin-function = <FSD_PIN_FUNC_2>; samsung,pin-pud = <FSD_PIN_PULL_UP>; - samsung,pin-drv = <FSD_PIN_DRV_LV1>; + samsung,pin-drv = <FSD_PIN_DRV_LV4>; }; spi2_bus: spi2-bus-pins { samsung,pins = "gpb5-0", "gpb5-2", "gpb5-3"; samsung,pin-function = <FSD_PIN_FUNC_2>; samsung,pin-pud = <FSD_PIN_PULL_UP>; - samsung,pin-drv = <FSD_PIN_DRV_LV1>; + samsung,pin-drv = <FSD_PIN_DRV_LV4>; }; }; diff --git a/arch/arm64/boot/dts/tesla/fsd-pinctrl.h b/arch/arm64/boot/dts/tesla/fsd-pinctrl.h index 6ffbda362493..c397d02208a0 100644 --- a/arch/arm64/boot/dts/tesla/fsd-pinctrl.h +++ b/arch/arm64/boot/dts/tesla/fsd-pinctrl.h @@ -16,9 +16,9 @@ #define FSD_PIN_PULL_UP 3 #define FSD_PIN_DRV_LV1 0 -#define FSD_PIN_DRV_LV2 2 -#define FSD_PIN_DRV_LV3 1 -#define FSD_PIN_DRV_LV4 3 +#define FSD_PIN_DRV_LV2 1 +#define FSD_PIN_DRV_LV4 2 +#define FSD_PIN_DRV_LV6 3 #define FSD_PIN_FUNC_INPUT 0 #define FSD_PIN_FUNC_OUTPUT 1 diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 4555a5be2257..cf7c509538a4 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -12,6 +12,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am6528-iot2050-basic-pg2.dtb dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced.dtb dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced-pg2.dtb +dtb-$(CONFIG_ARCH_K3) += k3-j721e-beagleboneai64.dtb dtb-$(CONFIG_ARCH_K3) += k3-j721e-common-proc-board.dtb dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk.dtb diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi index 03660476364f..072903649d6e 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -192,6 +192,102 @@ pinctrl-single,function-mask = <0xffffffff>; }; + main_timer0: timer@2400000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2400000 0x00 0x400>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 36 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 36 2>; + assigned-clock-parents = <&k3_clks 36 3>; + power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer1: timer@2410000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2410000 0x00 0x400>; + interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 37 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 37 2>; + assigned-clock-parents = <&k3_clks 37 3>; + power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer2: timer@2420000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2420000 0x00 0x400>; + interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 38 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 38 2>; + assigned-clock-parents = <&k3_clks 38 3>; + power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer3: timer@2430000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2430000 0x00 0x400>; + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 39 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 39 2>; + assigned-clock-parents = <&k3_clks 39 3>; + power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer4: timer@2440000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2440000 0x00 0x400>; + interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 40 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 40 2>; + assigned-clock-parents = <&k3_clks 40 3>; + power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer5: timer@2450000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2450000 0x00 0x400>; + interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 41 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 41 2>; + assigned-clock-parents = <&k3_clks 41 3>; + power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer6: timer@2460000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2460000 0x00 0x400>; + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 42 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 42 2>; + assigned-clock-parents = <&k3_clks 42 3>; + power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer7: timer@2470000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2470000 0x00 0x400>; + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 43 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 43 2>; + assigned-clock-parents = <&k3_clks 43 3>; + power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + main_uart0: serial@2800000 { compatible = "ti,am64-uart", "ti,am654-uart"; reg = <0x00 0x02800000 0x00 0x100>; @@ -199,6 +295,7 @@ power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 146 0>; clock-names = "fclk"; + status = "disabled"; }; main_uart1: serial@2810000 { @@ -208,6 +305,7 @@ power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 152 0>; clock-names = "fclk"; + status = "disabled"; }; main_uart2: serial@2820000 { @@ -217,6 +315,7 @@ power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 153 0>; clock-names = "fclk"; + status = "disabled"; }; main_uart3: serial@2830000 { @@ -226,6 +325,7 @@ power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 154 0>; clock-names = "fclk"; + status = "disabled"; }; main_uart4: serial@2840000 { @@ -235,6 +335,7 @@ power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 155 0>; clock-names = "fclk"; + status = "disabled"; }; main_uart5: serial@2850000 { @@ -244,6 +345,7 @@ power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 156 0>; clock-names = "fclk"; + status = "disabled"; }; main_uart6: serial@2860000 { @@ -253,6 +355,7 @@ power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 158 0>; clock-names = "fclk"; + status = "disabled"; }; main_i2c0: i2c@20000000 { @@ -264,6 +367,7 @@ power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 102 2>; clock-names = "fck"; + status = "disabled"; }; main_i2c1: i2c@20010000 { @@ -275,6 +379,7 @@ power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 103 2>; clock-names = "fck"; + status = "disabled"; }; main_i2c2: i2c@20020000 { @@ -286,6 +391,7 @@ power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 104 2>; clock-names = "fck"; + status = "disabled"; }; main_i2c3: i2c@20030000 { @@ -297,6 +403,7 @@ power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 105 2>; clock-names = "fck"; + status = "disabled"; }; main_spi0: spi@20100000 { @@ -307,6 +414,7 @@ #size-cells = <0>; power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 172 0>; + status = "disabled"; }; main_spi1: spi@20110000 { @@ -317,6 +425,7 @@ #size-cells = <0>; power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 173 0>; + status = "disabled"; }; main_spi2: spi@20120000 { @@ -327,6 +436,7 @@ #size-cells = <0>; power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 174 0>; + status = "disabled"; }; main_gpio_intr: interrupt-controller@a00000 { @@ -393,6 +503,7 @@ ti,otap-del-sel-mmc-hs = <0x0>; ti,otap-del-sel-ddr52 = <0x9>; ti,otap-del-sel-hs200 = <0x6>; + status = "disabled"; }; sdhci1: mmc@fa00000 { @@ -416,6 +527,7 @@ ti,itap-del-sel-sdr25 = <0x0>; ti,clkbuf-sel = <0x7>; bus-width = <4>; + status = "disabled"; }; sdhci2: mmc@fa20000 { @@ -438,6 +550,7 @@ ti,itap-del-sel-sdr12 = <0x0>; ti,itap-del-sel-sdr25 = <0x0>; ti,clkbuf-sel = <0x7>; + status = "disabled"; }; fss: bus@fc00000 { @@ -462,6 +575,7 @@ power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; }; @@ -520,6 +634,7 @@ clocks = <&k3_clks 13 0>; clock-names = "fck"; bus_freq = <1000000>; + status = "disabled"; }; cpts@3d000 { @@ -557,6 +672,7 @@ power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 51 0>; clock-names = "fck"; + status = "disabled"; }; ecap1: pwm@23110000 { @@ -566,6 +682,7 @@ power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 52 0>; clock-names = "fck"; + status = "disabled"; }; ecap2: pwm@23120000 { @@ -575,6 +692,7 @@ power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 53 0>; clock-names = "fck"; + status = "disabled"; }; main_mcan0: can@20701000 { @@ -589,6 +707,7 @@ <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; epwm0: pwm@23000000 { @@ -598,6 +717,7 @@ power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>; clock-names = "tbclk", "fck"; + status = "disabled"; }; epwm1: pwm@23010000 { @@ -607,6 +727,7 @@ power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>; clock-names = "tbclk", "fck"; + status = "disabled"; }; epwm2: pwm@23020000 { @@ -616,5 +737,6 @@ power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>; clock-names = "tbclk", "fck"; + status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi index f56c803560f2..a427231527c3 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi @@ -14,6 +14,51 @@ pinctrl-single,function-mask = <0xffffffff>; }; + /* + * The MCU domain timer interrupts are routed only to the ESM module, + * and not currently available for Linux. The MCU domain timers are + * of limited use without interrupts, and likely reserved by the ESM. + */ + mcu_timer0: timer@4800000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x4800000 0x00 0x400>; + clocks = <&k3_clks 35 2>; + clock-names = "fck"; + power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + status = "reserved"; + }; + + mcu_timer1: timer@4810000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x4810000 0x00 0x400>; + clocks = <&k3_clks 48 2>; + clock-names = "fck"; + power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + status = "reserved"; + }; + + mcu_timer2: timer@4820000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x4820000 0x00 0x400>; + clocks = <&k3_clks 49 2>; + clock-names = "fck"; + power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + status = "reserved"; + }; + + mcu_timer3: timer@4830000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x4830000 0x00 0x400>; + clocks = <&k3_clks 50 2>; + clock-names = "fck"; + power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + status = "reserved"; + }; + mcu_uart0: serial@4a00000 { compatible = "ti,am64-uart", "ti,am654-uart"; reg = <0x00 0x04a00000 0x00 0x100>; @@ -21,6 +66,7 @@ power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 149 0>; clock-names = "fclk"; + status = "disabled"; }; mcu_i2c0: i2c@4900000 { @@ -32,6 +78,7 @@ power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 106 2>; clock-names = "fck"; + status = "disabled"; }; mcu_spi0: spi@4b00000 { @@ -42,6 +89,7 @@ #size-cells = <0>; power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 147 0>; + status = "disabled"; }; mcu_spi1: spi@4b10000 { @@ -52,6 +100,7 @@ #size-cells = <0>; power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 148 0>; + status = "disabled"; }; mcu_gpio_intr: interrupt-controller@4210000 { diff --git a/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi index 4090134676cf..38dced6b4fef 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi @@ -26,16 +26,18 @@ power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 114 0>; clock-names = "fclk"; + status = "disabled"; }; wkup_i2c0: i2c@2b200000 { compatible = "ti,am64-i2c", "ti,omap4-i2c"; - reg = <0x00 0x02b200000 0x00 0x100>; + reg = <0x00 0x2b200000 0x00 0x100>; interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 107 4>; clock-names = "fck"; + status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am625-sk.dts b/arch/arm64/boot/dts/ti/k3-am625-sk.dts index 93a5f0817efc..18ca56cedc63 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am625-sk.dts @@ -282,11 +282,8 @@ status = "reserved"; }; -&mcu_uart0 { - status = "disabled"; -}; - &main_uart0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_uart0_pins_default>; }; @@ -296,41 +293,15 @@ status = "reserved"; }; -&main_uart2 { - status = "disabled"; -}; - -&main_uart3 { - status = "disabled"; -}; - -&main_uart4 { - status = "disabled"; -}; - -&main_uart5 { - status = "disabled"; -}; - -&main_uart6 { - status = "disabled"; -}; - -&mcu_i2c0 { - status = "disabled"; -}; - -&wkup_i2c0 { - status = "disabled"; -}; - &main_i2c0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c0_pins_default>; clock-frequency = <400000>; }; &main_i2c1 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c1_pins_default>; clock-frequency = <400000>; @@ -363,15 +334,8 @@ }; }; -&main_i2c2 { - status = "disabled"; -}; - -&main_i2c3 { - status = "disabled"; -}; - &sdhci0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_mmc0_pins_default>; ti,driver-strength-ohm = <50>; @@ -380,6 +344,7 @@ &sdhci1 { /* SD/MMC */ + status = "okay"; vmmc-supply = <&vdd_mmc1>; vqmmc-supply = <&vdd_sd_dv>; pinctrl-names = "default"; @@ -390,8 +355,7 @@ &cpsw3g { pinctrl-names = "default"; - pinctrl-0 = <&main_mdio1_pins_default - &main_rgmii1_pins_default + pinctrl-0 = <&main_rgmii1_pins_default &main_rgmii2_pins_default>; }; @@ -406,6 +370,10 @@ }; &cpsw3g_mdio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_mdio1_pins_default>; + cpsw3g_phy0: ethernet-phy@0 { reg = <0>; ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; @@ -429,6 +397,7 @@ }; &ospi0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&ospi0_pins_default>; @@ -486,31 +455,3 @@ }; }; }; - -&ecap0 { - status = "disabled"; -}; - -&ecap1 { - status = "disabled"; -}; - -&ecap2 { - status = "disabled"; -}; - -&main_mcan0 { - status = "disabled"; -}; - -&epwm0 { - status = "disabled"; -}; - -&epwm1 { - status = "disabled"; -}; - -&epwm2 { - status = "disabled"; -}; diff --git a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi index 99afac40e8d4..81d984414fd4 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi @@ -31,7 +31,7 @@ wkup_i2c0: i2c@2b200000 { compatible = "ti,am64-i2c", "ti,omap4-i2c"; - reg = <0x00 0x02b200000 0x00 0x100>; + reg = <0x00 0x2b200000 0x00 0x100>; interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index d6aa23681bbe..5e8036f32d79 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -237,6 +237,7 @@ power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 146 0>; clock-names = "fclk"; + status = "disabled"; }; main_uart1: serial@2810000 { @@ -248,6 +249,7 @@ power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 152 0>; clock-names = "fclk"; + status = "disabled"; }; main_uart2: serial@2820000 { @@ -259,6 +261,7 @@ power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 153 0>; clock-names = "fclk"; + status = "disabled"; }; main_uart3: serial@2830000 { @@ -270,6 +273,7 @@ power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 154 0>; clock-names = "fclk"; + status = "disabled"; }; main_uart4: serial@2840000 { @@ -281,6 +285,7 @@ power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 155 0>; clock-names = "fclk"; + status = "disabled"; }; main_uart5: serial@2850000 { @@ -292,6 +297,7 @@ power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 156 0>; clock-names = "fclk"; + status = "disabled"; }; main_uart6: serial@2860000 { @@ -303,6 +309,7 @@ power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 158 0>; clock-names = "fclk"; + status = "disabled"; }; main_i2c0: i2c@20000000 { @@ -314,6 +321,7 @@ power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 102 2>; clock-names = "fck"; + status = "disabled"; }; main_i2c1: i2c@20010000 { @@ -325,6 +333,7 @@ power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 103 2>; clock-names = "fck"; + status = "disabled"; }; main_i2c2: i2c@20020000 { @@ -336,6 +345,7 @@ power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 104 2>; clock-names = "fck"; + status = "disabled"; }; main_i2c3: i2c@20030000 { @@ -347,6 +357,7 @@ power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 105 2>; clock-names = "fck"; + status = "disabled"; }; main_spi0: spi@20100000 { @@ -359,6 +370,7 @@ clocks = <&k3_clks 141 0>; dmas = <&main_pktdma 0xc300 0>, <&main_pktdma 0x4300 0>; dma-names = "tx0", "rx0"; + status = "disabled"; }; main_spi1: spi@20110000 { @@ -369,6 +381,7 @@ #size-cells = <0>; power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 142 0>; + status = "disabled"; }; main_spi2: spi@20120000 { @@ -379,6 +392,7 @@ #size-cells = <0>; power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 143 0>; + status = "disabled"; }; main_spi3: spi@20130000 { @@ -389,6 +403,7 @@ #size-cells = <0>; power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 144 0>; + status = "disabled"; }; main_spi4: spi@20140000 { @@ -399,6 +414,7 @@ #size-cells = <0>; power-domains = <&k3_pds 145 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 145 0>; + status = "disabled"; }; main_gpio_intr: interrupt-controller@a00000 { @@ -536,6 +552,7 @@ clocks = <&k3_clks 13 0>; clock-names = "fck"; bus_freq = <1000000>; + status = "disabled"; }; cpts@3d000 { @@ -612,7 +629,7 @@ assigned-clocks = <&k3_clks 0 0>; assigned-clock-parents = <&k3_clks 0 3>; assigned-clock-rates = <60000000>; - clock-names = "adc_tsc_fck"; + clock-names = "fck"; adc { #io-channel-cells = <1>; @@ -855,6 +872,7 @@ ranges = <0x01000000 0x00 0x68001000 0x00 0x68001000 0x00 0x0010000>, <0x02000000 0x00 0x68011000 0x00 0x68011000 0x00 0x7fef000>; dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x00000010 0x0>; + status = "disabled"; }; pcie0_ep: pcie-ep@f102000 { @@ -873,6 +891,7 @@ clocks = <&k3_clks 114 0>; clock-names = "fck"; max-functions = /bits/ 8 <1>; + status = "disabled"; }; epwm0: pwm@23000000 { @@ -882,6 +901,7 @@ power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>; clock-names = "tbclk", "fck"; + status = "disabled"; }; epwm1: pwm@23010000 { @@ -891,6 +911,7 @@ power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>; clock-names = "tbclk", "fck"; + status = "disabled"; }; epwm2: pwm@23020000 { @@ -900,6 +921,7 @@ power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>; clock-names = "tbclk", "fck"; + status = "disabled"; }; epwm3: pwm@23030000 { @@ -909,6 +931,7 @@ power-domains = <&k3_pds 89 TI_SCI_PD_EXCLUSIVE>; clocks = <&epwm_tbclk 3>, <&k3_clks 89 0>; clock-names = "tbclk", "fck"; + status = "disabled"; }; epwm4: pwm@23040000 { @@ -918,6 +941,7 @@ power-domains = <&k3_pds 90 TI_SCI_PD_EXCLUSIVE>; clocks = <&epwm_tbclk 4>, <&k3_clks 90 0>; clock-names = "tbclk", "fck"; + status = "disabled"; }; epwm5: pwm@23050000 { @@ -927,6 +951,7 @@ power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; clocks = <&epwm_tbclk 5>, <&k3_clks 91 0>; clock-names = "tbclk", "fck"; + status = "disabled"; }; epwm6: pwm@23060000 { @@ -936,6 +961,7 @@ power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; clocks = <&epwm_tbclk 6>, <&k3_clks 92 0>; clock-names = "tbclk", "fck"; + status = "disabled"; }; epwm7: pwm@23070000 { @@ -945,6 +971,7 @@ power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>; clocks = <&epwm_tbclk 7>, <&k3_clks 93 0>; clock-names = "tbclk", "fck"; + status = "disabled"; }; epwm8: pwm@23080000 { @@ -954,6 +981,7 @@ power-domains = <&k3_pds 94 TI_SCI_PD_EXCLUSIVE>; clocks = <&epwm_tbclk 8>, <&k3_clks 94 0>; clock-names = "tbclk", "fck"; + status = "disabled"; }; ecap0: pwm@23100000 { @@ -963,6 +991,7 @@ power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 51 0>; clock-names = "fck"; + status = "disabled"; }; ecap1: pwm@23110000 { @@ -972,6 +1001,7 @@ power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 52 0>; clock-names = "fck"; + status = "disabled"; }; ecap2: pwm@23120000 { @@ -981,6 +1011,7 @@ power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 53 0>; clock-names = "fck"; + status = "disabled"; }; main_rti0: watchdog@e000000 { @@ -1138,6 +1169,7 @@ #address-cells = <1>; #size-cells = <0>; bus_freq = <1000000>; + status = "disabled"; }; }; @@ -1278,6 +1310,7 @@ clocks = <&k3_clks 82 0>; clock-names = "fck"; bus_freq = <1000000>; + status = "disabled"; }; }; @@ -1293,6 +1326,7 @@ <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan1: can@20711000 { @@ -1307,6 +1341,7 @@ <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; crypto: crypto@40900000 { @@ -1324,7 +1359,6 @@ compatible = "inside-secure,safexcel-eip76"; reg = <0x00 0x40910000 0x00 0x7d>; interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 133 1>; status = "disabled"; /* Used by OP-TEE */ }; }; @@ -1334,8 +1368,8 @@ power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 80 0>; clock-names = "fck"; - reg = <0x00 0x03b000000 0x00 0x400>, - <0x00 0x050000000 0x00 0x8000000>; + reg = <0x00 0x3b000000 0x00 0x400>, + <0x00 0x50000000 0x00 0x8000000>; reg-names = "cfg", "data"; interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; gpmc,num-cs = <3>; @@ -1346,6 +1380,7 @@ #interrupt-cells = <2>; gpio-controller; #gpio-cells = <2>; + status = "disabled"; }; elm0: ecc@25010000 { @@ -1355,5 +1390,6 @@ power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 54 0>; clock-names = "fck"; + status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi index 02d4285acbb8..38ddf0b3b8a0 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi @@ -14,6 +14,7 @@ power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 149 0>; clock-names = "fclk"; + status = "disabled"; }; mcu_uart1: serial@4a10000 { @@ -24,6 +25,7 @@ power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 160 0>; clock-names = "fclk"; + status = "disabled"; }; mcu_i2c0: i2c@4900000 { @@ -35,6 +37,7 @@ power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 106 2>; clock-names = "fck"; + status = "disabled"; }; mcu_i2c1: i2c@4910000 { @@ -46,6 +49,7 @@ power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 107 2>; clock-names = "fck"; + status = "disabled"; }; mcu_spi0: spi@4b00000 { @@ -56,6 +60,7 @@ #size-cells = <0>; power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 147 0>; + status = "disabled"; }; mcu_spi1: spi@4b10000 { @@ -66,6 +71,7 @@ #size-cells = <0>; power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 148 0>; + status = "disabled"; }; mcu_gpio_intr: interrupt-controller@4210000 { diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index 5cf913860f80..39feea78a084 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -325,6 +325,7 @@ }; &main_uart0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_uart0_pins_default>; }; @@ -334,35 +335,8 @@ status = "reserved"; }; -&main_uart2 { - status = "disabled"; -}; - -&main_uart3 { - status = "disabled"; -}; - -&main_uart4 { - status = "disabled"; -}; - -&main_uart5 { - status = "disabled"; -}; - -&main_uart6 { - status = "disabled"; -}; - -&mcu_uart0 { - status = "disabled"; -}; - -&mcu_uart1 { - status = "disabled"; -}; - &main_i2c1 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c1_pins_default>; clock-frequency = <400000>; @@ -405,23 +379,8 @@ status = "reserved"; }; -&mcu_i2c0 { - status = "disabled"; -}; - -&mcu_i2c1 { - status = "disabled"; -}; - -&mcu_spi0 { - status = "disabled"; -}; - -&mcu_spi1 { - status = "disabled"; -}; - &main_spi0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_spi0_pins_default>; ti,pindir-d0-out-d1-in; @@ -466,8 +425,7 @@ &cpsw3g { pinctrl-names = "default"; - pinctrl-0 = <&mdio1_pins_default - &rgmii1_pins_default + pinctrl-0 = <&rgmii1_pins_default &rgmii2_pins_default>; }; @@ -482,6 +440,10 @@ }; &cpsw3g_mdio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mdio1_pins_default>; + cpsw3g_phy0: ethernet-phy@0 { reg = <0>; ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; @@ -594,6 +556,7 @@ }; &pcie0_rc { + status = "okay"; reset-gpios = <&exp1 5 GPIO_ACTIVE_HIGH>; phys = <&serdes0_pcie_link>; phy-names = "pcie-phy"; @@ -604,83 +567,25 @@ phys = <&serdes0_pcie_link>; phy-names = "pcie-phy"; num-lanes = <1>; - status = "disabled"; }; &ecap0 { + status = "okay"; /* PWM is available on Pin 1 of header J12 */ pinctrl-names = "default"; pinctrl-0 = <&main_ecap0_pins_default>; }; -&ecap1 { - status = "disabled"; -}; - -&ecap2 { - status = "disabled"; -}; - -&epwm0 { - status = "disabled"; -}; - -&epwm1 { - status = "disabled"; -}; - -&epwm2 { - status = "disabled"; -}; - -&epwm3 { - status = "disabled"; -}; - -&epwm4 { - status = "disabled"; -}; - -&epwm5 { - status = "disabled"; -}; - -&epwm6 { - status = "disabled"; -}; - -&epwm7 { - status = "disabled"; -}; - -&epwm8 { - status = "disabled"; -}; - -&icssg0_mdio { - status = "disabled"; -}; - -&icssg1_mdio { - status = "disabled"; -}; - &main_mcan0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_mcan0_pins_default>; phys = <&transceiver1>; }; &main_mcan1 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_mcan1_pins_default>; phys = <&transceiver2>; }; - -&gpmc0 { - status = "disabled"; -}; - -&elm0 { - status = "disabled"; -}; diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index 738d0cf6c40a..2e2d40da360a 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -338,15 +338,8 @@ }; }; -&mcu_uart0 { - status = "disabled"; -}; - -&mcu_uart1 { - status = "disabled"; -}; - &main_uart0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_uart0_pins_default>; }; @@ -356,35 +349,8 @@ status = "reserved"; }; -&main_uart2 { - status = "disabled"; -}; - -&main_uart3 { - status = "disabled"; -}; - -&main_uart4 { - status = "disabled"; -}; - -&main_uart5 { - status = "disabled"; -}; - -&main_uart6 { - status = "disabled"; -}; - -&mcu_i2c0 { - status = "disabled"; -}; - -&mcu_i2c1 { - status = "disabled"; -}; - &main_i2c1 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c1_pins_default>; clock-frequency = <400000>; @@ -409,18 +375,6 @@ }; }; -&main_i2c3 { - status = "disabled"; -}; - -&mcu_spi0 { - status = "disabled"; -}; - -&mcu_spi1 { - status = "disabled"; -}; - /* mcu_gpio0 is reserved for mcu firmware usage */ &mcu_gpio0 { status = "reserved"; @@ -485,8 +439,7 @@ &cpsw3g { pinctrl-names = "default"; - pinctrl-0 = <&mdio1_pins_default - &rgmii1_pins_default + pinctrl-0 = <&rgmii1_pins_default &rgmii2_pins_default>; }; @@ -501,6 +454,10 @@ }; &cpsw3g_mdio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mdio1_pins_default>; + cpsw3g_phy0: ethernet-phy@0 { reg = <0>; ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; @@ -603,92 +560,9 @@ <&main_r5fss1_core1_memory_region>; }; -&pcie0_rc { - status = "disabled"; -}; - -&pcie0_ep { - status = "disabled"; -}; - &ecap0 { + status = "okay"; /* PWM is available on Pin 1 of header J3 */ pinctrl-names = "default"; pinctrl-0 = <&main_ecap0_pins_default>; }; - -&ecap1 { - status = "disabled"; -}; - -&ecap2 { - status = "disabled"; -}; - -&epwm0 { - status = "disabled"; -}; - -&epwm1 { - status = "disabled"; -}; - -&epwm2 { - status = "disabled"; -}; - -&epwm3 { - status = "disabled"; -}; - -&epwm4 { - /* - * EPWM4_A, EPWM4_B is available on Pin 32 and 33 on J4 (RPi hat) - * But RPi Hat will be used for other use cases, so marking epwm4 as disabled. - */ - status = "disabled"; -}; - -&epwm5 { - /* - * EPWM5_A, EPWM5_B is available on Pin 29 and 31 on J4 (RPi hat) - * But RPi Hat will be used for other use cases, so marking epwm5 as disabled. - */ - status = "disabled"; -}; - -&epwm6 { - status = "disabled"; -}; - -&epwm7 { - status = "disabled"; -}; - -&epwm8 { - status = "disabled"; -}; - -&icssg0_mdio { - status = "disabled"; -}; - -&icssg1_mdio { - status = "disabled"; -}; - -&main_mcan0 { - status = "disabled"; -}; - -&main_mcan1 { - status = "disabled"; -}; - -&gpmc0 { - status = "disabled"; -}; - -&elm0 { - status = "disabled"; -}; diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi index 32b797237581..3cced26b520a 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi @@ -360,15 +360,13 @@ }; &main_uart1 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_uart1_pins_default>; }; -&main_uart2 { - status = "disabled"; -}; - &mcu_uart0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&arduino_uart_pins_default>; }; @@ -413,12 +411,14 @@ }; &wkup_i2c0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&wkup_i2c0_pins_default>; clock-frequency = <400000>; }; &mcu_i2c0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcu_i2c0_pins_default>; clock-frequency = <400000>; @@ -478,6 +478,7 @@ }; &main_i2c0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c0_pins_default>; clock-frequency = <400000>; @@ -495,18 +496,21 @@ }; &main_i2c1 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c1_pins_default>; clock-frequency = <400000>; }; &main_i2c2 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c2_pins_default>; clock-frequency = <400000>; }; &main_i2c3 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c3_pins_default>; clock-frequency = <400000>; @@ -546,6 +550,7 @@ }; &ecap0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&ecap0_pins_default>; }; @@ -570,6 +575,7 @@ }; &mcu_spi0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcu_spi0_pins_default>; @@ -626,15 +632,8 @@ }; }; -&pcie0_rc { - status = "disabled"; -}; - -&pcie0_ep { - status = "disabled"; -}; - &pcie1_rc { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&minipcie_pins_default>; @@ -644,19 +643,8 @@ reset-gpios = <&wkup_gpio0 27 GPIO_ACTIVE_HIGH>; }; -&m_can0 { - status = "disabled"; -}; - -&m_can1 { - status = "disabled"; -}; - -&pcie1_ep { - status = "disabled"; -}; - &mailbox0_cluster0 { + status = "okay"; interrupts = <436>; mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { @@ -666,6 +654,7 @@ }; &mailbox0_cluster1 { + status = "okay"; interrupts = <432>; mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { @@ -674,46 +663,6 @@ }; }; -&mailbox0_cluster2 { - status = "disabled"; -}; - -&mailbox0_cluster3 { - status = "disabled"; -}; - -&mailbox0_cluster4 { - status = "disabled"; -}; - -&mailbox0_cluster5 { - status = "disabled"; -}; - -&mailbox0_cluster6 { - status = "disabled"; -}; - -&mailbox0_cluster7 { - status = "disabled"; -}; - -&mailbox0_cluster8 { - status = "disabled"; -}; - -&mailbox0_cluster9 { - status = "disabled"; -}; - -&mailbox0_cluster10 { - status = "disabled"; -}; - -&mailbox0_cluster11 { - status = "disabled"; -}; - &mcu_r5fss0_core0 { memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; @@ -725,27 +674,3 @@ <&mcu_r5fss0_core1_memory_region>; mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>; }; - -&icssg0_mdio { - status = "disabled"; -}; - -&icssg1_mdio { - status = "disabled"; -}; - -&icssg2_mdio { - status = "disabled"; -}; - -&mcasp0 { - status = "disabled"; -}; - -&mcasp1 { - status = "disabled"; -}; - -&mcasp2 { - status = "disabled"; -}; diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index 4005a73cfea9..1adba2f2c153 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -91,6 +91,7 @@ clock-frequency = <48000000>; current-speed = <115200>; power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_uart1: serial@2810000 { @@ -99,6 +100,7 @@ interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_uart2: serial@2820000 { @@ -107,6 +109,7 @@ interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; crypto: crypto@4e00000 { @@ -120,17 +123,33 @@ dmas = <&main_udmap 0xc001>, <&main_udmap 0x4002>, <&main_udmap 0x4003>; dma-names = "tx", "rx1", "rx2"; - dma-coherent; rng: rng@4e10000 { compatible = "inside-secure,safexcel-eip76"; reg = <0x0 0x4e10000 0x0 0x7d>; interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 136 1>; status = "disabled"; /* Used by OP-TEE */ }; }; + /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */ + main_timerio_input: pinctrl@104200 { + compatible = "pinctrl-single"; + reg = <0x0 0x104200 0x0 0x30>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000001ff>; + }; + + /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */ + main_timerio_output: pinctrl@104280 { + compatible = "pinctrl-single"; + reg = <0x0 0x104280 0x0 0x20>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000000f>; + }; + main_pmx0: pinctrl@11c000 { compatible = "pinctrl-single"; reg = <0x0 0x11c000 0x0 0x2e4>; @@ -156,6 +175,7 @@ clock-names = "fck"; clocks = <&k3_clks 110 1>; power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_i2c1: i2c@2010000 { @@ -167,6 +187,7 @@ clock-names = "fck"; clocks = <&k3_clks 111 1>; power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_i2c2: i2c@2020000 { @@ -178,6 +199,7 @@ clock-names = "fck"; clocks = <&k3_clks 112 1>; power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_i2c3: i2c@2030000 { @@ -189,6 +211,7 @@ clock-names = "fck"; clocks = <&k3_clks 113 1>; power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; ecap0: pwm@3100000 { @@ -198,6 +221,7 @@ power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 39 0>; clock-names = "fck"; + status = "disabled"; }; main_spi0: spi@2100000 { @@ -210,6 +234,7 @@ #size-cells = <0>; dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>; dma-names = "tx0", "rx0"; + status = "disabled"; }; main_spi1: spi@2110000 { @@ -222,6 +247,7 @@ #size-cells = <0>; assigned-clocks = <&k3_clks 137 1>; assigned-clock-rates = <48000000>; + status = "disabled"; }; main_spi2: spi@2120000 { @@ -232,6 +258,7 @@ power-domains = <&k3_pds 139 TI_SCI_PD_EXCLUSIVE>; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; main_spi3: spi@2130000 { @@ -242,6 +269,7 @@ power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; main_spi4: spi@2140000 { @@ -252,6 +280,151 @@ power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; + }; + + main_timer0: timer@2400000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2400000 0x00 0x400>; + interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 23 0>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 23 0>; + assigned-clock-parents = <&k3_clks 23 1>; + power-domains = <&k3_pds 23 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer1: timer@2410000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2410000 0x00 0x400>; + interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 24 0>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 24 0>; + assigned-clock-parents = <&k3_clks 24 1>; + power-domains = <&k3_pds 24 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer2: timer@2420000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2420000 0x00 0x400>; + interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 27 0>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 27 0>; + assigned-clock-parents = <&k3_clks 27 1>; + power-domains = <&k3_pds 27 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer3: timer@2430000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2430000 0x00 0x400>; + interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 28 0>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 28 0>; + assigned-clock-parents = <&k3_clks 28 1>; + power-domains = <&k3_pds 28 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer4: timer@2440000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2440000 0x00 0x400>; + interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 29 0>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 29 0>; + assigned-clock-parents = <&k3_clks 29 1>; + power-domains = <&k3_pds 29 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer5: timer@2450000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2450000 0x00 0x400>; + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 30 0>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 30 0>; + assigned-clock-parents = <&k3_clks 30 1>; + power-domains = <&k3_pds 30 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer6: timer@2460000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2460000 0x00 0x400>; + interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 31 0>; + assigned-clocks = <&k3_clks 31 0>; + assigned-clock-parents = <&k3_clks 31 1>; + clock-names = "fck"; + power-domains = <&k3_pds 31 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer7: timer@2470000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2470000 0x00 0x400>; + interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 32 0>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 32 0>; + assigned-clock-parents = <&k3_clks 32 1>; + power-domains = <&k3_pds 32 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer8: timer@2480000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2480000 0x00 0x400>; + interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 33 0>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 33 0>; + assigned-clock-parents = <&k3_clks 33 1>; + power-domains = <&k3_pds 33 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer9: timer@2490000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2490000 0x00 0x400>; + interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 34 0>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 34 0>; + assigned-clock-parents = <&k3_clks 34 1>; + power-domains = <&k3_pds 34 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer10: timer@24a0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24a0000 0x00 0x400>; + interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 25 0>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 25 0>; + assigned-clock-parents = <&k3_clks 25 1>; + power-domains = <&k3_pds 25 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer11: timer@24b0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24b0000 0x00 0x400>; + interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 26 0>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 26 0>; + assigned-clock-parents = <&k3_clks 26 1>; + power-domains = <&k3_pds 26 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; }; sdhci0: mmc@4f80000 { @@ -342,7 +515,7 @@ dss_oldi_io_ctrl: dss-oldi-io-ctrl@41e0 { compatible = "syscon"; - reg = <0x0000041e0 0x14>; + reg = <0x000041e0 0x14>; }; ehrpwm_tbclk: clock@4140 { @@ -501,6 +674,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&intr_main_navss>; + status = "disabled"; }; mailbox0_cluster1: mailbox@31f81000 { @@ -510,6 +684,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&intr_main_navss>; + status = "disabled"; }; mailbox0_cluster2: mailbox@31f82000 { @@ -519,6 +694,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&intr_main_navss>; + status = "disabled"; }; mailbox0_cluster3: mailbox@31f83000 { @@ -528,6 +704,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&intr_main_navss>; + status = "disabled"; }; mailbox0_cluster4: mailbox@31f84000 { @@ -537,6 +714,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&intr_main_navss>; + status = "disabled"; }; mailbox0_cluster5: mailbox@31f85000 { @@ -546,6 +724,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&intr_main_navss>; + status = "disabled"; }; mailbox0_cluster6: mailbox@31f86000 { @@ -555,6 +734,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&intr_main_navss>; + status = "disabled"; }; mailbox0_cluster7: mailbox@31f87000 { @@ -564,6 +744,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&intr_main_navss>; + status = "disabled"; }; mailbox0_cluster8: mailbox@31f88000 { @@ -573,6 +754,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&intr_main_navss>; + status = "disabled"; }; mailbox0_cluster9: mailbox@31f89000 { @@ -582,6 +764,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&intr_main_navss>; + status = "disabled"; }; mailbox0_cluster10: mailbox@31f8a000 { @@ -591,6 +774,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&intr_main_navss>; + status = "disabled"; }; mailbox0_cluster11: mailbox@31f8b000 { @@ -600,6 +784,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&intr_main_navss>; + status = "disabled"; }; ringacc: ringacc@3c000000 { @@ -707,6 +892,7 @@ interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>; msi-map = <0x0 &gic_its 0x0 0x10000>; device_type = "pci"; + status = "disabled"; }; pcie0_ep: pcie-ep@5500000 { @@ -720,6 +906,7 @@ max-link-speed = <2>; dma-coherent; interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; }; pcie1_rc: pcie@5600000 { @@ -740,6 +927,7 @@ interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>; msi-map = <0x0 &gic_its 0x10000 0x10000>; device_type = "pci"; + status = "disabled"; }; pcie1_ep: pcie-ep@5600000 { @@ -753,6 +941,7 @@ max-link-speed = <2>; dma-coherent; interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; }; mcasp0: mcasp@2b00000 { @@ -770,6 +959,7 @@ clocks = <&k3_clks 104 0>; clock-names = "fck"; power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; mcasp1: mcasp@2b10000 { @@ -787,6 +977,7 @@ clocks = <&k3_clks 105 0>; clock-names = "fck"; power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; mcasp2: mcasp@2b20000 { @@ -804,6 +995,7 @@ clocks = <&k3_clks 106 0>; clock-names = "fck"; power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; cal: cal@6f03000 { @@ -874,6 +1066,7 @@ power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>; clocks = <&ehrpwm_tbclk 0>, <&k3_clks 40 0>; clock-names = "tbclk", "fck"; + status = "disabled"; }; ehrpwm1: pwm@3010000 { @@ -883,6 +1076,7 @@ power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>; clocks = <&ehrpwm_tbclk 1>, <&k3_clks 41 0>; clock-names = "tbclk", "fck"; + status = "disabled"; }; ehrpwm2: pwm@3020000 { @@ -892,6 +1086,7 @@ power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>; clocks = <&ehrpwm_tbclk 2>, <&k3_clks 42 0>; clock-names = "tbclk", "fck"; + status = "disabled"; }; ehrpwm3: pwm@3030000 { @@ -901,6 +1096,7 @@ power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>; clocks = <&ehrpwm_tbclk 3>, <&k3_clks 43 0>; clock-names = "tbclk", "fck"; + status = "disabled"; }; ehrpwm4: pwm@3040000 { @@ -910,6 +1106,7 @@ power-domains = <&k3_pds 44 TI_SCI_PD_EXCLUSIVE>; clocks = <&ehrpwm_tbclk 4>, <&k3_clks 44 0>; clock-names = "tbclk", "fck"; + status = "disabled"; }; ehrpwm5: pwm@3050000 { @@ -919,6 +1116,7 @@ power-domains = <&k3_pds 45 TI_SCI_PD_EXCLUSIVE>; clocks = <&ehrpwm_tbclk 5>, <&k3_clks 45 0>; clock-names = "tbclk", "fck"; + status = "disabled"; }; icssg0: icssg@b000000 { @@ -1059,6 +1257,7 @@ #address-cells = <1>; #size-cells = <0>; bus_freq = <1000000>; + status = "disabled"; }; }; @@ -1200,6 +1399,7 @@ #address-cells = <1>; #size-cells = <0>; bus_freq = <1000000>; + status = "disabled"; }; }; @@ -1341,6 +1541,7 @@ #address-cells = <1>; #size-cells = <0>; bus_freq = <1000000>; + status = "disabled"; }; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi index 8d592bf41d6f..5dfa31840e9c 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi @@ -20,13 +20,32 @@ }; }; + /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */ + mcu_timerio_input: pinctrl@40f04200 { + compatible = "pinctrl-single"; + reg = <0x0 0x40f04200 0x0 0x10>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x00000101>; + }; + + /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */ + mcu_timerio_output: pinctrl@40f04280 { + compatible = "pinctrl-single"; + reg = <0x0 0x40f04280 0x0 0x8>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x00000003>; + }; + mcu_uart0: serial@40a00000 { compatible = "ti,am654-uart"; - reg = <0x00 0x40a00000 0x00 0x100>; - interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <96000000>; - current-speed = <115200>; - power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; + reg = <0x00 0x40a00000 0x00 0x100>; + interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <96000000>; + current-speed = <115200>; + power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; mcu_ram: sram@41c00000 { @@ -46,6 +65,7 @@ clock-names = "fck"; clocks = <&k3_clks 114 1>; power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; mcu_spi0: spi@40300000 { @@ -56,6 +76,7 @@ power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; mcu_spi1: spi@40310000 { @@ -66,6 +87,7 @@ power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; mcu_spi2: spi@40320000 { @@ -76,6 +98,7 @@ power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; tscadc0: tscadc@40200000 { @@ -85,7 +108,7 @@ clocks = <&k3_clks 0 2>; assigned-clocks = <&k3_clks 0 2>; assigned-clock-rates = <60000000>; - clock-names = "adc_tsc_fck"; + clock-names = "fck"; dmas = <&mcu_udmap 0x7100>, <&mcu_udmap 0x7101 >; dma-names = "fifo0", "fifo1"; @@ -103,7 +126,7 @@ clocks = <&k3_clks 1 2>; assigned-clocks = <&k3_clks 1 2>; assigned-clock-rates = <60000000>; - clock-names = "adc_tsc_fck"; + clock-names = "fck"; dmas = <&mcu_udmap 0x7102>, <&mcu_udmap 0x7103>; dma-names = "fifo0", "fifo1"; @@ -114,6 +137,51 @@ }; }; + /* + * The MCU domain timer interrupts are routed only to the ESM module, + * and not currently available for Linux. The MCU domain timers are + * of limited use without interrupts, and likely reserved by the ESM. + */ + mcu_timer0: timer@40400000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40400000 0x00 0x400>; + clocks = <&k3_clks 35 0>; + clock-names = "fck"; + power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + status = "reserved"; + }; + + mcu_timer1: timer@40410000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40410000 0x00 0x400>; + clocks = <&k3_clks 36 0>; + clock-names = "fck"; + power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + status = "reserved"; + }; + + mcu_timer2: timer@40420000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40420000 0x00 0x400>; + clocks = <&k3_clks 37 0>; + clock-names = "fck"; + power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + status = "reserved"; + }; + + mcu_timer3: timer@40430000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40430000 0x00 0x400>; + clocks = <&k3_clks 38 0>; + clock-names = "fck"; + power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + status = "reserved"; + }; + mcu_navss: bus@28380000 { compatible = "simple-mfd"; #address-cells = <2>; @@ -172,6 +240,7 @@ <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; m_can1: mcan@40568000 { @@ -187,6 +256,7 @@ <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; fss: fss@47000000 { @@ -273,6 +343,7 @@ clocks = <&k3_clks 5 10>; clock-names = "fck"; bus_freq = <1000000>; + status = "disabled"; }; cpts@3d000 { diff --git a/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi index fa11d7142006..fd2b998ebddc 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi @@ -54,6 +54,7 @@ clock-frequency = <48000000>; current-speed = <115200>; power-domains = <&k3_pds 150 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; wkup_i2c0: i2c@42120000 { @@ -65,6 +66,7 @@ clock-names = "fck"; clocks = <&k3_clks 115 1>; power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; intr_wkup_gpio: interrupt-controller@42200000 { diff --git a/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic-common.dtsi b/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic-common.dtsi index 4a9bf7d7c07d..cd43fd11a5c2 100644 --- a/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic-common.dtsi @@ -50,6 +50,7 @@ }; &main_uart0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_uart0_pins_default>; }; diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index 5850582dd4ed..592ab2b54cb3 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -271,13 +271,20 @@ status = "reserved"; }; +&mcu_uart0 { + status = "okay"; + /* Default pinmux */ +}; + &main_uart0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_uart0_pins_default>; power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; }; &wkup_i2c0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&wkup_i2c0_pins_default>; clock-frequency = <400000>; @@ -296,7 +303,13 @@ }; }; +&mcu_i2c0 { + status = "okay"; + /* Default pinmux */ +}; + &main_i2c0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c0_pins_default>; clock-frequency = <400000>; @@ -310,23 +323,27 @@ }; &main_i2c1 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c1_pins_default>; clock-frequency = <400000>; }; &main_i2c2 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c2_pins_default>; clock-frequency = <400000>; }; &ecap0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&ecap0_pins_default>; }; &main_spi0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_spi0_pins_default>; #address-cells = <1>; @@ -398,31 +415,8 @@ status = "disabled"; }; -&pcie0_rc { - status = "disabled"; -}; - -&pcie0_ep { - status = "disabled"; -}; - -&pcie1_rc { - status = "disabled"; -}; - -&pcie1_ep { - status = "disabled"; -}; - -&m_can0 { - status = "disabled"; -}; - -&m_can1 { - status = "disabled"; -}; - &mailbox0_cluster0 { + status = "okay"; interrupts = <436>; mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { @@ -432,6 +426,7 @@ }; &mailbox0_cluster1 { + status = "okay"; interrupts = <432>; mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { @@ -440,46 +435,6 @@ }; }; -&mailbox0_cluster2 { - status = "disabled"; -}; - -&mailbox0_cluster3 { - status = "disabled"; -}; - -&mailbox0_cluster4 { - status = "disabled"; -}; - -&mailbox0_cluster5 { - status = "disabled"; -}; - -&mailbox0_cluster6 { - status = "disabled"; -}; - -&mailbox0_cluster7 { - status = "disabled"; -}; - -&mailbox0_cluster8 { - status = "disabled"; -}; - -&mailbox0_cluster9 { - status = "disabled"; -}; - -&mailbox0_cluster10 { - status = "disabled"; -}; - -&mailbox0_cluster11 { - status = "disabled"; -}; - &mcu_r5fss0_core0 { memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; @@ -512,10 +467,14 @@ &mcu_cpsw { pinctrl-names = "default"; - pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; + pinctrl-0 = <&mcu_cpsw_pins_default>; }; &davinci_mdio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mdio_pins_default>; + phy0: ethernet-phy@0 { reg = <0>; ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; @@ -528,30 +487,6 @@ phy-handle = <&phy0>; }; -&mcasp0 { - status = "disabled"; -}; - -&mcasp1 { - status = "disabled"; -}; - -&mcasp2 { - status = "disabled"; -}; - &dss { status = "disabled"; }; - -&icssg0_mdio { - status = "disabled"; -}; - -&icssg1_mdio { - status = "disabled"; -}; - -&icssg2_mdio { - status = "disabled"; -}; diff --git a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-common.dtsi b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-common.dtsi index d25e8b26187f..0f67e1ec0fb8 100644 --- a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-common.dtsi @@ -50,7 +50,3 @@ ti,driver-strength-ohm = <50>; disable-wp; }; - -&main_uart0 { - status = "disabled"; -}; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts index 7e8552fd2b6a..6240856e4863 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -154,51 +154,27 @@ status = "reserved"; }; +&mcu_uart0 { + status = "okay"; + /* Default pinmux */ +}; + &main_uart0 { + status = "okay"; /* Shared with ATF on this platform */ power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; }; +&main_uart1 { + status = "okay"; + /* Default pinmux */ +}; + &main_uart2 { /* MAIN UART 2 is used by R5F firmware */ status = "reserved"; }; -&main_uart3 { - /* UART not brought out */ - status = "disabled"; -}; - -&main_uart4 { - /* UART not brought out */ - status = "disabled"; -}; - -&main_uart5 { - /* UART not brought out */ - status = "disabled"; -}; - -&main_uart6 { - /* UART not brought out */ - status = "disabled"; -}; - -&main_uart7 { - /* UART not brought out */ - status = "disabled"; -}; - -&main_uart8 { - /* UART not brought out */ - status = "disabled"; -}; - -&main_uart9 { - /* UART not brought out */ - status = "disabled"; -}; - &main_gpio2 { status = "disabled"; }; @@ -234,6 +210,7 @@ }; &main_i2c0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c0_pins_default>; clock-frequency = <400000>; @@ -261,6 +238,7 @@ * The i2c1 of the CPB (as it is labeled) is not connected to j7200. */ &main_i2c1 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c1_pins_default>; clock-frequency = <400000>; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index 80a57916bcb3..138381f43ce4 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -142,6 +142,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster1: mailbox@31f81000 { @@ -151,6 +152,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster2: mailbox@31f82000 { @@ -160,6 +162,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster3: mailbox@31f83000 { @@ -169,6 +172,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster4: mailbox@31f84000 { @@ -178,6 +182,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster5: mailbox@31f85000 { @@ -187,6 +192,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster6: mailbox@31f86000 { @@ -196,6 +202,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster7: mailbox@31f87000 { @@ -205,6 +212,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster8: mailbox@31f88000 { @@ -214,6 +222,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster9: mailbox@31f89000 { @@ -223,6 +232,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster10: mailbox@31f8a000 { @@ -232,6 +242,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster11: mailbox@31f8b000 { @@ -241,6 +252,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; main_ringacc: ringacc@3c000000 { @@ -319,6 +331,7 @@ power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 146 2>; clock-names = "fclk"; + status = "disabled"; }; main_uart1: serial@2810000 { @@ -330,6 +343,7 @@ power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 278 2>; clock-names = "fclk"; + status = "disabled"; }; main_uart2: serial@2820000 { @@ -341,6 +355,7 @@ power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 279 2>; clock-names = "fclk"; + status = "disabled"; }; main_uart3: serial@2830000 { @@ -352,6 +367,7 @@ power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 280 2>; clock-names = "fclk"; + status = "disabled"; }; main_uart4: serial@2840000 { @@ -363,6 +379,7 @@ power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 281 2>; clock-names = "fclk"; + status = "disabled"; }; main_uart5: serial@2850000 { @@ -374,6 +391,7 @@ power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 282 2>; clock-names = "fclk"; + status = "disabled"; }; main_uart6: serial@2860000 { @@ -385,6 +403,7 @@ power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 283 2>; clock-names = "fclk"; + status = "disabled"; }; main_uart7: serial@2870000 { @@ -396,6 +415,7 @@ power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 284 2>; clock-names = "fclk"; + status = "disabled"; }; main_uart8: serial@2880000 { @@ -407,6 +427,7 @@ power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 285 2>; clock-names = "fclk"; + status = "disabled"; }; main_uart9: serial@2890000 { @@ -418,6 +439,7 @@ power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 286 2>; clock-names = "fclk"; + status = "disabled"; }; main_i2c0: i2c@2000000 { @@ -429,6 +451,7 @@ clock-names = "fck"; clocks = <&k3_clks 187 1>; power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>; + status = "disabled"; }; main_i2c1: i2c@2010000 { @@ -440,6 +463,7 @@ clock-names = "fck"; clocks = <&k3_clks 188 1>; power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_i2c2: i2c@2020000 { @@ -451,6 +475,7 @@ clock-names = "fck"; clocks = <&k3_clks 189 1>; power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_i2c3: i2c@2030000 { @@ -462,6 +487,7 @@ clock-names = "fck"; clocks = <&k3_clks 190 1>; power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_i2c4: i2c@2040000 { @@ -473,6 +499,7 @@ clock-names = "fck"; clocks = <&k3_clks 191 1>; power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_i2c5: i2c@2050000 { @@ -484,6 +511,7 @@ clock-names = "fck"; clocks = <&k3_clks 192 1>; power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_i2c6: i2c@2060000 { @@ -495,6 +523,7 @@ clock-names = "fck"; clocks = <&k3_clks 193 1>; power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_sdhci0: mmc@4f80000 { diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi index e5be78a58682..fe669deba489 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -79,6 +79,7 @@ power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 287 2>; clock-names = "fclk"; + status = "disabled"; }; mcu_uart0: serial@40a00000 { @@ -90,6 +91,7 @@ power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 149 2>; clock-names = "fclk"; + status = "disabled"; }; wkup_gpio_intr: interrupt-controller@42200000 { @@ -249,6 +251,7 @@ clock-names = "fck"; clocks = <&k3_clks 194 1>; power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; mcu_i2c1: i2c@40b10000 { @@ -260,6 +263,7 @@ clock-names = "fck"; clocks = <&k3_clks 195 1>; power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; wkup_i2c0: i2c@42120000 { @@ -271,6 +275,7 @@ clock-names = "fck"; clocks = <&k3_clks 197 1>; power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>; + status = "disabled"; }; fss: syscon@47000000 { @@ -325,7 +330,7 @@ clocks = <&k3_clks 0 1>; assigned-clocks = <&k3_clks 0 3>; assigned-clock-rates = <60000000>; - clock-names = "adc_tsc_fck"; + clock-names = "fck"; dmas = <&main_udmap 0x7400>, <&main_udmap 0x7401>; dma-names = "fifo0", "fifo1"; @@ -386,7 +391,6 @@ dmas = <&mcu_udmap 0xf501>, <&mcu_udmap 0x7502>, <&mcu_udmap 0x7503>; dma-names = "tx", "rx1", "rx2"; - dma-coherent; rng: rng@40910000 { compatible = "inside-secure,safexcel-eip76"; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi index 2d615c3e9fa1..fa44ed4c17d5 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi @@ -144,6 +144,7 @@ }; &mailbox0_cluster0 { + status = "okay"; interrupts = <436>; mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { @@ -158,6 +159,7 @@ }; &mailbox0_cluster1 { + status = "okay"; interrupts = <432>; mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { @@ -171,46 +173,6 @@ }; }; -&mailbox0_cluster2 { - status = "disabled"; -}; - -&mailbox0_cluster3 { - status = "disabled"; -}; - -&mailbox0_cluster4 { - status = "disabled"; -}; - -&mailbox0_cluster5 { - status = "disabled"; -}; - -&mailbox0_cluster6 { - status = "disabled"; -}; - -&mailbox0_cluster7 { - status = "disabled"; -}; - -&mailbox0_cluster8 { - status = "disabled"; -}; - -&mailbox0_cluster9 { - status = "disabled"; -}; - -&mailbox0_cluster10 { - status = "disabled"; -}; - -&mailbox0_cluster11 { - status = "disabled"; -}; - &mcu_r5fss0_core0 { mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; memory-region = <&mcu_r5fss0_core0_dma_memory_region>, diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts new file mode 100644 index 000000000000..37c24b077b6a --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts @@ -0,0 +1,1055 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * https://beagleboard.org/ai-64 + * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022 Jason Kridner, BeagleBoard.org Foundation + * Copyright (C) 2022 Robert Nelson, BeagleBoard.org Foundation + */ + +/dts-v1/; + +#include "k3-j721e.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/net/ti-dp83867.h> +#include <dt-bindings/phy/phy-cadence.h> + +/ { + compatible = "beagle,j721e-beagleboneai64", "ti,j721e"; + model = "BeagleBoard.org BeagleBone AI-64"; + + aliases { + serial2 = &main_uart0; + mmc0 = &main_sdhci0; + mmc1 = &main_sdhci1; + i2c0 = &wkup_i2c0; + i2c1 = &main_i2c6; + i2c2 = &main_i2c2; + i2c3 = &main_i2c4; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + memory@80000000 { + device_type = "memory"; + /* 4G RAM */ + reg = <0x00000000 0x80000000 0x00000000 0x80000000>, + <0x00000008 0x80000000 0x00000000 0x80000000>; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; + no-map; + }; + + mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0100000 0x00 0xf00000>; + no-map; + }; + + mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core0_memory_region: r5f-memory@a2100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core1_memory_region: r5f-memory@a3100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core0_memory_region: r5f-memory@a4100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa5000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core1_memory_region: r5f-memory@a5100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa5100000 0x00 0xf00000>; + no-map; + }; + + c66_1_dma_memory_region: c66-dma-memory@a6000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa6000000 0x00 0x100000>; + no-map; + }; + + c66_0_memory_region: c66-memory@a6100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa6100000 0x00 0xf00000>; + no-map; + }; + + c66_0_dma_memory_region: c66-dma-memory@a7000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa7000000 0x00 0x100000>; + no-map; + }; + + c66_1_memory_region: c66-memory@a7100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa7100000 0x00 0xf00000>; + no-map; + }; + + c71_0_dma_memory_region: c71-dma-memory@a8000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa8000000 0x00 0x100000>; + no-map; + }; + + c71_0_memory_region: c71-memory@a8100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa8100000 0x00 0xf00000>; + no-map; + }; + + rtos_ipc_memory_region: ipc-memories@aa000000 { + reg = <0x00 0xaa000000 0x00 0x01c00000>; + alignment = <0x1000>; + no-map; + }; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&sw_pwr_pins_default>; + + button-1 { + label = "BOOT"; + linux,code = <BTN_0>; + gpios = <&wkup_gpio0 0 GPIO_ACTIVE_LOW>; + }; + + button-2 { + label = "POWER"; + linux,code = <KEY_POWER>; + gpios = <&wkup_gpio0 4 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_default>; + + led-0 { + gpios = <&main_gpio0 96 GPIO_ACTIVE_HIGH>; + function = LED_FUNCTION_HEARTBEAT; + linux,default-trigger = "heartbeat"; + }; + + led-1 { + gpios = <&main_gpio0 95 GPIO_ACTIVE_HIGH>; + function = LED_FUNCTION_DISK_ACTIVITY; + linux,default-trigger = "mmc0"; + }; + + led-2 { + gpios = <&main_gpio0 97 GPIO_ACTIVE_HIGH>; + function = LED_FUNCTION_CPU; + linux,default-trigger = "cpu"; + }; + + led-3 { + gpios = <&main_gpio0 110 GPIO_ACTIVE_HIGH>; + function = LED_FUNCTION_DISK_ACTIVITY; + linux,default-trigger = "mmc1"; + }; + + led-4 { + gpios = <&main_gpio0 109 GPIO_ACTIVE_HIGH>; + function = LED_FUNCTION_WLAN; + default-state = "off"; + }; + }; + + evm_12v0: regulator-0 { + /* main supply */ + compatible = "regulator-fixed"; + regulator-name = "evm_12v0"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + regulator-boot-on; + }; + + vsys_3v3: regulator-1 { + /* Output of LMS140 */ + compatible = "regulator-fixed"; + regulator-name = "vsys_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&evm_12v0>; + regulator-always-on; + regulator-boot-on; + }; + + vsys_5v0: regulator-2 { + /* Output of LM5140 */ + compatible = "regulator-fixed"; + regulator-name = "vsys_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&evm_12v0>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_mmc1: regulator-3 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&sd_pwr_en_pins_default>; + regulator-name = "vdd_mmc1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + enable-active-high; + vin-supply = <&vsys_3v3>; + gpio = <&main_gpio0 82 GPIO_ACTIVE_HIGH>; + }; + + vdd_sd_dv_alt: regulator-4 { + compatible = "regulator-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&vdd_sd_dv_alt_pins_default>; + regulator-name = "tlv71033"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + vin-supply = <&vsys_5v0>; + gpios = <&main_gpio0 117 GPIO_ACTIVE_HIGH>; + states = <1800000 0x0>, + <3300000 0x1>; + }; + + dp_pwr_3v3: regulator-5 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&dp0_3v3_en_pins_default>; + regulator-name = "dp-pwr"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&main_gpio0 49 GPIO_ACTIVE_HIGH>; /* DP0_PWR_SW_EN */ + enable-active-high; + }; + + dp0: connector { + compatible = "dp-connector"; + label = "DP0"; + type = "full-size"; + dp-pwr-supply = <&dp_pwr_3v3>; + + port { + dp_connector_in: endpoint { + remote-endpoint = <&dp0_out>; + }; + }; + }; +}; + +&main_pmx0 { + led_pins_default: led-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x184, PIN_INPUT, 7) /* (T23) RGMII5_RD0.GPIO0_96 */ + J721E_IOPAD(0x180, PIN_INPUT, 7) /* (R23) RGMII5_RD1.GPIO0_95 */ + J721E_IOPAD(0x188, PIN_INPUT, 7) /* (Y28) RGMII6_TX_CTL.GPIO0_97 */ + J721E_IOPAD(0x1bc, PIN_INPUT, 7) /* (V24) MDIO0_MDC.GPIO0_110 */ + J721E_IOPAD(0x1b8, PIN_INPUT, 7) /* (V26) MDIO0_MDIO.GPIO0_109 */ + >; + }; + + main_mmc1_pins_default: main-mmc1-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */ + J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */ + J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */ + J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */ + J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */ + J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */ + J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */ + J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */ + >; + }; + + main_uart0_pins_default: main-uart0-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */ + J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */ + >; + }; + + sd_pwr_en_pins_default: sd-pwr-en-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x14c, PIN_INPUT, 7) /* (AA29) PRG0_PRU1_GPO19.GPIO0_82 */ + >; + }; + + vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x1d8, PIN_INPUT, 7) /* (W4) SPI1_CS1.GPIO0_117 */ + >; + }; + + main_usbss0_pins_default: main-usbss0-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 - USBC_DIR */ + >; + }; + + main_usbss1_pins_default: main-usbss1-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x290, INPUT_DISABLE, 1) /* (U6) USB0_DRVVBUS.USB1_DRVVBUS */ + >; + }; + + dp0_3v3_en_pins_default:dp0-3v3-en-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0xc8, PIN_INPUT, 7) /* (AE26) PRG0_PRU0_GPO6.GPIO0_49 */ + >; + }; + + dp0_pins_default: dp0-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* (Y4) SPI0_CS1.DP0_HPD */ + >; + }; + + main_i2c0_pins_default: main-i2c0-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */ + J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */ + >; + }; + + main_i2c1_pins_default: main-i2c1-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */ + J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */ + >; + }; + + main_i2c2_pins_default: main-i2c2-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x208, PIN_INPUT_PULLUP, 4) /* (W5) MCAN0_RX.I2C2_SCL */ + J721E_IOPAD(0x20c, PIN_INPUT_PULLUP, 4) /* (W6) MCAN0_TX.I2C2_SDA */ + J721E_IOPAD(0x138, PIN_INPUT, 7) /* (AE25) PRG0_PRU1_GPO14.GPIO0_77 */ + J721E_IOPAD(0x13c, PIN_INPUT, 7) /* (AF29) PRG0_PRU1_GPO15.GPIO0_78 */ + >; + }; + + main_i2c3_pins_default: main-i2c3-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */ + J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */ + >; + }; + + main_i2c4_pins_default: main-i2c4-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x1e0, PIN_INPUT_PULLUP, 2) /* (Y5) SPI1_D0.I2C4_SCL */ + J721E_IOPAD(0x1dc, PIN_INPUT_PULLUP, 2) /* (Y1) SPI1_CLK.I2C4_SDA */ + J721E_IOPAD(0x30, PIN_INPUT, 7) /* (AF24) PRG1_PRU0_GPO11.GPIO0_12 */ + J721E_IOPAD(0x34, PIN_INPUT, 7) /* (AJ24) PRG1_PRU0_GPO12.GPIO0_13 */ + >; + }; + + main_i2c5_pins_default: main-i2c5-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x150, PIN_INPUT_PULLUP, 2) /* (Y26) PRG0_MDIO0_MDIO.I2C5_SCL */ + J721E_IOPAD(0x154, PIN_INPUT_PULLUP, 2) /* (AA27) PRG0_MDIO0_MDC.I2C5_SDA */ + >; + }; + + main_i2c6_pins_default: main-i2c6-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x1d0, PIN_INPUT_PULLUP, 2) /* (AA3) SPI0_D1.I2C6_SCL */ + J721E_IOPAD(0x1e4, PIN_INPUT_PULLUP, 2) /* (Y2) SPI1_D1.I2C6_SDA */ + J721E_IOPAD(0x74, PIN_INPUT, 7) /* (AC21) PRG1_PRU1_GPO7.GPIO0_28 */ + J721E_IOPAD(0xa4, PIN_INPUT, 7) /* (AH22) PRG1_PRU1_GPO19.GPIO0_40 */ + >; + }; + + csi0_gpio_pins_default: csi0-gpio-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x19c, PIN_INPUT_PULLDOWN, 7) /* (W27) RGMII6_TD0.GPIO0_102 */ + J721E_IOPAD(0x1a0, PIN_INPUT_PULLDOWN, 7) /* (W29) RGMII6_TXC.GPIO0_103 */ + >; + }; + + csi1_gpio_pins_default: csi1-gpio-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x198, PIN_INPUT_PULLDOWN, 7) /* (V25) RGMII6_TD1.GPIO0_101 */ + J721E_IOPAD(0x1b0, PIN_INPUT_PULLDOWN, 7) /* (W24) RGMII6_RD1.GPIO0_107 */ + >; + }; + + pcie1_rst_pins_default: pcie1-rst-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x5c, PIN_INPUT, 7) /* (AG23) PRG1_PRU1_GPO1.GPIO0_22 */ + >; + }; +}; + +&wkup_pmx0 { + eeprom_wp_pins_default: eeprom-wp-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0xc4, PIN_OUTPUT_PULLUP, 7) /* (G24) WKUP_GPIO0_5 */ + >; + }; + + mcu_adc0_pins_default: mcu-adc0-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x130, PIN_INPUT, 0) /* (K25) MCU_ADC0_AIN0 */ + J721E_WKUP_IOPAD(0x134, PIN_INPUT, 0) /* (K26) MCU_ADC0_AIN1 */ + J721E_WKUP_IOPAD(0x138, PIN_INPUT, 0) /* (K28) MCU_ADC0_AIN2 */ + J721E_WKUP_IOPAD(0x13c, PIN_INPUT, 0) /* (L28) MCU_ADC0_AIN3 */ + J721E_WKUP_IOPAD(0x140, PIN_INPUT, 0) /* (K24) MCU_ADC0_AIN4 */ + J721E_WKUP_IOPAD(0x144, PIN_INPUT, 0) /* (K27) MCU_ADC0_AIN5 */ + J721E_WKUP_IOPAD(0x148, PIN_INPUT, 0) /* (K29) MCU_ADC0_AIN6 */ + >; + }; + + mcu_adc1_pins_default: mcu-adc1-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x150, PIN_INPUT, 0) /* (N23) MCU_ADC1_AIN0 */ + >; + }; + + mikro_bus_pins_default: mikro-bus-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x108, PIN_INPUT, 7) /* SDAPULLEN (E26) PMIC_POWER_EN0.WKUP_GPIO0_66 */ + J721E_WKUP_IOPAD(0xd4, PIN_INPUT, 7) /* SDA (G26) WKUP_GPIO0_9.MCU_I2C1_SDA */ + J721E_WKUP_IOPAD(0xf4, PIN_INPUT, 7) /* SDA (D25) MCU_I3C0_SDA.WKUP_GPIO0_61 */ + J721E_WKUP_IOPAD(0xd0, PIN_INPUT, 7) /* SCL (G27) WKUP_GPIO0_8.MCU_I2C1_SCL */ + J721E_WKUP_IOPAD(0xf0, PIN_INPUT, 7) /* SCL (D26) MCU_I3C0_SCL.WKUP_GPIO0_60 */ + + J721E_WKUP_IOPAD(0xb8, PIN_INPUT, 7) /* MOSI (F28) WKUP_GPIO0_2.MCU_SPI1_D1 */ + J721E_WKUP_IOPAD(0xb4, PIN_INPUT, 7) /* MISO (F25) WKUP_GPIO0_1.MCU_SPI1_D0 */ + J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 7) /* CLK (F26) WKUP_GPIO0_0.MCU_SPI1_CLK */ + J721E_WKUP_IOPAD(0xbc, PIN_INPUT, 7) /* CS (F27) WKUP_GPIO0_3.MCU_SPI1_CS0 */ + + J721E_WKUP_IOPAD(0x44, PIN_INPUT, 7) /* RX (G22) MCU_OSPI1_D1.WKUP_GPIO0_33 */ + J721E_WKUP_IOPAD(0x48, PIN_INPUT, 7) /* TX (D23) MCU_OSPI1_D2.WKUP_GPIO0_34 */ + + J721E_WKUP_IOPAD(0x4c, PIN_INPUT, 7) /* INT (C23) MCU_OSPI1_D3.WKUP_GPIO0_35 */ + J721E_WKUP_IOPAD(0x54, PIN_INPUT, 7) /* RST (E22) MCU_OSPI1_CSn1.WKUP_GPIO0_37 */ + J721E_WKUP_IOPAD(0xdc, PIN_INPUT, 7) /* PWM (H27) WKUP_GPIO0_11 */ + J721E_WKUP_IOPAD(0xac, PIN_INPUT, 7) /* AN (C29) MCU_MCAN0_RX.WKUP_GPIO0_59 */ + >; + }; + + mcu_cpsw_pins_default: mcu-cpsw-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x84, PIN_INPUT, 0) /* (B24) MCU_RGMII1_RD0 */ + J721E_WKUP_IOPAD(0x80, PIN_INPUT, 0) /* (A24) MCU_RGMII1_RD1 */ + J721E_WKUP_IOPAD(0x7c, PIN_INPUT, 0) /* (D24) MCU_RGMII1_RD2 */ + J721E_WKUP_IOPAD(0x78, PIN_INPUT, 0) /* (A25) MCU_RGMII1_RD3 */ + J721E_WKUP_IOPAD(0x74, PIN_INPUT, 0) /* (C24) MCU_RGMII1_RXC */ + J721E_WKUP_IOPAD(0x5c, PIN_INPUT, 0) /* (C25) MCU_RGMII1_RX_CTL */ + J721E_WKUP_IOPAD(0x6c, PIN_OUTPUT, 0) /* (B25) MCU_RGMII1_TD0 */ + J721E_WKUP_IOPAD(0x68, PIN_OUTPUT, 0) /* (A26) MCU_RGMII1_TD1 */ + J721E_WKUP_IOPAD(0x64, PIN_OUTPUT, 0) /* (A27) MCU_RGMII1_TD2 */ + J721E_WKUP_IOPAD(0x60, PIN_OUTPUT, 0) /* (A28) MCU_RGMII1_TD3 */ + J721E_WKUP_IOPAD(0x70, PIN_OUTPUT, 0) /* (B26) MCU_RGMII1_TXC */ + J721E_WKUP_IOPAD(0x58, PIN_OUTPUT, 0) /* (B27) MCU_RGMII1_TX_CTL */ + >; + }; + + mcu_mdio_pins_default: mcu-mdio1-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x8c, PIN_OUTPUT, 0) /* (F23) MCU_MDIO0_MDC */ + J721E_WKUP_IOPAD(0x88, PIN_INPUT, 0) /* (E23) MCU_MDIO0_MDIO */ + >; + }; + + sw_pwr_pins_default: sw-pwr-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0xc0, PIN_INPUT, 7) /* (G25) WKUP_GPIO0_4 */ + >; + }; + + wkup_i2c0_pins_default: wkup-i2c0-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */ + J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */ + >; + }; + + mcu_usbss1_pins_default: mcu-usbss1-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x3c, PIN_OUTPUT_PULLUP, 5) /* (A23) MCU_OSPI1_LBCLKO.WKUP_GPIO0_30 */ + >; + }; +}; + +&wkup_uart0 { + /* Wakeup UART is used by TIFS firmware. */ + status = "reserved"; +}; + +&main_uart0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_uart0_pins_default>; + /* Shared with ATF on this platform */ + power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; +}; + +&main_sdhci0 { + /* eMMC */ + non-removable; + ti,driver-strength-ohm = <50>; + disable-wp; +}; + +&main_sdhci1 { + /* SD Card */ + vmmc-supply = <&vdd_mmc1>; + vqmmc-supply = <&vdd_sd_dv_alt>; + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc1_pins_default>; + ti,driver-strength-ohm = <50>; + disable-wp; +}; + +&main_sdhci2 { + /* Unused */ + status = "disabled"; +}; + +&ospi0 { + /* Unused */ + status = "disabled"; +}; + +&ospi1 { + /* Unused */ + status = "disabled"; +}; + +&main_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c0_pins_default>; + clock-frequency = <400000>; +}; + +&main_i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c1_pins_default &csi1_gpio_pins_default>; + clock-frequency = <400000>; +}; + +&main_i2c2 { + /* BBB Header: P9.19 and P9.20 */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c2_pins_default>; + clock-frequency = <100000>; +}; + +&main_i2c3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c3_pins_default>; + clock-frequency = <400000>; +}; + +&main_i2c4 { + /* BBB Header: P9.24 and P9.26 */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c4_pins_default>; + clock-frequency = <100000>; +}; + +&main_i2c5 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c5_pins_default &csi0_gpio_pins_default>; + clock-frequency = <400000>; +}; + +&main_i2c6 { + /* BBB Header: P9.17 and P9.18 */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c6_pins_default>; + clock-frequency = <100000>; + status = "okay"; +}; + +&wkup_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_i2c0_pins_default &eeprom_wp_pins_default>; + clock-frequency = <400000>; + + eeprom@50 { + compatible = "atmel,24c04"; + reg = <0x50>; + }; +}; + +&main_gpio2 { + /* Unused */ + status = "disabled"; +}; + +&main_gpio3 { + /* Unused */ + status = "disabled"; +}; + +&main_gpio4 { + /* Unused */ + status = "disabled"; +}; + +&main_gpio5 { + /* Unused */ + status = "disabled"; +}; + +&main_gpio6 { + /* Unused */ + status = "disabled"; +}; + +&main_gpio7 { + /* Unused */ + status = "disabled"; +}; + +&wkup_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_adc0_pins_default &mcu_adc1_pins_default &mikro_bus_pins_default>; +}; + +&wkup_gpio1 { + /* Unused */ + status = "disabled"; +}; + +&usb_serdes_mux { + idle-states = <1>, <1>; /* USB0 to SERDES3, USB1 to SERDES2 */ +}; + +&serdes_ln_ctrl { + idle-states = <J721E_SERDES0_LANE0_IP4_UNUSED>, <J721E_SERDES0_LANE1_IP4_UNUSED>, + <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>, + <J721E_SERDES2_LANE0_IP1_UNUSED>, <J721E_SERDES2_LANE1_USB3_1>, + <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>, + <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>, + <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>; +}; + +&serdes_wiz3 { + typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_LOW>; + typec-dir-debounce-ms = <700>; /* TUSB321, tCCB_DEFAULT 133 ms */ +}; + +&serdes3 { + serdes3_usb_link: phy@0 { + reg = <0>; + cdns,num-lanes = <2>; + #phy-cells = <0>; + cdns,phy-type = <PHY_TYPE_USB3>; + resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>; + }; +}; + +&serdes4 { + torrent_phy_dp: phy@0 { + reg = <0>; + resets = <&serdes_wiz4 1>; + cdns,phy-type = <PHY_TYPE_DP>; + cdns,num-lanes = <4>; + cdns,max-bit-rate = <5400>; + #phy-cells = <0>; + }; +}; + +&mhdp { + phys = <&torrent_phy_dp>; + phy-names = "dpphy"; + pinctrl-names = "default"; + pinctrl-0 = <&dp0_pins_default>; +}; + +&usbss0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_usbss0_pins_default>; + ti,vbus-divider; +}; + +&usb0 { + dr_mode = "peripheral"; + maximum-speed = "super-speed"; + phys = <&serdes3_usb_link>; + phy-names = "cdns3,usb3-phy"; +}; + +&serdes2 { + serdes2_usb_link: phy@1 { + reg = <1>; + cdns,num-lanes = <1>; + #phy-cells = <0>; + cdns,phy-type = <PHY_TYPE_USB3>; + resets = <&serdes_wiz2 2>; + }; +}; + +&usbss1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_usbss1_pins_default &mcu_usbss1_pins_default>; + ti,vbus-divider; +}; + +&usb1 { + dr_mode = "host"; + maximum-speed = "super-speed"; + phys = <&serdes2_usb_link>; + phy-names = "cdns3,usb3-phy"; +}; + +&tscadc0 { + /* BBB Header: P9.39, P9.40, P9.37, P9.38, P9.33, P9.36, P9.35 */ + adc { + ti,adc-channels = <0 1 2 3 4 5 6>; + }; +}; + +&tscadc1 { + /* MCU mikroBUS Header J10.1 - MCU_ADC1_AIN0 */ + adc { + ti,adc-channels = <0>; + }; +}; + +&mcu_cpsw { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_cpsw_pins_default>; +}; + +&davinci_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mdio_pins_default>; + + phy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + }; +}; + +&cpsw_port1 { + phy-mode = "rgmii-rxid"; + phy-handle = <&phy0>; +}; + +&dss { + /* + * These clock assignments are chosen to enable the following outputs: + * + * VP0 - DisplayPort SST + * VP1 - DPI0 + * VP2 - DSI + * VP3 - DPI1 + */ + + assigned-clocks = <&k3_clks 152 1>, /* VP 1 pixel clock */ + <&k3_clks 152 4>, /* VP 2 pixel clock */ + <&k3_clks 152 9>, /* VP 3 pixel clock */ + <&k3_clks 152 13>; /* VP 4 pixel clock */ + assigned-clock-parents = <&k3_clks 152 2>, /* PLL16_HSDIV0 */ + <&k3_clks 152 6>, /* PLL19_HSDIV0 */ + <&k3_clks 152 11>, /* PLL18_HSDIV0 */ + <&k3_clks 152 18>; /* PLL23_HSDIV0 */ +}; + +&dss_ports { + port { + dpi0_out: endpoint { + remote-endpoint = <&dp0_in>; + }; + }; +}; + +&dp0_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dp0_in: endpoint { + remote-endpoint = <&dpi0_out>; + }; + }; + + port@4 { + reg = <4>; + dp0_out: endpoint { + remote-endpoint = <&dp_connector_in>; + }; + }; +}; + +&serdes0 { + serdes0_pcie_link: phy@0 { + reg = <0>; + cdns,num-lanes = <1>; + #phy-cells = <0>; + cdns,phy-type = <PHY_TYPE_PCIE>; + resets = <&serdes_wiz0 1>; + }; +}; + +&serdes1 { + serdes1_pcie_link: phy@0 { + reg = <0>; + cdns,num-lanes = <2>; + #phy-cells = <0>; + cdns,phy-type = <PHY_TYPE_PCIE>; + resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>; + }; +}; + +&pcie0_rc { + /* Unused */ + status = "disabled"; +}; + +&pcie1_rc { + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_rst_pins_default>; + phys = <&serdes1_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <2>; + max-link-speed = <3>; + reset-gpios = <&main_gpio0 22 GPIO_ACTIVE_HIGH>; +}; + +&pcie2_rc { + /* Unused */ + status = "disabled"; +}; + +&pcie0_ep { + status = "disabled"; + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <1>; +}; + +&pcie1_ep { + status = "disabled"; + phys = <&serdes1_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <2>; +}; + +&pcie2_ep { + /* Unused */ + status = "disabled"; +}; + +&pcie3_rc { + /* Unused */ + status = "disabled"; +}; + +&pcie3_ep { + /* Unused */ + status = "disabled"; +}; + +&icssg0_mdio { + /* Unused */ + status = "disabled"; +}; + +&icssg1_mdio { + /* Unused */ + status = "disabled"; +}; + +&ufs_wrapper { + status = "disabled"; +}; + +&mailbox0_cluster0 { + interrupts = <436>; + + mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster1 { + interrupts = <432>; + + mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster2 { + interrupts = <428>; + + mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster3 { + interrupts = <424>; + + mbox_c66_0: mbox-c66-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_c66_1: mbox-c66-1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster4 { + interrupts = <420>; + + mbox_c71_0: mbox-c71-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&mcu_r5fss0_core0 { + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; + memory-region = <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; +}; + +&mcu_r5fss0_core1 { + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; + memory-region = <&mcu_r5fss0_core1_dma_memory_region>, + <&mcu_r5fss0_core1_memory_region>; +}; + +&main_r5fss0_core0 { + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; + memory-region = <&main_r5fss0_core0_dma_memory_region>, + <&main_r5fss0_core0_memory_region>; +}; + +&main_r5fss0_core1 { + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; + memory-region = <&main_r5fss0_core1_dma_memory_region>, + <&main_r5fss0_core1_memory_region>; +}; + +&main_r5fss1_core0 { + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; + memory-region = <&main_r5fss1_core0_dma_memory_region>, + <&main_r5fss1_core0_memory_region>; +}; + +&main_r5fss1_core1 { + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; + memory-region = <&main_r5fss1_core1_dma_memory_region>, + <&main_r5fss1_core1_memory_region>; +}; + +&c66_0 { + mboxes = <&mailbox0_cluster3 &mbox_c66_0>; + memory-region = <&c66_0_dma_memory_region>, + <&c66_0_memory_region>; +}; + +&c66_1 { + mboxes = <&mailbox0_cluster3 &mbox_c66_1>; + memory-region = <&c66_1_dma_memory_region>, + <&c66_1_memory_region>; +}; + +&c71_0 { + mboxes = <&mailbox0_cluster4 &mbox_c71_0>; + memory-region = <&c71_0_dma_memory_region>, + <&c71_0_memory_region>; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index b1691ac3442d..7db0603125aa 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -96,7 +96,7 @@ <3300000 0x1>; }; - sound0: sound@0 { + sound0: sound-0 { compatible = "ti,j721e-cpb-audio"; model = "j721e-cpb"; @@ -370,38 +370,30 @@ status = "reserved"; }; -&main_uart0 { - power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; -}; - -&main_uart3 { - /* UART not brought out */ - status = "disabled"; +&mcu_uart0 { + status = "okay"; + /* Default pinmux */ }; -&main_uart5 { - /* UART not brought out */ - status = "disabled"; +&main_uart0 { + status = "okay"; + /* Shared with ATF on this platform */ + power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; }; -&main_uart6 { - /* UART not brought out */ - status = "disabled"; +&main_uart1 { + status = "okay"; + /* Default pinmux */ }; -&main_uart7 { - /* UART not brought out */ - status = "disabled"; +&main_uart2 { + status = "okay"; + /* Default pinmux */ }; -&main_uart8 { - /* UART not brought out */ - status = "disabled"; -}; - -&main_uart9 { - /* UART not brought out */ - status = "disabled"; +&main_uart4 { + status = "okay"; + /* Default pinmux */ }; &main_gpio2 { @@ -537,6 +529,7 @@ }; &main_i2c0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c0_pins_default>; clock-frequency = <400000>; @@ -573,6 +566,7 @@ }; &main_i2c1 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c1_pins_default>; clock-frequency = <400000>; @@ -598,6 +592,7 @@ }; &main_i2c3 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c3_pins_default>; clock-frequency = <400000>; @@ -636,6 +631,7 @@ }; &main_i2c6 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c6_pins_default>; clock-frequency = <400000>; @@ -713,47 +709,8 @@ }; }; -&mcasp0 { - status = "disabled"; -}; - -&mcasp1 { - status = "disabled"; -}; - -&mcasp2 { - status = "disabled"; -}; - -&mcasp3 { - status = "disabled"; -}; - -&mcasp4 { - status = "disabled"; -}; - -&mcasp5 { - status = "disabled"; -}; - -&mcasp6 { - status = "disabled"; -}; - -&mcasp7 { - status = "disabled"; -}; - -&mcasp8 { - status = "disabled"; -}; - -&mcasp9 { - status = "disabled"; -}; - &mcasp10 { + status = "okay"; #sound-dai-cells = <0>; pinctrl-names = "default"; @@ -771,10 +728,6 @@ rx-num-evt = <0>; }; -&mcasp11 { - status = "disabled"; -}; - &cmn_refclk1 { clock-frequency = <100000000>; }; @@ -925,73 +878,29 @@ }; &mcu_mcan0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcu_mcan0_pins_default>; phys = <&transceiver1>; }; &mcu_mcan1 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcu_mcan1_pins_default>; phys = <&transceiver2>; }; &main_mcan0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_mcan0_pins_default>; phys = <&transceiver3>; }; -&main_mcan1 { - status = "disabled"; -}; - &main_mcan2 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_mcan2_pins_default>; phys = <&transceiver4>; }; - -&main_mcan3 { - status = "disabled"; -}; - -&main_mcan4 { - status = "disabled"; -}; - -&main_mcan5 { - status = "disabled"; -}; - -&main_mcan6 { - status = "disabled"; -}; - -&main_mcan7 { - status = "disabled"; -}; - -&main_mcan8 { - status = "disabled"; -}; - -&main_mcan9 { - status = "disabled"; -}; - -&main_mcan10 { - status = "disabled"; -}; - -&main_mcan11 { - status = "disabled"; -}; - -&main_mcan12 { - status = "disabled"; -}; - -&main_mcan13 { - status = "disabled"; -}; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index 917c9dc99efa..c935622f0102 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -66,7 +66,73 @@ #mux-control-cells = <1>; mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */ <0x4010 0x8000000>; /* USB1 to SERDES1/2 mux */ - }; + }; + + ehrpwm_tbclk: clock-controller@4140 { + compatible = "ti,am654-ehrpwm-tbclk", "syscon"; + reg = <0x4140 0x18>; + #clock-cells = <1>; + }; + }; + + main_ehrpwm0: pwm@3000000 { + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x3000000 0x00 0x100>; + power-domains = <&k3_pds 83 TI_SCI_PD_EXCLUSIVE>; + clocks = <&ehrpwm_tbclk 0>, <&k3_clks 83 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + main_ehrpwm1: pwm@3010000 { + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x3010000 0x00 0x100>; + power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>; + clocks = <&ehrpwm_tbclk 1>, <&k3_clks 84 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + main_ehrpwm2: pwm@3020000 { + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x3020000 0x00 0x100>; + power-domains = <&k3_pds 85 TI_SCI_PD_EXCLUSIVE>; + clocks = <&ehrpwm_tbclk 2>, <&k3_clks 85 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + main_ehrpwm3: pwm@3030000 { + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x3030000 0x00 0x100>; + power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; + clocks = <&ehrpwm_tbclk 3>, <&k3_clks 86 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + main_ehrpwm4: pwm@3040000 { + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x3040000 0x00 0x100>; + power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; + clocks = <&ehrpwm_tbclk 4>, <&k3_clks 87 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + main_ehrpwm5: pwm@3050000 { + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x3050000 0x00 0x100>; + power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; + clocks = <&ehrpwm_tbclk 5>, <&k3_clks 88 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; }; gic500: interrupt-controller@1800000 { @@ -176,6 +242,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster1: mailbox@31f81000 { @@ -185,6 +252,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster2: mailbox@31f82000 { @@ -194,6 +262,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster3: mailbox@31f83000 { @@ -203,6 +272,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster4: mailbox@31f84000 { @@ -212,6 +282,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster5: mailbox@31f85000 { @@ -221,6 +292,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster6: mailbox@31f86000 { @@ -230,6 +302,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster7: mailbox@31f87000 { @@ -239,6 +312,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster8: mailbox@31f88000 { @@ -248,6 +322,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster9: mailbox@31f89000 { @@ -257,6 +332,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster10: mailbox@31f8a000 { @@ -266,6 +342,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster11: mailbox@31f8b000 { @@ -275,6 +352,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; main_ringacc: ringacc@3c000000 { @@ -337,13 +415,11 @@ dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>, <&main_udmap 0x4001>; dma-names = "tx", "rx1", "rx2"; - dma-coherent; rng: rng@4e10000 { compatible = "inside-secure,safexcel-eip76"; reg = <0x0 0x4e10000 0x0 0x7d>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&k3_clks 264 2>; }; }; @@ -840,6 +916,7 @@ power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 146 0>; clock-names = "fclk"; + status = "disabled"; }; main_uart1: serial@2810000 { @@ -851,6 +928,7 @@ power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 278 0>; clock-names = "fclk"; + status = "disabled"; }; main_uart2: serial@2820000 { @@ -862,6 +940,7 @@ power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 279 0>; clock-names = "fclk"; + status = "disabled"; }; main_uart3: serial@2830000 { @@ -873,6 +952,7 @@ power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 280 0>; clock-names = "fclk"; + status = "disabled"; }; main_uart4: serial@2840000 { @@ -884,6 +964,7 @@ power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 281 0>; clock-names = "fclk"; + status = "disabled"; }; main_uart5: serial@2850000 { @@ -895,6 +976,7 @@ power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 282 0>; clock-names = "fclk"; + status = "disabled"; }; main_uart6: serial@2860000 { @@ -906,6 +988,7 @@ power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 283 0>; clock-names = "fclk"; + status = "disabled"; }; main_uart7: serial@2870000 { @@ -917,6 +1000,7 @@ power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 284 0>; clock-names = "fclk"; + status = "disabled"; }; main_uart8: serial@2880000 { @@ -928,6 +1012,7 @@ power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 285 0>; clock-names = "fclk"; + status = "disabled"; }; main_uart9: serial@2890000 { @@ -939,6 +1024,7 @@ power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 286 0>; clock-names = "fclk"; + status = "disabled"; }; main_gpio0: gpio@600000 { @@ -1219,6 +1305,7 @@ clock-names = "fck"; clocks = <&k3_clks 187 0>; power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>; + status = "disabled"; }; main_i2c1: i2c@2010000 { @@ -1230,6 +1317,7 @@ clock-names = "fck"; clocks = <&k3_clks 188 0>; power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_i2c2: i2c@2020000 { @@ -1241,6 +1329,7 @@ clock-names = "fck"; clocks = <&k3_clks 189 0>; power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_i2c3: i2c@2030000 { @@ -1252,6 +1341,7 @@ clock-names = "fck"; clocks = <&k3_clks 190 0>; power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_i2c4: i2c@2040000 { @@ -1263,6 +1353,7 @@ clock-names = "fck"; clocks = <&k3_clks 191 0>; power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_i2c5: i2c@2050000 { @@ -1274,6 +1365,7 @@ clock-names = "fck"; clocks = <&k3_clks 192 0>; power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_i2c6: i2c@2060000 { @@ -1285,6 +1377,7 @@ clock-names = "fck"; clocks = <&k3_clks 193 0>; power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; ufs_wrapper: ufs-wrapper@4e80000 { @@ -1408,6 +1501,7 @@ clocks = <&k3_clks 174 1>; clock-names = "fck"; power-domains = <&k3_pds 174 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; mcasp1: mcasp@2b10000 { @@ -1425,6 +1519,7 @@ clocks = <&k3_clks 175 1>; clock-names = "fck"; power-domains = <&k3_pds 175 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; mcasp2: mcasp@2b20000 { @@ -1442,6 +1537,7 @@ clocks = <&k3_clks 176 1>; clock-names = "fck"; power-domains = <&k3_pds 176 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; mcasp3: mcasp@2b30000 { @@ -1459,6 +1555,7 @@ clocks = <&k3_clks 177 1>; clock-names = "fck"; power-domains = <&k3_pds 177 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; mcasp4: mcasp@2b40000 { @@ -1476,6 +1573,7 @@ clocks = <&k3_clks 178 1>; clock-names = "fck"; power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; mcasp5: mcasp@2b50000 { @@ -1493,6 +1591,7 @@ clocks = <&k3_clks 179 1>; clock-names = "fck"; power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; mcasp6: mcasp@2b60000 { @@ -1510,6 +1609,7 @@ clocks = <&k3_clks 180 1>; clock-names = "fck"; power-domains = <&k3_pds 180 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; mcasp7: mcasp@2b70000 { @@ -1527,6 +1627,7 @@ clocks = <&k3_clks 181 1>; clock-names = "fck"; power-domains = <&k3_pds 181 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; mcasp8: mcasp@2b80000 { @@ -1544,6 +1645,7 @@ clocks = <&k3_clks 182 1>; clock-names = "fck"; power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; mcasp9: mcasp@2b90000 { @@ -1561,6 +1663,7 @@ clocks = <&k3_clks 183 1>; clock-names = "fck"; power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; mcasp10: mcasp@2ba0000 { @@ -1578,6 +1681,7 @@ clocks = <&k3_clks 184 1>; clock-names = "fck"; power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; mcasp11: mcasp@2bb0000 { @@ -1595,6 +1699,7 @@ clocks = <&k3_clks 185 1>; clock-names = "fck"; power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; watchdog0: watchdog@2200000 { @@ -2027,6 +2132,7 @@ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan1: can@2711000 { @@ -2041,6 +2147,7 @@ <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan2: can@2721000 { @@ -2055,6 +2162,7 @@ <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan3: can@2731000 { @@ -2069,6 +2177,7 @@ <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan4: can@2741000 { @@ -2083,6 +2192,7 @@ <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan5: can@2751000 { @@ -2097,6 +2207,7 @@ <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan6: can@2761000 { @@ -2111,6 +2222,7 @@ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan7: can@2771000 { @@ -2125,6 +2237,7 @@ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan8: can@2781000 { @@ -2139,6 +2252,7 @@ <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan9: can@2791000 { @@ -2153,6 +2267,7 @@ <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan10: can@27a1000 { @@ -2167,6 +2282,7 @@ <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan11: can@27b1000 { @@ -2181,6 +2297,7 @@ <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan12: can@27c1000 { @@ -2195,6 +2312,7 @@ <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan13: can@27d1000 { @@ -2209,5 +2327,6 @@ <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi index df08724bbf1c..8ac78034d5d6 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi @@ -79,6 +79,7 @@ power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 287 0>; clock-names = "fclk"; + status = "disabled"; }; mcu_uart0: serial@40a00000 { @@ -90,6 +91,7 @@ power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 149 0>; clock-names = "fclk"; + status = "disabled"; }; wkup_gpio_intr: interrupt-controller@42200000 { @@ -145,6 +147,7 @@ clock-names = "fck"; clocks = <&k3_clks 194 0>; power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; mcu_i2c1: i2c@40b10000 { @@ -156,6 +159,7 @@ clock-names = "fck"; clocks = <&k3_clks 195 0>; power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; wkup_i2c0: i2c@42120000 { @@ -167,6 +171,7 @@ clock-names = "fck"; clocks = <&k3_clks 197 0>; power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>; + status = "disabled"; }; fss: fss@47000000 { @@ -216,7 +221,7 @@ clocks = <&k3_clks 0 1>; assigned-clocks = <&k3_clks 0 3>; assigned-clock-rates = <60000000>; - clock-names = "adc_tsc_fck"; + clock-names = "fck"; dmas = <&main_udmap 0x7400>, <&main_udmap 0x7401>; dma-names = "fifo0", "fifo1"; @@ -235,7 +240,7 @@ clocks = <&k3_clks 1 1>; assigned-clocks = <&k3_clks 1 3>; assigned-clock-rates = <60000000>; - clock-names = "adc_tsc_fck"; + clock-names = "fck"; dmas = <&main_udmap 0x7402>, <&main_udmap 0x7403>; dma-names = "fifo0", "fifo1"; @@ -403,6 +408,7 @@ <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; mcu_mcan1: can@40568000 { @@ -417,5 +423,6 @@ <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts index 80358cba6954..4640d280c85c 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -400,6 +400,47 @@ J721E_IOPAD(0x124, PIN_INPUT, 7) /* (Y24) PRG0_PRU1_GPO9.GPIO0_72 */ >; }; + + main_i2c5_pins_default: main-i2c5-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x150, PIN_INPUT_PULLUP, 2) /* (Y26) PRG0_MDIO0_MDIO.I2C5_SCL */ + J721E_IOPAD(0x154, PIN_INPUT_PULLUP, 2) /* (AA27) PRG0_MDIO0_MDC.I2C5_SDA */ + >; + }; + + rpi_header_gpio0_pins_default: rpi-header-gpio0-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x01C, PIN_INPUT, 7) /* (AD22) PRG1_PRU0_GPO6.GPIO0_7 */ + J721E_IOPAD(0x120, PIN_INPUT, 7) /* (AA28) PRG0_PRU1_GPO8.GPIO0_71 */ + J721E_IOPAD(0x14C, PIN_INPUT, 7) /* (AA29) PRG0_PRU1_GPO19.GPIO0_82 */ + J721E_IOPAD(0x02C, PIN_INPUT, 7) /* (AD21) PRG1_PRU0_GPO10.GPIO0_11 */ + J721E_IOPAD(0x198, PIN_INPUT, 7) /* (V25) RGMII6_TD1.GPIO0_101 */ + J721E_IOPAD(0x1B0, PIN_INPUT, 7) /* (W24) RGMII6_RD1.GPIO0_107 */ + J721E_IOPAD(0x1A0, PIN_INPUT, 7) /* (W29) RGMII6_TXC.GPIO0_103 */ + J721E_IOPAD(0x008, PIN_INPUT, 7) /* (AG22) PRG1_PRU0_GPO1.GPIO0_2 */ + J721E_IOPAD(0x1D0, PIN_INPUT, 7) /* (AA3) SPI0_D1.GPIO0_115 */ + J721E_IOPAD(0x11C, PIN_INPUT, 7) /* (AA24) PRG0_PRU1_GPO7.GPIO0_70 */ + J721E_IOPAD(0x148, PIN_INPUT, 7) /* (AA26) PRG0_PRU1_GPO18.GPIO0_81 */ + J721E_IOPAD(0x004, PIN_INPUT, 7) /* (AC23) PRG1_PRU0_GPO0.GPIO0_1 */ + J721E_IOPAD(0x014, PIN_INPUT, 7) /* (AH23) PRG1_PRU0_GPO4.GPIO0_5 */ + J721E_IOPAD(0x020, PIN_INPUT, 7) /* (AE20) PRG1_PRU0_GPO7.GPIO0_8 */ + J721E_IOPAD(0x19C, PIN_INPUT, 7) /* (W27) RGMII6_TD0.GPIO0_102 */ + J721E_IOPAD(0x1B4, PIN_INPUT, 7) /* (W25) RGMII6_RD0.GPIO0_108 */ + J721E_IOPAD(0x188, PIN_INPUT, 7) /* (Y28) RGMII6_TX_CTL.GPIO0_97 */ + J721E_IOPAD(0x00C, PIN_INPUT, 7) /* (AF22) PRG1_PRU0_GPO2.GPIO0_3 */ + J721E_IOPAD(0x010, PIN_INPUT, 7) /* (AJ23) PRG1_PRU0_GPO3.GPIO0_4 */ + J721E_IOPAD(0x178, PIN_INPUT, 7) /* (U27) RGMII5_RD3.GPIO0_93 */ + J721E_IOPAD(0x17C, PIN_INPUT, 7) /* (U24) RGMII5_RD2.GPIO0_94 */ + J721E_IOPAD(0x190, PIN_INPUT, 7) /* (W23) RGMII6_TD3.GPIO0_99 */ + J721E_IOPAD(0x18C, PIN_INPUT, 7) /* (V23) RGMII6_RX_CTL.GPIO0_98 */ + >; + }; + + rpi_header_gpio1_pins_default: rpi-header-gpio1-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x234, PIN_INPUT, 7) /* (U3) EXT_REFCLK1.GPIO1_12 */ + >; + }; }; &wkup_pmx0 { @@ -475,46 +516,22 @@ status = "reserved"; }; +&mcu_uart0 { + status = "okay"; + /* Default pinmux */ +}; + &main_uart0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_uart0_pins_default>; /* Shared with ATF on this platform */ power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; }; -&main_uart2 { - /* Brought out on RPi header */ - status = "disabled"; -}; - -&main_uart3 { - /* UART not brought out */ - status = "disabled"; -}; - -&main_uart5 { - /* UART not brought out */ - status = "disabled"; -}; - -&main_uart6 { - /* UART not brought out */ - status = "disabled"; -}; - -&main_uart7 { - /* UART not brought out */ - status = "disabled"; -}; - -&main_uart8 { - /* UART not brought out */ - status = "disabled"; -}; - -&main_uart9 { - /* Brought out on M.2 E Key */ - status = "disabled"; +&main_uart1 { + status = "okay"; + /* Default pinmux */ }; &main_sdhci0 { @@ -561,6 +578,7 @@ }; &main_i2c0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c0_pins_default>; clock-frequency = <400000>; @@ -588,18 +606,15 @@ }; &main_i2c1 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c1_pins_default>; /* i2c1 is used for DVI DDC, so we need to use 100kHz */ clock-frequency = <100000>; }; -&main_i2c2 { - /* Unused */ - status = "disabled"; -}; - &main_i2c3 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c3_pins_default>; clock-frequency = <400000>; @@ -626,19 +641,22 @@ }; }; -&main_i2c4 { - /* Unused */ - status = "disabled"; -}; - &main_i2c5 { /* Brought out on RPi Header */ - status = "disabled"; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c5_pins_default>; + clock-frequency = <400000>; }; -&main_i2c6 { - /* Unused */ - status = "disabled"; +&main_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&rpi_header_gpio0_pins_default>; +}; + +&main_gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&rpi_header_gpio1_pins_default>; }; &main_gpio2 { @@ -837,66 +855,6 @@ }; }; -&mcasp0 { - /* Unused */ - status = "disabled"; -}; - -&mcasp1 { - /* Unused */ - status = "disabled"; -}; - -&mcasp2 { - /* Unused */ - status = "disabled"; -}; - -&mcasp3 { - /* Unused */ - status = "disabled"; -}; - -&mcasp4 { - /* Unused */ - status = "disabled"; -}; - -&mcasp5 { - /* Unused */ - status = "disabled"; -}; - -&mcasp6 { - /* Brought out on RPi header */ - status = "disabled"; -}; - -&mcasp7 { - /* Unused */ - status = "disabled"; -}; - -&mcasp8 { - /* Unused */ - status = "disabled"; -}; - -&mcasp9 { - /* Unused */ - status = "disabled"; -}; - -&mcasp10 { - /* Unused */ - status = "disabled"; -}; - -&mcasp11 { - /* Brought out on M.2 E Key */ - status = "disabled"; -}; - &serdes0 { serdes0_pcie_link: phy@0 { reg = <0>; @@ -984,6 +942,7 @@ }; &mailbox0_cluster0 { + status = "okay"; interrupts = <436>; mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { @@ -998,6 +957,7 @@ }; &mailbox0_cluster1 { + status = "okay"; interrupts = <432>; mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { @@ -1012,6 +972,7 @@ }; &mailbox0_cluster2 { + status = "okay"; interrupts = <428>; mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { @@ -1026,6 +987,7 @@ }; &mailbox0_cluster3 { + status = "okay"; interrupts = <424>; mbox_c66_0: mbox-c66-0 { @@ -1040,6 +1002,7 @@ }; &mailbox0_cluster4 { + status = "okay"; interrupts = <420>; mbox_c71_0: mbox-c71-0 { @@ -1048,34 +1011,6 @@ }; }; -&mailbox0_cluster5 { - status = "disabled"; -}; - -&mailbox0_cluster6 { - status = "disabled"; -}; - -&mailbox0_cluster7 { - status = "disabled"; -}; - -&mailbox0_cluster8 { - status = "disabled"; -}; - -&mailbox0_cluster9 { - status = "disabled"; -}; - -&mailbox0_cluster10 { - status = "disabled"; -}; - -&mailbox0_cluster11 { - status = "disabled"; -}; - &mcu_r5fss0_core0 { mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; memory-region = <&mcu_r5fss0_core0_dma_memory_region>, diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi index e36335232cf8..e289d5b44356 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi @@ -186,6 +186,7 @@ }; &mailbox0_cluster0 { + status = "okay"; interrupts = <436>; mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { @@ -200,6 +201,7 @@ }; &mailbox0_cluster1 { + status = "okay"; interrupts = <432>; mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { @@ -214,6 +216,7 @@ }; &mailbox0_cluster2 { + status = "okay"; interrupts = <428>; mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { @@ -228,6 +231,7 @@ }; &mailbox0_cluster3 { + status = "okay"; interrupts = <424>; mbox_c66_0: mbox-c66-0 { @@ -242,6 +246,7 @@ }; &mailbox0_cluster4 { + status = "okay"; interrupts = <420>; mbox_c71_0: mbox-c71-0 { @@ -250,34 +255,6 @@ }; }; -&mailbox0_cluster5 { - status = "disabled"; -}; - -&mailbox0_cluster6 { - status = "disabled"; -}; - -&mailbox0_cluster7 { - status = "disabled"; -}; - -&mailbox0_cluster8 { - status = "disabled"; -}; - -&mailbox0_cluster9 { - status = "disabled"; -}; - -&mailbox0_cluster10 { - status = "disabled"; -}; - -&mailbox0_cluster11 { - status = "disabled"; -}; - &mcu_r5fss0_core0 { mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; memory-region = <&mcu_r5fss0_core0_dma_memory_region>, diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index b210cc07c539..a7aa6cf08acd 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -219,49 +219,19 @@ status = "reserved"; }; -&main_uart0 { - status = "disabled"; -}; - -&main_uart1 { - status = "disabled"; -}; - -&main_uart2 { - status = "disabled"; -}; - -&main_uart3 { - status = "disabled"; -}; - -&main_uart4 { - status = "disabled"; -}; - -&main_uart5 { - status = "disabled"; -}; - -&main_uart6 { - status = "disabled"; -}; - -&main_uart7 { - status = "disabled"; +&mcu_uart0 { + status = "okay"; + /* Default pinmux */ }; &main_uart8 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_uart8_pins_default>; /* Shared with TFA on this platform */ power-domains = <&k3_pds 357 TI_SCI_PD_SHARED>; }; -&main_uart9 { - status = "disabled"; -}; - &main_i2c0 { clock-frequency = <400000>; @@ -291,30 +261,6 @@ }; }; -&main_i2c1 { - status = "disabled"; -}; - -&main_i2c2 { - status = "disabled"; -}; - -&main_i2c3 { - status = "disabled"; -}; - -&main_i2c4 { - status = "disabled"; -}; - -&main_i2c5 { - status = "disabled"; -}; - -&main_i2c6 { - status = "disabled"; -}; - &main_sdhci0 { /* eMMC */ non-removable; @@ -351,81 +297,15 @@ }; &mcu_mcan0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcu_mcan0_pins_default>; phys = <&transceiver1>; }; &mcu_mcan1 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcu_mcan1_pins_default>; phys = <&transceiver2>; }; - -&main_mcan0 { - status = "disabled"; -}; - -&main_mcan1 { - status = "disabled"; -}; - -&main_mcan2 { - status = "disabled"; -}; - -&main_mcan3 { - status = "disabled"; -}; - -&main_mcan4 { - status = "disabled"; -}; - -&main_mcan5 { - status = "disabled"; -}; - -&main_mcan6 { - status = "disabled"; -}; - -&main_mcan7 { - status = "disabled"; -}; - -&main_mcan8 { - status = "disabled"; -}; - -&main_mcan9 { - status = "disabled"; -}; - -&main_mcan10 { - status = "disabled"; -}; - -&main_mcan11 { - status = "disabled"; -}; - -&main_mcan12 { - status = "disabled"; -}; - -&main_mcan13 { - status = "disabled"; -}; - -&main_mcan14 { - status = "disabled"; -}; - -&main_mcan15 { - status = "disabled"; -}; - -&main_mcan17 { - status = "disabled"; -}; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi index 34e7d577ae13..8915132efcc1 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -60,7 +60,7 @@ #interrupt-cells = <1>; ti,sci = <&sms>; ti,sci-dev-id = <148>; - ti,interrupt-ranges = <8 360 56>; + ti,interrupt-ranges = <8 392 56>; }; main_pmx0: pinctrl@11c000 { @@ -72,6 +72,25 @@ pinctrl-single,function-mask = <0xffffffff>; }; + main_crypto: crypto@4e00000 { + compatible = "ti,j721e-sa2ul"; + reg = <0x00 0x04e00000 0x00 0x1200>; + power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x04e00000 0x00 0x04e00000 0x00 0x30000>; + + dmas = <&main_udmap 0xca40>, <&main_udmap 0x4a40>, + <&main_udmap 0x4a41>; + dma-names = "tx", "rx1", "rx2"; + + rng: rng@4e10000 { + compatible = "inside-secure,safexcel-eip76"; + reg = <0x00 0x04e10000 0x00 0x7d>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + main_uart0: serial@2800000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02800000 0x00 0x200>; @@ -80,6 +99,7 @@ clocks = <&k3_clks 146 3>; clock-names = "fclk"; power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_uart1: serial@2810000 { @@ -90,6 +110,7 @@ clocks = <&k3_clks 350 3>; clock-names = "fclk"; power-domains = <&k3_pds 350 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_uart2: serial@2820000 { @@ -100,6 +121,7 @@ clocks = <&k3_clks 351 3>; clock-names = "fclk"; power-domains = <&k3_pds 351 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_uart3: serial@2830000 { @@ -110,6 +132,7 @@ clocks = <&k3_clks 352 3>; clock-names = "fclk"; power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_uart4: serial@2840000 { @@ -120,6 +143,7 @@ clocks = <&k3_clks 353 3>; clock-names = "fclk"; power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_uart5: serial@2850000 { @@ -130,6 +154,7 @@ clocks = <&k3_clks 354 3>; clock-names = "fclk"; power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_uart6: serial@2860000 { @@ -140,6 +165,7 @@ clocks = <&k3_clks 355 3>; clock-names = "fclk"; power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_uart7: serial@2870000 { @@ -150,6 +176,7 @@ clocks = <&k3_clks 356 3>; clock-names = "fclk"; power-domains = <&k3_pds 356 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_uart8: serial@2880000 { @@ -160,6 +187,7 @@ clocks = <&k3_clks 357 3>; clock-names = "fclk"; power-domains = <&k3_pds 357 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_uart9: serial@2890000 { @@ -170,6 +198,7 @@ clocks = <&k3_clks 358 3>; clock-names = "fclk"; power-domains = <&k3_pds 358 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_gpio0: gpio@600000 { @@ -256,6 +285,7 @@ clocks = <&k3_clks 215 1>; clock-names = "fck"; power-domains = <&k3_pds 215 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_i2c2: i2c@2020000 { @@ -267,6 +297,7 @@ clocks = <&k3_clks 216 1>; clock-names = "fck"; power-domains = <&k3_pds 216 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_i2c3: i2c@2030000 { @@ -278,6 +309,7 @@ clocks = <&k3_clks 217 1>; clock-names = "fck"; power-domains = <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_i2c4: i2c@2040000 { @@ -289,6 +321,7 @@ clocks = <&k3_clks 218 1>; clock-names = "fck"; power-domains = <&k3_pds 218 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_i2c5: i2c@2050000 { @@ -300,6 +333,7 @@ clocks = <&k3_clks 219 1>; clock-names = "fck"; power-domains = <&k3_pds 219 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_i2c6: i2c@2060000 { @@ -311,6 +345,7 @@ clocks = <&k3_clks 220 1>; clock-names = "fck"; power-domains = <&k3_pds 220 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; main_sdhci0: mmc@4f80000 { @@ -428,6 +463,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster1: mailbox@31f81000 { @@ -437,6 +473,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster2: mailbox@31f82000 { @@ -446,6 +483,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster3: mailbox@31f83000 { @@ -455,6 +493,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster4: mailbox@31f84000 { @@ -464,6 +503,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster5: mailbox@31f85000 { @@ -473,6 +513,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster6: mailbox@31f86000 { @@ -482,6 +523,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster7: mailbox@31f87000 { @@ -491,6 +533,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster8: mailbox@31f88000 { @@ -500,6 +543,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster9: mailbox@31f89000 { @@ -509,6 +553,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster10: mailbox@31f8a000 { @@ -518,6 +563,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox0_cluster11: mailbox@31f8b000 { @@ -527,6 +573,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox1_cluster0: mailbox@31f90000 { @@ -536,6 +583,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox1_cluster1: mailbox@31f91000 { @@ -545,6 +593,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox1_cluster2: mailbox@31f92000 { @@ -554,6 +603,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox1_cluster3: mailbox@31f93000 { @@ -563,6 +613,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox1_cluster4: mailbox@31f94000 { @@ -572,6 +623,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox1_cluster5: mailbox@31f95000 { @@ -581,6 +633,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox1_cluster6: mailbox@31f96000 { @@ -590,6 +643,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox1_cluster7: mailbox@31f97000 { @@ -599,6 +653,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox1_cluster8: mailbox@31f98000 { @@ -608,6 +663,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox1_cluster9: mailbox@31f99000 { @@ -617,6 +673,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox1_cluster10: mailbox@31f9a000 { @@ -626,6 +683,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; mailbox1_cluster11: mailbox@31f9b000 { @@ -635,6 +693,7 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; interrupt-parent = <&main_navss_intr>; + status = "disabled"; }; main_ringacc: ringacc@3c000000 { @@ -698,6 +757,7 @@ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan1: can@2711000 { @@ -712,6 +772,7 @@ <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan2: can@2721000 { @@ -726,6 +787,7 @@ <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan3: can@2731000 { @@ -740,6 +802,7 @@ <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan4: can@2741000 { @@ -754,6 +817,7 @@ <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan5: can@2751000 { @@ -768,6 +832,7 @@ <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan6: can@2761000 { @@ -782,6 +847,7 @@ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan7: can@2771000 { @@ -796,6 +862,7 @@ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan8: can@2781000 { @@ -810,6 +877,7 @@ <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan9: can@2791000 { @@ -824,6 +892,7 @@ <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan10: can@27a1000 { @@ -838,6 +907,7 @@ <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan11: can@27b1000 { @@ -852,6 +922,7 @@ <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan12: can@27c1000 { @@ -866,6 +937,7 @@ <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan13: can@27d1000 { @@ -880,6 +952,7 @@ <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan14: can@2681000 { @@ -894,6 +967,7 @@ <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan15: can@2691000 { @@ -908,6 +982,7 @@ <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan16: can@26a1000 { @@ -922,6 +997,7 @@ <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan17: can@26b1000 { @@ -936,5 +1012,6 @@ <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi index 4d1bfabd1313..0af242aa9816 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -65,7 +65,7 @@ #interrupt-cells = <1>; ti,sci = <&sms>; ti,sci-dev-id = <125>; - ti,interrupt-ranges = <16 928 16>; + ti,interrupt-ranges = <16 960 16>; }; mcu_conf: syscon@40f00000 { @@ -91,6 +91,7 @@ clocks = <&k3_clks 359 3>; clock-names = "fclk"; power-domains = <&k3_pds 359 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; mcu_uart0: serial@40a00000 { @@ -101,6 +102,7 @@ clocks = <&k3_clks 149 3>; clock-names = "fclk"; power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; wkup_gpio0: gpio@42110000 { @@ -144,6 +146,7 @@ clocks = <&k3_clks 223 1>; clock-names = "fck"; power-domains = <&k3_pds 223 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; mcu_i2c0: i2c@40b00000 { @@ -155,6 +158,7 @@ clocks = <&k3_clks 221 1>; clock-names = "fck"; power-domains = <&k3_pds 221 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; mcu_i2c1: i2c@40b10000 { @@ -166,6 +170,7 @@ clocks = <&k3_clks 222 1>; clock-names = "fck"; power-domains = <&k3_pds 222 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; mcu_mcan0: can@40528000 { @@ -180,6 +185,7 @@ <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; mcu_mcan1: can@40568000 { @@ -194,6 +200,7 @@ <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; mcu_navss: bus@28380000{ diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi index 76f0ceacb6d4..6930efff8a5a 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi @@ -56,6 +56,7 @@ }; &main_i2c0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c0_pins_default>; clock-frequency = <400000>; @@ -73,103 +74,8 @@ }; &main_mcan16 { + status = "okay"; pinctrl-0 = <&main_mcan16_pins_default>; pinctrl-names = "default"; phys = <&transceiver0>; }; - -&mailbox0_cluster0 { - status = "disabled"; -}; - -&mailbox0_cluster1 { - status = "disabled"; -}; - -&mailbox0_cluster2 { - status = "disabled"; -}; - -&mailbox0_cluster3 { - status = "disabled"; -}; - -&mailbox0_cluster4 { - status = "disabled"; -}; - -&mailbox0_cluster5 { - status = "disabled"; -}; - -&mailbox0_cluster6 { - status = "disabled"; -}; - -&mailbox0_cluster7 { - status = "disabled"; -}; - -&mailbox0_cluster8 { - status = "disabled"; -}; - -&mailbox0_cluster9 { - status = "disabled"; -}; - -&mailbox0_cluster10 { - status = "disabled"; -}; - -&mailbox0_cluster11 { - status = "disabled"; -}; - -&mailbox1_cluster0 { - status = "disabled"; -}; - -&mailbox1_cluster1 { - status = "disabled"; -}; - -&mailbox1_cluster2 { - status = "disabled"; -}; - -&mailbox1_cluster3 { - status = "disabled"; -}; - -&mailbox1_cluster4 { - status = "disabled"; -}; - -&mailbox1_cluster5 { - status = "disabled"; -}; - -&mailbox1_cluster6 { - status = "disabled"; -}; - -&mailbox1_cluster7 { - status = "disabled"; -}; - -&mailbox1_cluster8 { - status = "disabled"; -}; - -&mailbox1_cluster9 { - status = "disabled"; -}; - -&mailbox1_cluster10 { - status = "disabled"; -}; - -&mailbox1_cluster11 { - status = "disabled"; -}; diff --git a/arch/arm64/include/asm/kvm_pgtable.h b/arch/arm64/include/asm/kvm_pgtable.h index 1b098bd4cd37..3252eb50ecfe 100644 --- a/arch/arm64/include/asm/kvm_pgtable.h +++ b/arch/arm64/include/asm/kvm_pgtable.h @@ -13,6 +13,18 @@ #define KVM_PGTABLE_MAX_LEVELS 4U +/* + * The largest supported block sizes for KVM (no 52-bit PA support): + * - 4K (level 1): 1GB + * - 16K (level 2): 32MB + * - 64K (level 2): 512MB + */ +#ifdef CONFIG_ARM64_4K_PAGES +#define KVM_PGTABLE_MIN_BLOCK_LEVEL 1U +#else +#define KVM_PGTABLE_MIN_BLOCK_LEVEL 2U +#endif + static inline u64 kvm_get_parange(u64 mmfr0) { u64 parange = cpuid_feature_extract_unsigned_field(mmfr0, @@ -58,11 +70,7 @@ static inline u64 kvm_granule_size(u32 level) static inline bool kvm_level_supports_block_mapping(u32 level) { - /* - * Reject invalid block mappings and don't bother with 4TB mappings for - * 52-bit PAs. - */ - return !(level == 0 || (PAGE_SIZE != SZ_4K && level == 1)); + return level >= KVM_PGTABLE_MIN_BLOCK_LEVEL; } /** diff --git a/arch/arm64/include/asm/stage2_pgtable.h b/arch/arm64/include/asm/stage2_pgtable.h index fe341a6578c3..c8dca8ae359c 100644 --- a/arch/arm64/include/asm/stage2_pgtable.h +++ b/arch/arm64/include/asm/stage2_pgtable.h @@ -11,13 +11,6 @@ #include <linux/pgtable.h> /* - * PGDIR_SHIFT determines the size a top-level page table entry can map - * and depends on the number of levels in the page table. Compute the - * PGDIR_SHIFT for a given number of levels. - */ -#define pt_levels_pgdir_shift(lvls) ARM64_HW_PGTABLE_LEVEL_SHIFT(4 - (lvls)) - -/* * The hardware supports concatenation of up to 16 tables at stage2 entry * level and we use the feature whenever possible, which means we resolve 4 * additional bits of address at the entry level. @@ -30,11 +23,6 @@ #define stage2_pgtable_levels(ipa) ARM64_HW_PGTABLE_LEVELS((ipa) - 4) #define kvm_stage2_levels(kvm) VTCR_EL2_LVLS(kvm->arch.vtcr) -/* stage2_pgdir_shift() is the size mapped by top-level stage2 entry for the VM */ -#define stage2_pgdir_shift(kvm) pt_levels_pgdir_shift(kvm_stage2_levels(kvm)) -#define stage2_pgdir_size(kvm) (1ULL << stage2_pgdir_shift(kvm)) -#define stage2_pgdir_mask(kvm) ~(stage2_pgdir_size(kvm) - 1) - /* * kvm_mmmu_cache_min_pages() is the number of pages required to install * a stage-2 translation. We pre-allocate the entry level page table at @@ -42,12 +30,4 @@ */ #define kvm_mmu_cache_min_pages(kvm) (kvm_stage2_levels(kvm) - 1) -static inline phys_addr_t -stage2_pgd_addr_end(struct kvm *kvm, phys_addr_t addr, phys_addr_t end) -{ - phys_addr_t boundary = (addr + stage2_pgdir_size(kvm)) & stage2_pgdir_mask(kvm); - - return (boundary - 1 < end - 1) ? boundary : end; -} - #endif /* __ARM64_S2_PGTABLE_H_ */ diff --git a/arch/arm64/kernel/entry-ftrace.S b/arch/arm64/kernel/entry-ftrace.S index bd5df50e4643..795344ab4ec4 100644 --- a/arch/arm64/kernel/entry-ftrace.S +++ b/arch/arm64/kernel/entry-ftrace.S @@ -7,6 +7,7 @@ */ #include <linux/linkage.h> +#include <linux/cfi_types.h> #include <asm/asm-offsets.h> #include <asm/assembler.h> #include <asm/ftrace.h> @@ -294,10 +295,14 @@ SYM_FUNC_END(ftrace_graph_caller) #endif /* CONFIG_FUNCTION_GRAPH_TRACER */ #endif /* CONFIG_DYNAMIC_FTRACE_WITH_REGS */ -SYM_FUNC_START(ftrace_stub) +SYM_TYPED_FUNC_START(ftrace_stub) ret SYM_FUNC_END(ftrace_stub) +SYM_TYPED_FUNC_START(ftrace_stub_graph) + ret +SYM_FUNC_END(ftrace_stub_graph) + #ifdef CONFIG_FUNCTION_GRAPH_TRACER /* * void return_to_handler(void) diff --git a/arch/arm64/kvm/hyp/Makefile b/arch/arm64/kvm/hyp/Makefile index 687598e41b21..a38dea6186c9 100644 --- a/arch/arm64/kvm/hyp/Makefile +++ b/arch/arm64/kvm/hyp/Makefile @@ -5,9 +5,6 @@ incdir := $(srctree)/$(src)/include subdir-asflags-y := -I$(incdir) -subdir-ccflags-y := -I$(incdir) \ - -fno-stack-protector \ - -DDISABLE_BRANCH_PROFILING \ - $(DISABLE_STACKLEAK_PLUGIN) +subdir-ccflags-y := -I$(incdir) obj-$(CONFIG_KVM) += vhe/ nvhe/ pgtable.o diff --git a/arch/arm64/kvm/hyp/nvhe/Makefile b/arch/arm64/kvm/hyp/nvhe/Makefile index b5c5119c7396..be0a2bc3e20d 100644 --- a/arch/arm64/kvm/hyp/nvhe/Makefile +++ b/arch/arm64/kvm/hyp/nvhe/Makefile @@ -10,6 +10,9 @@ asflags-y := -D__KVM_NVHE_HYPERVISOR__ -D__DISABLE_EXPORTS # will explode instantly (Words of Marc Zyngier). So introduce a generic flag # __DISABLE_TRACE_MMIO__ to disable MMIO tracing for nVHE KVM. ccflags-y := -D__KVM_NVHE_HYPERVISOR__ -D__DISABLE_EXPORTS -D__DISABLE_TRACE_MMIO__ +ccflags-y += -fno-stack-protector \ + -DDISABLE_BRANCH_PROFILING \ + $(DISABLE_STACKLEAK_PLUGIN) hostprogs := gen-hyprel HOST_EXTRACFLAGS += -I$(objtree)/include @@ -89,6 +92,10 @@ quiet_cmd_hypcopy = HYPCOPY $@ # Remove ftrace, Shadow Call Stack, and CFI CFLAGS. # This is equivalent to the 'notrace', '__noscs', and '__nocfi' annotations. KBUILD_CFLAGS := $(filter-out $(CC_FLAGS_FTRACE) $(CC_FLAGS_SCS) $(CC_FLAGS_CFI), $(KBUILD_CFLAGS)) +# Starting from 13.0.0 llvm emits SHT_REL section '.llvm.call-graph-profile' +# when profile optimization is applied. gen-hyprel does not support SHT_REL and +# causes a build failure. Remove profile optimization flags. +KBUILD_CFLAGS := $(filter-out -fprofile-sample-use=% -fprofile-use=%, $(KBUILD_CFLAGS)) # KVM nVHE code is run at a different exception code with a different map, so # compiler instrumentation that inserts callbacks or checks into the code may diff --git a/arch/arm64/kvm/mmu.c b/arch/arm64/kvm/mmu.c index 34c5feed9dc1..60ee3d9f01f8 100644 --- a/arch/arm64/kvm/mmu.c +++ b/arch/arm64/kvm/mmu.c @@ -31,6 +31,13 @@ static phys_addr_t hyp_idmap_vector; static unsigned long io_map_base; +static phys_addr_t stage2_range_addr_end(phys_addr_t addr, phys_addr_t end) +{ + phys_addr_t size = kvm_granule_size(KVM_PGTABLE_MIN_BLOCK_LEVEL); + phys_addr_t boundary = ALIGN_DOWN(addr + size, size); + + return (boundary - 1 < end - 1) ? boundary : end; +} /* * Release kvm_mmu_lock periodically if the memory region is large. Otherwise, @@ -52,7 +59,7 @@ static int stage2_apply_range(struct kvm *kvm, phys_addr_t addr, if (!pgt) return -EINVAL; - next = stage2_pgd_addr_end(kvm, addr, end); + next = stage2_range_addr_end(addr, end); ret = fn(pgt, addr, next - addr); if (ret) break; diff --git a/arch/arm64/kvm/vgic/vgic-its.c b/arch/arm64/kvm/vgic/vgic-its.c index 24d7778d1ce6..733b53055f97 100644 --- a/arch/arm64/kvm/vgic/vgic-its.c +++ b/arch/arm64/kvm/vgic/vgic-its.c @@ -2149,7 +2149,7 @@ static int scan_its_table(struct vgic_its *its, gpa_t base, int size, u32 esz, memset(entry, 0, esz); - while (len > 0) { + while (true) { int next_offset; size_t byte_offset; @@ -2162,6 +2162,9 @@ static int scan_its_table(struct vgic_its *its, gpa_t base, int size, u32 esz, return next_offset; byte_offset = next_offset * esz; + if (byte_offset >= len) + break; + id += next_offset; gpa += byte_offset; len -= byte_offset; diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile index ff174996cdfd..b0ff5fbabb0c 100644 --- a/arch/riscv/boot/dts/Makefile +++ b/arch/riscv/boot/dts/Makefile @@ -3,5 +3,6 @@ subdir-y += sifive subdir-y += starfive subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan subdir-y += microchip +subdir-y += renesas obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y)) diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi index 24b1cfb9a73e..1069134f2e12 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi @@ -9,8 +9,8 @@ compatible = "microchip,corepwm-rtl-v4"; reg = <0x0 0x40000000 0x0 0xF0>; microchip,sync-update-mask = /bits/ 32 <0>; - #pwm-cells = <2>; - clocks = <&fabric_clk3>; + #pwm-cells = <3>; + clocks = <&ccc_nw CLK_CCC_PLL0_OUT3>; status = "disabled"; }; @@ -19,25 +19,13 @@ reg = <0x0 0x40000200 0x0 0x100>; #address-cells = <1>; #size-cells = <0>; - clocks = <&fabric_clk3>; + clocks = <&ccc_nw CLK_CCC_PLL0_OUT3>; interrupt-parent = <&plic>; interrupts = <122>; clock-frequency = <100000>; status = "disabled"; }; - fabric_clk3: fabric-clk3 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <50000000>; - }; - - fabric_clk1: fabric-clk1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - }; - pcie: pcie@3000000000 { compatible = "microchip,pcie-host-1.0"; #address-cells = <0x3>; @@ -54,7 +42,7 @@ <0 0 0 3 &pcie_intc 2>, <0 0 0 4 &pcie_intc 3>; interrupt-map-mask = <0 0 0 7>; - clocks = <&fabric_clk1>, <&fabric_clk3>; + clocks = <&ccc_nw CLK_CCC_PLL0_OUT1>, <&ccc_nw CLK_CCC_PLL0_OUT3>; clock-names = "fic1", "fic3"; ranges = <0x3000000 0x0 0x8000000 0x30 0x8000000 0x0 0x80000000>; dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 0x1 0x00000000>; @@ -67,4 +55,17 @@ interrupt-controller; }; }; + + refclk_ccc: cccrefclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; +}; + +&ccc_nw { + clocks = <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, + <&refclk_ccc>, <&refclk_ccc>; + clock-names = "pll0_ref0", "pll0_ref1", "pll1_ref0", "pll1_ref1", + "dll0_ref", "dll1_ref"; + status = "okay"; }; diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts index ec7b7c2a3ce2..90b261114763 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts @@ -5,6 +5,8 @@ #include "mpfs.dtsi" #include "mpfs-icicle-kit-fabric.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> /* Clock frequency (in Hz) of the rtcclk */ #define RTCCLK_FREQ 1000000 @@ -31,13 +33,41 @@ timebase-frequency = <RTCCLK_FREQ>; }; + leds { + compatible = "gpio-leds"; + + led-1 { + gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_RED>; + label = "led1"; + }; + + led-2 { + gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_RED>; + label = "led2"; + }; + + led-3 { + gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_AMBER>; + label = "led3"; + }; + + led-4 { + gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_AMBER>; + label = "led4"; + }; + }; + ddrc_cache_lo: memory@80000000 { device_type = "memory"; reg = <0x0 0x80000000 0x0 0x40000000>; status = "okay"; }; - ddrc_cache_hi: memory@1000000000 { + ddrc_cache_hi: memory@1040000000 { device_type = "memory"; reg = <0x10 0x40000000 0x0 0x40000000>; status = "okay"; @@ -149,6 +179,10 @@ clock-frequency = <125000000>; }; +&refclk_ccc { + clock-frequency = <50000000>; +}; + &rtc { status = "okay"; }; diff --git a/arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi index 7b9ee13b6a3a..8230f06ddf48 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi @@ -30,8 +30,8 @@ <0 0 0 3 &pcie_intc 2>, <0 0 0 4 &pcie_intc 3>; interrupt-map-mask = <0 0 0 7>; - clocks = <&fabric_clk1>, <&fabric_clk1>, <&fabric_clk3>; - clock-names = "fic0", "fic1", "fic3"; + clocks = <&fabric_clk1>, <&fabric_clk3>; + clock-names = "fic0", "fic3"; ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>; msi-parent = <&pcie>; msi-controller; diff --git a/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi index 67303bc0e451..9a56de7b91d6 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi @@ -30,8 +30,8 @@ <0 0 0 3 &pcie_intc 2>, <0 0 0 4 &pcie_intc 3>; interrupt-map-mask = <0 0 0 7>; - clocks = <&fabric_clk1>, <&fabric_clk1>, <&fabric_clk3>; - clock-names = "fic0", "fic1", "fic3"; + clocks = <&fabric_clk1>, <&fabric_clk3>; + clock-names = "fic0", "fic3"; ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>; msi-parent = <&pcie>; msi-controller; diff --git a/arch/riscv/boot/dts/microchip/mpfs-sev-kit-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-sev-kit-fabric.dtsi index 8545baf4d129..39a77df489ab 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-sev-kit-fabric.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs-sev-kit-fabric.dtsi @@ -13,33 +13,4 @@ #clock-cells = <0>; clock-frequency = <125000000>; }; - - pcie: pcie@2000000000 { - compatible = "microchip,pcie-host-1.0"; - #address-cells = <0x3>; - #interrupt-cells = <0x1>; - #size-cells = <0x2>; - device_type = "pci"; - reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>; - reg-names = "cfg", "apb"; - bus-range = <0x0 0x7f>; - interrupt-parent = <&plic>; - interrupts = <119>; - interrupt-map = <0 0 0 1 &pcie_intc 0>, - <0 0 0 2 &pcie_intc 1>, - <0 0 0 3 &pcie_intc 2>, - <0 0 0 4 &pcie_intc 3>; - interrupt-map-mask = <0 0 0 7>; - clocks = <&fabric_clk1>, <&fabric_clk1>, <&fabric_clk3>; - clock-names = "fic0", "fic1", "fic3"; - ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>; - msi-parent = <&pcie>; - msi-controller; - status = "disabled"; - pcie_intc: interrupt-controller { - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - }; - }; }; diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi index 8f463399a568..0a9bb84af438 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -236,6 +236,38 @@ #clock-cells = <1>; }; + ccc_se: clock-controller@38010000 { + compatible = "microchip,mpfs-ccc"; + reg = <0x0 0x38010000 0x0 0x1000>, <0x0 0x38020000 0x0 0x1000>, + <0x0 0x39010000 0x0 0x1000>, <0x0 0x39020000 0x0 0x1000>; + #clock-cells = <1>; + status = "disabled"; + }; + + ccc_ne: clock-controller@38040000 { + compatible = "microchip,mpfs-ccc"; + reg = <0x0 0x38040000 0x0 0x1000>, <0x0 0x38080000 0x0 0x1000>, + <0x0 0x39040000 0x0 0x1000>, <0x0 0x39080000 0x0 0x1000>; + #clock-cells = <1>; + status = "disabled"; + }; + + ccc_nw: clock-controller@38100000 { + compatible = "microchip,mpfs-ccc"; + reg = <0x0 0x38100000 0x0 0x1000>, <0x0 0x38200000 0x0 0x1000>, + <0x0 0x39100000 0x0 0x1000>, <0x0 0x39200000 0x0 0x1000>; + #clock-cells = <1>; + status = "disabled"; + }; + + ccc_sw: clock-controller@38400000 { + compatible = "microchip,mpfs-ccc"; + reg = <0x0 0x38400000 0x0 0x1000>, <0x0 0x38800000 0x0 0x1000>, + <0x0 0x39400000 0x0 0x1000>, <0x0 0x39800000 0x0 0x1000>; + #clock-cells = <1>; + status = "disabled"; + }; + mmuart0: serial@20000000 { compatible = "ns16550a"; reg = <0x0 0x20000000 0x0 0x400>; diff --git a/arch/riscv/boot/dts/renesas/Makefile b/arch/riscv/boot/dts/renesas/Makefile new file mode 100644 index 000000000000..2d3f5751a649 --- /dev/null +++ b/arch/riscv/boot/dts/renesas/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043f01-smarc.dtb diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi new file mode 100644 index 000000000000..6ec1c6f9a403 --- /dev/null +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/Five SoC + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +#include <dt-bindings/interrupt-controller/irq.h> + +#define SOC_PERIPHERAL_IRQ(nr) (nr + 32) + +#include <arm64/renesas/r9a07g043.dtsi> + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <12000000>; + + cpu0: cpu@0 { + compatible = "andestech,ax45mp", "riscv"; + device_type = "cpu"; + #cooling-cells = <2>; + reg = <0x0>; + status = "okay"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + i-cache-size = <0x8000>; + i-cache-line-size = <0x40>; + d-cache-size = <0x8000>; + d-cache-line-size = <0x40>; + clocks = <&cpg CPG_CORE R9A07G043_CLK_I>; + operating-points-v2 = <&cluster0_opp>; + + cpu0_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; +}; + +&soc { + interrupt-parent = <&plic>; + + plic: interrupt-controller@12c00000 { + compatible = "renesas,r9a07g043-plic", "andestech,nceplic100"; + #interrupt-cells = <2>; + #address-cells = <0>; + riscv,ndev = <511>; + interrupt-controller; + reg = <0x0 0x12c00000 0 0x400000>; + clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>; + power-domains = <&cpg>; + resets = <&cpg R9A07G043_NCEPLIC_ARESETN>; + interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>; + }; +}; diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts b/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts new file mode 100644 index 000000000000..2aa8515451d3 --- /dev/null +++ b/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/Five SMARC EVK + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +/dts-v1/; + +/* + * DIP-Switch SW1 setting + * 1 : High; 0: Low + * SW1-2 : SW_SD0_DEV_SEL (0: uSD; 1: eMMC) + * SW1-3 : SW_ET0_EN_N (0: ETHER0; 1: CAN0, CAN1, SSI1, RSPI1) + * Please change below macros according to SW1 setting on the SoM + */ +#define SW_SW0_DEV_SEL 1 +#define SW_ET0_EN_N 1 + +#include "r9a07g043f.dtsi" +#include "rzfive-smarc-som.dtsi" +#include "rzfive-smarc.dtsi" + +/ { + model = "Renesas SMARC EVK based on r9a07g043f01"; + compatible = "renesas,smarc-evk", "renesas,r9a07g043f01", "renesas,r9a07g043"; +}; diff --git a/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi new file mode 100644 index 000000000000..2b7672bc4b52 --- /dev/null +++ b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/Five SMARC EVK SOM + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +#include <arm64/renesas/rzg2ul-smarc-som.dtsi> + +/ { + aliases { + /delete-property/ ethernet0; + /delete-property/ ethernet1; + }; + + chosen { + bootargs = "ignore_loglevel"; + }; +}; + +&dmac { + status = "disabled"; +}; + +ð0 { + status = "disabled"; +}; + +ð1 { + status = "disabled"; +}; + +&ostm1 { + status = "disabled"; +}; + +&ostm2 { + status = "disabled"; +}; + +&sdhi0 { + status = "disabled"; +}; + +&wdt0 { + status = "disabled"; +}; diff --git a/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi b/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi new file mode 100644 index 000000000000..c07a487c4e5a --- /dev/null +++ b/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/Five SMARC EVK carrier board + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +#include <arm64/renesas/rzg2ul-smarc.dtsi> + +&ehci0 { + status = "disabled"; +}; + +&ehci1 { + status = "disabled"; +}; + +&hsusb { + status = "disabled"; +}; + +&ohci0 { + status = "disabled"; +}; + +&ohci1 { + status = "disabled"; +}; + +&phyrst { + status = "disabled"; +}; + +&sdhi1 { + status = "disabled"; +}; + +&snd_rzg2l { + status = "disabled"; +}; + +&spi1 { + status = "disabled"; +}; + +&ssi1 { + status = "disabled"; +}; + +&usb0_vbus_otg { + status = "disabled"; +}; + +&usb2_phy0 { + status = "disabled"; +}; + +&usb2_phy1 { + status = "disabled"; +}; + +&vccq_sdhi1 { + status = "disabled"; +}; diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile index 0ea1bc15ab30..039c143cba33 100644 --- a/arch/riscv/boot/dts/starfive/Makefile +++ b/arch/riscv/boot/dts/starfive/Makefile @@ -1,2 +1,2 @@ # SPDX-License-Identifier: GPL-2.0 -dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb +dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb jh7100-starfive-visionfive-v1.dtb diff --git a/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts b/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts index f7a230110512..7cda3a89020a 100644 --- a/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts +++ b/arch/riscv/boot/dts/starfive/jh7100-beaglev-starlight.dts @@ -5,160 +5,9 @@ */ /dts-v1/; -#include "jh7100.dtsi" -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/leds/common.h> -#include <dt-bindings/pinctrl/pinctrl-starfive-jh7100.h> +#include "jh7100-common.dtsi" / { model = "BeagleV Starlight Beta"; compatible = "beagle,beaglev-starlight-jh7100-r0", "starfive,jh7100"; - - aliases { - serial0 = &uart3; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - cpus { - timebase-frequency = <6250000>; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x0 0x80000000 0x2 0x0>; - }; - - leds { - compatible = "gpio-leds"; - - led-ack { - gpios = <&gpio 43 GPIO_ACTIVE_HIGH>; - color = <LED_COLOR_ID_GREEN>; - function = LED_FUNCTION_HEARTBEAT; - linux,default-trigger = "heartbeat"; - label = "ack"; - }; - }; -}; - -&gpio { - i2c0_pins: i2c0-0 { - i2c-pins { - pinmux = <GPIOMUX(62, GPO_LOW, - GPO_I2C0_PAD_SCK_OEN, - GPI_I2C0_PAD_SCK_IN)>, - <GPIOMUX(61, GPO_LOW, - GPO_I2C0_PAD_SDA_OEN, - GPI_I2C0_PAD_SDA_IN)>; - bias-disable; /* external pull-up */ - input-enable; - input-schmitt-enable; - }; - }; - - i2c1_pins: i2c1-0 { - i2c-pins { - pinmux = <GPIOMUX(47, GPO_LOW, - GPO_I2C1_PAD_SCK_OEN, - GPI_I2C1_PAD_SCK_IN)>, - <GPIOMUX(48, GPO_LOW, - GPO_I2C1_PAD_SDA_OEN, - GPI_I2C1_PAD_SDA_IN)>; - bias-pull-up; - input-enable; - input-schmitt-enable; - }; - }; - - i2c2_pins: i2c2-0 { - i2c-pins { - pinmux = <GPIOMUX(60, GPO_LOW, - GPO_I2C2_PAD_SCK_OEN, - GPI_I2C2_PAD_SCK_IN)>, - <GPIOMUX(59, GPO_LOW, - GPO_I2C2_PAD_SDA_OEN, - GPI_I2C2_PAD_SDA_IN)>; - bias-disable; /* external pull-up */ - input-enable; - input-schmitt-enable; - }; - }; - - uart3_pins: uart3-0 { - rx-pins { - pinmux = <GPIOMUX(13, GPO_LOW, GPO_DISABLE, - GPI_UART3_PAD_SIN)>; - bias-pull-up; - drive-strength = <14>; - input-enable; - input-schmitt-enable; - slew-rate = <0>; - }; - tx-pins { - pinmux = <GPIOMUX(14, GPO_UART3_PAD_SOUT, - GPO_ENABLE, GPI_NONE)>; - bias-disable; - drive-strength = <35>; - input-disable; - input-schmitt-disable; - slew-rate = <0>; - }; - }; -}; - -&i2c0 { - clock-frequency = <100000>; - i2c-sda-hold-time-ns = <300>; - i2c-sda-falling-time-ns = <500>; - i2c-scl-falling-time-ns = <500>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "okay"; - - pmic@5e { - compatible = "ti,tps65086"; - reg = <0x5e>; - gpio-controller; - #gpio-cells = <2>; - - regulators { - }; - }; -}; - -&i2c1 { - clock-frequency = <400000>; - i2c-sda-hold-time-ns = <300>; - i2c-sda-falling-time-ns = <100>; - i2c-scl-falling-time-ns = <100>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - status = "okay"; -}; - -&i2c2 { - clock-frequency = <100000>; - i2c-sda-hold-time-ns = <300>; - i2c-sda-falling-time-ns = <500>; - i2c-scl-falling-time-ns = <500>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - status = "okay"; -}; - -&osc_sys { - clock-frequency = <25000000>; -}; - -&osc_aud { - clock-frequency = <27000000>; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; - status = "okay"; }; diff --git a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi new file mode 100644 index 000000000000..b93ce351a90f --- /dev/null +++ b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2021 StarFive Technology Co., Ltd. + * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk> + */ + +/dts-v1/; +#include "jh7100.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/pinctrl-starfive-jh7100.h> + +/ { + aliases { + serial0 = &uart3; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + cpus { + timebase-frequency = <6250000>; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x2 0x0>; + }; + + leds { + compatible = "gpio-leds"; + + led-ack { + gpios = <&gpio 43 GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_HEARTBEAT; + linux,default-trigger = "heartbeat"; + label = "ack"; + }; + }; +}; + +&gpio { + i2c0_pins: i2c0-0 { + i2c-pins { + pinmux = <GPIOMUX(62, GPO_LOW, + GPO_I2C0_PAD_SCK_OEN, + GPI_I2C0_PAD_SCK_IN)>, + <GPIOMUX(61, GPO_LOW, + GPO_I2C0_PAD_SDA_OEN, + GPI_I2C0_PAD_SDA_IN)>; + bias-disable; /* external pull-up */ + input-enable; + input-schmitt-enable; + }; + }; + + i2c1_pins: i2c1-0 { + i2c-pins { + pinmux = <GPIOMUX(47, GPO_LOW, + GPO_I2C1_PAD_SCK_OEN, + GPI_I2C1_PAD_SCK_IN)>, + <GPIOMUX(48, GPO_LOW, + GPO_I2C1_PAD_SDA_OEN, + GPI_I2C1_PAD_SDA_IN)>; + bias-pull-up; + input-enable; + input-schmitt-enable; + }; + }; + + i2c2_pins: i2c2-0 { + i2c-pins { + pinmux = <GPIOMUX(60, GPO_LOW, + GPO_I2C2_PAD_SCK_OEN, + GPI_I2C2_PAD_SCK_IN)>, + <GPIOMUX(59, GPO_LOW, + GPO_I2C2_PAD_SDA_OEN, + GPI_I2C2_PAD_SDA_IN)>; + bias-disable; /* external pull-up */ + input-enable; + input-schmitt-enable; + }; + }; + + uart3_pins: uart3-0 { + rx-pins { + pinmux = <GPIOMUX(13, GPO_LOW, GPO_DISABLE, + GPI_UART3_PAD_SIN)>; + bias-pull-up; + drive-strength = <14>; + input-enable; + input-schmitt-enable; + slew-rate = <0>; + }; + tx-pins { + pinmux = <GPIOMUX(14, GPO_UART3_PAD_SOUT, + GPO_ENABLE, GPI_NONE)>; + bias-disable; + drive-strength = <35>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + }; +}; + +&i2c0 { + clock-frequency = <100000>; + i2c-sda-hold-time-ns = <300>; + i2c-sda-falling-time-ns = <500>; + i2c-scl-falling-time-ns = <500>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "okay"; + + pmic@5e { + compatible = "ti,tps65086"; + reg = <0x5e>; + gpio-controller; + #gpio-cells = <2>; + + regulators { + }; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + i2c-sda-hold-time-ns = <300>; + i2c-sda-falling-time-ns = <100>; + i2c-scl-falling-time-ns = <100>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <100000>; + i2c-sda-hold-time-ns = <300>; + i2c-sda-falling-time-ns = <500>; + i2c-scl-falling-time-ns = <500>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + status = "okay"; +}; + +&osc_sys { + clock-frequency = <25000000>; +}; + +&osc_aud { + clock-frequency = <27000000>; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; + status = "okay"; +}; diff --git a/arch/riscv/boot/dts/starfive/jh7100-starfive-visionfive-v1.dts b/arch/riscv/boot/dts/starfive/jh7100-starfive-visionfive-v1.dts new file mode 100644 index 000000000000..e82af72f1aaf --- /dev/null +++ b/arch/riscv/boot/dts/starfive/jh7100-starfive-visionfive-v1.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2021 StarFive Technology Co., Ltd. + * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk> + */ + +/dts-v1/; +#include "jh7100-common.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "StarFive VisionFive V1"; + compatible = "starfive,visionfive-v1", "starfive,jh7100"; + + gpio-restart { + compatible = "gpio-restart"; + gpios = <&gpio 63 GPIO_ACTIVE_HIGH>; + priority = <224>; + }; +}; diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h index 8a5c246b0a21..f6fbe7042f1c 100644 --- a/arch/riscv/include/asm/cacheflush.h +++ b/arch/riscv/include/asm/cacheflush.h @@ -42,16 +42,8 @@ void flush_icache_mm(struct mm_struct *mm, bool local); #endif /* CONFIG_SMP */ -/* - * The T-Head CMO errata internally probe the CBOM block size, but otherwise - * don't depend on Zicbom. - */ extern unsigned int riscv_cbom_block_size; -#ifdef CONFIG_RISCV_ISA_ZICBOM void riscv_init_cbom_blocksize(void); -#else -static inline void riscv_init_cbom_blocksize(void) { } -#endif #ifdef CONFIG_RISCV_DMA_NONCOHERENT void riscv_noncoherent_supported(void); diff --git a/arch/riscv/include/asm/kvm_vcpu_timer.h b/arch/riscv/include/asm/kvm_vcpu_timer.h index 0d8fdb8ec63a..82f7260301da 100644 --- a/arch/riscv/include/asm/kvm_vcpu_timer.h +++ b/arch/riscv/include/asm/kvm_vcpu_timer.h @@ -45,6 +45,7 @@ int kvm_riscv_vcpu_timer_deinit(struct kvm_vcpu *vcpu); int kvm_riscv_vcpu_timer_reset(struct kvm_vcpu *vcpu); void kvm_riscv_vcpu_timer_restore(struct kvm_vcpu *vcpu); void kvm_riscv_guest_timer_init(struct kvm *kvm); +void kvm_riscv_vcpu_timer_sync(struct kvm_vcpu *vcpu); void kvm_riscv_vcpu_timer_save(struct kvm_vcpu *vcpu); bool kvm_riscv_vcpu_timer_pending(struct kvm_vcpu *vcpu); diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index a032c4f0d600..71ebbc4821f0 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -708,6 +708,9 @@ void kvm_riscv_vcpu_sync_interrupts(struct kvm_vcpu *vcpu) clear_bit(IRQ_VS_SOFT, &v->irqs_pending); } } + + /* Sync-up timer CSRs */ + kvm_riscv_vcpu_timer_sync(vcpu); } int kvm_riscv_vcpu_set_interrupt(struct kvm_vcpu *vcpu, unsigned int irq) diff --git a/arch/riscv/kvm/vcpu_timer.c b/arch/riscv/kvm/vcpu_timer.c index 185f2386a747..ad34519c8a13 100644 --- a/arch/riscv/kvm/vcpu_timer.c +++ b/arch/riscv/kvm/vcpu_timer.c @@ -320,20 +320,33 @@ void kvm_riscv_vcpu_timer_restore(struct kvm_vcpu *vcpu) kvm_riscv_vcpu_timer_unblocking(vcpu); } -void kvm_riscv_vcpu_timer_save(struct kvm_vcpu *vcpu) +void kvm_riscv_vcpu_timer_sync(struct kvm_vcpu *vcpu) { struct kvm_vcpu_timer *t = &vcpu->arch.timer; if (!t->sstc_enabled) return; - t = &vcpu->arch.timer; #if defined(CONFIG_32BIT) t->next_cycles = csr_read(CSR_VSTIMECMP); t->next_cycles |= (u64)csr_read(CSR_VSTIMECMPH) << 32; #else t->next_cycles = csr_read(CSR_VSTIMECMP); #endif +} + +void kvm_riscv_vcpu_timer_save(struct kvm_vcpu *vcpu) +{ + struct kvm_vcpu_timer *t = &vcpu->arch.timer; + + if (!t->sstc_enabled) + return; + + /* + * The vstimecmp CSRs are saved by kvm_riscv_vcpu_timer_sync() + * upon every VM exit so no need to save here. + */ + /* timer should be enabled for the remaining operations */ if (unlikely(!t->init_done)) return; diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c index 6cb7d96ad9c7..57b40a350420 100644 --- a/arch/riscv/mm/cacheflush.c +++ b/arch/riscv/mm/cacheflush.c @@ -3,6 +3,7 @@ * Copyright (C) 2017 SiFive */ +#include <linux/of.h> #include <asm/cacheflush.h> #ifdef CONFIG_SMP @@ -86,3 +87,40 @@ void flush_icache_pte(pte_t pte) flush_icache_all(); } #endif /* CONFIG_MMU */ + +unsigned int riscv_cbom_block_size; +EXPORT_SYMBOL_GPL(riscv_cbom_block_size); + +void riscv_init_cbom_blocksize(void) +{ + struct device_node *node; + unsigned long cbom_hartid; + u32 val, probed_block_size; + int ret; + + probed_block_size = 0; + for_each_of_cpu_node(node) { + unsigned long hartid; + + ret = riscv_of_processor_hartid(node, &hartid); + if (ret) + continue; + + /* set block-size for cbom extension if available */ + ret = of_property_read_u32(node, "riscv,cbom-block-size", &val); + if (ret) + continue; + + if (!probed_block_size) { + probed_block_size = val; + cbom_hartid = hartid; + } else { + if (probed_block_size != val) + pr_warn("cbom-block-size mismatched between harts %lu and %lu\n", + cbom_hartid, hartid); + } + } + + if (probed_block_size) + riscv_cbom_block_size = probed_block_size; +} diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c index b0add983530a..d919efab6eba 100644 --- a/arch/riscv/mm/dma-noncoherent.c +++ b/arch/riscv/mm/dma-noncoherent.c @@ -8,13 +8,8 @@ #include <linux/dma-direct.h> #include <linux/dma-map-ops.h> #include <linux/mm.h> -#include <linux/of.h> -#include <linux/of_device.h> #include <asm/cacheflush.h> -unsigned int riscv_cbom_block_size; -EXPORT_SYMBOL_GPL(riscv_cbom_block_size); - static bool noncoherent_supported; void arch_sync_dma_for_device(phys_addr_t paddr, size_t size, @@ -77,42 +72,6 @@ void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size, dev->dma_coherent = coherent; } -#ifdef CONFIG_RISCV_ISA_ZICBOM -void riscv_init_cbom_blocksize(void) -{ - struct device_node *node; - unsigned long cbom_hartid; - u32 val, probed_block_size; - int ret; - - probed_block_size = 0; - for_each_of_cpu_node(node) { - unsigned long hartid; - - ret = riscv_of_processor_hartid(node, &hartid); - if (ret) - continue; - - /* set block-size for cbom extension if available */ - ret = of_property_read_u32(node, "riscv,cbom-block-size", &val); - if (ret) - continue; - - if (!probed_block_size) { - probed_block_size = val; - cbom_hartid = hartid; - } else { - if (probed_block_size != val) - pr_warn("cbom-block-size mismatched between harts %lu and %lu\n", - cbom_hartid, hartid); - } - } - - if (probed_block_size) - riscv_cbom_block_size = probed_block_size; -} -#endif - void riscv_noncoherent_supported(void) { WARN(!riscv_cbom_block_size, diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 6d1879ef933a..67745ceab0db 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1973,7 +1973,6 @@ config EFI config EFI_STUB bool "EFI stub support" depends on EFI - depends on $(cc-option,-mabi=ms) || X86_32 select RELOCATABLE help This kernel feature allows a bzImage to be loaded directly diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c index 4fce1a4226e3..8259d725054d 100644 --- a/arch/x86/events/intel/lbr.c +++ b/arch/x86/events/intel/lbr.c @@ -1596,7 +1596,7 @@ void __init intel_pmu_arch_lbr_init(void) return; clear_arch_lbr: - clear_cpu_cap(&boot_cpu_data, X86_FEATURE_ARCH_LBR); + setup_clear_cpu_cap(X86_FEATURE_ARCH_LBR); } /** diff --git a/arch/x86/include/asm/iommu.h b/arch/x86/include/asm/iommu.h index 0bef44d30a27..2fd52b65deac 100644 --- a/arch/x86/include/asm/iommu.h +++ b/arch/x86/include/asm/iommu.h @@ -25,8 +25,10 @@ arch_rmrr_sanity_check(struct acpi_dmar_reserved_memory *rmrr) { u64 start = rmrr->base_address; u64 end = rmrr->end_address + 1; + int entry_type; - if (e820__mapped_all(start, end, E820_TYPE_RESERVED)) + entry_type = e820__get_entry_type(start, end); + if (entry_type == E820_TYPE_RESERVED || entry_type == E820_TYPE_NVS) return 0; pr_err(FW_BUG "No firmware reserved region can cover this RMRR [%#018Lx-%#018Lx], contact BIOS vendor for fixes\n", diff --git a/arch/x86/kernel/cpu/microcode/amd.c b/arch/x86/kernel/cpu/microcode/amd.c index e7410e98fc1f..3a35dec3ec55 100644 --- a/arch/x86/kernel/cpu/microcode/amd.c +++ b/arch/x86/kernel/cpu/microcode/amd.c @@ -440,7 +440,13 @@ apply_microcode_early_amd(u32 cpuid_1_eax, void *ucode, size_t size, bool save_p return ret; native_rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy); - if (rev >= mc->hdr.patch_id) + + /* + * Allow application of the same revision to pick up SMT-specific + * changes even if the revision of the other SMT thread is already + * up-to-date. + */ + if (rev > mc->hdr.patch_id) return ret; if (!__apply_microcode_amd(mc)) { @@ -528,8 +534,12 @@ void load_ucode_amd_ap(unsigned int cpuid_1_eax) native_rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy); - /* Check whether we have saved a new patch already: */ - if (*new_rev && rev < mc->hdr.patch_id) { + /* + * Check whether a new patch has been saved already. Also, allow application of + * the same revision in order to pick up SMT-thread-specific configuration even + * if the sibling SMT thread already has an up-to-date revision. + */ + if (*new_rev && rev <= mc->hdr.patch_id) { if (!__apply_microcode_amd(mc)) { *new_rev = mc->hdr.patch_id; return; diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resctrl/core.c index de62b0b87ced..3266ea36667c 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -66,9 +66,6 @@ struct rdt_hw_resource rdt_resources_all[] = { .rid = RDT_RESOURCE_L3, .name = "L3", .cache_level = 3, - .cache = { - .min_cbm_bits = 1, - }, .domains = domain_init(RDT_RESOURCE_L3), .parse_ctrlval = parse_cbm, .format_str = "%d=%0*x", @@ -83,9 +80,6 @@ struct rdt_hw_resource rdt_resources_all[] = { .rid = RDT_RESOURCE_L2, .name = "L2", .cache_level = 2, - .cache = { - .min_cbm_bits = 1, - }, .domains = domain_init(RDT_RESOURCE_L2), .parse_ctrlval = parse_cbm, .format_str = "%d=%0*x", @@ -836,6 +830,7 @@ static __init void rdt_init_res_defs_intel(void) r->cache.arch_has_sparse_bitmaps = false; r->cache.arch_has_empty_bitmaps = false; r->cache.arch_has_per_cpu_cfg = false; + r->cache.min_cbm_bits = 1; } else if (r->rid == RDT_RESOURCE_MBA) { hw_res->msr_base = MSR_IA32_MBA_THRTL_BASE; hw_res->msr_update = mba_wrmsr_intel; @@ -856,6 +851,7 @@ static __init void rdt_init_res_defs_amd(void) r->cache.arch_has_sparse_bitmaps = true; r->cache.arch_has_empty_bitmaps = true; r->cache.arch_has_per_cpu_cfg = true; + r->cache.min_cbm_bits = 0; } else if (r->rid == RDT_RESOURCE_MBA) { hw_res->msr_base = MSR_IA32_MBA_BW_BASE; hw_res->msr_update = mba_wrmsr_amd; diff --git a/arch/x86/kernel/cpu/topology.c b/arch/x86/kernel/cpu/topology.c index 132a2de44d2f..5e868b62a7c4 100644 --- a/arch/x86/kernel/cpu/topology.c +++ b/arch/x86/kernel/cpu/topology.c @@ -96,6 +96,7 @@ int detect_extended_topology(struct cpuinfo_x86 *c) unsigned int ht_mask_width, core_plus_mask_width, die_plus_mask_width; unsigned int core_select_mask, core_level_siblings; unsigned int die_select_mask, die_level_siblings; + unsigned int pkg_mask_width; bool die_level_present = false; int leaf; @@ -111,10 +112,10 @@ int detect_extended_topology(struct cpuinfo_x86 *c) core_level_siblings = smp_num_siblings = LEVEL_MAX_SIBLINGS(ebx); core_plus_mask_width = ht_mask_width = BITS_SHIFT_NEXT_LEVEL(eax); die_level_siblings = LEVEL_MAX_SIBLINGS(ebx); - die_plus_mask_width = BITS_SHIFT_NEXT_LEVEL(eax); + pkg_mask_width = die_plus_mask_width = BITS_SHIFT_NEXT_LEVEL(eax); sub_index = 1; - do { + while (true) { cpuid_count(leaf, sub_index, &eax, &ebx, &ecx, &edx); /* @@ -132,10 +133,15 @@ int detect_extended_topology(struct cpuinfo_x86 *c) die_plus_mask_width = BITS_SHIFT_NEXT_LEVEL(eax); } + if (LEAFB_SUBTYPE(ecx) != INVALID_TYPE) + pkg_mask_width = BITS_SHIFT_NEXT_LEVEL(eax); + else + break; + sub_index++; - } while (LEAFB_SUBTYPE(ecx) != INVALID_TYPE); + } - core_select_mask = (~(-1 << core_plus_mask_width)) >> ht_mask_width; + core_select_mask = (~(-1 << pkg_mask_width)) >> ht_mask_width; die_select_mask = (~(-1 << die_plus_mask_width)) >> core_plus_mask_width; @@ -148,7 +154,7 @@ int detect_extended_topology(struct cpuinfo_x86 *c) } c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, - die_plus_mask_width); + pkg_mask_width); /* * Reinit the apicid, now that we have extended initial_apicid. */ diff --git a/arch/x86/kernel/fpu/init.c b/arch/x86/kernel/fpu/init.c index 621f4b6cac4a..8946f89761cc 100644 --- a/arch/x86/kernel/fpu/init.c +++ b/arch/x86/kernel/fpu/init.c @@ -210,13 +210,6 @@ static void __init fpu__init_system_xstate_size_legacy(void) fpstate_reset(¤t->thread.fpu); } -static void __init fpu__init_init_fpstate(void) -{ - /* Bring init_fpstate size and features up to date */ - init_fpstate.size = fpu_kernel_cfg.max_size; - init_fpstate.xfeatures = fpu_kernel_cfg.max_features; -} - /* * Called on the boot CPU once per system bootup, to set up the initial * FPU state that is later cloned into all processes: @@ -236,5 +229,4 @@ void __init fpu__init_system(struct cpuinfo_x86 *c) fpu__init_system_xstate_size_legacy(); fpu__init_system_xstate(fpu_kernel_cfg.max_size); fpu__init_task_struct_size(); - fpu__init_init_fpstate(); } diff --git a/arch/x86/kernel/fpu/xstate.c b/arch/x86/kernel/fpu/xstate.c index c8340156bfd2..59e543b95a3c 100644 --- a/arch/x86/kernel/fpu/xstate.c +++ b/arch/x86/kernel/fpu/xstate.c @@ -360,7 +360,7 @@ static void __init setup_init_fpu_buf(void) print_xstate_features(); - xstate_init_xcomp_bv(&init_fpstate.regs.xsave, fpu_kernel_cfg.max_features); + xstate_init_xcomp_bv(&init_fpstate.regs.xsave, init_fpstate.xfeatures); /* * Init all the features state with header.xfeatures being 0x0 @@ -678,20 +678,6 @@ static unsigned int __init get_xsave_size_user(void) return ebx; } -/* - * Will the runtime-enumerated 'xstate_size' fit in the init - * task's statically-allocated buffer? - */ -static bool __init is_supported_xstate_size(unsigned int test_xstate_size) -{ - if (test_xstate_size <= sizeof(init_fpstate.regs)) - return true; - - pr_warn("x86/fpu: xstate buffer too small (%zu < %d), disabling xsave\n", - sizeof(init_fpstate.regs), test_xstate_size); - return false; -} - static int __init init_xstate_size(void) { /* Recompute the context size for enabled features: */ @@ -717,10 +703,6 @@ static int __init init_xstate_size(void) kernel_default_size = xstate_calculate_size(fpu_kernel_cfg.default_features, compacted); - /* Ensure we have the space to store all default enabled features. */ - if (!is_supported_xstate_size(kernel_default_size)) - return -EINVAL; - if (!paranoid_xstate_size_valid(kernel_size)) return -EINVAL; @@ -875,6 +857,19 @@ void __init fpu__init_system_xstate(unsigned int legacy_size) update_regset_xstate_info(fpu_user_cfg.max_size, fpu_user_cfg.max_features); + /* + * init_fpstate excludes dynamic states as they are large but init + * state is zero. + */ + init_fpstate.size = fpu_kernel_cfg.default_size; + init_fpstate.xfeatures = fpu_kernel_cfg.default_features; + + if (init_fpstate.size > sizeof(init_fpstate.regs)) { + pr_warn("x86/fpu: init_fpstate buffer too small (%zu < %d), disabling XSAVE\n", + sizeof(init_fpstate.regs), init_fpstate.size); + goto out_disable; + } + setup_init_fpu_buf(); /* @@ -1130,6 +1125,15 @@ void __copy_xstate_to_uabi_buf(struct membuf to, struct fpstate *fpstate, */ mask = fpstate->user_xfeatures; + /* + * Dynamic features are not present in init_fpstate. When they are + * in an all zeros init state, remove those from 'mask' to zero + * those features in the user buffer instead of retrieving them + * from init_fpstate. + */ + if (fpu_state_size_dynamic()) + mask &= (header.xfeatures | xinit->header.xcomp_bv); + for_each_extended_xfeature(i, mask) { /* * If there was a feature or alignment gap, zero the space diff --git a/arch/x86/kernel/ftrace_64.S b/arch/x86/kernel/ftrace_64.S index dfeb227de561..2a4be92fd144 100644 --- a/arch/x86/kernel/ftrace_64.S +++ b/arch/x86/kernel/ftrace_64.S @@ -4,6 +4,7 @@ */ #include <linux/linkage.h> +#include <linux/cfi_types.h> #include <asm/ptrace.h> #include <asm/ftrace.h> #include <asm/export.h> @@ -129,6 +130,14 @@ .endm +SYM_TYPED_FUNC_START(ftrace_stub) + RET +SYM_FUNC_END(ftrace_stub) + +SYM_TYPED_FUNC_START(ftrace_stub_graph) + RET +SYM_FUNC_END(ftrace_stub_graph) + #ifdef CONFIG_DYNAMIC_FTRACE SYM_FUNC_START(__fentry__) @@ -172,21 +181,10 @@ SYM_INNER_LABEL(ftrace_call, SYM_L_GLOBAL) */ SYM_INNER_LABEL(ftrace_caller_end, SYM_L_GLOBAL) ANNOTATE_NOENDBR - - jmp ftrace_epilogue + RET SYM_FUNC_END(ftrace_caller); STACK_FRAME_NON_STANDARD_FP(ftrace_caller) -SYM_FUNC_START(ftrace_epilogue) -/* - * This is weak to keep gas from relaxing the jumps. - */ -SYM_INNER_LABEL_ALIGN(ftrace_stub, SYM_L_WEAK) - UNWIND_HINT_FUNC - ENDBR - RET -SYM_FUNC_END(ftrace_epilogue) - SYM_FUNC_START(ftrace_regs_caller) /* Save the current flags before any operations that can change them */ pushfq @@ -262,14 +260,11 @@ SYM_INNER_LABEL(ftrace_regs_caller_jmp, SYM_L_GLOBAL) popfq /* - * As this jmp to ftrace_epilogue can be a short jump - * it must not be copied into the trampoline. - * The trampoline will add the code to jump - * to the return. + * The trampoline will add the return. */ SYM_INNER_LABEL(ftrace_regs_caller_end, SYM_L_GLOBAL) ANNOTATE_NOENDBR - jmp ftrace_epilogue + RET /* Swap the flags with orig_rax */ 1: movq MCOUNT_REG_SIZE(%rsp), %rdi @@ -280,7 +275,7 @@ SYM_INNER_LABEL(ftrace_regs_caller_end, SYM_L_GLOBAL) /* Restore flags */ popfq UNWIND_HINT_FUNC - jmp ftrace_epilogue + RET SYM_FUNC_END(ftrace_regs_caller) STACK_FRAME_NON_STANDARD_FP(ftrace_regs_caller) @@ -291,9 +286,6 @@ STACK_FRAME_NON_STANDARD_FP(ftrace_regs_caller) SYM_FUNC_START(__fentry__) cmpq $ftrace_stub, ftrace_trace_function jnz trace - -SYM_INNER_LABEL(ftrace_stub, SYM_L_GLOBAL) - ENDBR RET trace: diff --git a/arch/x86/kernel/unwind_orc.c b/arch/x86/kernel/unwind_orc.c index 0ea57da92940..c059820dfaea 100644 --- a/arch/x86/kernel/unwind_orc.c +++ b/arch/x86/kernel/unwind_orc.c @@ -713,7 +713,7 @@ void __unwind_start(struct unwind_state *state, struct task_struct *task, /* Otherwise, skip ahead to the user-specified starting frame: */ while (!unwind_done(state) && (!on_stack(&state->stack_info, first_frame, sizeof(long)) || - state->sp < (unsigned long)first_frame)) + state->sp <= (unsigned long)first_frame)) unwind_next_frame(state); return; diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 4bd5f8a751de..9cf1ba865562 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -6442,26 +6442,22 @@ static int kvm_add_msr_filter(struct kvm_x86_msr_filter *msr_filter, return 0; } -static int kvm_vm_ioctl_set_msr_filter(struct kvm *kvm, void __user *argp) +static int kvm_vm_ioctl_set_msr_filter(struct kvm *kvm, + struct kvm_msr_filter *filter) { - struct kvm_msr_filter __user *user_msr_filter = argp; struct kvm_x86_msr_filter *new_filter, *old_filter; - struct kvm_msr_filter filter; bool default_allow; bool empty = true; int r = 0; u32 i; - if (copy_from_user(&filter, user_msr_filter, sizeof(filter))) - return -EFAULT; - - if (filter.flags & ~KVM_MSR_FILTER_DEFAULT_DENY) + if (filter->flags & ~KVM_MSR_FILTER_DEFAULT_DENY) return -EINVAL; - for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) - empty &= !filter.ranges[i].nmsrs; + for (i = 0; i < ARRAY_SIZE(filter->ranges); i++) + empty &= !filter->ranges[i].nmsrs; - default_allow = !(filter.flags & KVM_MSR_FILTER_DEFAULT_DENY); + default_allow = !(filter->flags & KVM_MSR_FILTER_DEFAULT_DENY); if (empty && !default_allow) return -EINVAL; @@ -6469,8 +6465,8 @@ static int kvm_vm_ioctl_set_msr_filter(struct kvm *kvm, void __user *argp) if (!new_filter) return -ENOMEM; - for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) { - r = kvm_add_msr_filter(new_filter, &filter.ranges[i]); + for (i = 0; i < ARRAY_SIZE(filter->ranges); i++) { + r = kvm_add_msr_filter(new_filter, &filter->ranges[i]); if (r) { kvm_free_msr_filter(new_filter); return r; @@ -6493,6 +6489,62 @@ static int kvm_vm_ioctl_set_msr_filter(struct kvm *kvm, void __user *argp) return 0; } +#ifdef CONFIG_KVM_COMPAT +/* for KVM_X86_SET_MSR_FILTER */ +struct kvm_msr_filter_range_compat { + __u32 flags; + __u32 nmsrs; + __u32 base; + __u32 bitmap; +}; + +struct kvm_msr_filter_compat { + __u32 flags; + struct kvm_msr_filter_range_compat ranges[KVM_MSR_FILTER_MAX_RANGES]; +}; + +#define KVM_X86_SET_MSR_FILTER_COMPAT _IOW(KVMIO, 0xc6, struct kvm_msr_filter_compat) + +long kvm_arch_vm_compat_ioctl(struct file *filp, unsigned int ioctl, + unsigned long arg) +{ + void __user *argp = (void __user *)arg; + struct kvm *kvm = filp->private_data; + long r = -ENOTTY; + + switch (ioctl) { + case KVM_X86_SET_MSR_FILTER_COMPAT: { + struct kvm_msr_filter __user *user_msr_filter = argp; + struct kvm_msr_filter_compat filter_compat; + struct kvm_msr_filter filter; + int i; + + if (copy_from_user(&filter_compat, user_msr_filter, + sizeof(filter_compat))) + return -EFAULT; + + filter.flags = filter_compat.flags; + for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) { + struct kvm_msr_filter_range_compat *cr; + + cr = &filter_compat.ranges[i]; + filter.ranges[i] = (struct kvm_msr_filter_range) { + .flags = cr->flags, + .nmsrs = cr->nmsrs, + .base = cr->base, + .bitmap = (__u8 *)(ulong)cr->bitmap, + }; + } + + r = kvm_vm_ioctl_set_msr_filter(kvm, &filter); + break; + } + } + + return r; +} +#endif + #ifdef CONFIG_HAVE_KVM_PM_NOTIFIER static int kvm_arch_suspend_notifier(struct kvm *kvm) { @@ -6915,9 +6967,16 @@ set_pit2_out: case KVM_SET_PMU_EVENT_FILTER: r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp); break; - case KVM_X86_SET_MSR_FILTER: - r = kvm_vm_ioctl_set_msr_filter(kvm, argp); + case KVM_X86_SET_MSR_FILTER: { + struct kvm_msr_filter __user *user_msr_filter = argp; + struct kvm_msr_filter filter; + + if (copy_from_user(&filter, user_msr_filter, sizeof(filter))) + return -EFAULT; + + r = kvm_vm_ioctl_set_msr_filter(kvm, &filter); break; + } default: r = -ENOTTY; } |