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Diffstat (limited to 'arch/mips/kvm/emulate.c')
-rw-r--r--arch/mips/kvm/emulate.c1672
1 files changed, 16 insertions, 1656 deletions
diff --git a/arch/mips/kvm/emulate.c b/arch/mips/kvm/emulate.c
index d70c4f8e14e2..22e745e49b0a 100644
--- a/arch/mips/kvm/emulate.c
+++ b/arch/mips/kvm/emulate.c
@@ -30,7 +30,6 @@
#define CONFIG_MIPS_MT
#include "interrupt.h"
-#include "commpage.h"
#include "trace.h"
@@ -276,7 +275,8 @@ int kvm_get_badinstr(u32 *opc, struct kvm_vcpu *vcpu, u32 *out)
*out = vcpu->arch.host_cp0_badinstr;
return 0;
} else {
- return kvm_get_inst(opc, vcpu, out);
+ WARN_ONCE(1, "CPU doesn't have BadInstr register\n");
+ return -EINVAL;
}
}
@@ -297,7 +297,8 @@ int kvm_get_badinstrp(u32 *opc, struct kvm_vcpu *vcpu, u32 *out)
*out = vcpu->arch.host_cp0_badinstrp;
return 0;
} else {
- return kvm_get_inst(opc, vcpu, out);
+ WARN_ONCE(1, "CPU doesn't have BadInstrp register\n");
+ return -EINVAL;
}
}
@@ -721,7 +722,7 @@ void kvm_mips_write_compare(struct kvm_vcpu *vcpu, u32 compare, bool ack)
* preemption until the new value is written to prevent restore of a
* GTOffset corresponding to the old CP0_Compare value.
*/
- if (IS_ENABLED(CONFIG_KVM_MIPS_VZ) && delta > 0) {
+ if (delta > 0) {
preempt_disable();
write_c0_gtoffset(compare - read_c0_count());
back_to_back_c0_hazard();
@@ -734,7 +735,7 @@ void kvm_mips_write_compare(struct kvm_vcpu *vcpu, u32 compare, bool ack)
if (ack)
kvm_mips_callbacks->dequeue_timer_int(vcpu);
- else if (IS_ENABLED(CONFIG_KVM_MIPS_VZ))
+ else
/*
* With VZ, writing CP0_Compare acks (clears) CP0_Cause.TI, so
* preserve guest CP0_Cause.TI if we don't want to ack it.
@@ -743,15 +744,13 @@ void kvm_mips_write_compare(struct kvm_vcpu *vcpu, u32 compare, bool ack)
kvm_write_c0_guest_compare(cop0, compare);
- if (IS_ENABLED(CONFIG_KVM_MIPS_VZ)) {
- if (delta > 0)
- preempt_enable();
+ if (delta > 0)
+ preempt_enable();
- back_to_back_c0_hazard();
+ back_to_back_c0_hazard();
- if (!ack && cause & CAUSEF_TI)
- kvm_write_c0_guest_cause(cop0, cause);
- }
+ if (!ack && cause & CAUSEF_TI)
+ kvm_write_c0_guest_cause(cop0, cause);
/* resume_hrtimer() takes care of timer interrupts > count */
if (!dc)
@@ -762,7 +761,7 @@ void kvm_mips_write_compare(struct kvm_vcpu *vcpu, u32 compare, bool ack)
* until after the new CP0_Compare is written, otherwise new guest
* CP0_Count could hit new guest CP0_Compare.
*/
- if (IS_ENABLED(CONFIG_KVM_MIPS_VZ) && delta <= 0)
+ if (delta <= 0)
write_c0_gtoffset(compare - read_c0_count());
}
@@ -943,29 +942,6 @@ enum hrtimer_restart kvm_mips_count_timeout(struct kvm_vcpu *vcpu)
return HRTIMER_RESTART;
}
-enum emulation_result kvm_mips_emul_eret(struct kvm_vcpu *vcpu)
-{
- struct mips_coproc *cop0 = vcpu->arch.cop0;
- enum emulation_result er = EMULATE_DONE;
-
- if (kvm_read_c0_guest_status(cop0) & ST0_ERL) {
- kvm_clear_c0_guest_status(cop0, ST0_ERL);
- vcpu->arch.pc = kvm_read_c0_guest_errorepc(cop0);
- } else if (kvm_read_c0_guest_status(cop0) & ST0_EXL) {
- kvm_debug("[%#lx] ERET to %#lx\n", vcpu->arch.pc,
- kvm_read_c0_guest_epc(cop0));
- kvm_clear_c0_guest_status(cop0, ST0_EXL);
- vcpu->arch.pc = kvm_read_c0_guest_epc(cop0);
-
- } else {
- kvm_err("[%#lx] ERET when MIPS_SR_EXL|MIPS_SR_ERL == 0\n",
- vcpu->arch.pc);
- er = EMULATE_FAIL;
- }
-
- return er;
-}
-
enum emulation_result kvm_mips_emul_wait(struct kvm_vcpu *vcpu)
{
kvm_debug("[%#lx] !!!WAIT!!! (%#lx)\n", vcpu->arch.pc,
@@ -991,609 +967,6 @@ enum emulation_result kvm_mips_emul_wait(struct kvm_vcpu *vcpu)
return EMULATE_DONE;
}
-static void kvm_mips_change_entryhi(struct kvm_vcpu *vcpu,
- unsigned long entryhi)
-{
- struct mips_coproc *cop0 = vcpu->arch.cop0;
- struct mm_struct *kern_mm = &vcpu->arch.guest_kernel_mm;
- int cpu, i;
- u32 nasid = entryhi & KVM_ENTRYHI_ASID;
-
- if (((kvm_read_c0_guest_entryhi(cop0) & KVM_ENTRYHI_ASID) != nasid)) {
- trace_kvm_asid_change(vcpu, kvm_read_c0_guest_entryhi(cop0) &
- KVM_ENTRYHI_ASID, nasid);
-
- /*
- * Flush entries from the GVA page tables.
- * Guest user page table will get flushed lazily on re-entry to
- * guest user if the guest ASID actually changes.
- */
- kvm_mips_flush_gva_pt(kern_mm->pgd, KMF_KERN);
-
- /*
- * Regenerate/invalidate kernel MMU context.
- * The user MMU context will be regenerated lazily on re-entry
- * to guest user if the guest ASID actually changes.
- */
- preempt_disable();
- cpu = smp_processor_id();
- get_new_mmu_context(kern_mm);
- for_each_possible_cpu(i)
- if (i != cpu)
- set_cpu_context(i, kern_mm, 0);
- preempt_enable();
- }
- kvm_write_c0_guest_entryhi(cop0, entryhi);
-}
-
-enum emulation_result kvm_mips_emul_tlbr(struct kvm_vcpu *vcpu)
-{
- struct mips_coproc *cop0 = vcpu->arch.cop0;
- struct kvm_mips_tlb *tlb;
- unsigned long pc = vcpu->arch.pc;
- int index;
-
- index = kvm_read_c0_guest_index(cop0);
- if (index < 0 || index >= KVM_MIPS_GUEST_TLB_SIZE) {
- /* UNDEFINED */
- kvm_debug("[%#lx] TLBR Index %#x out of range\n", pc, index);
- index &= KVM_MIPS_GUEST_TLB_SIZE - 1;
- }
-
- tlb = &vcpu->arch.guest_tlb[index];
- kvm_write_c0_guest_pagemask(cop0, tlb->tlb_mask);
- kvm_write_c0_guest_entrylo0(cop0, tlb->tlb_lo[0]);
- kvm_write_c0_guest_entrylo1(cop0, tlb->tlb_lo[1]);
- kvm_mips_change_entryhi(vcpu, tlb->tlb_hi);
-
- return EMULATE_DONE;
-}
-
-/**
- * kvm_mips_invalidate_guest_tlb() - Indicates a change in guest MMU map.
- * @vcpu: VCPU with changed mappings.
- * @tlb: TLB entry being removed.
- *
- * This is called to indicate a single change in guest MMU mappings, so that we
- * can arrange TLB flushes on this and other CPUs.
- */
-static void kvm_mips_invalidate_guest_tlb(struct kvm_vcpu *vcpu,
- struct kvm_mips_tlb *tlb)
-{
- struct mm_struct *kern_mm = &vcpu->arch.guest_kernel_mm;
- struct mm_struct *user_mm = &vcpu->arch.guest_user_mm;
- int cpu, i;
- bool user;
-
- /* No need to flush for entries which are already invalid */
- if (!((tlb->tlb_lo[0] | tlb->tlb_lo[1]) & ENTRYLO_V))
- return;
- /* Don't touch host kernel page tables or TLB mappings */
- if ((unsigned long)tlb->tlb_hi > 0x7fffffff)
- return;
- /* User address space doesn't need flushing for KSeg2/3 changes */
- user = tlb->tlb_hi < KVM_GUEST_KSEG0;
-
- preempt_disable();
-
- /* Invalidate page table entries */
- kvm_trap_emul_invalidate_gva(vcpu, tlb->tlb_hi & VPN2_MASK, user);
-
- /*
- * Probe the shadow host TLB for the entry being overwritten, if one
- * matches, invalidate it
- */
- kvm_mips_host_tlb_inv(vcpu, tlb->tlb_hi, user, true);
-
- /* Invalidate the whole ASID on other CPUs */
- cpu = smp_processor_id();
- for_each_possible_cpu(i) {
- if (i == cpu)
- continue;
- if (user)
- set_cpu_context(i, user_mm, 0);
- set_cpu_context(i, kern_mm, 0);
- }
-
- preempt_enable();
-}
-
-/* Write Guest TLB Entry @ Index */
-enum emulation_result kvm_mips_emul_tlbwi(struct kvm_vcpu *vcpu)
-{
- struct mips_coproc *cop0 = vcpu->arch.cop0;
- int index = kvm_read_c0_guest_index(cop0);
- struct kvm_mips_tlb *tlb = NULL;
- unsigned long pc = vcpu->arch.pc;
-
- if (index < 0 || index >= KVM_MIPS_GUEST_TLB_SIZE) {
- kvm_debug("%s: illegal index: %d\n", __func__, index);
- kvm_debug("[%#lx] COP0_TLBWI [%d] (entryhi: %#lx, entrylo0: %#lx entrylo1: %#lx, mask: %#lx)\n",
- pc, index, kvm_read_c0_guest_entryhi(cop0),
- kvm_read_c0_guest_entrylo0(cop0),
- kvm_read_c0_guest_entrylo1(cop0),
- kvm_read_c0_guest_pagemask(cop0));
- index = (index & ~0x80000000) % KVM_MIPS_GUEST_TLB_SIZE;
- }
-
- tlb = &vcpu->arch.guest_tlb[index];
-
- kvm_mips_invalidate_guest_tlb(vcpu, tlb);
-
- tlb->tlb_mask = kvm_read_c0_guest_pagemask(cop0);
- tlb->tlb_hi = kvm_read_c0_guest_entryhi(cop0);
- tlb->tlb_lo[0] = kvm_read_c0_guest_entrylo0(cop0);
- tlb->tlb_lo[1] = kvm_read_c0_guest_entrylo1(cop0);
-
- kvm_debug("[%#lx] COP0_TLBWI [%d] (entryhi: %#lx, entrylo0: %#lx entrylo1: %#lx, mask: %#lx)\n",
- pc, index, kvm_read_c0_guest_entryhi(cop0),
- kvm_read_c0_guest_entrylo0(cop0),
- kvm_read_c0_guest_entrylo1(cop0),
- kvm_read_c0_guest_pagemask(cop0));
-
- return EMULATE_DONE;
-}
-
-/* Write Guest TLB Entry @ Random Index */
-enum emulation_result kvm_mips_emul_tlbwr(struct kvm_vcpu *vcpu)
-{
- struct mips_coproc *cop0 = vcpu->arch.cop0;
- struct kvm_mips_tlb *tlb = NULL;
- unsigned long pc = vcpu->arch.pc;
- int index;
-
- index = prandom_u32_max(KVM_MIPS_GUEST_TLB_SIZE);
- tlb = &vcpu->arch.guest_tlb[index];
-
- kvm_mips_invalidate_guest_tlb(vcpu, tlb);
-
- tlb->tlb_mask = kvm_read_c0_guest_pagemask(cop0);
- tlb->tlb_hi = kvm_read_c0_guest_entryhi(cop0);
- tlb->tlb_lo[0] = kvm_read_c0_guest_entrylo0(cop0);
- tlb->tlb_lo[1] = kvm_read_c0_guest_entrylo1(cop0);
-
- kvm_debug("[%#lx] COP0_TLBWR[%d] (entryhi: %#lx, entrylo0: %#lx entrylo1: %#lx)\n",
- pc, index, kvm_read_c0_guest_entryhi(cop0),
- kvm_read_c0_guest_entrylo0(cop0),
- kvm_read_c0_guest_entrylo1(cop0));
-
- return EMULATE_DONE;
-}
-
-enum emulation_result kvm_mips_emul_tlbp(struct kvm_vcpu *vcpu)
-{
- struct mips_coproc *cop0 = vcpu->arch.cop0;
- long entryhi = kvm_read_c0_guest_entryhi(cop0);
- unsigned long pc = vcpu->arch.pc;
- int index = -1;
-
- index = kvm_mips_guest_tlb_lookup(vcpu, entryhi);
-
- kvm_write_c0_guest_index(cop0, index);
-
- kvm_debug("[%#lx] COP0_TLBP (entryhi: %#lx), index: %d\n", pc, entryhi,
- index);
-
- return EMULATE_DONE;
-}
-
-/**
- * kvm_mips_config1_wrmask() - Find mask of writable bits in guest Config1
- * @vcpu: Virtual CPU.
- *
- * Finds the mask of bits which are writable in the guest's Config1 CP0
- * register, by userland (currently read-only to the guest).
- */
-unsigned int kvm_mips_config1_wrmask(struct kvm_vcpu *vcpu)
-{
- unsigned int mask = 0;
-
- /* Permit FPU to be present if FPU is supported */
- if (kvm_mips_guest_can_have_fpu(&vcpu->arch))
- mask |= MIPS_CONF1_FP;
-
- return mask;
-}
-
-/**
- * kvm_mips_config3_wrmask() - Find mask of writable bits in guest Config3
- * @vcpu: Virtual CPU.
- *
- * Finds the mask of bits which are writable in the guest's Config3 CP0
- * register, by userland (currently read-only to the guest).
- */
-unsigned int kvm_mips_config3_wrmask(struct kvm_vcpu *vcpu)
-{
- /* Config4 and ULRI are optional */
- unsigned int mask = MIPS_CONF_M | MIPS_CONF3_ULRI;
-
- /* Permit MSA to be present if MSA is supported */
- if (kvm_mips_guest_can_have_msa(&vcpu->arch))
- mask |= MIPS_CONF3_MSA;
-
- return mask;
-}
-
-/**
- * kvm_mips_config4_wrmask() - Find mask of writable bits in guest Config4
- * @vcpu: Virtual CPU.
- *
- * Finds the mask of bits which are writable in the guest's Config4 CP0
- * register, by userland (currently read-only to the guest).
- */
-unsigned int kvm_mips_config4_wrmask(struct kvm_vcpu *vcpu)
-{
- /* Config5 is optional */
- unsigned int mask = MIPS_CONF_M;
-
- /* KScrExist */
- mask |= 0xfc << MIPS_CONF4_KSCREXIST_SHIFT;
-
- return mask;
-}
-
-/**
- * kvm_mips_config5_wrmask() - Find mask of writable bits in guest Config5
- * @vcpu: Virtual CPU.
- *
- * Finds the mask of bits which are writable in the guest's Config5 CP0
- * register, by the guest itself.
- */
-unsigned int kvm_mips_config5_wrmask(struct kvm_vcpu *vcpu)
-{
- unsigned int mask = 0;
-
- /* Permit MSAEn changes if MSA supported and enabled */
- if (kvm_mips_guest_has_msa(&vcpu->arch))
- mask |= MIPS_CONF5_MSAEN;
-
- /*
- * Permit guest FPU mode changes if FPU is enabled and the relevant
- * feature exists according to FIR register.
- */
- if (kvm_mips_guest_has_fpu(&vcpu->arch)) {
- if (cpu_has_fre)
- mask |= MIPS_CONF5_FRE;
- /* We don't support UFR or UFE */
- }
-
- return mask;
-}
-
-enum emulation_result kvm_mips_emulate_CP0(union mips_instruction inst,
- u32 *opc, u32 cause,
- struct kvm_vcpu *vcpu)
-{
- struct mips_coproc *cop0 = vcpu->arch.cop0;
- enum emulation_result er = EMULATE_DONE;
- u32 rt, rd, sel;
- unsigned long curr_pc;
-
- /*
- * Update PC and hold onto current PC in case there is
- * an error and we want to rollback the PC
- */
- curr_pc = vcpu->arch.pc;
- er = update_pc(vcpu, cause);
- if (er == EMULATE_FAIL)
- return er;
-
- if (inst.co_format.co) {
- switch (inst.co_format.func) {
- case tlbr_op: /* Read indexed TLB entry */
- er = kvm_mips_emul_tlbr(vcpu);
- break;
- case tlbwi_op: /* Write indexed */
- er = kvm_mips_emul_tlbwi(vcpu);
- break;
- case tlbwr_op: /* Write random */
- er = kvm_mips_emul_tlbwr(vcpu);
- break;
- case tlbp_op: /* TLB Probe */
- er = kvm_mips_emul_tlbp(vcpu);
- break;
- case rfe_op:
- kvm_err("!!!COP0_RFE!!!\n");
- break;
- case eret_op:
- er = kvm_mips_emul_eret(vcpu);
- goto dont_update_pc;
- case wait_op:
- er = kvm_mips_emul_wait(vcpu);
- break;
- case hypcall_op:
- er = kvm_mips_emul_hypcall(vcpu, inst);
- break;
- }
- } else {
- rt = inst.c0r_format.rt;
- rd = inst.c0r_format.rd;
- sel = inst.c0r_format.sel;
-
- switch (inst.c0r_format.rs) {
- case mfc_op:
-#ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS
- cop0->stat[rd][sel]++;
-#endif
- /* Get reg */
- if ((rd == MIPS_CP0_COUNT) && (sel == 0)) {
- vcpu->arch.gprs[rt] =
- (s32)kvm_mips_read_count(vcpu);
- } else if ((rd == MIPS_CP0_ERRCTL) && (sel == 0)) {
- vcpu->arch.gprs[rt] = 0x0;
-#ifdef CONFIG_KVM_MIPS_DYN_TRANS
- kvm_mips_trans_mfc0(inst, opc, vcpu);
-#endif
- } else {
- vcpu->arch.gprs[rt] = (s32)cop0->reg[rd][sel];
-
-#ifdef CONFIG_KVM_MIPS_DYN_TRANS
- kvm_mips_trans_mfc0(inst, opc, vcpu);
-#endif
- }
-
- trace_kvm_hwr(vcpu, KVM_TRACE_MFC0,
- KVM_TRACE_COP0(rd, sel),
- vcpu->arch.gprs[rt]);
- break;
-
- case dmfc_op:
- vcpu->arch.gprs[rt] = cop0->reg[rd][sel];
-
- trace_kvm_hwr(vcpu, KVM_TRACE_DMFC0,
- KVM_TRACE_COP0(rd, sel),
- vcpu->arch.gprs[rt]);
- break;
-
- case mtc_op:
-#ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS
- cop0->stat[rd][sel]++;
-#endif
- trace_kvm_hwr(vcpu, KVM_TRACE_MTC0,
- KVM_TRACE_COP0(rd, sel),
- vcpu->arch.gprs[rt]);
-
- if ((rd == MIPS_CP0_TLB_INDEX)
- && (vcpu->arch.gprs[rt] >=
- KVM_MIPS_GUEST_TLB_SIZE)) {
- kvm_err("Invalid TLB Index: %ld",
- vcpu->arch.gprs[rt]);
- er = EMULATE_FAIL;
- break;
- }
- if ((rd == MIPS_CP0_PRID) && (sel == 1)) {
- /*
- * Preserve core number, and keep the exception
- * base in guest KSeg0.
- */
- kvm_change_c0_guest_ebase(cop0, 0x1ffff000,
- vcpu->arch.gprs[rt]);
- } else if (rd == MIPS_CP0_TLB_HI && sel == 0) {
- kvm_mips_change_entryhi(vcpu,
- vcpu->arch.gprs[rt]);
- }
- /* Are we writing to COUNT */
- else if ((rd == MIPS_CP0_COUNT) && (sel == 0)) {
- kvm_mips_write_count(vcpu, vcpu->arch.gprs[rt]);
- goto done;
- } else if ((rd == MIPS_CP0_COMPARE) && (sel == 0)) {
- /* If we are writing to COMPARE */
- /* Clear pending timer interrupt, if any */
- kvm_mips_write_compare(vcpu,
- vcpu->arch.gprs[rt],
- true);
- } else if ((rd == MIPS_CP0_STATUS) && (sel == 0)) {
- unsigned int old_val, val, change;
-
- old_val = kvm_read_c0_guest_status(cop0);
- val = vcpu->arch.gprs[rt];
- change = val ^ old_val;
-
- /* Make sure that the NMI bit is never set */
- val &= ~ST0_NMI;
-
- /*
- * Don't allow CU1 or FR to be set unless FPU
- * capability enabled and exists in guest
- * configuration.
- */
- if (!kvm_mips_guest_has_fpu(&vcpu->arch))
- val &= ~(ST0_CU1 | ST0_FR);
-
- /*
- * Also don't allow FR to be set if host doesn't
- * support it.
- */
- if (!(current_cpu_data.fpu_id & MIPS_FPIR_F64))
- val &= ~ST0_FR;
-
-
- /* Handle changes in FPU mode */
- preempt_disable();
-
- /*
- * FPU and Vector register state is made
- * UNPREDICTABLE by a change of FR, so don't
- * even bother saving it.
- */
- if (change & ST0_FR)
- kvm_drop_fpu(vcpu);
-
- /*
- * If MSA state is already live, it is undefined
- * how it interacts with FR=0 FPU state, and we
- * don't want to hit reserved instruction
- * exceptions trying to save the MSA state later
- * when CU=1 && FR=1, so play it safe and save
- * it first.
- */
- if (change & ST0_CU1 && !(val & ST0_FR) &&
- vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA)
- kvm_lose_fpu(vcpu);
-
- /*
- * Propagate CU1 (FPU enable) changes
- * immediately if the FPU context is already
- * loaded. When disabling we leave the context
- * loaded so it can be quickly enabled again in
- * the near future.
- */
- if (change & ST0_CU1 &&
- vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU)
- change_c0_status(ST0_CU1, val);
-
- preempt_enable();
-
- kvm_write_c0_guest_status(cop0, val);
-
-#ifdef CONFIG_KVM_MIPS_DYN_TRANS
- /*
- * If FPU present, we need CU1/FR bits to take
- * effect fairly soon.
- */
- if (!kvm_mips_guest_has_fpu(&vcpu->arch))
- kvm_mips_trans_mtc0(inst, opc, vcpu);
-#endif
- } else if ((rd == MIPS_CP0_CONFIG) && (sel == 5)) {
- unsigned int old_val, val, change, wrmask;
-
- old_val = kvm_read_c0_guest_config5(cop0);
- val = vcpu->arch.gprs[rt];
-
- /* Only a few bits are writable in Config5 */
- wrmask = kvm_mips_config5_wrmask(vcpu);
- change = (val ^ old_val) & wrmask;
- val = old_val ^ change;
-
-
- /* Handle changes in FPU/MSA modes */
- preempt_disable();
-
- /*
- * Propagate FRE changes immediately if the FPU
- * context is already loaded.
- */
- if (change & MIPS_CONF5_FRE &&
- vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU)
- change_c0_config5(MIPS_CONF5_FRE, val);
-
- /*
- * Propagate MSAEn changes immediately if the
- * MSA context is already loaded. When disabling
- * we leave the context loaded so it can be
- * quickly enabled again in the near future.
- */
- if (change & MIPS_CONF5_MSAEN &&
- vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA)
- change_c0_config5(MIPS_CONF5_MSAEN,
- val);
-
- preempt_enable();
-
- kvm_write_c0_guest_config5(cop0, val);
- } else if ((rd == MIPS_CP0_CAUSE) && (sel == 0)) {
- u32 old_cause, new_cause;
-
- old_cause = kvm_read_c0_guest_cause(cop0);
- new_cause = vcpu->arch.gprs[rt];
- /* Update R/W bits */
- kvm_change_c0_guest_cause(cop0, 0x08800300,
- new_cause);
- /* DC bit enabling/disabling timer? */
- if ((old_cause ^ new_cause) & CAUSEF_DC) {
- if (new_cause & CAUSEF_DC)
- kvm_mips_count_disable_cause(vcpu);
- else
- kvm_mips_count_enable_cause(vcpu);
- }
- } else if ((rd == MIPS_CP0_HWRENA) && (sel == 0)) {
- u32 mask = MIPS_HWRENA_CPUNUM |
- MIPS_HWRENA_SYNCISTEP |
- MIPS_HWRENA_CC |
- MIPS_HWRENA_CCRES;
-
- if (kvm_read_c0_guest_config3(cop0) &
- MIPS_CONF3_ULRI)
- mask |= MIPS_HWRENA_ULR;
- cop0->reg[rd][sel] = vcpu->arch.gprs[rt] & mask;
- } else {
- cop0->reg[rd][sel] = vcpu->arch.gprs[rt];
-#ifdef CONFIG_KVM_MIPS_DYN_TRANS
- kvm_mips_trans_mtc0(inst, opc, vcpu);
-#endif
- }
- break;
-
- case dmtc_op:
- kvm_err("!!!!!!![%#lx]dmtc_op: rt: %d, rd: %d, sel: %d!!!!!!\n",
- vcpu->arch.pc, rt, rd, sel);
- trace_kvm_hwr(vcpu, KVM_TRACE_DMTC0,
- KVM_TRACE_COP0(rd, sel),
- vcpu->arch.gprs[rt]);
- er = EMULATE_FAIL;
- break;
-
- case mfmc0_op:
-#ifdef KVM_MIPS_DEBUG_COP0_COUNTERS
- cop0->stat[MIPS_CP0_STATUS][0]++;
-#endif
- if (rt != 0)
- vcpu->arch.gprs[rt] =
- kvm_read_c0_guest_status(cop0);
- /* EI */
- if (inst.mfmc0_format.sc) {
- kvm_debug("[%#lx] mfmc0_op: EI\n",
- vcpu->arch.pc);
- kvm_set_c0_guest_status(cop0, ST0_IE);
- } else {
- kvm_debug("[%#lx] mfmc0_op: DI\n",
- vcpu->arch.pc);
- kvm_clear_c0_guest_status(cop0, ST0_IE);
- }
-
- break;
-
- case wrpgpr_op:
- {
- u32 css = cop0->reg[MIPS_CP0_STATUS][2] & 0xf;
- u32 pss =
- (cop0->reg[MIPS_CP0_STATUS][2] >> 6) & 0xf;
- /*
- * We don't support any shadow register sets, so
- * SRSCtl[PSS] == SRSCtl[CSS] = 0
- */
- if (css || pss) {
- er = EMULATE_FAIL;
- break;
- }
- kvm_debug("WRPGPR[%d][%d] = %#lx\n", pss, rd,
- vcpu->arch.gprs[rt]);
- vcpu->arch.gprs[rd] = vcpu->arch.gprs[rt];
- }
- break;
- default:
- kvm_err("[%#lx]MachEmulateCP0: unsupported COP0, copz: 0x%x\n",
- vcpu->arch.pc, inst.c0r_format.rs);
- er = EMULATE_FAIL;
- break;
- }
- }
-
-done:
- /* Rollback PC only if emulation was unsuccessful */
- if (er == EMULATE_FAIL)
- vcpu->arch.pc = curr_pc;
-
-dont_update_pc:
- /*
- * This is for special instructions whose emulation
- * updates the PC, so do not overwrite the PC under
- * any circumstances
- */
-
- return er;
-}
-
enum emulation_result kvm_mips_emulate_store(union mips_instruction inst,
u32 cause,
struct kvm_vcpu *vcpu)
@@ -1623,7 +996,7 @@ enum emulation_result kvm_mips_emulate_store(union mips_instruction inst,
goto out_fail;
switch (inst.i_format.opcode) {
-#if defined(CONFIG_64BIT) && defined(CONFIG_KVM_MIPS_VZ)
+#if defined(CONFIG_64BIT)
case sd_op:
run->mmio.len = 8;
*(u64 *)data = vcpu->arch.gprs[rt];
@@ -1721,7 +1094,7 @@ enum emulation_result kvm_mips_emulate_store(union mips_instruction inst,
vcpu->arch.gprs[rt], *(u32 *)data);
break;
-#if defined(CONFIG_64BIT) && defined(CONFIG_KVM_MIPS_VZ)
+#if defined(CONFIG_64BIT)
case sdl_op:
run->mmio.phys_addr = kvm_mips_callbacks->gva_to_gpa(
vcpu->arch.host_cp0_badvaddr) & (~0x7);
@@ -1928,7 +1301,7 @@ enum emulation_result kvm_mips_emulate_load(union mips_instruction inst,
vcpu->mmio_needed = 2; /* signed */
switch (op) {
-#if defined(CONFIG_64BIT) && defined(CONFIG_KVM_MIPS_VZ)
+#if defined(CONFIG_64BIT)
case ld_op:
run->mmio.len = 8;
break;
@@ -2003,7 +1376,7 @@ enum emulation_result kvm_mips_emulate_load(union mips_instruction inst,
}
break;
-#if defined(CONFIG_64BIT) && defined(CONFIG_KVM_MIPS_VZ)
+#if defined(CONFIG_64BIT)
case ldl_op:
run->mmio.phys_addr = kvm_mips_callbacks->gva_to_gpa(
vcpu->arch.host_cp0_badvaddr) & (~0x7);
@@ -2135,815 +1508,6 @@ enum emulation_result kvm_mips_emulate_load(union mips_instruction inst,
return EMULATE_DO_MMIO;
}
-#ifndef CONFIG_KVM_MIPS_VZ
-static enum emulation_result kvm_mips_guest_cache_op(int (*fn)(unsigned long),
- unsigned long curr_pc,
- unsigned long addr,
- struct kvm_vcpu *vcpu,
- u32 cause)
-{
- int err;
-
- for (;;) {
- /* Carefully attempt the cache operation */
- kvm_trap_emul_gva_lockless_begin(vcpu);
- err = fn(addr);
- kvm_trap_emul_gva_lockless_end(vcpu);
-
- if (likely(!err))
- return EMULATE_DONE;
-
- /*
- * Try to handle the fault and retry, maybe we just raced with a
- * GVA invalidation.
- */
- switch (kvm_trap_emul_gva_fault(vcpu, addr, false)) {
- case KVM_MIPS_GVA:
- case KVM_MIPS_GPA:
- /* bad virtual or physical address */
- return EMULATE_FAIL;
- case KVM_MIPS_TLB:
- /* no matching guest TLB */
- vcpu->arch.host_cp0_badvaddr = addr;
- vcpu->arch.pc = curr_pc;
- kvm_mips_emulate_tlbmiss_ld(cause, NULL, vcpu);
- return EMULATE_EXCEPT;
- case KVM_MIPS_TLBINV:
- /* invalid matching guest TLB */
- vcpu->arch.host_cp0_badvaddr = addr;
- vcpu->arch.pc = curr_pc;
- kvm_mips_emulate_tlbinv_ld(cause, NULL, vcpu);
- return EMULATE_EXCEPT;
- default:
- break;
- }
- }
-}
-
-enum emulation_result kvm_mips_emulate_cache(union mips_instruction inst,
- u32 *opc, u32 cause,
- struct kvm_vcpu *vcpu)
-{
- enum emulation_result er = EMULATE_DONE;
- u32 cache, op_inst, op, base;
- s16 offset;
- struct kvm_vcpu_arch *arch = &vcpu->arch;
- unsigned long va;
- unsigned long curr_pc;
-
- /*
- * Update PC and hold onto current PC in case there is
- * an error and we want to rollback the PC
- */
- curr_pc = vcpu->arch.pc;
- er = update_pc(vcpu, cause);
- if (er == EMULATE_FAIL)
- return er;
-
- base = inst.i_format.rs;
- op_inst = inst.i_format.rt;
- if (cpu_has_mips_r6)
- offset = inst.spec3_format.simmediate;
- else
- offset = inst.i_format.simmediate;
- cache = op_inst & CacheOp_Cache;
- op = op_inst & CacheOp_Op;
-
- va = arch->gprs[base] + offset;
-
- kvm_debug("CACHE (cache: %#x, op: %#x, base[%d]: %#lx, offset: %#x\n",
- cache, op, base, arch->gprs[base], offset);
-
- /*
- * Treat INDEX_INV as a nop, basically issued by Linux on startup to
- * invalidate the caches entirely by stepping through all the
- * ways/indexes
- */
- if (op == Index_Writeback_Inv) {
- kvm_debug("@ %#lx/%#lx CACHE (cache: %#x, op: %#x, base[%d]: %#lx, offset: %#x\n",
- vcpu->arch.pc, vcpu->arch.gprs[31], cache, op, base,
- arch->gprs[base], offset);
-
- if (cache == Cache_D) {
-#ifdef CONFIG_CPU_R4K_CACHE_TLB
- r4k_blast_dcache();
-#else
- switch (boot_cpu_type()) {
- case CPU_CAVIUM_OCTEON3:
- /* locally flush icache */
- local_flush_icache_range(0, 0);
- break;
- default:
- __flush_cache_all();
- break;
- }
-#endif
- } else if (cache == Cache_I) {
-#ifdef CONFIG_CPU_R4K_CACHE_TLB
- r4k_blast_icache();
-#else
- switch (boot_cpu_type()) {
- case CPU_CAVIUM_OCTEON3:
- /* locally flush icache */
- local_flush_icache_range(0, 0);
- break;
- default:
- flush_icache_all();
- break;
- }
-#endif
- } else {
- kvm_err("%s: unsupported CACHE INDEX operation\n",
- __func__);
- return EMULATE_FAIL;
- }
-
-#ifdef CONFIG_KVM_MIPS_DYN_TRANS
- kvm_mips_trans_cache_index(inst, opc, vcpu);
-#endif
- goto done;
- }
-
- /* XXXKYMA: Only a subset of cache ops are supported, used by Linux */
- if (op_inst == Hit_Writeback_Inv_D || op_inst == Hit_Invalidate_D) {
- /*
- * Perform the dcache part of icache synchronisation on the
- * guest's behalf.
- */
- er = kvm_mips_guest_cache_op(protected_writeback_dcache_line,
- curr_pc, va, vcpu, cause);
- if (er != EMULATE_DONE)
- goto done;
-#ifdef CONFIG_KVM_MIPS_DYN_TRANS
- /*
- * Replace the CACHE instruction, with a SYNCI, not the same,
- * but avoids a trap
- */
- kvm_mips_trans_cache_va(inst, opc, vcpu);
-#endif
- } else if (op_inst == Hit_Invalidate_I) {
- /* Perform the icache synchronisation on the guest's behalf */
- er = kvm_mips_guest_cache_op(protected_writeback_dcache_line,
- curr_pc, va, vcpu, cause);
- if (er != EMULATE_DONE)
- goto done;
- er = kvm_mips_guest_cache_op(protected_flush_icache_line,
- curr_pc, va, vcpu, cause);
- if (er != EMULATE_DONE)
- goto done;
-
-#ifdef CONFIG_KVM_MIPS_DYN_TRANS
- /* Replace the CACHE instruction, with a SYNCI */
- kvm_mips_trans_cache_va(inst, opc, vcpu);
-#endif
- } else {
- kvm_err("NO-OP CACHE (cache: %#x, op: %#x, base[%d]: %#lx, offset: %#x\n",
- cache, op, base, arch->gprs[base], offset);
- er = EMULATE_FAIL;
- }
-
-done:
- /* Rollback PC only if emulation was unsuccessful */
- if (er == EMULATE_FAIL)
- vcpu->arch.pc = curr_pc;
- /* Guest exception needs guest to resume */
- if (er == EMULATE_EXCEPT)
- er = EMULATE_DONE;
-
- return er;
-}
-
-enum emulation_result kvm_mips_emulate_inst(u32 cause, u32 *opc,
- struct kvm_vcpu *vcpu)
-{
- union mips_instruction inst;
- enum emulation_result er = EMULATE_DONE;
- int err;
-
- /* Fetch the instruction. */
- if (cause & CAUSEF_BD)
- opc += 1;
- err = kvm_get_badinstr(opc, vcpu, &inst.word);
- if (err)
- return EMULATE_FAIL;
-
- switch (inst.r_format.opcode) {
- case cop0_op:
- er = kvm_mips_emulate_CP0(inst, opc, cause, vcpu);
- break;
-
-#ifndef CONFIG_CPU_MIPSR6
- case cache_op:
- ++vcpu->stat.cache_exits;
- trace_kvm_exit(vcpu, KVM_TRACE_EXIT_CACHE);
- er = kvm_mips_emulate_cache(inst, opc, cause, vcpu);
- break;
-#else
- case spec3_op:
- switch (inst.spec3_format.func) {
- case cache6_op:
- ++vcpu->stat.cache_exits;
- trace_kvm_exit(vcpu, KVM_TRACE_EXIT_CACHE);
- er = kvm_mips_emulate_cache(inst, opc, cause,
- vcpu);
- break;
- default:
- goto unknown;
- }
- break;
-unknown:
-#endif
-
- default:
- kvm_err("Instruction emulation not supported (%p/%#x)\n", opc,
- inst.word);
- kvm_arch_vcpu_dump_regs(vcpu);
- er = EMULATE_FAIL;
- break;
- }
-
- return er;
-}
-#endif /* CONFIG_KVM_MIPS_VZ */
-
-/**
- * kvm_mips_guest_exception_base() - Find guest exception vector base address.
- *
- * Returns: The base address of the current guest exception vector, taking
- * both Guest.CP0_Status.BEV and Guest.CP0_EBase into account.
- */
-long kvm_mips_guest_exception_base(struct kvm_vcpu *vcpu)
-{
- struct mips_coproc *cop0 = vcpu->arch.cop0;
-
- if (kvm_read_c0_guest_status(cop0) & ST0_BEV)
- return KVM_GUEST_CKSEG1ADDR(0x1fc00200);
- else
- return kvm_read_c0_guest_ebase(cop0) & MIPS_EBASE_BASE;
-}
-
-enum emulation_result kvm_mips_emulate_syscall(u32 cause,
- u32 *opc,
- struct kvm_vcpu *vcpu)
-{
- struct mips_coproc *cop0 = vcpu->arch.cop0;
- struct kvm_vcpu_arch *arch = &vcpu->arch;
- enum emulation_result er = EMULATE_DONE;
-
- if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
- /* save old pc */
- kvm_write_c0_guest_epc(cop0, arch->pc);
- kvm_set_c0_guest_status(cop0, ST0_EXL);
-
- if (cause & CAUSEF_BD)
- kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
- else
- kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
-
- kvm_debug("Delivering SYSCALL @ pc %#lx\n", arch->pc);
-
- kvm_change_c0_guest_cause(cop0, (0xff),
- (EXCCODE_SYS << CAUSEB_EXCCODE));
-
- /* Set PC to the exception entry point */
- arch->pc = kvm_mips_guest_exception_base(vcpu) + 0x180;
-
- } else {
- kvm_err("Trying to deliver SYSCALL when EXL is already set\n");
- er = EMULATE_FAIL;
- }
-
- return er;
-}
-
-enum emulation_result kvm_mips_emulate_tlbmiss_ld(u32 cause,
- u32 *opc,
- struct kvm_vcpu *vcpu)
-{
- struct mips_coproc *cop0 = vcpu->arch.cop0;
- struct kvm_vcpu_arch *arch = &vcpu->arch;
- unsigned long entryhi = (vcpu->arch. host_cp0_badvaddr & VPN2_MASK) |
- (kvm_read_c0_guest_entryhi(cop0) & KVM_ENTRYHI_ASID);
-
- if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
- /* save old pc */
- kvm_write_c0_guest_epc(cop0, arch->pc);
- kvm_set_c0_guest_status(cop0, ST0_EXL);
-
- if (cause & CAUSEF_BD)
- kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
- else
- kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
-
- kvm_debug("[EXL == 0] delivering TLB MISS @ pc %#lx\n",
- arch->pc);
-
- /* set pc to the exception entry point */
- arch->pc = kvm_mips_guest_exception_base(vcpu) + 0x0;
-
- } else {
- kvm_debug("[EXL == 1] delivering TLB MISS @ pc %#lx\n",
- arch->pc);
-
- arch->pc = kvm_mips_guest_exception_base(vcpu) + 0x180;
- }
-
- kvm_change_c0_guest_cause(cop0, (0xff),
- (EXCCODE_TLBL << CAUSEB_EXCCODE));
-
- /* setup badvaddr, context and entryhi registers for the guest */
- kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr);
- /* XXXKYMA: is the context register used by linux??? */
- kvm_write_c0_guest_entryhi(cop0, entryhi);
-
- return EMULATE_DONE;
-}
-
-enum emulation_result kvm_mips_emulate_tlbinv_ld(u32 cause,
- u32 *opc,
- struct kvm_vcpu *vcpu)
-{
- struct mips_coproc *cop0 = vcpu->arch.cop0;
- struct kvm_vcpu_arch *arch = &vcpu->arch;
- unsigned long entryhi =
- (vcpu->arch.host_cp0_badvaddr & VPN2_MASK) |
- (kvm_read_c0_guest_entryhi(cop0) & KVM_ENTRYHI_ASID);
-
- if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
- /* save old pc */
- kvm_write_c0_guest_epc(cop0, arch->pc);
- kvm_set_c0_guest_status(cop0, ST0_EXL);
-
- if (cause & CAUSEF_BD)
- kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
- else
- kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
-
- kvm_debug("[EXL == 0] delivering TLB INV @ pc %#lx\n",
- arch->pc);
- } else {
- kvm_debug("[EXL == 1] delivering TLB MISS @ pc %#lx\n",
- arch->pc);
- }
-
- /* set pc to the exception entry point */
- arch->pc = kvm_mips_guest_exception_base(vcpu) + 0x180;
-
- kvm_change_c0_guest_cause(cop0, (0xff),
- (EXCCODE_TLBL << CAUSEB_EXCCODE));
-
- /* setup badvaddr, context and entryhi registers for the guest */
- kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr);
- /* XXXKYMA: is the context register used by linux??? */
- kvm_write_c0_guest_entryhi(cop0, entryhi);
-
- return EMULATE_DONE;
-}
-
-enum emulation_result kvm_mips_emulate_tlbmiss_st(u32 cause,
- u32 *opc,
- struct kvm_vcpu *vcpu)
-{
- struct mips_coproc *cop0 = vcpu->arch.cop0;
- struct kvm_vcpu_arch *arch = &vcpu->arch;
- unsigned long entryhi = (vcpu->arch.host_cp0_badvaddr & VPN2_MASK) |
- (kvm_read_c0_guest_entryhi(cop0) & KVM_ENTRYHI_ASID);
-
- if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
- /* save old pc */
- kvm_write_c0_guest_epc(cop0, arch->pc);
- kvm_set_c0_guest_status(cop0, ST0_EXL);
-
- if (cause & CAUSEF_BD)
- kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
- else
- kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
-
- kvm_debug("[EXL == 0] Delivering TLB MISS @ pc %#lx\n",
- arch->pc);
-
- /* Set PC to the exception entry point */
- arch->pc = kvm_mips_guest_exception_base(vcpu) + 0x0;
- } else {
- kvm_debug("[EXL == 1] Delivering TLB MISS @ pc %#lx\n",
- arch->pc);
- arch->pc = kvm_mips_guest_exception_base(vcpu) + 0x180;
- }
-
- kvm_change_c0_guest_cause(cop0, (0xff),
- (EXCCODE_TLBS << CAUSEB_EXCCODE));
-
- /* setup badvaddr, context and entryhi registers for the guest */
- kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr);
- /* XXXKYMA: is the context register used by linux??? */
- kvm_write_c0_guest_entryhi(cop0, entryhi);
-
- return EMULATE_DONE;
-}
-
-enum emulation_result kvm_mips_emulate_tlbinv_st(u32 cause,
- u32 *opc,
- struct kvm_vcpu *vcpu)
-{
- struct mips_coproc *cop0 = vcpu->arch.cop0;
- struct kvm_vcpu_arch *arch = &vcpu->arch;
- unsigned long entryhi = (vcpu->arch.host_cp0_badvaddr & VPN2_MASK) |
- (kvm_read_c0_guest_entryhi(cop0) & KVM_ENTRYHI_ASID);
-
- if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
- /* save old pc */
- kvm_write_c0_guest_epc(cop0, arch->pc);
- kvm_set_c0_guest_status(cop0, ST0_EXL);
-
- if (cause & CAUSEF_BD)
- kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
- else
- kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
-
- kvm_debug("[EXL == 0] Delivering TLB MISS @ pc %#lx\n",
- arch->pc);
- } else {
- kvm_debug("[EXL == 1] Delivering TLB MISS @ pc %#lx\n",
- arch->pc);
- }
-
- /* Set PC to the exception entry point */
- arch->pc = kvm_mips_guest_exception_base(vcpu) + 0x180;
-
- kvm_change_c0_guest_cause(cop0, (0xff),
- (EXCCODE_TLBS << CAUSEB_EXCCODE));
-
- /* setup badvaddr, context and entryhi registers for the guest */
- kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr);
- /* XXXKYMA: is the context register used by linux??? */
- kvm_write_c0_guest_entryhi(cop0, entryhi);
-
- return EMULATE_DONE;
-}
-
-enum emulation_result kvm_mips_emulate_tlbmod(u32 cause,
- u32 *opc,
- struct kvm_vcpu *vcpu)
-{
- struct mips_coproc *cop0 = vcpu->arch.cop0;
- unsigned long entryhi = (vcpu->arch.host_cp0_badvaddr & VPN2_MASK) |
- (kvm_read_c0_guest_entryhi(cop0) & KVM_ENTRYHI_ASID);
- struct kvm_vcpu_arch *arch = &vcpu->arch;
-
- if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
- /* save old pc */
- kvm_write_c0_guest_epc(cop0, arch->pc);
- kvm_set_c0_guest_status(cop0, ST0_EXL);
-
- if (cause & CAUSEF_BD)
- kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
- else
- kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
-
- kvm_debug("[EXL == 0] Delivering TLB MOD @ pc %#lx\n",
- arch->pc);
- } else {
- kvm_debug("[EXL == 1] Delivering TLB MOD @ pc %#lx\n",
- arch->pc);
- }
-
- arch->pc = kvm_mips_guest_exception_base(vcpu) + 0x180;
-
- kvm_change_c0_guest_cause(cop0, (0xff),
- (EXCCODE_MOD << CAUSEB_EXCCODE));
-
- /* setup badvaddr, context and entryhi registers for the guest */
- kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr);
- /* XXXKYMA: is the context register used by linux??? */
- kvm_write_c0_guest_entryhi(cop0, entryhi);
-
- return EMULATE_DONE;
-}
-
-enum emulation_result kvm_mips_emulate_fpu_exc(u32 cause,
- u32 *opc,
- struct kvm_vcpu *vcpu)
-{
- struct mips_coproc *cop0 = vcpu->arch.cop0;
- struct kvm_vcpu_arch *arch = &vcpu->arch;
-
- if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
- /* save old pc */
- kvm_write_c0_guest_epc(cop0, arch->pc);
- kvm_set_c0_guest_status(cop0, ST0_EXL);
-
- if (cause & CAUSEF_BD)
- kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
- else
- kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
-
- }
-
- arch->pc = kvm_mips_guest_exception_base(vcpu) + 0x180;
-
- kvm_change_c0_guest_cause(cop0, (0xff),
- (EXCCODE_CPU << CAUSEB_EXCCODE));
- kvm_change_c0_guest_cause(cop0, (CAUSEF_CE), (0x1 << CAUSEB_CE));
-
- return EMULATE_DONE;
-}
-
-enum emulation_result kvm_mips_emulate_ri_exc(u32 cause,
- u32 *opc,
- struct kvm_vcpu *vcpu)
-{
- struct mips_coproc *cop0 = vcpu->arch.cop0;
- struct kvm_vcpu_arch *arch = &vcpu->arch;
- enum emulation_result er = EMULATE_DONE;
-
- if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
- /* save old pc */
- kvm_write_c0_guest_epc(cop0, arch->pc);
- kvm_set_c0_guest_status(cop0, ST0_EXL);
-
- if (cause & CAUSEF_BD)
- kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
- else
- kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
-
- kvm_debug("Delivering RI @ pc %#lx\n", arch->pc);
-
- kvm_change_c0_guest_cause(cop0, (0xff),
- (EXCCODE_RI << CAUSEB_EXCCODE));
-
- /* Set PC to the exception entry point */
- arch->pc = kvm_mips_guest_exception_base(vcpu) + 0x180;
-
- } else {
- kvm_err("Trying to deliver RI when EXL is already set\n");
- er = EMULATE_FAIL;
- }
-
- return er;
-}
-
-enum emulation_result kvm_mips_emulate_bp_exc(u32 cause,
- u32 *opc,
- struct kvm_vcpu *vcpu)
-{
- struct mips_coproc *cop0 = vcpu->arch.cop0;
- struct kvm_vcpu_arch *arch = &vcpu->arch;
- enum emulation_result er = EMULATE_DONE;
-
- if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
- /* save old pc */
- kvm_write_c0_guest_epc(cop0, arch->pc);
- kvm_set_c0_guest_status(cop0, ST0_EXL);
-
- if (cause & CAUSEF_BD)
- kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
- else
- kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
-
- kvm_debug("Delivering BP @ pc %#lx\n", arch->pc);
-
- kvm_change_c0_guest_cause(cop0, (0xff),
- (EXCCODE_BP << CAUSEB_EXCCODE));
-
- /* Set PC to the exception entry point */
- arch->pc = kvm_mips_guest_exception_base(vcpu) + 0x180;
-
- } else {
- kvm_err("Trying to deliver BP when EXL is already set\n");
- er = EMULATE_FAIL;
- }
-
- return er;
-}
-
-enum emulation_result kvm_mips_emulate_trap_exc(u32 cause,
- u32 *opc,
- struct kvm_vcpu *vcpu)
-{
- struct mips_coproc *cop0 = vcpu->arch.cop0;
- struct kvm_vcpu_arch *arch = &vcpu->arch;
- enum emulation_result er = EMULATE_DONE;
-
- if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
- /* save old pc */
- kvm_write_c0_guest_epc(cop0, arch->pc);
- kvm_set_c0_guest_status(cop0, ST0_EXL);
-
- if (cause & CAUSEF_BD)
- kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
- else
- kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
-
- kvm_debug("Delivering TRAP @ pc %#lx\n", arch->pc);
-
- kvm_change_c0_guest_cause(cop0, (0xff),
- (EXCCODE_TR << CAUSEB_EXCCODE));
-
- /* Set PC to the exception entry point */
- arch->pc = kvm_mips_guest_exception_base(vcpu) + 0x180;
-
- } else {
- kvm_err("Trying to deliver TRAP when EXL is already set\n");
- er = EMULATE_FAIL;
- }
-
- return er;
-}
-
-enum emulation_result kvm_mips_emulate_msafpe_exc(u32 cause,
- u32 *opc,
- struct kvm_vcpu *vcpu)
-{
- struct mips_coproc *cop0 = vcpu->arch.cop0;
- struct kvm_vcpu_arch *arch = &vcpu->arch;
- enum emulation_result er = EMULATE_DONE;
-
- if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
- /* save old pc */
- kvm_write_c0_guest_epc(cop0, arch->pc);
- kvm_set_c0_guest_status(cop0, ST0_EXL);
-
- if (cause & CAUSEF_BD)
- kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
- else
- kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
-
- kvm_debug("Delivering MSAFPE @ pc %#lx\n", arch->pc);
-
- kvm_change_c0_guest_cause(cop0, (0xff),
- (EXCCODE_MSAFPE << CAUSEB_EXCCODE));
-
- /* Set PC to the exception entry point */
- arch->pc = kvm_mips_guest_exception_base(vcpu) + 0x180;
-
- } else {
- kvm_err("Trying to deliver MSAFPE when EXL is already set\n");
- er = EMULATE_FAIL;
- }
-
- return er;
-}
-
-enum emulation_result kvm_mips_emulate_fpe_exc(u32 cause,
- u32 *opc,
- struct kvm_vcpu *vcpu)
-{
- struct mips_coproc *cop0 = vcpu->arch.cop0;
- struct kvm_vcpu_arch *arch = &vcpu->arch;
- enum emulation_result er = EMULATE_DONE;
-
- if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
- /* save old pc */
- kvm_write_c0_guest_epc(cop0, arch->pc);
- kvm_set_c0_guest_status(cop0, ST0_EXL);
-
- if (cause & CAUSEF_BD)
- kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
- else
- kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
-
- kvm_debug("Delivering FPE @ pc %#lx\n", arch->pc);
-
- kvm_change_c0_guest_cause(cop0, (0xff),
- (EXCCODE_FPE << CAUSEB_EXCCODE));
-
- /* Set PC to the exception entry point */
- arch->pc = kvm_mips_guest_exception_base(vcpu) + 0x180;
-
- } else {
- kvm_err("Trying to deliver FPE when EXL is already set\n");
- er = EMULATE_FAIL;
- }
-
- return er;
-}
-
-enum emulation_result kvm_mips_emulate_msadis_exc(u32 cause,
- u32 *opc,
- struct kvm_vcpu *vcpu)
-{
- struct mips_coproc *cop0 = vcpu->arch.cop0;
- struct kvm_vcpu_arch *arch = &vcpu->arch;
- enum emulation_result er = EMULATE_DONE;
-
- if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
- /* save old pc */
- kvm_write_c0_guest_epc(cop0, arch->pc);
- kvm_set_c0_guest_status(cop0, ST0_EXL);
-
- if (cause & CAUSEF_BD)
- kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
- else
- kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
-
- kvm_debug("Delivering MSADIS @ pc %#lx\n", arch->pc);
-
- kvm_change_c0_guest_cause(cop0, (0xff),
- (EXCCODE_MSADIS << CAUSEB_EXCCODE));
-
- /* Set PC to the exception entry point */
- arch->pc = kvm_mips_guest_exception_base(vcpu) + 0x180;
-
- } else {
- kvm_err("Trying to deliver MSADIS when EXL is already set\n");
- er = EMULATE_FAIL;
- }
-
- return er;
-}
-
-enum emulation_result kvm_mips_handle_ri(u32 cause, u32 *opc,
- struct kvm_vcpu *vcpu)
-{
- struct mips_coproc *cop0 = vcpu->arch.cop0;
- struct kvm_vcpu_arch *arch = &vcpu->arch;
- enum emulation_result er = EMULATE_DONE;
- unsigned long curr_pc;
- union mips_instruction inst;
- int err;
-
- /*
- * Update PC and hold onto current PC in case there is
- * an error and we want to rollback the PC
- */
- curr_pc = vcpu->arch.pc;
- er = update_pc(vcpu, cause);
- if (er == EMULATE_FAIL)
- return er;
-
- /* Fetch the instruction. */
- if (cause & CAUSEF_BD)
- opc += 1;
- err = kvm_get_badinstr(opc, vcpu, &inst.word);
- if (err) {
- kvm_err("%s: Cannot get inst @ %p (%d)\n", __func__, opc, err);
- return EMULATE_FAIL;
- }
-
- if (inst.r_format.opcode == spec3_op &&
- inst.r_format.func == rdhwr_op &&
- inst.r_format.rs == 0 &&
- (inst.r_format.re >> 3) == 0) {
- int usermode = !KVM_GUEST_KERNEL_MODE(vcpu);
- int rd = inst.r_format.rd;
- int rt = inst.r_format.rt;
- int sel = inst.r_format.re & 0x7;
-
- /* If usermode, check RDHWR rd is allowed by guest HWREna */
- if (usermode && !(kvm_read_c0_guest_hwrena(cop0) & BIT(rd))) {
- kvm_debug("RDHWR %#x disallowed by HWREna @ %p\n",
- rd, opc);
- goto emulate_ri;
- }
- switch (rd) {
- case MIPS_HWR_CPUNUM: /* CPU number */
- arch->gprs[rt] = vcpu->vcpu_id;
- break;
- case MIPS_HWR_SYNCISTEP: /* SYNCI length */
- arch->gprs[rt] = min(current_cpu_data.dcache.linesz,
- current_cpu_data.icache.linesz);
- break;
- case MIPS_HWR_CC: /* Read count register */
- arch->gprs[rt] = (s32)kvm_mips_read_count(vcpu);
- break;
- case MIPS_HWR_CCRES: /* Count register resolution */
- switch (current_cpu_data.cputype) {
- case CPU_20KC:
- case CPU_25KF:
- arch->gprs[rt] = 1;
- break;
- default:
- arch->gprs[rt] = 2;
- }
- break;
- case MIPS_HWR_ULR: /* Read UserLocal register */
- arch->gprs[rt] = kvm_read_c0_guest_userlocal(cop0);
- break;
-
- default:
- kvm_debug("RDHWR %#x not supported @ %p\n", rd, opc);
- goto emulate_ri;
- }
-
- trace_kvm_hwr(vcpu, KVM_TRACE_RDHWR, KVM_TRACE_HWR(rd, sel),
- vcpu->arch.gprs[rt]);
- } else {
- kvm_debug("Emulate RI not supported @ %p: %#x\n",
- opc, inst.word);
- goto emulate_ri;
- }
-
- return EMULATE_DONE;
-
-emulate_ri:
- /*
- * Rollback PC (if in branch delay slot then the PC already points to
- * branch target), and pass the RI exception to the guest OS.
- */
- vcpu->arch.pc = curr_pc;
- return kvm_mips_emulate_ri_exc(cause, opc, vcpu);
-}
-
enum emulation_result kvm_mips_complete_mmio_load(struct kvm_vcpu *vcpu)
{
struct kvm_run *run = vcpu->run;
@@ -3086,207 +1650,3 @@ enum emulation_result kvm_mips_complete_mmio_load(struct kvm_vcpu *vcpu)
done:
return er;
}
-
-static enum emulation_result kvm_mips_emulate_exc(u32 cause,
- u32 *opc,
- struct kvm_vcpu *vcpu)
-{
- u32 exccode = (cause >> CAUSEB_EXCCODE) & 0x1f;
- struct mips_coproc *cop0 = vcpu->arch.cop0;
- struct kvm_vcpu_arch *arch = &vcpu->arch;
- enum emulation_result er = EMULATE_DONE;
-
- if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
- /* save old pc */
- kvm_write_c0_guest_epc(cop0, arch->pc);
- kvm_set_c0_guest_status(cop0, ST0_EXL);
-
- if (cause & CAUSEF_BD)
- kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
- else
- kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
-
- kvm_change_c0_guest_cause(cop0, (0xff),
- (exccode << CAUSEB_EXCCODE));
-
- /* Set PC to the exception entry point */
- arch->pc = kvm_mips_guest_exception_base(vcpu) + 0x180;
- kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr);
-
- kvm_debug("Delivering EXC %d @ pc %#lx, badVaddr: %#lx\n",
- exccode, kvm_read_c0_guest_epc(cop0),
- kvm_read_c0_guest_badvaddr(cop0));
- } else {
- kvm_err("Trying to deliver EXC when EXL is already set\n");
- er = EMULATE_FAIL;
- }
-
- return er;
-}
-
-enum emulation_result kvm_mips_check_privilege(u32 cause,
- u32 *opc,
- struct kvm_vcpu *vcpu)
-{
- enum emulation_result er = EMULATE_DONE;
- u32 exccode = (cause >> CAUSEB_EXCCODE) & 0x1f;
- unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr;
-
- int usermode = !KVM_GUEST_KERNEL_MODE(vcpu);
-
- if (usermode) {
- switch (exccode) {
- case EXCCODE_INT:
- case EXCCODE_SYS:
- case EXCCODE_BP:
- case EXCCODE_RI:
- case EXCCODE_TR:
- case EXCCODE_MSAFPE:
- case EXCCODE_FPE:
- case EXCCODE_MSADIS:
- break;
-
- case EXCCODE_CPU:
- if (((cause & CAUSEF_CE) >> CAUSEB_CE) == 0)
- er = EMULATE_PRIV_FAIL;
- break;
-
- case EXCCODE_MOD:
- break;
-
- case EXCCODE_TLBL:
- /*
- * We we are accessing Guest kernel space, then send an
- * address error exception to the guest
- */
- if (badvaddr >= (unsigned long) KVM_GUEST_KSEG0) {
- kvm_debug("%s: LD MISS @ %#lx\n", __func__,
- badvaddr);
- cause &= ~0xff;
- cause |= (EXCCODE_ADEL << CAUSEB_EXCCODE);
- er = EMULATE_PRIV_FAIL;
- }
- break;
-
- case EXCCODE_TLBS:
- /*
- * We we are accessing Guest kernel space, then send an
- * address error exception to the guest
- */
- if (badvaddr >= (unsigned long) KVM_GUEST_KSEG0) {
- kvm_debug("%s: ST MISS @ %#lx\n", __func__,
- badvaddr);
- cause &= ~0xff;
- cause |= (EXCCODE_ADES << CAUSEB_EXCCODE);
- er = EMULATE_PRIV_FAIL;
- }
- break;
-
- case EXCCODE_ADES:
- kvm_debug("%s: address error ST @ %#lx\n", __func__,
- badvaddr);
- if ((badvaddr & PAGE_MASK) == KVM_GUEST_COMMPAGE_ADDR) {
- cause &= ~0xff;
- cause |= (EXCCODE_TLBS << CAUSEB_EXCCODE);
- }
- er = EMULATE_PRIV_FAIL;
- break;
- case EXCCODE_ADEL:
- kvm_debug("%s: address error LD @ %#lx\n", __func__,
- badvaddr);
- if ((badvaddr & PAGE_MASK) == KVM_GUEST_COMMPAGE_ADDR) {
- cause &= ~0xff;
- cause |= (EXCCODE_TLBL << CAUSEB_EXCCODE);
- }
- er = EMULATE_PRIV_FAIL;
- break;
- default:
- er = EMULATE_PRIV_FAIL;
- break;
- }
- }
-
- if (er == EMULATE_PRIV_FAIL)
- kvm_mips_emulate_exc(cause, opc, vcpu);
-
- return er;
-}
-
-/*
- * User Address (UA) fault, this could happen if
- * (1) TLB entry not present/valid in both Guest and shadow host TLBs, in this
- * case we pass on the fault to the guest kernel and let it handle it.
- * (2) TLB entry is present in the Guest TLB but not in the shadow, in this
- * case we inject the TLB from the Guest TLB into the shadow host TLB
- */
-enum emulation_result kvm_mips_handle_tlbmiss(u32 cause,
- u32 *opc,
- struct kvm_vcpu *vcpu,
- bool write_fault)
-{
- enum emulation_result er = EMULATE_DONE;
- u32 exccode = (cause >> CAUSEB_EXCCODE) & 0x1f;
- unsigned long va = vcpu->arch.host_cp0_badvaddr;
- int index;
-
- kvm_debug("kvm_mips_handle_tlbmiss: badvaddr: %#lx\n",
- vcpu->arch.host_cp0_badvaddr);
-
- /*
- * KVM would not have got the exception if this entry was valid in the
- * shadow host TLB. Check the Guest TLB, if the entry is not there then
- * send the guest an exception. The guest exc handler should then inject
- * an entry into the guest TLB.
- */
- index = kvm_mips_guest_tlb_lookup(vcpu,
- (va & VPN2_MASK) |
- (kvm_read_c0_guest_entryhi(vcpu->arch.cop0) &
- KVM_ENTRYHI_ASID));
- if (index < 0) {
- if (exccode == EXCCODE_TLBL) {
- er = kvm_mips_emulate_tlbmiss_ld(cause, opc, vcpu);
- } else if (exccode == EXCCODE_TLBS) {
- er = kvm_mips_emulate_tlbmiss_st(cause, opc, vcpu);
- } else {
- kvm_err("%s: invalid exc code: %d\n", __func__,
- exccode);
- er = EMULATE_FAIL;
- }
- } else {
- struct kvm_mips_tlb *tlb = &vcpu->arch.guest_tlb[index];
-
- /*
- * Check if the entry is valid, if not then setup a TLB invalid
- * exception to the guest
- */
- if (!TLB_IS_VALID(*tlb, va)) {
- if (exccode == EXCCODE_TLBL) {
- er = kvm_mips_emulate_tlbinv_ld(cause, opc,
- vcpu);
- } else if (exccode == EXCCODE_TLBS) {
- er = kvm_mips_emulate_tlbinv_st(cause, opc,
- vcpu);
- } else {
- kvm_err("%s: invalid exc code: %d\n", __func__,
- exccode);
- er = EMULATE_FAIL;
- }
- } else {
- kvm_debug("Injecting hi: %#lx, lo0: %#lx, lo1: %#lx into shadow host TLB\n",
- tlb->tlb_hi, tlb->tlb_lo[0], tlb->tlb_lo[1]);
- /*
- * OK we have a Guest TLB entry, now inject it into the
- * shadow host TLB
- */
- if (kvm_mips_handle_mapped_seg_tlb_fault(vcpu, tlb, va,
- write_fault)) {
- kvm_err("%s: handling mapped seg tlb fault for %lx, index: %u, vcpu: %p, ASID: %#lx\n",
- __func__, va, index, vcpu,
- read_c0_entryhi());
- er = EMULATE_FAIL;
- }
- }
- }
-
- return er;
-}
generated by cgit v1.2.3 (git 2.39.0) at 2024-11-25 05:27:08 +0300