diff options
Diffstat (limited to 'arch/mips/cavium-octeon')
| -rw-r--r-- | arch/mips/cavium-octeon/Makefile | 1 | ||||
| -rw-r--r-- | arch/mips/cavium-octeon/crypto/octeon-crypto.c | 2 | ||||
| -rw-r--r-- | arch/mips/cavium-octeon/dma-octeon.c | 19 | ||||
| -rw-r--r-- | arch/mips/cavium-octeon/executive/cvmx-bootmem.c | 2 | ||||
| -rw-r--r-- | arch/mips/cavium-octeon/executive/cvmx-helper-errata.c | 2 | ||||
| -rw-r--r-- | arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c | 3 | ||||
| -rw-r--r-- | arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c | 3 | ||||
| -rw-r--r-- | arch/mips/cavium-octeon/executive/cvmx-helper-spi.c | 3 | ||||
| -rw-r--r-- | arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c | 3 | ||||
| -rw-r--r-- | arch/mips/cavium-octeon/executive/cvmx-helper.c | 47 | ||||
| -rw-r--r-- | arch/mips/cavium-octeon/executive/cvmx-sysinfo.c | 2 | ||||
| -rw-r--r-- | arch/mips/cavium-octeon/octeon-memcpy.S | 25 | ||||
| -rw-r--r-- | arch/mips/cavium-octeon/octeon-platform.c | 5 | ||||
| -rw-r--r-- | arch/mips/cavium-octeon/octeon-usb.c | 552 | ||||
| -rw-r--r-- | arch/mips/cavium-octeon/setup.c | 23 | ||||
| -rw-r--r-- | arch/mips/cavium-octeon/smp.c | 24 |
16 files changed, 630 insertions, 86 deletions
diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile index 2a5926578841..7c02e542959a 100644 --- a/arch/mips/cavium-octeon/Makefile +++ b/arch/mips/cavium-octeon/Makefile @@ -18,3 +18,4 @@ obj-y += crypto/ obj-$(CONFIG_MTD) += flash_setup.o obj-$(CONFIG_SMP) += smp.o obj-$(CONFIG_OCTEON_ILM) += oct_ilm.o +obj-$(CONFIG_USB) += octeon-usb.o diff --git a/arch/mips/cavium-octeon/crypto/octeon-crypto.c b/arch/mips/cavium-octeon/crypto/octeon-crypto.c index f66bd1adc7ff..4d22365844af 100644 --- a/arch/mips/cavium-octeon/crypto/octeon-crypto.c +++ b/arch/mips/cavium-octeon/crypto/octeon-crypto.c @@ -7,7 +7,7 @@ */ #include <asm/cop2.h> -#include <linux/module.h> +#include <linux/export.h> #include <linux/interrupt.h> #include "octeon-crypto.h" diff --git a/arch/mips/cavium-octeon/dma-octeon.c b/arch/mips/cavium-octeon/dma-octeon.c index fd69528b24fb..c64bd87f0b6e 100644 --- a/arch/mips/cavium-octeon/dma-octeon.c +++ b/arch/mips/cavium-octeon/dma-octeon.c @@ -164,19 +164,14 @@ static void *octeon_dma_alloc_coherent(struct device *dev, size_t size, /* ignore region specifiers */ gfp &= ~(__GFP_DMA | __GFP_DMA32 | __GFP_HIGHMEM); -#ifdef CONFIG_ZONE_DMA - if (dev == NULL) + if (IS_ENABLED(CONFIG_ZONE_DMA) && dev == NULL) gfp |= __GFP_DMA; - else if (dev->coherent_dma_mask <= DMA_BIT_MASK(24)) + else if (IS_ENABLED(CONFIG_ZONE_DMA) && + dev->coherent_dma_mask <= DMA_BIT_MASK(24)) gfp |= __GFP_DMA; - else -#endif -#ifdef CONFIG_ZONE_DMA32 - if (dev->coherent_dma_mask <= DMA_BIT_MASK(32)) + else if (IS_ENABLED(CONFIG_ZONE_DMA32) && + dev->coherent_dma_mask <= DMA_BIT_MASK(32)) gfp |= __GFP_DMA32; - else -#endif - ; /* Don't invoke OOM killer */ gfp |= __GFP_NORETRY; @@ -205,7 +200,7 @@ static phys_addr_t octeon_unity_dma_to_phys(struct device *dev, dma_addr_t daddr } struct octeon_dma_map_ops { - struct dma_map_ops dma_map_ops; + const struct dma_map_ops dma_map_ops; dma_addr_t (*phys_to_dma)(struct device *dev, phys_addr_t paddr); phys_addr_t (*dma_to_phys)(struct device *dev, dma_addr_t daddr); }; @@ -333,7 +328,7 @@ static struct octeon_dma_map_ops _octeon_pci_dma_map_ops = { }, }; -struct dma_map_ops *octeon_pci_dma_map_ops; +const struct dma_map_ops *octeon_pci_dma_map_ops; void __init octeon_pci_dma_init(void) { diff --git a/arch/mips/cavium-octeon/executive/cvmx-bootmem.c b/arch/mips/cavium-octeon/executive/cvmx-bootmem.c index b65a6c1ac016..8d54d774933c 100644 --- a/arch/mips/cavium-octeon/executive/cvmx-bootmem.c +++ b/arch/mips/cavium-octeon/executive/cvmx-bootmem.c @@ -30,8 +30,8 @@ * application start time. */ +#include <linux/export.h> #include <linux/kernel.h> -#include <linux/module.h> #include <asm/octeon/cvmx.h> #include <asm/octeon/cvmx-spinlock.h> diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-errata.c b/arch/mips/cavium-octeon/executive/cvmx-helper-errata.c index 868659e64d4a..4b26fedecf46 100644 --- a/arch/mips/cavium-octeon/executive/cvmx-helper-errata.c +++ b/arch/mips/cavium-octeon/executive/cvmx-helper-errata.c @@ -33,7 +33,7 @@ * these functions directly. * */ -#include <linux/module.h> +#include <linux/export.h> #include <asm/octeon/octeon.h> diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c b/arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c index 671ab1db2727..ba4753c23b03 100644 --- a/arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c +++ b/arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c @@ -287,8 +287,7 @@ cvmx_helper_link_info_t __cvmx_helper_rgmii_link_get(int ipd_port) * Configure an IPD/PKO port for the specified link state. This * function does not influence auto negotiation at the PHY level. * The passed link state must always match the link state returned - * by cvmx_helper_link_get(). It is normally best to use - * cvmx_helper_link_autoconf() instead. + * by cvmx_helper_link_get(). * * @ipd_port: IPD/PKO port to configure * @link_info: The new link state diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c b/arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c index 54375340afe8..578283350776 100644 --- a/arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c +++ b/arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c @@ -500,8 +500,7 @@ cvmx_helper_link_info_t __cvmx_helper_sgmii_link_get(int ipd_port) * Configure an IPD/PKO port for the specified link state. This * function does not influence auto negotiation at the PHY level. * The passed link state must always match the link state returned - * by cvmx_helper_link_get(). It is normally best to use - * cvmx_helper_link_autoconf() instead. + * by cvmx_helper_link_get(). * * @ipd_port: IPD/PKO port to configure * @link_info: The new link state diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-spi.c b/arch/mips/cavium-octeon/executive/cvmx-helper-spi.c index 1f3030c72d88..ef16aa00167b 100644 --- a/arch/mips/cavium-octeon/executive/cvmx-helper-spi.c +++ b/arch/mips/cavium-octeon/executive/cvmx-helper-spi.c @@ -188,8 +188,7 @@ cvmx_helper_link_info_t __cvmx_helper_spi_link_get(int ipd_port) * Configure an IPD/PKO port for the specified link state. This * function does not influence auto negotiation at the PHY level. * The passed link state must always match the link state returned - * by cvmx_helper_link_get(). It is normally best to use - * cvmx_helper_link_autoconf() instead. + * by cvmx_helper_link_get(). * * @ipd_port: IPD/PKO port to configure * @link_info: The new link state diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c b/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c index d347fe13b666..19d54e02c185 100644 --- a/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c +++ b/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c @@ -295,8 +295,7 @@ cvmx_helper_link_info_t __cvmx_helper_xaui_link_get(int ipd_port) * Configure an IPD/PKO port for the specified link state. This * function does not influence auto negotiation at the PHY level. * The passed link state must always match the link state returned - * by cvmx_helper_link_get(). It is normally best to use - * cvmx_helper_link_autoconf() instead. + * by cvmx_helper_link_get(). * * @ipd_port: IPD/PKO port to configure * @link_info: The new link state diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper.c b/arch/mips/cavium-octeon/executive/cvmx-helper.c index 6456af642471..f24be0b5db50 100644 --- a/arch/mips/cavium-octeon/executive/cvmx-helper.c +++ b/arch/mips/cavium-octeon/executive/cvmx-helper.c @@ -69,10 +69,6 @@ void (*cvmx_override_ipd_port_setup) (int ipd_port); /* Port count per interface */ static int interface_port_count[5]; -/* Port last configured link info index by IPD/PKO port */ -static cvmx_helper_link_info_t - port_link_info[CVMX_PIP_NUM_INPUT_PORTS]; - /** * Return the number of interfaces the chip has. Each interface * may have multiple ports. Most chips support two interfaces, @@ -1136,41 +1132,6 @@ int cvmx_helper_initialize_packet_io_local(void) } /** - * Auto configure an IPD/PKO port link state and speed. This - * function basically does the equivalent of: - * cvmx_helper_link_set(ipd_port, cvmx_helper_link_get(ipd_port)); - * - * @ipd_port: IPD/PKO port to auto configure - * - * Returns Link state after configure - */ -cvmx_helper_link_info_t cvmx_helper_link_autoconf(int ipd_port) -{ - cvmx_helper_link_info_t link_info; - int interface = cvmx_helper_get_interface_num(ipd_port); - int index = cvmx_helper_get_interface_index_num(ipd_port); - - if (index >= cvmx_helper_ports_on_interface(interface)) { - link_info.u64 = 0; - return link_info; - } - - link_info = cvmx_helper_link_get(ipd_port); - if (link_info.u64 == port_link_info[ipd_port].u64) - return link_info; - - /* If we fail to set the link speed, port_link_info will not change */ - cvmx_helper_link_set(ipd_port, link_info); - - /* - * port_link_info should be the current value, which will be - * different than expect if cvmx_helper_link_set() failed. - */ - return port_link_info[ipd_port]; -} -EXPORT_SYMBOL_GPL(cvmx_helper_link_autoconf); - -/** * Return the link state of an IPD/PKO port as returned by * auto negotiation. The result of this function may not match * Octeon's link config if auto negotiation has changed since @@ -1233,8 +1194,7 @@ EXPORT_SYMBOL_GPL(cvmx_helper_link_get); * Configure an IPD/PKO port for the specified link state. This * function does not influence auto negotiation at the PHY level. * The passed link state must always match the link state returned - * by cvmx_helper_link_get(). It is normally best to use - * cvmx_helper_link_autoconf() instead. + * by cvmx_helper_link_get(). * * @ipd_port: IPD/PKO port to configure * @link_info: The new link state @@ -1276,11 +1236,6 @@ int cvmx_helper_link_set(int ipd_port, cvmx_helper_link_info_t link_info) case CVMX_HELPER_INTERFACE_MODE_LOOP: break; } - /* Set the port_link_info here so that the link status is updated - no matter how cvmx_helper_link_set is called. We don't change - the value if link_set failed */ - if (result == 0) - port_link_info[ipd_port].u64 = link_info.u64; return result; } EXPORT_SYMBOL_GPL(cvmx_helper_link_set); diff --git a/arch/mips/cavium-octeon/executive/cvmx-sysinfo.c b/arch/mips/cavium-octeon/executive/cvmx-sysinfo.c index cc1b1d2a6fa1..30ecba134e09 100644 --- a/arch/mips/cavium-octeon/executive/cvmx-sysinfo.c +++ b/arch/mips/cavium-octeon/executive/cvmx-sysinfo.c @@ -29,7 +29,7 @@ * This module provides system/board/application information obtained * by the bootloader. */ -#include <linux/module.h> +#include <linux/export.h> #include <asm/octeon/cvmx.h> #include <asm/octeon/cvmx-sysinfo.h> diff --git a/arch/mips/cavium-octeon/octeon-memcpy.S b/arch/mips/cavium-octeon/octeon-memcpy.S index 64e08df51d65..cfd97f6448bb 100644 --- a/arch/mips/cavium-octeon/octeon-memcpy.S +++ b/arch/mips/cavium-octeon/octeon-memcpy.S @@ -15,6 +15,7 @@ #include <asm/asm.h> #include <asm/asm-offsets.h> +#include <asm/export.h> #include <asm/regdef.h> #define dst a0 @@ -142,6 +143,7 @@ * t7 is used as a flag to note inatomic mode. */ LEAF(__copy_user_inatomic) +EXPORT_SYMBOL(__copy_user_inatomic) b __copy_user_common li t7, 1 END(__copy_user_inatomic) @@ -154,9 +156,11 @@ LEAF(__copy_user_inatomic) */ .align 5 LEAF(memcpy) /* a0=dst a1=src a2=len */ +EXPORT_SYMBOL(memcpy) move v0, dst /* return value */ __memcpy: FEXPORT(__copy_user) +EXPORT_SYMBOL(__copy_user) li t7, 0 /* not inatomic */ __copy_user_common: /* @@ -208,18 +212,18 @@ EXC( STORE t2, UNIT(6)(dst), s_exc_p10u) ADD src, src, 16*NBYTES EXC( STORE t3, UNIT(7)(dst), s_exc_p9u) ADD dst, dst, 16*NBYTES -EXC( LOAD t0, UNIT(-8)(src), l_exc_copy) -EXC( LOAD t1, UNIT(-7)(src), l_exc_copy) -EXC( LOAD t2, UNIT(-6)(src), l_exc_copy) -EXC( LOAD t3, UNIT(-5)(src), l_exc_copy) +EXC( LOAD t0, UNIT(-8)(src), l_exc_copy_rewind16) +EXC( LOAD t1, UNIT(-7)(src), l_exc_copy_rewind16) +EXC( LOAD t2, UNIT(-6)(src), l_exc_copy_rewind16) +EXC( LOAD t3, UNIT(-5)(src), l_exc_copy_rewind16) EXC( STORE t0, UNIT(-8)(dst), s_exc_p8u) EXC( STORE t1, UNIT(-7)(dst), s_exc_p7u) EXC( STORE t2, UNIT(-6)(dst), s_exc_p6u) EXC( STORE t3, UNIT(-5)(dst), s_exc_p5u) -EXC( LOAD t0, UNIT(-4)(src), l_exc_copy) -EXC( LOAD t1, UNIT(-3)(src), l_exc_copy) -EXC( LOAD t2, UNIT(-2)(src), l_exc_copy) -EXC( LOAD t3, UNIT(-1)(src), l_exc_copy) +EXC( LOAD t0, UNIT(-4)(src), l_exc_copy_rewind16) +EXC( LOAD t1, UNIT(-3)(src), l_exc_copy_rewind16) +EXC( LOAD t2, UNIT(-2)(src), l_exc_copy_rewind16) +EXC( LOAD t3, UNIT(-1)(src), l_exc_copy_rewind16) EXC( STORE t0, UNIT(-4)(dst), s_exc_p4u) EXC( STORE t1, UNIT(-3)(dst), s_exc_p3u) EXC( STORE t2, UNIT(-2)(dst), s_exc_p2u) @@ -383,6 +387,10 @@ done: nop END(memcpy) +l_exc_copy_rewind16: + /* Rewind src and dst by 16*NBYTES for l_exc_copy */ + SUB src, src, 16*NBYTES + SUB dst, dst, 16*NBYTES l_exc_copy: /* * Copy bytes from src until faulting load address (or until a @@ -459,6 +467,7 @@ s_exc: .align 5 LEAF(memmove) +EXPORT_SYMBOL(memmove) ADD t0, a0, a2 ADD t1, a1, a2 sltu t0, a1, t0 # dst + len <= src -> memcpy diff --git a/arch/mips/cavium-octeon/octeon-platform.c b/arch/mips/cavium-octeon/octeon-platform.c index 37a932d9148c..3375e61daa19 100644 --- a/arch/mips/cavium-octeon/octeon-platform.c +++ b/arch/mips/cavium-octeon/octeon-platform.c @@ -448,6 +448,7 @@ static struct of_device_id __initdata octeon_ids[] = { { .compatible = "cavium,octeon-3860-bootbus", }, { .compatible = "cavium,mdio-mux", }, { .compatible = "gpio-leds", }, + { .compatible = "cavium,octeon-7130-usb-uctl", }, {}, }; @@ -1060,7 +1061,3 @@ static int __init octeon_publish_devices(void) return of_platform_bus_probe(NULL, octeon_ids, NULL); } arch_initcall(octeon_publish_devices); - -MODULE_AUTHOR("David Daney <ddaney@caviumnetworks.com>"); -MODULE_LICENSE("GPL"); -MODULE_DESCRIPTION("Platform driver for Octeon SOC"); diff --git a/arch/mips/cavium-octeon/octeon-usb.c b/arch/mips/cavium-octeon/octeon-usb.c new file mode 100644 index 000000000000..542be1cd0f32 --- /dev/null +++ b/arch/mips/cavium-octeon/octeon-usb.c @@ -0,0 +1,552 @@ +/* + * XHCI HCD glue for Cavium Octeon III SOCs. + * + * Copyright (C) 2010-2017 Cavium Networks + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#include <linux/module.h> +#include <linux/device.h> +#include <linux/mutex.h> +#include <linux/delay.h> +#include <linux/of_platform.h> + +#include <asm/octeon/octeon.h> +#include <asm/octeon/cvmx-gpio-defs.h> + +/* USB Control Register */ +union cvm_usbdrd_uctl_ctl { + uint64_t u64; + struct cvm_usbdrd_uctl_ctl_s { + /* 1 = BIST and set all USB RAMs to 0x0, 0 = BIST */ + __BITFIELD_FIELD(uint64_t clear_bist:1, + /* 1 = Start BIST and cleared by hardware */ + __BITFIELD_FIELD(uint64_t start_bist:1, + /* Reference clock select for SuperSpeed and HighSpeed PLLs: + * 0x0 = Both PLLs use DLMC_REF_CLK0 for reference clock + * 0x1 = Both PLLs use DLMC_REF_CLK1 for reference clock + * 0x2 = SuperSpeed PLL uses DLMC_REF_CLK0 for reference clock & + * HighSpeed PLL uses PLL_REF_CLK for reference clck + * 0x3 = SuperSpeed PLL uses DLMC_REF_CLK1 for reference clock & + * HighSpeed PLL uses PLL_REF_CLK for reference clck + */ + __BITFIELD_FIELD(uint64_t ref_clk_sel:2, + /* 1 = Spread-spectrum clock enable, 0 = SS clock disable */ + __BITFIELD_FIELD(uint64_t ssc_en:1, + /* Spread-spectrum clock modulation range: + * 0x0 = -4980 ppm downspread + * 0x1 = -4492 ppm downspread + * 0x2 = -4003 ppm downspread + * 0x3 - 0x7 = Reserved + */ + __BITFIELD_FIELD(uint64_t ssc_range:3, + /* Enable non-standard oscillator frequencies: + * [55:53] = modules -1 + * [52:47] = 2's complement push amount, 0 = Feature disabled + */ + __BITFIELD_FIELD(uint64_t ssc_ref_clk_sel:9, + /* Reference clock multiplier for non-standard frequencies: + * 0x19 = 100MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1 + * 0x28 = 125MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1 + * 0x32 = 50MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1 + * Other Values = Reserved + */ + __BITFIELD_FIELD(uint64_t mpll_multiplier:7, + /* Enable reference clock to prescaler for SuperSpeed functionality. + * Should always be set to "1" + */ + __BITFIELD_FIELD(uint64_t ref_ssp_en:1, + /* Divide the reference clock by 2 before entering the + * REF_CLK_FSEL divider: + * If REF_CLK_SEL = 0x0 or 0x1, then only 0x0 is legal + * If REF_CLK_SEL = 0x2 or 0x3, then: + * 0x1 = DLMC_REF_CLK* is 125MHz + * 0x0 = DLMC_REF_CLK* is another supported frequency + */ + __BITFIELD_FIELD(uint64_t ref_clk_div2:1, + /* Select reference clock freqnuency for both PLL blocks: + * 0x27 = REF_CLK_SEL is 0x0 or 0x1 + * 0x07 = REF_CLK_SEL is 0x2 or 0x3 + */ + __BITFIELD_FIELD(uint64_t ref_clk_fsel:6, + /* Reserved */ + __BITFIELD_FIELD(uint64_t reserved_31_31:1, + /* Controller clock enable. */ + __BITFIELD_FIELD(uint64_t h_clk_en:1, + /* Select bypass input to controller clock divider: + * 0x0 = Use divided coprocessor clock from H_CLKDIV + * 0x1 = Use clock from GPIO pins + */ + __BITFIELD_FIELD(uint64_t h_clk_byp_sel:1, + /* Reset controller clock divider. */ + __BITFIELD_FIELD(uint64_t h_clkdiv_rst:1, + /* Reserved */ + __BITFIELD_FIELD(uint64_t reserved_27_27:1, + /* Clock divider select: + * 0x0 = divide by 1 + * 0x1 = divide by 2 + * 0x2 = divide by 4 + * 0x3 = divide by 6 + * 0x4 = divide by 8 + * 0x5 = divide by 16 + * 0x6 = divide by 24 + * 0x7 = divide by 32 + */ + __BITFIELD_FIELD(uint64_t h_clkdiv_sel:3, + /* Reserved */ + __BITFIELD_FIELD(uint64_t reserved_22_23:2, + /* USB3 port permanently attached: 0x0 = No, 0x1 = Yes */ + __BITFIELD_FIELD(uint64_t usb3_port_perm_attach:1, + /* USB2 port permanently attached: 0x0 = No, 0x1 = Yes */ + __BITFIELD_FIELD(uint64_t usb2_port_perm_attach:1, + /* Reserved */ + __BITFIELD_FIELD(uint64_t reserved_19_19:1, + /* Disable SuperSpeed PHY: 0x0 = No, 0x1 = Yes */ + __BITFIELD_FIELD(uint64_t usb3_port_disable:1, + /* Reserved */ + __BITFIELD_FIELD(uint64_t reserved_17_17:1, + /* Disable HighSpeed PHY: 0x0 = No, 0x1 = Yes */ + __BITFIELD_FIELD(uint64_t usb2_port_disable:1, + /* Reserved */ + __BITFIELD_FIELD(uint64_t reserved_15_15:1, + /* Enable PHY SuperSpeed block power: 0x0 = No, 0x1 = Yes */ + __BITFIELD_FIELD(uint64_t ss_power_en:1, + /* Reserved */ + __BITFIELD_FIELD(uint64_t reserved_13_13:1, + /* Enable PHY HighSpeed block power: 0x0 = No, 0x1 = Yes */ + __BITFIELD_FIELD(uint64_t hs_power_en:1, + /* Reserved */ + __BITFIELD_FIELD(uint64_t reserved_5_11:7, + /* Enable USB UCTL interface clock: 0xx = No, 0x1 = Yes */ + __BITFIELD_FIELD(uint64_t csclk_en:1, + /* Controller mode: 0x0 = Host, 0x1 = Device */ + __BITFIELD_FIELD(uint64_t drd_mode:1, + /* PHY reset */ + __BITFIELD_FIELD(uint64_t uphy_rst:1, + /* Software reset UAHC */ + __BITFIELD_FIELD(uint64_t uahc_rst:1, + /* Software resets UCTL */ + __BITFIELD_FIELD(uint64_t uctl_rst:1, + ;))))))))))))))))))))))))))))))))) + } s; +}; + +/* UAHC Configuration Register */ +union cvm_usbdrd_uctl_host_cfg { + uint64_t u64; + struct cvm_usbdrd_uctl_host_cfg_s { + /* Reserved */ + __BITFIELD_FIELD(uint64_t reserved_60_63:4, + /* Indicates minimum value of all received BELT values */ + __BITFIELD_FIELD(uint64_t host_current_belt:12, + /* Reserved */ + __BITFIELD_FIELD(uint64_t reserved_38_47:10, + /* HS jitter adjustment */ + __BITFIELD_FIELD(uint64_t fla:6, + /* Reserved */ + __BITFIELD_FIELD(uint64_t reserved_29_31:3, + /* Bus-master enable: 0x0 = Disabled (stall DMAs), 0x1 = enabled */ + __BITFIELD_FIELD(uint64_t bme:1, + /* Overcurrent protection enable: 0x0 = unavailable, 0x1 = available */ + __BITFIELD_FIELD(uint64_t oci_en:1, + /* Overcurrent sene selection: + * 0x0 = Overcurrent indication from off-chip is active-low + * 0x1 = Overcurrent indication from off-chip is active-high + */ + __BITFIELD_FIELD(uint64_t oci_active_high_en:1, + /* Port power control enable: 0x0 = unavailable, 0x1 = available */ + __BITFIELD_FIELD(uint64_t ppc_en:1, + /* Port power control sense selection: + * 0x0 = Port power to off-chip is active-low + * 0x1 = Port power to off-chip is active-high + */ + __BITFIELD_FIELD(uint64_t ppc_active_high_en:1, + /* Reserved */ + __BITFIELD_FIELD(uint64_t reserved_0_23:24, + ;))))))))))) + } s; +}; + +/* UCTL Shim Features Register */ +union cvm_usbdrd_uctl_shim_cfg { + uint64_t u64; + struct cvm_usbdrd_uctl_shim_cfg_s { + /* Out-of-bound UAHC register access: 0 = read, 1 = write */ + __BITFIELD_FIELD(uint64_t xs_ncb_oob_wrn:1, + /* Reserved */ + __BITFIELD_FIELD(uint64_t reserved_60_62:3, + /* SRCID error log for out-of-bound UAHC register access: + * [59:58] = chipID + * [57] = Request source: 0 = core, 1 = NCB-device + * [56:51] = Core/NCB-device number, [56] always 0 for NCB devices + * [50:48] = SubID + */ + __BITFIELD_FIELD(uint64_t xs_ncb_oob_osrc:12, + /* Error log for bad UAHC DMA access: 0 = Read log, 1 = Write log */ + __BITFIELD_FIELD(uint64_t xm_bad_dma_wrn:1, + /* Reserved */ + __BITFIELD_FIELD(uint64_t reserved_44_46:3, + /* Encoded error type for bad UAHC DMA */ + __BITFIELD_FIELD(uint64_t xm_bad_dma_type:4, + /* Reserved */ + __BITFIELD_FIELD(uint64_t reserved_13_39:27, + /* Select the IOI read command used by DMA accesses */ + __BITFIELD_FIELD(uint64_t dma_read_cmd:1, + /* Reserved */ + __BITFIELD_FIELD(uint64_t reserved_10_11:2, + /* Select endian format for DMA accesses to the L2c: + * 0x0 = Little endian + *` 0x1 = Big endian + * 0x2 = Reserved + * 0x3 = Reserved + */ + __BITFIELD_FIELD(uint64_t dma_endian_mode:2, + /* Reserved */ + __BITFIELD_FIELD(uint64_t reserved_2_7:6, + /* Select endian format for IOI CSR access to UAHC: + * 0x0 = Little endian + *` 0x1 = Big endian + * 0x2 = Reserved + * 0x3 = Reserved + */ + __BITFIELD_FIELD(uint64_t csr_endian_mode:2, + ;)))))))))))) + } s; +}; + +#define OCTEON_H_CLKDIV_SEL 8 +#define OCTEON_MIN_H_CLK_RATE 150000000 +#define OCTEON_MAX_H_CLK_RATE 300000000 + +static DEFINE_MUTEX(dwc3_octeon_clocks_mutex); +static uint8_t clk_div[OCTEON_H_CLKDIV_SEL] = {1, 2, 4, 6, 8, 16, 24, 32}; + + +static int dwc3_octeon_config_power(struct device *dev, u64 base) +{ +#define UCTL_HOST_CFG 0xe0 + union cvm_usbdrd_uctl_host_cfg uctl_host_cfg; + union cvmx_gpio_bit_cfgx gpio_bit; + uint32_t gpio_pwr[3]; + int gpio, len, power_active_low; + struct device_node *node = dev->of_node; + int index = (base >> 24) & 1; + + if (of_find_property(node, "power", &len) != NULL) { + if (len == 12) { + of_property_read_u32_array(node, "power", gpio_pwr, 3); + power_active_low = gpio_pwr[2] & 0x01; + gpio = gpio_pwr[1]; + } else if (len == 8) { + of_property_read_u32_array(node, "power", gpio_pwr, 2); + power_active_low = 0; + gpio = gpio_pwr[1]; + } else { + dev_err(dev, "dwc3 controller clock init failure.\n"); + return -EINVAL; + } + if ((OCTEON_IS_MODEL(OCTEON_CN73XX) || + OCTEON_IS_MODEL(OCTEON_CNF75XX)) + && gpio <= 31) { + gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(gpio)); + gpio_bit.s.tx_oe = 1; + gpio_bit.cn73xx.output_sel = (index == 0 ? 0x14 : 0x15); + cvmx_write_csr(CVMX_GPIO_BIT_CFGX(gpio), gpio_bit.u64); + } else if (gpio <= 15) { + gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(gpio)); + gpio_bit.s.tx_oe = 1; + gpio_bit.cn70xx.output_sel = (index == 0 ? 0x14 : 0x19); + cvmx_write_csr(CVMX_GPIO_BIT_CFGX(gpio), gpio_bit.u64); + } else { + gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_XBIT_CFGX(gpio)); + gpio_bit.s.tx_oe = 1; + gpio_bit.cn70xx.output_sel = (index == 0 ? 0x14 : 0x19); + cvmx_write_csr(CVMX_GPIO_XBIT_CFGX(gpio), gpio_bit.u64); + } + + /* Enable XHCI power control and set if active high or low. */ + uctl_host_cfg.u64 = cvmx_read_csr(base + UCTL_HOST_CFG); + uctl_host_cfg.s.ppc_en = 1; + uctl_host_cfg.s.ppc_active_high_en = !power_active_low; + cvmx_write_csr(base + UCTL_HOST_CFG, uctl_host_cfg.u64); + } else { + /* Disable XHCI power control and set if active high. */ + uctl_host_cfg.u64 = cvmx_read_csr(base + UCTL_HOST_CFG); + uctl_host_cfg.s.ppc_en = 0; + uctl_host_cfg.s.ppc_active_high_en = 0; + cvmx_write_csr(base + UCTL_HOST_CFG, uctl_host_cfg.u64); + dev_warn(dev, "dwc3 controller clock init failure.\n"); + } + return 0; +} + +static int dwc3_octeon_clocks_start(struct device *dev, u64 base) +{ + union cvm_usbdrd_uctl_ctl uctl_ctl; + int ref_clk_sel = 2; + u64 div; + u32 clock_rate; + int mpll_mul; + int i; + u64 h_clk_rate; + u64 uctl_ctl_reg = base; + + if (dev->of_node) { + const char *ss_clock_type; + const char *hs_clock_type; + + i = of_property_read_u32(dev->of_node, + "refclk-frequency", &clock_rate); + if (i) { + pr_err("No UCTL \"refclk-frequency\"\n"); + return -EINVAL; + } + i = of_property_read_string(dev->of_node, + "refclk-type-ss", &ss_clock_type); + if (i) { + pr_err("No UCTL \"refclk-type-ss\"\n"); + return -EINVAL; + } + i = of_property_read_string(dev->of_node, + "refclk-type-hs", &hs_clock_type); + if (i) { + pr_err("No UCTL \"refclk-type-hs\"\n"); + return -EINVAL; + } + if (strcmp("dlmc_ref_clk0", ss_clock_type) == 0) { + if (strcmp(hs_clock_type, "dlmc_ref_clk0") == 0) + ref_clk_sel = 0; + else if (strcmp(hs_clock_type, "pll_ref_clk") == 0) + ref_clk_sel = 2; + else + pr_err("Invalid HS clock type %s, using pll_ref_clk instead\n", + hs_clock_type); + } else if (strcmp(ss_clock_type, "dlmc_ref_clk1") == 0) { + if (strcmp(hs_clock_type, "dlmc_ref_clk1") == 0) + ref_clk_sel = 1; + else if (strcmp(hs_clock_type, "pll_ref_clk") == 0) + ref_clk_sel = 3; + else { + pr_err("Invalid HS clock type %s, using pll_ref_clk instead\n", + hs_clock_type); + ref_clk_sel = 3; + } + } else + pr_err("Invalid SS clock type %s, using dlmc_ref_clk0 instead\n", + ss_clock_type); + + if ((ref_clk_sel == 0 || ref_clk_sel == 1) && + (clock_rate != 100000000)) + pr_err("Invalid UCTL clock rate of %u, using 100000000 instead\n", + clock_rate); + + } else { + pr_err("No USB UCTL device node\n"); + return -EINVAL; + } + + /* + * Step 1: Wait for all voltages to be stable...that surely + * happened before starting the kernel. SKIP + */ + + /* Step 2: Select GPIO for overcurrent indication, if desired. SKIP */ + + /* Step 3: Assert all resets. */ + uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg); + uctl_ctl.s.uphy_rst = 1; + uctl_ctl.s.uahc_rst = 1; + uctl_ctl.s.uctl_rst = 1; + cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64); + + /* Step 4a: Reset the clock dividers. */ + uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg); + uctl_ctl.s.h_clkdiv_rst = 1; + cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64); + + /* Step 4b: Select controller clock frequency. */ + for (div = 0; div < OCTEON_H_CLKDIV_SEL; div++) { + h_clk_rate = octeon_get_io_clock_rate() / clk_div[div]; + if (h_clk_rate <= OCTEON_MAX_H_CLK_RATE && + h_clk_rate >= OCTEON_MIN_H_CLK_RATE) + break; + } + uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg); + uctl_ctl.s.h_clkdiv_sel = div; + uctl_ctl.s.h_clk_en = 1; + cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64); + uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg); + if ((div != uctl_ctl.s.h_clkdiv_sel) || (!uctl_ctl.s.h_clk_en)) { + dev_err(dev, "dwc3 controller clock init failure.\n"); + return -EINVAL; + } + + /* Step 4c: Deassert the controller clock divider reset. */ + uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg); + uctl_ctl.s.h_clkdiv_rst = 0; + cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64); + + /* Step 5a: Reference clock configuration. */ + uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg); + uctl_ctl.s.ref_clk_sel = ref_clk_sel; + uctl_ctl.s.ref_clk_fsel = 0x07; + uctl_ctl.s.ref_clk_div2 = 0; + switch (clock_rate) { + default: + dev_err(dev, "Invalid ref_clk %u, using 100000000 instead\n", + clock_rate); + case 100000000: + mpll_mul = 0x19; + if (ref_clk_sel < 2) + uctl_ctl.s.ref_clk_fsel = 0x27; + break; + case 50000000: + mpll_mul = 0x32; + break; + case 125000000: + mpll_mul = 0x28; + break; + } + uctl_ctl.s.mpll_multiplier = mpll_mul; + + /* Step 5b: Configure and enable spread-spectrum for SuperSpeed. */ + uctl_ctl.s.ssc_en = 1; + + /* Step 5c: Enable SuperSpeed. */ + uctl_ctl.s.ref_ssp_en = 1; + + /* Step 5d: Cofngiure PHYs. SKIP */ + + /* Step 6a & 6b: Power up PHYs. */ + uctl_ctl.s.hs_power_en = 1; + uctl_ctl.s.ss_power_en = 1; + cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64); + + /* Step 7: Wait 10 controller-clock cycles to take effect. */ + udelay(10); + + /* Step 8a: Deassert UCTL reset signal. */ + uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg); + uctl_ctl.s.uctl_rst = 0; + cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64); + + /* Step 8b: Wait 10 controller-clock cycles. */ + udelay(10); + + /* Steo 8c: Setup power-power control. */ + if (dwc3_octeon_config_power(dev, base)) { + dev_err(dev, "Error configuring power.\n"); + return -EINVAL; + } + + /* Step 8d: Deassert UAHC reset signal. */ + uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg); + uctl_ctl.s.uahc_rst = 0; + cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64); + + /* Step 8e: Wait 10 controller-clock cycles. */ + udelay(10); + + /* Step 9: Enable conditional coprocessor clock of UCTL. */ + uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg); + uctl_ctl.s.csclk_en = 1; + cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64); + + /*Step 10: Set for host mode only. */ + uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg); + uctl_ctl.s.drd_mode = 0; + cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64); + + return 0; +} + +static void __init dwc3_octeon_set_endian_mode(u64 base) +{ +#define UCTL_SHIM_CFG 0xe8 + union cvm_usbdrd_uctl_shim_cfg shim_cfg; + + shim_cfg.u64 = cvmx_read_csr(base + UCTL_SHIM_CFG); +#ifdef __BIG_ENDIAN + shim_cfg.s.dma_endian_mode = 1; + shim_cfg.s.csr_endian_mode = 1; +#else + shim_cfg.s.dma_endian_mode = 0; + shim_cfg.s.csr_endian_mode = 0; +#endif + cvmx_write_csr(base + UCTL_SHIM_CFG, shim_cfg.u64); +} + +#define CVMX_USBDRDX_UCTL_CTL(index) \ + (CVMX_ADD_IO_SEG(0x0001180068000000ull) + \ + ((index & 1) * 0x1000000ull)) +static void __init dwc3_octeon_phy_reset(u64 base) +{ + union cvm_usbdrd_uctl_ctl uctl_ctl; + int index = (base >> 24) & 1; + + uctl_ctl.u64 = cvmx_read_csr(CVMX_USBDRDX_UCTL_CTL(index)); + uctl_ctl.s.uphy_rst = 0; + cvmx_write_csr(CVMX_USBDRDX_UCTL_CTL(index), uctl_ctl.u64); +} + +static int __init dwc3_octeon_device_init(void) +{ + const char compat_node_name[] = "cavium,octeon-7130-usb-uctl"; + struct platform_device *pdev; + struct device_node *node; + struct resource *res; + void __iomem *base; + + /* + * There should only be three universal controllers, "uctl" + * in the device tree. Two USB and a SATA, which we ignore. + */ + node = NULL; + do { + node = of_find_node_by_name(node, "uctl"); + if (!node) + return -ENODEV; + + if (of_device_is_compatible(node, compat_node_name)) { + pdev = of_find_device_by_node(node); + if (!pdev) + return -ENODEV; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res == NULL) { + dev_err(&pdev->dev, "No memory resources\n"); + return -ENXIO; + } + + /* + * The code below maps in the registers necessary for + * setting up the clocks and reseting PHYs. We must + * release the resources so the dwc3 subsystem doesn't + * know the difference. + */ + base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + mutex_lock(&dwc3_octeon_clocks_mutex); + dwc3_octeon_clocks_start(&pdev->dev, (u64)base); + dwc3_octeon_set_endian_mode((u64)base); + dwc3_octeon_phy_reset((u64)base); + dev_info(&pdev->dev, "clocks initialized.\n"); + mutex_unlock(&dwc3_octeon_clocks_mutex); + devm_iounmap(&pdev->dev, base); + devm_release_mem_region(&pdev->dev, res->start, + resource_size(res)); + } + } while (node != NULL); + + return 0; +} +device_initcall(dwc3_octeon_device_init); + +MODULE_AUTHOR("David Daney <david.daney@cavium.com>"); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("USB driver for OCTEON III SoC"); diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c index 9a2db1c013d9..d9dbeb0b165b 100644 --- a/arch/mips/cavium-octeon/setup.c +++ b/arch/mips/cavium-octeon/setup.c @@ -949,6 +949,29 @@ static __init void memory_exclude_page(u64 addr, u64 *mem, u64 *size) } #endif /* CONFIG_CRASH_DUMP */ +void __init fw_init_cmdline(void) +{ + int i; + + octeon_boot_desc_ptr = (struct octeon_boot_descriptor *)fw_arg3; + for (i = 0; i < octeon_boot_desc_ptr->argc; i++) { + const char *arg = + cvmx_phys_to_ptr(octeon_boot_desc_ptr->argv[i]); + if (strlen(arcs_cmdline) + strlen(arg) + 1 < + sizeof(arcs_cmdline) - 1) { + strcat(arcs_cmdline, " "); + strcat(arcs_cmdline, arg); + } + } +} + +void __init *plat_get_fdt(void) +{ + octeon_bootinfo = + cvmx_phys_to_ptr(octeon_boot_desc_ptr->cvmx_desc_vaddr); + return phys_to_virt(octeon_bootinfo->fdt_addr); +} + void __init plat_mem_setup(void) { uint64_t mem_alloc_size; diff --git a/arch/mips/cavium-octeon/smp.c b/arch/mips/cavium-octeon/smp.c index 256fe6f65cf2..4355a4cf4d74 100644 --- a/arch/mips/cavium-octeon/smp.c +++ b/arch/mips/cavium-octeon/smp.c @@ -11,7 +11,8 @@ #include <linux/interrupt.h> #include <linux/kernel_stat.h> #include <linux/sched.h> -#include <linux/module.h> +#include <linux/init.h> +#include <linux/export.h> #include <asm/mmu_context.h> #include <asm/time.h> @@ -24,12 +25,17 @@ volatile unsigned long octeon_processor_boot = 0xff; volatile unsigned long octeon_processor_sp; volatile unsigned long octeon_processor_gp; +#ifdef CONFIG_RELOCATABLE +volatile unsigned long octeon_processor_relocated_kernel_entry; +#endif /* CONFIG_RELOCATABLE */ #ifdef CONFIG_HOTPLUG_CPU uint64_t octeon_bootloader_entry_addr; EXPORT_SYMBOL(octeon_bootloader_entry_addr); #endif +extern void kernel_entry(unsigned long arg1, ...); + static void octeon_icache_flush(void) { asm volatile ("synci 0($0)\n"); @@ -180,6 +186,19 @@ static void __init octeon_smp_setup(void) octeon_smp_hotplug_setup(); } + +#ifdef CONFIG_RELOCATABLE +int plat_post_relocation(long offset) +{ + unsigned long entry = (unsigned long)kernel_entry; + + /* Send secondaries into relocated kernel */ + octeon_processor_relocated_kernel_entry = entry + offset; + + return 0; +} +#endif /* CONFIG_RELOCATABLE */ + /** * Firmware CPU startup hook * @@ -272,7 +291,6 @@ static int octeon_cpu_disable(void) set_cpu_online(cpu, false); calculate_cpu_foreign_map(); - cpumask_clear_cpu(cpu, &cpu_callin_map); octeon_fixup_irqs(); __flush_cache_all(); @@ -333,8 +351,6 @@ void play_dead(void) ; } -extern void kernel_entry(unsigned long arg1, ...); - static void start_after_reset(void) { kernel_entry(0, 0, 0); /* set a2 = 0 for secondary core */ |