diff options
Diffstat (limited to 'arch/arm')
894 files changed, 12029 insertions, 21699 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 3996b6572c3a..fe2f17eb2b50 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -120,6 +120,7 @@ config ARM select PCI_SYSCALL if PCI select PERF_USE_VMALLOC select RTC_LIB + select SET_FS select SYS_SUPPORTS_APM_EMULATION # Above selects are sorted alphabetically; please add new ones # according to that. Thanks. @@ -267,9 +268,7 @@ config PHYS_OFFSET depends on !ARM_PATCH_PHYS_VIRT default DRAM_BASE if !MMU default 0x00000000 if ARCH_EBSA110 || \ - ARCH_FOOTBRIDGE || \ - ARCH_INTEGRATOR || \ - ARCH_REALVIEW + ARCH_FOOTBRIDGE default 0x10000000 if ARCH_OMAP1 || ARCH_RPC default 0x20000000 if ARCH_S5PV210 default 0xc0000000 if ARCH_SA1100 @@ -505,11 +504,12 @@ config ARCH_S3C24XX select GPIOLIB select GENERIC_IRQ_MULTI_HANDLER select HAVE_S3C2410_I2C if I2C - select HAVE_S3C2410_WATCHDOG if WATCHDOG select HAVE_S3C_RTC if RTC_CLASS select NEED_MACH_IO_H + select S3C2410_WATCHDOG select SAMSUNG_ATAGS select USE_OF + select WATCHDOG help Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST @@ -638,7 +638,6 @@ source "arch/arm/mach-dove/Kconfig" source "arch/arm/mach-ep93xx/Kconfig" source "arch/arm/mach-exynos/Kconfig" -source "arch/arm/plat-samsung/Kconfig" source "arch/arm/mach-footbridge/Kconfig" @@ -711,9 +710,7 @@ source "arch/arm/mach-realview/Kconfig" source "arch/arm/mach-rockchip/Kconfig" -source "arch/arm/mach-s3c24xx/Kconfig" - -source "arch/arm/mach-s3c64xx/Kconfig" +source "arch/arm/mach-s3c/Kconfig" source "arch/arm/mach-s5pv210/Kconfig" diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 80000a66a4e3..8986a91a6f31 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -1005,7 +1005,7 @@ choice via SCIFA4 on Renesas SH-Mobile AG5 (SH73A0). config DEBUG_S3C_UART0 - depends on PLAT_SAMSUNG + depends on PLAT_SAMSUNG || ARCH_S5PV210 || ARCH_EXYNOS select DEBUG_EXYNOS_UART if ARCH_EXYNOS select DEBUG_S3C24XX_UART if ARCH_S3C24XX select DEBUG_S3C64XX_UART if ARCH_S3C64XX @@ -1017,7 +1017,7 @@ choice by the boot-loader before use. config DEBUG_S3C_UART1 - depends on PLAT_SAMSUNG + depends on PLAT_SAMSUNG || ARCH_S5PV210 || ARCH_EXYNOS select DEBUG_EXYNOS_UART if ARCH_EXYNOS select DEBUG_S3C24XX_UART if ARCH_S3C24XX select DEBUG_S3C64XX_UART if ARCH_S3C64XX @@ -1029,7 +1029,7 @@ choice by the boot-loader before use. config DEBUG_S3C_UART2 - depends on PLAT_SAMSUNG + depends on PLAT_SAMSUNG || ARCH_S5PV210 || ARCH_EXYNOS select DEBUG_EXYNOS_UART if ARCH_EXYNOS select DEBUG_S3C24XX_UART if ARCH_S3C24XX select DEBUG_S3C64XX_UART if ARCH_S3C64XX @@ -1041,7 +1041,7 @@ choice by the boot-loader before use. config DEBUG_S3C_UART3 - depends on PLAT_SAMSUNG && (ARCH_EXYNOS || ARCH_S5PV210) + depends on ARCH_EXYNOS || ARCH_S5PV210 select DEBUG_EXYNOS_UART if ARCH_EXYNOS select DEBUG_S3C64XX_UART if ARCH_S3C64XX select DEBUG_S5PV210_UART if ARCH_S5PV210 @@ -1086,6 +1086,14 @@ choice on SA-11x0 UART ports. The kernel will check for the first enabled UART in a sequence 3-1-2. + config DEBUG_SD5203_UART + bool "Hisilicon SD5203 Debug UART" + depends on ARCH_SD5203 + select DEBUG_UART_8250 + help + Say Y here if you want kernel low-level debugging support + on SD5203 UART. + config DEBUG_SOCFPGA_UART0 depends on ARCH_SOCFPGA bool "Use SOCFPGA UART0 for low-level debug" @@ -1497,6 +1505,16 @@ config DEBUG_S3C64XX_UART config DEBUG_S5PV210_UART bool +config DEBUG_S3C_UART + depends on DEBUG_S3C2410_UART || DEBUG_S3C24XX_UART || \ + DEBUG_S3C64XX_UART || DEBUG_S5PV210_UART || \ + DEBUG_EXYNOS_UART + int + default "0" if DEBUG_S3C_UART0 + default "1" if DEBUG_S3C_UART1 + default "2" if DEBUG_S3C_UART2 + default "3" if DEBUG_S3C_UART3 + config DEBUG_OMAP2PLUS_UART bool depends on ARCH_OMAP2PLUS @@ -1546,6 +1564,17 @@ config DEBUG_SIRFSOC_UART bool depends on ARCH_SIRF +config DEBUG_UART_FLOW_CONTROL + bool "Enable flow control (CTS) for the debug UART" + depends on DEBUG_LL + default y if ARCH_EBSA110 || DEBUG_FOOTBRIDGE_COM1 || DEBUG_GEMINI || ARCH_RPC + help + Some UART ports are connected to terminals that will use modem + control signals to indicate whether they are ready to receive text. + In practice this means that the terminal is asserting the special + control signal CTS (Clear To Send). If your debug UART supports + this and your debug terminal will require it, enable this option. + config DEBUG_LL_INCLUDE string default "debug/sa1100.S" if DEBUG_SA1100 @@ -1639,6 +1668,7 @@ config DEBUG_UART_PHYS default 0x11006000 if DEBUG_MT6589_UART0 default 0x11009000 if DEBUG_MT8135_UART3 default 0x16000000 if DEBUG_INTEGRATOR + default 0x1600d000 if DEBUG_SD5203_UART default 0x18000300 if DEBUG_BCM_5301X default 0x18000400 if DEBUG_BCM_HR2 default 0x18010000 if DEBUG_SIRFATLAS7_UART0 @@ -1841,7 +1871,7 @@ config DEBUG_UART_VIRT default 0xfec60000 if DEBUG_SIRFPRIMA2_UART1 default 0xfec90000 if DEBUG_RK32_UART2 default 0xfed0c000 if DEBUG_DAVINCI_DA8XX_UART1 - default 0xfed0d000 if DEBUG_DAVINCI_DA8XX_UART2 + default 0xfed0d000 if DEBUG_DAVINCI_DA8XX_UART2 || DEBUG_SD5203_UART default 0xfed60000 if DEBUG_RK29_UART0 default 0xfed64000 if DEBUG_RK29_UART1 || DEBUG_RK3X_UART2 default 0xfed68000 if DEBUG_RK29_UART2 || DEBUG_RK3X_UART3 @@ -1893,11 +1923,6 @@ config DEBUG_UART_8250_PALMCHIP except for having a different register layout. Say Y here if the debug UART is of this type. -config DEBUG_UART_8250_FLOW_CONTROL - bool "Enable flow control for 8250 UART" - depends on DEBUG_LL_UART_8250 || DEBUG_UART_8250 - default y if ARCH_EBSA110 || DEBUG_FOOTBRIDGE_COM1 || DEBUG_GEMINI || ARCH_RPC - config DEBUG_UNCOMPRESS bool "Enable decompressor debugging via DEBUG_LL output" depends on ARCH_MULTIPLATFORM || PLAT_SAMSUNG || ARM_SINGLE_ARMV7M diff --git a/arch/arm/Makefile b/arch/arm/Makefile index e589da3c8949..4d76eab2b22d 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -20,10 +20,6 @@ endif # linker. All sections should be explicitly named in the linker script. LDFLAGS_vmlinux += $(call ld-option, --orphan-handling=warn) -ifeq ($(CONFIG_ARM_MODULE_PLTS),y) -KBUILD_LDS_MODULE += $(srctree)/arch/arm/kernel/module.lds -endif - GZFLAGS :=-9 #KBUILD_CFLAGS +=-pipe @@ -143,6 +139,9 @@ head-y := arch/arm/kernel/head$(MMUEXT).o # Text offset. This list is sorted numerically by address in order to # provide a means to avoid/resolve conflicts in multi-arch kernels. +# Note: the 32kB below this value is reserved for use by the kernel +# during boot, and this offset is critical to the functioning of +# kexec-tools. textofs-y := 0x00008000 # We don't want the htc bootloader to corrupt kernel during resume textofs-$(CONFIG_PM_H1940) := 0x00108000 @@ -213,8 +212,7 @@ machine-$(CONFIG_ARCH_REALTEK) += realtek machine-$(CONFIG_ARCH_REALVIEW) += realview machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip machine-$(CONFIG_ARCH_RPC) += rpc -machine-$(CONFIG_ARCH_S3C24XX) += s3c24xx -machine-$(CONFIG_ARCH_S3C64XX) += s3c64xx +machine-$(CONFIG_PLAT_SAMSUNG) += s3c machine-$(CONFIG_ARCH_S5PV210) += s5pv210 machine-$(CONFIG_ARCH_SA1100) += sa1100 machine-$(CONFIG_ARCH_RENESAS) += shmobile @@ -236,13 +234,9 @@ machine-$(CONFIG_PLAT_SPEAR) += spear # Platform directory name. This list is sorted alphanumerically # by CONFIG_* macro name. -plat-$(CONFIG_ARCH_EXYNOS) += samsung plat-$(CONFIG_ARCH_OMAP) += omap -plat-$(CONFIG_ARCH_S3C64XX) += samsung -plat-$(CONFIG_ARCH_S5PV210) += samsung plat-$(CONFIG_PLAT_ORION) += orion plat-$(CONFIG_PLAT_PXA) += pxa -plat-$(CONFIG_PLAT_S3C24XX) += samsung plat-$(CONFIG_PLAT_VERSATILE) += versatile ifeq ($(CONFIG_ARCH_EBSA110),y) diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile index 58028abd05d9..47f001ca5499 100644 --- a/arch/arm/boot/compressed/Makefile +++ b/arch/arm/boot/compressed/Makefile @@ -7,11 +7,11 @@ OBJS = -AFLAGS_head.o += -DTEXT_OFFSET=$(TEXT_OFFSET) HEAD = head.o OBJS += misc.o decompress.o ifeq ($(CONFIG_DEBUG_UNCOMPRESS),y) OBJS += debug.o +AFLAGS_head.o += -DDEBUG endif FONTC = $(srctree)/lib/fonts/font_acorn_8x8.c @@ -68,7 +68,12 @@ ZTEXTADDR := 0 ZBSSADDR := ALIGN(8) endif +MALLOC_SIZE := 65536 + +AFLAGS_head.o += -DTEXT_OFFSET=$(TEXT_OFFSET) -DMALLOC_SIZE=$(MALLOC_SIZE) CPPFLAGS_vmlinux.lds := -DTEXT_START="$(ZTEXTADDR)" -DBSS_START="$(ZBSSADDR)" +CPPFLAGS_vmlinux.lds += -DTEXT_OFFSET="$(TEXT_OFFSET)" +CPPFLAGS_vmlinux.lds += -DMALLOC_SIZE="$(MALLOC_SIZE)" compress-$(CONFIG_KERNEL_GZIP) = gzip compress-$(CONFIG_KERNEL_LZO) = lzo diff --git a/arch/arm/boot/compressed/debug.S b/arch/arm/boot/compressed/debug.S index 6bf2917a4621..fac40a717fcf 100644 --- a/arch/arm/boot/compressed/debug.S +++ b/arch/arm/boot/compressed/debug.S @@ -8,7 +8,10 @@ ENTRY(putc) addruart r1, r2, r3 - waituart r3, r1 +#ifdef CONFIG_DEBUG_UART_FLOW_CONTROL + waituartcts r3, r1 +#endif + waituarttxrdy r3, r1 senduart r0, r1 busyuart r3, r1 mov pc, lr diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index 434a16982e34..caa27322a0ab 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -28,19 +28,19 @@ #if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) || defined(CONFIG_CPU_V7) .macro loadsp, rb, tmp1, tmp2 .endm - .macro writeb, ch, rb + .macro writeb, ch, rb, tmp mcr p14, 0, \ch, c0, c5, 0 .endm #elif defined(CONFIG_CPU_XSCALE) .macro loadsp, rb, tmp1, tmp2 .endm - .macro writeb, ch, rb + .macro writeb, ch, rb, tmp mcr p14, 0, \ch, c8, c0, 0 .endm #else .macro loadsp, rb, tmp1, tmp2 .endm - .macro writeb, ch, rb + .macro writeb, ch, rb, tmp mcr p14, 0, \ch, c1, c0, 0 .endm #endif @@ -49,8 +49,13 @@ #include CONFIG_DEBUG_LL_INCLUDE - .macro writeb, ch, rb + .macro writeb, ch, rb, tmp +#ifdef CONFIG_DEBUG_UART_FLOW_CONTROL + waituartcts \tmp, \rb +#endif + waituarttxrdy \tmp, \rb senduart \ch, \rb + busyuart \tmp, \rb .endm #if defined(CONFIG_ARCH_SA1100) @@ -81,42 +86,11 @@ bl phex .endm - .macro debug_reloc_start -#ifdef DEBUG - kputc #'\n' - kphex r6, 8 /* processor id */ - kputc #':' - kphex r7, 8 /* architecture id */ -#ifdef CONFIG_CPU_CP15 - kputc #':' - mrc p15, 0, r0, c1, c0 - kphex r0, 8 /* control reg */ -#endif - kputc #'\n' - kphex r5, 8 /* decompressed kernel start */ - kputc #'-' - kphex r9, 8 /* decompressed kernel end */ - kputc #'>' - kphex r4, 8 /* kernel execution address */ - kputc #'\n' -#endif - .endm - - .macro debug_reloc_end -#ifdef DEBUG - kphex r5, 8 /* end of kernel */ - kputc #'\n' - mov r0, r4 - bl memdump /* dump 256 bytes at start of kernel */ -#endif - .endm - /* * Debug kernel copy by printing the memory addresses involved */ .macro dbgkc, begin, end, cbegin, cend #ifdef DEBUG - kputc #'\n' kputc #'C' kputc #':' kputc #'0' @@ -136,7 +110,28 @@ kputc #'x' kphex \cend, 8 /* End of kernel copy */ kputc #'\n' - kputc #'\r' +#endif + .endm + + /* + * Debug print of the final appended DTB location + */ + .macro dbgadtb, begin, end +#ifdef DEBUG + kputc #'D' + kputc #'T' + kputc #'B' + kputc #':' + kputc #'0' + kputc #'x' + kphex \begin, 8 /* Start of appended DTB */ + kputc #' ' + kputc #'(' + kputc #'0' + kputc #'x' + kphex \end, 8 /* End of appended DTB */ + kputc #')' + kputc #'\n' #endif .endm @@ -303,7 +298,7 @@ restart: adr r0, LC1 #ifndef CONFIG_ZBOOT_ROM /* malloc space is above the relocated stack (64k max) */ - add r10, sp, #0x10000 + add r10, sp, #MALLOC_SIZE #else /* * With ZBOOT_ROM the bss/stack is non relocatable, @@ -357,6 +352,7 @@ restart: adr r0, LC1 mov r5, r5, ror #8 eor r5, r5, r1, lsr #8 #endif + dbgadtb r6, r5 /* 50% DTB growth should be good enough */ add r5, r5, r5, lsr #1 /* preserve 64-bit alignment */ @@ -614,7 +610,7 @@ not_relocated: mov r0, #0 */ mov r0, r4 mov r1, sp @ malloc space above stack - add r2, sp, #0x10000 @ 64k max + add r2, sp, #MALLOC_SIZE @ 64k max mov r3, r7 bl decompress_kernel @@ -1356,7 +1352,7 @@ puts: loadsp r3, r2, r1 1: ldrb r2, [r0], #1 teq r2, #0 moveq pc, lr -2: writeb r2, r3 +2: writeb r2, r3, r1 mov r1, #0x00020000 3: subs r1, r1, #1 bne 3b @@ -1476,6 +1472,9 @@ ENTRY(efi_enter_kernel) @ issued from HYP mode take us to the correct handler code. We @ will disable the MMU before jumping to the kernel proper. @ + ARM( bic r1, r1, #(1 << 30) ) @ clear HSCTLR.TE + THUMB( orr r1, r1, #(1 << 30) ) @ set HSCTLR.TE + mcr p15, 4, r1, c1, c0, 0 adr r0, __hyp_reentry_vectors mcr p15, 4, r0, c12, c0, 0 @ set HYP vector base (HVBAR) isb diff --git a/arch/arm/boot/compressed/vmlinux.lds.S b/arch/arm/boot/compressed/vmlinux.lds.S index b914be3a207b..1bcb68ac4b01 100644 --- a/arch/arm/boot/compressed/vmlinux.lds.S +++ b/arch/arm/boot/compressed/vmlinux.lds.S @@ -44,10 +44,12 @@ SECTIONS } .table : ALIGN(4) { _table_start = .; - LONG(ZIMAGE_MAGIC(4)) + LONG(ZIMAGE_MAGIC(6)) LONG(ZIMAGE_MAGIC(0x5a534c4b)) LONG(ZIMAGE_MAGIC(__piggy_size_addr - _start)) LONG(ZIMAGE_MAGIC(_kernel_bss_size)) + LONG(ZIMAGE_MAGIC(TEXT_OFFSET)) + LONG(ZIMAGE_MAGIC(MALLOC_SIZE)) LONG(0) _table_end = .; } diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 4572db3fa5ae..ce66ffd5a1bb 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -43,6 +43,7 @@ dtb-$(CONFIG_SOC_AT91SAM9) += \ at91-smartkiz.dtb \ at91-wb45n.dtb \ at91sam9g15ek.dtb \ + at91sam9g25-gardena-smart-gateway.dtb \ at91sam9g25ek.dtb \ at91sam9g35ek.dtb \ at91sam9x25ek.dtb \ @@ -127,6 +128,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \ bcm47094-luxul-xwr-3150-v1.dtb \ bcm47094-netgear-r8500.dtb \ bcm47094-phicomm-k3.dtb \ + bcm53016-meraki-mr32.dtb \ bcm94708.dtb \ bcm94709.dtb \ bcm953012er.dtb \ @@ -357,6 +359,8 @@ dtb-$(CONFIG_ARCH_MPS2) += \ mps2-an399.dtb dtb-$(CONFIG_ARCH_MOXART) += \ moxart-uc7112lx.dtb +dtb-$(CONFIG_ARCH_SD5203) += \ + sd5203.dtb dtb-$(CONFIG_SOC_IMX1) += \ imx1-ads.dtb \ imx1-apf9328.dtb @@ -482,6 +486,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-wandboard-revd1.dtb \ imx6dl-yapp4-draco.dtb \ imx6dl-yapp4-hydra.dtb \ + imx6dl-yapp4-orion.dtb \ imx6dl-yapp4-ursa.dtb \ imx6q-apalis-eval.dtb \ imx6q-apalis-ixora.dtb \ @@ -531,6 +536,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6q-icore-ofcap12.dtb \ imx6q-icore-rqs.dtb \ imx6q-kp-tpc.dtb \ + imx6q-logicpd.dtb \ imx6q-marsboard.dtb \ imx6q-mccmon6.dtb \ imx6q-nitrogen6x.dtb \ @@ -585,6 +591,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6qp-zii-rdu2.dtb dtb-$(CONFIG_SOC_IMX6SL) += \ imx6sl-evk.dtb \ + imx6sl-tolino-shine2hd.dtb \ imx6sl-tolino-shine3.dtb \ imx6sl-warp.dtb dtb-$(CONFIG_SOC_IMX6SLL) += \ @@ -868,7 +875,12 @@ dtb-$(CONFIG_ARCH_ORION5X) += \ dtb-$(CONFIG_ARCH_ACTIONS) += \ owl-s500-cubieboard6.dtb \ owl-s500-guitar-bb-rev-b.dtb \ + owl-s500-labrador-base-m.dtb \ + owl-s500-roseapplepi.dtb \ owl-s500-sparky.dtb +dtb-$(CONFIG_ARCH_PICOXCELL) += \ + picoxcell-pc7302-pc3x2.dtb \ + picoxcell-pc7302-pc3x3.dtb dtb-$(CONFIG_ARCH_PRIMA2) += \ prima2-evb.dtb dtb-$(CONFIG_ARCH_PXA) += \ @@ -1047,6 +1059,7 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32746g-eval.dtb \ stm32h743i-eval.dtb \ stm32h743i-disco.dtb \ + stm32mp153c-dhcom-drc02.dtb \ stm32mp157a-avenger96.dtb \ stm32mp157a-dhcor-avenger96.dtb \ stm32mp157a-dk1.dtb \ @@ -1056,7 +1069,8 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32mp157c-dk2.dtb \ stm32mp157c-ed1.dtb \ stm32mp157c-ev1.dtb \ - stm32mp157c-lxa-mc1.dtb + stm32mp157c-lxa-mc1.dtb \ + stm32mp157c-odyssey.dtb dtb-$(CONFIG_MACH_SUN4I) += \ sun4i-a10-a1000.dtb \ sun4i-a10-ba10-tvbox.dtb \ @@ -1194,6 +1208,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-r16-parrot.dtb \ sun8i-r40-bananapi-m2-ultra.dtb \ sun8i-s3-lichee-zero-plus.dtb \ + sun8i-s3-pinecube.dtb \ sun8i-t3-cqa3t-bv3.dtb \ sun8i-v3s-licheepi-zero.dtb \ sun8i-v3s-licheepi-zero-dock.dtb \ @@ -1356,9 +1371,9 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt8135-evbp1.dtb dtb-$(CONFIG_ARCH_MILBEAUT) += milbeaut-m10v-evb.dtb dtb-$(CONFIG_ARCH_MSTARV7) += \ - infinity-msc313-breadbee_crust.dtb \ - infinity3-msc313e-breadbee.dtb \ - mercury5-ssc8336n-midrived08.dtb + mstar-infinity-msc313-breadbee_crust.dtb \ + mstar-infinity3-msc313e-breadbee.dtb \ + mstar-mercury5-ssc8336n-midrived08.dtb dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-ast2500-evb.dtb \ @@ -1371,6 +1386,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-bmc-facebook-tiogapass.dtb \ aspeed-bmc-facebook-wedge40.dtb \ aspeed-bmc-facebook-wedge100.dtb \ + aspeed-bmc-facebook-wedge400.dtb \ aspeed-bmc-facebook-yamp.dtb \ aspeed-bmc-facebook-yosemitev2.dtb \ aspeed-bmc-ibm-rainier.dtb \ @@ -1381,6 +1397,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-bmc-microsoft-olympus.dtb \ aspeed-bmc-opp-lanyang.dtb \ aspeed-bmc-opp-mihawk.dtb \ + aspeed-bmc-opp-mowgli.dtb \ aspeed-bmc-opp-nicole.dtb \ aspeed-bmc-opp-palmetto.dtb \ aspeed-bmc-opp-romulus.dtb \ diff --git a/arch/arm/boot/dts/alpine.dtsi b/arch/arm/boot/dts/alpine.dtsi index d3036ea823d1..3b0675a1c460 100644 --- a/arch/arm/boot/dts/alpine.dtsi +++ b/arch/arm/boot/dts/alpine.dtsi @@ -91,7 +91,7 @@ }; /* Interrupt Controller */ - gic: gic@fb001000 { + gic: interrupt-controller@fb001000 { compatible = "arm,cortex-a15-gic"; #interrupt-cells = <3>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/am335x-lxm.dts b/arch/arm/boot/dts/am335x-lxm.dts index cd55f11260ea..0f078465297a 100644 --- a/arch/arm/boot/dts/am335x-lxm.dts +++ b/arch/arm/boot/dts/am335x-lxm.dts @@ -160,11 +160,15 @@ serial_config1: serial_config1@20 { compatible = "nxp,pca9539"; reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; }; serial_config2: serial_config2@21 { compatible = "nxp,pca9539"; reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; }; tps: tps@2d { diff --git a/arch/arm/boot/dts/am335x-moxa-uc-8100-common.dtsi b/arch/arm/boot/dts/am335x-moxa-uc-8100-common.dtsi new file mode 100644 index 000000000000..98d8ed4ad967 --- /dev/null +++ b/arch/arm/boot/dts/am335x-moxa-uc-8100-common.dtsi @@ -0,0 +1,427 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2020 MOXA Inc. - https://www.moxa.com/ + * + * Author: Johnson Chen <johnsonch.chen@moxa.com> + */ + +#include "am33xx.dtsi" + +/ { + + cpus { + cpu@0 { + cpu0-supply = <&vdd1_reg>; + }; + }; + + vbat: vbat-regulator { + compatible = "regulator-fixed"; + }; + + /* Power supply provides a fixed 3.3V @3A */ + vmmcsd_fixed: vmmcsd-regulator { + compatible = "regulator-fixed"; + regulator-name = "vmmcsd_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + + buttons: push_button { + compatible = "gpio-keys"; + }; + +}; + +&am33xx_pinmux { + pinctrl-names = "default"; + pinctrl-0 = <&minipcie_pins>; + + minipcie_pins: pinmux_minipcie { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_pclk.gpio2_24 */ + AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_ac_bias_en.gpio2_25 */ + AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_vsync.gpio2_22 Power off PIN*/ + >; + }; + + push_button_pins: pinmux_push_button { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLDOWN, MUX_MODE7) /* mcasp0_ahcklx.gpio3_21 */ + >; + }; + + i2c0_pins: pinmux_i2c0_pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) + >; + }; + + + i2c1_pins: pinmux_i2c1_pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart0_ctsn.i2c1_sda */ + AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart0_rtsn.i2c1_scl */ + >; + }; + + uart0_pins: pinmux_uart0_pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + >; + }; + + uart1_pins: pinmux_uart1_pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT, MUX_MODE0) + >; + }; + + uart2_pins: pinmux_uart2_pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_INPUT, MUX_MODE6) /* lcd_data14.uart5_ctsn */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT_PULLDOWN, MUX_MODE6) /* lcd_data15.uart5_rtsn */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_INPUT_PULLUP, MUX_MODE4) /* lcd_data9.uart5_rxd */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE4) /* lcd_data8.uart5_txd */ + >; + }; + + cpsw_default: cpsw_default { + pinctrl-single,pins = < + /* Slave 1 */ + AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0) + + /* Slave 2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_crs_dv */ + AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rxer */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_txen */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_td1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_td0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rd1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rd0 */ + AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE1) /* rmii2_refclk */ + + >; + }; + + davinci_mdio_default: davinci_mdio_default { + pinctrl-single,pins = < + /* MDIO */ + AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) + >; + }; + + mmc0_pins_default: pinmux_mmc0_pins { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLUP, MUX_MODE7) /* mcasp0_aclkx.gpio3_14 */ + AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLUP, MUX_MODE7) /* mcasp0_aclkx.gpio3_18 */ + >; + }; + + mmc2_pins_default: pinmux_mmc2_pins { + pinctrl-single,pins = < + /* eMMC */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad12.mmc2_dat0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad13.mmc2_dat1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad14.mmc2_dat2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad15.mmc2_dat3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad8.mmc2_dat4 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad9.mmc2_dat5 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad10.mmc2_dat6 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad11.mmc2_dat7 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_csn3.mmc2_cmd */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_clk.mmc2_clk */ + >; + }; + + spi0_pins: pinmux_spi0 { + pinctrl-single,pins = < + AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0) + >; + }; + +}; + +&uart0 { + /* Console */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; +}; + +&uart1 { + /* UART 1 setting */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; +}; + +&uart5 { + /* UART 2 setting */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + + status = "okay"; + clock-frequency = <400000>; + + tps: tps@2d { + compatible = "ti,tps65910"; + reg = <0x2d>; + }; + + eeprom: eeprom@50 { + compatible = "atmel,24c16"; + pagesize = <16>; + reg = <0x50>; + }; + + rtc_wdt: rtc_wdt@68 { + compatible = "dallas,ds1374"; + reg = <0x68>; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + + status = "okay"; + clock-frequency = <400000>; + gpio_xten: gpio_xten@27 { + compatible = "nxp,pca9535"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x27>; + }; +}; + +&usb0 { + dr_mode = "host"; +}; + +&usb1 { + dr_mode = "host"; +}; + + +#include "tps65910.dtsi" +&tps { + vcc1-supply = <&vbat>; + vcc2-supply = <&vbat>; + vcc3-supply = <&vbat>; + vcc4-supply = <&vbat>; + vcc5-supply = <&vbat>; + vcc6-supply = <&vbat>; + vcc7-supply = <&vbat>; + vccio-supply = <&vbat>; + + regulators { + vrtc_reg: regulator@0 { + regulator-always-on; + }; + + vio_reg: regulator@1 { + regulator-always-on; + }; + + vdd1_reg: regulator@2 { + regulator-always-on; + }; + + vdd2_reg: regulator@3 { + regulator-always-on; + }; + + vdd3_reg: regulator@4 { + regulator-always-on; + }; + + vdig1_reg: regulator@5 { + regulator-always-on; + }; + + vdig2_reg: regulator@6 { + regulator-always-on; + }; + + vpll_reg: regulator@7 { + regulator-always-on; + }; + + vdac_reg: regulator@8 { + regulator-always-on; + }; + + vaux1_reg: regulator@9 { + regulator-always-on; + }; + + vaux2_reg: regulator@10 { + regulator-always-on; + }; + + vaux33_reg: regulator@11 { + regulator-always-on; + }; + + vmmc_reg: regulator@12 { + compatible = "regulator-fixed"; + regulator-name = "vmmc_reg"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; +}; + +/* Power */ +&vbat { + regulator-name = "vbat"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; +}; + +&mac { + pinctrl-names = "default"; + pinctrl-0 = <&cpsw_default>; + dual_emac = <1>; + status = "okay"; +}; + +&davinci_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&davinci_mdio_default>; + status = "okay"; + + ethphy0: ethernet-phy@4 { + reg = <4>; + }; + + ethphy1: ethernet-phy@5 { + reg = <5>; + }; +}; + +&cpsw_emac0 { + status = "okay"; + phy-handle = <ðphy0>; + phy-mode = "rmii"; + dual_emac_res_vlan = <1>; +}; + +&cpsw_emac1 { + status = "okay"; + phy-handle = <ðphy1>; + phy-mode = "rmii"; + dual_emac_res_vlan = <2>; +}; + +&sham { + status = "okay"; +}; + +&aes { + status = "okay"; +}; + +&gpio0 { + ti,no-reset-on-init; +}; + +&mmc1 { + pinctrl-names = "default"; + vmmc-supply = <&vmmcsd_fixed>; + bus-width = <4>; + pinctrl-0 = <&mmc0_pins_default>; + cd-gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; + wp-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&mmc3 { + dmas = <&edma_xbar 12 0 1 + &edma_xbar 13 0 2>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + vmmc-supply = <&vmmcsd_fixed>; + bus-width = <8>; + pinctrl-0 = <&mmc2_pins_default>; + ti,non-removable; + status = "okay"; +}; + +&buttons { + pinctrl-names = "default"; + pinctrl-0 = <&push_button_pins>; + #address-cells = <1>; + #size-cells = <0>; + + button@0 { + label = "push_button"; + linux,code = <0x100>; + gpios = <&gpio3 21 GPIO_ACTIVE_LOW>; + }; +}; + +/* SPI Busses */ +&spi0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; + + m25p80@0 { + compatible = "mx25l6405d"; + spi-max-frequency = <40000000>; + + reg = <0>; + spi-cpol; + spi-cpha; + #address-cells = <1>; + #size-cells = <1>; + + /* reg : The partition's offset and size within the mtd bank. */ + partitions@0 { + label = "MLO"; + reg = <0x0 0x80000>; + }; + + partitions@1 { + label = "U-Boot"; + reg = <0x80000 0x100000>; + }; + + partitions@2 { + label = "U-Boot Env"; + reg = <0x180000 0x20000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts b/arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts index f03e72cada41..0c7949d21bd9 100644 --- a/arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts +++ b/arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts @@ -4,39 +4,19 @@ * * Author: SZ Lin (林上智) <sz.lin@moxa.com> */ - /dts-v1/; -#include "am33xx.dtsi" +#include "am335x-moxa-uc-8100-common.dtsi" / { model = "Moxa UC-8100-ME-T"; compatible = "moxa,uc-8100-me-t", "ti,am33xx"; - cpus { - cpu@0 { - cpu0-supply = <&vdd1_reg>; - }; - }; - memory { device_type = "memory"; reg = <0x80000000 0x20000000>; /* 512 MB */ }; - vbat: vbat-regulator { - compatible = "regulator-fixed"; - }; - - /* Power supply provides a fixed 3.3V @3A */ - vmmcsd_fixed: vmmcsd-regulator { - compatible = "regulator-fixed"; - regulator-name = "vmmcsd_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - leds { compatible = "gpio-leds"; led1 { @@ -88,237 +68,17 @@ default-state = "off"; }; }; - - buttons: push_button { - compatible = "gpio-keys"; - }; - -}; - -&am33xx_pinmux { - pinctrl-names = "default"; - pinctrl-0 = <&minipcie_pins>; - - minipcie_pins: pinmux_minipcie { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_pclk.gpio2_24 */ - AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_ac_bias_en.gpio2_25 */ - AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_vsync.gpio2_22 Power off PIN*/ - >; - }; - - push_button_pins: pinmux_push_button { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLDOWN, MUX_MODE7) /* mcasp0_ahcklx.gpio3_21 */ - >; - }; - - i2c0_pins: pinmux_i2c0_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) - >; - }; - - - i2c1_pins: pinmux_i2c1_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart0_ctsn.i2c1_sda */ - AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart0_rtsn.i2c1_scl */ - >; - }; - - uart0_pins: pinmux_uart0_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - >; - }; - - uart1_pins: pinmux_uart1_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT, MUX_MODE0) - >; - }; - - uart2_pins: pinmux_uart2_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_INPUT, MUX_MODE6) /* lcd_data14.uart5_ctsn */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT_PULLDOWN, MUX_MODE6) /* lcd_data15.uart5_rtsn */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_INPUT_PULLUP, MUX_MODE4) /* lcd_data9.uart5_rxd */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE4) /* lcd_data8.uart5_txd */ - >; - }; - - cpsw_default: cpsw_default { - pinctrl-single,pins = < - /* Slave 1 */ - AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE1) - AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0) - - /* Slave 2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_crs_dv */ - AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rxer */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_txen */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_td1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_td0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rd1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rd0 */ - AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE1) /* rmii2_refclk */ - - >; - }; - - davinci_mdio_default: davinci_mdio_default { - pinctrl-single,pins = < - /* MDIO */ - AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) - >; - }; - - mmc0_pins_default: pinmux_mmc0_pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLUP, MUX_MODE7) /* mcasp0_aclkx.gpio3_14 */ - AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLUP, MUX_MODE7) /* mcasp0_aclkx.gpio3_18 */ - >; - }; - - mmc2_pins_default: pinmux_mmc2_pins { - pinctrl-single,pins = < - /* eMMC */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad12.mmc2_dat0 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad13.mmc2_dat1 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad14.mmc2_dat2 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad15.mmc2_dat3 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad8.mmc2_dat4 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad9.mmc2_dat5 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad10.mmc2_dat6 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad11.mmc2_dat7 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_csn3.mmc2_cmd */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_clk.mmc2_clk */ - >; - }; - - spi0_pins: pinmux_spi0 { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0) - >; - }; - -}; - -&uart0 { - /* Console */ - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; -}; - -&uart1 { - /* UART 1 setting */ - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; -}; - -&uart5 { - /* UART 2 setting */ - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; }; &i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - - status = "okay"; - clock-frequency = <400000>; - tpm: tpm@20 { compatible = "infineon,slb9645tt"; reg = <0x20>; }; - - tps: tps@2d { - compatible = "ti,tps65910"; - reg = <0x2d>; - }; - - eeprom: eeprom@50 { - compatible = "atmel,24c16"; - pagesize = <16>; - reg = <0x50>; - }; - - rtc_wdt: rtc_wdt@68 { - compatible = "dallas,ds1374"; - reg = <0x68>; - }; }; -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - - status = "okay"; - clock-frequency = <400000>; - gpio_xten: gpio_xten@27 { - compatible = "nxp,pca9535"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x27>; - }; -}; - -&usb0 { - dr_mode = "host"; -}; - -&usb1 { - dr_mode = "host"; -}; - -#include "tps65910.dtsi" - &tps { - vcc1-supply = <&vbat>; - vcc2-supply = <&vbat>; - vcc3-supply = <&vbat>; - vcc4-supply = <&vbat>; - vcc5-supply = <&vbat>; - vcc6-supply = <&vbat>; - vcc7-supply = <&vbat>; - vccio-supply = <&vbat>; - regulators { - vrtc_reg: regulator@0 { - regulator-always-on; - }; - - vio_reg: regulator@1 { - regulator-always-on; - }; - vdd1_reg: regulator@2 { /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ regulator-name = "vdd_mpu"; @@ -336,168 +96,6 @@ regulator-boot-on; regulator-always-on; }; - - vdd3_reg: regulator@4 { - regulator-always-on; - }; - - vdig1_reg: regulator@5 { - regulator-always-on; - }; - - vdig2_reg: regulator@6 { - regulator-always-on; - }; - - vpll_reg: regulator@7 { - regulator-always-on; - }; - - vdac_reg: regulator@8 { - regulator-always-on; - }; - - vaux1_reg: regulator@9 { - regulator-always-on; - }; - - vaux2_reg: regulator@10 { - regulator-always-on; - }; - - vaux33_reg: regulator@11 { - regulator-always-on; - }; - - vmmc_reg: regulator@12 { - compatible = "regulator-fixed"; - regulator-name = "vmmc_reg"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; -}; - -/* Power */ -&vbat { - regulator-name = "vbat"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; -}; - -&mac { - pinctrl-names = "default"; - pinctrl-0 = <&cpsw_default>; - dual_emac = <1>; - status = "okay"; -}; - -&davinci_mdio { - pinctrl-names = "default"; - pinctrl-0 = <&davinci_mdio_default>; - status = "okay"; - - ethphy0: ethernet-phy@4 { - reg = <4>; - }; - - ethphy1: ethernet-phy@5 { - reg = <5>; - }; -}; - -&cpsw_emac0 { - status = "okay"; - phy-handle = <ðphy0>; - phy-mode = "rmii"; - dual_emac_res_vlan = <1>; -}; - -&cpsw_emac1 { - status = "okay"; - phy-handle = <ðphy1>; - phy-mode = "rmii"; - dual_emac_res_vlan = <2>; -}; - -&sham { - status = "okay"; -}; - -&aes { - status = "okay"; -}; - -&gpio0 { - ti,no-reset-on-init; -}; - -&mmc1 { - pinctrl-names = "default"; - vmmc-supply = <&vmmcsd_fixed>; - bus-width = <4>; - pinctrl-0 = <&mmc0_pins_default>; - cd-gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; - wp-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&mmc3 { - dmas = <&edma_xbar 12 0 1 - &edma_xbar 13 0 2>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - vmmc-supply = <&vmmcsd_fixed>; - bus-width = <8>; - pinctrl-0 = <&mmc2_pins_default>; - non-removable; - status = "okay"; -}; - -&buttons { - pinctrl-names = "default"; - pinctrl-0 = <&push_button_pins>; - #address-cells = <1>; - #size-cells = <0>; - - button@0 { - label = "push_button"; - linux,code = <0x100>; - gpios = <&gpio3 21 GPIO_ACTIVE_LOW>; }; }; -/* SPI Busses */ -&spi0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins>; - - m25p80@0 { - compatible = "mx25l6405d"; - spi-max-frequency = <40000000>; - - reg = <0>; - spi-cpol; - spi-cpha; - #address-cells = <1>; - #size-cells = <1>; - - /* reg : The partition's offset and size within the mtd bank. */ - partitions@0 { - label = "MLO"; - reg = <0x0 0x80000>; - }; - - partitions@1 { - label = "U-Boot"; - reg = <0x80000 0x100000>; - }; - - partitions@2 { - label = "U-Boot Env"; - reg = <0x180000 0x20000>; - }; - }; -}; diff --git a/arch/arm/boot/dts/am335x-sbc-t335.dts b/arch/arm/boot/dts/am335x-sbc-t335.dts index a3f6bc4072d9..81e4453687ba 100644 --- a/arch/arm/boot/dts/am335x-sbc-t335.dts +++ b/arch/arm/boot/dts/am335x-sbc-t335.dts @@ -155,13 +155,13 @@ gpio-controller; #gpio-cells = <2>; reg = <0x26>; - dvi_ena { + dvi-ena-hog { gpio-hog; gpios = <13 GPIO_ACTIVE_HIGH>; output-high; line-name = "dvi-enable"; }; - lcd_ena { + lcd-ena-hog { gpio-hog; gpios = <11 GPIO_ACTIVE_HIGH>; output-high; diff --git a/arch/arm/boot/dts/am33xx-l4.dtsi b/arch/arm/boot/dts/am33xx-l4.dtsi index b88d0caa4b2d..ea20e4bdf040 100644 --- a/arch/arm/boot/dts/am33xx-l4.dtsi +++ b/arch/arm/boot/dts/am33xx-l4.dtsi @@ -425,7 +425,6 @@ target-module@3e000 { /* 0x44e3e000, ap 35 60.0 */ compatible = "ti,sysc-omap4-simple", "ti,sysc"; - ti,hwmods = "rtc"; reg = <0x3e074 0x4>, <0x3e078 0x4>; reg-names = "rev", "sysc"; diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 5cb4cc37cb6d..4c2298024137 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -172,7 +172,7 @@ * for the moment, just use a fake OCP bus entry to represent * the whole bus hierarchy. */ - ocp { + ocp: ocp { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -578,6 +578,7 @@ <SYSC_IDLE_SMART>; clocks = <&gfx_l3_clkctrl AM3_GFX_L3_GFX_CLKCTRL 0>; clock-names = "fck"; + power-domains = <&prm_gfx>; resets = <&prm_gfx 0>; reset-names = "rstctrl"; #address-cells = <1>; @@ -617,6 +618,7 @@ prm_gfx: prm@1100 { compatible = "ti,am3-prm-inst", "ti,omap-prm-inst"; reg = <0x1100 0x100>; + #power-domain-cells = <0>; #reset-cells = <1>; }; }; diff --git a/arch/arm/boot/dts/am3517-evm-ui.dtsi b/arch/arm/boot/dts/am3517-evm-ui.dtsi index 250c40da2535..7d8f32bf70db 100644 --- a/arch/arm/boot/dts/am3517-evm-ui.dtsi +++ b/arch/arm/boot/dts/am3517-evm-ui.dtsi @@ -183,14 +183,14 @@ }; &mcbsp1 { - status = "ok"; + status = "okay"; #sound-dai-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&mcbsp1_pins>; }; &mcbsp2 { - status = "ok"; + status = "okay"; #sound-dai-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&mcbsp2_pins>; diff --git a/arch/arm/boot/dts/am3517-evm.dts b/arch/arm/boot/dts/am3517-evm.dts index 04f20e7680b1..0d2fac98ce7d 100644 --- a/arch/arm/boot/dts/am3517-evm.dts +++ b/arch/arm/boot/dts/am3517-evm.dts @@ -176,7 +176,7 @@ }; &dss { - status = "ok"; + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&dss_dpi_pins>; diff --git a/arch/arm/boot/dts/am3874-iceboard.dts b/arch/arm/boot/dts/am3874-iceboard.dts index 1bb57019d082..9423e9feaa10 100644 --- a/arch/arm/boot/dts/am3874-iceboard.dts +++ b/arch/arm/boot/dts/am3874-iceboard.dts @@ -195,7 +195,7 @@ "FMCA_PG_C2M", "FMCA_PRSNT_M2C_L", "FMCA_CLK_DIR", "SFP_LOS", "FMCB_EN_12V0", "FMCB_EN_3V3", "FMCB_EN_VADJ", "FMCB_PG_M2C", "FMCB_PG_C2M", "FMCB_PRSNT_M2C_L", "FMCB_CLK_DIR", "SFP_ModPrsL"; - reset_gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; }; u42: pca9575@21 { @@ -208,7 +208,7 @@ "QSFPA_LPMode", "QSFPB_ModPrsL", "QSFPB_IntL", "QSFPB_ResetL", "SFP_TxFault", "SFP_TxDisable", "SFP_RS0", "SFP_RS1", "QSFPB_ModSelL", "QSFPB_LPMode", "SEL_SFP", "ARM_MR"; - reset_gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; }; u48: pca9575@22 { @@ -227,7 +227,7 @@ "GP_SW5", "GP_SW6", "GP_SW7", "GP_SW8", "GP_LED8", "GP_LED7", "GP_LED6", "GP_LED5", "GP_LED4", "GP_LED3", "GP_LED2", "GP_LED1"; - reset_gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; }; u59: pca9575@23 { @@ -240,7 +240,7 @@ "GTX1V8PowerFault", "PHYAPowerFault", "PHYBPowerFault", "ArmPowerFault", "BP_SLOW_GPIO0", "BP_SLOW_GPIO1", "BP_SLOW_GPIO2", "BP_SLOW_GPIO3", "BP_SLOW_GPIO4", "BP_SLOW_GPIO5", "__unused_u59_p16", "__unused_u59_p17"; - reset_gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; }; tmp100@48 { compatible = "ti,tmp100"; reg = <0x48>; }; diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index 14314046256c..878406b120be 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -35,8 +35,8 @@ serial3 = &uart3; serial4 = &uart4; serial5 = &uart5; - ethernet0 = &cpsw_emac0; - ethernet1 = &cpsw_emac1; + ethernet0 = &cpsw_port1; + ethernet1 = &cpsw_port2; spi0 = &qspi; }; @@ -517,6 +517,7 @@ <SYSC_IDLE_SMART>; clocks = <&gfx_l3_clkctrl AM4_GFX_L3_GFX_CLKCTRL 0>; clock-names = "fck"; + power-domains = <&prm_gfx>; resets = <&prm_gfx 0>; reset-names = "rstctrl"; #address-cells = <1>; @@ -533,6 +534,7 @@ prm_gfx: prm@400 { compatible = "ti,am4-prm-inst", "ti,omap-prm-inst"; reg = <0x400 0x100>; + #power-domain-cells = <0>; #reset-cells = <1>; }; diff --git a/arch/arm/boot/dts/am437x-cm-t43.dts b/arch/arm/boot/dts/am437x-cm-t43.dts index a6b4fca8626a..a83f46ed0c9a 100644 --- a/arch/arm/boot/dts/am437x-cm-t43.dts +++ b/arch/arm/boot/dts/am437x-cm-t43.dts @@ -325,17 +325,15 @@ }; }; -&mac { +&mac_sw { pinctrl-names = "default"; pinctrl-0 = <&cpsw_default>; - dual_emac = <1>; status = "okay"; }; -&davinci_mdio { +&davinci_mdio_sw { pinctrl-names = "default"; pinctrl-0 = <&davinci_mdio_default>; - status = "okay"; ethphy0: ethernet-phy@0 { reg = <0>; @@ -346,16 +344,16 @@ }; }; -&cpsw_emac0 { +&cpsw_port1 { phy-handle = <ðphy0>; phy-mode = "rgmii-txid"; - dual_emac_res_vlan = <1>; + ti,dual-emac-pvid = <1>; }; -&cpsw_emac1 { +&cpsw_port2 { phy-handle = <ðphy1>; phy-mode = "rgmii-txid"; - dual_emac_res_vlan = <2>; + ti,dual-emac-pvid = <2>; }; &dwc3_1 { diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts index b28e5c8cd02a..6e4d05d649e9 100644 --- a/arch/arm/boot/dts/am437x-gp-evm.dts +++ b/arch/arm/boot/dts/am437x-gp-evm.dts @@ -906,28 +906,31 @@ status = "okay"; }; -&mac { - slaves = <1>; +&mac_sw { pinctrl-names = "default", "sleep"; pinctrl-0 = <&cpsw_default>; pinctrl-1 = <&cpsw_sleep>; status = "okay"; }; -&davinci_mdio { +&davinci_mdio_sw { pinctrl-names = "default", "sleep"; pinctrl-0 = <&davinci_mdio_default>; pinctrl-1 = <&davinci_mdio_sleep>; - status = "okay"; ethphy0: ethernet-phy@0 { reg = <0>; }; }; -&cpsw_emac0 { +&cpsw_port1 { phy-handle = <ðphy0>; phy-mode = "rgmii-rxid"; + ti,dual-emac-pvid = <1>; +}; + +&cpsw_port2 { + status = "disabled"; }; &elm { @@ -1024,7 +1027,7 @@ }; &dss { - status = "ok"; + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&dss_pins>; diff --git a/arch/arm/boot/dts/am437x-idk-evm.dts b/arch/arm/boot/dts/am437x-idk-evm.dts index 8b986c45f09d..2dc525512266 100644 --- a/arch/arm/boot/dts/am437x-idk-evm.dts +++ b/arch/arm/boot/dts/am437x-idk-evm.dts @@ -483,28 +483,31 @@ }; }; -&mac { - slaves = <1>; +&mac_sw { pinctrl-names = "default", "sleep"; pinctrl-0 = <&cpsw_default>; pinctrl-1 = <&cpsw_sleep>; status = "okay"; }; -&davinci_mdio { +&davinci_mdio_sw { pinctrl-names = "default", "sleep"; pinctrl-0 = <&davinci_mdio_default>; pinctrl-1 = <&davinci_mdio_sleep>; - status = "okay"; ethphy0: ethernet-phy@0 { reg = <0>; }; }; -&cpsw_emac0 { +&cpsw_port1 { phy-handle = <ðphy0>; phy-mode = "rgmii-rxid"; + ti,dual-emac-pvid = <1>; +}; + +&cpsw_port2 { + status = "disabled"; }; &rtc { diff --git a/arch/arm/boot/dts/am437x-l4.dtsi b/arch/arm/boot/dts/am437x-l4.dtsi index 3d393fe252c6..c220dc3c4e0f 100644 --- a/arch/arm/boot/dts/am437x-l4.dtsi +++ b/arch/arm/boot/dts/am437x-l4.dtsi @@ -409,9 +409,8 @@ ranges = <0x0 0x39000 0x1000>; }; - target-module@3e000 { /* 0x44e3e000, ap 34 60.0 */ + rtc_target: target-module@3e000 { /* 0x44e3e000, ap 34 60.0 */ compatible = "ti,sysc-omap4-simple", "ti,sysc"; - ti,hwmods = "rtc"; reg = <0x3e074 0x4>, <0x3e078 0x4>; reg-names = "rev", "sysc"; @@ -521,54 +520,57 @@ #size-cells = <1>; ranges = <0x0 0x100000 0x8000>; - mac: ethernet@0 { - compatible = "ti,am4372-cpsw","ti,cpsw"; - reg = <0x0 0x800 - 0x1200 0x100>; + mac_sw: switch@0 { + compatible = "ti,am4372-cpsw","ti,cpsw-switch"; + reg = <0x0 0x4000>; + ranges = <0 0 0x4000>; + clocks = <&cpsw_125mhz_gclk>, <&dpll_clksel_mac_clk>; + clock-names = "fck", "50mclk"; + assigned-clocks = <&dpll_clksel_mac_clk>; + assigned-clock-rates = <50000000>; + #address-cells = <1>; + #size-cells = <1>; + syscon = <&scm_conf>; + status = "disabled"; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>, - <&dpll_clksel_mac_clk>; - clock-names = "fck", "cpts", "50mclk"; - assigned-clocks = <&dpll_clksel_mac_clk>; - assigned-clock-rates = <50000000>; - status = "disabled"; - cpdma_channels = <8>; - ale_entries = <1024>; - bd_ram_size = <0x2000>; - mac_control = <0x20>; - slaves = <2>; - active_slave = <0>; - cpts_clock_mult = <0x80000000>; - cpts_clock_shift = <29>; - ranges = <0 0 0x8000>; - syscon = <&scm_conf>; + interrupt-names = "rx_thresh", "rx", "tx", "misc"; - davinci_mdio: mdio@1000 { - compatible = "ti,am4372-mdio","ti,cpsw-mdio","ti,davinci_mdio"; - reg = <0x1000 0x100>; - clocks = <&cpsw_125mhz_clkctrl AM4_CPSW_125MHZ_CPGMAC0_CLKCTRL 0>; - clock-names = "fck"; + ethernet-ports { #address-cells = <1>; #size-cells = <0>; - bus_freq = <1000000>; - status = "disabled"; + + cpsw_port1: port@1 { + reg = <1>; + label = "port1"; + mac-address = [ 00 00 00 00 00 00 ]; + phys = <&phy_gmii_sel 1 0>; + }; + + cpsw_port2: port@2 { + reg = <2>; + label = "port2"; + mac-address = [ 00 00 00 00 00 00 ]; + phys = <&phy_gmii_sel 2 0>; + }; }; - cpsw_emac0: slave@200 { - /* Filled in by U-Boot */ - mac-address = [ 00 00 00 00 00 00 ]; - phys = <&phy_gmii_sel 1 0>; + davinci_mdio_sw: mdio@1000 { + compatible = "ti,am4372-mdio", "ti,cpsw-mdio","ti,davinci_mdio"; + clocks = <&cpsw_125mhz_gclk>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <0>; + bus_freq = <1000000>; + reg = <0x1000 0x100>; }; - cpsw_emac1: slave@300 { - /* Filled in by U-Boot */ - mac-address = [ 00 00 00 00 00 00 ]; - phys = <&phy_gmii_sel 2 0>; + cpts { + clocks = <&cpsw_cpts_rft_clk>; + clock-names = "cpts"; }; }; }; diff --git a/arch/arm/boot/dts/am437x-sbc-t43.dts b/arch/arm/boot/dts/am437x-sbc-t43.dts index 94cf07ea27f7..8ea3780f939d 100644 --- a/arch/arm/boot/dts/am437x-sbc-t43.dts +++ b/arch/arm/boot/dts/am437x-sbc-t43.dts @@ -136,7 +136,7 @@ }; &dss { - status = "ok"; + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&dss_pinctrl_default>; diff --git a/arch/arm/boot/dts/am437x-sk-evm.dts b/arch/arm/boot/dts/am437x-sk-evm.dts index 5fffdce853b1..496ed34f7755 100644 --- a/arch/arm/boot/dts/am437x-sk-evm.dts +++ b/arch/arm/boot/dts/am437x-sk-evm.dts @@ -792,19 +792,17 @@ }; }; -&mac { +&mac_sw { pinctrl-names = "default", "sleep"; pinctrl-0 = <&cpsw_default>; pinctrl-1 = <&cpsw_sleep>; - dual_emac = <1>; status = "okay"; }; -&davinci_mdio { +&davinci_mdio_sw { pinctrl-names = "default", "sleep"; pinctrl-0 = <&davinci_mdio_default>; pinctrl-1 = <&davinci_mdio_sleep>; - status = "okay"; ethphy0: ethernet-phy@4 { reg = <4>; @@ -815,16 +813,16 @@ }; }; -&cpsw_emac0 { +&cpsw_port1 { phy-handle = <ðphy0>; phy-mode = "rgmii-rxid"; - dual_emac_res_vlan = <1>; + ti,dual-emac-pvid = <1>; }; -&cpsw_emac1 { +&cpsw_port2 { phy-handle = <ðphy1>; phy-mode = "rgmii-rxid"; - dual_emac_res_vlan = <2>; + ti,dual-emac-pvid = <2>; }; &elm { diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts index de4fc78498a0..f517d1e843cf 100644 --- a/arch/arm/boot/dts/am43x-epos-evm.dts +++ b/arch/arm/boot/dts/am43x-epos-evm.dts @@ -550,29 +550,32 @@ cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; }; -&mac { +&mac_sw { pinctrl-names = "default", "sleep"; pinctrl-0 = <&cpsw_default>; pinctrl-1 = <&cpsw_sleep>; status = "okay"; - slaves = <1>; }; -&davinci_mdio { +&davinci_mdio_sw { pinctrl-names = "default", "sleep"; pinctrl-0 = <&davinci_mdio_default>; pinctrl-1 = <&davinci_mdio_sleep>; - status = "okay"; ethphy0: ethernet-phy@16 { reg = <16>; }; }; -&cpsw_emac0 { +&cpsw_port1 { phy-handle = <ðphy0>; phy-mode = "rmii"; phys = <&phy_gmii_sel 1 1>; + ti,dual-emac-pvid = <1>; +}; + +&cpsw_port2 { + status = "disabled"; }; &i2c0 { @@ -833,6 +836,10 @@ status = "okay"; }; +&rtc_target { + status = "disabled"; +}; + &tscadc { status = "okay"; @@ -948,7 +955,7 @@ }; &dss { - status = "ok"; + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&dss_pins>; diff --git a/arch/arm/boot/dts/am571x-idk.dts b/arch/arm/boot/dts/am571x-idk.dts index 391a92e24472..e81078c2d00d 100644 --- a/arch/arm/boot/dts/am571x-idk.dts +++ b/arch/arm/boot/dts/am571x-idk.dts @@ -208,30 +208,3 @@ pinctrl-1 = <&mmc2_pins_hs>; pinctrl-2 = <&mmc2_pins_ddr_rev20 &mmc2_iodelay_ddr_conf>; }; - -&mac_sw { - pinctrl-names = "default", "sleep"; - status = "okay"; -}; - -&cpsw_port1 { - phy-handle = <ðphy0_sw>; - phy-mode = "rgmii-rxid"; - ti,dual-emac-pvid = <1>; -}; - -&cpsw_port2 { - phy-handle = <ðphy1_sw>; - phy-mode = "rgmii-rxid"; - ti,dual-emac-pvid = <2>; -}; - -&davinci_mdio_sw { - ethphy0_sw: ethernet-phy@0 { - reg = <0>; - }; - - ethphy1_sw: ethernet-phy@1 { - reg = <1>; - }; -}; diff --git a/arch/arm/boot/dts/am5729-beagleboneai.dts b/arch/arm/boot/dts/am5729-beagleboneai.dts index e9c7f44126e7..149cfafb90bf 100644 --- a/arch/arm/boot/dts/am5729-beagleboneai.dts +++ b/arch/arm/boot/dts/am5729-beagleboneai.dts @@ -488,25 +488,29 @@ status = "okay"; }; -&davinci_mdio { +&davinci_mdio_sw { reset-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; reset-delay-us = <2>; - phy0: ethernet-phy@1 { + phy0: ethernet-phy@4 { reg = <4>; eee-broken-100tx; eee-broken-1000t; }; }; -&mac { - slaves = <1>; +&mac_sw { status = "okay"; }; -&cpsw_emac0 { +&cpsw_port1 { phy-handle = <&phy0>; phy-mode = "rgmii-rxid"; + ti,dual-emac-pvid = <1>; +}; + +&cpsw_port2 { + status = "disabled"; }; &ocp { diff --git a/arch/arm/boot/dts/am572x-idk.dts b/arch/arm/boot/dts/am572x-idk.dts index 1a3af4b54308..6504265f3f7e 100644 --- a/arch/arm/boot/dts/am572x-idk.dts +++ b/arch/arm/boot/dts/am572x-idk.dts @@ -27,8 +27,3 @@ pinctrl-1 = <&mmc2_pins_hs>; pinctrl-2 = <&mmc2_pins_ddr_rev20>; }; - -&mac { - status = "okay"; - dual_emac; -}; diff --git a/arch/arm/boot/dts/am574x-idk.dts b/arch/arm/boot/dts/am574x-idk.dts index c9275d0c62cf..37758761cd88 100644 --- a/arch/arm/boot/dts/am574x-idk.dts +++ b/arch/arm/boot/dts/am574x-idk.dts @@ -36,11 +36,6 @@ pinctrl-2 = <&mmc2_pins_default>; }; -&mac { - status = "okay"; - dual_emac; -}; - &m_can0 { status = "disabled"; }; diff --git a/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi b/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi index b3a0206ebd6c..6b82ecf803c5 100644 --- a/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi +++ b/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi @@ -451,7 +451,7 @@ <&dra7_pmx_core 0x3f8>; }; -&davinci_mdio { +&davinci_mdio_sw { phy0: ethernet-phy@1 { reg = <1>; }; @@ -461,21 +461,20 @@ }; }; -&mac { +&mac_sw { status = "okay"; - dual_emac; }; -&cpsw_emac0 { +&cpsw_port1 { phy-handle = <&phy0>; phy-mode = "rgmii-rxid"; - dual_emac_res_vlan = <1>; + ti,dual-emac-pvid = <1>; }; -&cpsw_emac1 { +&cpsw_port2 { phy-handle = <&phy1>; phy-mode = "rgmii-rxid"; - dual_emac_res_vlan = <2>; + ti,dual-emac-pvid = <2>; }; &mmc1 { @@ -582,13 +581,13 @@ }; &dss { - status = "ok"; + status = "okay"; vdda_video-supply = <&ldoln_reg>; }; &hdmi { - status = "ok"; + status = "okay"; vdda-supply = <&ldo4_reg>; port { @@ -599,7 +598,7 @@ }; &pcie1_rc { - status = "ok"; + status = "okay"; gpios = <&gpio2 8 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/boot/dts/am57xx-cl-som-am57x.dts b/arch/arm/boot/dts/am57xx-cl-som-am57x.dts index 34ca761aeded..0d5fe2bfb683 100644 --- a/arch/arm/boot/dts/am57xx-cl-som-am57x.dts +++ b/arch/arm/boot/dts/am57xx-cl-som-am57x.dts @@ -546,27 +546,26 @@ }; }; -&mac { +&mac_sw { status = "okay"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&cpsw_pins_default>; pinctrl-1 = <&cpsw_pins_sleep>; - dual_emac; }; -&cpsw_emac0 { +&cpsw_port1 { phy-handle = <ðphy0>; phy-mode = "rgmii-txid"; - dual_emac_res_vlan = <0>; + ti,dual-emac-pvid = <1>; }; -&cpsw_emac1 { +&cpsw_port2 { phy-handle = <ðphy1>; phy-mode = "rgmii-txid"; - dual_emac_res_vlan = <1>; + ti,dual-emac-pvid = <2>; }; -&davinci_mdio { +&davinci_mdio_sw { pinctrl-names = "default", "sleep"; pinctrl-0 = <&davinci_mdio_pins_default>; pinctrl-1 = <&davinci_mdio_pins_sleep>; diff --git a/arch/arm/boot/dts/am57xx-idk-common.dtsi b/arch/arm/boot/dts/am57xx-idk-common.dtsi index 1c77006cccd1..9fcb8944aa3e 100644 --- a/arch/arm/boot/dts/am57xx-idk-common.dtsi +++ b/arch/arm/boot/dts/am57xx-idk-common.dtsi @@ -448,19 +448,23 @@ ext-clk-src; }; -&cpsw_emac0 { +&mac_sw { + status = "okay"; +}; + +&cpsw_port1 { phy-handle = <ðphy0>; phy-mode = "rgmii-rxid"; - dual_emac_res_vlan = <1>; + ti,dual-emac-pvid = <1>; }; -&cpsw_emac1 { +&cpsw_port2 { phy-handle = <ðphy1>; phy-mode = "rgmii-rxid"; - dual_emac_res_vlan = <2>; + ti,dual-emac-pvid = <2>; }; -&davinci_mdio { +&davinci_mdio_sw { ethphy0: ethernet-phy@0 { reg = <0>; }; diff --git a/arch/arm/boot/dts/am57xx-sbc-am57x.dts b/arch/arm/boot/dts/am57xx-sbc-am57x.dts index ce5bf1d92eab..beef63e8a005 100644 --- a/arch/arm/boot/dts/am57xx-sbc-am57x.dts +++ b/arch/arm/boot/dts/am57xx-sbc-am57x.dts @@ -120,7 +120,7 @@ }; &dss { - status = "ok"; + status = "okay"; vdda_video-supply = <&ldoln_reg>; @@ -148,7 +148,7 @@ }; &hdmi { - status = "ok"; + status = "okay"; vdda-supply = <&ldo4_reg>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/animeo_ip.dts b/arch/arm/boot/dts/animeo_ip.dts index c36d28c295d6..7da718abbd85 100644 --- a/arch/arm/boot/dts/animeo_ip.dts +++ b/arch/arm/boot/dts/animeo_ip.dts @@ -26,7 +26,7 @@ stdout-path = &usart2; }; - memory { + memory@20000000 { reg = <0x20000000 0x4000000>; }; @@ -81,6 +81,7 @@ pinctrl-0 = <&pinctrl_mmc0_clk &pinctrl_mmc0_slot1_cmd_dat0 &pinctrl_mmc0_slot1_dat1_3>; + pinctrl-names = "default"; status = "okay"; slot@1 { diff --git a/arch/arm/boot/dts/arm-realview-eb.dtsi b/arch/arm/boot/dts/arm-realview-eb.dtsi index fe0207b88053..a534a8e444d9 100644 --- a/arch/arm/boot/dts/arm-realview-eb.dtsi +++ b/arch/arm/boot/dts/arm-realview-eb.dtsi @@ -390,7 +390,7 @@ compatible = "arm,sp805", "arm,primecell"; reg = <0x10010000 0x1000>; clocks = <&wdogclk>, <&pclk>; - clock-names = "wdogclk", "apb_pclk"; + clock-names = "wdog_clk", "apb_pclk"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/arm-realview-pb11mp.dts b/arch/arm/boot/dts/arm-realview-pb11mp.dts index 9748e0fe800f..0c7dabef4a5f 100644 --- a/arch/arm/boot/dts/arm-realview-pb11mp.dts +++ b/arch/arm/boot/dts/arm-realview-pb11mp.dts @@ -546,7 +546,7 @@ interrupt-parent = <&intc_pb11mp>; interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; clocks = <&wdogclk>, <&pclk>; - clock-names = "wdogclk", "apb_pclk"; + clock-names = "wdog_clk", "apb_pclk"; status = "disabled"; }; @@ -556,7 +556,7 @@ interrupt-parent = <&intc_pb11mp>; interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; clocks = <&wdogclk>, <&pclk>; - clock-names = "wdogclk", "apb_pclk"; + clock-names = "wdog_clk", "apb_pclk"; }; timer01: timer@10011000 { @@ -568,8 +568,8 @@ clocks = <&sp810_syscon 0>, <&sp810_syscon 1>, <&pclk>; - clock-names = "timerclk0", - "timerclk1", + clock-names = "timer0clk", + "timer1clk", "apb_pclk"; }; @@ -582,8 +582,8 @@ clocks = <&sp810_syscon 2>, <&sp810_syscon 3>, <&pclk>; - clock-names = "timerclk2", - "timerclk3", + clock-names = "timer0clk", + "timer1clk", "apb_pclk"; }; @@ -645,16 +645,16 @@ timer45: timer@10018000 { compatible = "arm,sp804", "arm,primecell"; reg = <0x10018000 0x1000>; - clocks = <&timclk>, <&pclk>; - clock-names = "timer", "apb_pclk"; + clocks = <&timclk>, <&timclk>, <&pclk>; + clock-names = "timer0clk", "timer1clk", "apb_pclk"; status = "disabled"; }; timer67: timer@10019000 { compatible = "arm,sp804", "arm,primecell"; reg = <0x10019000 0x1000>; - clocks = <&timclk>, <&pclk>; - clock-names = "timer", "apb_pclk"; + clocks = <&timclk>, <&timclk>, <&pclk>; + clock-names = "timer0clk", "timer1clk", "apb_pclk"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/arm-realview-pbx.dtsi b/arch/arm/boot/dts/arm-realview-pbx.dtsi index f61bd59ae5ba..ac95667ed781 100644 --- a/arch/arm/boot/dts/arm-realview-pbx.dtsi +++ b/arch/arm/boot/dts/arm-realview-pbx.dtsi @@ -381,7 +381,7 @@ compatible = "arm,sp805", "arm,primecell"; reg = <0x1000f000 0x1000>; clocks = <&wdogclk>, <&pclk>; - clock-names = "wdogclk", "apb_pclk"; + clock-names = "wdog_clk", "apb_pclk"; status = "disabled"; }; @@ -389,7 +389,7 @@ compatible = "arm,sp805", "arm,primecell"; reg = <0x10010000 0x1000>; clocks = <&wdogclk>, <&pclk>; - clock-names = "wdogclk", "apb_pclk"; + clock-names = "wdog_clk", "apb_pclk"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-cmm.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-cmm.dts index 7bc7df7ed428..2fb8b147f489 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-cmm.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-cmm.dts @@ -1571,3 +1571,20 @@ &sdhci1 { status = "disabled"; }; + +&fmc_flash0 { +#include "facebook-bmc-flash-layout.dtsi" +}; + +&fmc_flash1 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + flash1@0 { + reg = <0x0 0x2000000>; + label = "flash1"; + }; + }; +}; diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-minipack.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-minipack.dts index 88ce4ff9f47e..c34741dbd268 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-minipack.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-minipack.dts @@ -88,17 +88,60 @@ */ &fmc_flash0 { partitions { - data0@1c00000 { - reg = <0x1c00000 0x2400000>; + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* + * u-boot partition: 384KB. + */ + u-boot@0 { + reg = <0x0 0x60000>; + label = "u-boot"; }; + + /* + * u-boot environment variables: 128KB. + */ + u-boot-env@60000 { + reg = <0x60000 0x20000>; + label = "env"; + }; + + /* + * FIT image: 59.5 MB. + */ + fit@80000 { + reg = <0x80000 0x3b80000>; + label = "fit"; + }; + + /* + * "data0" partition (4MB) is reserved for persistent + * data store. + */ + data0@3800000 { + reg = <0x3c00000 0x400000>; + label = "data0"; + }; + + /* + * "flash0" partition (covering the entire flash) is + * explicitly created to avoid breaking legacy applications. + */ flash0@0 { reg = <0x0 0x4000000>; + label = "flash0"; }; }; }; &fmc_flash1 { partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + flash1@0 { reg = <0x0 0x4000000>; }; diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-wedge40.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-wedge40.dts index 8ac23ff6b09e..8c426ba2f8ab 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-wedge40.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-wedge40.dts @@ -48,7 +48,7 @@ flash@0 { status = "okay"; m25p,fast-read; - label = "fmc0"; + label = "spi0.0"; #include "facebook-bmc-flash-layout.dtsi" }; }; @@ -71,7 +71,8 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_txd4_default - &pinctrl_rxd4_default>; + &pinctrl_rxd4_default + &pinctrl_ndts4_default>; }; &uart5 { diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-wedge400.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-wedge400.dts new file mode 100644 index 000000000000..ad1fcad3676c --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-wedge400.dts @@ -0,0 +1,420 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (c) 2019 Facebook Inc. +/dts-v1/; + +#include <dt-bindings/gpio/aspeed-gpio.h> +#include "ast2500-facebook-netbmc-common.dtsi" + +/ { + model = "Facebook Wedge 400 BMC"; + compatible = "facebook,wedge400-bmc", "aspeed,ast2500"; + + aliases { + /* + * PCA9548 (2-0070) provides 8 channels connecting to + * SCM (System Controller Module). + */ + i2c16 = &imux16; + i2c17 = &imux17; + i2c18 = &imux18; + i2c19 = &imux19; + i2c20 = &imux20; + i2c21 = &imux21; + i2c22 = &imux22; + i2c23 = &imux23; + + /* + * PCA9548 (8-0070) provides 8 channels connecting to + * SMB (Switch Main Board). + */ + i2c24 = &imux24; + i2c25 = &imux25; + i2c26 = &imux26; + i2c27 = &imux27; + i2c28 = &imux28; + i2c29 = &imux29; + i2c30 = &imux30; + i2c31 = &imux31; + + /* + * PCA9548 (11-0076) provides 8 channels connecting to + * FCM (Fan Controller Module). + */ + i2c32 = &imux32; + i2c33 = &imux33; + i2c34 = &imux34; + i2c35 = &imux35; + i2c36 = &imux36; + i2c37 = &imux37; + i2c38 = &imux38; + i2c39 = &imux39; + + spi2 = &spi_gpio; + }; + + chosen { + stdout-path = &uart1; + bootargs = "console=ttyS0,9600n8 root=/dev/ram rw"; + }; + + ast-adc-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, <&adc 4>; + }; + + /* + * GPIO-based SPI Master is required to access SPI TPM, because + * full-duplex SPI transactions are not supported by ASPEED SPI + * Controllers. + */ + spi_gpio: spi-gpio { + status = "okay"; + compatible = "spi-gpio"; + #address-cells = <1>; + #size-cells = <0>; + + cs-gpios = <&gpio ASPEED_GPIO(R, 2) GPIO_ACTIVE_LOW>; + gpio-sck = <&gpio ASPEED_GPIO(R, 3) GPIO_ACTIVE_HIGH>; + gpio-mosi = <&gpio ASPEED_GPIO(R, 4) GPIO_ACTIVE_HIGH>; + gpio-miso = <&gpio ASPEED_GPIO(R, 5) GPIO_ACTIVE_HIGH>; + num-chipselects = <1>; + + tpmdev@0 { + compatible = "tcg,tpm_tis-spi"; + spi-max-frequency = <33000000>; + reg = <0>; + }; + }; +}; + +/* + * Both firmware flashes are 128MB on Wedge400 BMC. + */ +&fmc_flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* + * u-boot partition: 384KB. + */ + u-boot@0 { + reg = <0x0 0x60000>; + label = "u-boot"; + }; + + /* + * u-boot environment variables: 128KB. + */ + u-boot-env@60000 { + reg = <0x60000 0x20000>; + label = "env"; + }; + + /* + * FIT image: 123.5 MB. + */ + fit@80000 { + reg = <0x80000 0x7b80000>; + label = "fit"; + }; + + /* + * "data0" partition (4MB) is reserved for persistent + * data store. + */ + data0@3800000 { + reg = <0x7c00000 0x800000>; + label = "data0"; + }; + + /* + * "flash0" partition (covering the entire flash) is + * explicitly created to avoid breaking legacy applications. + */ + flash0@0 { + reg = <0x0 0x8000000>; + label = "flash0"; + }; + }; +}; + +&fmc_flash1 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + flash1@0 { + reg = <0x0 0x8000000>; + label = "flash1"; + }; + }; +}; + +&uart2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd2_default + &pinctrl_rxd2_default>; +}; + +&uart4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd4_default + &pinctrl_rxd4_default>; +}; + +/* + * I2C bus #0 is multi-master environment dedicated for BMC and Bridge IC + * communication. + */ +&i2c0 { + status = "okay"; + multi-master; + bus-frequency = <1000000>; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; + + i2c-switch@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + i2c-mux-idle-disconnect; + + imux16: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux17: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux18: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux19: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux20: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux21: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux22: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux23: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; +}; + +&i2c7 { + status = "okay"; +}; + +&i2c8 { + status = "okay"; + + i2c-switch@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + i2c-mux-idle-disconnect; + + imux24: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux25: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux26: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux27: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux28: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux29: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux30: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux31: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + + }; +}; + +&i2c9 { + status = "okay"; +}; + +&i2c10 { + status = "okay"; +}; + +&i2c11 { + status = "okay"; + + i2c-switch@76 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x76>; + i2c-mux-idle-disconnect; + + imux32: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux33: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux34: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux35: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux36: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux37: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux38: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux39: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + + }; +}; + +&i2c12 { + status = "okay"; +}; + +&i2c13 { + status = "okay"; +}; + +&adc { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&uhci { + status = "okay"; +}; + +&sdhci1 { + /* + * DMA mode needs to be disabled to avoid conflicts with UHCI + * Controller in AST2500 SoC. + */ + sdhci-caps-mask = <0x0 0x580000>; +}; diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-yamp.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-yamp.dts index fe2e11c2da15..5e6105874217 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-yamp.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-yamp.dts @@ -108,3 +108,20 @@ &i2c13 { status = "okay"; }; + +&fmc_flash0 { +#include "facebook-bmc-flash-layout.dtsi" +}; + +&fmc_flash1 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + flash1@0 { + reg = <0x0 0x2000000>; + label = "flash1"; + }; + }; +}; diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts index b94421f6cbd5..21ae880c7530 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts @@ -4,6 +4,7 @@ #include "aspeed-g6.dtsi" #include <dt-bindings/gpio/aspeed-gpio.h> +#include <dt-bindings/i2c/i2c.h> #include <dt-bindings/leds/leds-pca955x.h> / { @@ -52,9 +53,10 @@ }; vga_memory: region@bf000000 { - no-map; - reg = <0xbf000000 0x01000000>; /* 16M */ - }; + no-map; + compatible = "shared-dma-pool"; + reg = <0xbf000000 0x01000000>; /* 16M */ + }; }; gpio-keys { @@ -178,6 +180,10 @@ status = "okay"; }; +&pinctrl_emmc_default { + bias-disable; +}; + &emmc { status = "okay"; }; @@ -698,6 +704,7 @@ }; &i2c7 { + multi-master; status = "okay"; si7021-a20@20 { @@ -831,6 +838,11 @@ }; }; + ibm-panel@62 { + compatible = "ibm,op-panel"; + reg = <(0x62 | I2C_OWN_SLAVE_ADDRESS)>; + }; + dps: dps310@76 { compatible = "infineon,dps310"; reg = <0x76>; @@ -1121,3 +1133,8 @@ spi-max-frequency = <100000000>; }; }; + +&xdma { + status = "okay"; + memory-region = <&vga_memory>; +}; diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-mowgli.dts b/arch/arm/boot/dts/aspeed-bmc-opp-mowgli.dts new file mode 100644 index 000000000000..b648e468e9db --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-opp-mowgli.dts @@ -0,0 +1,662 @@ +// SPDX-License-Identifier: GPL-2.0+ +/dts-v1/; +#include "aspeed-g5.dtsi" +#include <dt-bindings/gpio/aspeed-gpio.h> +#include <dt-bindings/leds/leds-pca955x.h> + +/ { + model = "Mowgli BMC"; + compatible = "ibm,mowgli-bmc", "aspeed,ast2500"; + + + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS4,115200 earlyprintk"; + }; + + memory@80000000 { + reg = <0x80000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + flash_memory: region@98000000 { + no-map; + reg = <0x98000000 0x04000000>; /* 64M */ + }; + + gfx_memory: framebuffer { + size = <0x01000000>; + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + + video_engine_memory: jpegbuffer { + size = <0x02000000>; + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + air-water { + label = "air-water"; + gpios = <&gpio ASPEED_GPIO(F, 6) GPIO_ACTIVE_LOW>; + linux,code = <ASPEED_GPIO(F, 6)>; + }; + + checkstop { + label = "checkstop"; + gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>; + linux,code = <ASPEED_GPIO(J, 2)>; + }; + + ps0-presence { + label = "ps0-presence"; + gpios = <&gpio ASPEED_GPIO(Z, 2) GPIO_ACTIVE_LOW>; + linux,code = <ASPEED_GPIO(Z, 2)>; + }; + + ps1-presence { + label = "ps1-presence"; + gpios = <&gpio ASPEED_GPIO(Z, 0) GPIO_ACTIVE_LOW>; + linux,code = <ASPEED_GPIO(Z, 0)>; + }; + + id-button { + label = "id-button"; + gpios = <&gpio ASPEED_GPIO(F, 1) GPIO_ACTIVE_LOW>; + linux,code = <ASPEED_GPIO(F, 1)>; + }; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + poll-interval = <1000>; + + fan0-presence { + label = "fan0-presence"; + gpios = <&pca9552 9 GPIO_ACTIVE_LOW>; + linux,code = <9>; + }; + + fan1-presence { + label = "fan1-presence"; + gpios = <&pca9552 10 GPIO_ACTIVE_LOW>; + linux,code = <10>; + }; + + fan2-presence { + label = "fan2-presence"; + gpios = <&pca9552 11 GPIO_ACTIVE_LOW>; + linux,code = <11>; + }; + + fan3-presence { + label = "fan3-presence"; + gpios = <&pca9552 12 GPIO_ACTIVE_LOW>; + linux,code = <12>; + }; + + fan4-presence { + label = "fan4-presence"; + gpios = <&pca9552 13 GPIO_ACTIVE_LOW>; + linux,code = <13>; + }; + }; + + leds { + compatible = "gpio-leds"; + + front-fault { + retain-state-shutdown; + default-state = "keep"; + gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_LOW>; + }; + + power-button { + retain-state-shutdown; + default-state = "keep"; + gpios = <&gpio ASPEED_GPIO(AA, 1) GPIO_ACTIVE_LOW>; + }; + + front-id { + retain-state-shutdown; + default-state = "keep"; + gpios = <&gpio ASPEED_GPIO(AA, 2) GPIO_ACTIVE_LOW>; + }; + + fan0 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca9552 0 GPIO_ACTIVE_LOW>; + }; + + fan1 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca9552 1 GPIO_ACTIVE_LOW>; + }; + + fan2 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca9552 2 GPIO_ACTIVE_LOW>; + }; + + fan3 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca9552 3 GPIO_ACTIVE_LOW>; + }; + + fan4 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca9552 4 GPIO_ACTIVE_LOW>; + }; + }; + + fsi: gpio-fsi { + compatible = "fsi-master-gpio", "fsi-master"; + #address-cells = <2>; + #size-cells = <0>; + no-gpio-delays; + + clock-gpios = <&gpio ASPEED_GPIO(E, 6) GPIO_ACTIVE_HIGH>; + data-gpios = <&gpio ASPEED_GPIO(E, 7) GPIO_ACTIVE_HIGH>; + mux-gpios = <&gpio ASPEED_GPIO(R, 2) GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>; + trans-gpios = <&gpio ASPEED_GPIO(E, 5) GPIO_ACTIVE_HIGH>; + }; + + iio-hwmon-12v { + compatible = "iio-hwmon"; + io-channels = <&adc 0>; + }; + + iio-hwmon-5v { + compatible = "iio-hwmon"; + io-channels = <&adc 1>; + }; + + iio-hwmon-3v { + compatible = "iio-hwmon"; + io-channels = <&adc 2>; + }; + + iio-hwmon-vdd { + compatible = "iio-hwmon"; + io-channels = <&adc 3>; + }; + + iio-hwmon-vcs { + compatible = "iio-hwmon"; + io-channels = <&adc 5>; + }; + + iio-hwmon-vdn { + compatible = "iio-hwmon"; + io-channels = <&adc 7>; + }; + + iio-hwmon-vio { + compatible = "iio-hwmon"; + io-channels = <&adc 9>; + }; + + iio-hwmon-vddra { + compatible = "iio-hwmon"; + io-channels = <&adc 11>; + }; + + iio-hwmon-battery { + compatible = "iio-hwmon"; + io-channels = <&adc 12>; + }; + + iio-hwmon-vddrb { + compatible = "iio-hwmon"; + io-channels = <&adc 13>; + }; +}; + +&pwm_tacho { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default + &pinctrl_pwm2_default &pinctrl_pwm3_default + &pinctrl_pwm4_default>; + + fan@0 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x00>; + }; + + fan@1 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x01>; + }; + + fan@2 { + reg = <0x02>; + aspeed,fan-tach-ch = /bits/ 8 <0x02>; + }; + + fan@3 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x03>; + }; + + fan@4 { + reg = <0x04>; + aspeed,fan-tach-ch = /bits/ 8 <0x04>; + }; + + fan@5 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x05>; + }; + + fan@6 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x06>; + }; + + fan@7 { + reg = <0x02>; + aspeed,fan-tach-ch = /bits/ 8 <0x07>; + }; + + fan@8 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x08>; + }; + + fan@9 { + reg = <0x04>; + aspeed,fan-tach-ch = /bits/ 8 <0x09>; + }; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + label = "bmc"; + m25p,fast-read; + spi-max-frequency = <50000000>; + partitions { + #address-cells = < 1 >; + #size-cells = < 1 >; + compatible = "fixed-partitions"; + u-boot@0 { + reg = < 0 0x60000 >; + label = "u-boot"; + }; + u-boot-env@60000 { + reg = < 0x60000 0x20000 >; + label = "u-boot-env"; + }; + obmc-ubi@80000 { + reg = < 0x80000 0x1F80000 >; + label = "obmc-ubi"; + }; + }; + }; + flash@1 { + status = "okay"; + label = "alt-bmc"; + m25p,fast-read; + spi-max-frequency = <50000000>; + partitions { + #address-cells = < 1 >; + #size-cells = < 1 >; + compatible = "fixed-partitions"; + u-boot@0 { + reg = < 0 0x60000 >; + label = "alt-u-boot"; + }; + u-boot-env@60000 { + reg = < 0x60000 0x20000 >; + label = "alt-u-boot-env"; + }; + obmc-ubi@80000 { + reg = < 0x80000 0x1F80000 >; + label = "alt-obmc-ubi"; + }; + }; + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + + flash@0 { + status = "okay"; + label = "pnor"; + m25p,fast-read; + spi-max-frequency = <100000000>; + }; +}; + +&lpc_ctrl { + status = "okay"; + memory-region = <&flash_memory>; + flash = <&spi1>; +}; + +&uart1 { + /* Rear RS-232 connector */ + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd1_default + &pinctrl_rxd1_default + &pinctrl_nrts1_default + &pinctrl_ndtr1_default + &pinctrl_ndsr1_default + &pinctrl_ncts1_default + &pinctrl_ndcd1_default + &pinctrl_nri1_default>; +}; + +&uart2 { + /* APSS */ + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd2_default &pinctrl_rxd2_default>; +}; + +&uart5 { + status = "okay"; +}; + +&mac0 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii1_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, + <&syscon ASPEED_CLK_MAC1RCLK>; + clock-names = "MACCLK", "RCLK"; + use-ncsi; +}; + +&mac1 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; +}; + +&i2c0 { + status = "okay"; + + tmp275@48 { + compatible = "ti,tmp275"; + reg = <0x48>; + }; +}; + +&i2c1 { + status = "disabled"; +}; + +&i2c2 { + status = "okay"; + + /* CPU MFG CONN */ + +}; + +&i2c3 { + status = "okay"; + + /* APSS */ + /* CPLD */ + + /* PCA9516 (repeater) -> + * CLK Buffer 9FGS9092 + * Power Supply 0 + * Power Supply 1 + * PCA 9552 LED + */ + + pca9552: pca9552@60 { + compatible = "nxp,pca9552"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio@0 { + reg = <0>; + type = <PCA955X_TYPE_GPIO>; + }; + gpio@1 { + reg = <1>; + type = <PCA955X_TYPE_GPIO>; + }; + gpio@2 { + reg = <2>; + type = <PCA955X_TYPE_GPIO>; + }; + gpio@3 { + reg = <3>; + type = <PCA955X_TYPE_GPIO>; + }; + gpio@4 { + reg = <4>; + type = <PCA955X_TYPE_GPIO>; + }; + gpio@5 { + reg = <5>; + type = <PCA955X_TYPE_GPIO>; + }; + gpio@6 { + reg = <6>; + type = <PCA955X_TYPE_GPIO>; + }; + gpio@7 { + reg = <7>; + type = <PCA955X_TYPE_GPIO>; + }; + gpio@8 { + reg = <8>; + type = <PCA955X_TYPE_GPIO>; + }; + gpio@9 { + reg = <9>; + type = <PCA955X_TYPE_GPIO>; + }; + gpio@10 { + reg = <10>; + type = <PCA955X_TYPE_GPIO>; + }; + gpio@11 { + reg = <11>; + type = <PCA955X_TYPE_GPIO>; + }; + gpio@12 { + reg = <12>; + type = <PCA955X_TYPE_GPIO>; + }; + gpio@13 { + reg = <13>; + type = <PCA955X_TYPE_GPIO>; + }; + gpio@14 { + reg = <14>; + type = <PCA955X_TYPE_GPIO>; + }; + gpio@15 { + reg = <15>; + type = <PCA955X_TYPE_GPIO>; + }; + }; + + power-supply@68 { + compatible = "ibm,cffps1"; + reg = <0x68>; + }; + + power-supply@69 { + compatible = "ibm,cffps1"; + reg = <0x69>; + }; +}; + +&i2c4 { + status = "okay"; + + /* CP0 VDD & VCS : IR35221 */ + /* CP0 VDN & VIO : IR35221 */ + /* CP0 VDDR : IR35221 */ + + ir35221@28 { + compatible = "infineon,ir35221"; + reg = <0x28>; + }; + + ir35221@29 { + compatible = "infineon,ir35221"; + reg = <0x29>; + }; + + ir35221@2d { + compatible = "infineon,ir35221"; + reg = <0x2d>; + }; + +}; + +&i2c5 { + status = "disabled"; +}; + +&i2c6 { + status = "disabled"; +}; + +&i2c7 { + status = "disabled"; +}; + +&i2c8 { + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; +}; + +&i2c9 { + status = "okay"; + + /* PCIe G3 x16 slot */ +}; + +&i2c10 { + status = "disabled"; +}; + +&i2c11 { + status = "okay"; + + /* CPLD */ + /* TPM */ + /* RTC RX8900CE */ + /* TMP275A */ + /* TMP275A */ + + tmp275@48 { + compatible = "ti,tmp275"; + reg = <0x48>; + }; + + tmp275@49 { + compatible = "ti,tmp275"; + reg = <0x49>; + }; + +}; + +&i2c12 { + status = "disabled"; +}; + +&i2c13 { + status = "disabled"; +}; + +&vuart { + status = "okay"; +}; + +&gfx { + status = "okay"; + memory-region = <&gfx_memory>; +}; + +&adc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0_default + &pinctrl_adc1_default + &pinctrl_adc2_default + &pinctrl_adc3_default + &pinctrl_adc4_default + &pinctrl_adc5_default + &pinctrl_adc6_default + &pinctrl_adc7_default + &pinctrl_adc8_default + &pinctrl_adc9_default + &pinctrl_adc10_default + &pinctrl_adc11_default + &pinctrl_adc12_default + &pinctrl_adc13_default + &pinctrl_adc14_default + &pinctrl_adc15_default>; +}; + +&wdt1 { + aspeed,reset-type = "none"; + aspeed,external-signal; + aspeed,ext-push-pull; + aspeed,ext-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdtrst1_default>; +}; + +&wdt2 { + aspeed,alt-boot; +}; + +&ibt { + status = "okay"; +}; + +&vhub { + status = "okay"; +}; + +&video { + status = "okay"; + memory-region = <&video_engine_memory>; +}; + +#include "ibm-power9-dual.dtsi" diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts index 5f4ee67ac787..4d070d6ba09f 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts @@ -4,6 +4,7 @@ #include "aspeed-g6.dtsi" #include <dt-bindings/gpio/aspeed-gpio.h> +#include <dt-bindings/i2c/i2c.h> #include <dt-bindings/leds/leds-pca955x.h> / { @@ -438,7 +439,13 @@ }; &i2c0 { + multi-master; status = "okay"; + + ibm-panel@62 { + compatible = "ibm,op-panel"; + reg = <(0x62 | I2C_OWN_SLAVE_ADDRESS)>; + }; }; &i2c1 { diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index 9c91afb2b404..a93009aa2f04 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -425,7 +425,6 @@ interrupts = <8>; clocks = <&syscon ASPEED_CLK_APB>; no-loopback-test; - aspeed,sirq-polarity-sense = <&syscon 0x70 25>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/ast2500-facebook-netbmc-common.dtsi b/arch/arm/boot/dts/ast2500-facebook-netbmc-common.dtsi index 7468f102bd76..c0c43b8644ee 100644 --- a/arch/arm/boot/dts/ast2500-facebook-netbmc-common.dtsi +++ b/arch/arm/boot/dts/ast2500-facebook-netbmc-common.dtsi @@ -47,25 +47,12 @@ status = "okay"; m25p,fast-read; label = "spi0.0"; - -#include "facebook-bmc-flash-layout.dtsi" }; fmc_flash1: flash@1 { status = "okay"; m25p,fast-read; label = "spi0.1"; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - flash1@0 { - reg = <0x0 0x2000000>; - label = "flash1"; - }; - }; }; }; diff --git a/arch/arm/boot/dts/at91-ariag25.dts b/arch/arm/boot/dts/at91-ariag25.dts index dbfefef2869d..713d18f80356 100644 --- a/arch/arm/boot/dts/at91-ariag25.dts +++ b/arch/arm/boot/dts/at91-ariag25.dts @@ -22,7 +22,7 @@ bootargs = "console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootwait"; }; - memory { + memory@20000000 { /* 128 MB, change this for 256 MB revision */ reg = <0x20000000 0x8000000>; }; @@ -93,6 +93,7 @@ pinctrl-0 = < &pinctrl_mmc0_slot0_clk_cmd_dat0 &pinctrl_mmc0_slot0_dat1_3>; + pinctrl-names = "default"; status = "okay"; slot@0 { diff --git a/arch/arm/boot/dts/at91-ariettag25.dts b/arch/arm/boot/dts/at91-ariettag25.dts index 0267e72c074a..2c52a71752c2 100644 --- a/arch/arm/boot/dts/at91-ariettag25.dts +++ b/arch/arm/boot/dts/at91-ariettag25.dts @@ -15,7 +15,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@20000000 { reg = <0x20000000 0x8000000>; }; @@ -48,6 +48,7 @@ pinctrl-0 = < &pinctrl_mmc0_slot0_clk_cmd_dat0 &pinctrl_mmc0_slot0_dat1_3>; + pinctrl-names = "default"; status = "okay"; slot@0 { diff --git a/arch/arm/boot/dts/at91-cosino.dtsi b/arch/arm/boot/dts/at91-cosino.dtsi index feebd54f670e..ee0f5da6d819 100644 --- a/arch/arm/boot/dts/at91-cosino.dtsi +++ b/arch/arm/boot/dts/at91-cosino.dtsi @@ -20,7 +20,7 @@ bootargs = "console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootfstype=ext3 rootwait"; }; - memory { + memory@20000000 { reg = <0x20000000 0x8000000>; }; @@ -112,6 +112,7 @@ &pinctrl_board_mmc0 &pinctrl_mmc0_slot0_clk_cmd_dat0 &pinctrl_mmc0_slot0_dat1_3>; + pinctrl-names = "default"; status = "okay"; slot@0 { diff --git a/arch/arm/boot/dts/at91-cosino_mega2560.dts b/arch/arm/boot/dts/at91-cosino_mega2560.dts index 73e88d1ba4ed..04cb7bee937d 100644 --- a/arch/arm/boot/dts/at91-cosino_mega2560.dts +++ b/arch/arm/boot/dts/at91-cosino_mega2560.dts @@ -34,6 +34,7 @@ pinctrl-0 = < &pinctrl_mmc1_slot0_clk_cmd_dat0 &pinctrl_mmc1_slot0_dat1_3>; + pinctrl-names = "default"; status = "okay"; slot@0 { diff --git a/arch/arm/boot/dts/at91-foxg20.dts b/arch/arm/boot/dts/at91-foxg20.dts index 683b9e37f9c5..7edf057047f8 100644 --- a/arch/arm/boot/dts/at91-foxg20.dts +++ b/arch/arm/boot/dts/at91-foxg20.dts @@ -17,7 +17,7 @@ bootargs = "console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootwait"; }; - memory { + memory@20000000 { reg = <0x20000000 0x4000000>; }; @@ -55,6 +55,7 @@ &pinctrl_mmc0_clk &pinctrl_mmc0_slot1_cmd_dat0 &pinctrl_mmc0_slot1_dat1_3>; + pinctrl-names = "default"; status = "okay"; slot@1 { diff --git a/arch/arm/boot/dts/at91-kizbox.dts b/arch/arm/boot/dts/at91-kizbox.dts index 7d938ccf71b0..7add151f6250 100644 --- a/arch/arm/boot/dts/at91-kizbox.dts +++ b/arch/arm/boot/dts/at91-kizbox.dts @@ -18,7 +18,7 @@ stdout-path = &dbgu; }; - memory { + memory@20000000 { reg = <0x20000000 0x2000000>; }; diff --git a/arch/arm/boot/dts/at91-kizbox2-common.dtsi b/arch/arm/boot/dts/at91-kizbox2-common.dtsi index af38253a6e7a..25f761065106 100644 --- a/arch/arm/boot/dts/at91-kizbox2-common.dtsi +++ b/arch/arm/boot/dts/at91-kizbox2-common.dtsi @@ -17,7 +17,7 @@ stdout-path = &dbgu; }; - memory { + memory@20000000 { reg = <0x20000000 0x10000000>; }; diff --git a/arch/arm/boot/dts/at91-kizboxmini-common.dtsi b/arch/arm/boot/dts/at91-kizboxmini-common.dtsi index fddf267b2d17..d37724c10695 100644 --- a/arch/arm/boot/dts/at91-kizboxmini-common.dtsi +++ b/arch/arm/boot/dts/at91-kizboxmini-common.dtsi @@ -16,7 +16,7 @@ stdout-path = &dbgu; }; - memory { + memory@20000000 { reg = <0x20000000 0x8000000>; }; diff --git a/arch/arm/boot/dts/at91-linea.dtsi b/arch/arm/boot/dts/at91-linea.dtsi index 41f163955b1e..533a440d5583 100644 --- a/arch/arm/boot/dts/at91-linea.dtsi +++ b/arch/arm/boot/dts/at91-linea.dtsi @@ -13,7 +13,7 @@ compatible = "axentia,linea", "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5"; - memory { + memory@20000000 { reg = <0x20000000 0x4000000>; }; }; diff --git a/arch/arm/boot/dts/at91-qil_a9260.dts b/arch/arm/boot/dts/at91-qil_a9260.dts index a50b7fd2149f..969d990767fc 100644 --- a/arch/arm/boot/dts/at91-qil_a9260.dts +++ b/arch/arm/boot/dts/at91-qil_a9260.dts @@ -14,7 +14,7 @@ bootargs = "console=ttyS0,115200"; }; - memory { + memory@20000000 { reg = <0x20000000 0x4000000>; }; @@ -52,6 +52,7 @@ &pinctrl_mmc0_clk &pinctrl_mmc0_slot0_cmd_dat0 &pinctrl_mmc0_slot0_dat1_3>; + pinctrl-names = "default"; status = "okay"; slot@0 { reg = <0>; diff --git a/arch/arm/boot/dts/at91-sam9_l9260.dts b/arch/arm/boot/dts/at91-sam9_l9260.dts index 954404ed8158..1e2a28c2f365 100644 --- a/arch/arm/boot/dts/at91-sam9_l9260.dts +++ b/arch/arm/boot/dts/at91-sam9_l9260.dts @@ -15,7 +15,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@20000000 { reg = <0x20000000 0x4000000>; }; @@ -49,6 +49,7 @@ &pinctrl_mmc0_clk &pinctrl_mmc0_slot1_cmd_dat0 &pinctrl_mmc0_slot1_dat1_3>; + pinctrl-names = "default"; status = "okay"; slot@1 { diff --git a/arch/arm/boot/dts/at91-sama5d3_xplained.dts b/arch/arm/boot/dts/at91-sama5d3_xplained.dts index 7abf555cd2fe..cf13632edd44 100644 --- a/arch/arm/boot/dts/at91-sama5d3_xplained.dts +++ b/arch/arm/boot/dts/at91-sama5d3_xplained.dts @@ -16,7 +16,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@20000000 { reg = <0x20000000 0x10000000>; }; diff --git a/arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi b/arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi index 0be184a870eb..710cb72bda5a 100644 --- a/arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi +++ b/arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi @@ -9,7 +9,7 @@ model = "Aries/DENX MA5D4"; compatible = "aries,ma5d4", "denx,ma5d4", "atmel,sama5d4", "atmel,sama5"; - memory { + memory@20000000 { reg = <0x20000000 0x10000000>; }; diff --git a/arch/arm/boot/dts/at91-sama5d4_xplained.dts b/arch/arm/boot/dts/at91-sama5d4_xplained.dts index 924d9491780d..e5974a17374c 100644 --- a/arch/arm/boot/dts/at91-sama5d4_xplained.dts +++ b/arch/arm/boot/dts/at91-sama5d4_xplained.dts @@ -16,7 +16,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@20000000 { reg = <0x20000000 0x20000000>; }; diff --git a/arch/arm/boot/dts/at91-sama5d4ek.dts b/arch/arm/boot/dts/at91-sama5d4ek.dts index 0cc1cff13e46..fe432b6b7e95 100644 --- a/arch/arm/boot/dts/at91-sama5d4ek.dts +++ b/arch/arm/boot/dts/at91-sama5d4ek.dts @@ -16,7 +16,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@20000000 { reg = <0x20000000 0x20000000>; }; diff --git a/arch/arm/boot/dts/at91-som60.dtsi b/arch/arm/boot/dts/at91-som60.dtsi index 241682a207c5..39474a112b16 100644 --- a/arch/arm/boot/dts/at91-som60.dtsi +++ b/arch/arm/boot/dts/at91-som60.dtsi @@ -16,7 +16,7 @@ stdout-path = &dbgu; }; - memory { + memory@20000000 { reg = <0x20000000 0x8000000>; }; diff --git a/arch/arm/boot/dts/at91-vinco.dts b/arch/arm/boot/dts/at91-vinco.dts index 15050fdd479d..a51a3372afa1 100644 --- a/arch/arm/boot/dts/at91-vinco.dts +++ b/arch/arm/boot/dts/at91-vinco.dts @@ -17,7 +17,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@20000000 { reg = <0x20000000 0x4000000>; }; diff --git a/arch/arm/boot/dts/at91-wb45n.dtsi b/arch/arm/boot/dts/at91-wb45n.dtsi index ebe61a25ca96..430c75358086 100644 --- a/arch/arm/boot/dts/at91-wb45n.dtsi +++ b/arch/arm/boot/dts/at91-wb45n.dtsi @@ -17,7 +17,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@20000000 { reg = <0x20000000 0x4000000>; }; @@ -145,6 +145,7 @@ }; &mmc0 { + pinctrl-names = "default"; pinctrl-0 = < &pinctrl_mmc0_slot0_clk_cmd_dat0 &pinctrl_mmc0_slot0_dat1_3>; diff --git a/arch/arm/boot/dts/at91-wb50n.dtsi b/arch/arm/boot/dts/at91-wb50n.dtsi index 1487b893cfa7..74b249bb6351 100644 --- a/arch/arm/boot/dts/at91-wb50n.dtsi +++ b/arch/arm/boot/dts/at91-wb50n.dtsi @@ -17,7 +17,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@20000000 { reg = <0x20000000 0x4000000>; }; }; diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi index a5040f5ea641..d1181ead18e5 100644 --- a/arch/arm/boot/dts/at91rm9200.dtsi +++ b/arch/arm/boot/dts/at91rm9200.dtsi @@ -39,16 +39,17 @@ ssc2 = &ssc2; }; cpus { - #address-cells = <0>; + #address-cells = <1>; #size-cells = <0>; - cpu { + cpu@0 { compatible = "arm,arm920t"; device_type = "cpu"; + reg = <0>; }; }; - memory { + memory@20000000 { device_type = "memory"; reg = <0x20000000 0x04000000>; }; @@ -70,6 +71,9 @@ sram: sram@200000 { compatible = "mmio-sram"; reg = <0x00200000 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00200000 0x4000>; }; ahb { @@ -169,7 +173,6 @@ clock-names = "mci_clk"; #address-cells = <1>; #size-cells = <0>; - pinctrl-names = "default"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/at91rm9200ek.dts b/arch/arm/boot/dts/at91rm9200ek.dts index 1e0bf5afa913..e1ef4e44e663 100644 --- a/arch/arm/boot/dts/at91rm9200ek.dts +++ b/arch/arm/boot/dts/at91rm9200ek.dts @@ -15,7 +15,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@20000000 { reg = <0x20000000 0x4000000>; }; diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi index 6afbb48e7ff0..82c5d7fd9811 100644 --- a/arch/arm/boot/dts/at91sam9260.dtsi +++ b/arch/arm/boot/dts/at91sam9260.dtsi @@ -36,16 +36,17 @@ ssc0 = &ssc0; }; cpus { - #address-cells = <0>; + #address-cells = <1>; #size-cells = <0>; - cpu { + cpu@0 { compatible = "arm,arm926ej-s"; device_type = "cpu"; + reg = <0>; }; }; - memory { + memory@20000000 { device_type = "memory"; reg = <0x20000000 0x04000000>; }; @@ -73,6 +74,9 @@ sram0: sram@2ff000 { compatible = "mmio-sram"; reg = <0x002ff000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x002ff000 0x2000>; }; ahb { @@ -650,7 +654,6 @@ interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>; #address-cells = <1>; #size-cells = <0>; - pinctrl-names = "default"; clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; clock-names = "mci_clk"; status = "disabled"; diff --git a/arch/arm/boot/dts/at91sam9260ek.dts b/arch/arm/boot/dts/at91sam9260ek.dts index 81f808a10931..d3446e42b598 100644 --- a/arch/arm/boot/dts/at91sam9260ek.dts +++ b/arch/arm/boot/dts/at91sam9260ek.dts @@ -16,7 +16,7 @@ stdout-path = &dbgu; }; - memory { + memory@20000000 { reg = <0x20000000 0x4000000>; }; @@ -55,6 +55,7 @@ &pinctrl_mmc0_clk &pinctrl_mmc0_slot1_cmd_dat0 &pinctrl_mmc0_slot1_dat1_3>; + pinctrl-names = "default"; status = "okay"; slot@1 { reg = <1>; diff --git a/arch/arm/boot/dts/at91sam9261.dtsi b/arch/arm/boot/dts/at91sam9261.dtsi index 5ed3d745ac86..7adc36ca8a46 100644 --- a/arch/arm/boot/dts/at91sam9261.dtsi +++ b/arch/arm/boot/dts/at91sam9261.dtsi @@ -33,16 +33,17 @@ }; cpus { - #address-cells = <0>; + #address-cells = <1>; #size-cells = <0>; - cpu { + cpu@0 { compatible = "arm,arm926ej-s"; device_type = "cpu"; + reg = <0>; }; }; - memory { + memory@20000000 { device_type = "memory"; reg = <0x20000000 0x08000000>; }; @@ -64,6 +65,9 @@ sram: sram@300000 { compatible = "mmio-sram"; reg = <0x00300000 0x28000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00300000 0x28000>; }; ahb { diff --git a/arch/arm/boot/dts/at91sam9261ek.dts b/arch/arm/boot/dts/at91sam9261ek.dts index c4ef74fea97c..beed819609e8 100644 --- a/arch/arm/boot/dts/at91sam9261ek.dts +++ b/arch/arm/boot/dts/at91sam9261ek.dts @@ -16,7 +16,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@20000000 { reg = <0x20000000 0x4000000>; }; diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi index 5c990cfae254..fe45d96239c9 100644 --- a/arch/arm/boot/dts/at91sam9263.dtsi +++ b/arch/arm/boot/dts/at91sam9263.dtsi @@ -35,16 +35,17 @@ }; cpus { - #address-cells = <0>; + #address-cells = <1>; #size-cells = <0>; - cpu { + cpu@0 { compatible = "arm,arm926ej-s"; device_type = "cpu"; + reg = <0>; }; }; - memory { + memory@20000000 { device_type = "memory"; reg = <0x20000000 0x08000000>; }; @@ -66,11 +67,17 @@ sram0: sram@300000 { compatible = "mmio-sram"; reg = <0x00300000 0x14000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00300000 0x14000>; }; sram1: sram@500000 { compatible = "mmio-sram"; reg = <0x00500000 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00500000 0x4000>; }; ahb { @@ -647,7 +654,6 @@ compatible = "atmel,hsmci"; reg = <0xfff80000 0x600>; interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>; - pinctrl-names = "default"; #address-cells = <1>; #size-cells = <0>; clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; @@ -659,7 +665,6 @@ compatible = "atmel,hsmci"; reg = <0xfff84000 0x600>; interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>; - pinctrl-names = "default"; #address-cells = <1>; #size-cells = <0>; clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; diff --git a/arch/arm/boot/dts/at91sam9263ek.dts b/arch/arm/boot/dts/at91sam9263ek.dts index 62d218542a48..71f60576761a 100644 --- a/arch/arm/boot/dts/at91sam9263ek.dts +++ b/arch/arm/boot/dts/at91sam9263ek.dts @@ -16,7 +16,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@20000000 { reg = <0x20000000 0x4000000>; }; @@ -72,6 +72,7 @@ &pinctrl_mmc0_clk &pinctrl_mmc0_slot0_cmd_dat0 &pinctrl_mmc0_slot0_dat1_3>; + pinctrl-names = "default"; status = "okay"; slot@0 { reg = <0>; diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi index 4117cf880508..708e1646b7f4 100644 --- a/arch/arm/boot/dts/at91sam9g20.dtsi +++ b/arch/arm/boot/dts/at91sam9g20.dtsi @@ -11,7 +11,7 @@ model = "Atmel AT91SAM9G20 family SoC"; compatible = "atmel,at91sam9g20"; - memory { + memory@20000000 { reg = <0x20000000 0x08000000>; }; @@ -22,6 +22,9 @@ sram1: sram@2fc000 { compatible = "mmio-sram"; reg = <0x002fc000 0x8000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x002fc000 0x8000>; }; ahb { diff --git a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi index bda22700110c..6e6e672c0b86 100644 --- a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi +++ b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi @@ -13,7 +13,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@20000000 { reg = <0x20000000 0x4000000>; }; @@ -93,6 +93,7 @@ &pinctrl_mmc0_clk &pinctrl_mmc0_slot1_cmd_dat0 &pinctrl_mmc0_slot1_dat1_3>; + pinctrl-names = "default"; status = "okay"; slot@1 { reg = <1>; diff --git a/arch/arm/boot/dts/at91sam9g25-gardena-smart-gateway.dts b/arch/arm/boot/dts/at91sam9g25-gardena-smart-gateway.dts new file mode 100644 index 000000000000..7da70aeeb528 --- /dev/null +++ b/arch/arm/boot/dts/at91sam9g25-gardena-smart-gateway.dts @@ -0,0 +1,158 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Device Tree file for the GARDENA smart Gateway (Article No. 19000) + * + * Copyright (C) 2020 GARDENA GmbH + */ + +/dts-v1/; + +#include "at91sam9g25.dtsi" +#include "at91sam9x5ek.dtsi" +#include <dt-bindings/input/input.h> + +/ { + model = "GARDENA smart Gateway (Article No. 19000)"; + compatible = "gardena,smart-gateway-at91sam", "atmel,at91sam9g25", "atmel,at91sam9x5", + "atmel,at91sam9"; + + aliases { + serial1 = &usart3; + }; + + gpio-keys { + compatible = "gpio-keys"; + + user_btn1 { + label = "USER_BTN1"; + gpios = <&pioA 24 GPIO_ACTIVE_LOW>; + linux,code = <KEY_PROG1>; + }; + }; + + 1wire_cm { + status = "disabled"; + }; + + leds { + compatible = "gpio-leds"; + + power_blue { + label = "smartgw:power:blue"; + gpios = <&pioC 21 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + power_green { + label = "smartgw:power:green"; + gpios = <&pioC 20 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + power_red { + label = "smartgw:power:red"; + gpios = <&pioC 19 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + radio_blue { + label = "smartgw:radio:blue"; + gpios = <&pioC 18 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + radio_green { + label = "smartgw:radio:green"; + gpios = <&pioC 17 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + radio_red { + label = "smartgw:radio:red"; + gpios = <&pioC 16 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + internet_blue { + label = "smartgw:internet:blue"; + gpios = <&pioC 15 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + internet_green { + label = "smartgw:internet:green"; + gpios = <&pioC 14 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + internet_red { + label = "smartgw:internet:red"; + gpios = <&pioC 13 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + heartbeat { + label = "smartgw:heartbeat"; + gpios = <&pioB 8 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + pb18 { + status = "disabled"; + }; + + pd21 { + status = "disabled"; + }; + }; +}; + +&macb0 { + phy-mode = "rmii"; + status = "okay"; +}; + +&usart0 { + status = "disabled"; +}; + +&usart2 { + status = "disabled"; +}; + +&usart3 { + status = "okay"; + + pinctrl-0 = <&pinctrl_usart3 + &pinctrl_usart3_rts + &pinctrl_usart3_cts + >; +}; + +&watchdog { + status = "okay"; +}; + +&mmc0 { + status = "disabled"; +}; + +&mmc1 { + status = "disabled"; +}; + +&spi0 { + status = "disabled"; +}; + +&i2c0 { + status = "disabled"; +}; + +&adc0 { + status = "disabled"; +}; + +&ssc0 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index 1fbee2a7785f..19fc748a87c5 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi @@ -41,16 +41,17 @@ pwm0 = &pwm0; }; cpus { - #address-cells = <0>; + #address-cells = <1>; #size-cells = <0>; - cpu { + cpu@0 { compatible = "arm,arm926ej-s"; device_type = "cpu"; + reg = <0>; }; }; - memory { + memory@70000000 { device_type = "memory"; reg = <0x70000000 0x10000000>; }; @@ -78,6 +79,9 @@ sram: sram@300000 { compatible = "mmio-sram"; reg = <0x00300000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00300000 0x10000>; }; ahb { @@ -871,7 +875,6 @@ compatible = "atmel,hsmci"; reg = <0xfff80000 0x600>; interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>; - pinctrl-names = "default"; dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>; dma-names = "rxtx"; #address-cells = <1>; @@ -885,7 +888,6 @@ compatible = "atmel,hsmci"; reg = <0xfffd0000 0x600>; interrupts = <29 IRQ_TYPE_LEVEL_HIGH 0>; - pinctrl-names = "default"; dmas = <&dma 1 AT91_DMA_CFG_PER_ID(13)>; dma-names = "rxtx"; #address-cells = <1>; diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts index a3a5c82d9f29..9734667abbfc 100644 --- a/arch/arm/boot/dts/at91sam9m10g45ek.dts +++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts @@ -18,7 +18,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@70000000 { reg = <0x70000000 0x4000000>; }; @@ -99,6 +99,7 @@ &pinctrl_board_mmc0 &pinctrl_mmc0_slot0_clk_cmd_dat0 &pinctrl_mmc0_slot0_dat1_3>; + pinctrl-names = "default"; status = "okay"; slot@0 { reg = <0>; @@ -112,6 +113,7 @@ &pinctrl_board_mmc1 &pinctrl_mmc1_slot0_clk_cmd_dat0 &pinctrl_mmc1_slot0_dat1_3>; + pinctrl-names = "default"; status = "okay"; slot@0 { reg = <0>; diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi index a994d076dc7e..0785389f5507 100644 --- a/arch/arm/boot/dts/at91sam9n12.dtsi +++ b/arch/arm/boot/dts/at91sam9n12.dtsi @@ -37,16 +37,17 @@ pwm0 = &pwm0; }; cpus { - #address-cells = <0>; + #address-cells = <1>; #size-cells = <0>; - cpu { + cpu@0 { compatible = "arm,arm926ej-s"; device_type = "cpu"; + reg = <0>; }; }; - memory { + memory@20000000 { device_type = "memory"; reg = <0x20000000 0x10000000>; }; @@ -68,6 +69,9 @@ sram: sram@300000 { compatible = "mmio-sram"; reg = <0x00300000 0x8000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00300000 0x8000>; }; ahb { diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts index 870b83ff6b97..2bc4e6e0a923 100644 --- a/arch/arm/boot/dts/at91sam9n12ek.dts +++ b/arch/arm/boot/dts/at91sam9n12ek.dts @@ -17,7 +17,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@20000000 { reg = <0x20000000 0x8000000>; }; diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi index 4d70194fd808..5653e70c84b4 100644 --- a/arch/arm/boot/dts/at91sam9rl.dtsi +++ b/arch/arm/boot/dts/at91sam9rl.dtsi @@ -38,16 +38,17 @@ }; cpus { - #address-cells = <0>; + #address-cells = <1>; #size-cells = <0>; - cpu { + cpu@0 { compatible = "arm,arm926ej-s"; device_type = "cpu"; + reg = <0>; }; }; - memory { + memory@20000000 { device_type = "memory"; reg = <0x20000000 0x04000000>; }; @@ -75,6 +76,9 @@ sram: sram@300000 { compatible = "mmio-sram"; reg = <0x00300000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00300000 0x10000>; }; ahb { diff --git a/arch/arm/boot/dts/at91sam9rlek.dts b/arch/arm/boot/dts/at91sam9rlek.dts index 0de75d3c4f18..1590862f16f2 100644 --- a/arch/arm/boot/dts/at91sam9rlek.dts +++ b/arch/arm/boot/dts/at91sam9rlek.dts @@ -17,7 +17,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@20000000 { reg = <0x20000000 0x4000000>; }; diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi index 948fe99ab6c3..4cdb05079cc7 100644 --- a/arch/arm/boot/dts/at91sam9x5.dtsi +++ b/arch/arm/boot/dts/at91sam9x5.dtsi @@ -39,16 +39,17 @@ pwm0 = &pwm0; }; cpus { - #address-cells = <0>; + #address-cells = <1>; #size-cells = <0>; - cpu { + cpu@0 { compatible = "arm,arm926ej-s"; device_type = "cpu"; + reg = <0>; }; }; - memory { + memory@20000000 { device_type = "memory"; reg = <0x20000000 0x10000000>; }; @@ -76,6 +77,9 @@ sram: sram@300000 { compatible = "mmio-sram"; reg = <0x00300000 0x8000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00300000 0x8000>; }; ahb { @@ -647,7 +651,6 @@ interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(0)>; dma-names = "rxtx"; - pinctrl-names = "default"; clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; clock-names = "mci_clk"; #address-cells = <1>; @@ -661,7 +664,6 @@ interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>; dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(0)>; dma-names = "rxtx"; - pinctrl-names = "default"; clocks = <&pmc PMC_TYPE_PERIPHERAL 26>; clock-names = "mci_clk"; #address-cells = <1>; diff --git a/arch/arm/boot/dts/at91sam9x5cm.dtsi b/arch/arm/boot/dts/at91sam9x5cm.dtsi index 75d2f7fd314f..cdd37f67280b 100644 --- a/arch/arm/boot/dts/at91sam9x5cm.dtsi +++ b/arch/arm/boot/dts/at91sam9x5cm.dtsi @@ -7,7 +7,7 @@ */ / { - memory { + memory@20000000 { reg = <0x20000000 0x8000000>; }; diff --git a/arch/arm/boot/dts/at91sam9x5ek.dtsi b/arch/arm/boot/dts/at91sam9x5ek.dtsi index c934928742b0..6d1264de6060 100644 --- a/arch/arm/boot/dts/at91sam9x5ek.dtsi +++ b/arch/arm/boot/dts/at91sam9x5ek.dtsi @@ -56,6 +56,7 @@ &pinctrl_board_mmc0 &pinctrl_mmc0_slot0_clk_cmd_dat0 &pinctrl_mmc0_slot0_dat1_3>; + pinctrl-names = "default"; status = "okay"; slot@0 { @@ -70,6 +71,7 @@ &pinctrl_board_mmc1 &pinctrl_mmc1_slot0_clk_cmd_dat0 &pinctrl_mmc1_slot0_dat1_3>; + pinctrl-names = "default"; status = "okay"; slot@0 { diff --git a/arch/arm/boot/dts/at91sam9xe.dtsi b/arch/arm/boot/dts/at91sam9xe.dtsi index 3f9d8caf8b0a..f571f77779c3 100644 --- a/arch/arm/boot/dts/at91sam9xe.dtsi +++ b/arch/arm/boot/dts/at91sam9xe.dtsi @@ -19,5 +19,8 @@ sram1: sram@300000 { compatible = "mmio-sram"; reg = <0x00300000 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00300000 0x4000>; }; }; diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi index 35bdd0969f0a..dacaef2c14ca 100644 --- a/arch/arm/boot/dts/bcm-cygnus.dtsi +++ b/arch/arm/boot/dts/bcm-cygnus.dtsi @@ -234,8 +234,8 @@ compatible = "arm,sp805" , "arm,primecell"; reg = <0x18009000 0x1000>; interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&axi81_clk>; - clock-names = "apb_pclk"; + clocks = <&axi81_clk>, <&axi81_clk>; + clock-names = "wdog_clk", "apb_pclk"; }; gpio_ccm: gpio@1800a000 { diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi index c846fa3c244d..e895f7cb8c9f 100644 --- a/arch/arm/boot/dts/bcm-nsp.dtsi +++ b/arch/arm/boot/dts/bcm-nsp.dtsi @@ -368,7 +368,7 @@ }; ccbtimer0: timer@34000 { - compatible = "arm,sp804"; + compatible = "arm,sp804", "arm,primecell"; reg = <0x34000 0x1000>; interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; @@ -377,7 +377,7 @@ }; ccbtimer1: timer@35000 { - compatible = "arm,sp804"; + compatible = "arm,sp804", "arm,primecell"; reg = <0x35000 0x1000>; interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; @@ -438,7 +438,7 @@ reg = <0x39000 0x1000>; interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; clocks = <&iprocslow>, <&iprocslow>; - clock-names = "wdogclk", "apb_pclk"; + clock-names = "wdog_clk", "apb_pclk"; }; lcpll0: lcpll0@3f100 { diff --git a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts index e94244a215af..09a1182c2936 100644 --- a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts +++ b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts @@ -70,6 +70,14 @@ }; }; +&ddc0 { + status = "okay"; +}; + +&ddc1 { + status = "okay"; +}; + &firmware { firmware_clocks: clocks { compatible = "raspberrypi,firmware-clocks"; @@ -170,6 +178,38 @@ "RGMII_TXD3"; }; +&hdmi0 { + clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 0>, <&clk_27MHz>; + clock-names = "hdmi", "bvb", "audio", "cec"; + status = "okay"; +}; + +&hdmi1 { + clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 1>, <&clk_27MHz>; + clock-names = "hdmi", "bvb", "audio", "cec"; + status = "okay"; +}; + +&hvs { + clocks = <&firmware_clocks 4>; +}; + +&pixelvalve0 { + status = "okay"; +}; + +&pixelvalve1 { + status = "okay"; +}; + +&pixelvalve2 { + status = "okay"; +}; + +&pixelvalve4 { + status = "okay"; +}; + &pwm1 { pinctrl-names = "default"; pinctrl-0 = <&pwm1_0_gpio40 &pwm1_1_gpio41>; @@ -253,3 +293,11 @@ &vchiq { interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; }; + +&vc4 { + status = "okay"; +}; + +&vec { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/bcm2711.dtsi b/arch/arm/boot/dts/bcm2711.dtsi index 00bcaed1be32..4847dd305317 100644 --- a/arch/arm/boot/dts/bcm2711.dtsi +++ b/arch/arm/boot/dts/bcm2711.dtsi @@ -12,6 +12,18 @@ interrupt-parent = <&gicv2>; + vc4: gpu { + compatible = "brcm,bcm2711-vc5"; + status = "disabled"; + }; + + clk_27MHz: clk-27M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <27000000>; + clock-output-names = "27MHz-clock"; + }; + clk_108MHz: clk-108M { #clock-cells = <0>; compatible = "fixed-clock"; @@ -238,6 +250,27 @@ status = "disabled"; }; + pixelvalve0: pixelvalve@7e206000 { + compatible = "brcm,bcm2711-pixelvalve0"; + reg = <0x7e206000 0x100>; + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + pixelvalve1: pixelvalve@7e207000 { + compatible = "brcm,bcm2711-pixelvalve1"; + reg = <0x7e207000 0x100>; + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + pixelvalve2: pixelvalve@7e20a000 { + compatible = "brcm,bcm2711-pixelvalve2"; + reg = <0x7e20a000 0x100>; + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + pwm1: pwm@7e20c800 { compatible = "brcm,bcm2835-pwm"; reg = <0x7e20c800 0x28>; @@ -248,10 +281,25 @@ status = "disabled"; }; - hvs@7e400000 { + pixelvalve4: pixelvalve@7e216000 { + compatible = "brcm,bcm2711-pixelvalve4"; + reg = <0x7e216000 0x100>; + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + hvs: hvs@7e400000 { + compatible = "brcm,bcm2711-hvs"; interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; }; + pixelvalve3: pixelvalve@7ec12000 { + compatible = "brcm,bcm2711-pixelvalve3"; + reg = <0x7ec12000 0x100>; + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + dvp: clock@7ef00000 { compatible = "brcm,brcm2711-dvp"; reg = <0x7ef00000 0x10>; @@ -259,6 +307,78 @@ #clock-cells = <1>; #reset-cells = <1>; }; + + hdmi0: hdmi@7ef00700 { + compatible = "brcm,bcm2711-hdmi0"; + reg = <0x7ef00700 0x300>, + <0x7ef00300 0x200>, + <0x7ef00f00 0x80>, + <0x7ef00f80 0x80>, + <0x7ef01b00 0x200>, + <0x7ef01f00 0x400>, + <0x7ef00200 0x80>, + <0x7ef04300 0x100>, + <0x7ef20000 0x100>; + reg-names = "hdmi", + "dvp", + "phy", + "rm", + "packet", + "metadata", + "csc", + "cec", + "hd"; + clock-names = "hdmi", "bvb", "audio", "cec"; + resets = <&dvp 0>; + ddc = <&ddc0>; + dmas = <&dma 10>; + dma-names = "audio-rx"; + status = "disabled"; + }; + + ddc0: i2c@7ef04500 { + compatible = "brcm,bcm2711-hdmi-i2c"; + reg = <0x7ef04500 0x100>, <0x7ef00b00 0x300>; + reg-names = "bsc", "auto-i2c"; + clock-frequency = <97500>; + status = "disabled"; + }; + + hdmi1: hdmi@7ef05700 { + compatible = "brcm,bcm2711-hdmi1"; + reg = <0x7ef05700 0x300>, + <0x7ef05300 0x200>, + <0x7ef05f00 0x80>, + <0x7ef05f80 0x80>, + <0x7ef06b00 0x200>, + <0x7ef06f00 0x400>, + <0x7ef00280 0x80>, + <0x7ef09300 0x100>, + <0x7ef20000 0x100>; + reg-names = "hdmi", + "dvp", + "phy", + "rm", + "packet", + "metadata", + "csc", + "cec", + "hd"; + ddc = <&ddc1>; + clock-names = "hdmi", "bvb", "audio", "cec"; + resets = <&dvp 1>; + dmas = <&dma 17>; + dma-names = "audio-rx"; + status = "disabled"; + }; + + ddc1: i2c@7ef09500 { + compatible = "brcm,bcm2711-hdmi-i2c"; + reg = <0x7ef09500 0x100>, <0x7ef05b00 0x300>; + reg-names = "bsc", "auto-i2c"; + clock-frequency = <97500>; + status = "disabled"; + }; }; /* diff --git a/arch/arm/boot/dts/bcm53016-meraki-mr32.dts b/arch/arm/boot/dts/bcm53016-meraki-mr32.dts new file mode 100644 index 000000000000..3b978dc8997a --- /dev/null +++ b/arch/arm/boot/dts/bcm53016-meraki-mr32.dts @@ -0,0 +1,197 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Broadcom BCM470X / BCM5301X ARM platform code. + * DTS for Meraki MR32 / Codename: Espresso + * + * Copyright (C) 2018-2020 Christian Lamparter <chunkeey@gmail.com> + */ + +/dts-v1/; + +#include "bcm4708.dtsi" +#include "bcm5301x-nand-cs0-bch8.dtsi" +#include <dt-bindings/leds/common.h> + +/ { + compatible = "meraki,mr32", "brcm,brcm53016", "brcm,bcm4708"; + model = "Meraki MR32"; + + chosen { + bootargs = " console=ttyS0,115200n8 earlycon"; + }; + + memory { + reg = <0x00000000 0x08000000>; + device_type = "memory"; + }; + + aliases { + serial1 = &uart2; + }; + + leds { + compatible = "gpio-leds"; + + sysled3 { + function = LED_FUNCTION_FAULT; + color = <LED_COLOR_ID_AMBER>; + gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; + panic-indicator; + }; + sysled2 { + function = LED_FUNCTION_INDICATOR; + color = <LED_COLOR_ID_WHITE>; + gpios = <&chipcommon 19 GPIO_ACTIVE_HIGH>; + }; + }; + + keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + restart { + label = "Reset"; + linux,code = <KEY_RESTART>; + gpios = <&chipcommon 21 GPIO_ACTIVE_LOW>; + }; + }; + + pwm-leds { + compatible = "pwm-leds"; + + red { + /* SYS-LED 1 - Tricolor */ + function = LED_FUNCTION_INDICATOR; + color = <LED_COLOR_ID_RED>; + pwms = <&pwm 0 50000 0>; + max-brightness = <255>; + }; + + green { + /* SYS-LED 1 - Tricolor */ + function = LED_FUNCTION_POWER; + color = <LED_COLOR_ID_GREEN>; + pwms = <&pwm 1 50000 0>; + max-brightness = <255>; + }; + + blue { + /* SYS-LED 1 - Tricolor */ + function = LED_FUNCTION_INDICATOR; + color = <LED_COLOR_ID_BLUE>; + pwms = <&pwm 2 50000 0>; + max-brightness = <255>; + }; + }; + + i2c { + /* + * The platform provided I2C does not budge. + * This is a replacement until I can figure + * out what are the missing bits... + */ + + compatible = "i2c-gpio"; + sda-gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>; + scl-gpios = <&chipcommon 4 GPIO_ACTIVE_HIGH>; + i2c-gpio,delay-us = <10>; /* close to 100 kHz */ + #address-cells = <1>; + #size-cells = <0>; + + current_sense: ina219@45 { + compatible = "ti,ina219"; + reg = <0x45>; + shunt-resistor = <60000>; /* = 60 mOhms */ + }; + + eeprom: eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + read-only; + }; + }; +}; + +&uart0 { + clock-frequency = <62500000>; + /delete-property/ clocks; +}; + +&uart1 { + status = "disabled"; +}; + +&uart2 { + status = "okay"; + /* + * bluetooth-le { + * compatible = "brcm,bcm20732"; + * enable-gpios = <&chipcommon 20 GPIO_ACTIVE_HIGH>; + *}; + */ +}; + +&gmac1 { + status = "disabled"; +}; +&gmac2 { + status = "disabled"; +}; +&gmac3 { + status = "disabled"; +}; + +&pwm { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinmux_pwm>; +}; + +&nandcs { + nand-ecc-algo = "hw"; + + partitions { + /* + * The partition autodetection does not work for this device. + * It will only detect the "nvram" partition with an incorrect size. + * [ 1.721667] 1 bcm47xxpart partitions found on MTD device brcmnand.0 + * [ 1.727962] Creating 1 MTD partitions on "brcmnand.0": + * [ 1.733117] 0x000000400000-0x000008000000 : "nvram" + */ + + compatible = "fixed-partitions"; + #address-cells = <0x1>; + #size-cells = <0x1>; + + partition0@0 { + label = "u-boot"; + reg = <0x0 0x100000>; + read-only; + }; + + partition1@100000 { + label = "bootkernel1"; + reg = <0x100000 0x300000>; + read-only; + }; + + partition2@400000 { + label = "nvram"; + reg = <0x400000 0x100000>; + read-only; + }; + + partition3@500000 { + label = "bootkernel2"; + reg = <0x500000 0x300000>; + read-only; + }; + + partition4@800000 { + label = "ubi"; + reg = <0x800000 0x7780000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi index 0016720ce530..ac3a99cf2079 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/bcm5301x.dtsi @@ -252,6 +252,10 @@ reg = <0x00013000 0x1000>; }; + pcie2: pcie@14000 { + reg = <0x00014000 0x1000>; + }; + usb2: usb2@21000 { reg = <0x00021000 0x1000>; @@ -350,6 +354,14 @@ }; }; + pwm: pwm@18002000 { + compatible = "brcm,iproc-pwm"; + reg = <0x18002000 0x28>; + clocks = <&osc>; + #pwm-cells = <3>; + status = "disabled"; + }; + mdio: mdio@18003000 { compatible = "brcm,iproc-mdio"; reg = <0x18003000 0x8>; @@ -384,6 +396,15 @@ reg = <0x18105000 0x1000>; }; + uart2: serial@18008000 { + compatible = "ns16550a"; + reg = <0x18008000 0x20>; + clocks = <&iprocslow>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + status = "disabled"; + }; + i2c0: i2c@18009000 { compatible = "brcm,iproc-i2c"; reg = <0x18009000 0x50>; @@ -417,12 +438,12 @@ function = "spi"; }; - i2c { + pinmux_i2c: i2c { groups = "i2c_grp"; function = "i2c"; }; - pwm { + pinmux_pwm: pwm { groups = "pwm0_grp", "pwm1_grp", "pwm2_grp", "pwm3_grp"; function = "pwm"; diff --git a/arch/arm/boot/dts/bcm958525xmc.dts b/arch/arm/boot/dts/bcm958525xmc.dts index 716da62f5788..21f922dc6019 100644 --- a/arch/arm/boot/dts/bcm958525xmc.dts +++ b/arch/arm/boot/dts/bcm958525xmc.dts @@ -196,7 +196,7 @@ }; &sdio { - status = "ok"; + status = "okay"; }; &uart0 { diff --git a/arch/arm/boot/dts/bcm958625k.dts b/arch/arm/boot/dts/bcm958625k.dts index 7b84b54436ed..7782b61c51a1 100644 --- a/arch/arm/boot/dts/bcm958625k.dts +++ b/arch/arm/boot/dts/bcm958625k.dts @@ -208,7 +208,7 @@ &sdio { bus-width = <4>; no-1-8-v; - status = "ok"; + status = "okay"; }; &srab { diff --git a/arch/arm/boot/dts/cros-ec-keyboard.dtsi b/arch/arm/boot/dts/cros-ec-keyboard.dtsi index 4a0c1037fbc0..165c5bcd510e 100644 --- a/arch/arm/boot/dts/cros-ec-keyboard.dtsi +++ b/arch/arm/boot/dts/cros-ec-keyboard.dtsi @@ -46,6 +46,7 @@ MATRIX_KEY(0x02, 0x09, KEY_F8) MATRIX_KEY(0x02, 0x0a, KEY_YEN) + MATRIX_KEY(0x03, 0x00, KEY_LEFTMETA) MATRIX_KEY(0x03, 0x01, KEY_GRAVE) MATRIX_KEY(0x03, 0x02, KEY_F2) MATRIX_KEY(0x03, 0x03, KEY_5) diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts index a952d934fcf2..38530dbb89a0 100644 --- a/arch/arm/boot/dts/dra7-evm.dts +++ b/arch/arm/boot/dts/dra7-evm.dts @@ -537,24 +537,23 @@ ti,no-idle-on-init; }; -&mac { +&mac_sw { status = "okay"; - dual_emac; }; -&cpsw_emac0 { +&cpsw_port1 { phy-handle = <ðphy0>; phy-mode = "rgmii"; - dual_emac_res_vlan = <1>; + ti,dual-emac-pvid = <1>; }; -&cpsw_emac1 { +&cpsw_port2 { phy-handle = <ðphy1>; phy-mode = "rgmii"; - dual_emac_res_vlan = <2>; + ti,dual-emac-pvid = <2>; }; -&davinci_mdio { +&davinci_mdio_sw { ethphy0: ethernet-phy@2 { reg = <2>; }; @@ -565,7 +564,7 @@ }; &dcan1 { - status = "ok"; + status = "okay"; pinctrl-names = "default", "sleep", "active"; pinctrl-0 = <&dcan1_pins_sleep>; pinctrl-1 = <&dcan1_pins_sleep>; diff --git a/arch/arm/boot/dts/dra7-l4.dtsi b/arch/arm/boot/dts/dra7-l4.dtsi index 27a6a83cc60c..3bf90d9e3335 100644 --- a/arch/arm/boot/dts/dra7-l4.dtsi +++ b/arch/arm/boot/dts/dra7-l4.dtsi @@ -3038,60 +3038,6 @@ */ ti,no-idle; - mac: ethernet@0 { - compatible = "ti,dra7-cpsw","ti,cpsw"; - clocks = <&gmac_main_clk>, <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 25>; - clock-names = "fck", "cpts"; - cpdma_channels = <8>; - ale_entries = <1024>; - bd_ram_size = <0x2000>; - mac_control = <0x20>; - slaves = <2>; - active_slave = <0>; - cpts_clock_mult = <0x784CFE14>; - cpts_clock_shift = <29>; - reg = <0x0 0x1000 - 0x1200 0x2e00>; - #address-cells = <1>; - #size-cells = <1>; - - /* - * rx_thresh_pend - * rx_pend - * tx_pend - * misc_pend - */ - interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>; - ranges = <0 0 0x4000>; - syscon = <&scm_conf>; - status = "disabled"; - - davinci_mdio: mdio@1000 { - compatible = "ti,cpsw-mdio","ti,davinci_mdio"; - clocks = <&gmac_main_clk>; - clock-names = "fck"; - #address-cells = <1>; - #size-cells = <0>; - bus_freq = <1000000>; - reg = <0x1000 0x100>; - }; - - cpsw_emac0: slave@200 { - /* Filled in by U-Boot */ - mac-address = [ 00 00 00 00 00 00 ]; - phys = <&phy_gmii_sel 1>; - }; - - cpsw_emac1: slave@300 { - /* Filled in by U-Boot */ - mac-address = [ 00 00 00 00 00 00 ]; - phys = <&phy_gmii_sel 2>; - }; - }; - mac_sw: switch@0 { compatible = "ti,dra7-cpsw-switch","ti,cpsw-switch"; reg = <0x0 0x4000>; @@ -3561,7 +3507,6 @@ rtctarget: target-module@38000 { /* 0x48838000, ap 29 12.0 */ compatible = "ti,sysc-omap4-simple", "ti,sysc"; - ti,hwmods = "rtcss"; reg = <0x38074 0x4>, <0x38078 0x4>; reg-names = "rev", "sysc"; diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index cca6b123856f..4e1bbc0198eb 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -37,8 +37,8 @@ serial7 = &uart8; serial8 = &uart9; serial9 = &uart10; - ethernet0 = &cpsw_emac0; - ethernet1 = &cpsw_emac1; + ethernet0 = &cpsw_port1; + ethernet1 = &cpsw_port2; d_can0 = &dcan1; d_can1 = &dcan2; spi0 = &qspi; diff --git a/arch/arm/boot/dts/dra71-evm.dts b/arch/arm/boot/dts/dra71-evm.dts index 10da51bee42f..cad58f733bd6 100644 --- a/arch/arm/boot/dts/dra71-evm.dts +++ b/arch/arm/boot/dts/dra71-evm.dts @@ -219,26 +219,26 @@ vqmmc-supply = <&evm_1v8_sw>; }; -&mac { +&mac_sw { mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_LOW>, <&pcf_hdmi 9 GPIO_ACTIVE_LOW>, /* P11 */ <&pcf_hdmi 10 GPIO_ACTIVE_LOW>; /* P12 */ - dual_emac; + status = "okay"; }; -&cpsw_emac0 { +&cpsw_port1 { phy-handle = <&dp83867_0>; phy-mode = "rgmii-id"; - dual_emac_res_vlan = <1>; + ti,dual-emac-pvid = <1>; }; -&cpsw_emac1 { +&cpsw_port2 { phy-handle = <&dp83867_1>; phy-mode = "rgmii-id"; - dual_emac_res_vlan = <2>; + ti,dual-emac-pvid = <2>; }; -&davinci_mdio { +&davinci_mdio_sw { dp83867_0: ethernet-phy@2 { reg = <2>; ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; diff --git a/arch/arm/boot/dts/dra72-evm-common.dtsi b/arch/arm/boot/dts/dra72-evm-common.dtsi index 9273a7d6fa29..b65b2dd094d0 100644 --- a/arch/arm/boot/dts/dra72-evm-common.dtsi +++ b/arch/arm/boot/dts/dra72-evm-common.dtsi @@ -462,12 +462,8 @@ }; }; -&mac { - status = "okay"; -}; - &dcan1 { - status = "ok"; + status = "okay"; pinctrl-names = "default", "sleep", "active"; pinctrl-0 = <&dcan1_pins_sleep>; pinctrl-1 = <&dcan1_pins_sleep>; @@ -536,11 +532,11 @@ }; &dss { - status = "ok"; + status = "okay"; }; &hdmi { - status = "ok"; + status = "okay"; port { hdmi_out: endpoint { diff --git a/arch/arm/boot/dts/dra72-evm-revc.dts b/arch/arm/boot/dts/dra72-evm-revc.dts index 54dab0f212d1..f242b937f88c 100644 --- a/arch/arm/boot/dts/dra72-evm-revc.dts +++ b/arch/arm/boot/dts/dra72-evm-revc.dts @@ -77,26 +77,26 @@ interrupts = <30 IRQ_TYPE_EDGE_FALLING>; }; -&mac { +&mac_sw { mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_LOW>, <&pcf_hdmi 9 GPIO_ACTIVE_LOW>, /* P11 */ <&pcf_hdmi 10 GPIO_ACTIVE_LOW>; /* P12 */ - dual_emac; + status = "okay"; }; -&cpsw_emac0 { +&cpsw_port1 { phy-handle = <&dp83867_0>; phy-mode = "rgmii-id"; - dual_emac_res_vlan = <1>; + ti,dual-emac-pvid = <1>; }; -&cpsw_emac1 { +&cpsw_port2 { phy-handle = <&dp83867_1>; phy-mode = "rgmii-id"; - dual_emac_res_vlan = <2>; + ti,dual-emac-pvid = <2>; }; -&davinci_mdio { +&davinci_mdio_sw { dp83867_0: ethernet-phy@2 { reg = <2>; ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts index 6ea9936f7d9c..5f62f92eb96c 100644 --- a/arch/arm/boot/dts/dra72-evm.dts +++ b/arch/arm/boot/dts/dra72-evm.dts @@ -69,17 +69,22 @@ interrupts = <11 IRQ_TYPE_EDGE_FALLING>; }; -&mac { - slaves = <1>; +&mac_sw { mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_HIGH>; + status = "okay"; }; -&cpsw_emac0 { +&cpsw_port1 { phy-handle = <ðphy0>; phy-mode = "rgmii"; + ti,dual-emac-pvid = <1>; +}; + +&cpsw_port2 { + status = "disabled"; }; -&davinci_mdio { +&davinci_mdio_sw { ethphy0: ethernet-phy@3 { reg = <3>; }; diff --git a/arch/arm/boot/dts/dra76-evm.dts b/arch/arm/boot/dts/dra76-evm.dts index 803981cc762e..9bd01ae40b1d 100644 --- a/arch/arm/boot/dts/dra76-evm.dts +++ b/arch/arm/boot/dts/dra76-evm.dts @@ -475,25 +475,23 @@ status = "disabled"; }; -&mac { +&mac_sw { status = "okay"; - - dual_emac; }; -&cpsw_emac0 { +&cpsw_port1 { phy-handle = <&dp83867_0>; phy-mode = "rgmii-id"; - dual_emac_res_vlan = <1>; + ti,dual-emac-pvid = <1>; }; -&cpsw_emac1 { +&cpsw_port2 { phy-handle = <&dp83867_1>; phy-mode = "rgmii-id"; - dual_emac_res_vlan = <2>; + ti,dual-emac-pvid = <2>; }; -&davinci_mdio { +&davinci_mdio_sw { dp83867_0: ethernet-phy@2 { reg = <2>; ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; @@ -522,12 +520,12 @@ }; &dss { - status = "ok"; + status = "okay"; vdda_video-supply = <&ldo5_reg>; }; &hdmi { - status = "ok"; + status = "okay"; vdda-supply = <&ldo1_reg>; diff --git a/arch/arm/boot/dts/emev2.dtsi b/arch/arm/boot/dts/emev2.dtsi index 96678ddbb4e6..ecfaa0b7523e 100644 --- a/arch/arm/boot/dts/emev2.dtsi +++ b/arch/arm/boot/dts/emev2.dtsi @@ -195,7 +195,7 @@ clock-names = "sclk"; }; - pfc: pin-controller@e0140200 { + pfc: pinctrl@e0140200 { compatible = "renesas,pfc-emev2"; reg = <0xe0140200 0x100>; }; diff --git a/arch/arm/boot/dts/ethernut5.dts b/arch/arm/boot/dts/ethernut5.dts index 052a52f947ce..ad7a0850252a 100644 --- a/arch/arm/boot/dts/ethernut5.dts +++ b/arch/arm/boot/dts/ethernut5.dts @@ -15,7 +15,7 @@ bootargs = "console=ttyS0,115200 root=/dev/mtdblock0 rw rootfstype=jffs2"; }; - memory { + memory@20000000 { reg = <0x20000000 0x08000000>; }; diff --git a/arch/arm/boot/dts/exynos3250-artik5.dtsi b/arch/arm/boot/dts/exynos3250-artik5.dtsi index 6c2f320be2f4..12887b3924af 100644 --- a/arch/arm/boot/dts/exynos3250-artik5.dtsi +++ b/arch/arm/boot/dts/exynos3250-artik5.dtsi @@ -55,6 +55,10 @@ assigned-clock-rates = <6000000>; }; +&cmu { + clocks = <&xusbxti>; +}; + &cpu0 { cpu0-supply = <&buck2_reg>; }; diff --git a/arch/arm/boot/dts/exynos3250-monk.dts b/arch/arm/boot/dts/exynos3250-monk.dts index ca29d7ed8216..c1a68e612037 100644 --- a/arch/arm/boot/dts/exynos3250-monk.dts +++ b/arch/arm/boot/dts/exynos3250-monk.dts @@ -26,7 +26,7 @@ memory@40000000 { device_type = "memory"; - reg = <0x40000000 0x1ff00000>; + reg = <0x40000000 0x1ff00000>; }; firmware@205f000 { @@ -164,6 +164,10 @@ status = "okay"; }; +&cmu { + clocks = <&xusbxti>; +}; + &cpu0 { cpu0-supply = <&buck2_reg>; }; diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts b/arch/arm/boot/dts/exynos3250-rinato.dts index aba8350cfdaf..b55afaaa691e 100644 --- a/arch/arm/boot/dts/exynos3250-rinato.dts +++ b/arch/arm/boot/dts/exynos3250-rinato.dts @@ -30,7 +30,7 @@ memory@40000000 { device_type = "memory"; - reg = <0x40000000 0x1ff00000>; + reg = <0x40000000 0x1ff00000>; }; firmware@205f000 { @@ -205,6 +205,10 @@ status = "okay"; }; +&cmu { + clocks = <&xusbxti>; +}; + &cpu0 { cpu0-supply = <&buck2_reg>; }; diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi index d3fb45a56527..a1e93fb7f694 100644 --- a/arch/arm/boot/dts/exynos3250.dtsi +++ b/arch/arm/boot/dts/exynos3250.dtsi @@ -97,33 +97,25 @@ }; }; - fixed-rate-clocks { - #address-cells = <1>; - #size-cells = <0>; - - xusbxti: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - clock-frequency = <0>; - #clock-cells = <0>; - clock-output-names = "xusbxti"; - }; + xusbxti: clock-0 { + compatible = "fixed-clock"; + clock-frequency = <0>; + #clock-cells = <0>; + clock-output-names = "xusbxti"; + }; - xxti: clock@1 { - compatible = "fixed-clock"; - reg = <1>; - clock-frequency = <0>; - #clock-cells = <0>; - clock-output-names = "xxti"; - }; + xxti: clock-1 { + compatible = "fixed-clock"; + clock-frequency = <0>; + #clock-cells = <0>; + clock-output-names = "xxti"; + }; - xtcxo: clock@2 { - compatible = "fixed-clock"; - reg = <2>; - clock-frequency = <0>; - #clock-cells = <0>; - clock-output-names = "xtcxo"; - }; + xtcxo: clock-2 { + compatible = "fixed-clock"; + clock-frequency = <0>; + #clock-cells = <0>; + clock-output-names = "xtcxo"; }; pmu { @@ -362,7 +354,7 @@ }; hsotg: hsotg@12480000 { - compatible = "samsung,s3c6400-hsotg", "snps,dwc2"; + compatible = "samsung,s3c6400-hsotg"; reg = <0x12480000 0x20000>; interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cmu CLK_USBOTG>; diff --git a/arch/arm/boot/dts/exynos4210-i9100.dts b/arch/arm/boot/dts/exynos4210-i9100.dts index 6d0c04d77a39..5370ee477186 100644 --- a/arch/arm/boot/dts/exynos4210-i9100.dts +++ b/arch/arm/boot/dts/exynos4210-i9100.dts @@ -123,7 +123,7 @@ reset-gpios = <&gpl1 2 GPIO_ACTIVE_LOW>; }; - i2c_max17042_fuel: i2c-gpio { + i2c_max17042_fuel: i2c-gpio-0 { compatible = "i2c-gpio"; #address-cells = <1>; #size-cells = <0>; @@ -147,7 +147,7 @@ }; }; - spi-lcd { + spi-3 { compatible = "spi-gpio"; #address-cells = <1>; #size-cells = <0>; @@ -209,20 +209,12 @@ compatible = "samsung,clock-xusbxti"; clock-frequency = <24000000>; }; - }; - thermal-zones { - cpu_thermal: cpu-thermal { - cooling-maps { - map0 { - /* Corresponds to 800MHz */ - cooling-device = <&cpu0 2 2>; - }; - map1 { - /* Corresponds to 200MHz */ - cooling-device = <&cpu0 4 4>; - }; - }; + pmic_ap_clk: pmic-ap-clk { + /* Workaround for missing clock on max8997 PMIC */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; }; }; }; @@ -235,6 +227,19 @@ cpu0-supply = <&varm_breg>; }; +&cpu_thermal { + cooling-maps { + map0 { + /* Corresponds to 800MHz */ + cooling-device = <&cpu0 2 2>; + }; + map1 { + /* Corresponds to 200MHz */ + cooling-device = <&cpu0 4 4>; + }; + }; +}; + &ehci { status = "okay"; @@ -304,8 +309,6 @@ status = "okay"; mali-supply = <&vg3d_breg>; - regulator-microvolt-offset = <50000>; - regulator-microsecs-delay = <50>; }; &hsotg { @@ -524,6 +527,7 @@ regulator-name = "G3D_1.1V"; regulator-min-microvolt = <900000>; regulator-max-microvolt = <1200000>; + regulator-microvolt-offset = <50000>; regulator-always-on; }; @@ -569,6 +573,16 @@ regulator-max-microvolt = <4100000>; regulator-always-on; }; + + EN32KHZ_AP { + regulator-name = "EN32KHZ_AP"; + regulator-always-on; + }; + + EN32KHZ_CP { + regulator-name = "EN32KHZ_CP"; + regulator-always-on; + }; }; }; }; @@ -667,7 +681,7 @@ samsung,pin-val = <0>; }; - mag_mhl_gpio: mag-mhl-gpio { + mag_mhl_gpio: mag-mhl { samsung,pins = "gpd0-2"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; @@ -689,6 +703,12 @@ }; }; +&rtc { + status = "okay"; + clocks = <&clock CLK_RTC>, <&pmic_ap_clk>; + clock-names = "rtc", "rtc_src"; +}; + &sdhci_0 { status = "okay"; diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts index 890525b10d22..7d2cfbafefb2 100644 --- a/arch/arm/boot/dts/exynos4210-origen.dts +++ b/arch/arm/boot/dts/exynos4210-origen.dts @@ -100,6 +100,13 @@ compatible = "samsung,clock-xusbxti"; clock-frequency = <24000000>; }; + + pmic_ap_clk: pmic-ap-clk { + /* Workaround for missing clock on max8997 PMIC */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; }; display-timings { @@ -122,6 +129,19 @@ cpu0-supply = <&buck1_reg>; }; +&cpu_thermal { + cooling-maps { + map0 { + /* Corresponds to 800MHz */ + cooling-device = <&cpu0 2 2>; + }; + map1 { + /* Corresponds to 200MHz */ + cooling-device = <&cpu0 4 4>; + }; + }; +}; + &exynos_usbphy { status = "okay"; }; @@ -286,6 +306,11 @@ regulator-boot-on; regulator-always-on; }; + + EN32KHZ_AP { + regulator-name = "EN32KHZ_AP"; + regulator-always-on; + }; }; }; }; @@ -331,6 +356,8 @@ &rtc { status = "okay"; + clocks = <&clock CLK_RTC>, <&pmic_ap_clk>; + clock-names = "rtc", "rtc_src"; }; &tmu { diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts b/arch/arm/boot/dts/exynos4210-smdkv310.dts index 77fc11e593ad..c5609afa6101 100644 --- a/arch/arm/boot/dts/exynos4210-smdkv310.dts +++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts @@ -40,6 +40,26 @@ compatible = "samsung,clock-xusbxti"; clock-frequency = <24000000>; }; + + pmic_ap_clk: pmic-ap-clk { + /* Workaround for missing clock on PMIC */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; +}; + +&cpu_thermal { + cooling-maps { + map0 { + /* Corresponds to 800MHz */ + cooling-device = <&cpu0 2 2>; + }; + map1 { + /* Corresponds to 200MHz */ + cooling-device = <&cpu0 4 4>; + }; }; }; @@ -148,6 +168,11 @@ }; }; +&rtc { + clocks = <&clock CLK_RTC>, <&pmic_ap_clk>; + clock-names = "rtc", "rtc_src"; +}; + &sdhci_2 { bus-width = <4>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts index 5cc96f04a4fa..a226bec56a45 100644 --- a/arch/arm/boot/dts/exynos4210-trats.dts +++ b/arch/arm/boot/dts/exynos4210-trats.dts @@ -132,23 +132,14 @@ compatible = "samsung,clock-xusbxti"; clock-frequency = <24000000>; }; - }; - thermal-zones { - cpu_thermal: cpu-thermal { - cooling-maps { - map0 { - /* Corresponds to 800MHz at freq_table */ - cooling-device = <&cpu0 2 2>, <&cpu1 2 2>; - }; - map1 { - /* Corresponds to 200MHz at freq_table */ - cooling-device = <&cpu0 4 4>, <&cpu1 4 4>; - }; - }; + pmic_ap_clk: pmic-ap-clk { + /* Workaround for missing clock on max8997 PMIC */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; }; }; - }; &camera { @@ -161,6 +152,19 @@ cpu0-supply = <&varm_breg>; }; +&cpu_thermal { + cooling-maps { + map0 { + /* Corresponds to 800MHz at freq_table */ + cooling-device = <&cpu0 2 2>, <&cpu1 2 2>; + }; + map1 { + /* Corresponds to 200MHz at freq_table */ + cooling-device = <&cpu0 4 4>, <&cpu1 4 4>; + }; + }; +}; + &dsi_0 { vddcore-supply = <&vusb_reg>; vddio-supply = <&vmipi_reg>; @@ -314,140 +318,156 @@ regulators { valive_reg: LDO2 { - regulator-name = "VALIVE_1.1V_C210"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; + regulator-name = "VALIVE_1.1V_C210"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; }; vusb_reg: LDO3 { - regulator-name = "VUSB_1.1V_C210"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; + regulator-name = "VUSB_1.1V_C210"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; }; vmipi_reg: LDO4 { - regulator-name = "VMIPI_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; + regulator-name = "VMIPI_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; }; vpda_reg: LDO6 { - regulator-name = "VCC_1.8V_PDA"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; + regulator-name = "VCC_1.8V_PDA"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; }; vcam_reg: LDO7 { - regulator-name = "CAM_ISP_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; + regulator-name = "CAM_ISP_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; }; vusbdac_reg: LDO8 { - regulator-name = "VUSB+VDAC_3.3V_C210"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; + regulator-name = "VUSB+VDAC_3.3V_C210"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; }; vccpda_reg: LDO9 { - regulator-name = "VCC_2.8V_PDA"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; + regulator-name = "VCC_2.8V_PDA"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; }; vpll_reg: LDO10 { - regulator-name = "VPLL_1.1V_C210"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; + regulator-name = "VPLL_1.1V_C210"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; }; vtcam_reg: LDO12 { - regulator-name = "VT_CAM_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; + regulator-name = "VT_CAM_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; }; vcclcd_reg: LDO13 { - regulator-name = "VCC_3.3V_LCD"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; + regulator-name = "VCC_3.3V_LCD"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; }; vlcd_reg: LDO15 { - regulator-name = "VLCD_2.2V"; - regulator-min-microvolt = <2200000>; - regulator-max-microvolt = <2200000>; + regulator-name = "VLCD_2.2V"; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2200000>; }; camsensor_reg: LDO16 { - regulator-name = "CAM_SENSOR_IO_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; + regulator-name = "CAM_SENSOR_IO_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; }; tflash_reg: LDO17 { - regulator-name = "VTF_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; + regulator-name = "VTF_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; }; vddq_reg: LDO21 { - regulator-name = "VDDQ_M1M2_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; + regulator-name = "VDDQ_M1M2_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; }; varm_breg: BUCK1 { - regulator-name = "VARM_1.2V_C210"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; + regulator-name = "VARM_1.2V_C210"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; }; vint_breg: BUCK2 { - regulator-name = "VINT_1.1V_C210"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; + regulator-name = "VINT_1.1V_C210"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; }; camisp_breg: BUCK4 { - regulator-name = "CAM_ISP_CORE_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; + regulator-name = "CAM_ISP_CORE_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; }; vmem_breg: BUCK5 { - regulator-name = "VMEM_1.2V_C210"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; + regulator-name = "VMEM_1.2V_C210"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; }; vccsub_breg: BUCK7 { - regulator-name = "VCC_SUB_2.0V"; - regulator-min-microvolt = <2000000>; - regulator-max-microvolt = <2000000>; - regulator-always-on; + regulator-name = "VCC_SUB_2.0V"; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-always-on; }; safe1_sreg: ESAFEOUT1 { - regulator-name = "SAFEOUT1"; + regulator-name = "SAFEOUT1"; }; safe2_sreg: ESAFEOUT2 { - regulator-name = "SAFEOUT2"; - regulator-boot-on; + regulator-name = "SAFEOUT2"; + regulator-boot-on; + }; + + EN32KHZ_AP { + regulator-name = "EN32KHZ_AP"; + regulator-always-on; + }; + + EN32KHZ_CP { + regulator-name = "EN32KHZ_CP"; + regulator-always-on; }; }; }; }; +&rtc { + status = "okay"; + clocks = <&clock CLK_RTC>, <&pmic_ap_clk>; + clock-names = "rtc", "rtc_src"; +}; + &sdhci_0 { bus-width = <8>; non-removable; diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts index 99ce53b120ac..08284e8f3624 100644 --- a/arch/arm/boot/dts/exynos4210-universal_c210.dts +++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts @@ -39,10 +39,17 @@ compatible = "samsung,clock-xusbxti"; clock-frequency = <24000000>; }; + + pmic_ap_clk: pmic-ap-clk { + /* Workaround for missing clock on PMIC */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; }; vemmc_reg: voltage-regulator { - compatible = "regulator-fixed"; + compatible = "regulator-fixed"; regulator-name = "VMEM_VDD_2_8V"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; @@ -104,7 +111,7 @@ }; tsp_reg: voltage-regulator { - compatible = "regulator-fixed"; + compatible = "regulator-fixed"; regulator-name = "TSP_2_8V"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; @@ -112,13 +119,13 @@ enable-active-high; }; - spi-lcd { + spi-3 { compatible = "spi-gpio"; #address-cells = <1>; #size-cells = <0>; - gpio-sck = <&gpy3 1 GPIO_ACTIVE_HIGH>; - gpio-mosi = <&gpy3 3 GPIO_ACTIVE_HIGH>; + sck-gpios = <&gpy3 1 GPIO_ACTIVE_HIGH>; + mosi-gpios = <&gpy3 3 GPIO_ACTIVE_HIGH>; num-chipselects = <1>; cs-gpios = <&gpy4 3 GPIO_ACTIVE_LOW>; @@ -192,6 +199,19 @@ cpu0-supply = <&vdd_arm_reg>; }; +&cpu_thermal { + cooling-maps { + map0 { + /* Corresponds to 800MHz */ + cooling-device = <&cpu0 2 2>; + }; + map1 { + /* Corresponds to 200MHz */ + cooling-device = <&cpu0 4 4>; + }; + }; +}; + &ehci { status = "okay"; phys = <&exynos_usbphy 1>; @@ -537,6 +557,12 @@ status = "okay"; }; +&rtc { + status = "okay"; + clocks = <&clock CLK_RTC>, <&pmic_ap_clk>; + clock-names = "rtc", "rtc_src"; +}; + &sdhci_0 { bus-width = <8>; non-removable; diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index 33435ce79ce4..fddc661ded28 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -102,6 +102,8 @@ reg = <0x10502000 0x1000>; cache-unified; cache-level = <2>; + prefetch-data = <1>; + prefetch-instr = <1>; arm,tag-latency = <2 2 1>; arm,data-latency = <2 2 1>; }; @@ -363,26 +365,24 @@ }; }; }; +}; - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tmu 0>; - - trips { - cpu_alert0: cpu-alert-0 { - temperature = <85000>; /* millicelsius */ - }; - cpu_alert1: cpu-alert-1 { - temperature = <100000>; /* millicelsius */ - }; - cpu_alert2: cpu-alert-2 { - temperature = <110000>; /* millicelsius */ - }; - }; - }; - }; +&cpu_alert0 { + temperature = <85000>; /* millicelsius */ +}; + +&cpu_alert1 { + temperature = <100000>; /* millicelsius */ +}; + +&cpu_alert2 { + temperature = <110000>; /* millicelsius */ +}; + +&cpu_thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmu 0>; }; &gic { diff --git a/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi b/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi index 53b3ca3effab..89ed81fb348d 100644 --- a/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi +++ b/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi @@ -33,7 +33,7 @@ }; }; - lcd_vdd3_reg: voltage-regulator-7 { + lcd_vdd3_reg: voltage-regulator-10 { compatible = "regulator-fixed"; regulator-name = "LCD_VDD_2.2V"; regulator-min-microvolt = <2200000>; @@ -42,7 +42,7 @@ enable-active-high; }; - ps_als_reg: voltage-regulator-8 { + ps_als_reg: voltage-regulator-11 { compatible = "regulator-fixed"; regulator-name = "LED_A_3.0V"; regulator-min-microvolt = <3000000>; @@ -171,6 +171,44 @@ status = "okay"; }; +&sound { + samsung,audio-routing = + "HP", "HPOUT1L", + "HP", "HPOUT1R", + + "SPK", "SPKOUTLN", + "SPK", "SPKOUTLP", + "SPK", "SPKOUTRN", + "SPK", "SPKOUTRP", + + "RCV", "HPOUT2N", + "RCV", "HPOUT2P", + + "HDMI", "LINEOUT1N", + "HDMI", "LINEOUT1P", + + "LINE", "LINEOUT2N", + "LINE", "LINEOUT2P", + + "IN1LP", "MICBIAS1", + "IN1LN", "MICBIAS1", + "Main Mic", "MICBIAS1", + + "IN1RP", "Sub Mic", + "IN1RN", "Sub Mic", + + "IN2LP:VXRN", "MICBIAS2", + "Headset Mic", "MICBIAS2", + + "IN2RN", "FM In", + "IN2RP:VXRP", "FM In"; +}; + +&submic_bias_reg { + gpio = <&gpf2 0 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; + &touchkey_reg { gpio = <&gpm0 0 GPIO_ACTIVE_HIGH>; status = "okay"; diff --git a/arch/arm/boot/dts/exynos4412-i9300.dts b/arch/arm/boot/dts/exynos4412-i9300.dts index f8125a945f8d..07fbcf845c49 100644 --- a/arch/arm/boot/dts/exynos4412-i9300.dts +++ b/arch/arm/boot/dts/exynos4412-i9300.dts @@ -17,6 +17,10 @@ memory@40000000 { device_type = "memory"; - reg = <0x40000000 0x40000000>; + reg = <0x40000000 0x40000000>; }; }; + +&sound { + fm-sel-gpios = <&gpl0 3 GPIO_ACTIVE_HIGH>; +}; diff --git a/arch/arm/boot/dts/exynos4412-i9305.dts b/arch/arm/boot/dts/exynos4412-i9305.dts index 54a2a55dbf70..6bc3d897f432 100644 --- a/arch/arm/boot/dts/exynos4412-i9305.dts +++ b/arch/arm/boot/dts/exynos4412-i9305.dts @@ -10,7 +10,7 @@ memory@40000000 { device_type = "memory"; - reg = <0x40000000 0x80000000>; + reg = <0x40000000 0x80000000>; }; }; diff --git a/arch/arm/boot/dts/exynos4412-midas.dtsi b/arch/arm/boot/dts/exynos4412-midas.dtsi index 2c8111c6b065..7e7c243ff196 100644 --- a/arch/arm/boot/dts/exynos4412-midas.dtsi +++ b/arch/arm/boot/dts/exynos4412-midas.dtsi @@ -37,12 +37,12 @@ fixed-rate-clocks { xxti { - compatible = "samsung,clock-xxti", "fixed-clock"; + compatible = "samsung,clock-xxti"; clock-frequency = <0>; }; xusbxti { - compatible = "samsung,clock-xusbxti", "fixed-clock"; + compatible = "samsung,clock-xusbxti"; clock-frequency = <24000000>; }; }; @@ -102,6 +102,30 @@ status = "disabled"; }; + vbatt_reg: voltage-regulator-7 { + compatible = "regulator-fixed"; + regulator-name = "VBATT"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + mic_bias_reg: voltage-regulator-8 { + compatible = "regulator-fixed"; + regulator-name = "MICBIAS_LDO_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpf1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + submic_bias_reg: voltage-regulator-9 { + compatible = "regulator-fixed"; + regulator-name = "SUB_MICBIAS_LDO_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; @@ -266,16 +290,18 @@ clock-names = "ext_clock"; }; - sound { - compatible = "samsung,trats2-audio"; - samsung,i2s-controller = <&i2s0>; - samsung,model = "Trats2"; - samsung,audio-codec = <&wm1811>; - samsung,audio-routing = - "SPK", "SPKOUTLN", - "SPK", "SPKOUTLP", - "SPK", "SPKOUTRN", - "SPK", "SPKOUTRP"; + sound: sound { + compatible = "samsung,midas-audio"; + model = "Midas"; + mic-bias-supply = <&mic_bias_reg>; + submic-bias-supply = <&submic_bias_reg>; + + cpu { + sound-dai = <&i2s0 0>; + }; + codec { + sound-dai = <&wm1811>; + }; }; thermistor-ap { @@ -293,25 +319,6 @@ pulldown-ohm = <100000>; /* 100K */ io-channels = <&adc 2>; /* Battery temperature */ }; - - thermal-zones { - cpu_thermal: cpu-thermal { - cooling-maps { - map0 { - /* Corresponds to 800MHz at freq_table */ - cooling-device = <&cpu0 7 7>, <&cpu1 7 7>, - <&cpu2 7 7>, <&cpu3 7 7>; - }; - map1 { - /* Corresponds to 200MHz at freq_table */ - cooling-device = <&cpu0 13 13>, - <&cpu1 13 13>, - <&cpu2 13 13>, - <&cpu3 13 13>; - }; - }; - }; - }; }; &adc { @@ -380,6 +387,21 @@ cpu0-supply = <&buck2_reg>; }; +&cpu_thermal { + cooling-maps { + map0 { + /* Corresponds to 800MHz at freq_table */ + cooling-device = <&cpu0 7 7>, <&cpu1 7 7>, + <&cpu2 7 7>, <&cpu3 7 7>; + }; + map1 { + /* Corresponds to 200MHz at freq_table */ + cooling-device = <&cpu0 13 13>, <&cpu1 13 13>, + <&cpu2 13 13>, <&cpu3 13 13>; + }; + }; +}; + &csis_0 { status = "okay"; vddcore-supply = <&ldo8_reg>; @@ -597,11 +619,37 @@ wm1811: wm1811@1a { compatible = "wlf,wm1811"; reg = <0x1a>; - clocks = <&pmu_system_controller 0>; - clock-names = "MCLK1"; - DCVDD-supply = <&ldo3_reg>; + clocks = <&pmu_system_controller 0>, + <&max77686 MAX77686_CLK_PMIC>; + clock-names = "MCLK1", "MCLK2"; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gpx3>; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH>; + + gpio-controller; + #gpio-cells = <2>; + #sound-dai-cells = <0>; + + wlf,gpio-cfg = <0x3 0x0 0x0 0x0 0x0 0x0 + 0x0 0x8000 0x0 0x0 0x0>; + wlf,micbias-cfg = <0x2f 0x2b>; + + wlf,lineout1-feedback; + wlf,lineout1-se; + wlf,lineout2-se; + wlf,ldoena-always-driven; + + AVDD2-supply = <&vbatt_reg>; DBVDD1-supply = <&ldo3_reg>; + DBVDD2-supply = <&vbatt_reg>; + DBVDD3-supply = <&vbatt_reg>; + DCVDD-supply = <&ldo3_reg>; + CPVDD-supply = <&vbatt_reg>; + SPKVDD1-supply = <&vbatt_reg>; + SPKVDD2-supply = <&vbatt_reg>; wlf,ldo1ena = <&gpj0 4 0>; + wlf,ldo2ena = <&gpj0 4 0>; }; }; diff --git a/arch/arm/boot/dts/exynos4412-n710x.dts b/arch/arm/boot/dts/exynos4412-n710x.dts index 4189e1fb204c..a47b7f35fc80 100644 --- a/arch/arm/boot/dts/exynos4412-n710x.dts +++ b/arch/arm/boot/dts/exynos4412-n710x.dts @@ -8,12 +8,12 @@ memory@40000000 { device_type = "memory"; - reg = <0x40000000 0x80000000>; + reg = <0x40000000 0x80000000>; }; /* bootargs are passed in by bootloader */ - cam_vdda_reg: voltage-regulator-7 { + cam_vdda_reg: voltage-regulator-10 { compatible = "regulator-fixed"; regulator-name = "CAM_SENSOR_CORE_1.2V"; regulator-min-microvolt = <1200000>; @@ -74,6 +74,41 @@ status = "okay"; }; +&sound { + samsung,audio-routing = + "HP", "HPOUT1L", + "HP", "HPOUT1R", + + "SPK", "SPKOUTLN", + "SPK", "SPKOUTLP", + + "RCV", "HPOUT2N", + "RCV", "HPOUT2P", + + "HDMI", "LINEOUT1N", + "HDMI", "LINEOUT1P", + + "LINE", "LINEOUT2N", + "LINE", "LINEOUT2P", + + "IN1LP", "MICBIAS2", + "IN1LN", "MICBIAS2", + "Headset Mic", "MICBIAS2", + + "IN1RP", "Sub Mic", + "IN1RN", "Sub Mic", + + "IN2LP:VXRN", "Main Mic", + "IN2LN", "Main Mic", + + "IN2RN", "FM In", + "IN2RP:VXRP", "FM In"; +}; + +&submic_bias_reg { + regulator-always-on; +}; + &touchkey_reg { gpio = <&gpm0 5 GPIO_ACTIVE_HIGH>; status = "okay"; diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi index a5c1ce1e396c..2983e91bc7dd 100644 --- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi +++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi @@ -66,25 +66,6 @@ clock-frequency = <24000000>; }; }; - - thermal-zones { - cpu_thermal: cpu-thermal { - cooling-maps { - cooling_map0: map0 { - /* Corresponds to 800MHz at freq_table */ - cooling-device = <&cpu0 7 7>, <&cpu1 7 7>, - <&cpu2 7 7>, <&cpu3 7 7>; - }; - cooling_map1: map1 { - /* Corresponds to 200MHz at freq_table */ - cooling-device = <&cpu0 13 13>, - <&cpu1 13 13>, - <&cpu2 13 13>, - <&cpu3 13 13>; - }; - }; - }; - }; }; &bus_dmc { @@ -174,6 +155,21 @@ }; }; +&cpu_thermal { + cooling-maps { + cooling_map0: map0 { + /* Corresponds to 800MHz at freq_table */ + cooling-device = <&cpu0 7 7>, <&cpu1 7 7>, + <&cpu2 7 7>, <&cpu3 7 7>; + }; + cooling_map1: map1 { + /* Corresponds to 200MHz at freq_table */ + cooling-device = <&cpu0 13 13>, <&cpu1 13 13>, + <&cpu2 13 13>, <&cpu3 13 13>; + }; + }; +}; + &pinctrl_1 { gpio_power_key: power_key { samsung,pins = "gpx1-3"; diff --git a/arch/arm/boot/dts/exynos4412-odroidu3.dts b/arch/arm/boot/dts/exynos4412-odroidu3.dts index 8ff243ba4542..b8549d846f86 100644 --- a/arch/arm/boot/dts/exynos4412-odroidu3.dts +++ b/arch/arm/boot/dts/exynos4412-odroidu3.dts @@ -37,31 +37,6 @@ #cooling-cells = <2>; cooling-levels = <0 102 170 230>; }; - - thermal-zones { - cpu_thermal: cpu-thermal { - cooling-maps { - map0 { - trip = <&cpu_alert1>; - cooling-device = <&cpu0 9 9>, <&cpu1 9 9>, - <&cpu2 9 9>, <&cpu3 9 9>, - <&fan0 1 2>; - }; - map1 { - trip = <&cpu_alert2>; - cooling-device = <&cpu0 15 15>, - <&cpu1 15 15>, - <&cpu2 15 15>, - <&cpu3 15 15>, - <&fan0 2 3>; - }; - map2 { - trip = <&cpu_alert0>; - cooling-device = <&fan0 0 1>; - }; - }; - }; - }; }; &adc { @@ -76,6 +51,27 @@ regulator-max-microvolt = <3300000>; }; +&cpu_thermal { + cooling-maps { + map0 { + trip = <&cpu_alert1>; + cooling-device = <&cpu0 9 9>, <&cpu1 9 9>, + <&cpu2 9 9>, <&cpu3 9 9>, + <&fan0 1 2>; + }; + map1 { + trip = <&cpu_alert2>; + cooling-device = <&cpu0 15 15>, <&cpu1 15 15>, + <&cpu2 15 15>, <&cpu3 15 15>, + <&fan0 2 3>; + }; + map2 { + trip = <&cpu_alert0>; + cooling-device = <&fan0 0 1>; + }; + }; +}; + &hdmicec { needs-hpd; }; diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts index 8b11ad391252..c2e793b69e7d 100644 --- a/arch/arm/boot/dts/exynos4412-origen.dts +++ b/arch/arm/boot/dts/exynos4412-origen.dts @@ -11,6 +11,7 @@ /dts-v1/; #include "exynos4412.dtsi" +#include <dt-bindings/clock/samsung,s2mps11.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> #include "exynos-mfc-reserved-memory.dtsi" @@ -74,6 +75,21 @@ cpu0-supply = <&buck2_reg>; }; +&cpu_thermal { + cooling-maps { + cooling_map0: map0 { + /* Corresponds to 800MHz at freq_table */ + cooling-device = <&cpu0 7 7>, <&cpu1 7 7>, + <&cpu2 7 7>, <&cpu3 7 7>; + }; + cooling_map1: map1 { + /* Corresponds to 200MHz at freq_table */ + cooling-device = <&cpu0 13 13>, <&cpu1 13 13>, + <&cpu2 13 13>, <&cpu3 13 13>; + }; + }; +}; + &exynos_usbphy { status = "okay"; }; @@ -129,6 +145,13 @@ <1200000>, <1200000>, <1200000>, <1200000>; + s5m8767_osc: clocks { + compatible = "samsung,s5m8767-clk"; + #clock-cells = <1>; + clock-output-names = "s5m8767_ap", "s5m8767_cp", + "s5m8767_bt"; + }; + regulators { ldo1_reg: LDO1 { regulator-name = "VDD_ALIVE"; @@ -499,6 +522,8 @@ &rtc { status = "okay"; + clocks = <&clock CLK_RTC>, <&s5m8767_osc S2MPS11_CLK_AP>; + clock-names = "rtc", "rtc_src"; }; &sdhci_2 { diff --git a/arch/arm/boot/dts/exynos4412-smdk4412.dts b/arch/arm/boot/dts/exynos4412-smdk4412.dts index e70fb6e601f0..49971203a8aa 100644 --- a/arch/arm/boot/dts/exynos4412-smdk4412.dts +++ b/arch/arm/boot/dts/exynos4412-smdk4412.dts @@ -37,6 +37,28 @@ compatible = "samsung,clock-xusbxti"; clock-frequency = <24000000>; }; + + pmic_ap_clk: pmic-ap-clk { + /* Workaround for missing clock on PMIC */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; +}; + +&cpu_thermal { + cooling-maps { + cooling_map0: map0 { + /* Corresponds to 800MHz at freq_table */ + cooling-device = <&cpu0 7 7>, <&cpu1 7 7>, + <&cpu2 7 7>, <&cpu3 7 7>; + }; + cooling_map1: map1 { + /* Corresponds to 200MHz at freq_table */ + cooling-device = <&cpu0 13 13>, <&cpu1 13 13>, + <&cpu2 13 13>, <&cpu3 13 13>; + }; }; }; @@ -127,6 +149,11 @@ }; }; +&rtc { + clocks = <&clock CLK_RTC>, <&pmic_ap_clk>; + clock-names = "rtc", "rtc_src"; +}; + &sdhci_2 { bus-width = <4>; pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>; diff --git a/arch/arm/boot/dts/exynos4412-tiny4412.dts b/arch/arm/boot/dts/exynos4412-tiny4412.dts index 3a91de8a8082..017b26108bb0 100644 --- a/arch/arm/boot/dts/exynos4412-tiny4412.dts +++ b/arch/arm/boot/dts/exynos4412-tiny4412.dts @@ -65,6 +65,13 @@ compatible = "samsung,clock-xusbxti"; clock-frequency = <24000000>; }; + + pmic_ap_clk: pmic-ap-clk { + /* Workaround for missing clock on PMIC */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; }; panel { @@ -78,6 +85,21 @@ }; }; +&cpu_thermal { + cooling-maps { + cooling_map0: map0 { + /* Corresponds to 800MHz at freq_table */ + cooling-device = <&cpu0 7 7>, <&cpu1 7 7>, + <&cpu2 7 7>, <&cpu3 7 7>; + }; + cooling_map1: map1 { + /* Corresponds to 200MHz at freq_table */ + cooling-device = <&cpu0 13 13>, <&cpu1 13 13>, + <&cpu2 13 13>, <&cpu3 13 13>; + }; + }; +}; + &fimd { pinctrl-0 = <&lcd_clk>, <&lcd_data24>; pinctrl-names = "default"; @@ -95,6 +117,8 @@ &rtc { status = "okay"; + clocks = <&clock CLK_RTC>, <&pmic_ap_clk>; + clock-names = "rtc", "rtc_src"; }; &sdhci_2 { diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts index aac533933c61..7b447b63007e 100644 --- a/arch/arm/boot/dts/exynos4412-trats2.dts +++ b/arch/arm/boot/dts/exynos4412-trats2.dts @@ -18,7 +18,7 @@ memory@40000000 { device_type = "memory"; - reg = <0x40000000 0x40000000>; + reg = <0x40000000 0x40000000>; }; chosen { diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi index 7002832eb4c0..e76881dc0014 100644 --- a/arch/arm/boot/dts/exynos4412.dtsi +++ b/arch/arm/boot/dts/exynos4412.dtsi @@ -76,7 +76,7 @@ }; }; - cpu0_opp_table: opp_table0 { + cpu0_opp_table: opp-table0 { compatible = "operating-points-v2"; opp-shared; @@ -218,6 +218,8 @@ reg = <0x10502000 0x1000>; cache-unified; cache-level = <2>; + prefetch-data = <1>; + prefetch-instr = <1>; arm,tag-latency = <2 2 1>; arm,data-latency = <3 2 1>; arm,double-linefill = <1>; @@ -400,7 +402,7 @@ status = "disabled"; }; - bus_dmc_opp_table: opp_table1 { + bus_dmc_opp_table: opp-table1 { compatible = "operating-points-v2"; opp-shared; @@ -427,7 +429,7 @@ }; }; - bus_acp_opp_table: opp_table2 { + bus_acp_opp_table: opp-table2 { compatible = "operating-points-v2"; opp-shared; @@ -493,7 +495,7 @@ status = "disabled"; }; - bus_leftbus_opp_table: opp_table3 { + bus_leftbus_opp_table: opp-table3 { compatible = "operating-points-v2"; opp-shared; @@ -516,7 +518,7 @@ }; }; - bus_display_opp_table: opp_table4 { + bus_display_opp_table: opp-table4 { compatible = "operating-points-v2"; opp-shared; @@ -528,7 +530,7 @@ }; }; - bus_fsys_opp_table: opp_table5 { + bus_fsys_opp_table: opp-table5 { compatible = "operating-points-v2"; opp-shared; @@ -540,7 +542,7 @@ }; }; - bus_peri_opp_table: opp_table6 { + bus_peri_opp_table: opp-table6 { compatible = "operating-points-v2"; opp-shared; @@ -732,7 +734,7 @@ "pmu"; operating-points-v2 = <&gpu_opp_table>; - gpu_opp_table: opp_table { + gpu_opp_table: opp-table { compatible = "operating-points-v2"; opp-160000000 { diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi index 22eb951c614c..9ce9fb3fc190 100644 --- a/arch/arm/boot/dts/exynos5.dtsi +++ b/arch/arm/boot/dts/exynos5.dtsi @@ -86,7 +86,7 @@ }; gic: interrupt-controller@10481000 { - compatible = "arm,gic-400", "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + compatible = "arm,gic-400", "arm,cortex-a15-gic"; #interrupt-cells = <3>; interrupt-controller; reg = <0x10481000 0x1000>, @@ -211,13 +211,13 @@ }; prng: rng@10830400 { - compatible = "samsung,exynos5250-prng"; - reg = <0x10830400 0x200>; + compatible = "samsung,exynos5250-prng"; + reg = <0x10830400 0x200>; }; trng: rng@10830600 { - compatible = "samsung,exynos5250-trng"; - reg = <0x10830600 0x100>; + compatible = "samsung,exynos5250-trng"; + reg = <0x10830600 0x100>; }; g2d: g2d@10850000 { diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index 59872d83da6e..79546f11af26 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts @@ -243,11 +243,11 @@ s5m8767,pmic-buck3-dvs-voltage = <1100000>; s5m8767,pmic-buck4-dvs-voltage = <1200000>; s5m8767,pmic-buck-dvs-gpios = <&gpd1 0 GPIO_ACTIVE_HIGH>, - <&gpd1 1 GPIO_ACTIVE_HIGH>, - <&gpd1 2 GPIO_ACTIVE_HIGH>; + <&gpd1 1 GPIO_ACTIVE_HIGH>, + <&gpd1 2 GPIO_ACTIVE_HIGH>; s5m8767,pmic-buck-ds-gpios = <&gpx2 3 GPIO_ACTIVE_HIGH>, - <&gpx2 4 GPIO_ACTIVE_HIGH>, - <&gpx2 5 GPIO_ACTIVE_HIGH>; + <&gpx2 4 GPIO_ACTIVE_HIGH>, + <&gpx2 5 GPIO_ACTIVE_HIGH>; s5m8767_osc: clocks { compatible = "samsung,s5m8767-clk"; @@ -542,12 +542,6 @@ status = "okay"; samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <40000>; - samsung,i2c-slave-addr = <0x38>; - - sata_phy_i2c:sata-phy@38 { - compatible = "samsung,exynos-sataphy-i2c"; - reg = <0x38>; - }; }; &i2s0 { @@ -619,12 +613,16 @@ samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>; }; +&sata_phy_i2c { + status = "okay"; +}; + &soc { /* * For unknown reasons HDMI-DDC does not work with Exynos I2C * controllers. Lets use software I2C over GPIO pins as a workaround. */ - i2c_ddc: i2c-gpio { + i2c_ddc: i2c-10 { pinctrl-names = "default"; pinctrl-0 = <&i2c2_gpio_bus>; status = "okay"; diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts index 5c42df024adf..186790f39e4d 100644 --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts @@ -7,6 +7,7 @@ */ /dts-v1/; +#include <dt-bindings/clock/maxim,max77686.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> #include "exynos5250.dtsi" @@ -129,13 +130,14 @@ reg = <0x50>; }; - max77686@9 { + max77686: pmic@9 { compatible = "maxim,max77686"; reg = <0x09>; interrupt-parent = <&gpx3>; interrupts = <2 IRQ_TYPE_NONE>; pinctrl-names = "default"; pinctrl-0 = <&max77686_irq>; + #clock-cells = <1>; wakeup-source; voltage-regulators { @@ -324,12 +326,6 @@ status = "okay"; samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <40000>; - samsung,i2c-slave-addr = <0x38>; - - sata_phy_i2c: sata-phy@38 { - compatible = "samsung,exynos-sataphy-i2c"; - reg = <0x38>; - }; }; &i2s0 { @@ -368,6 +364,8 @@ &rtc { status = "okay"; + clocks = <&clock CLK_RTC>, <&max77686 MAX77686_CLK_AP>; + clock-names = "rtc", "rtc_src"; }; &sata { @@ -379,6 +377,10 @@ samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>; }; +&sata_phy_i2c { + status = "okay"; +}; + &spi_1 { status = "okay"; cs-gpios = <&gpa2 5 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/exynos5250-spring.dts b/arch/arm/boot/dts/exynos5250-spring.dts index 3d501926c227..a92ade33779c 100644 --- a/arch/arm/boot/dts/exynos5250-spring.dts +++ b/arch/arm/boot/dts/exynos5250-spring.dts @@ -7,6 +7,7 @@ */ /dts-v1/; +#include <dt-bindings/clock/samsung,s2mps11.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/input/input.h> @@ -114,12 +115,12 @@ wakeup-source; s5m8767,pmic-buck-dvs-gpios = <&gpd1 0 GPIO_ACTIVE_LOW>, /* DVS1 */ - <&gpd1 1 GPIO_ACTIVE_LOW>, /* DVS2 */ - <&gpd1 2 GPIO_ACTIVE_LOW>; /* DVS3 */ + <&gpd1 1 GPIO_ACTIVE_LOW>, /* DVS2 */ + <&gpd1 2 GPIO_ACTIVE_LOW>; /* DVS3 */ s5m8767,pmic-buck-ds-gpios = <&gpx2 3 GPIO_ACTIVE_LOW>, /* SET1 */ - <&gpx2 4 GPIO_ACTIVE_LOW>, /* SET2 */ - <&gpx2 5 GPIO_ACTIVE_LOW>; /* SET3 */ + <&gpx2 4 GPIO_ACTIVE_LOW>, /* SET2 */ + <&gpx2 5 GPIO_ACTIVE_LOW>; /* SET3 */ /* * The following arrays of DVS voltages are not used, since we are @@ -127,26 +128,26 @@ * to please the driver. */ s5m8767,pmic-buck2-dvs-voltage = <1350000>, <1300000>, - <1250000>, <1200000>, - <1150000>, <1100000>, - <1000000>, <950000>; + <1250000>, <1200000>, + <1150000>, <1100000>, + <1000000>, <950000>; s5m8767,pmic-buck3-dvs-voltage = <1100000>, <1100000>, - <1100000>, <1100000>, - <1000000>, <1000000>, - <1000000>, <1000000>; + <1100000>, <1100000>, + <1000000>, <1000000>, + <1000000>, <1000000>; s5m8767,pmic-buck4-dvs-voltage = <1200000>, <1200000>, - <1200000>, <1200000>, - <1200000>, <1200000>, - <1200000>, <1200000>; + <1200000>, <1200000>, + <1200000>, <1200000>, + <1200000>, <1200000>; - clocks { + s5m8767_osc: clocks { compatible = "samsung,s5m8767-clk"; #clock-cells = <1>; clock-output-names = "en32khz_ap", - "en32khz_cp", - "en32khz_bt"; + "en32khz_cp", + "en32khz_bt"; }; regulators { @@ -456,7 +457,7 @@ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; - dp_hpd_gpio: dp-hpd-gpio { + dp_hpd_gpio: dp-hpd { samsung,pins = "gpc3-0"; samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; @@ -522,6 +523,12 @@ }; }; +&rtc { + status = "okay"; + clocks = <&clock CLK_RTC>, <&s5m8767_osc S2MPS11_CLK_AP>; + clock-names = "rtc", "rtc_src"; +}; + &sd1_bus4 { samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index e3dbe4166836..bd2d8835dd36 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -330,7 +330,7 @@ power-domains = <&pd_g3d>; status = "disabled"; - gpu_opp_table: gpu-opp-table { + gpu_opp_table: opp-table { compatible = "operating-points-v2"; opp-100000000 { @@ -473,6 +473,12 @@ clocks = <&clock CLK_SATA_PHYI2C>; clock-names = "i2c"; status = "disabled"; + + sata_phy_i2c: sata-phy-i2c@38 { + compatible = "samsung,exynos-sataphy-i2c"; + reg = <0x38>; + status = "disabled"; + }; }; spi_0: spi@12d20000 { @@ -723,7 +729,7 @@ #dma-requests = <1>; }; - gsc_0: gsc@13e00000 { + gsc_0: gsc@13e00000 { compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc"; reg = <0x13e00000 0x1000>; interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; @@ -733,7 +739,7 @@ iommus = <&sysmmu_gsc0>; }; - gsc_1: gsc@13e10000 { + gsc_1: gsc@13e10000 { compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc"; reg = <0x13e10000 0x1000>; interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; @@ -743,7 +749,7 @@ iommus = <&sysmmu_gsc1>; }; - gsc_2: gsc@13e20000 { + gsc_2: gsc@13e20000 { compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc"; reg = <0x13e20000 0x1000>; interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; @@ -753,7 +759,7 @@ iommus = <&sysmmu_gsc2>; }; - gsc_3: gsc@13e30000 { + gsc_3: gsc@13e30000 { compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc"; reg = <0x13e30000 0x1000>; interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; @@ -1085,26 +1091,6 @@ }; }; - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tmu 0>; - - cooling-maps { - map0 { - /* Corresponds to 800MHz at freq_table */ - cooling-device = <&cpu0 9 9>, <&cpu1 9 9>; - }; - map1 { - /* Corresponds to 200MHz at freq_table */ - cooling-device = <&cpu0 15 15>, - <&cpu1 15 15>; - }; - }; - }; - }; - timer { compatible = "arm,armv7-timer"; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, @@ -1120,6 +1106,24 @@ }; }; +&cpu_thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmu 0>; + + cooling-maps { + map0 { + /* Corresponds to 800MHz at freq_table */ + cooling-device = <&cpu0 9 9>, <&cpu1 9 9>; + }; + map1 { + /* Corresponds to 200MHz at freq_table */ + cooling-device = <&cpu0 15 15>, + <&cpu1 15 15>; + }; + }; +}; + &dp { power-domains = <&pd_disp1>; clocks = <&clock CLK_DP>; diff --git a/arch/arm/boot/dts/exynos5260.dtsi b/arch/arm/boot/dts/exynos5260.dtsi index 154df70128f3..973448c4ad93 100644 --- a/arch/arm/boot/dts/exynos5260.dtsi +++ b/arch/arm/boot/dts/exynos5260.dtsi @@ -162,10 +162,8 @@ }; gic: interrupt-controller@10481000 { - compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + compatible = "arm,gic-400", "arm,cortex-a15-gic"; #interrupt-cells = <3>; - #address-cells = <0>; - #size-cells = <0>; interrupt-controller; reg = <0x10481000 0x1000>, <0x10482000 0x2000>, diff --git a/arch/arm/boot/dts/exynos5410-odroidxu.dts b/arch/arm/boot/dts/exynos5410-odroidxu.dts index 4f9297ae0763..75b4150c26d7 100644 --- a/arch/arm/boot/dts/exynos5410-odroidxu.dts +++ b/arch/arm/boot/dts/exynos5410-odroidxu.dts @@ -109,10 +109,10 @@ assigned-clock-parents = <&clock CLK_FOUT_EPLL>, <&clock_audss EXYNOS_MOUT_AUDSS>; - assigned-clock-rates = <0>, - <0>, - <96000000>, - <19200000>; + assigned-clock-rates = <0>, + <0>, + <96000000>, + <19200000>; }; &cpu0_thermal { diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts b/arch/arm/boot/dts/exynos5410-smdk5410.dts index 5282b5deca86..2a3ade77a2de 100644 --- a/arch/arm/boot/dts/exynos5410-smdk5410.dts +++ b/arch/arm/boot/dts/exynos5410-smdk5410.dts @@ -29,6 +29,13 @@ #clock-cells = <0>; }; + pmic_ap_clk: pmic-ap-clk { + /* Workaround for missing PMIC and its clock */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + firmware@2037000 { compatible = "samsung,secure-firmware"; reg = <0x02037000 0x1000>; @@ -79,6 +86,11 @@ }; }; +&rtc { + clocks = <&clock CLK_RTC>, <&pmic_ap_clk>; + clock-names = "rtc", "rtc_src"; +}; + &sromc { pinctrl-names = "default"; pinctrl-0 = <&srom_ctl>, <&srom_ebi>; diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi index abe75b9e39f5..60a87684b1af 100644 --- a/arch/arm/boot/dts/exynos5410.dtsi +++ b/arch/arm/boot/dts/exynos5410.dtsi @@ -238,16 +238,16 @@ #include "exynos5420-trip-points.dtsi" }; cpu1_thermal: cpu1-thermal { - thermal-sensors = <&tmu_cpu1>; - #include "exynos5420-trip-points.dtsi" + thermal-sensors = <&tmu_cpu1>; + #include "exynos5420-trip-points.dtsi" }; cpu2_thermal: cpu2-thermal { - thermal-sensors = <&tmu_cpu2>; - #include "exynos5420-trip-points.dtsi" + thermal-sensors = <&tmu_cpu2>; + #include "exynos5420-trip-points.dtsi" }; cpu3_thermal: cpu3-thermal { - thermal-sensors = <&tmu_cpu3>; - #include "exynos5420-trip-points.dtsi" + thermal-sensors = <&tmu_cpu3>; + #include "exynos5420-trip-points.dtsi" }; }; }; diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts index 83fa800fa1eb..4e49d8095b29 100644 --- a/arch/arm/boot/dts/exynos5420-smdk5420.dts +++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts @@ -9,6 +9,7 @@ /dts-v1/; #include "exynos5420.dtsi" #include "exynos5420-cpus.dtsi" +#include <dt-bindings/clock/samsung,s2mps11.h> #include <dt-bindings/gpio/gpio.h> / { @@ -401,6 +402,8 @@ &rtc { status = "okay"; + clocks = <&clock CLK_RTC>, <&s2mps11_osc S2MPS11_CLK_AP>; + clock-names = "rtc", "rtc_src"; }; &usbdrd_phy0 { diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index c76460b70532..83580f076a58 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -1199,20 +1199,20 @@ #include "exynos5420-trip-points.dtsi" }; cpu1_thermal: cpu1-thermal { - thermal-sensors = <&tmu_cpu1>; - #include "exynos5420-trip-points.dtsi" + thermal-sensors = <&tmu_cpu1>; + #include "exynos5420-trip-points.dtsi" }; cpu2_thermal: cpu2-thermal { - thermal-sensors = <&tmu_cpu2>; - #include "exynos5420-trip-points.dtsi" + thermal-sensors = <&tmu_cpu2>; + #include "exynos5420-trip-points.dtsi" }; cpu3_thermal: cpu3-thermal { - thermal-sensors = <&tmu_cpu3>; - #include "exynos5420-trip-points.dtsi" + thermal-sensors = <&tmu_cpu3>; + #include "exynos5420-trip-points.dtsi" }; gpu_thermal: gpu-thermal { - thermal-sensors = <&tmu_gpu>; - #include "exynos5420-trip-points.dtsi" + thermal-sensors = <&tmu_gpu>; + #include "exynos5420-trip-points.dtsi" }; }; }; diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi index afe090578e8f..b1cf9414ce17 100644 --- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi @@ -333,8 +333,8 @@ compatible = "samsung,K3QF2F20DB", "jedec,lpddr3"; density = <16384>; io-width = <32>; - #address-cells = <1>; - #size-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; tRFC-min-tck = <17>; tRRD-min-tck = <2>; diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi index c3c2d85267da..b5ec4f47eb3a 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi @@ -29,30 +29,6 @@ "HiFi Playback", "Mixer DAI TX", "Mixer DAI RX", "HiFi Capture"; - assigned-clocks = <&clock CLK_MOUT_EPLL>, - <&clock CLK_MOUT_MAU_EPLL>, - <&clock CLK_MOUT_USER_MAU_EPLL>, - <&clock_audss EXYNOS_MOUT_AUDSS>, - <&clock_audss EXYNOS_MOUT_I2S>, - <&clock_audss EXYNOS_DOUT_SRP>, - <&clock_audss EXYNOS_DOUT_AUD_BUS>, - <&clock_audss EXYNOS_DOUT_I2S>; - - assigned-clock-parents = <&clock CLK_FOUT_EPLL>, - <&clock CLK_MOUT_EPLL>, - <&clock CLK_MOUT_MAU_EPLL>, - <&clock CLK_MAU_EPLL>, - <&clock_audss EXYNOS_MOUT_AUDSS>; - - assigned-clock-rates = <0>, - <0>, - <0>, - <0>, - <0>, - <196608001>, - <(196608002 / 2)>, - <196608000>; - cpu { sound-dai = <&i2s0 0>, <&i2s0 1>; }; @@ -62,13 +38,6 @@ }; }; -&clock_audss { - assigned-clocks = <&clock_audss EXYNOS_DOUT_SRP>, - <&clock CLK_FOUT_EPLL>; - assigned-clock-rates = <(196608000 / 256)>, - <196608000>; -}; - &hsi2c_5 { status = "okay"; max98090: max98090@10 { @@ -84,6 +53,31 @@ &i2s0 { status = "okay"; - assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>; - assigned-clock-parents = <&clock_audss EXYNOS_SCLK_I2S>; + assigned-clocks = <&clock CLK_MOUT_EPLL>, + <&clock CLK_MOUT_MAU_EPLL>, + <&clock CLK_MOUT_USER_MAU_EPLL>, + <&clock_audss EXYNOS_MOUT_AUDSS>, + <&clock_audss EXYNOS_MOUT_I2S>, + <&i2s0 CLK_I2S_RCLK_SRC>, + <&clock_audss EXYNOS_DOUT_SRP>, + <&clock_audss EXYNOS_DOUT_AUD_BUS>, + <&clock_audss EXYNOS_DOUT_I2S>; + + assigned-clock-parents = <&clock CLK_FOUT_EPLL>, + <&clock CLK_MOUT_EPLL>, + <&clock CLK_MOUT_MAU_EPLL>, + <&clock CLK_MAU_EPLL>, + <&clock_audss EXYNOS_MOUT_AUDSS>, + <&clock_audss EXYNOS_SCLK_I2S>; + + assigned-clock-rates = <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <196608001>, + <(196608002 / 2)>, + <196608000>; + }; diff --git a/arch/arm/boot/dts/exynos5422-odroidxu4.dts b/arch/arm/boot/dts/exynos5422-odroidxu4.dts index 892d389d6d09..ddd55d3bcadd 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu4.dts +++ b/arch/arm/boot/dts/exynos5422-odroidxu4.dts @@ -35,30 +35,6 @@ samsung,audio-routing = "I2S Playback", "Mixer DAI TX"; - assigned-clocks = <&clock CLK_MOUT_EPLL>, - <&clock CLK_MOUT_MAU_EPLL>, - <&clock CLK_MOUT_USER_MAU_EPLL>, - <&clock_audss EXYNOS_MOUT_AUDSS>, - <&clock_audss EXYNOS_MOUT_I2S>, - <&clock_audss EXYNOS_DOUT_SRP>, - <&clock_audss EXYNOS_DOUT_AUD_BUS>, - <&clock_audss EXYNOS_DOUT_I2S>; - - assigned-clock-parents = <&clock CLK_FOUT_EPLL>, - <&clock CLK_MOUT_EPLL>, - <&clock CLK_MOUT_MAU_EPLL>, - <&clock CLK_MAU_EPLL>, - <&clock_audss EXYNOS_MOUT_AUDSS>; - - assigned-clock-rates = <0>, - <0>, - <0>, - <0>, - <0>, - <196608001>, - <(196608002 / 2)>, - <196608000>; - cpu { sound-dai = <&i2s0 0>, <&i2s0 1>; }; @@ -69,17 +45,35 @@ }; }; -&clock_audss { - assigned-clocks = <&clock_audss EXYNOS_DOUT_SRP>, - <&clock CLK_FOUT_EPLL>; - assigned-clock-rates = <(196608000 / 256)>, - <196608000>; -}; - &i2s0 { status = "okay"; - assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>; - assigned-clock-parents = <&clock_audss EXYNOS_SCLK_I2S>; + + assigned-clocks = <&clock CLK_MOUT_EPLL>, + <&clock CLK_MOUT_MAU_EPLL>, + <&clock CLK_MOUT_USER_MAU_EPLL>, + <&clock_audss EXYNOS_MOUT_AUDSS>, + <&clock_audss EXYNOS_MOUT_I2S>, + <&i2s0 CLK_I2S_RCLK_SRC>, + <&clock_audss EXYNOS_DOUT_SRP>, + <&clock_audss EXYNOS_DOUT_AUD_BUS>, + <&clock_audss EXYNOS_DOUT_I2S>; + + assigned-clock-parents = <&clock CLK_FOUT_EPLL>, + <&clock CLK_MOUT_EPLL>, + <&clock CLK_MOUT_MAU_EPLL>, + <&clock CLK_MAU_EPLL>, + <&clock_audss EXYNOS_MOUT_AUDSS>, + <&clock_audss EXYNOS_SCLK_I2S>; + + assigned-clock-rates = <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <196608001>, + <(196608002 / 2)>, + <196608000>; }; &pwm { diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi index f0af1bf2b4d8..f683440ee569 100644 --- a/arch/arm/boot/dts/hi3620.dtsi +++ b/arch/arm/boot/dts/hi3620.dtsi @@ -89,7 +89,7 @@ }; sysctrl: system-controller@802000 { - compatible = "hisilicon,sysctrl"; + compatible = "hisilicon,sysctrl", "syscon"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x802000 0x1000>; @@ -111,8 +111,10 @@ reg = <0x800000 0x1000>; /* timer00 & timer01 */ interrupts = <0 0 4>, <0 1 4>; - clocks = <&clock HI3620_TIMER0_MUX>, <&clock HI3620_TIMER1_MUX>; - clock-names = "apb_pclk"; + clocks = <&clock HI3620_TIMER0_MUX>, + <&clock HI3620_TIMER1_MUX>, + <&clock HI3620_TIMER0_MUX>; + clock-names = "timer0clk", "timer1clk", "apb_pclk"; status = "disabled"; }; @@ -121,8 +123,10 @@ reg = <0x801000 0x1000>; /* timer10 & timer11 */ interrupts = <0 2 4>, <0 3 4>; - clocks = <&clock HI3620_TIMER2_MUX>, <&clock HI3620_TIMER3_MUX>; - clock-names = "apb_pclk"; + clocks = <&clock HI3620_TIMER2_MUX>, + <&clock HI3620_TIMER3_MUX>, + <&clock HI3620_TIMER2_MUX>; + clock-names = "timer0clk", "timer1clk", "apb_pclk"; status = "disabled"; }; @@ -131,8 +135,10 @@ reg = <0xa01000 0x1000>; /* timer20 & timer21 */ interrupts = <0 4 4>, <0 5 4>; - clocks = <&clock HI3620_TIMER4_MUX>, <&clock HI3620_TIMER5_MUX>; - clock-names = "apb_pclk"; + clocks = <&clock HI3620_TIMER4_MUX>, + <&clock HI3620_TIMER5_MUX>, + <&clock HI3620_TIMER4_MUX>; + clock-names = "timer0lck", "timer1clk", "apb_pclk"; status = "disabled"; }; @@ -141,8 +147,10 @@ reg = <0xa02000 0x1000>; /* timer30 & timer31 */ interrupts = <0 6 4>, <0 7 4>; - clocks = <&clock HI3620_TIMER6_MUX>, <&clock HI3620_TIMER7_MUX>; - clock-names = "apb_pclk"; + clocks = <&clock HI3620_TIMER6_MUX>, + <&clock HI3620_TIMER7_MUX>, + <&clock HI3620_TIMER6_MUX>; + clock-names = "timer0clk", "timer1clk", "apb_pclk"; status = "disabled"; }; @@ -151,8 +159,10 @@ reg = <0xa03000 0x1000>; /* timer40 & timer41 */ interrupts = <0 96 4>, <0 97 4>; - clocks = <&clock HI3620_TIMER8_MUX>, <&clock HI3620_TIMER9_MUX>; - clock-names = "apb_pclk"; + clocks = <&clock HI3620_TIMER8_MUX>, + <&clock HI3620_TIMER9_MUX>, + <&clock HI3620_TIMER8_MUX>; + clock-names = "timer0clk", "timer1clk", "apb_pclk"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/hip04.dtsi b/arch/arm/boot/dts/hip04.dtsi index 4263a9339c2e..555bc6b6720f 100644 --- a/arch/arm/boot/dts/hip04.dtsi +++ b/arch/arm/boot/dts/hip04.dtsi @@ -213,7 +213,7 @@ }; sysctrl: sysctrl { - compatible = "hisilicon,sysctrl"; + compatible = "hisilicon,sysctrl", "syscon"; reg = <0x3e00000 0x00100000>; }; @@ -226,8 +226,8 @@ compatible = "arm,sp804", "arm,primecell"; reg = <0x3000000 0x1000>; interrupts = <0 224 4>; - clocks = <&clk_50m>, <&clk_50m>; - clock-names = "apb_pclk"; + clocks = <&clk_50m>, <&clk_50m>, <&clk_50m>; + clock-names = "timer0clk", "timer1clk", "apb_pclk"; }; arm-pmu { diff --git a/arch/arm/boot/dts/hisi-x5hd2.dtsi b/arch/arm/boot/dts/hisi-x5hd2.dtsi index 3ee7967c202d..e2dbf1d8a67b 100644 --- a/arch/arm/boot/dts/hisi-x5hd2.dtsi +++ b/arch/arm/boot/dts/hisi-x5hd2.dtsi @@ -370,8 +370,9 @@ arm,primecell-periphid = <0x00141805>; reg = <0xa2c000 0x1000>; interrupts = <0 29 4>; - clocks = <&clock HIX5HD2_WDG0_RST>; - clock-names = "apb_pclk"; + clocks = <&clock HIX5HD2_WDG0_RST>, + <&clock HIX5HD2_WDG0_RST>; + clock-names = "wdog_clk", "apb_pclk"; }; }; diff --git a/arch/arm/boot/dts/imx23-evk.dts b/arch/arm/boot/dts/imx23-evk.dts index 0b2701ca2921..8cbaf1c81174 100644 --- a/arch/arm/boot/dts/imx23-evk.dts +++ b/arch/arm/boot/dts/imx23-evk.dts @@ -53,7 +53,7 @@ apb@80000000 { apbh@80000000 { - gpmi-nand@8000c000 { + nand-controller@8000c000 { pinctrl-names = "default"; pinctrl-0 = <&gpmi_pins_a &gpmi_pins_fixup>; status = "okay"; diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi index 18289f6fb1f3..7f4c602454a5 100644 --- a/arch/arm/boot/dts/imx23.dtsi +++ b/arch/arm/boot/dts/imx23.dtsi @@ -76,7 +76,7 @@ status = "disabled"; }; - gpmi-nand@8000c000 { + nand-controller@8000c000 { compatible = "fsl,imx23-gpmi-nand"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/imx25-pinfunc.h b/arch/arm/boot/dts/imx25-pinfunc.h index 111bfdcbe552..f984b702efc5 100644 --- a/arch/arm/boot/dts/imx25-pinfunc.h +++ b/arch/arm/boot/dts/imx25-pinfunc.h @@ -87,6 +87,7 @@ #define MX25_PAD_EB1__EB1 0x044 0x25c 0x000 0x00 0x000 #define MX25_PAD_EB1__AUD4_RXD 0x044 0x25c 0x460 0x04 0x000 #define MX25_PAD_EB1__GPIO_2_13 0x044 0x25c 0x000 0x05 0x000 +#define MX25_PAD_EB1__CSPI3_SS1 0x044 0x25c 0x4c0 0x06 0x000 #define MX25_PAD_OE__OE 0x048 0x260 0x000 0x00 0x000 #define MX25_PAD_OE__AUD4_TXC 0x048 0x260 0x000 0x04 0x000 @@ -112,6 +113,7 @@ #define MX25_PAD_CS5__CSPI3_MISO 0x058 0x268 0x4b4 0x06 0x000 #define MX25_PAD_NF_CE0__NF_CE0 0x05c 0x26c 0x000 0x00 0x000 +#define MX25_PAD_NF_CE0__CSPI1_SS3 0x05c 0x26c 0x490 0x01 0x000 #define MX25_PAD_NF_CE0__GPIO_3_22 0x05c 0x26c 0x000 0x05 0x000 #define MX25_PAD_ECB__ECB 0x060 0x270 0x000 0x00 0x000 @@ -122,6 +124,7 @@ #define MX25_PAD_LBA__LBA 0x064 0x274 0x000 0x00 0x000 #define MX25_PAD_LBA__UART5_RXD 0x064 0x274 0x578 0x03 0x000 #define MX25_PAD_LBA__GPIO_3_24 0x064 0x274 0x000 0x05 0x000 +#define MX25_PAD_LBA__CSPI3_RDY 0x064 0x274 0x4b0 0x06 0x000 #define MX25_PAD_BCLK__BCLK 0x068 0x000 0x000 0x00 0x000 #define MX25_PAD_BCLK__GPIO_4_4 0x068 0x000 0x000 0x05 0x000 @@ -285,7 +288,8 @@ #define MX25_PAD_OE_ACD__GPIO_1_25 0x114 0x30c 0x000 0x05 0x000 #define MX25_PAD_CONTRAST__CONTRAST 0x118 0x310 0x000 0x00 0x000 -#define MX25_PAD_CONTRAST__CC4 0x118 0x310 0x000 0x01 0x000 +#define MX25_PAD_CONTRAST__GPT4_CAPIN1 0x118 0x310 0x000 0x01 0x000 +#define MX25_PAD_CONTRAST__CSPI2_SS1 0x118 0x310 0x4a8 0x02 0x000 #define MX25_PAD_CONTRAST__PWM4_PWMO 0x118 0x310 0x000 0x04 0x000 #define MX25_PAD_CONTRAST__FEC_CRS 0x118 0x310 0x508 0x05 0x001 #define MX25_PAD_CONTRAST__USBH2_PWR 0x118 0x310 0x000 0x06 0x000 @@ -298,7 +302,7 @@ #define MX25_PAD_CSI_D2__UART5_RXD 0x120 0x318 0x578 0x01 0x001 #define MX25_PAD_CSI_D2__SIM1_CLK0 0x120 0x318 0x000 0x04 0x000 #define MX25_PAD_CSI_D2__GPIO_1_27 0x120 0x318 0x000 0x05 0x000 -#define MX25_PAD_CSI_D2__CSPI3_MOSI 0x120 0x318 0x000 0x07 0x000 +#define MX25_PAD_CSI_D2__CSPI3_MOSI 0x120 0x318 0x4b8 0x07 0x001 #define MX25_PAD_CSI_D3__CSI_D3 0x124 0x31c 0x000 0x00 0x000 #define MX25_PAD_CSI_D3__UART5_TXD 0x124 0x31c 0x000 0x01 0x000 @@ -310,23 +314,25 @@ #define MX25_PAD_CSI_D4__UART5_RTS 0x128 0x320 0x574 0x01 0x001 #define MX25_PAD_CSI_D4__SIM1_VEN0 0x128 0x320 0x000 0x04 0x000 #define MX25_PAD_CSI_D4__GPIO_1_29 0x128 0x320 0x000 0x05 0x000 -#define MX25_PAD_CSI_D4__CSPI3_SCLK 0x128 0x320 0x000 0x07 0x000 +#define MX25_PAD_CSI_D4__CSPI3_SCLK 0x128 0x320 0x4ac 0x07 0x001 #define MX25_PAD_CSI_D5__CSI_D5 0x12c 0x324 0x000 0x00 0x000 #define MX25_PAD_CSI_D5__UART5_CTS 0x12c 0x324 0x000 0x01 0x000 #define MX25_PAD_CSI_D5__SIM1_TX0 0x12c 0x324 0x000 0x04 0x000 #define MX25_PAD_CSI_D5__GPIO_1_30 0x12c 0x324 0x000 0x05 0x000 -#define MX25_PAD_CSI_D5__CSPI3_RDY 0x12c 0x324 0x000 0x07 0x000 +#define MX25_PAD_CSI_D5__CSPI3_RDY 0x12c 0x324 0x4b0 0x07 0x001 #define MX25_PAD_CSI_D6__CSI_D6 0x130 0x328 0x000 0x00 0x000 /* SION must be set; see the comment for MX25_PAD_SD1_CMD__ESDHC1_CMD. */ #define MX25_PAD_CSI_D6__ESDHC2_CMD 0x130 0x328 0x4e0 0x12 0x001 #define MX25_PAD_CSI_D6__SIM1_PD0 0x130 0x328 0x000 0x04 0x000 #define MX25_PAD_CSI_D6__GPIO_1_31 0x130 0x328 0x000 0x05 0x000 +#define MX25_PAD_CSI_D6__CSPI3_SS0 0x130 0x328 0x4bc 0x07 0x001 #define MX25_PAD_CSI_D7__CSI_D7 0x134 0x32c 0x000 0x00 0x000 #define MX25_PAD_CSI_D7__ESDHC2_CLK 0x134 0x32C 0x4dc 0x02 0x001 #define MX25_PAD_CSI_D7__GPIO_1_6 0x134 0x32c 0x000 0x05 0x000 +#define MX25_PAD_CSI_D7__CSPI3_SS1 0x134 0x32c 0x4c0 0x07 0x001 #define MX25_PAD_CSI_D8__CSI_D8 0x138 0x330 0x000 0x00 0x000 #define MX25_PAD_CSI_D8__AUD6_RXC 0x138 0x330 0x000 0x02 0x000 @@ -398,7 +404,7 @@ #define MX25_PAD_UART1_RTS__UART1_RTS 0x178 0x370 0x000 0x00 0x000 #define MX25_PAD_UART1_RTS__CSI_D0 0x178 0x370 0x488 0x01 0x001 -#define MX25_PAD_UART1_RTS__CC3 0x178 0x370 0x000 0x02 0x000 +#define MX25_PAD_UART1_RTS__GPT3_CAPIN1 0x178 0x370 0x000 0x02 0x000 #define MX25_PAD_UART1_RTS__UART2_DCD 0x178 0x370 0x000 0x03 0x000 #define MX25_PAD_UART1_RTS__GPIO_4_24 0x178 0x370 0x000 0x05 0x000 @@ -415,12 +421,14 @@ #define MX25_PAD_UART2_RTS__UART2_RTS 0x188 0x380 0x000 0x00 0x000 #define MX25_PAD_UART2_RTS__FEC_COL 0x188 0x380 0x504 0x02 0x002 -#define MX25_PAD_UART2_RTS__CC1 0x188 0x380 0x000 0x03 0x000 +#define MX25_PAD_UART2_RTS__GPT1_CAPIN1 0x188 0x380 0x000 0x03 0x000 #define MX25_PAD_UART2_RTS__GPIO_4_28 0x188 0x380 0x000 0x05 0x000 +#define MX25_PAD_UART2_RTS__CSPI2_SS3 0x188 0x380 0x000 0x06 0x000 #define MX25_PAD_UART2_CTS__UART2_CTS 0x18c 0x384 0x000 0x00 0x000 #define MX25_PAD_UART2_CTS__FEC_RX_ERR 0x18c 0x384 0x518 0x02 0x002 #define MX25_PAD_UART2_CTS__GPIO_4_29 0x18c 0x384 0x000 0x05 0x000 +#define MX25_PAD_UART2_CTS__CSPI3_SS3 0x18c 0x384 0x4c8 0x06 0x001 /* * Removing the SION bit from MX25_PAD_*__ESDHCn_CMD breaks detecting an SD @@ -446,14 +454,17 @@ #define MX25_PAD_SD1_DATA0__GPIO_2_25 0x198 0x390 0x000 0x05 0x000 #define MX25_PAD_SD1_DATA1__ESDHC1_DAT1 0x19c 0x394 0x000 0x00 0x000 +#define MX25_PAD_SD1_DATA1__CSPI2_RDY 0x19c 0x394 0x498 0x01 0x001 #define MX25_PAD_SD1_DATA1__AUD7_RXD 0x19c 0x394 0x478 0x03 0x000 #define MX25_PAD_SD1_DATA1__GPIO_2_26 0x19c 0x394 0x000 0x05 0x000 #define MX25_PAD_SD1_DATA2__ESDHC1_DAT2 0x1a0 0x398 0x000 0x00 0x000 +#define MX25_PAD_SD1_DATA2__CSPI2_SS0 0x1a0 0x398 0x4a4 0x01 0x001 #define MX25_PAD_SD1_DATA2__FEC_RX_CLK 0x1a0 0x398 0x514 0x02 0x002 #define MX25_PAD_SD1_DATA2__GPIO_2_27 0x1a0 0x398 0x000 0x05 0x000 #define MX25_PAD_SD1_DATA3__ESDHC1_DAT3 0x1a4 0x39c 0x000 0x00 0x000 +#define MX25_PAD_SD1_DATA3__CSPI2_SS1 0x1a4 0x39c 0x4a8 0x01 0x001 #define MX25_PAD_SD1_DATA3__FEC_CRS 0x1a4 0x39c 0x508 0x02 0x002 #define MX25_PAD_SD1_DATA3__GPIO_2_28 0x1a4 0x39c 0x000 0x05 0x000 @@ -564,11 +575,15 @@ #define MX25_PAD_GPIO_C__PWM4_PWMO 0x1fc 0x3f8 0x000 0x01 0x000 #define MX25_PAD_GPIO_C__I2C2_SCL 0x1fc 0x3f8 0x51c 0x02 0x001 #define MX25_PAD_GPIO_C__KPP_COL4 0x1fc 0x3f8 0x52c 0x03 0x001 +#define MX25_PAD_GPIO_C__GPT2_CAPIN1 0x1fc 0x3f8 0x000 0x04 0x000 +#define MX25_PAD_GPIO_C__CSPI1_SS2 0x1fc 0x3f8 0x000 0x05 0x000 #define MX25_PAD_GPIO_C__CAN2_TX 0x1fc 0x3f8 0x000 0x06 0x000 +#define MX25_PAD_GPIO_C__CSPI2_SS2 0x1fc 0x3f8 0x000 0x07 0x000 #define MX25_PAD_GPIO_D__GPIO_D 0x200 0x3fc 0x000 0x00 0x000 #define MX25_PAD_GPIO_D__I2C2_SDA 0x200 0x3fc 0x520 0x02 0x001 #define MX25_PAD_GPIO_D__CAN2_RX 0x200 0x3fc 0x484 0x06 0x001 +#define MX25_PAD_GPIO_D__CSPI3_SS2 0x200 0x3fc 0x4c4 0x07 0x001 #define MX25_PAD_GPIO_E__GPIO_E 0x204 0x400 0x000 0x00 0x000 #define MX25_PAD_GPIO_E__I2C3_CLK 0x204 0x400 0x524 0x01 0x002 @@ -593,6 +608,7 @@ #define MX25_PAD_VSTBY_REQ__UART4_RTS 0x214 0x408 0x56c 0x06 0x002 #define MX25_PAD_VSTBY_ACK__VSTBY_ACK 0x218 0x40c 0x000 0x00 0x000 +#define MX25_PAD_VSTBY_ACK__CSPI1_SS3 0x218 0x40c 0x490 0x02 0x001 #define MX25_PAD_VSTBY_ACK__GPIO_3_18 0x218 0x40c 0x000 0x05 0x000 #define MX25_PAD_POWER_FAIL__POWER_FAIL 0x21c 0x410 0x000 0x00 0x000 diff --git a/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi b/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi index 52c95248e25d..303f920201c5 100644 --- a/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi +++ b/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi @@ -18,8 +18,8 @@ }; &cspi1 { - cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>, - <&gpio4 27 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>, + <&gpio4 27 GPIO_ACTIVE_LOW>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts index bf883e45576a..344e77790152 100644 --- a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts +++ b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts @@ -65,7 +65,7 @@ &cspi1 { pinctrl-0 = <&pinctrl_cspi1>, <&pinctrl_cspi1cs1>; - cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>, + cs-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>, <&gpio4 27 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi index fc0b318f8733..7bc132737a37 100644 --- a/arch/arm/boot/dts/imx27.dtsi +++ b/arch/arm/boot/dts/imx27.dtsi @@ -558,7 +558,7 @@ }; }; - nfc: nand@d8000000 { + nfc: nand-controller@d8000000 { #address-cells = <1>; #size-cells = <1>; compatible = "fsl,imx27-nand"; diff --git a/arch/arm/boot/dts/imx28-apf28.dts b/arch/arm/boot/dts/imx28-apf28.dts index 3ed2b328f7ef..14a92fe59770 100644 --- a/arch/arm/boot/dts/imx28-apf28.dts +++ b/arch/arm/boot/dts/imx28-apf28.dts @@ -17,7 +17,7 @@ apb@80000000 { apbh@80000000 { - gpmi-nand@8000c000 { + nand-controller@8000c000 { pinctrl-names = "default"; pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>; status = "okay"; diff --git a/arch/arm/boot/dts/imx28-apx4devkit.dts b/arch/arm/boot/dts/imx28-apx4devkit.dts index c5acc19c982d..b86be320496b 100644 --- a/arch/arm/boot/dts/imx28-apx4devkit.dts +++ b/arch/arm/boot/dts/imx28-apx4devkit.dts @@ -13,7 +13,7 @@ apb@80000000 { apbh@80000000 { - gpmi-nand@8000c000 { + nand-controller@8000c000 { pinctrl-names = "default"; pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>; status = "okay"; diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts index 96c1d106bc64..7e2b0f198dfa 100644 --- a/arch/arm/boot/dts/imx28-evk.dts +++ b/arch/arm/boot/dts/imx28-evk.dts @@ -97,7 +97,7 @@ apb@80000000 { apbh@80000000 { - gpmi-nand@8000c000 { + nand-controller@8000c000 { pinctrl-names = "default"; pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg &gpmi_pins_evk>; diff --git a/arch/arm/boot/dts/imx28-m28.dtsi b/arch/arm/boot/dts/imx28-m28.dtsi index 0bac72d5351f..2bdb4c093545 100644 --- a/arch/arm/boot/dts/imx28-m28.dtsi +++ b/arch/arm/boot/dts/imx28-m28.dtsi @@ -16,7 +16,7 @@ apb@80000000 { apbh@80000000 { - gpmi-nand@8000c000 { + nand-controller@8000c000 { #address-cells = <1>; #size-cells = <1>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/imx28-m28cu3.dts b/arch/arm/boot/dts/imx28-m28cu3.dts index 91bd6deffee5..865ac3d573c7 100644 --- a/arch/arm/boot/dts/imx28-m28cu3.dts +++ b/arch/arm/boot/dts/imx28-m28cu3.dts @@ -17,7 +17,7 @@ apb@80000000 { apbh@80000000 { - gpmi-nand@8000c000 { + nand-controller@8000c000 { #address-cells = <1>; #size-cells = <1>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index a2b799c56f8f..94dfbf5b3f34 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi @@ -100,7 +100,7 @@ status = "disabled"; }; - gpmi: gpmi-nand@8000c000 { + gpmi: nand-controller@8000c000 { compatible = "fsl,imx28-gpmi-nand"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/imx50-evk.dts b/arch/arm/boot/dts/imx50-evk.dts index a25da415cb02..4ea5c23f181b 100644 --- a/arch/arm/boot/dts/imx50-evk.dts +++ b/arch/arm/boot/dts/imx50-evk.dts @@ -20,7 +20,7 @@ &cspi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_cspi>; - cs-gpios = <&gpio4 11 0>, <&gpio4 13 0>; + cs-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>, <&gpio4 13 GPIO_ACTIVE_LOW>; status = "okay"; flash: m25p32@1 { @@ -59,7 +59,7 @@ MX50_PAD_CSPI_MISO__CSPI_MISO 0x00 MX50_PAD_CSPI_MOSI__CSPI_MOSI 0x00 MX50_PAD_CSPI_SS0__GPIO4_11 0xc4 - MX50_PAD_ECSPI1_MOSI__CSPI_SS1 0xf4 + MX50_PAD_ECSPI1_MOSI__GPIO4_13 0x84 >; }; diff --git a/arch/arm/boot/dts/imx51-apf51dev.dts b/arch/arm/boot/dts/imx51-apf51dev.dts index 563c1aae8c0c..c66f274ba4e9 100644 --- a/arch/arm/boot/dts/imx51-apf51dev.dts +++ b/arch/arm/boot/dts/imx51-apf51dev.dts @@ -74,8 +74,8 @@ &ecspi1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>, - <&gpio4 25 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>, + <&gpio4 25 GPIO_ACTIVE_LOW>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx53-m53menlo.dts b/arch/arm/boot/dts/imx53-m53menlo.dts index 719ed5ca454a..f98691ae4415 100644 --- a/arch/arm/boot/dts/imx53-m53menlo.dts +++ b/arch/arm/boot/dts/imx53-m53menlo.dts @@ -104,7 +104,7 @@ &ecspi2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi2>; - cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>, <&gpio2 27 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>, <&gpio2 27 GPIO_ACTIVE_LOW>; status = "okay"; spidev@0 { diff --git a/arch/arm/boot/dts/imx53-smd.dts b/arch/arm/boot/dts/imx53-smd.dts index ec9fb8940ffa..9be44e807188 100644 --- a/arch/arm/boot/dts/imx53-smd.dts +++ b/arch/arm/boot/dts/imx53-smd.dts @@ -58,7 +58,7 @@ &ecspi1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>; + cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>, <&gpio3 19 GPIO_ACTIVE_LOW>; status = "okay"; zigbee: mc1323@0 { diff --git a/arch/arm/boot/dts/imx53-tqma53.dtsi b/arch/arm/boot/dts/imx53-tqma53.dtsi index 9a6cb138adf3..7e7f9f3b3906 100644 --- a/arch/arm/boot/dts/imx53-tqma53.dtsi +++ b/arch/arm/boot/dts/imx53-tqma53.dtsi @@ -50,8 +50,8 @@ &ecspi1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>, - <&gpio3 24 0>, <&gpio3 25 0>; + cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>, <&gpio3 19 GPIO_ACTIVE_LOW>, + <&gpio3 24 GPIO_ACTIVE_LOW>, <&gpio3 25 GPIO_ACTIVE_LOW>; status = "disabled"; }; @@ -251,8 +251,8 @@ &cspi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_cspi>; - cs-gpios = <&gpio1 18 0>, <&gpio1 19 0>, - <&gpio1 21 0>; + cs-gpios = <&gpio1 18 GPIO_ACTIVE_LOW>, <&gpio1 19 GPIO_ACTIVE_LOW>, + <&gpio1 21 GPIO_ACTIVE_LOW>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi b/arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi index 289feab42b88..24859d0c09c1 100644 --- a/arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi +++ b/arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi @@ -119,7 +119,8 @@ &ecspi1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>, <&gpio2 16 0>, <&gpio2 17 0>; + cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>, <&gpio3 19 GPIO_ACTIVE_LOW>, + <&gpio2 16 GPIO_ACTIVE_LOW>, <&gpio2 17 GPIO_ACTIVE_LOW>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6-logicpd-baseboard.dtsi b/arch/arm/boot/dts/imx6-logicpd-baseboard.dtsi index 9e027b9a5f91..665d63765cdc 100644 --- a/arch/arm/boot/dts/imx6-logicpd-baseboard.dtsi +++ b/arch/arm/boot/dts/imx6-logicpd-baseboard.dtsi @@ -212,6 +212,7 @@ &ecspi1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; status = "disabled"; }; @@ -383,7 +384,7 @@ MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_KEY_ROW1__ECSPI1_SS0 0x100b1 + MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0 >; }; diff --git a/arch/arm/boot/dts/imx6dl-aristainetos_4.dts b/arch/arm/boot/dts/imx6dl-aristainetos_4.dts index 809ca5611072..5c7e85300695 100644 --- a/arch/arm/boot/dts/imx6dl-aristainetos_4.dts +++ b/arch/arm/boot/dts/imx6dl-aristainetos_4.dts @@ -61,7 +61,7 @@ }; &ecspi2 { - cs-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi2>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts b/arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts index 9eb2b73951b2..b4a9523e325b 100644 --- a/arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts +++ b/arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts @@ -67,7 +67,7 @@ &ecspi2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi2>; - cs-gpios = <&gpio5 12 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>; status = "okay"; flash@0 { @@ -80,7 +80,7 @@ &ecspi1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; status = "okay"; tpm@0 { diff --git a/arch/arm/boot/dts/imx6dl-prtrvt.dts b/arch/arm/boot/dts/imx6dl-prtrvt.dts index fa882458957b..5ac84445e9cc 100644 --- a/arch/arm/boot/dts/imx6dl-prtrvt.dts +++ b/arch/arm/boot/dts/imx6dl-prtrvt.dts @@ -37,7 +37,7 @@ }; &ecspi1 { - cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; @@ -52,7 +52,7 @@ }; &ecspi3 { - cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi3>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6dl-prtvt7.dts b/arch/arm/boot/dts/imx6dl-prtvt7.dts index 306b4f7bf762..ae6da241f13e 100644 --- a/arch/arm/boot/dts/imx6dl-prtvt7.dts +++ b/arch/arm/boot/dts/imx6dl-prtvt7.dts @@ -219,7 +219,7 @@ }; &ecspi2 { - cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi2>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6dl-tqma6a.dtsi b/arch/arm/boot/dts/imx6dl-tqma6a.dtsi new file mode 100644 index 000000000000..e891ef9b0091 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-tqma6a.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Sascha Hauer, Pengutronix + * Copyright 2013-2017 Markus Niebel <Markus.Niebel@tq-group.com> + */ + +#include "imx6dl.dtsi" +#include "imx6qdl-tqma6a.dtsi" +#include "imx6qdl-tqma6.dtsi" + +/ { + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x20000000>; + }; +}; diff --git a/arch/arm/boot/dts/imx6dl-tqma6b.dtsi b/arch/arm/boot/dts/imx6dl-tqma6b.dtsi new file mode 100644 index 000000000000..38cd8501a886 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-tqma6b.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Sascha Hauer, Pengutronix + * Copyright 2013-2017 Markus Niebel <Markus.Niebel@tq-group.com> + */ + +#include "imx6dl.dtsi" +#include "imx6qdl-tqma6b.dtsi" +#include "imx6qdl-tqma6.dtsi" + +/ { + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x20000000>; + }; +}; diff --git a/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi b/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi index c4a235d212b6..7d2c72562c73 100644 --- a/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi +++ b/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi @@ -8,6 +8,11 @@ #include <dt-bindings/pwm/pwm.h> / { + aliases: aliases { + ethernet1 = ð1; + ethernet2 = ð2; + }; + backlight: backlight { compatible = "pwm-backlight"; pwms = <&pwm1 0 500000 PWM_POLARITY_INVERTED>; @@ -135,13 +140,13 @@ }; }; - port@2 { + eth2: port@2 { reg = <2>; label = "eth2"; phy-handle = <&phy_port2>; }; - port@3 { + eth1: port@3 { reg = <3>; label = "eth1"; phy-handle = <&phy_port3>; @@ -258,29 +263,35 @@ reg = <0x30>; clock-mode = /bits/ 8 <1>; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; - chan0 { + chan@0 { chan-name = "R"; led-cur = /bits/ 8 <0x20>; max-cur = /bits/ 8 <0x60>; + reg = <0>; }; - chan1 { + chan@1 { chan-name = "G"; led-cur = /bits/ 8 <0x20>; max-cur = /bits/ 8 <0x60>; + reg = <1>; }; - chan2 { + chan@2 { chan-name = "B"; led-cur = /bits/ 8 <0x20>; max-cur = /bits/ 8 <0x60>; + reg = <2>; }; - chan3 { + chan@3 { chan-name = "W"; led-cur = /bits/ 8 <0x0>; max-cur = /bits/ 8 <0x0>; + reg = <3>; }; }; @@ -311,7 +322,20 @@ pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; - oled: oled@3d { + oled_1309: oled@3c { + compatible = "solomon,ssd1309fb-i2c"; + reg = <0x3c>; + solomon,height = <64>; + solomon,width = <128>; + solomon,page-offset = <0>; + solomon,segment-no-remap; + solomon,prechargep2 = <15>; + reset-gpios = <&gpio_oled 1 GPIO_ACTIVE_LOW>; + vbat-supply = <&sw2_reg>; + status = "disabled"; + }; + + oled_1305: oled@3d { compatible = "solomon,ssd1305fb-i2c"; reg = <0x3d>; solomon,height = <64>; diff --git a/arch/arm/boot/dts/imx6dl-yapp4-hydra.dts b/arch/arm/boot/dts/imx6dl-yapp4-hydra.dts index 6010d3d872ab..a19609c7c7c0 100644 --- a/arch/arm/boot/dts/imx6dl-yapp4-hydra.dts +++ b/arch/arm/boot/dts/imx6dl-yapp4-hydra.dts @@ -29,7 +29,11 @@ status = "okay"; }; -&oled { +&oled_1305 { + status = "okay"; +}; + +&oled_1309 { status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6dl-yapp4-orion.dts b/arch/arm/boot/dts/imx6dl-yapp4-orion.dts new file mode 100644 index 000000000000..884b236746bb --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-yapp4-orion.dts @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2020 Y Soft Corporation, a.s. + +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6dl-yapp4-common.dtsi" + +/ { + model = "Y Soft IOTA Orion i.MX6DualLite board"; + compatible = "ysoft,imx6dl-yapp4-orion", "fsl,imx6dl"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0xf0000000>; + }; +}; + +&gpio_oled { + status = "okay"; +}; + +&leds { + status = "okay"; +}; + +&oled_1305 { + status = "okay"; +}; + +&oled_1309 { + status = "okay"; +}; + +®_usb_h1_vbus { + status = "okay"; +}; + +&touchkeys { + status = "okay"; +}; + +&uart2 { + status = "disabled"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbphy2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6dl-yapp4-ursa.dts b/arch/arm/boot/dts/imx6dl-yapp4-ursa.dts index a1173bf5bff5..f6ae24efd4aa 100644 --- a/arch/arm/boot/dts/imx6dl-yapp4-ursa.dts +++ b/arch/arm/boot/dts/imx6dl-yapp4-ursa.dts @@ -17,6 +17,10 @@ }; }; +&aliases { + /delete-property/ ethernet1; +}; + &backlight { status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi index 77b65a402e19..fdd81fdc3f35 100644 --- a/arch/arm/boot/dts/imx6dl.dtsi +++ b/arch/arm/boot/dts/imx6dl.dtsi @@ -88,10 +88,6 @@ }; aips1: bus@2000000 { - iomuxc: pinctrl@20e0000 { - compatible = "fsl,imx6dl-iomuxc"; - }; - pxp: pxp@20f0000 { reg = <0x020f0000 0x4000>; interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; @@ -298,6 +294,10 @@ compatible = "fsl,imx6dl-hdmi"; }; +&iomuxc { + compatible = "fsl,imx6dl-iomuxc"; +}; + &ipu1_csi1 { ipu1_csi1_from_ipu1_csi1_mux: endpoint { remote-endpoint = <&ipu1_csi1_mux_to_ipu1_csi1>; diff --git a/arch/arm/boot/dts/imx6q-b450v3.dts b/arch/arm/boot/dts/imx6q-b450v3.dts index fb0980190aa0..604f2420370f 100644 --- a/arch/arm/boot/dts/imx6q-b450v3.dts +++ b/arch/arm/boot/dts/imx6q-b450v3.dts @@ -84,19 +84,19 @@ }; &pca9539 { - P04 { + P04-hog { gpio-hog; gpios = <4 0>; output-low; line-name = "PCA9539-P04"; }; - P07 { - gpio-hog; - gpios = <7 0>; - output-low; - line-name = "PCA9539-P07"; - }; + P07-hog { + gpio-hog; + gpios = <7 0>; + output-low; + line-name = "PCA9539-P07"; + }; }; &pci_root { diff --git a/arch/arm/boot/dts/imx6q-b650v3.dts b/arch/arm/boot/dts/imx6q-b650v3.dts index 8f762d9c5ae9..56d2aeb1900c 100644 --- a/arch/arm/boot/dts/imx6q-b650v3.dts +++ b/arch/arm/boot/dts/imx6q-b650v3.dts @@ -84,12 +84,12 @@ }; &pca9539 { - P07 { - gpio-hog; - gpios = <7 0>; - output-low; - line-name = "PCA9539-P07"; - }; + P07-hog { + gpio-hog; + gpios = <7 0>; + output-low; + line-name = "PCA9539-P07"; + }; }; &usbphy1 { diff --git a/arch/arm/boot/dts/imx6q-b850v3.dts b/arch/arm/boot/dts/imx6q-b850v3.dts index 1ea64ecf4291..3d6b757bf325 100644 --- a/arch/arm/boot/dts/imx6q-b850v3.dts +++ b/arch/arm/boot/dts/imx6q-b850v3.dts @@ -199,14 +199,14 @@ }; &pca9539 { - P10 { + P10-hog { gpio-hog; gpios = <8 0>; output-low; line-name = "PCA9539-P10"; }; - P11 { + P11-hog { gpio-hog; gpios = <9 0>; output-low; diff --git a/arch/arm/boot/dts/imx6q-ba16.dtsi b/arch/arm/boot/dts/imx6q-ba16.dtsi index fc81f2f4b62d..e4578ed3371e 100644 --- a/arch/arm/boot/dts/imx6q-ba16.dtsi +++ b/arch/arm/boot/dts/imx6q-ba16.dtsi @@ -134,7 +134,7 @@ }; &ecspi1 { - cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6q-bx50v3.dtsi b/arch/arm/boot/dts/imx6q-bx50v3.dtsi index 1938b04199c4..2a98cc657595 100644 --- a/arch/arm/boot/dts/imx6q-bx50v3.dtsi +++ b/arch/arm/boot/dts/imx6q-bx50v3.dtsi @@ -102,10 +102,15 @@ #address-cells = <1>; #size-cells = <0>; - switch@0 { + switch: switch@0 { compatible = "marvell,mv88e6085"; /* 88e6240*/ reg = <0>; + interrupt-parent = <&gpio2>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + switch_ports: ports { #address-cells = <1>; #size-cells = <0>; @@ -117,22 +122,32 @@ switchphy0: switchphy@0 { reg = <0>; + interrupt-parent = <&switch>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; }; switchphy1: switchphy@1 { reg = <1>; + interrupt-parent = <&switch>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; }; switchphy2: switchphy@2 { reg = <2>; + interrupt-parent = <&switch>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; }; switchphy3: switchphy@3 { reg = <3>; + interrupt-parent = <&switch>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; }; switchphy4: switchphy@4 { reg = <4>; + interrupt-parent = <&switch>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; }; }; }; @@ -140,7 +155,7 @@ }; &ecspi5 { - cs-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi5>; status = "okay"; @@ -233,42 +248,42 @@ interrupt-parent = <&gpio2>; interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - P12 { + P12-hog { gpio-hog; gpios = <10 0>; output-low; line-name = "PCA9539-P12"; }; - P13 { + P13-hog { gpio-hog; gpios = <11 0>; output-low; line-name = "PCA9539-P13"; }; - P14 { + P14-hog { gpio-hog; gpios = <12 0>; output-low; line-name = "PCA9539-P14"; }; - P15 { + P15-hog { gpio-hog; gpios = <13 0>; output-low; line-name = "PCA9539-P15"; }; - P16 { + P16-hog { gpio-hog; gpios = <14 0>; output-low; line-name = "PCA9539-P16"; }; - P17 { + P17-hog { gpio-hog; gpios = <15 0>; output-low; diff --git a/arch/arm/boot/dts/imx6q-cm-fx6.dts b/arch/arm/boot/dts/imx6q-cm-fx6.dts index cab9e92531c7..bfb530f29d9d 100644 --- a/arch/arm/boot/dts/imx6q-cm-fx6.dts +++ b/arch/arm/boot/dts/imx6q-cm-fx6.dts @@ -255,7 +255,7 @@ }; &ecspi1 { - cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>, <&gpio3 19 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>, <&gpio3 19 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6q-dhcom-som.dtsi b/arch/arm/boot/dts/imx6q-dhcom-som.dtsi index 87f0aa897086..236fc205c389 100644 --- a/arch/arm/boot/dts/imx6q-dhcom-som.dtsi +++ b/arch/arm/boot/dts/imx6q-dhcom-som.dtsi @@ -59,7 +59,7 @@ }; &ecspi1 { - cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>, <&gpio4 11 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>, <&gpio4 11 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts index f9df207b2778..fa2307d8ce86 100644 --- a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts +++ b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts @@ -99,7 +99,7 @@ &ecspi5 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi5>; - cs-gpios = <&gpio1 12 0>; + cs-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; status = "okay"; flash: m25p80@0 { diff --git a/arch/arm/boot/dts/imx6q-dms-ba16.dts b/arch/arm/boot/dts/imx6q-dms-ba16.dts index 57761f3172fa..48fb47e715f6 100644 --- a/arch/arm/boot/dts/imx6q-dms-ba16.dts +++ b/arch/arm/boot/dts/imx6q-dms-ba16.dts @@ -42,7 +42,7 @@ }; &ecspi5 { - cs-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi5>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6q-gw5400-a.dts b/arch/arm/boot/dts/imx6q-gw5400-a.dts index b6e2b580051d..4cde45d5c90c 100644 --- a/arch/arm/boot/dts/imx6q-gw5400-a.dts +++ b/arch/arm/boot/dts/imx6q-gw5400-a.dts @@ -132,7 +132,7 @@ }; &ecspi1 { - cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6q-kontron-samx6i.dtsi b/arch/arm/boot/dts/imx6q-kontron-samx6i.dtsi index 2618eccfe50d..4d6a0c3e8455 100644 --- a/arch/arm/boot/dts/imx6q-kontron-samx6i.dtsi +++ b/arch/arm/boot/dts/imx6q-kontron-samx6i.dtsi @@ -14,10 +14,9 @@ /* Quad/Dual SoMs have 3 chip-select signals */ &ecspi4 { - fsl,spi-num-chipselects = <3>; - cs-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>, - <&gpio3 29 GPIO_ACTIVE_HIGH>, - <&gpio3 25 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>, + <&gpio3 29 GPIO_ACTIVE_LOW>, + <&gpio3 25 GPIO_ACTIVE_LOW>; }; &pinctrl_ecspi4 { diff --git a/arch/arm/boot/dts/imx6q-logicpd.dts b/arch/arm/boot/dts/imx6q-logicpd.dts index 8f94364ba484..46a4ddedb423 100644 --- a/arch/arm/boot/dts/imx6q-logicpd.dts +++ b/arch/arm/boot/dts/imx6q-logicpd.dts @@ -9,7 +9,7 @@ / { model = "Logic PD i.MX6QD SOM-M3"; - compatible = "fsl,imx6q"; + compatible = "logicpd,imx6q-logicpd", "fsl,imx6q"; backlight: backlight-lvds { compatible = "pwm-backlight"; diff --git a/arch/arm/boot/dts/imx6q-prti6q.dts b/arch/arm/boot/dts/imx6q-prti6q.dts index de6cbaab8b49..b4605edfd2ab 100644 --- a/arch/arm/boot/dts/imx6q-prti6q.dts +++ b/arch/arm/boot/dts/imx6q-prti6q.dts @@ -158,7 +158,7 @@ }; &ecspi1 { - cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; @@ -171,7 +171,7 @@ }; &ecspi2 { - cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>, <&gpio4 25 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>, <&gpio4 25 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>; status = "okay"; @@ -195,7 +195,7 @@ }; &ecspi3 { - cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi3>; status = "okay"; @@ -213,8 +213,8 @@ #size-cells = <0>; /* Microchip KSZ9031RNX PHY */ - rgmii_phy: ethernet-phy@4 { - reg = <4>; + rgmii_phy: ethernet-phy@0 { + reg = <0>; interrupts-extended = <&gpio1 28 IRQ_TYPE_LEVEL_LOW>; reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; reset-assert-us = <10000>; diff --git a/arch/arm/boot/dts/imx6q-tqma6a.dtsi b/arch/arm/boot/dts/imx6q-tqma6a.dtsi new file mode 100644 index 000000000000..ab4c07c13a13 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-tqma6a.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Sascha Hauer, Pengutronix + * Copyright 2013-2017 Markus Niebel <Markus.Niebel@tq-group.com> + */ + +#include "imx6q.dtsi" +#include "imx6qdl-tqma6a.dtsi" +#include "imx6qdl-tqma6.dtsi" + +/ { + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x40000000>; + }; +}; diff --git a/arch/arm/boot/dts/imx6q-tqma6b.dtsi b/arch/arm/boot/dts/imx6q-tqma6b.dtsi new file mode 100644 index 000000000000..7224c376c318 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-tqma6b.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Sascha Hauer, Pengutronix + */ + +#include "imx6q.dtsi" +#include "imx6qdl-tqma6b.dtsi" +#include "imx6qdl-tqma6.dtsi" + +/ { + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x40000000>; + }; +}; diff --git a/arch/arm/boot/dts/imx6q-var-dt6customboard.dts b/arch/arm/boot/dts/imx6q-var-dt6customboard.dts index a57c2e3a8435..63550351340d 100644 --- a/arch/arm/boot/dts/imx6q-var-dt6customboard.dts +++ b/arch/arm/boot/dts/imx6q-var-dt6customboard.dts @@ -144,8 +144,8 @@ }; &ecspi1 { - cs-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>, - <&gpio4 10 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>, + <&gpio4 10 GPIO_ACTIVE_LOW>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index 78a4d64929f3..5277e3903291 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -182,10 +182,6 @@ status = "disabled"; }; }; - - iomuxc: pinctrl@20e0000 { - compatible = "fsl,imx6q-iomuxc"; - }; }; sata: sata@2200000 { @@ -427,6 +423,10 @@ }; }; +&iomuxc { + compatible = "fsl,imx6q-iomuxc"; +}; + &ipu1_csi1 { ipu1_csi1_from_mipi_vc1: endpoint { remote-endpoint = <&mipi_vc1_to_ipu1_csi1>; diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/imx6qdl-apalis.dtsi index dbdd7db60325..30fa349f9d05 100644 --- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi +++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi @@ -127,7 +127,7 @@ /* Apalis SPI1 */ &ecspi1 { - cs-gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; status = "disabled"; @@ -135,7 +135,7 @@ /* Apalis SPI2 */ &ecspi2 { - cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi2>; status = "disabled"; diff --git a/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi b/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi index d954661fa055..e21f6ac864e5 100644 --- a/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi +++ b/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi @@ -91,7 +91,7 @@ }; &ecspi4 { - cs-gpios = <&gpio3 20 0>; + cs-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi4>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi b/arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi index d38630d4b892..ead7ba27e105 100644 --- a/arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi +++ b/arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi @@ -110,23 +110,23 @@ }; &ecspi1 { - cs-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH - &gpio4 10 GPIO_ACTIVE_HIGH - &gpio4 11 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW + &gpio4 10 GPIO_ACTIVE_LOW + &gpio4 11 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; }; &ecspi2 { - cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH &gpio2 27 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW &gpio2 27 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi2>; status = "okay"; }; &ecspi4 { - cs-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH &gpio5 2 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio3 29 GPIO_ACTIVE_LOW &gpio5 2 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi4>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi index 0930194fd960..4e2a309c93fa 100644 --- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi +++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi @@ -94,7 +94,7 @@ /* Colibri SSP */ &ecspi4 { - cs-gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi4>; status = "disabled"; diff --git a/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi b/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi index ebe7a8bddf04..648f5fcb72e6 100644 --- a/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi +++ b/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi @@ -30,7 +30,7 @@ }; &ecspi3 { - cs-gpios = <&gpio4 24 0>; + cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi3>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6qdl-emcon.dtsi b/arch/arm/boot/dts/imx6qdl-emcon.dtsi index 35e230f991f1..7228b894a763 100644 --- a/arch/arm/boot/dts/imx6qdl-emcon.dtsi +++ b/arch/arm/boot/dts/imx6qdl-emcon.dtsi @@ -168,8 +168,8 @@ &ecspi2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi2>; - cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>, - <&gpio2 27 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>, + <&gpio2 27 GPIO_ACTIVE_LOW>; }; &ecspi4 { diff --git a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi index 4d01c3300b97..3c04b5a4f3cb 100644 --- a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi @@ -5,6 +5,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/linux-event-codes.h> +#include <dt-bindings/interrupt-controller/irq.h> / { /* these are used by bootloader for disabling nodes */ @@ -152,7 +153,7 @@ compatible = "gw,gsc"; reg = <0x20>; interrupt-parent = <&gpio1>; - interrupts = <4 GPIO_ACTIVE_LOW>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; #interrupt-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi index a46ea98228c2..736074f1c3ef 100644 --- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi @@ -5,6 +5,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/linux-event-codes.h> +#include <dt-bindings/interrupt-controller/irq.h> / { /* these are used by bootloader for disabling nodes */ @@ -182,7 +183,7 @@ }; &ecspi3 { - cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi3>; status = "okay"; @@ -217,7 +218,7 @@ compatible = "gw,gsc"; reg = <0x20>; interrupt-parent = <&gpio1>; - interrupts = <4 GPIO_ACTIVE_LOW>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; #interrupt-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi index a28e79463d0c..8072ed47c6bb 100644 --- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi @@ -5,6 +5,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/linux-event-codes.h> +#include <dt-bindings/interrupt-controller/irq.h> / { /* these are used by bootloader for disabling nodes */ @@ -210,7 +211,7 @@ compatible = "gw,gsc"; reg = <0x20>; interrupt-parent = <&gpio1>; - interrupts = <4 GPIO_ACTIVE_LOW>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; #interrupt-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi index b5f934b8a239..8c9bcdd39830 100644 --- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi @@ -5,6 +5,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/linux-event-codes.h> +#include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/sound/fsl-imx-audmux.h> / { @@ -212,7 +213,7 @@ }; &ecspi2 { - cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi2>; status = "okay"; @@ -247,7 +248,7 @@ compatible = "gw,gsc"; reg = <0x20>; interrupt-parent = <&gpio1>; - interrupts = <4 GPIO_ACTIVE_LOW>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; #interrupt-cells = <1>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/imx6qdl-gw551x.dtsi b/arch/arm/boot/dts/imx6qdl-gw551x.dtsi index 1516e2b0bcde..e5d803d023c8 100644 --- a/arch/arm/boot/dts/imx6qdl-gw551x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw551x.dtsi @@ -48,6 +48,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/media/tda1997x.h> #include <dt-bindings/input/linux-event-codes.h> +#include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/sound/fsl-imx-audmux.h> / { @@ -219,7 +220,7 @@ compatible = "gw,gsc"; reg = <0x20>; interrupt-parent = <&gpio1>; - interrupts = <4 GPIO_ACTIVE_LOW>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; #interrupt-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi index 0da6e6f7482b..290a607fede9 100644 --- a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi @@ -5,6 +5,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/linux-event-codes.h> +#include <dt-bindings/interrupt-controller/irq.h> / { /* these are used by bootloader for disabling nodes */ @@ -144,7 +145,7 @@ compatible = "gw,gsc"; reg = <0x20>; interrupt-parent = <&gpio1>; - interrupts = <4 GPIO_ACTIVE_LOW>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; #interrupt-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/imx6qdl-gw553x.dtsi b/arch/arm/boot/dts/imx6qdl-gw553x.dtsi index db30de5d6490..c15b9cc63bf8 100644 --- a/arch/arm/boot/dts/imx6qdl-gw553x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw553x.dtsi @@ -47,6 +47,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/linux-event-codes.h> +#include <dt-bindings/interrupt-controller/irq.h> / { /* these are used by bootloader for disabling nodes */ @@ -64,8 +65,6 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; user-pb { label = "user_pb"; @@ -182,7 +181,7 @@ compatible = "gw,gsc"; reg = <0x20>; interrupt-parent = <&gpio1>; - interrupts = <4 GPIO_ACTIVE_LOW>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; #interrupt-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/imx6qdl-gw560x.dtsi b/arch/arm/boot/dts/imx6qdl-gw560x.dtsi index d6b074597518..093a219a77ae 100644 --- a/arch/arm/boot/dts/imx6qdl-gw560x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw560x.dtsi @@ -47,6 +47,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/irq.h> / { /* these are used by bootloader for disabling nodes */ @@ -252,7 +253,7 @@ }; &ecspi3 { - cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi3>; status = "okay"; @@ -294,7 +295,7 @@ compatible = "gw,gsc"; reg = <0x20>; interrupt-parent = <&gpio1>; - interrupts = <4 GPIO_ACTIVE_LOW>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; #interrupt-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/imx6qdl-gw5903.dtsi b/arch/arm/boot/dts/imx6qdl-gw5903.dtsi index fbe6c32bd756..e1c8dd233cab 100644 --- a/arch/arm/boot/dts/imx6qdl-gw5903.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw5903.dtsi @@ -47,6 +47,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/linux-event-codes.h> +#include <dt-bindings/interrupt-controller/irq.h> / { chosen { @@ -235,7 +236,7 @@ compatible = "gw,gsc"; reg = <0x20>; interrupt-parent = <&gpio1>; - interrupts = <4 GPIO_ACTIVE_LOW>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; #interrupt-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/imx6qdl-gw5904.dtsi b/arch/arm/boot/dts/imx6qdl-gw5904.dtsi index 23c6e4047621..3cd2e717c1da 100644 --- a/arch/arm/boot/dts/imx6qdl-gw5904.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw5904.dtsi @@ -47,6 +47,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/linux-event-codes.h> +#include <dt-bindings/interrupt-controller/irq.h> / { /* these are used by bootloader for disabling nodes */ @@ -257,7 +258,7 @@ compatible = "gw,gsc"; reg = <0x20>; interrupt-parent = <&gpio1>; - interrupts = <4 GPIO_ACTIVE_LOW>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; #interrupt-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/imx6qdl-gw5907.dtsi b/arch/arm/boot/dts/imx6qdl-gw5907.dtsi index b1ff7c859c4d..21c68a55bcb9 100644 --- a/arch/arm/boot/dts/imx6qdl-gw5907.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw5907.dtsi @@ -5,6 +5,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/linux-event-codes.h> +#include <dt-bindings/interrupt-controller/irq.h> / { /* these are used by bootloader for disabling nodes */ @@ -154,7 +155,7 @@ compatible = "gw,gsc"; reg = <0x20>; interrupt-parent = <&gpio1>; - interrupts = <4 GPIO_ACTIVE_LOW>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; #interrupt-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/imx6qdl-gw5910.dtsi b/arch/arm/boot/dts/imx6qdl-gw5910.dtsi index 11f84ee7b88f..ed4e22259959 100644 --- a/arch/arm/boot/dts/imx6qdl-gw5910.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw5910.dtsi @@ -5,6 +5,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/linux-event-codes.h> +#include <dt-bindings/interrupt-controller/irq.h> / { /* these are used by bootloader for disabling nodes */ @@ -134,7 +135,7 @@ &ecspi3 { - cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi3>; status = "okay"; @@ -163,7 +164,7 @@ compatible = "gw,gsc"; reg = <0x20>; interrupt-parent = <&gpio1>; - interrupts = <4 GPIO_ACTIVE_LOW>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; #interrupt-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/imx6qdl-gw5912.dtsi b/arch/arm/boot/dts/imx6qdl-gw5912.dtsi index 0a1ffff9eb75..797f160249f7 100644 --- a/arch/arm/boot/dts/imx6qdl-gw5912.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw5912.dtsi @@ -5,6 +5,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/linux-event-codes.h> +#include <dt-bindings/interrupt-controller/irq.h> / { /* these are used by bootloader for disabling nodes */ @@ -129,7 +130,7 @@ }; &ecspi2 { - cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi2>; status = "okay"; @@ -158,7 +159,7 @@ compatible = "gw,gsc"; reg = <0x20>; interrupt-parent = <&gpio1>; - interrupts = <4 GPIO_ACTIVE_LOW>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; #interrupt-cells = <1>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/imx6qdl-gw5913.dtsi b/arch/arm/boot/dts/imx6qdl-gw5913.dtsi index d62a8da49367..4cd7d290f5b2 100644 --- a/arch/arm/boot/dts/imx6qdl-gw5913.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw5913.dtsi @@ -5,6 +5,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/linux-event-codes.h> +#include <dt-bindings/interrupt-controller/irq.h> / { /* these are used by bootloader for disabling nodes */ @@ -139,7 +140,7 @@ compatible = "gw,gsc"; reg = <0x20>; interrupt-parent = <&gpio1>; - interrupts = <4 GPIO_ACTIVE_LOW>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; #interrupt-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/imx6qdl-hummingboard2.dtsi b/arch/arm/boot/dts/imx6qdl-hummingboard2.dtsi index e4231331f04e..eb1ad28946d3 100644 --- a/arch/arm/boot/dts/imx6qdl-hummingboard2.dtsi +++ b/arch/arm/boot/dts/imx6qdl-hummingboard2.dtsi @@ -203,7 +203,7 @@ &ecspi2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hummingboard2_ecspi2>; - cs-gpios = <&gpio2 26 0>; + cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi b/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi index 81c7ebb4b3fb..265f5f3dbff6 100644 --- a/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi +++ b/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi @@ -245,16 +245,16 @@ &ecspi2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi2>; - cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>, - <&gpio2 27 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>, + <&gpio2 27 GPIO_ACTIVE_LOW>; }; /* SPI0 */ &ecspi4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi4>; - cs-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>, - <&gpio3 29 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>, + <&gpio3 29 GPIO_ACTIVE_LOW>; status = "okay"; /* default boot source: workaround #1 for errata ERR006282 */ diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi index 185a1a31ca39..a0917823c244 100644 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi @@ -316,7 +316,7 @@ }; &ecspi1 { - cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi index 4bbe54e1ddb5..92d09a3ebe0e 100644 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi @@ -247,7 +247,7 @@ }; &ecspi1 { - cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi index c63e1bc1ad3a..1243677b5f97 100644 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi @@ -232,7 +232,7 @@ }; &ecspi1 { - cs-gpios = <&gpio3 19 0>; + cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi index bc43c75f1745..e361df26a168 100644 --- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi +++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi @@ -71,7 +71,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi3>; status = "okay"; - cs-gpios = <&gpio4 24 0>; + cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; som_flash: flash@0 { compatible = "m25p80", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/imx6qdl-pico.dtsi b/arch/arm/boot/dts/imx6qdl-pico.dtsi index 39dfd90c2c6b..5de4ccb97916 100644 --- a/arch/arm/boot/dts/imx6qdl-pico.dtsi +++ b/arch/arm/boot/dts/imx6qdl-pico.dtsi @@ -167,7 +167,7 @@ &ecspi2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi2>; - cs-gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio2 27 GPIO_ACTIVE_LOW>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi index 55f736dbee0b..afe477f32984 100644 --- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi @@ -267,7 +267,7 @@ }; &ecspi1 { - cs-gpios = <&gpio3 19 0>; + cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; status = "disabled"; /* pin conflict with WEIM NOR */ diff --git a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi index 95f9ddab5996..fdc3aa9d544d 100644 --- a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi @@ -308,7 +308,7 @@ }; &ecspi1 { - cs-gpios = <&gpio3 19 0>; + cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index 68b3e68cb8df..f824c9abd11a 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi @@ -105,9 +105,13 @@ "Ext Spk", "SPKOUTL", "Ext Spk", "SPKOUTR", "AMIC", "MICBIAS", - "IN3R", "AMIC"; + "IN3R", "AMIC", + "DMIC", "MICBIAS", + "DMICDAT", "DMIC"; mux-int-port = <2>; mux-ext-port = <3>; + hp-det-gpio = <&gpio7 8 GPIO_ACTIVE_LOW>; + mic-det-gpio = <&gpio1 9 GPIO_ACTIVE_LOW>; }; backlight_lvds: backlight-lvds { @@ -185,7 +189,7 @@ }; &ecspi1 { - cs-gpios = <&gpio4 9 0>; + cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6qdl-tqma6.dtsi b/arch/arm/boot/dts/imx6qdl-tqma6.dtsi new file mode 100644 index 000000000000..b18b83ac6aee --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-tqma6.dtsi @@ -0,0 +1,201 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Sascha Hauer, Pengutronix + * Copyright 2013-2017 Markus Niebel <Markus.Niebel@tq-group.com> + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "supply-3p3v"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; + status = "okay"; + + m25p80: flash@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + m25p,fast-read; + }; +}; + +&iomuxc { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + /* HYS, SPEED = MED, 100k up, DSE = 011, SRE_FAST */ + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x1b099 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0xb099 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0xb099 + /* eCSPI1 SS1 */ + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0xb099 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b899 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b899 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b899 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b899 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b099 /* PMIC irq */ + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 + >; + }; +}; + +&pmic { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio6>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; + + regulators { + reg_vddcore: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + }; + + reg_vddsoc: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + }; + + reg_gen_3v3: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_ddr_1v5a: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-always-on; + }; + + reg_ddr_1v5b: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_5v_600mA: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + regulator-always-on; + }; + + reg_snvs_3v: vsnvs { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + reg_vrefddr: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + reg_vgen1_1v5: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + /* not used */ + }; + + reg_vgen2_1v2_eth: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + reg_vgen3_2v8: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_vgen4_1v8: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_vgen5_1v8_eth: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_vgen6_3v3: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; +}; + +/* eMMC */ +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + vmmc-supply = <®_3p3v>; + non-removable; + disable-wp; + no-sd; + no-sdio; + bus-width = <8>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + mmccard: mmccard@0 { + reg = <0>; + compatible = "mmc-card"; + broken-hpi; + }; +}; diff --git a/arch/arm/boot/dts/imx6qdl-tqma6a.dtsi b/arch/arm/boot/dts/imx6qdl-tqma6a.dtsi new file mode 100644 index 000000000000..b679bec78e6c --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-tqma6a.dtsi @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Sascha Hauer, Pengutronix + * Copyright 2013-2017 Markus Niebel <Markus.Niebel@tq-group.com> + */ + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clock-frequency = <100000>; + status = "okay"; + + pmic: pmic@8 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + }; + + sensor@48 { + compatible = "national,lm75"; + reg = <0x48>; + }; + + eeprom@50 { + compatible = "st,24c64", "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + }; +}; diff --git a/arch/arm/boot/dts/imx6qdl-tqma6b.dtsi b/arch/arm/boot/dts/imx6qdl-tqma6b.dtsi new file mode 100644 index 000000000000..49c472285c06 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-tqma6b.dtsi @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Sascha Hauer, Pengutronix + * Copyright 2013-2017 Markus Niebel <Markus.Niebel@tq-group.com> + */ + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clock-frequency = <100000>; + status = "okay"; + + pmic: pmic@8 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + }; + + sensor@48 { + compatible = "national,lm75"; + reg = <0x48>; + }; + + eeprom@50 { + compatible = "st,24c64", "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + }; +}; diff --git a/arch/arm/boot/dts/imx6qdl-ts4900.dtsi b/arch/arm/boot/dts/imx6qdl-ts4900.dtsi index 267c956d8910..f88da757edda 100644 --- a/arch/arm/boot/dts/imx6qdl-ts4900.dtsi +++ b/arch/arm/boot/dts/imx6qdl-ts4900.dtsi @@ -95,7 +95,7 @@ }; &ecspi1 { - cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; @@ -108,7 +108,7 @@ }; &ecspi2 { - cs-gpios = <&gpio6 2 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi2>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6qdl-ts7970.dtsi b/arch/arm/boot/dts/imx6qdl-ts7970.dtsi index f0be516dc28e..e6aa0c33754d 100644 --- a/arch/arm/boot/dts/imx6qdl-ts7970.dtsi +++ b/arch/arm/boot/dts/imx6qdl-ts7970.dtsi @@ -165,7 +165,7 @@ }; &ecspi1 { - cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; @@ -179,9 +179,9 @@ &ecspi2 { cs-gpios = < - &gpio5 31 GPIO_ACTIVE_HIGH - &gpio7 12 GPIO_ACTIVE_HIGH - &gpio5 18 GPIO_ACTIVE_HIGH + &gpio5 31 GPIO_ACTIVE_LOW + &gpio7 12 GPIO_ACTIVE_LOW + &gpio5 18 GPIO_ACTIVE_LOW >; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi2>; diff --git a/arch/arm/boot/dts/imx6qdl-udoo.dtsi b/arch/arm/boot/dts/imx6qdl-udoo.dtsi index 828dd20cd27d..d07d8f83456d 100644 --- a/arch/arm/boot/dts/imx6qdl-udoo.dtsi +++ b/arch/arm/boot/dts/imx6qdl-udoo.dtsi @@ -98,7 +98,7 @@ &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi index 5af9ce977b12..66b15748e287 100644 --- a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi +++ b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi @@ -316,7 +316,7 @@ &ecspi1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; status = "okay"; flash@0 { diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index 43edbf1156c7..7a8837cbe21b 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -159,7 +159,7 @@ clocks = <&clks IMX6QDL_CLK_APBH_DMA>; }; - gpmi: gpmi-nand@112000 { + gpmi: nand-controller@112000 { compatible = "fsl,imx6q-gpmi-nand"; reg = <0x00112000 0x2000>, <0x00114000 0x2000>; reg-names = "gpmi-nand", "bch"; @@ -1043,8 +1043,9 @@ <0 119 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6QDL_CLK_ENET>, <&clks IMX6QDL_CLK_ENET>, + <&clks IMX6QDL_CLK_ENET_REF>, <&clks IMX6QDL_CLK_ENET_REF>; - clock-names = "ipg", "ahb", "ptp"; + clock-names = "ipg", "ahb", "ptp", "enet_out"; fsl,stop-mode = <&gpr 0x34 27>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx6qp-sabreauto.dts b/arch/arm/boot/dts/imx6qp-sabreauto.dts index 639d9dd35377..2bb3bfb18ec3 100644 --- a/arch/arm/boot/dts/imx6qp-sabreauto.dts +++ b/arch/arm/boot/dts/imx6qp-sabreauto.dts @@ -47,7 +47,8 @@ }; &pcie { - status = "disabled"; + reset-gpio = <&max7310_c 5 GPIO_ACTIVE_LOW>; + status = "okay"; }; &sata { diff --git a/arch/arm/boot/dts/imx6qp-tqma6b.dtsi b/arch/arm/boot/dts/imx6qp-tqma6b.dtsi new file mode 100644 index 000000000000..bb6ff7c64b27 --- /dev/null +++ b/arch/arm/boot/dts/imx6qp-tqma6b.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2013 Sascha Hauer, Pengutronix + */ + +#include "imx6q.dtsi" +#include "imx6qp.dtsi" +#include "imx6qdl-tqma6b.dtsi" +#include "imx6qdl-tqma6.dtsi" + +/ { + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x40000000>; + }; +}; diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts index b1b069e723d2..25f6f2fb1555 100644 --- a/arch/arm/boot/dts/imx6sl-evk.dts +++ b/arch/arm/boot/dts/imx6sl-evk.dts @@ -94,6 +94,8 @@ sound { compatible = "fsl,imx6sl-evk-wm8962", "fsl,imx-audio-wm8962"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hp>; model = "wm8962-audio"; ssi-controller = <&ssi2>; audio-codec = <&codec>; @@ -106,6 +108,7 @@ "IN3R", "AMIC"; mux-int-port = <2>; mux-ext-port = <3>; + hp-det-gpio = <&gpio4 19 GPIO_ACTIVE_LOW>; }; panel { @@ -129,7 +132,7 @@ }; &ecspi1 { - cs-gpios = <&gpio4 11 0>; + cs-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; @@ -343,6 +346,12 @@ >; }; + pinctrl_hp: hpgrp { + fsl,pins = < + MX6SL_PAD_FEC_RX_ER__GPIO4_IO19 0x1b0b0 + >; + }; + pinctrl_i2c1: i2c1grp { fsl,pins = < MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x4001b8b1 diff --git a/arch/arm/boot/dts/imx6sl-tolino-shine2hd.dts b/arch/arm/boot/dts/imx6sl-tolino-shine2hd.dts new file mode 100644 index 000000000000..caa279608803 --- /dev/null +++ b/arch/arm/boot/dts/imx6sl-tolino-shine2hd.dts @@ -0,0 +1,588 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device tree for the Tolino Shine 2 HD ebook reader + * + * Name on mainboard is: 37NB-E60QF0+4A2 or 37NB-E60QF0+4A3 + * Serials start with: E60QF2 + * + * Copyright 2020 Andreas Kemnade + */ + +/dts-v1/; + +#include <dt-bindings/input/input.h> +#include <dt-bindings/gpio/gpio.h> +#include "imx6sl.dtsi" + +/ { + model = "Tolino Shine 2 HD"; + compatible = "kobo,tolino-shine2hd", "fsl,imx6sl"; + + chosen { + stdout-path = &uart1; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + cover { + label = "Cover"; + gpios = <&gpio5 12 GPIO_ACTIVE_LOW>; + linux,code = <SW_LID>; + linux,input-type = <EV_SW>; + wakeup-source; + }; + + fl { + label = "Frontlight"; + gpios = <&gpio3 26 GPIO_ACTIVE_LOW>; + linux,code = <KEY_BRIGHTNESS_CYCLE>; + }; + + home { + label = "Home"; + gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; + linux,code = <KEY_HOME>; + }; + + power { + label = "Power"; + gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; + linux,code = <KEY_POWER>; + wakeup-source; + }; + }; + + leds: leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led>; + + on { + label = "tolinoshine2hd:white:on"; + gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + linux,default-trigger = "timer"; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + reg_wifi: regulator-wifi { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi_power>; + regulator-name = "SD3_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi_reset>; + post-power-on-delay-ms = <20>; + reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + }; +}; + +&i2c1 { + pinctrl-names = "default","sleep"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_sleep>; + status = "okay"; + + /* TODO: embedded controller at 0x43 (driver missing) */ + +}; + +&i2c2 { + pinctrl-names = "default","sleep"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_sleep>; + clock-frequency = <100000>; + status = "okay"; + + zforce: touchscreen@50 { + compatible = "neonode,zforce"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_zforce>; + reg = <0x50>; + interrupt-parent = <&gpio5>; + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; + vdd-supply = <&ldo1_reg>; + reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + x-size = <1072>; + y-size = <1448>; + }; + + /* TODO: TPS65185 PMIC for E Ink at 0x68 */ + +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clock-frequency = <400000>; + status = "okay"; + + ricoh619: pmic@32 { + compatible = "ricoh,rc5t619"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ricoh_gpio>; + reg = <0x32>; + interrupt-parent = <&gpio5>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + system-power-controller; + + regulators { + dcdc1_reg: DCDC1 { + regulator-name = "DCDC1"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-max-microvolt = <900000>; + regulator-suspend-min-microvolt = <900000>; + }; + }; + + /* Core3_3V3 */ + dcdc2_reg: DCDC2 { + regulator-name = "DCDC2"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-max-microvolt = <3100000>; + regulator-suspend-min-microvolt = <3100000>; + }; + }; + + dcdc3_reg: DCDC3 { + regulator-name = "DCDC3"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-max-microvolt = <1140000>; + regulator-suspend-min-microvolt = <1140000>; + }; + }; + + /* Core4_1V2 */ + dcdc4_reg: DCDC4 { + regulator-name = "DCDC4"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-max-microvolt = <1140000>; + regulator-suspend-min-microvolt = <1140000>; + }; + }; + + /* Core4_1V8 */ + dcdc5_reg: DCDC5 { + regulator-name = "DCDC5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-max-microvolt = <1700000>; + regulator-suspend-min-microvolt = <1700000>; + }; + }; + + /* IR_3V3 */ + ldo1_reg: LDO1 { + regulator-name = "LDO1"; + regulator-boot-on; + }; + + /* Core1_3V3 */ + ldo2_reg: LDO2 { + regulator-name = "LDO2"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-max-microvolt = <3000000>; + regulator-suspend-min-microvolt = <3000000>; + }; + }; + + /* Core5_1V2 */ + ldo3_reg: LDO3 { + regulator-name = "LDO3"; + regulator-always-on; + regulator-boot-on; + }; + + ldo4_reg: LDO4 { + regulator-name = "LDO4"; + regulator-boot-on; + }; + + /* SPD_3V3 */ + ldo5_reg: LDO5 { + regulator-name = "LDO5"; + regulator-always-on; + regulator-boot-on; + }; + + /* DDR_0V6 */ + ldo6_reg: LDO6 { + regulator-name = "LDO6"; + regulator-always-on; + regulator-boot-on; + }; + + /* VDD_PWM */ + ldo7_reg: LDO7 { + regulator-name = "LDO7"; + regulator-always-on; + regulator-boot-on; + }; + + /* ldo_1v8 */ + ldo8_reg: LDO8 { + regulator-name = "LDO8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo9_reg: LDO9 { + regulator-name = "LDO9"; + regulator-boot-on; + }; + + ldo10_reg: LDO10 { + regulator-name = "LDO10"; + regulator-boot-on; + }; + + ldortc1_reg: LDORTC1 { + regulator-name = "LDORTC1"; + regulator-always-on; + regulator-boot-on; + }; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_gpio_keys: gpio-keysgrp { + fsl,pins = < + MX6SL_PAD_SD1_DAT1__GPIO5_IO08 0x17059 + MX6SL_PAD_SD1_DAT4__GPIO5_IO12 0x17059 + MX6SL_PAD_KEY_COL1__GPIO3_IO26 0x17059 + MX6SL_PAD_KEY_ROW0__GPIO3_IO25 0x17059 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX6SL_PAD_LCD_DAT0__GPIO2_IO20 0x79 + MX6SL_PAD_LCD_DAT1__GPIO2_IO21 0x79 + MX6SL_PAD_LCD_DAT2__GPIO2_IO22 0x79 + MX6SL_PAD_LCD_DAT3__GPIO2_IO23 0x79 + MX6SL_PAD_LCD_DAT4__GPIO2_IO24 0x79 + MX6SL_PAD_LCD_DAT5__GPIO2_IO25 0x79 + MX6SL_PAD_LCD_DAT6__GPIO2_IO26 0x79 + MX6SL_PAD_LCD_DAT7__GPIO2_IO27 0x79 + MX6SL_PAD_LCD_DAT8__GPIO2_IO28 0x79 + MX6SL_PAD_LCD_DAT9__GPIO2_IO29 0x79 + MX6SL_PAD_LCD_DAT10__GPIO2_IO30 0x79 + MX6SL_PAD_LCD_DAT11__GPIO2_IO31 0x79 + MX6SL_PAD_LCD_DAT12__GPIO3_IO00 0x79 + MX6SL_PAD_LCD_DAT13__GPIO3_IO01 0x79 + MX6SL_PAD_LCD_DAT14__GPIO3_IO02 0x79 + MX6SL_PAD_LCD_DAT15__GPIO3_IO03 0x79 + MX6SL_PAD_LCD_DAT16__GPIO3_IO04 0x79 + MX6SL_PAD_LCD_DAT17__GPIO3_IO05 0x79 + MX6SL_PAD_LCD_DAT18__GPIO3_IO06 0x79 + MX6SL_PAD_LCD_DAT19__GPIO3_IO07 0x79 + MX6SL_PAD_LCD_DAT20__GPIO3_IO08 0x79 + MX6SL_PAD_LCD_DAT21__GPIO3_IO09 0x79 + MX6SL_PAD_LCD_DAT22__GPIO3_IO10 0x79 + MX6SL_PAD_LCD_DAT23__GPIO3_IO11 0x79 + MX6SL_PAD_LCD_CLK__GPIO2_IO15 0x79 + MX6SL_PAD_LCD_ENABLE__GPIO2_IO16 0x79 + MX6SL_PAD_LCD_HSYNC__GPIO2_IO17 0x79 + MX6SL_PAD_LCD_VSYNC__GPIO2_IO18 0x79 + MX6SL_PAD_LCD_RESET__GPIO2_IO19 0x79 + MX6SL_PAD_KEY_COL3__GPIO3_IO30 0x79 + MX6SL_PAD_KEY_ROW7__GPIO4_IO07 0x79 + MX6SL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x79 + MX6SL_PAD_KEY_COL5__GPIO4_IO02 0x79 + MX6SL_PAD_KEY_ROW6__GPIO4_IO05 0x79 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x4001f8b1 + MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x4001f8b1 + >; + }; + + pinctrl_i2c1_sleep: i2c1grp-sleep { + fsl,pins = < + MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x400108b1 + MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x400108b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x4001f8b1 + MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x4001f8b1 + >; + }; + + pinctrl_i2c2_sleep: i2c2grp-sleep { + fsl,pins = < + MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x400108b1 + MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x400108b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6SL_PAD_REF_CLK_24M__I2C3_SCL 0x4001f8b1 + MX6SL_PAD_REF_CLK_32K__I2C3_SDA 0x4001f8b1 + >; + }; + + pinctrl_led: ledgrp { + fsl,pins = < + MX6SL_PAD_SD1_DAT2__GPIO5_IO13 0x17059 + >; + }; + + pinctrl_ricoh_gpio: ricoh_gpiogrp { + fsl,pins = < + MX6SL_PAD_SD1_CLK__GPIO5_IO15 0x1b8b1 /* ricoh619 chg */ + MX6SL_PAD_SD1_DAT0__GPIO5_IO11 0x1b8b1 /* ricoh619 irq */ + MX6SL_PAD_KEY_COL2__GPIO3_IO28 0x1b8b1 /* ricoh619 bat_low_int */ + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1 + MX6SL_PAD_UART1_RXD__UART1_TX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg1: usbotg1grp { + fsl,pins = < + MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6SL_PAD_SD2_CLK__SD2_CLK 0x13059 + MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp-100mhz { + fsl,pins = < + MX6SL_PAD_SD2_CMD__SD2_CMD 0x170b9 + MX6SL_PAD_SD2_CLK__SD2_CLK 0x130b9 + MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 + MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 + MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 + MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp-200mhz { + fsl,pins = < + MX6SL_PAD_SD2_CMD__SD2_CMD 0x170f9 + MX6SL_PAD_SD2_CLK__SD2_CLK 0x130f9 + MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 + MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 + MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 + MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc2_sleep: usdhc2grp-sleep { + fsl,pins = < + MX6SL_PAD_SD2_CMD__GPIO5_IO04 0x100f9 + MX6SL_PAD_SD2_CLK__GPIO5_IO05 0x100f9 + MX6SL_PAD_SD2_DAT0__GPIO5_IO01 0x100f9 + MX6SL_PAD_SD2_DAT1__GPIO4_IO30 0x100f9 + MX6SL_PAD_SD2_DAT2__GPIO5_IO03 0x100f9 + MX6SL_PAD_SD2_DAT3__GPIO4_IO28 0x100f9 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6SL_PAD_SD3_CMD__SD3_CMD 0x11059 + MX6SL_PAD_SD3_CLK__SD3_CLK 0x11059 + MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x11059 + MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x11059 + MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x11059 + MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x11059 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { + fsl,pins = < + MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9 + MX6SL_PAD_SD3_CLK__SD3_CLK 0x170b9 + MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 + MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 + MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 + MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { + fsl,pins = < + MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9 + MX6SL_PAD_SD3_CLK__SD3_CLK 0x170f9 + MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 + MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 + MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 + MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc3_sleep: usdhc3grp-sleep { + fsl,pins = < + MX6SL_PAD_SD3_CMD__GPIO5_IO21 0x100c1 + MX6SL_PAD_SD3_CLK__GPIO5_IO18 0x100c1 + MX6SL_PAD_SD3_DAT0__GPIO5_IO19 0x100c1 + MX6SL_PAD_SD3_DAT1__GPIO5_IO20 0x100c1 + MX6SL_PAD_SD3_DAT2__GPIO5_IO16 0x100c1 + MX6SL_PAD_SD3_DAT3__GPIO5_IO17 0x100c1 + >; + }; + + pinctrl_wifi_power: wifi-powergrp { + fsl,pins = < + MX6SL_PAD_SD2_DAT6__GPIO4_IO29 0x10059 /* WIFI_3V3_ON */ + >; + }; + + pinctrl_wifi_reset: wifi-resetgrp { + fsl,pins = < + MX6SL_PAD_SD2_DAT7__GPIO5_IO00 0x10059 /* WIFI_RST */ + >; + }; + + pinctrl_zforce: zforcegrp { + fsl,pins = < + MX6SL_PAD_SD1_DAT3__GPIO5_IO06 0x17059 /* TP_INT */ + MX6SL_PAD_SD1_DAT5__GPIO5_IO09 0x10059 /* TP_RST */ + >; + }; +}; + +®_vdd1p1 { + vin-supply = <&dcdc2_reg>; +}; + +®_vdd2p5 { + vin-supply = <&dcdc2_reg>; +}; + +®_arm { + vin-supply = <&dcdc3_reg>; +}; + +®_soc { + vin-supply = <&dcdc1_reg>; +}; + +®_pu { + vin-supply = <&dcdc1_reg>; +}; + +&snvs_rtc { + /* + * We are using the RTC in the PMIC, but this one is not disabled + * in imx6sl.dtsi. + */ + status = "disabled"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + pinctrl-3 = <&pinctrl_usdhc2_sleep>; + non-removable; + status = "okay"; + + /* internal uSD card */ +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + pinctrl-3 = <&pinctrl_usdhc3_sleep>; + vmmc-supply = <®_wifi>; + mmc-pwrseq = <&wifi_pwrseq>; + cap-power-off-card; + non-removable; + status = "okay"; + + /* + * 37NB-E60QF0+4A2: CyberTan WC121 (BCM43362) SDIO WiFi + * 37NB-E60QF0+4A3: RTL8189F SDIO WiFi + */ +}; + +&usbotg1 { + pinctrl-names = "default"; + disable-over-current; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index 1c7180f28539..91a8c54d5e11 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -939,8 +939,10 @@ }; rngb: rngb@21b4000 { + compatible = "fsl,imx6sl-rngb", "fsl,imx25-rngb"; reg = <0x021b4000 0x4000>; interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SL_CLK_DUMMY>; }; weim: weim@21b8000 { diff --git a/arch/arm/boot/dts/imx6sll-evk.dts b/arch/arm/boot/dts/imx6sll-evk.dts index c755cbdb7cde..32b3d82fec53 100644 --- a/arch/arm/boot/dts/imx6sll-evk.dts +++ b/arch/arm/boot/dts/imx6sll-evk.dts @@ -132,6 +132,31 @@ }; }; }; + + sound { + compatible = "fsl,imx6sl-evk-wm8962", "fsl,imx-audio-wm8962"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hp>; + model = "wm8962-audio"; + audio-cpu = <&ssi2>; + audio-codec = <&wm8962>; + audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "Ext Spk", "SPKOUTL", + "Ext Spk", "SPKOUTR", + "AMIC", "MICBIAS", + "IN3R", "AMIC"; + mux-int-port = <2>; + mux-ext-port = <3>; + hp-det-gpio = <&gpio4 24 GPIO_ACTIVE_LOW>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux3>; + status = "okay"; }; &cpu0 { @@ -247,6 +272,27 @@ }; }; +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + wm8962: audio-codec@1a { + compatible = "wlf,wm8962"; + reg = <0x1a>; + clocks = <&clks IMX6SLL_CLK_EXTERN_AUDIO>; + DCVDD-supply = <&vgen3_reg>; + DBVDD-supply = <®_aud3v>; + AVDD-supply = <&vgen3_reg>; + CPVDD-supply = <&vgen3_reg>; + MICVDD-supply = <®_aud3v>; + PLLVDD-supply = <&vgen3_reg>; + SPKVDD1-supply = <®_aud4v>; + SPKVDD2-supply = <®_aud4v>; + }; +}; + &lcdif { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lcd>; @@ -274,6 +320,10 @@ status = "okay"; }; +&ssi2 { + status = "okay"; +}; + &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; @@ -330,6 +380,22 @@ }; &iomuxc { + pinctrl_audmux3: audmux3grp { + fsl,pins = < + MX6SLL_PAD_AUD_TXC__AUD3_TXC 0x4130b0 + MX6SLL_PAD_AUD_TXFS__AUD3_TXFS 0x4130b0 + MX6SLL_PAD_AUD_TXD__AUD3_TXD 0x4110b0 + MX6SLL_PAD_AUD_RXD__AUD3_RXD 0x4130b0 + MX6SLL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x4130b0 + >; + }; + + pinctrl_hp: hpgrp { + fsl,pins = < + MX6SLL_PAD_GPIO4_IO24__GPIO4_IO24 0x17059 /* HP DETECT */ + >; + }; + pinctrl_reg_sd3_vmmc: sd3vmmcgrp { fsl,pins = < MX6SLL_PAD_KEY_COL6__GPIO4_IO04 0x17059 @@ -449,6 +515,13 @@ >; }; + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6SLL_PAD_AUD_RXFS__I2C3_SCL 0x4041b8b1 + MX6SLL_PAD_AUD_RXC__I2C3_SDA 0x4041b8b1 + >; + }; + pinctrl_lcd: lcdgrp { fsl,pins = < MX6SLL_PAD_LCD_DATA00__LCD_DATA00 0x79 diff --git a/arch/arm/boot/dts/imx6sll.dtsi b/arch/arm/boot/dts/imx6sll.dtsi index fb5d3bc50c6b..0b622201a1f3 100644 --- a/arch/arm/boot/dts/imx6sll.dtsi +++ b/arch/arm/boot/dts/imx6sll.dtsi @@ -786,6 +786,13 @@ clocks = <&clks IMX6SLL_CLK_MMDC_P0_IPG>; }; + rngb: rng@21b4000 { + compatible = "fsl,imx6sll-rngb", "fsl,imx25-rngb"; + reg = <0x021b4000 0x4000>; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SLL_CLK_DUMMY>; + }; + ocotp: efuse@21bc000 { #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/imx6sx-sdb.dtsi b/arch/arm/boot/dts/imx6sx-sdb.dtsi index b8c23eba9dc7..1351d7f70a54 100644 --- a/arch/arm/boot/dts/imx6sx-sdb.dtsi +++ b/arch/arm/boot/dts/imx6sx-sdb.dtsi @@ -153,6 +153,8 @@ sound { compatible = "fsl,imx6sx-sdb-wm8962", "fsl,imx-audio-wm8962"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hp>; model = "wm8962-audio"; ssi-controller = <&ssi2>; audio-codec = <&codec>; @@ -165,6 +167,7 @@ "IN3R", "AMIC"; mux-int-port = <2>; mux-ext-port = <6>; + hp-det-gpio = <&gpio1 17 GPIO_ACTIVE_LOW>; }; panel { @@ -468,6 +471,12 @@ >; }; + pinctrl_hp: hpgrp { + fsl,pins = < + MX6SX_PAD_CSI_DATA03__GPIO1_IO_17 0x17059 + >; + }; + pinctrl_i2c1: i2c1grp { fsl,pins = < MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1 diff --git a/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts b/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts index d25e27d0315f..5547916870c7 100644 --- a/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts +++ b/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts @@ -93,7 +93,7 @@ &ecspi4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi4>; - cs-gpios = <&gpio7 4 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio7 4 GPIO_ACTIVE_LOW>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index b480dfa9e251..dfdca1804f9f 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -213,7 +213,7 @@ clocks = <&clks IMX6SX_CLK_APBH_DMA>; }; - gpmi: gpmi-nand@1806000{ + gpmi: nand-controller@1806000{ compatible = "fsl,imx6sx-gpmi-nand"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/imx6ul-kontron-n6x1x-s.dtsi b/arch/arm/boot/dts/imx6ul-kontron-n6x1x-s.dtsi index a35be2a369b3..770f59b23102 100644 --- a/arch/arm/boot/dts/imx6ul-kontron-n6x1x-s.dtsi +++ b/arch/arm/boot/dts/imx6ul-kontron-n6x1x-s.dtsi @@ -84,7 +84,7 @@ }; &ecspi1 { - cs-gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6ul-kontron-n6x1x-som-common.dtsi b/arch/arm/boot/dts/imx6ul-kontron-n6x1x-som-common.dtsi index 61ba21a605a8..2a449a3c1ae2 100644 --- a/arch/arm/boot/dts/imx6ul-kontron-n6x1x-som-common.dtsi +++ b/arch/arm/boot/dts/imx6ul-kontron-n6x1x-som-common.dtsi @@ -14,7 +14,7 @@ }; &ecspi2 { - cs-gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi2>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi b/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi index 8d5f8dc6ad58..f1513e676c2f 100644 --- a/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi +++ b/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi @@ -106,7 +106,7 @@ &ecspi3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi3>; - cs-gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi index 2b088f210331..d7d9f3e46b92 100644 --- a/arch/arm/boot/dts/imx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul.dtsi @@ -174,7 +174,7 @@ clocks = <&clks IMX6UL_CLK_APBHDMA>; }; - gpmi: gpmi-nand@1806000 { + gpmi: nand-controller@1806000 { compatible = "fsl,imx6q-gpmi-nand"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi index 6cf95939121d..4436556624d6 100644 --- a/arch/arm/boot/dts/imx6ull-colibri.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi @@ -68,7 +68,7 @@ /* Colibri SPI */ &ecspi1 { - cs-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; }; diff --git a/arch/arm/boot/dts/imx6ull.dtsi b/arch/arm/boot/dts/imx6ull.dtsi index fcde7f77ae42..9bf67490ac49 100644 --- a/arch/arm/boot/dts/imx6ull.dtsi +++ b/arch/arm/boot/dts/imx6ull.dtsi @@ -68,6 +68,13 @@ clock-names = "dcp"; }; + rngb: rng@2284000 { + compatible = "fsl,imx6ull-rngb", "fsl,imx25-rngb"; + reg = <0x02284000 0x4000>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_DUMMY>; + }; + iomuxc_snvs: iomuxc-snvs@2290000 { compatible = "fsl,imx6ull-iomuxc-snvs"; reg = <0x02290000 0x4000>; diff --git a/arch/arm/boot/dts/imx7-colibri.dtsi b/arch/arm/boot/dts/imx7-colibri.dtsi index e18e89dec879..62b771c1d5a9 100644 --- a/arch/arm/boot/dts/imx7-colibri.dtsi +++ b/arch/arm/boot/dts/imx7-colibri.dtsi @@ -60,7 +60,7 @@ &ecspi3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs>; - cs-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; }; &fec1 { diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts index 17cca8a9f77b..ac0751bc1177 100644 --- a/arch/arm/boot/dts/imx7d-sdb.dts +++ b/arch/arm/boot/dts/imx7d-sdb.dts @@ -146,6 +146,24 @@ }; }; }; + + sound { + compatible = "fsl,imx7d-evk-wm8960", + "fsl,imx-audio-wm8960"; + model = "wm8960-audio"; + audio-cpu = <&sai1>; + audio-codec = <&codec>; + hp-det-gpio = <&gpio2 28 GPIO_ACTIVE_HIGH>; + audio-routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT1", "AMIC", + "AMIC", "MICB"; + }; }; &adc1 { @@ -169,7 +187,7 @@ &ecspi3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi3>; - cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; status = "okay"; tsc2046@0 { @@ -363,6 +381,13 @@ clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; clock-names = "mclk"; wlf,shared-lrclk; + wlf,hp-cfg = <2 2 3>; + wlf,gpio-cfg = <1 3>; + assigned-clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_SRC>, + <&clks IMX7D_PLL_AUDIO_POST_DIV>, + <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; + assigned-clock-rates = <0>, <884736000>, <12288000>; }; }; @@ -391,6 +416,28 @@ vin-supply = <&sw2_reg>; }; +&sai1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>, + <&clks IMX7D_PLL_AUDIO_POST_DIV>, + <&clks IMX7D_SAI1_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; + assigned-clock-rates = <0>, <884736000>, <36864000>; + status = "okay"; +}; + +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3 &pinctrl_sai3_mclk>; + assigned-clocks = <&clks IMX7D_SAI3_ROOT_SRC>, + <&clks IMX7D_PLL_AUDIO_POST_DIV>, + <&clks IMX7D_SAI3_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; + assigned-clock-rates = <0>, <884736000>, <36864000>; + status = "okay"; +}; + &snvs_pwrkey { status = "okay"; }; @@ -550,6 +597,7 @@ pinctrl_hog: hoggrp { fsl,pins = < MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x34 /* bt reg on */ + MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x59 /* headphone detect */ >; }; @@ -615,6 +663,33 @@ >; }; + pinctrl_sai1: sai1grp { + fsl,pins = < + MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f + MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f + MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC 0x1f + MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x30 + MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x1f + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK 0x1f + MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC 0x1f + MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0 0x30 + MX7D_PAD_SAI2_RX_DATA__SAI2_RX_DATA0 0x1f + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX7D_PAD_UART3_TX_DATA__SAI3_TX_BCLK 0x1f + MX7D_PAD_UART3_CTS_B__SAI3_TX_SYNC 0x1f + MX7D_PAD_UART3_RTS_B__SAI3_TX_DATA0 0x30 + >; + }; + pinctrl_spi4: spi4grp { fsl,pins = < MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x59 @@ -776,4 +851,10 @@ MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x14 >; }; + + pinctrl_sai3_mclk: sai3grp_mclk { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO03__SAI3_MCLK 0x1f + >; + }; }; diff --git a/arch/arm/boot/dts/imx7d-zii-rmu2.dts b/arch/arm/boot/dts/imx7d-zii-rmu2.dts index 7cb6153fc650..1065941807e8 100644 --- a/arch/arm/boot/dts/imx7d-zii-rmu2.dts +++ b/arch/arm/boot/dts/imx7d-zii-rmu2.dts @@ -39,7 +39,7 @@ &ecspi1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>; status = "okay"; flash@0 { diff --git a/arch/arm/boot/dts/imx7d-zii-rpu2.dts b/arch/arm/boot/dts/imx7d-zii-rpu2.dts index cbf0dbb4c198..893bd30aa2a3 100644 --- a/arch/arm/boot/dts/imx7d-zii-rpu2.dts +++ b/arch/arm/boot/dts/imx7d-zii-rpu2.dts @@ -193,7 +193,7 @@ &ecspi1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>; status = "okay"; flash@0 { diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index 1cfaf410aa43..84d9cc13afb9 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -1162,6 +1162,19 @@ status = "disabled"; }; + qspi: spi@30bb0000 { + compatible = "fsl,imx7d-qspi"; + reg = <0x30bb0000 0x10000>, <0x60000000 0x10000000>; + reg-names = "QuadSPI", "QuadSPI-memory"; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_QSPI_ROOT_CLK>, + <&clks IMX7D_QSPI_ROOT_CLK>; + clock-names = "qspi_en", "qspi"; + status = "disabled"; + }; + sdma: sdma@30bd0000 { compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma"; reg = <0x30bd0000 0x10000>; @@ -1208,7 +1221,7 @@ clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>; }; - gpmi: gpmi-nand@33002000{ + gpmi: nand-controller@33002000{ compatible = "fsl,imx7d-gpmi-nand"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/iwg20d-q7-common.dtsi b/arch/arm/boot/dts/iwg20d-q7-common.dtsi index ebbe1518ef8a..63cafd220dba 100644 --- a/arch/arm/boot/dts/iwg20d-q7-common.dtsi +++ b/arch/arm/boot/dts/iwg20d-q7-common.dtsi @@ -57,7 +57,7 @@ lvds-receiver { compatible = "ti,ds90cf384a", "lvds-decoder"; - powerdown-gpios = <&gpio7 25 GPIO_ACTIVE_LOW>; + power-supply = <&vcc_3v3_tft1>; ports { #address-cells = <1>; @@ -81,6 +81,7 @@ panel { compatible = "edt,etm0700g0dh6"; backlight = <&lcd_backlight>; + power-supply = <&vcc_3v3_tft1>; port { panel_in: endpoint { @@ -113,6 +114,17 @@ }; }; + vcc_3v3_tft1: regulator-panel { + compatible = "regulator-fixed"; + + regulator-name = "vcc-3v3-tft1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + startup-delay-us = <500>; + gpio = <&gpio7 25 GPIO_ACTIVE_HIGH>; + }; + vcc_sdhi1: regulator-vcc-sdhi1 { compatible = "regulator-fixed"; @@ -207,6 +219,7 @@ reg = <0x38>; interrupt-parent = <&gpio2>; interrupts = <12 IRQ_TYPE_EDGE_FALLING>; + vcc-supply = <&vcc_3v3_tft1>; }; }; diff --git a/arch/arm/boot/dts/logicpd-som-lv-baseboard.dtsi b/arch/arm/boot/dts/logicpd-som-lv-baseboard.dtsi index 395e05f10d36..7d0468a23781 100644 --- a/arch/arm/boot/dts/logicpd-som-lv-baseboard.dtsi +++ b/arch/arm/boot/dts/logicpd-som-lv-baseboard.dtsi @@ -79,7 +79,7 @@ }; &dss { - status = "ok"; + status = "okay"; vdds_dsi-supply = <&vpll2>; vdda_video-supply = <&video_reg>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/logicpd-torpedo-baseboard.dtsi b/arch/arm/boot/dts/logicpd-torpedo-baseboard.dtsi index b0f6613e6d54..533a47bc4a53 100644 --- a/arch/arm/boot/dts/logicpd-torpedo-baseboard.dtsi +++ b/arch/arm/boot/dts/logicpd-torpedo-baseboard.dtsi @@ -115,7 +115,7 @@ }; &dss { - status = "ok"; + status = "okay"; vdds_dsi-supply = <&vpll2>; vdda_video-supply = <&vpll2>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi index eadb0832bcfc..7649dd1e0b9e 100644 --- a/arch/arm/boot/dts/meson.dtsi +++ b/arch/arm/boot/dts/meson.dtsi @@ -11,13 +11,6 @@ #size-cells = <1>; interrupt-parent = <&gic>; - L2: cache-controller@c4200000 { - compatible = "arm,pl310-cache"; - reg = <0xc4200000 0x1000>; - cache-unified; - cache-level = <2>; - }; - soc { compatible = "simple-bus"; #address-cells = <1>; @@ -172,6 +165,13 @@ }; }; + L2: cache-controller@c4200000 { + compatible = "arm,pl310-cache"; + reg = <0xc4200000 0x1000>; + cache-unified; + cache-level = <2>; + }; + periph: bus@c4300000 { compatible = "simple-bus"; reg = <0xc4300000 0x10000>; diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index 277c0bb10453..04688e8abce2 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -240,8 +240,6 @@ <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, diff --git a/arch/arm/boot/dts/mmp2-olpc-xo-1-75.dts b/arch/arm/boot/dts/mmp2-olpc-xo-1-75.dts index f1a41152e9dd..adde62d6fce7 100644 --- a/arch/arm/boot/dts/mmp2-olpc-xo-1-75.dts +++ b/arch/arm/boot/dts/mmp2-olpc-xo-1-75.dts @@ -227,12 +227,12 @@ /delete-property/ #size-cells; spi-slave; status = "okay"; - ready-gpio = <&gpio 125 GPIO_ACTIVE_HIGH>; + ready-gpios = <&gpio 125 GPIO_ACTIVE_HIGH>; slave { compatible = "olpc,xo1.75-ec"; spi-cpha; - cmd-gpio = <&gpio 155 GPIO_ACTIVE_HIGH>; + cmd-gpios = <&gpio 155 GPIO_ACTIVE_HIGH>; }; }; diff --git a/arch/arm/boot/dts/mmp3.dtsi b/arch/arm/boot/dts/mmp3.dtsi index cc4efd0efabd..4ae630d37d09 100644 --- a/arch/arm/boot/dts/mmp3.dtsi +++ b/arch/arm/boot/dts/mmp3.dtsi @@ -296,6 +296,7 @@ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; clocks = <&soc_clocks MMP2_CLK_CCIC0>; clock-names = "axi"; + power-domains = <&soc_clocks MMP3_POWER_DOMAIN_CAMERA>; #clock-cells = <0>; clock-output-names = "mclk"; status = "disabled"; @@ -307,6 +308,7 @@ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; clocks = <&soc_clocks MMP2_CLK_CCIC1>; clock-names = "axi"; + power-domains = <&soc_clocks MMP3_POWER_DOMAIN_CAMERA>; #clock-cells = <0>; clock-output-names = "mclk"; status = "disabled"; diff --git a/arch/arm/boot/dts/motorola-mapphone-common.dtsi b/arch/arm/boot/dts/motorola-mapphone-common.dtsi index 1990239cc6af..d5ded4f794df 100644 --- a/arch/arm/boot/dts/motorola-mapphone-common.dtsi +++ b/arch/arm/boot/dts/motorola-mapphone-common.dtsi @@ -207,8 +207,9 @@ }; }; - lcd0: display { - compatible = "panel-dsi-cm"; + lcd0: panel@0 { + compatible = "motorola,droid4-panel", "panel-dsi-cm"; + reg = <0>; label = "lcd0"; vddi-supply = <&lcd_regulator>; reset-gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; /* gpio101 */ @@ -217,6 +218,7 @@ width-mm = <50>; height-mm = <89>; + rotation = <90>; panel-timing { clock-frequency = <0>; /* Calculated by dsi */ diff --git a/arch/arm/boot/dts/mpa1600.dts b/arch/arm/boot/dts/mpa1600.dts index a5c91c240db9..005c2758e229 100644 --- a/arch/arm/boot/dts/mpa1600.dts +++ b/arch/arm/boot/dts/mpa1600.dts @@ -11,7 +11,7 @@ model = "Phontech MPA 1600"; compatible = "phontech,mpa1600", "atmel,at91rm9200"; - memory { + memory@20000000 { reg = <0x20000000 0x4000000>; }; diff --git a/arch/arm/boot/dts/mps2.dtsi b/arch/arm/boot/dts/mps2.dtsi index 96fb5a5cf4d3..37f5023f529c 100644 --- a/arch/arm/boot/dts/mps2.dtsi +++ b/arch/arm/boot/dts/mps2.dtsi @@ -161,9 +161,11 @@ }; timer2: dual-timer@2000 { - compatible = "arm,sp804"; + compatible = "arm,sp804", "arm,primecell"; reg = <0x2000 0x1000>; - clocks = <&sysclk>; + clocks = <&sysclk>, <&sysclk>, <&sysclk>; + clock-names = "timer0clk", "timer1clk", + "apb_pclk"; interrupts = <10>; status = "disabled"; }; @@ -197,8 +199,8 @@ arm,primecell-periphid = <0x00141805>; reg = <0x8000 0x1000>; interrupts = <0>; - clocks = <&sysclk>; - clock-names = "apb_pclk"; + clocks = <&sysclk>, <&sysclk>; + clock-names = "wdog_clk", "apb_pclk"; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/infinity-msc313-breadbee_crust.dts b/arch/arm/boot/dts/mstar-infinity-msc313-breadbee_crust.dts index f24c5580d3e4..f9db2ff86f2d 100644 --- a/arch/arm/boot/dts/infinity-msc313-breadbee_crust.dts +++ b/arch/arm/boot/dts/mstar-infinity-msc313-breadbee_crust.dts @@ -5,7 +5,7 @@ */ /dts-v1/; -#include "infinity-msc313.dtsi" +#include "mstar-infinity-msc313.dtsi" / { model = "BreadBee Crust"; diff --git a/arch/arm/boot/dts/infinity-msc313.dtsi b/arch/arm/boot/dts/mstar-infinity-msc313.dtsi index 42f2b5552c77..3499fde263be 100644 --- a/arch/arm/boot/dts/infinity-msc313.dtsi +++ b/arch/arm/boot/dts/mstar-infinity-msc313.dtsi @@ -4,7 +4,7 @@ * Author: Daniel Palmer <daniel@thingy.jp> */ -#include "infinity.dtsi" +#include "mstar-infinity.dtsi" / { memory@20000000 { diff --git a/arch/arm/boot/dts/infinity.dtsi b/arch/arm/boot/dts/mstar-infinity.dtsi index cd911adef014..cd911adef014 100644 --- a/arch/arm/boot/dts/infinity.dtsi +++ b/arch/arm/boot/dts/mstar-infinity.dtsi diff --git a/arch/arm/boot/dts/infinity3-msc313e-breadbee.dts b/arch/arm/boot/dts/mstar-infinity3-msc313e-breadbee.dts index 1f93401c8530..f0eda80a95cc 100644 --- a/arch/arm/boot/dts/infinity3-msc313e-breadbee.dts +++ b/arch/arm/boot/dts/mstar-infinity3-msc313e-breadbee.dts @@ -5,7 +5,7 @@ */ /dts-v1/; -#include "infinity3-msc313e.dtsi" +#include "mstar-infinity3-msc313e.dtsi" / { model = "BreadBee"; diff --git a/arch/arm/boot/dts/infinity3-msc313e.dtsi b/arch/arm/boot/dts/mstar-infinity3-msc313e.dtsi index 4e7239afd823..f581b6f89555 100644 --- a/arch/arm/boot/dts/infinity3-msc313e.dtsi +++ b/arch/arm/boot/dts/mstar-infinity3-msc313e.dtsi @@ -4,7 +4,7 @@ * Author: Daniel Palmer <daniel@thingy.jp> */ -#include "infinity3.dtsi" +#include "mstar-infinity3.dtsi" / { memory@20000000 { diff --git a/arch/arm/boot/dts/infinity3.dtsi b/arch/arm/boot/dts/mstar-infinity3.dtsi index 9b918c802654..9857e2a9934d 100644 --- a/arch/arm/boot/dts/infinity3.dtsi +++ b/arch/arm/boot/dts/mstar-infinity3.dtsi @@ -4,7 +4,7 @@ * Author: Daniel Palmer <daniel@thingy.jp> */ -#include "infinity.dtsi" +#include "mstar-infinity.dtsi" &imi { reg = <0xa0000000 0x20000>; diff --git a/arch/arm/boot/dts/mercury5-ssc8336n-midrived08.dts b/arch/arm/boot/dts/mstar-mercury5-ssc8336n-midrived08.dts index f24bd8cb8e60..7306b737d9c4 100644 --- a/arch/arm/boot/dts/mercury5-ssc8336n-midrived08.dts +++ b/arch/arm/boot/dts/mstar-mercury5-ssc8336n-midrived08.dts @@ -5,7 +5,7 @@ */ /dts-v1/; -#include "mercury5-ssc8336n.dtsi" +#include "mstar-mercury5-ssc8336n.dtsi" / { model = "70mai Midrive D08"; diff --git a/arch/arm/boot/dts/mercury5-ssc8336n.dtsi b/arch/arm/boot/dts/mstar-mercury5-ssc8336n.dtsi index 7d4a4630c25c..3f5a4c029744 100644 --- a/arch/arm/boot/dts/mercury5-ssc8336n.dtsi +++ b/arch/arm/boot/dts/mstar-mercury5-ssc8336n.dtsi @@ -4,7 +4,7 @@ * Author: Daniel Palmer <daniel@thingy.jp> */ -#include "mercury5.dtsi" +#include "mstar-mercury5.dtsi" / { memory@20000000 { diff --git a/arch/arm/boot/dts/mercury5.dtsi b/arch/arm/boot/dts/mstar-mercury5.dtsi index a7d0dd9d6132..a7d0dd9d6132 100644 --- a/arch/arm/boot/dts/mercury5.dtsi +++ b/arch/arm/boot/dts/mstar-mercury5.dtsi diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi index 3b7b9b793736..f07880561e11 100644 --- a/arch/arm/boot/dts/mstar-v7.dtsi +++ b/arch/arm/boot/dts/mstar-v7.dtsi @@ -85,6 +85,25 @@ mask = <0x79>; }; + intc_fiq: interrupt-controller@201310 { + compatible = "mstar,mst-intc"; + reg = <0x201310 0x40>; + #interrupt-cells = <3>; + interrupt-controller; + interrupt-parent = <&gic>; + mstar,irqs-map-range = <96 127>; + }; + + intc_irq: interrupt-controller@201350 { + compatible = "mstar,mst-intc"; + reg = <0x201350 0x40>; + #interrupt-cells = <3>; + interrupt-controller; + interrupt-parent = <&gic>; + mstar,irqs-map-range = <32 95>; + mstar,intc-no-eoi; + }; + l3bridge: l3bridge@204400 { compatible = "mstar,l3bridge"; reg = <0x204400 0x200>; @@ -94,6 +113,7 @@ compatible = "ns16550a"; reg = <0x221000 0x100>; reg-shift = <3>; + interrupts-extended = <&intc_irq GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <172000000>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi index 39b3a2f4bef4..fade14284017 100644 --- a/arch/arm/boot/dts/mt2701.dtsi +++ b/arch/arm/boot/dts/mt2701.dtsi @@ -569,6 +569,19 @@ <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>; }; + jpegenc: jpegenc@1500a000 { + compatible = "mediatek,mt2701-jpgenc", + "mediatek,mtk-jpgenc"; + reg = <0 0x1500a000 0 0x1000>; + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_LOW>; + clocks = <&imgsys CLK_IMG_VENC>; + clock-names = "jpgenc"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>; + mediatek,larb = <&larb2>; + iommus = <&iommu MT2701_M4U_PORT_JPGENC_RDMA>, + <&iommu MT2701_M4U_PORT_JPGENC_BSDMA>; + }; + vdecsys: syscon@16000000 { compatible = "mediatek,mt2701-vdecsys", "syscon"; reg = <0 0x16000000 0 0x1000>; diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi index 3a6b856e5b74..aea6809500d7 100644 --- a/arch/arm/boot/dts/mt7623.dtsi +++ b/arch/arm/boot/dts/mt7623.dtsi @@ -14,7 +14,6 @@ #include <dt-bindings/power/mt2701-power.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/phy/phy.h> -#include <dt-bindings/memory/mt2701-larb-port.h> #include <dt-bindings/reset/mt2701-resets.h> #include <dt-bindings/thermal/thermal.h> @@ -297,17 +296,6 @@ clock-names = "system-clk", "rtc-clk"; }; - smi_common: smi@1000c000 { - compatible = "mediatek,mt7623-smi-common", - "mediatek,mt2701-smi-common"; - reg = <0 0x1000c000 0 0x1000>; - clocks = <&infracfg CLK_INFRA_SMI>, - <&mmsys CLK_MM_SMI_COMMON>, - <&infracfg CLK_INFRA_SMI>; - clock-names = "apb", "smi", "async"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>; - }; - pwrap: pwrap@1000d000 { compatible = "mediatek,mt7623-pwrap", "mediatek,mt2701-pwrap"; @@ -339,17 +327,6 @@ reg = <0 0x10200100 0 0x1c>; }; - iommu: mmsys_iommu@10205000 { - compatible = "mediatek,mt7623-m4u", - "mediatek,mt2701-m4u"; - reg = <0 0x10205000 0 0x1000>; - interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>; - clocks = <&infracfg CLK_INFRA_M4U>; - clock-names = "bclk"; - mediatek,larbs = <&larb0 &larb1 &larb2>; - #iommu-cells = <1>; - }; - efuse: efuse@10206000 { compatible = "mediatek,mt7623-efuse", "mediatek,mt8173-efuse"; @@ -725,94 +702,6 @@ status = "disabled"; }; - g3dsys: syscon@13000000 { - compatible = "mediatek,mt7623-g3dsys", - "mediatek,mt2701-g3dsys", - "syscon"; - reg = <0 0x13000000 0 0x200>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - mali: gpu@13040000 { - compatible = "mediatek,mt7623-mali", "arm,mali-450"; - reg = <0 0x13040000 0 0x30000>; - interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_LOW>, - <GIC_SPI 171 IRQ_TYPE_LEVEL_LOW>, - <GIC_SPI 172 IRQ_TYPE_LEVEL_LOW>, - <GIC_SPI 173 IRQ_TYPE_LEVEL_LOW>, - <GIC_SPI 174 IRQ_TYPE_LEVEL_LOW>, - <GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>, - <GIC_SPI 176 IRQ_TYPE_LEVEL_LOW>, - <GIC_SPI 177 IRQ_TYPE_LEVEL_LOW>, - <GIC_SPI 178 IRQ_TYPE_LEVEL_LOW>, - <GIC_SPI 179 IRQ_TYPE_LEVEL_LOW>, - <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1", - "ppmmu1", "pp2", "ppmmu2", "pp3", "ppmmu3", - "pp"; - clocks = <&topckgen CLK_TOP_MMPLL>, - <&g3dsys CLK_G3DSYS_CORE>; - clock-names = "bus", "core"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_MFG>; - resets = <&g3dsys MT2701_G3DSYS_CORE_RST>; - }; - - mmsys: syscon@14000000 { - compatible = "mediatek,mt7623-mmsys", - "mediatek,mt2701-mmsys", - "syscon"; - reg = <0 0x14000000 0 0x1000>; - #clock-cells = <1>; - }; - - larb0: larb@14010000 { - compatible = "mediatek,mt7623-smi-larb", - "mediatek,mt2701-smi-larb"; - reg = <0 0x14010000 0 0x1000>; - mediatek,smi = <&smi_common>; - mediatek,larb-id = <0>; - clocks = <&mmsys CLK_MM_SMI_LARB0>, - <&mmsys CLK_MM_SMI_LARB0>; - clock-names = "apb", "smi"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>; - }; - - imgsys: syscon@15000000 { - compatible = "mediatek,mt7623-imgsys", - "mediatek,mt2701-imgsys", - "syscon"; - reg = <0 0x15000000 0 0x1000>; - #clock-cells = <1>; - }; - - larb2: larb@15001000 { - compatible = "mediatek,mt7623-smi-larb", - "mediatek,mt2701-smi-larb"; - reg = <0 0x15001000 0 0x1000>; - mediatek,smi = <&smi_common>; - mediatek,larb-id = <2>; - clocks = <&imgsys CLK_IMG_SMI_COMM>, - <&imgsys CLK_IMG_SMI_COMM>; - clock-names = "apb", "smi"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>; - }; - - jpegdec: jpegdec@15004000 { - compatible = "mediatek,mt7623-jpgdec", - "mediatek,mt2701-jpgdec"; - reg = <0 0x15004000 0 0x1000>; - interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>; - clocks = <&imgsys CLK_IMG_JPGDEC_SMI>, - <&imgsys CLK_IMG_JPGDEC>; - clock-names = "jpgdec-smi", - "jpgdec"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>; - mediatek,larb = <&larb2>; - iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>, - <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>; - }; - vdecsys: syscon@16000000 { compatible = "mediatek,mt7623-vdecsys", "mediatek,mt2701-vdecsys", @@ -821,18 +710,6 @@ #clock-cells = <1>; }; - larb1: larb@16010000 { - compatible = "mediatek,mt7623-smi-larb", - "mediatek,mt2701-smi-larb"; - reg = <0 0x16010000 0 0x1000>; - mediatek,smi = <&smi_common>; - mediatek,larb-id = <1>; - clocks = <&vdecsys CLK_VDEC_CKGEN>, - <&vdecsys CLK_VDEC_LARB>; - clock-names = "apb", "smi"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>; - }; - hifsys: syscon@1a000000 { compatible = "mediatek,mt7623-hifsys", "mediatek,mt2701-hifsys", diff --git a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts index 2b760f90f38c..e96aa0ed1ebd 100644 --- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts +++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts @@ -6,7 +6,7 @@ /dts-v1/; #include <dt-bindings/input/input.h> -#include "mt7623.dtsi" +#include "mt7623n.dtsi" #include "mt6323.dtsi" / { @@ -21,6 +21,19 @@ stdout-path = "serial2:115200n8"; }; + connector { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "d"; + ddc-i2c-bus = <&hdmiddc0>; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi0_out>; + }; + }; + }; + cpus { cpu@0 { proc-supply = <&mt6323_vproc_reg>; @@ -66,6 +79,13 @@ regulator-always-on; }; + reg_vgpu: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vdd_fixed_vgpu"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + }; + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; @@ -114,10 +134,18 @@ }; }; +&bls { + status = "okay"; +}; + &btif { status = "okay"; }; +&cec { + status = "okay"; +}; + &cir { pinctrl-names = "default"; pinctrl-0 = <&cir_pins_a>; @@ -128,6 +156,21 @@ status = "okay"; }; +&dpi0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + dpi0_out: endpoint { + remote-endpoint = <&hdmi0_in>; + }; + }; + }; +}; + ð { status = "okay"; @@ -192,6 +235,7 @@ fixed-link { speed = <1000>; full-duplex; + pause; }; }; }; @@ -199,6 +243,42 @@ }; }; +&hdmi0 { + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_pins_a>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + hdmi0_in: endpoint { + remote-endpoint = <&dpi0_out>; + }; + }; + + port@1 { + reg = <1>; + hdmi0_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; +}; + +&hdmiddc0 { + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_ddc_pins_a>; + status = "okay"; +}; + +&hdmi_phy { + mediatek,ibias = <0xa>; + mediatek,ibias_up = <0x1c>; + status = "okay"; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>; @@ -211,6 +291,11 @@ status = "okay"; }; +&mali { + mali-supply = <®_vgpu>; + status = "okay"; +}; + &mmc0 { pinctrl-names = "default", "state_uhs"; pinctrl-0 = <&mmc0_pins_default>; @@ -330,4 +415,3 @@ &u3phy2 { status = "okay"; }; - diff --git a/arch/arm/boot/dts/mt7623n-rfb-emmc.dts b/arch/arm/boot/dts/mt7623n-rfb-emmc.dts index 0447748f9fa0..1b9b9a8145a7 100644 --- a/arch/arm/boot/dts/mt7623n-rfb-emmc.dts +++ b/arch/arm/boot/dts/mt7623n-rfb-emmc.dts @@ -7,7 +7,7 @@ /dts-v1/; #include <dt-bindings/input/input.h> -#include "mt7623.dtsi" +#include "mt7623n.dtsi" #include "mt6323.dtsi" / { @@ -24,6 +24,19 @@ stdout-path = "serial2:115200n8"; }; + connector { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "d"; + ddc-i2c-bus = <&hdmiddc0>; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi0_out>; + }; + }; + }; + cpus { cpu@0 { proc-supply = <&mt6323_vproc_reg>; @@ -106,10 +119,18 @@ }; }; +&bls { + status = "okay"; +}; + &btif { status = "okay"; }; +&cec { + status = "okay"; +}; + &cir { pinctrl-names = "default"; pinctrl-0 = <&cir_pins_a>; @@ -120,6 +141,21 @@ status = "okay"; }; +&dpi0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + dpi0_out: endpoint { + remote-endpoint = <&hdmi0_in>; + }; + }; + }; +}; + ð { status = "okay"; @@ -203,6 +239,42 @@ }; }; +&hdmi0 { + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_pins_a>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + hdmi0_in: endpoint { + remote-endpoint = <&dpi0_out>; + }; + }; + + port@1 { + reg = <1>; + hdmi0_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; +}; + +&hdmiddc0 { + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_ddc_pins_a>; + status = "okay"; +}; + +&hdmi_phy { + mediatek,ibias = <0xa>; + mediatek,ibias_up = <0x1c>; + status = "okay"; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>; diff --git a/arch/arm/boot/dts/mt7623n.dtsi b/arch/arm/boot/dts/mt7623n.dtsi new file mode 100644 index 000000000000..1880ac9e32cf --- /dev/null +++ b/arch/arm/boot/dts/mt7623n.dtsi @@ -0,0 +1,306 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright © 2017-2020 MediaTek Inc. + * Author: Sean Wang <sean.wang@mediatek.com> + * Ryder Lee <ryder.lee@mediatek.com> + * + */ + +#include "mt7623.dtsi" +#include <dt-bindings/memory/mt2701-larb-port.h> + +/ { + aliases { + rdma0 = &rdma0; + rdma1 = &rdma1; + }; + + g3dsys: syscon@13000000 { + compatible = "mediatek,mt7623-g3dsys", + "mediatek,mt2701-g3dsys", + "syscon"; + reg = <0 0x13000000 0 0x200>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + mali: gpu@13040000 { + compatible = "mediatek,mt7623-mali", "arm,mali-450"; + reg = <0 0x13040000 0 0x30000>; + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 171 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 172 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 173 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 174 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 176 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 177 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 178 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 179 IRQ_TYPE_LEVEL_LOW>, + <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1", + "ppmmu1", "pp2", "ppmmu2", "pp3", "ppmmu3", + "pp"; + clocks = <&topckgen CLK_TOP_MMPLL>, + <&g3dsys CLK_G3DSYS_CORE>; + clock-names = "bus", "core"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_MFG>; + resets = <&g3dsys MT2701_G3DSYS_CORE_RST>; + }; + + mmsys: syscon@14000000 { + compatible = "mediatek,mt7623-mmsys", + "mediatek,mt2701-mmsys", + "syscon"; + reg = <0 0x14000000 0 0x1000>; + #clock-cells = <1>; + }; + + larb0: larb@14010000 { + compatible = "mediatek,mt7623-smi-larb", + "mediatek,mt2701-smi-larb"; + reg = <0 0x14010000 0 0x1000>; + mediatek,smi = <&smi_common>; + mediatek,larb-id = <0>; + clocks = <&mmsys CLK_MM_SMI_LARB0>, + <&mmsys CLK_MM_SMI_LARB0>; + clock-names = "apb", "smi"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>; + }; + + larb1: larb@16010000 { + compatible = "mediatek,mt7623-smi-larb", + "mediatek,mt2701-smi-larb"; + reg = <0 0x16010000 0 0x1000>; + mediatek,smi = <&smi_common>; + mediatek,larb-id = <1>; + clocks = <&vdecsys CLK_VDEC_CKGEN>, + <&vdecsys CLK_VDEC_LARB>; + clock-names = "apb", "smi"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>; + }; + + larb2: larb@15001000 { + compatible = "mediatek,mt7623-smi-larb", + "mediatek,mt2701-smi-larb"; + reg = <0 0x15001000 0 0x1000>; + mediatek,smi = <&smi_common>; + mediatek,larb-id = <2>; + clocks = <&imgsys CLK_IMG_SMI_COMM>, + <&imgsys CLK_IMG_SMI_COMM>; + clock-names = "apb", "smi"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>; + }; + + imgsys: syscon@15000000 { + compatible = "mediatek,mt7623-imgsys", + "mediatek,mt2701-imgsys", + "syscon"; + reg = <0 0x15000000 0 0x1000>; + #clock-cells = <1>; + }; + + iommu: mmsys_iommu@10205000 { + compatible = "mediatek,mt7623-m4u", + "mediatek,mt2701-m4u"; + reg = <0 0x10205000 0 0x1000>; + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>; + clocks = <&infracfg CLK_INFRA_M4U>; + clock-names = "bclk"; + mediatek,larbs = <&larb0 &larb1 &larb2>; + #iommu-cells = <1>; + }; + + jpegdec: jpegdec@15004000 { + compatible = "mediatek,mt7623-jpgdec", + "mediatek,mt2701-jpgdec"; + reg = <0 0x15004000 0 0x1000>; + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>; + clocks = <&imgsys CLK_IMG_JPGDEC_SMI>, + <&imgsys CLK_IMG_JPGDEC>; + clock-names = "jpgdec-smi", + "jpgdec"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>; + mediatek,larb = <&larb2>; + iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>, + <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>; + }; + + smi_common: smi@1000c000 { + compatible = "mediatek,mt7623-smi-common", + "mediatek,mt2701-smi-common"; + reg = <0 0x1000c000 0 0x1000>; + clocks = <&infracfg CLK_INFRA_SMI>, + <&mmsys CLK_MM_SMI_COMMON>, + <&infracfg CLK_INFRA_SMI>; + clock-names = "apb", "smi", "async"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>; + }; + + ovl: ovl@14007000 { + compatible = "mediatek,mt7623-disp-ovl", + "mediatek,mt2701-disp-ovl"; + reg = <0 0x14007000 0 0x1000>; + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_LOW>; + clocks = <&mmsys CLK_MM_DISP_OVL>; + iommus = <&iommu MT2701_M4U_PORT_DISP_OVL_0>; + mediatek,larb = <&larb0>; + }; + + rdma0: rdma@14008000 { + compatible = "mediatek,mt7623-disp-rdma", + "mediatek,mt2701-disp-rdma"; + reg = <0 0x14008000 0 0x1000>; + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>; + clocks = <&mmsys CLK_MM_DISP_RDMA>; + iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA>; + mediatek,larb = <&larb0>; + }; + + wdma@14009000 { + compatible = "mediatek,mt7623-disp-wdma", + "mediatek,mt2701-disp-wdma"; + reg = <0 0x14009000 0 0x1000>; + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_LOW>; + clocks = <&mmsys CLK_MM_DISP_WDMA>; + iommus = <&iommu MT2701_M4U_PORT_DISP_WDMA>; + mediatek,larb = <&larb0>; + }; + + bls: pwm@1400a000 { + compatible = "mediatek,mt7623-disp-pwm", + "mediatek,mt2701-disp-pwm"; + reg = <0 0x1400a000 0 0x1000>; + #pwm-cells = <2>; + clocks = <&mmsys CLK_MM_MDP_BLS_26M>, + <&mmsys CLK_MM_DISP_BLS>; + clock-names = "main", "mm"; + status = "disabled"; + }; + + color: color@1400b000 { + compatible = "mediatek,mt7623-disp-color", + "mediatek,mt2701-disp-color"; + reg = <0 0x1400b000 0 0x1000>; + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_LOW>; + clocks = <&mmsys CLK_MM_DISP_COLOR>; + }; + + dsi: dsi@1400c000 { + compatible = "mediatek,mt7623-dsi", + "mediatek,mt2701-dsi"; + reg = <0 0x1400c000 0 0x1000>; + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_LOW>; + clocks = <&mmsys CLK_MM_DSI_ENGINE>, + <&mmsys CLK_MM_DSI_DIG>, + <&mipi_tx0>; + clock-names = "engine", "digital", "hs"; + phys = <&mipi_tx0>; + phy-names = "dphy"; + status = "disabled"; + }; + + mutex: mutex@1400e000 { + compatible = "mediatek,mt7623-disp-mutex", + "mediatek,mt2701-disp-mutex"; + reg = <0 0x1400e000 0 0x1000>; + interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>; + clocks = <&mmsys CLK_MM_MUTEX_32K>; + }; + + rdma1: rdma@14012000 { + compatible = "mediatek,mt7623-disp-rdma", + "mediatek,mt2701-disp-rdma"; + reg = <0 0x14012000 0 0x1000>; + interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_LOW>; + clocks = <&mmsys CLK_MM_DISP_RDMA1>; + iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA1>; + mediatek,larb = <&larb0>; + }; + + dpi0: dpi@14014000 { + compatible = "mediatek,mt7623-dpi", + "mediatek,mt2701-dpi"; + reg = <0 0x14014000 0 0x1000>; + interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; + clocks = <&mmsys CLK_MM_DPI1_DIGL>, + <&mmsys CLK_MM_DPI1_ENGINE>, + <&apmixedsys CLK_APMIXED_TVDPLL>; + clock-names = "pixel", "engine", "pll"; + status = "disabled"; + }; + + hdmi0: hdmi@14015000 { + compatible = "mediatek,mt7623-hdmi", + "mediatek,mt2701-hdmi"; + reg = <0 0x14015000 0 0x400>; + clocks = <&mmsys CLK_MM_HDMI_PIXEL>, + <&mmsys CLK_MM_HDMI_PLL>, + <&mmsys CLK_MM_HDMI_AUDIO>, + <&mmsys CLK_MM_HDMI_SPDIF>; + clock-names = "pixel", "pll", "bclk", "spdif"; + phys = <&hdmi_phy>; + phy-names = "hdmi"; + mediatek,syscon-hdmi = <&mmsys 0x900>; + cec = <&cec>; + status = "disabled"; + }; + + mipi_tx0: mipi-dphy@10010000 { + compatible = "mediatek,mt7623-mipi-tx", + "mediatek,mt2701-mipi-tx"; + reg = <0 0x10010000 0 0x90>; + clocks = <&clk26m>; + clock-output-names = "mipi_tx0_pll"; + #clock-cells = <0>; + #phy-cells = <0>; + }; + + cec: cec@10012000 { + compatible = "mediatek,mt7623-cec", + "mediatek,mt8173-cec"; + reg = <0 0x10012000 0 0xbc>; + interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>; + clocks = <&infracfg CLK_INFRA_CEC>; + status = "disabled"; + }; + + hdmi_phy: phy@10209100 { + compatible = "mediatek,mt7623-hdmi-phy", + "mediatek,mt2701-hdmi-phy"; + reg = <0 0x10209100 0 0x24>; + clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>; + clock-names = "pll_ref"; + clock-output-names = "hdmitx_dig_cts"; + #clock-cells = <0>; + #phy-cells = <0>; + status = "disabled"; + }; + + hdmiddc0: i2c@11013000 { + compatible = "mediatek,mt7623-hdmi-ddc", + "mediatek,mt8173-hdmi-ddc"; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; + reg = <0 0x11013000 0 0x1C>; + clocks = <&pericfg CLK_PERI_I2C3>; + clock-names = "ddc-i2c"; + status = "disabled"; + }; +}; + +&pio { + hdmi_pins_a: hdmi-default { + pins-hdmi { + pinmux = <MT7623_PIN_123_HTPLG_FUNC_HTPLG>; + input-enable; + bias-pull-down; + }; + }; + + hdmi_ddc_pins_a: hdmi_ddc-default { + pins-hdmi-ddc { + pinmux = <MT7623_PIN_124_GPIO124_FUNC_HDMISCK>, + <MT7623_PIN_125_GPIO125_FUNC_HDMISD>; + }; + }; +}; diff --git a/arch/arm/boot/dts/nspire.dtsi b/arch/arm/boot/dts/nspire.dtsi index d9a0fd7524dc..90e033d9141f 100644 --- a/arch/arm/boot/dts/nspire.dtsi +++ b/arch/arm/boot/dts/nspire.dtsi @@ -145,15 +145,19 @@ timer0: timer@900C0000 { reg = <0x900C0000 0x1000>; - - clocks = <&timer_clk>; + clocks = <&timer_clk>, <&timer_clk>, + <&timer_clk>; + clock-names = "timer0clk", "timer1clk", + "apb_pclk"; }; timer1: timer@900D0000 { reg = <0x900D0000 0x1000>; interrupts = <19>; - - clocks = <&timer_clk>; + clocks = <&timer_clk>, <&timer_clk>, + <&timer_clk>; + clock-names = "timer0clk", "timer1clk", + "apb_pclk"; }; watchdog: watchdog@90060000 { diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts index 05077f3c75cd..252507cf300b 100644 --- a/arch/arm/boot/dts/omap3-beagle-xm.dts +++ b/arch/arm/boot/dts/omap3-beagle-xm.dts @@ -389,7 +389,7 @@ }; &dss { - status = "ok"; + status = "okay"; pinctrl-names = "default"; pinctrl-0 = < @@ -406,7 +406,7 @@ }; &venc { - status = "ok"; + status = "okay"; vdda-supply = <&vdac>; diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts index 79bc710c05fc..f9f34b8458e9 100644 --- a/arch/arm/boot/dts/omap3-beagle.dts +++ b/arch/arm/boot/dts/omap3-beagle.dts @@ -386,7 +386,7 @@ }; &dss { - status = "ok"; + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&dss_dpi_pins>; @@ -400,7 +400,7 @@ }; &venc { - status = "ok"; + status = "okay"; vdda-supply = <&vdac>; @@ -413,7 +413,7 @@ }; &gpmc { - status = "ok"; + status = "okay"; ranges = <0 0 0x30000000 0x1000000>; /* CS0 space, 16MB */ /* Chip select 0 */ diff --git a/arch/arm/boot/dts/omap3-cm-t3517.dts b/arch/arm/boot/dts/omap3-cm-t3517.dts index 632f52efdf98..3b8349094baa 100644 --- a/arch/arm/boot/dts/omap3-cm-t3517.dts +++ b/arch/arm/boot/dts/omap3-cm-t3517.dts @@ -147,7 +147,7 @@ }; &dss { - status = "ok"; + status = "okay"; pinctrl-names = "default"; pinctrl-0 = < diff --git a/arch/arm/boot/dts/omap3-cm-t3530.dts b/arch/arm/boot/dts/omap3-cm-t3530.dts index 32dbaeaed147..bc545ee23e71 100644 --- a/arch/arm/boot/dts/omap3-cm-t3530.dts +++ b/arch/arm/boot/dts/omap3-cm-t3530.dts @@ -49,7 +49,7 @@ }; &dss { - status = "ok"; + status = "okay"; pinctrl-names = "default"; pinctrl-0 = < diff --git a/arch/arm/boot/dts/omap3-cm-t3730.dts b/arch/arm/boot/dts/omap3-cm-t3730.dts index 683819bf0915..48e48b0c8190 100644 --- a/arch/arm/boot/dts/omap3-cm-t3730.dts +++ b/arch/arm/boot/dts/omap3-cm-t3730.dts @@ -87,7 +87,7 @@ }; &dss { - status = "ok"; + status = "okay"; pinctrl-names = "default"; pinctrl-0 = < diff --git a/arch/arm/boot/dts/omap3-cm-t3x.dtsi b/arch/arm/boot/dts/omap3-cm-t3x.dtsi index cdb632df152a..e61b8a2bfb7d 100644 --- a/arch/arm/boot/dts/omap3-cm-t3x.dtsi +++ b/arch/arm/boot/dts/omap3-cm-t3x.dtsi @@ -246,7 +246,7 @@ }; &venc { - status = "ok"; + status = "okay"; port { venc_out: endpoint { @@ -257,7 +257,7 @@ }; &mcbsp2 { - status = "ok"; + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcbsp2_pins>; diff --git a/arch/arm/boot/dts/omap3-cpu-thermal.dtsi b/arch/arm/boot/dts/omap3-cpu-thermal.dtsi index aee46fa8c055..1ed837859374 100644 --- a/arch/arm/boot/dts/omap3-cpu-thermal.dtsi +++ b/arch/arm/boot/dts/omap3-cpu-thermal.dtsi @@ -17,4 +17,25 @@ cpu_thermal: cpu_thermal { /* sensor ID */ thermal-sensors = <&bandgap 0>; + + cpu_trips: trips { + cpu_alert0: cpu_alert { + temperature = <80000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + cpu_crit: cpu_crit { + temperature = <90000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; + + cpu_cooling_maps: cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&cpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; diff --git a/arch/arm/boot/dts/omap3-devkit8000-common.dtsi b/arch/arm/boot/dts/omap3-devkit8000-common.dtsi index ac3d996cec5c..2c19d6e255bd 100644 --- a/arch/arm/boot/dts/omap3-devkit8000-common.dtsi +++ b/arch/arm/boot/dts/omap3-devkit8000-common.dtsi @@ -337,7 +337,7 @@ }; &dss { - status = "ok"; + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&dss_dpi_pins>; @@ -361,7 +361,7 @@ }; &venc { - status = "ok"; + status = "okay"; vdda-supply = <&vdac>; diff --git a/arch/arm/boot/dts/omap3-gta04.dtsi b/arch/arm/boot/dts/omap3-gta04.dtsi index ecc45862b4f3..c8745bc800f7 100644 --- a/arch/arm/boot/dts/omap3-gta04.dtsi +++ b/arch/arm/boot/dts/omap3-gta04.dtsi @@ -822,27 +822,27 @@ }; &mcbsp1 { /* FM Transceiver PCM */ - status = "ok"; + status = "okay"; #sound-dai-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&mcbsp1_pins>; }; &mcbsp2 { /* TPS65950 I2S */ - status = "ok"; + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcbsp2_pins>; }; &mcbsp3 { /* Bluetooth PCM */ - status = "ok"; + status = "okay"; #sound-dai-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&mcbsp3_pins>; }; &mcbsp4 { /* GSM voice PCM */ - status = "ok"; + status = "okay"; #sound-dai-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&mcbsp4_pins>; diff --git a/arch/arm/boot/dts/omap3-ha-lcd.dts b/arch/arm/boot/dts/omap3-ha-lcd.dts index b3f7f9966c3c..643283f0c3db 100644 --- a/arch/arm/boot/dts/omap3-ha-lcd.dts +++ b/arch/arm/boot/dts/omap3-ha-lcd.dts @@ -100,7 +100,7 @@ }; &dss { - status = "ok"; + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&dss_dpi_pins>; diff --git a/arch/arm/boot/dts/omap3-igep0020-common.dtsi b/arch/arm/boot/dts/omap3-igep0020-common.dtsi index 91caa50b74c4..af8aa5f0feb7 100644 --- a/arch/arm/boot/dts/omap3-igep0020-common.dtsi +++ b/arch/arm/boot/dts/omap3-igep0020-common.dtsi @@ -245,7 +245,7 @@ }; &dss { - status = "ok"; + status = "okay"; port { dpi_out: endpoint { diff --git a/arch/arm/boot/dts/omap3-n9.dts b/arch/arm/boot/dts/omap3-n9.dts index 2495a696cec6..d211bcc31174 100644 --- a/arch/arm/boot/dts/omap3-n9.dts +++ b/arch/arm/boot/dts/omap3-n9.dts @@ -23,7 +23,6 @@ vana-supply = <&vaux3>; clocks = <&isp 0>; clock-frequency = <9600000>; - nokia,nvm-size = <(16 * 64)>; flash-leds = <&as3645a_flash &as3645a_indicator>; port { smia_1_1: endpoint { diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts index bc24e3dc7cda..32335d4ce478 100644 --- a/arch/arm/boot/dts/omap3-n900.dts +++ b/arch/arm/boot/dts/omap3-n900.dts @@ -1083,7 +1083,7 @@ }; &dss { - status = "ok"; + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&dss_sdi_pins>; @@ -1106,7 +1106,7 @@ }; &venc { - status = "ok"; + status = "okay"; vdda-supply = <&vdac>; @@ -1119,7 +1119,7 @@ }; &mcbsp2 { - status = "ok"; + status = "okay"; }; &ssi_port1 { diff --git a/arch/arm/boot/dts/omap3-n950.dts b/arch/arm/boot/dts/omap3-n950.dts index 31d47a1fad84..b2f480022ff6 100644 --- a/arch/arm/boot/dts/omap3-n950.dts +++ b/arch/arm/boot/dts/omap3-n950.dts @@ -76,7 +76,6 @@ vana-supply = <&vaux3>; clocks = <&isp 0>; clock-frequency = <9600000>; - nokia,nvm-size = <(16 * 64)>; flash-leds = <&as3645a_flash &as3645a_indicator>; port { smia_1_1: endpoint { @@ -205,13 +204,13 @@ }; &dss { - status = "ok"; + status = "okay"; vdda_video-supply = <&vdac>; }; &dsi { - status = "ok"; + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&dsi_pins>; @@ -225,8 +224,9 @@ }; }; - lcd0: display { + lcd0: panel@0 { compatible = "nokia,himalaya", "panel-dsi-cm"; + reg = <0>; label = "lcd0"; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/omap3-overo-common-dvi.dtsi b/arch/arm/boot/dts/omap3-overo-common-dvi.dtsi index c9e62e414abb..339a51fa4119 100644 --- a/arch/arm/boot/dts/omap3-overo-common-dvi.dtsi +++ b/arch/arm/boot/dts/omap3-overo-common-dvi.dtsi @@ -48,7 +48,7 @@ }; &dss { - status = "ok"; + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&dss_dpi_pins>; diff --git a/arch/arm/boot/dts/omap3-overo-common-lcd35.dtsi b/arch/arm/boot/dts/omap3-overo-common-lcd35.dtsi index 185ce53de0ec..1d6e88f99eb3 100644 --- a/arch/arm/boot/dts/omap3-overo-common-lcd35.dtsi +++ b/arch/arm/boot/dts/omap3-overo-common-lcd35.dtsi @@ -76,7 +76,7 @@ }; &dss { - status = "ok"; + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&dss_dpi_pins>; diff --git a/arch/arm/boot/dts/omap3-overo-common-lcd43.dtsi b/arch/arm/boot/dts/omap3-overo-common-lcd43.dtsi index 7fe0f9148232..7e30f9d45790 100644 --- a/arch/arm/boot/dts/omap3-overo-common-lcd43.dtsi +++ b/arch/arm/boot/dts/omap3-overo-common-lcd43.dtsi @@ -75,7 +75,7 @@ }; &dss { - status = "ok"; + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&dss_dpi_pins>; diff --git a/arch/arm/boot/dts/omap3-pandora-common.dtsi b/arch/arm/boot/dts/omap3-pandora-common.dtsi index 150d5be42d27..37608af6c07f 100644 --- a/arch/arm/boot/dts/omap3-pandora-common.dtsi +++ b/arch/arm/boot/dts/omap3-pandora-common.dtsi @@ -702,7 +702,7 @@ }; &venc { - status = "ok"; + status = "okay"; vdda-supply = <&vdac>; @@ -718,7 +718,7 @@ pinctrl-names = "default"; pinctrl-0 = < &dss_dpi_pins >; - status = "ok"; + status = "okay"; vdds_dsi-supply = <&vpll2>; port { diff --git a/arch/arm/boot/dts/omap3-panel-sharp-ls037v7dw01.dtsi b/arch/arm/boot/dts/omap3-panel-sharp-ls037v7dw01.dtsi index b8b9fcc41ef1..2dbb687d4df2 100644 --- a/arch/arm/boot/dts/omap3-panel-sharp-ls037v7dw01.dtsi +++ b/arch/arm/boot/dts/omap3-panel-sharp-ls037v7dw01.dtsi @@ -46,7 +46,7 @@ }; &dss { - status = "ok"; + status = "okay"; port { dpi_out: endpoint { remote-endpoint = <&lcd_in>; diff --git a/arch/arm/boot/dts/omap3-thunder.dts b/arch/arm/boot/dts/omap3-thunder.dts index f7930f198ce5..d82cab8e213a 100644 --- a/arch/arm/boot/dts/omap3-thunder.dts +++ b/arch/arm/boot/dts/omap3-thunder.dts @@ -64,7 +64,7 @@ }; &dss { - status = "ok"; + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&dss_dpi_pins>; diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi index cf22a7e1c63c..9dcae1f2bc99 100644 --- a/arch/arm/boot/dts/omap3.dtsi +++ b/arch/arm/boot/dts/omap3.dtsi @@ -941,6 +941,9 @@ ti,hwmods = "dss_dsi1"; clocks = <&dss1_alwon_fck>, <&dss2_alwon_fck>; clock-names = "fck", "sys_clk"; + + #address-cells = <1>; + #size-cells = <0>; }; rfbi: encoder@48050800 { diff --git a/arch/arm/boot/dts/omap34xx.dtsi b/arch/arm/boot/dts/omap34xx.dtsi index 9c3ee4ac8165..feaa43b78535 100644 --- a/arch/arm/boot/dts/omap34xx.dtsi +++ b/arch/arm/boot/dts/omap34xx.dtsi @@ -20,6 +20,7 @@ operating-points-v2 = <&cpu0_opp_table>; clock-latency = <300000>; /* From legacy driver */ + #cooling-cells = <2>; }; }; @@ -182,7 +183,7 @@ }; &ssi { - status = "ok"; + status = "okay"; clocks = <&ssi_ssr_fck>, <&ssi_sst_fck>, diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi index 9c3beefc0fe0..05fe5ed127b0 100644 --- a/arch/arm/boot/dts/omap36xx.dtsi +++ b/arch/arm/boot/dts/omap36xx.dtsi @@ -25,6 +25,7 @@ vbb-supply = <&abb_mpu_iva>; clock-latency = <300000>; /* From omap-cpufreq driver */ + #cooling-cells = <2>; }; }; @@ -234,7 +235,7 @@ }; &ssi { - status = "ok"; + status = "okay"; clocks = <&ssi_ssr_fck>, <&ssi_sst_fck>, diff --git a/arch/arm/boot/dts/omap4-duovero-parlor.dts b/arch/arm/boot/dts/omap4-duovero-parlor.dts index 4548d87534e3..b294c22177cb 100644 --- a/arch/arm/boot/dts/omap4-duovero-parlor.dts +++ b/arch/arm/boot/dts/omap4-duovero-parlor.dts @@ -171,11 +171,11 @@ }; &dss { - status = "ok"; + status = "okay"; }; &hdmi { - status = "ok"; + status = "okay"; vdda-supply = <&vdac>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/omap4-l4-abe.dtsi b/arch/arm/boot/dts/omap4-l4-abe.dtsi index b2cf5f41e222..a9573d441dea 100644 --- a/arch/arm/boot/dts/omap4-l4-abe.dtsi +++ b/arch/arm/boot/dts/omap4-l4-abe.dtsi @@ -1,14 +1,16 @@ &l4_abe { /* 0x40100000 */ - compatible = "ti,omap4-l4-abe", "simple-bus"; + compatible = "ti,omap4-l4-abe", "simple-pm-bus"; reg = <0x40100000 0x400>, <0x40100400 0x400>; reg-names = "la", "ap"; + power-domains = <&prm_abe>; + /* OMAP4_L4_ABE_CLKCTRL is read-only */ #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x40100000 0x100000>, /* segment 0 */ <0x49000000 0x49000000 0x100000>; segment@0 { /* 0x40100000 */ - compatible = "simple-bus"; + compatible = "simple-pm-bus"; #address-cells = <1>; #size-cells = <1>; ranges = diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi index 3e78caefa2b8..609a8dea946b 100644 --- a/arch/arm/boot/dts/omap4-panda-common.dtsi +++ b/arch/arm/boot/dts/omap4-panda-common.dtsi @@ -566,7 +566,7 @@ }; &dss { - status = "ok"; + status = "okay"; port { dpi_out: endpoint { @@ -577,12 +577,12 @@ }; &dsi2 { - status = "ok"; + status = "okay"; vdd-supply = <&vcxio>; }; &hdmi { - status = "ok"; + status = "okay"; vdda-supply = <&vdac>; port { diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts index 79e7a41ecb7e..afb49a2d6963 100644 --- a/arch/arm/boot/dts/omap4-sdp.dts +++ b/arch/arm/boot/dts/omap4-sdp.dts @@ -648,11 +648,11 @@ }; &dss { - status = "ok"; + status = "okay"; }; &dsi1 { - status = "ok"; + status = "okay"; vdd-supply = <&vcxio>; port { @@ -662,8 +662,9 @@ }; }; - lcd0: display { + lcd0: panel@0 { compatible = "tpo,taal", "panel-dsi-cm"; + reg = <0>; label = "lcd0"; reset-gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* 102 */ @@ -677,7 +678,7 @@ }; &dsi2 { - status = "ok"; + status = "okay"; vdd-supply = <&vcxio>; port { @@ -687,8 +688,9 @@ }; }; - lcd1: display { + lcd1: panel@0 { compatible = "tpo,taal", "panel-dsi-cm"; + reg = <0>; label = "lcd1"; reset-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* 104 */ @@ -702,7 +704,7 @@ }; &hdmi { - status = "ok"; + status = "okay"; vdda-supply = <&vdac>; port { diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 0282b9de3384..d6475cc6a91a 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -410,7 +410,7 @@ status = "disabled"; }; - target-module@56000000 { + sgx_module: target-module@56000000 { compatible = "ti,sysc-omap4", "ti,sysc"; reg = <0x5600fe00 0x4>, <0x5600fe10 0x4>; @@ -572,6 +572,9 @@ clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>; clock-names = "fck", "sys_clk"; + + #address-cells = <1>; + #size-cells = <0>; }; }; @@ -604,6 +607,9 @@ clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>; clock-names = "fck", "sys_clk"; + + #address-cells = <1>; + #size-cells = <0>; }; }; @@ -658,6 +664,12 @@ #reset-cells = <1>; }; + prm_abe: prm@500 { + compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; + reg = <0x500 0x100>; + #power-domain-cells = <0>; + }; + prm_core: prm@700 { compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst"; reg = <0x700 0x100>; diff --git a/arch/arm/boot/dts/omap443x.dtsi b/arch/arm/boot/dts/omap443x.dtsi index 8ed510ab00c5..cb309743de5d 100644 --- a/arch/arm/boot/dts/omap443x.dtsi +++ b/arch/arm/boot/dts/omap443x.dtsi @@ -74,3 +74,13 @@ }; /include/ "omap443x-clocks.dtsi" + +/* + * Use dpll_per for sgx at 153.6MHz like droid4 stock v3.0.8 Android kernel + */ +&sgx_module { + assigned-clocks = <&l3_gfx_clkctrl OMAP4_GPU_CLKCTRL 24>, + <&dpll_per_m7x2_ck>; + assigned-clock-rates = <0>, <153600000>; + assigned-clock-parents = <&dpll_per_m7x2_ck>; +}; diff --git a/arch/arm/boot/dts/omap5-board-common.dtsi b/arch/arm/boot/dts/omap5-board-common.dtsi index edf1906016c8..d8f13626cfd1 100644 --- a/arch/arm/boot/dts/omap5-board-common.dtsi +++ b/arch/arm/boot/dts/omap5-board-common.dtsi @@ -743,11 +743,11 @@ }; &dss { - status = "ok"; + status = "okay"; }; &hdmi { - status = "ok"; + status = "okay"; /* vdda-supply populated in board specific dts file */ diff --git a/arch/arm/boot/dts/omap5-cm-t54.dts b/arch/arm/boot/dts/omap5-cm-t54.dts index e78d3718f145..ca759b7b8a58 100644 --- a/arch/arm/boot/dts/omap5-cm-t54.dts +++ b/arch/arm/boot/dts/omap5-cm-t54.dts @@ -653,7 +653,7 @@ }; &dss { - status = "ok"; + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&dss_dpi_pins>; @@ -677,12 +677,12 @@ }; &dsi2 { - status = "ok"; + status = "okay"; vdd-supply = <&ldo4_reg>; }; &hdmi { - status = "ok"; + status = "okay"; vdda-supply = <&ldo4_reg>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/omap5-l4-abe.dtsi b/arch/arm/boot/dts/omap5-l4-abe.dtsi index 25b7fce8de2d..a03bca5a3584 100644 --- a/arch/arm/boot/dts/omap5-l4-abe.dtsi +++ b/arch/arm/boot/dts/omap5-l4-abe.dtsi @@ -1,14 +1,16 @@ &l4_abe { /* 0x40100000 */ - compatible = "ti,omap5-l4-abe", "simple-bus"; + compatible = "ti,omap5-l4-abe", "simple-pm-bus"; reg = <0x40100000 0x400>, <0x40100400 0x400>; reg-names = "la", "ap"; + power-domains = <&prm_abe>; + /* OMAP5_L4_ABE_CLKCTRL is read-only */ #address-cells = <1>; #size-cells = <1>; ranges = <0x00000000 0x40100000 0x100000>, /* segment 0 */ <0x49000000 0x49000000 0x100000>; segment@0 { /* 0x40100000 */ - compatible = "simple-bus"; + compatible = "simple-pm-bus"; #address-cells = <1>; #size-cells = <1>; ranges = diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index a82c96258a93..2bf2e5839a7f 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -676,6 +676,12 @@ #reset-cells = <1>; }; + prm_abe: prm@500 { + compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; + reg = <0x500 0x100>; + #power-domain-cells = <0>; + }; + prm_core: prm@700 { compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; reg = <0x700 0x100>; diff --git a/arch/arm/boot/dts/owl-s500-labrador-base-m.dts b/arch/arm/boot/dts/owl-s500-labrador-base-m.dts new file mode 100644 index 000000000000..c92f8bdcb331 --- /dev/null +++ b/arch/arm/boot/dts/owl-s500-labrador-base-m.dts @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Caninos Labrador Base Board + * + * Copyright (c) 2019-2020 Matheus Castello + */ + +/dts-v1/; + +#include "owl-s500-labrador-v2.dtsi" + +/ { + model = "Caninos Labrador Core v2 on Labrador Base-M v1"; + compatible = "caninos,labrador-base-m", + "caninos,labrador-v2", "actions,s500"; + + aliases { + serial3 = &uart3; + }; + + chosen { + stdout-path = "serial3:115200n8"; + }; + + uart3_clk: uart3-clk { + compatible = "fixed-clock"; + clock-frequency = <921600>; + #clock-cells = <0>; + }; +}; + +&uart3 { + status = "okay"; + clocks = <&uart3_clk>; +}; diff --git a/arch/arm/boot/dts/owl-s500-labrador-v2.dtsi b/arch/arm/boot/dts/owl-s500-labrador-v2.dtsi new file mode 100644 index 000000000000..883ff2f9886d --- /dev/null +++ b/arch/arm/boot/dts/owl-s500-labrador-v2.dtsi @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Caninos Labrador SoM V2 + * + * Copyright (c) 2019-2020 Matheus Castello + */ + +#include "owl-s500.dtsi" + +/ { + model = "Caninos Labrador Core V2.1"; + compatible = "caninos,labrador-v2", "actions,s500"; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x80000000>; + }; +}; + +&timer { + clocks = <&hosc>; +}; diff --git a/arch/arm/boot/dts/owl-s500-roseapplepi.dts b/arch/arm/boot/dts/owl-s500-roseapplepi.dts new file mode 100644 index 000000000000..a2087e617cb2 --- /dev/null +++ b/arch/arm/boot/dts/owl-s500-roseapplepi.dts @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Roseapple Pi + * + * Copyright (C) 2020 Cristian Ciocaltea <cristian.ciocaltea@gmail.com> + */ + +/dts-v1/; + +#include "owl-s500.dtsi" + +/ { + compatible = "roseapplepi,roseapplepi", "actions,s500"; + model = "Roseapple Pi"; + + aliases { + serial2 = &uart2; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x80000000>; /* 2GB */ + }; + + uart2_clk: uart2-clk { + compatible = "fixed-clock"; + clock-frequency = <921600>; + #clock-cells = <0>; + }; +}; + +&twd_timer { + status = "okay"; +}; + +&timer { + clocks = <&hosc>; +}; + +&uart2 { + status = "okay"; + clocks = <&uart2_clk>; +}; diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi index 5ceb6cc4451d..1dbe4e8b38ac 100644 --- a/arch/arm/boot/dts/owl-s500.dtsi +++ b/arch/arm/boot/dts/owl-s500.dtsi @@ -84,21 +84,21 @@ global_timer: timer@b0020200 { compatible = "arm,cortex-a9-global-timer"; reg = <0xb0020200 0x100>; - interrupts = <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; + interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; status = "disabled"; }; twd_timer: timer@b0020600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0xb0020600 0x20>; - interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; status = "disabled"; }; twd_wdt: wdt@b0020620 { compatible = "arm,cortex-a9-twd-wdt"; reg = <0xb0020620 0xe0>; - interrupts = <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; + interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/picoxcell-pc3x2.dtsi b/arch/arm/boot/dts/picoxcell-pc3x2.dtsi index 5ae860788339..c4c6c7e9e37b 100644 --- a/arch/arm/boot/dts/picoxcell-pc3x2.dtsi +++ b/arch/arm/boot/dts/picoxcell-pc3x2.dtsi @@ -160,7 +160,6 @@ reg = <0x20000 0x1000>; #address-cells = <1>; #size-cells = <0>; - reg-io-width = <4>; banka: gpio-controller@0 { compatible = "snps,dw-apb-gpio-bank"; diff --git a/arch/arm/boot/dts/picoxcell-pc3x3.dtsi b/arch/arm/boot/dts/picoxcell-pc3x3.dtsi index fa93155fadb7..0e85bb6bd150 100644 --- a/arch/arm/boot/dts/picoxcell-pc3x3.dtsi +++ b/arch/arm/boot/dts/picoxcell-pc3x3.dtsi @@ -243,7 +243,6 @@ reg = <0x20000 0x1000>; #address-cells = <1>; #size-cells = <0>; - reg-io-width = <4>; banka: gpio-controller@0 { compatible = "snps,dw-apb-gpio-bank"; diff --git a/arch/arm/boot/dts/pm9g45.dts b/arch/arm/boot/dts/pm9g45.dts index 4dfe0f15d7bd..c349fd3758a6 100644 --- a/arch/arm/boot/dts/pm9g45.dts +++ b/arch/arm/boot/dts/pm9g45.dts @@ -15,7 +15,7 @@ bootargs = "console=ttyS0,115200"; }; - memory { + memory@70000000 { reg = <0x70000000 0x8000000>; }; @@ -68,6 +68,7 @@ &pinctrl_board_mmc &pinctrl_mmc0_slot0_clk_cmd_dat0 &pinctrl_mmc0_slot0_dat1_3>; + pinctrl-names = "default"; status = "okay"; slot@0 { reg = <0>; diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi index 9c7b46b90c3c..7d3d93c22ed9 100644 --- a/arch/arm/boot/dts/prima2.dtsi +++ b/arch/arm/boot/dts/prima2.dtsi @@ -50,7 +50,7 @@ #size-cells = <1>; ranges = <0x40000000 0x40000000 0x80000000>; - l2-cache-controller@80040000 { + cache-controller@80040000 { compatible = "arm,pl310-cache"; reg = <0x80040000 0x1000>; interrupts = <59>; diff --git a/arch/arm/boot/dts/qcom-mdm9615.dtsi b/arch/arm/boot/dts/qcom-mdm9615.dtsi index 347b4f7d7889..dda2ceec6591 100644 --- a/arch/arm/boot/dts/qcom-mdm9615.dtsi +++ b/arch/arm/boot/dts/qcom-mdm9615.dtsi @@ -98,7 +98,7 @@ ranges; compatible = "simple-bus"; - L2: l2-cache@2040000 { + L2: cache-controller@2040000 { compatible = "arm,pl310-cache"; reg = <0x02040000 0x1000>; arm,data-latency = <2 2 0>; diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi index b9b138888048..45cf75b5824c 100644 --- a/arch/arm/boot/dts/r7s72100.dtsi +++ b/arch/arm/boot/dts/r7s72100.dtsi @@ -499,7 +499,7 @@ clock-output-names = "sdhi00", "sdhi01", "sdhi10", "sdhi11"; }; - pinctrl: pin-controller@fcfe3000 { + pinctrl: pinctrl@fcfe3000 { compatible = "renesas,r7s72100-ports"; reg = <0xfcfe3000 0x4230>; diff --git a/arch/arm/boot/dts/r7s9210.dtsi b/arch/arm/boot/dts/r7s9210.dtsi index 838920aef992..85c0399b1339 100644 --- a/arch/arm/boot/dts/r7s9210.dtsi +++ b/arch/arm/boot/dts/r7s9210.dtsi @@ -489,7 +489,7 @@ interrupt-map-mask = <7 0>; }; - pinctrl: pin-controller@fcffe000 { + pinctrl: pinctrl@fcffe000 { compatible = "renesas,r7s9210-pinctrl"; reg = <0xfcffe000 0x1000>; diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi index b92e72579836..e5fb1ce261f7 100644 --- a/arch/arm/boot/dts/r8a73a4.dtsi +++ b/arch/arm/boot/dts/r8a73a4.dtsi @@ -221,7 +221,7 @@ power-domains = <&pd_c4>; }; - pfc: pin-controller@e6050000 { + pfc: pinctrl@e6050000 { compatible = "renesas,pfc-r8a73a4"; reg = <0 0xe6050000 0 0x9000>; gpio-controller; diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi index 8048303037ee..1b2cf5fa322b 100644 --- a/arch/arm/boot/dts/r8a7740.dtsi +++ b/arch/arm/boot/dts/r8a7740.dtsi @@ -311,7 +311,7 @@ status = "disabled"; }; - pfc: pin-controller@e6050000 { + pfc: pinctrl@e6050000 { compatible = "renesas,pfc-r8a7740"; reg = <0xe6050000 0x8000>, <0xe605800c 0x20>; diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts b/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts index 1479ced50873..961c0f2eeefb 100644 --- a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts +++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts @@ -27,6 +27,12 @@ status = "disabled"; }; +&can0 { + pinctrl-0 = <&can0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + ðer { pinctrl-0 = <ðer_pins>; pinctrl-names = "default"; @@ -49,6 +55,11 @@ }; &pfc { + can0_pins: can0 { + groups = "can0_data_d"; + function = "can0"; + }; + ether_pins: ether { groups = "eth_mdio", "eth_rmii"; function = "eth"; diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts index e90aaf1c94f0..c2c05c9685d1 100644 --- a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts +++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts @@ -52,6 +52,16 @@ clock-frequency = <26000000>; }; + leds { + compatible = "gpio-leds"; + + sdhi2_led { + label = "sdio-led"; + gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc1"; + }; + }; + reg_1p5v: 1p5v { compatible = "regulator-fixed"; regulator-name = "1P5V"; @@ -131,17 +141,109 @@ }; }; +&can1 { + pinctrl-0 = <&can1_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&cmt0 { + status = "okay"; +}; + +&gpio1 { + can-trx-en-gpio{ + gpio-hog; + gpios = <28 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "can-trx-en-gpio"; + }; +}; + +&hsusb { + pinctrl-0 = <&usb0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&msiof0 { + pinctrl-0 = <&msiof0_pins>; + pinctrl-names = "default"; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + + status = "okay"; + + flash1: flash@0 { + compatible = "sst,sst25vf016b", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + m25p,fast-read; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "user"; + reg = <0x00000000 0x00200000>; + }; + }; + }; +}; + +&pci0 { + pinctrl-0 = <&usb0_pins>; + pinctrl-names = "default"; + /* Disable hsusb to enable USB2.0 host mode support on J2 */ + /* status = "okay"; */ +}; + +&pci1 { + pinctrl-0 = <&usb1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pci2 { + /* Disable xhci to enable USB2.0 host mode support on J23 bottom port */ + /* status = "okay"; */ +}; + +&pcie_bus_clk { + clock-frequency = <100000000>; +}; + +&pciec { + /* SW2[6] determines which connector is activated + * ON = PCIe X4 (connector-J7) + * OFF = mini-PCIe (connector-J26) + */ + status = "okay"; +}; + &pfc { avb_pins: avb { groups = "avb_mdio", "avb_gmii"; function = "avb"; }; + can1_pins: can1 { + groups = "can1_data_b"; + function = "can1"; + }; + i2c2_pins: i2c2 { groups = "i2c2_b"; function = "i2c2"; }; + msiof0_pins: msiof0 { + groups = "msiof0_clk", "msiof0_sync", "msiof0_tx", "msiof0_rx"; + function = "msiof0"; + }; + scifa2_pins: scifa2 { groups = "scifa2_data_c"; function = "scifa2"; @@ -168,6 +270,16 @@ groups = "ssi34_ctrl", "ssi3_data", "ssi4_data"; function = "ssi"; }; + + usb0_pins: usb0 { + groups = "usb0"; + function = "usb0"; + }; + + usb1_pins: usb1 { + groups = "usb1_pwen"; + function = "usb1"; + }; }; &rcar_sound { @@ -222,3 +334,11 @@ &ssi4 { shared-pin; }; + +&usbphy { + status = "okay"; +}; + +&xhci { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/r8a7742-iwg21m.dtsi b/arch/arm/boot/dts/r8a7742-iwg21m.dtsi index 85aff429d408..5621c9ed698f 100644 --- a/arch/arm/boot/dts/r8a7742-iwg21m.dtsi +++ b/arch/arm/boot/dts/r8a7742-iwg21m.dtsi @@ -35,10 +35,28 @@ clock-frequency = <20000000>; }; -&pfc { - mmc1_pins: mmc1 { - groups = "mmc1_data4", "mmc1_ctrl"; - function = "mmc1"; +&gpio0 { + /* GP0_18 set low to select QSPI. Doing so will disable VIN2 */ + qspi_en { + gpio-hog; + gpios = <18 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "QSPI_EN"; + }; +}; + +&i2c0 { + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + rtc@68 { + compatible = "ti,bq32000"; + reg = <0x68>; + interrupt-parent = <&gpio1>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; }; }; @@ -51,3 +69,56 @@ non-removable; status = "okay"; }; + +&pfc { + i2c0_pins: i2c0 { + groups = "i2c0"; + function = "i2c0"; + }; + + mmc1_pins: mmc1 { + groups = "mmc1_data4", "mmc1_ctrl"; + function = "mmc1"; + }; + + qspi_pins: qspi { + groups = "qspi_ctrl", "qspi_data2"; + function = "qspi"; + }; +}; + +&qspi { + pinctrl-0 = <&qspi_pins>; + pinctrl-names = "default"; + + status = "okay"; + + flash: flash@0 { + compatible = "sst,sst25vf016b", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + m25p,fast-read; + spi-cpol; + spi-cpha; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "bootloader"; + reg = <0x00000000 0x000c0000>; + read-only; + }; + partition@c0000 { + label = "env"; + reg = <0x000c0000 0x00002000>; + }; + partition@c2000 { + label = "user"; + reg = <0x000c2000 0x0013e000>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi index 0240d017c90d..6a78c813057b 100644 --- a/arch/arm/boot/dts/r8a7742.dtsi +++ b/arch/arm/boot/dts/r8a7742.dtsi @@ -36,6 +36,14 @@ clock-frequency = <0>; }; + /* External CAN clock */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -188,6 +196,13 @@ clock-frequency = <0>; }; + /* External PCIe clock - can be overridden by the board */ + pcie_bus_clk: pcie_bus { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + pmu-0 { compatible = "arm,cortex-a15-pmu"; interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, @@ -323,11 +338,22 @@ resets = <&cpg 907>; }; - pfc: pin-controller@e6060000 { + pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a7742"; reg = <0 0xe6060000 0 0x250>; }; + tpu: pwm@e60f0000 { + compatible = "renesas,tpu-r8a7742", "renesas,tpu"; + reg = <0 0xe60f0000 0 0x148>; + interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 304>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 304>; + #pwm-cells = <3>; + status = "disabled"; + }; + cpg: clock-controller@e6150000 { compatible = "renesas,r8a7742-cpg-mssr"; reg = <0 0xe6150000 0 0x1000>; @@ -731,6 +757,22 @@ status = "disabled"; }; + qspi: spi@e6b10000 { + compatible = "renesas,qspi-r8a7742", "renesas,qspi"; + reg = <0 0xe6b10000 0 0x2c>; + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 917>; + dmas = <&dmac0 0x17>, <&dmac0 0x18>, + <&dmac1 0x17>, <&dmac1 0x18>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 917>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + scifa0: serial@e6c40000 { compatible = "renesas,scifa-r8a7742", "renesas,rcar-gen2-scifa", "renesas,scifa"; @@ -965,6 +1007,146 @@ status = "disabled"; }; + can0: can@e6e80000 { + compatible = "renesas,can-r8a7742", + "renesas,rcar-gen2-can"; + reg = <0 0xe6e80000 0 0x1000>; + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 916>, + <&cpg CPG_CORE R8A7742_CLK_RCAN>, <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 916>; + status = "disabled"; + }; + + can1: can@e6e88000 { + compatible = "renesas,can-r8a7742", + "renesas,rcar-gen2-can"; + reg = <0 0xe6e88000 0 0x1000>; + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 915>, + <&cpg CPG_CORE R8A7742_CLK_RCAN>, <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 915>; + status = "disabled"; + }; + + pwm0: pwm@e6e30000 { + compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar"; + reg = <0 0xe6e30000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm1: pwm@e6e31000 { + compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar"; + reg = <0 0xe6e31000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm2: pwm@e6e32000 { + compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar"; + reg = <0 0xe6e32000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm3: pwm@e6e33000 { + compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar"; + reg = <0 0xe6e33000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm4: pwm@e6e34000 { + compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar"; + reg = <0 0xe6e34000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm5: pwm@e6e35000 { + compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar"; + reg = <0 0xe6e35000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm6: pwm@e6e36000 { + compatible = "renesas,pwm-r8a7742", "renesas,pwm-rcar"; + reg = <0 0xe6e36000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + vin0: video@e6ef0000 { + compatible = "renesas,vin-r8a7742", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef0000 0 0x1000>; + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 811>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 811>; + status = "disabled"; + }; + + vin1: video@e6ef1000 { + compatible = "renesas,vin-r8a7742", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef1000 0 0x1000>; + interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 810>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 810>; + status = "disabled"; + }; + + vin2: video@e6ef2000 { + compatible = "renesas,vin-r8a7742", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef2000 0 0x1000>; + interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 809>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 809>; + status = "disabled"; + }; + + vin3: video@e6ef3000 { + compatible = "renesas,vin-r8a7742", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef3000 0 0x1000>; + interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 808>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 808>; + status = "disabled"; + }; + rcar_sound: sound@ec500000 { /* * #sound-dai-cells is required @@ -1476,6 +1658,159 @@ resets = <&cpg 408>; }; + pciec: pcie@fe000000 { + compatible = "renesas,pcie-r8a7742", + "renesas,pcie-rcar-gen2"; + reg = <0 0xfe000000 0 0x80000>; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, + <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, + <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, + <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; + /* Map all possible DDR as inbound ranges */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>, + <0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 319>; + status = "disabled"; + }; + + vsp@fe920000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe920000 0 0x8000>; + interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 130>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 130>; + }; + + vsp@fe928000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe928000 0 0x8000>; + interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 131>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 131>; + }; + + vsp@fe930000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe930000 0 0x8000>; + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 128>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 128>; + }; + + vsp@fe938000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe938000 0 0x8000>; + interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 127>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 127>; + }; + + du: display@feb00000 { + compatible = "renesas,du-r8a7742"; + reg = <0 0xfeb00000 0 0x70000>; + interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, + <&cpg CPG_MOD 722>; + clock-names = "du.0", "du.1", "du.2"; + resets = <&cpg 724>; + reset-names = "du.0"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_rgb: endpoint { + }; + }; + port@1 { + reg = <1>; + du_out_lvds0: endpoint { + remote-endpoint = <&lvds0_in>; + }; + }; + port@2 { + reg = <2>; + du_out_lvds1: endpoint { + remote-endpoint = <&lvds1_in>; + }; + }; + }; + }; + + lvds0: lvds@feb90000 { + compatible = "renesas,r8a7742-lvds"; + reg = <0 0xfeb90000 0 0x14>; + clocks = <&cpg CPG_MOD 726>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 726>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lvds0_in: endpoint { + remote-endpoint = <&du_out_lvds0>; + }; + }; + port@1 { + reg = <1>; + lvds0_out: endpoint { + }; + }; + }; + }; + + lvds1: lvds@feb94000 { + compatible = "renesas,r8a7742-lvds"; + reg = <0 0xfeb94000 0 0x14>; + clocks = <&cpg CPG_MOD 725>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 725>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lvds1_in: endpoint { + remote-endpoint = <&du_out_lvds1>; + }; + }; + port@1 { + reg = <1>; + lvds1_out: endpoint { + }; + }; + }; + }; + prr: chipid@ff000044 { compatible = "renesas,prr"; reg = <0 0xff000044 0 4>; diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi index 896916a00b84..f444e418f408 100644 --- a/arch/arm/boot/dts/r8a7743.dtsi +++ b/arch/arm/boot/dts/r8a7743.dtsi @@ -265,7 +265,7 @@ resets = <&cpg 904>; }; - pfc: pin-controller@e6060000 { + pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a7743"; reg = <0 0xe6060000 0 0x250>; }; diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi index 6b56aa286337..0442aad4f9db 100644 --- a/arch/arm/boot/dts/r8a7744.dtsi +++ b/arch/arm/boot/dts/r8a7744.dtsi @@ -265,7 +265,7 @@ resets = <&cpg 904>; }; - pfc: pin-controller@e6060000 { + pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a7744"; reg = <0 0xe6060000 0 0x250>; }; diff --git a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts index b15b1b088a32..1c7b37a01f0a 100644 --- a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts +++ b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts @@ -53,42 +53,6 @@ clock-frequency = <26000000>; }; - rsnd_sgtl5000: sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&sndcodec>; - simple-audio-card,frame-master = <&sndcodec>; - - sndcpu: simple-audio-card,cpu { - sound-dai = <&rcar_sound>; - }; - - sndcodec: simple-audio-card,codec { - sound-dai = <&sgtl5000>; - }; - }; - - vccq_sdhi0: regulator-vccq-sdhi0 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI0 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; - gpios-states = <1>; - states = <3300000 1>, <1800000 0>; - }; - - vccq_panel: regulator-vccq-panel { - compatible = "regulator-fixed"; - regulator-name = "Panel VccQ"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 13 GPIO_ACTIVE_LOW>; - enable-active-high; - }; - backlight_lcd: backlight { compatible = "pwm-backlight"; pwms = <&tpu 3 5000000 PWM_POLARITY_INVERTED>; @@ -107,19 +71,40 @@ }; }; }; -}; -&du { - pinctrl-0 = <&du0_pins>; - pinctrl-names = "default"; + vccq_panel: regulator-vccq-panel { + compatible = "regulator-fixed"; + regulator-name = "Panel VccQ"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 13 GPIO_ACTIVE_LOW>; + enable-active-high; + }; - status = "okay"; + vccq_sdhi0: regulator-vccq-sdhi0 { + compatible = "regulator-gpio"; - ports { - port@0 { - endpoint { - remote-endpoint = <&lcd_in>; - }; + regulator-name = "SDHI0 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; + gpios-states = <1>; + states = <3300000 1>, <1800000 0>; + }; + + rsnd_sgtl5000: sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&sndcodec>; + simple-audio-card,frame-master = <&sndcodec>; + + sndcpu: simple-audio-card,cpu { + sound-dai = <&rcar_sound>; + }; + + sndcodec: simple-audio-card,codec { + sound-dai = <&sgtl5000>; }; }; }; @@ -150,6 +135,21 @@ status = "okay"; }; +&du { + pinctrl-0 = <&du0_pins>; + pinctrl-names = "default"; + + status = "okay"; + + ports { + port@0 { + endpoint { + remote-endpoint = <&lcd_in>; + }; + }; + }; +}; + &hscif1 { pinctrl-0 = <&hscif1_pins>; pinctrl-names = "default"; @@ -171,6 +171,15 @@ status = "okay"; clock-frequency = <400000>; + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + #sound-dai-cells = <0>; + reg = <0x0a>; + clocks = <&audio_clock>; + VDDA-supply = <®_3p3v>; + VDDIO-supply = <®_3p3v>; + }; + stmpe811@44 { compatible = "st,stmpe811"; reg = <0x44>; @@ -179,7 +188,7 @@ /* 3.25 MHz ADC clock speed */ st,adc-freq = <1>; - /* ADC converstion time: 80 clocks */ + /* ADC conversion time: 80 clocks */ st,sample-time = <4>; /* 12-bit ADC */ st,mod-12b = <1>; @@ -203,15 +212,6 @@ st,touch-det-delay = <5>; }; }; - - sgtl5000: codec@a { - compatible = "fsl,sgtl5000"; - #sound-dai-cells = <0>; - reg = <0x0a>; - clocks = <&audio_clock>; - VDDA-supply = <®_3p3v>; - VDDIO-supply = <®_3p3v>; - }; }; &pci1 { diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi index 636248f370e0..0f14ac22921d 100644 --- a/arch/arm/boot/dts/r8a7745.dtsi +++ b/arch/arm/boot/dts/r8a7745.dtsi @@ -230,7 +230,7 @@ resets = <&cpg 905>; }; - pfc: pin-controller@e6060000 { + pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a7745"; reg = <0 0xe6060000 0 0x11c>; }; diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi index 6baa126b6590..691b1a131c87 100644 --- a/arch/arm/boot/dts/r8a77470.dtsi +++ b/arch/arm/boot/dts/r8a77470.dtsi @@ -187,7 +187,7 @@ resets = <&cpg 907>; }; - pfc: pin-controller@e6060000 { + pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a77470"; reg = <0 0xe6060000 0 0x118>; }; diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi index 1612b003fb55..c9f8735860bf 100644 --- a/arch/arm/boot/dts/r8a7778.dtsi +++ b/arch/arm/boot/dts/r8a7778.dtsi @@ -142,7 +142,7 @@ interrupt-controller; }; - pfc: pin-controller@fffc0000 { + pfc: pinctrl@fffc0000 { compatible = "renesas,pfc-r8a7778"; reg = <0xfffc0000 0x118>; }; diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi index c5634daef96f..74d7e9084eab 100644 --- a/arch/arm/boot/dts/r8a7779.dtsi +++ b/arch/arm/boot/dts/r8a7779.dtsi @@ -321,7 +321,7 @@ status = "disabled"; }; - pfc: pin-controller@fffc0000 { + pfc: pinctrl@fffc0000 { compatible = "renesas,pfc-r8a7779"; reg = <0xfffc0000 0x23c>; }; diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 769ba2a33d39..b0569b4ea5c8 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -363,7 +363,7 @@ resets = <&cpg 907>; }; - pfc: pin-controller@e6060000 { + pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a7790"; reg = <0 0xe6060000 0 0x250>; }; diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 499cf388735f..87f0d6dc3e5a 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -286,7 +286,7 @@ resets = <&cpg 904>; }; - pfc: pin-controller@e6060000 { + pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a7791"; reg = <0 0xe6060000 0 0x250>; }; diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index 597848ad4dfa..f5b299bfcb23 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -296,7 +296,7 @@ resets = <&cpg 913>; }; - pfc: pin-controller@e6060000 { + pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a7792"; reg = <0 0xe6060000 0 0x144>; }; diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi index 6d507091b163..f930f69f7bcc 100644 --- a/arch/arm/boot/dts/r8a7793.dtsi +++ b/arch/arm/boot/dts/r8a7793.dtsi @@ -271,7 +271,7 @@ resets = <&cpg 904>; }; - pfc: pin-controller@e6060000 { + pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a7793"; reg = <0 0xe6060000 0 0x250>; }; diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index 5f340397ab64..cd5e2904068a 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -238,7 +238,7 @@ resets = <&cpg 905>; }; - pfc: pin-controller@e6060000 { + pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a7794"; reg = <0 0xe6060000 0 0x11c>; }; diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi index ee59cc84f212..c47896e4ab58 100644 --- a/arch/arm/boot/dts/r9a06g032.dtsi +++ b/arch/arm/boot/dts/r9a06g032.dtsi @@ -165,7 +165,7 @@ status = "disabled"; }; - pinctrl: pin-controller@40067000 { + pinctrl: pinctrl@40067000 { compatible = "renesas,r9a06g032-pinctrl", "renesas,rzn1-pinctrl"; reg = <0x40067000 0x1000>, <0x51000000 0x480>; clocks = <&sysctrl R9A06G032_HCLK_PINCONFIG>; diff --git a/arch/arm/boot/dts/rk3066a-bqcurie2.dts b/arch/arm/boot/dts/rk3066a-bqcurie2.dts index 0a56a2f1bc4d..eba7a1344976 100644 --- a/arch/arm/boot/dts/rk3066a-bqcurie2.dts +++ b/arch/arm/boot/dts/rk3066a-bqcurie2.dts @@ -63,7 +63,11 @@ }; &cpu0 { - cpu0-supply = <&vdd_arm>; + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; }; &i2c1 { diff --git a/arch/arm/boot/dts/rk3066a-marsboard.dts b/arch/arm/boot/dts/rk3066a-marsboard.dts index 7e01f6406a86..6b121658d93c 100644 --- a/arch/arm/boot/dts/rk3066a-marsboard.dts +++ b/arch/arm/boot/dts/rk3066a-marsboard.dts @@ -47,7 +47,11 @@ }; &cpu0 { - cpu0-supply = <&vdd_arm>; + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; }; &i2c1 { diff --git a/arch/arm/boot/dts/rk3066a-rayeager.dts b/arch/arm/boot/dts/rk3066a-rayeager.dts index f9db6bb9fa11..309518403d86 100644 --- a/arch/arm/boot/dts/rk3066a-rayeager.dts +++ b/arch/arm/boot/dts/rk3066a-rayeager.dts @@ -128,7 +128,11 @@ }; &cpu0 { - cpu0-supply = <&vdd_arm>; + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; }; &emac { diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index b599394d149d..252750c97f97 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -36,7 +36,7 @@ clock-latency = <40000>; clocks = <&cru ARMCLK>; }; - cpu@1 { + cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; next-level-cache = <&L2>; diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi b/arch/arm/boot/dts/rk3288-evb.dtsi index 018802df4c0e..c4ca73b40d4a 100644 --- a/arch/arm/boot/dts/rk3288-evb.dtsi +++ b/arch/arm/boot/dts/rk3288-evb.dtsi @@ -247,7 +247,7 @@ pinctrl-0 = <&rgmii_pins>; tx_delay = <0x30>; rx_delay = <0x10>; - status = "ok"; + status = "okay"; }; &gpu { diff --git a/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi b/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi index 61435d8ee37b..36efa36b7190 100644 --- a/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi +++ b/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi @@ -61,7 +61,7 @@ snps,reset-gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_LOW>; tx_delay = <0x30>; rx_delay = <0x10>; - status = "ok"; + status = "okay"; }; &i2c0 { diff --git a/arch/arm/boot/dts/rk3288-firefly.dtsi b/arch/arm/boot/dts/rk3288-firefly.dtsi index e5c4fd4ea67e..7fb582302b32 100644 --- a/arch/arm/boot/dts/rk3288-firefly.dtsi +++ b/arch/arm/boot/dts/rk3288-firefly.dtsi @@ -191,7 +191,7 @@ snps,reset-gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_LOW>; tx_delay = <0x30>; rx_delay = <0x10>; - status = "ok"; + status = "okay"; }; &gpu { diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts index 213c9eb84f76..cf54d5ffff2f 100644 --- a/arch/arm/boot/dts/rk3288-miqi.dts +++ b/arch/arm/boot/dts/rk3288-miqi.dts @@ -81,7 +81,19 @@ }; &cpu0 { - cpu0-supply = <&vdd_cpu>; + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; }; &emmc { @@ -108,7 +120,7 @@ snps,reset-gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_LOW>; tx_delay = <0x30>; rx_delay = <0x10>; - status = "ok"; + status = "okay"; }; &hdmi { diff --git a/arch/arm/boot/dts/rk3288-popmetal.dts b/arch/arm/boot/dts/rk3288-popmetal.dts index 6a51940398b5..8c7376d64bc4 100644 --- a/arch/arm/boot/dts/rk3288-popmetal.dts +++ b/arch/arm/boot/dts/rk3288-popmetal.dts @@ -103,7 +103,19 @@ }; &cpu0 { - cpu0-supply = <&vdd_cpu>; + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; }; &emmc { @@ -149,7 +161,7 @@ pinctrl-0 = <&rgmii_pins>; tx_delay = <0x30>; rx_delay = <0x10>; - status = "ok"; + status = "okay"; }; &hdmi { diff --git a/arch/arm/boot/dts/rk3288-r89.dts b/arch/arm/boot/dts/rk3288-r89.dts index a258c7ae5329..55467bc30fa6 100644 --- a/arch/arm/boot/dts/rk3288-r89.dts +++ b/arch/arm/boot/dts/rk3288-r89.dts @@ -91,7 +91,19 @@ }; &cpu0 { - cpu0-supply = <&vdd_cpu>; + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; }; &gmac { @@ -107,7 +119,7 @@ pinctrl-0 = <&rgmii_pins>; tx_delay = <0x30>; rx_delay = <0x10>; - status = "ok"; + status = "okay"; }; &hdmi { diff --git a/arch/arm/boot/dts/rk3288-rock2-square.dts b/arch/arm/boot/dts/rk3288-rock2-square.dts index 3cca4d0f9b09..c4d1d142d8c6 100644 --- a/arch/arm/boot/dts/rk3288-rock2-square.dts +++ b/arch/arm/boot/dts/rk3288-rock2-square.dts @@ -156,7 +156,7 @@ }; &gmac { - status = "ok"; + status = "okay"; }; &hdmi { diff --git a/arch/arm/boot/dts/rk3288-tinker.dtsi b/arch/arm/boot/dts/rk3288-tinker.dtsi index 90e9be443fe6..9c1e38c54eae 100644 --- a/arch/arm/boot/dts/rk3288-tinker.dtsi +++ b/arch/arm/boot/dts/rk3288-tinker.dtsi @@ -137,7 +137,7 @@ snps,reset-delays-us = <0 10000 1000000>; tx_delay = <0x30>; rx_delay = <0x10>; - status = "ok"; + status = "okay"; }; &gpu { diff --git a/arch/arm/boot/dts/rk3288-vyasa.dts b/arch/arm/boot/dts/rk3288-vyasa.dts index 1a20854a1317..aa50f8ed4ca0 100644 --- a/arch/arm/boot/dts/rk3288-vyasa.dts +++ b/arch/arm/boot/dts/rk3288-vyasa.dts @@ -125,7 +125,19 @@ }; &cpu0 { - cpu0-supply = <&vdd_cpu>; + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; }; &emmc { diff --git a/arch/arm/boot/dts/s3c2416-smdk2416.dts b/arch/arm/boot/dts/s3c2416-smdk2416.dts index 811bfdef4e9b..47626ede6fdd 100644 --- a/arch/arm/boot/dts/s3c2416-smdk2416.dts +++ b/arch/arm/boot/dts/s3c2416-smdk2416.dts @@ -17,18 +17,11 @@ reg = <0x30000000 0x4000000>; }; - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - xti: xti@0 { - compatible = "fixed-clock"; - reg = <0>; - clock-frequency = <12000000>; - clock-output-names = "xti"; - #clock-cells = <0>; - }; + xti: clock-0 { + compatible = "fixed-clock"; + clock-frequency = <12000000>; + clock-output-names = "xti"; + #clock-cells = <0>; }; }; diff --git a/arch/arm/boot/dts/s3c2416.dtsi b/arch/arm/boot/dts/s3c2416.dtsi index 6adf64ea3ff2..4f084f4fe44f 100644 --- a/arch/arm/boot/dts/s3c2416.dtsi +++ b/arch/arm/boot/dts/s3c2416.dtsi @@ -18,54 +18,22 @@ }; cpus { - cpu { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; compatible = "arm,arm926ej-s"; + reg = <0x0>; }; }; - interrupt-controller@4a000000 { - compatible = "samsung,s3c2416-irq"; - }; - clocks: clock-controller@4c000000 { compatible = "samsung,s3c2416-clock"; reg = <0x4c000000 0x40>; #clock-cells = <1>; }; - pinctrl@56000000 { - compatible = "samsung,s3c2416-pinctrl"; - }; - - timer@51000000 { - clocks = <&clocks PCLK_PWM>; - clock-names = "timers"; - }; - - uart_0: serial@50000000 { - compatible = "samsung,s3c2440-uart"; - clock-names = "uart", "clk_uart_baud2", - "clk_uart_baud3"; - clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>, - <&clocks SCLK_UART>; - }; - - uart_1: serial@50004000 { - compatible = "samsung,s3c2440-uart"; - clock-names = "uart", "clk_uart_baud2", - "clk_uart_baud3"; - clocks = <&clocks PCLK_UART1>, <&clocks PCLK_UART1>, - <&clocks SCLK_UART>; - }; - - uart_2: serial@50008000 { - compatible = "samsung,s3c2440-uart"; - clock-names = "uart", "clk_uart_baud2", - "clk_uart_baud3"; - clocks = <&clocks PCLK_UART2>, <&clocks PCLK_UART2>, - <&clocks SCLK_UART>; - }; - uart_3: serial@5000c000 { compatible = "samsung,s3c2440-uart"; reg = <0x5000C000 0x4000>; @@ -98,22 +66,59 @@ <&clocks MUX_HSMMC1>; status = "disabled"; }; +}; - watchdog: watchdog@53000000 { - interrupts = <1 9 27 3>; - clocks = <&clocks PCLK_WDT>; - clock-names = "watchdog"; - }; +&i2c { + compatible = "samsung,s3c2440-i2c"; + clocks = <&clocks PCLK_I2C0>; + clock-names = "i2c"; +}; - rtc: rtc@57000000 { - compatible = "samsung,s3c2416-rtc"; - clocks = <&clocks PCLK_RTC>; - clock-names = "rtc"; - }; +&intc { + compatible = "samsung,s3c2416-irq"; +}; - i2c@54000000 { - compatible = "samsung,s3c2440-i2c"; - clocks = <&clocks PCLK_I2C0>; - clock-names = "i2c"; - }; +&pinctrl_0 { + compatible = "samsung,s3c2416-pinctrl"; +}; + +&rtc { + compatible = "samsung,s3c2416-rtc"; + clocks = <&clocks PCLK_RTC>; + clock-names = "rtc"; +}; + +&timer { + clocks = <&clocks PCLK_PWM>; + clock-names = "timers"; +}; + +&uart_0 { + compatible = "samsung,s3c2440-uart"; + clock-names = "uart", "clk_uart_baud2", + "clk_uart_baud3"; + clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>, + <&clocks SCLK_UART>; +}; + +&uart_1 { + compatible = "samsung,s3c2440-uart"; + clock-names = "uart", "clk_uart_baud2", + "clk_uart_baud3"; + clocks = <&clocks PCLK_UART1>, <&clocks PCLK_UART1>, + <&clocks SCLK_UART>; +}; + +&uart_2 { + compatible = "samsung,s3c2440-uart"; + clock-names = "uart", "clk_uart_baud2", + "clk_uart_baud3"; + clocks = <&clocks PCLK_UART2>, <&clocks PCLK_UART2>, + <&clocks SCLK_UART>; +}; + +&watchdog { + interrupts = <1 9 27 3>; + clocks = <&clocks PCLK_WDT>; + clock-names = "watchdog"; }; diff --git a/arch/arm/boot/dts/s3c24xx.dtsi b/arch/arm/boot/dts/s3c24xx.dtsi index 6d8dd3cdd3c0..06f82c7e458e 100644 --- a/arch/arm/boot/dts/s3c24xx.dtsi +++ b/arch/arm/boot/dts/s3c24xx.dtsi @@ -13,12 +13,12 @@ aliases { pinctrl0 = &pinctrl_0; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; + serial0 = &uart_0; + serial1 = &uart_1; + serial2 = &uart_2; }; - intc:interrupt-controller@4a000000 { + intc: interrupt-controller@4a000000 { compatible = "samsung,s3c2410-irq"; reg = <0x4a000000 0x100>; interrupt-controller; @@ -39,49 +39,49 @@ }; }; - timer@51000000 { + timer: pwm@51000000 { compatible = "samsung,s3c2410-pwm"; reg = <0x51000000 0x1000>; interrupts = <0 0 10 3>, <0 0 11 3>, <0 0 12 3>, <0 0 13 3>, <0 0 14 3>; - #pwm-cells = <4>; + #pwm-cells = <3>; }; - uart0: serial@50000000 { + uart_0: serial@50000000 { compatible = "samsung,s3c2410-uart"; reg = <0x50000000 0x4000>; interrupts = <1 28 0 4>, <1 28 1 4>; status = "disabled"; }; - uart1: serial@50004000 { + uart_1: serial@50004000 { compatible = "samsung,s3c2410-uart"; reg = <0x50004000 0x4000>; interrupts = <1 23 3 4>, <1 23 4 4>; status = "disabled"; }; - uart2: serial@50008000 { + uart_2: serial@50008000 { compatible = "samsung,s3c2410-uart"; reg = <0x50008000 0x4000>; interrupts = <1 15 6 4>, <1 15 7 4>; status = "disabled"; }; - watchdog@53000000 { + watchdog: watchdog@53000000 { compatible = "samsung,s3c2410-wdt"; reg = <0x53000000 0x100>; interrupts = <0 0 9 3>; status = "disabled"; }; - rtc@57000000 { + rtc: rtc@57000000 { compatible = "samsung,s3c2410-rtc"; reg = <0x57000000 0x100>; interrupts = <0 0 30 3>, <0 0 8 3>; status = "disabled"; }; - i2c@54000000 { + i2c: i2c@54000000 { compatible = "samsung,s3c2410-i2c"; reg = <0x54000000 0x100>; interrupts = <0 0 27 3>; diff --git a/arch/arm/boot/dts/s3c6410-mini6410.dts b/arch/arm/boot/dts/s3c6410-mini6410.dts index 1aeac33b0d34..285555b9ed94 100644 --- a/arch/arm/boot/dts/s3c6410-mini6410.dts +++ b/arch/arm/boot/dts/s3c6410-mini6410.dts @@ -28,29 +28,21 @@ bootargs = "console=ttySAC0,115200n8 earlyprintk rootwait root=/dev/mmcblk0p1"; }; - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - fin_pll: oscillator@0 { - compatible = "fixed-clock"; - reg = <0>; - clock-frequency = <12000000>; - clock-output-names = "fin_pll"; - #clock-cells = <0>; - }; + fin_pll: oscillator-0 { + compatible = "fixed-clock"; + clock-frequency = <12000000>; + clock-output-names = "fin_pll"; + #clock-cells = <0>; + }; - xusbxti: oscillator@1 { - compatible = "fixed-clock"; - reg = <1>; - clock-output-names = "xusbxti"; - clock-frequency = <48000000>; - #clock-cells = <0>; - }; + xusbxti: oscillator-1 { + compatible = "fixed-clock"; + clock-output-names = "xusbxti"; + clock-frequency = <48000000>; + #clock-cells = <0>; }; - srom-cs1@18000000 { + srom-cs1-bus@18000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/s3c6410-smdk6410.dts b/arch/arm/boot/dts/s3c6410-smdk6410.dts index 96267f5f02a8..69c9ec4cf381 100644 --- a/arch/arm/boot/dts/s3c6410-smdk6410.dts +++ b/arch/arm/boot/dts/s3c6410-smdk6410.dts @@ -28,29 +28,21 @@ bootargs = "console=ttySAC0,115200n8 earlyprintk rootwait root=/dev/mmcblk0p1"; }; - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - fin_pll: oscillator@0 { - compatible = "fixed-clock"; - reg = <0>; - clock-frequency = <12000000>; - clock-output-names = "fin_pll"; - #clock-cells = <0>; - }; + fin_pll: oscillator-0 { + compatible = "fixed-clock"; + clock-frequency = <12000000>; + clock-output-names = "fin_pll"; + #clock-cells = <0>; + }; - xusbxti: oscillator@1 { - compatible = "fixed-clock"; - reg = <1>; - clock-output-names = "xusbxti"; - clock-frequency = <48000000>; - #clock-cells = <0>; - }; + xusbxti: oscillator-1 { + compatible = "fixed-clock"; + clock-output-names = "xusbxti"; + clock-frequency = <48000000>; + #clock-cells = <0>; }; - srom-cs1@18000000 { + srom-cs1-bus@18000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/s3c64xx.dtsi b/arch/arm/boot/dts/s3c64xx.dtsi index 2e611df37911..cb11a87dbc42 100644 --- a/arch/arm/boot/dts/s3c64xx.dtsi +++ b/arch/arm/boot/dts/s3c64xx.dtsi @@ -34,7 +34,7 @@ cpu@0 { device_type = "cpu"; - compatible = "arm,arm1176jzf-s", "arm,arm1176"; + compatible = "arm,arm1176jzf-s"; reg = <0x0>; }; }; diff --git a/arch/arm/boot/dts/s5pv210-aquila.dts b/arch/arm/boot/dts/s5pv210-aquila.dts index 14969b6529e8..8e57e5a1f0c5 100644 --- a/arch/arm/boot/dts/s5pv210-aquila.dts +++ b/arch/arm/boot/dts/s5pv210-aquila.dts @@ -11,6 +11,7 @@ */ /dts-v1/; +#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> #include "s5pv210.dtsi" @@ -32,42 +33,40 @@ 0x40000000 0x18000000>; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; + pmic_ap_clk: clock-0 { + /* Workaround for missing clock on PMIC */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; - vtf_reg: fixed-regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "V_TF_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&mp05 4 0>; - enable-active-high; - }; + vtf_reg: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "V_TF_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&mp05 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; - pda_reg: fixed-regulator@1 { - compatible = "regulator-fixed"; - regulator-name = "VCC_1.8V_PDA"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - reg = <1>; - }; + pda_reg: regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "VCC_1.8V_PDA"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; - bat_reg: fixed-regulator@2 { - compatible = "regulator-fixed"; - regulator-name = "V_BAT"; - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - reg = <2>; - }; + bat_reg: regulator-2 { + compatible = "regulator-fixed"; + regulator-name = "V_BAT"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; }; i2c_pmic: i2c-pmic { compatible = "i2c-gpio"; - gpios = <&gpj4 0 0>, /* sda */ - <&gpj4 3 0>; /* scl */ + sda-gpios = <&gpj4 0 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpj4 3 GPIO_ACTIVE_HIGH>; i2c-gpio,delay-us = <2>; /* ~100 kHz */ #address-cells = <1>; #size-cells = <0>; @@ -77,13 +76,13 @@ reg = <0x66>; max8998,pmic-buck1-default-dvs-idx = <0>; - max8998,pmic-buck1-dvs-gpios = <&gph0 3 0>, - <&gph0 4 0>; + max8998,pmic-buck1-dvs-gpios = <&gph0 3 GPIO_ACTIVE_HIGH>, + <&gph0 4 GPIO_ACTIVE_HIGH>; max8998,pmic-buck1-dvs-voltage = <1200000>, <1200000>, <1200000>, <1200000>; max8998,pmic-buck2-default-dvs-idx = <0>; - max8998,pmic-buck2-dvs-gpio = <&gph0 5 0>; + max8998,pmic-buck2-dvs-gpio = <&gph0 5 GPIO_ACTIVE_HIGH>; max8998,pmic-buck2-dvs-voltage = <1200000>, <1200000>; regulators { @@ -228,6 +227,11 @@ regulator-always-on; }; + ap32khz_reg: EN32KHz-AP { + regulator-name = "32KHz AP"; + regulator-always-on; + }; + vichg_reg: ENVICHG { regulator-name = "VICHG"; }; @@ -326,6 +330,11 @@ status = "okay"; }; +&rtc { + clocks = <&clocks CLK_RTC>, <&pmic_ap_clk>; + clock-names = "rtc", "rtc_src"; +}; + &sdhci0 { bus-width = <4>; non-removable; diff --git a/arch/arm/boot/dts/s5pv210-aries.dtsi b/arch/arm/boot/dts/s5pv210-aries.dtsi index 822207f63ee0..bd4450dbdcb6 100644 --- a/arch/arm/boot/dts/s5pv210-aries.dtsi +++ b/arch/arm/boot/dts/s5pv210-aries.dtsi @@ -47,6 +47,18 @@ }; }; + pmic_ap_clk: clock-0 { + /* Workaround for missing clock on PMIC */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + + bt_codec: bt_sco { + compatible = "linux,bt-sco"; + #sound-dai-cells = <0>; + }; + vibrator_pwr: regulator-fixed-0 { compatible = "regulator-fixed"; regulator-name = "vibrator-en"; @@ -54,7 +66,7 @@ gpio = <&gpj1 1 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; - pinctr-0 = <&vibrator_ena>; + pinctrl-0 = <&vibrator_ena>; }; touchkey_vdd: regulator-fixed-1 { @@ -533,7 +545,7 @@ value = <0x5200>; }; - spi_lcd: spi-gpio-0 { + spi_lcd: spi-2 { compatible = "spi-gpio"; #address-cells = <1>; #size-cells = <0>; @@ -624,6 +636,11 @@ }; }; +&i2s0 { + dmas = <&pdma0 9>, <&pdma0 10>, <&pdma0 11>; + status = "okay"; +}; + &mfc { memory-region = <&mfc_left>, <&mfc_right>; }; @@ -815,6 +832,11 @@ samsung,pwm-outputs = <1>; }; +&rtc { + clocks = <&clocks CLK_RTC>, <&pmic_ap_clk>; + clock-names = "rtc", "rtc_src"; +}; + &sdhci1 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/s5pv210-fascinate4g.dts b/arch/arm/boot/dts/s5pv210-fascinate4g.dts index 65eed01cfced..ca064359dd30 100644 --- a/arch/arm/boot/dts/s5pv210-fascinate4g.dts +++ b/arch/arm/boot/dts/s5pv210-fascinate4g.dts @@ -35,6 +35,80 @@ linux,code = <KEY_VOLUMEUP>; }; }; + + headset_micbias_reg: regulator-fixed-3 { + compatible = "regulator-fixed"; + regulator-name = "Headset_Micbias"; + gpio = <&gpj2 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&headset_micbias_ena>; + }; + + main_micbias_reg: regulator-fixed-4 { + compatible = "regulator-fixed"; + regulator-name = "Main_Micbias"; + gpio = <&gpj4 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&main_micbias_ena>; + }; + + sound { + compatible = "samsung,fascinate4g-wm8994"; + + model = "Fascinate4G"; + + extcon = <&fsa9480>; + + main-micbias-supply = <&main_micbias_reg>; + headset-micbias-supply = <&headset_micbias_reg>; + + earpath-sel-gpios = <&gpj2 6 GPIO_ACTIVE_HIGH>; + + io-channels = <&adc 3>; + io-channel-names = "headset-detect"; + headset-detect-gpios = <&gph0 6 GPIO_ACTIVE_HIGH>; + headset-key-gpios = <&gph3 6 GPIO_ACTIVE_HIGH>; + + samsung,audio-routing = + "HP", "HPOUT1L", + "HP", "HPOUT1R", + + "SPK", "SPKOUTLN", + "SPK", "SPKOUTLP", + + "RCV", "HPOUT2N", + "RCV", "HPOUT2P", + + "LINE", "LINEOUT2N", + "LINE", "LINEOUT2P", + + "IN1LP", "Main Mic", + "IN1LN", "Main Mic", + + "IN1RP", "Headset Mic", + "IN1RN", "Headset Mic", + + "Modem Out", "Modem TX", + "Modem RX", "Modem In", + + "Bluetooth SPK", "TX", + "RX", "Bluetooth Mic"; + + pinctrl-names = "default"; + pinctrl-0 = <&headset_det &earpath_sel>; + + cpu { + sound-dai = <&i2s0>, <&bt_codec>; + }; + + codec { + sound-dai = <&wm8994>; + }; + }; }; &fg { @@ -51,6 +125,12 @@ pinctrl-names = "default"; pinctrl-0 = <&sleep_cfg>; + headset_det: headset-det { + samsung,pins = "gph0-6", "gph3-6"; + samsung,pin-function = <EXYNOS_PIN_FUNC_F>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + }; + fg_irq: fg-irq { samsung,pins = "gph3-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_F>; @@ -58,6 +138,24 @@ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; + headset_micbias_ena: headset-micbias-ena { + samsung,pins = "gpj2-5"; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + }; + + earpath_sel: earpath-sel { + samsung,pins = "gpj2-6"; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + }; + + main_micbias_ena: main-micbias-ena { + samsung,pins = "gpj4-2"; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + }; + /* Based on vendor kernel v2.6.35.7 */ sleep_cfg: sleep-cfg { PIN_SLP(gpa0-0, PREV, NONE); diff --git a/arch/arm/boot/dts/s5pv210-galaxys.dts b/arch/arm/boot/dts/s5pv210-galaxys.dts index 5d10dd67eacc..560f830b6f6b 100644 --- a/arch/arm/boot/dts/s5pv210-galaxys.dts +++ b/arch/arm/boot/dts/s5pv210-galaxys.dts @@ -72,6 +72,73 @@ pinctrl-0 = <&fm_irq &fm_rst>; }; }; + + micbias_reg: regulator-fixed-3 { + compatible = "regulator-fixed"; + regulator-name = "MICBIAS"; + gpio = <&gpj4 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&micbias_reg_ena>; + }; + + sound { + compatible = "samsung,aries-wm8994"; + + model = "Aries"; + + extcon = <&fsa9480>; + + main-micbias-supply = <&micbias_reg>; + headset-micbias-supply = <&micbias_reg>; + + earpath-sel-gpios = <&gpj2 6 GPIO_ACTIVE_HIGH>; + + io-channels = <&adc 3>; + io-channel-names = "headset-detect"; + headset-detect-gpios = <&gph0 6 GPIO_ACTIVE_LOW>; + headset-key-gpios = <&gph3 6 GPIO_ACTIVE_HIGH>; + + samsung,audio-routing = + "HP", "HPOUT1L", + "HP", "HPOUT1R", + + "SPK", "SPKOUTLN", + "SPK", "SPKOUTLP", + + "RCV", "HPOUT2N", + "RCV", "HPOUT2P", + + "LINE", "LINEOUT2N", + "LINE", "LINEOUT2P", + + "IN1LP", "Main Mic", + "IN1LN", "Main Mic", + + "IN1RP", "Headset Mic", + "IN1RN", "Headset Mic", + + "IN2LN", "FM In", + "IN2RN", "FM In", + + "Modem Out", "Modem TX", + "Modem RX", "Modem In", + + "Bluetooth SPK", "TX", + "RX", "Bluetooth Mic"; + + pinctrl-names = "default"; + pinctrl-0 = <&headset_det &earpath_sel>; + + cpu { + sound-dai = <&i2s0>, <&bt_codec>; + }; + + codec { + sound-dai = <&wm8994>; + }; + }; }; &aliases { @@ -88,6 +155,12 @@ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; + headset_det: headset-det { + samsung,pins = "gph0-6", "gph3-6"; + samsung,pin-function = <EXYNOS_PIN_FUNC_F>; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + }; + fm_irq: fm-irq { samsung,pins = "gpj2-4"; samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; @@ -102,6 +175,12 @@ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; + earpath_sel: earpath-sel { + samsung,pins = "gpj2-6"; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + }; + massmemory_en: massmemory-en { samsung,pins = "gpj2-7"; samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; @@ -109,6 +188,12 @@ samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; }; + micbias_reg_ena: micbias-reg-ena { + samsung,pins = "gpj4-2"; + samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + }; + /* Based on CyanogenMod 3.0.101 kernel */ sleep_cfg: sleep-cfg { PIN_SLP(gpa0-0, PREV, NONE); diff --git a/arch/arm/boot/dts/s5pv210-goni.dts b/arch/arm/boot/dts/s5pv210-goni.dts index fbbd93707404..ad8d5d2fa32d 100644 --- a/arch/arm/boot/dts/s5pv210-goni.dts +++ b/arch/arm/boot/dts/s5pv210-goni.dts @@ -11,6 +11,8 @@ */ /dts-v1/; +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/input/input.h> #include "s5pv210.dtsi" @@ -33,52 +35,49 @@ 0x50000000 0x08000000>; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; + pmic_ap_clk: clock-0 { + /* Workaround for missing clock on PMIC */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; - vtf_reg: fixed-regulator@0 { - compatible = "regulator-fixed"; - regulator-name = "V_TF_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - reg = <0>; - gpio = <&mp05 4 0>; - enable-active-high; - }; + vtf_reg: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "V_TF_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&mp05 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; - pda_reg: fixed-regulator@1 { - compatible = "regulator-fixed"; - regulator-name = "VCC_1.8V_PDA"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - reg = <1>; - }; + pda_reg: regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "VCC_1.8V_PDA"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; - bat_reg: fixed-regulator@2 { - compatible = "regulator-fixed"; - regulator-name = "V_BAT"; - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - reg = <2>; - }; + bat_reg: regulator-2 { + compatible = "regulator-fixed"; + regulator-name = "V_BAT"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; - tsp_reg: fixed-regulator@3 { - compatible = "regulator-fixed"; - regulator-name = "TSP_VDD"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - reg = <3>; - gpio = <&gpj1 3 0>; - enable-active-high; - }; + tsp_reg: regulator-3 { + compatible = "regulator-fixed"; + regulator-name = "TSP_VDD"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpj1 3 GPIO_ACTIVE_HIGH>; + enable-active-high; }; i2c_pmic: i2c-pmic { compatible = "i2c-gpio"; - gpios = <&gpj4 0 0>, /* sda */ - <&gpj4 3 0>; /* scl */ + sda-gpios = <&gpj4 0 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpj4 3 GPIO_ACTIVE_HIGH>; i2c-gpio,delay-us = <2>; /* ~100 kHz */ #address-cells = <1>; #size-cells = <0>; @@ -88,13 +87,13 @@ reg = <0x66>; max8998,pmic-buck1-default-dvs-idx = <0>; - max8998,pmic-buck1-dvs-gpios = <&gph0 3 0>, - <&gph0 4 0>; + max8998,pmic-buck1-dvs-gpios = <&gph0 3 GPIO_ACTIVE_HIGH>, + <&gph0 4 GPIO_ACTIVE_HIGH>; max8998,pmic-buck1-dvs-voltage = <1200000>, <1200000>, <1200000>, <1200000>; max8998,pmic-buck2-default-dvs-idx = <0>; - max8998,pmic-buck2-dvs-gpio = <&gph0 5 0>; + max8998,pmic-buck2-dvs-gpio = <&gph0 5 GPIO_ACTIVE_HIGH>; max8998,pmic-buck2-dvs-voltage = <1200000>, <1200000>; regulators { @@ -224,6 +223,11 @@ regulator-max-microvolt = <1200000>; regulator-always-on; }; + + ap32khz_reg: EN32KHz-AP { + regulator-name = "32KHz AP"; + regulator-always-on; + }; }; }; }; @@ -308,6 +312,11 @@ status = "okay"; }; +&rtc { + clocks = <&clocks CLK_RTC>, <&pmic_ap_clk>; + clock-names = "rtc", "rtc_src"; +}; + &sdhci0 { bus-width = <4>; non-removable; @@ -348,7 +357,7 @@ compatible = "atmel,maxtouch"; reg = <0x4a>; interrupt-parent = <&gpj0>; - interrupts = <5 2>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; atmel,x-line = <17>; atmel,y-line = <11>; @@ -378,8 +387,8 @@ clock-frequency = <16000000>; clocks = <&camera 0>; clock-names = "mclk"; - nreset-gpios = <&gpb 2 0>; - nstby-gpios = <&gpb 0 0>; + nreset-gpios = <&gpb 2 GPIO_ACTIVE_HIGH>; + nstby-gpios = <&gpb 0 GPIO_ACTIVE_HIGH>; port { noon010pc30_ep: endpoint { diff --git a/arch/arm/boot/dts/s5pv210-smdkc110.dts b/arch/arm/boot/dts/s5pv210-smdkc110.dts index e5aec6c526fb..0c623b78af72 100644 --- a/arch/arm/boot/dts/s5pv210-smdkc110.dts +++ b/arch/arm/boot/dts/s5pv210-smdkc110.dts @@ -30,6 +30,13 @@ device_type = "memory"; reg = <0x20000000 0x20000000>; }; + + pmic_ap_clk: clock-0 { + /* Workaround for missing PMIC and its clock */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; }; &xusbxti { @@ -54,6 +61,8 @@ &rtc { status = "okay"; + clocks = <&clocks CLK_RTC>, <&pmic_ap_clk>; + clock-names = "rtc", "rtc_src"; }; &i2c0 { diff --git a/arch/arm/boot/dts/s5pv210-smdkv210.dts b/arch/arm/boot/dts/s5pv210-smdkv210.dts index 84b38f185199..7459e41e8ef1 100644 --- a/arch/arm/boot/dts/s5pv210-smdkv210.dts +++ b/arch/arm/boot/dts/s5pv210-smdkv210.dts @@ -15,6 +15,7 @@ */ /dts-v1/; +#include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/input/input.h> #include "s5pv210.dtsi" @@ -31,11 +32,18 @@ reg = <0x20000000 0x40000000>; }; - ethernet@18000000 { + pmic_ap_clk: clock-0 { + /* Workaround for missing PMIC and its clock */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + + ethernet@a8000000 { compatible = "davicom,dm9000"; reg = <0xA8000000 0x2 0xA8000002 0x2>; interrupt-parent = <&gph1>; - interrupts = <1 4>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; local-mac-address = [00 00 de ad be ef]; davicom,no-eeprom; }; @@ -147,6 +155,8 @@ &rtc { status = "okay"; + clocks = <&clocks CLK_RTC>, <&pmic_ap_clk>; + clock-names = "rtc", "rtc_src"; }; &sdhci0 { diff --git a/arch/arm/boot/dts/s5pv210-torbreck.dts b/arch/arm/boot/dts/s5pv210-torbreck.dts index cd25e72ccd84..e18259737684 100644 --- a/arch/arm/boot/dts/s5pv210-torbreck.dts +++ b/arch/arm/boot/dts/s5pv210-torbreck.dts @@ -30,6 +30,13 @@ device_type = "memory"; reg = <0x20000000 0x20000000>; }; + + pmic_ap_clk: clock-0 { + /* Workaround for missing PMIC and its clock */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; }; &xusbxti { @@ -54,6 +61,8 @@ &rtc { status = "okay"; + clocks = <&clocks CLK_RTC>, <&pmic_ap_clk>; + clock-names = "rtc", "rtc_src"; }; &sdhci0 { diff --git a/arch/arm/boot/dts/s5pv210.dtsi b/arch/arm/boot/dts/s5pv210.dtsi index 1b0ee884e91d..2871351ab907 100644 --- a/arch/arm/boot/dts/s5pv210.dtsi +++ b/arch/arm/boot/dts/s5pv210.dtsi @@ -52,34 +52,26 @@ }; }; + xxti: oscillator-0 { + compatible = "fixed-clock"; + clock-frequency = <0>; + clock-output-names = "xxti"; + #clock-cells = <0>; + }; + + xusbxti: oscillator-1 { + compatible = "fixed-clock"; + clock-frequency = <0>; + clock-output-names = "xusbxti"; + #clock-cells = <0>; + }; + soc { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges; - external-clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - xxti: oscillator@0 { - compatible = "fixed-clock"; - reg = <0>; - clock-frequency = <0>; - clock-output-names = "xxti"; - #clock-cells = <0>; - }; - - xusbxti: oscillator@1 { - compatible = "fixed-clock"; - reg = <1>; - clock-frequency = <0>; - clock-output-names = "xusbxti"; - #clock-cells = <0>; - }; - }; - onenand: onenand@b0600000 { compatible = "samsung,s5pv210-onenand"; reg = <0xb0600000 0x2000>, @@ -100,19 +92,16 @@ }; clocks: clock-controller@e0100000 { - compatible = "samsung,s5pv210-clock", "simple-bus"; + compatible = "samsung,s5pv210-clock"; reg = <0xe0100000 0x10000>; clock-names = "xxti", "xusbxti"; clocks = <&xxti>, <&xusbxti>; #clock-cells = <1>; - #address-cells = <1>; - #size-cells = <1>; - ranges; + }; - pmu_syscon: syscon@e0108000 { - compatible = "samsung-s5pv210-pmu", "syscon"; - reg = <0xe0108000 0x8000>; - }; + pmu_syscon: syscon@e0108000 { + compatible = "samsung-s5pv210-pmu", "syscon"; + reg = <0xe0108000 0x8000>; }; pinctrl0: pinctrl@e0200000 { @@ -128,35 +117,28 @@ }; }; - amba { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges; - - pdma0: dma@e0900000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0xe0900000 0x1000>; - interrupt-parent = <&vic0>; - interrupts = <19>; - clocks = <&clocks CLK_PDMA0>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - }; + pdma0: dma@e0900000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0xe0900000 0x1000>; + interrupt-parent = <&vic0>; + interrupts = <19>; + clocks = <&clocks CLK_PDMA0>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + }; - pdma1: dma@e0a00000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0xe0a00000 0x1000>; - interrupt-parent = <&vic0>; - interrupts = <20>; - clocks = <&clocks CLK_PDMA1>; - clock-names = "apb_pclk"; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - }; + pdma1: dma@e0a00000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0xe0a00000 0x1000>; + interrupt-parent = <&vic0>; + interrupts = <20>; + clocks = <&clocks CLK_PDMA1>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; }; adc: adc@e1700000 { @@ -241,43 +223,36 @@ status = "disabled"; }; - audio-subsystem { - compatible = "samsung,s5pv210-audss", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - clk_audss: clock-controller@eee10000 { - compatible = "samsung,s5pv210-audss-clock"; - reg = <0xeee10000 0x1000>; - clock-names = "hclk", "xxti", - "fout_epll", - "sclk_audio0"; - clocks = <&clocks DOUT_HCLKP>, <&xxti>, - <&clocks FOUT_EPLL>, - <&clocks SCLK_AUDIO0>; - #clock-cells = <1>; - }; + clk_audss: clock-controller@eee10000 { + compatible = "samsung,s5pv210-audss-clock"; + reg = <0xeee10000 0x1000>; + clock-names = "hclk", "xxti", + "fout_epll", + "sclk_audio0"; + clocks = <&clocks DOUT_HCLKP>, <&xxti>, + <&clocks FOUT_EPLL>, + <&clocks SCLK_AUDIO0>; + #clock-cells = <1>; + }; - i2s0: i2s@eee30000 { - compatible = "samsung,s5pv210-i2s"; - reg = <0xeee30000 0x1000>; - interrupt-parent = <&vic2>; - interrupts = <16>; - dma-names = "rx", "tx", "tx-sec"; - dmas = <&pdma1 9>, <&pdma1 10>, <&pdma1 11>; - clock-names = "iis", - "i2s_opclk0", - "i2s_opclk1"; - clocks = <&clk_audss CLK_I2S>, - <&clk_audss CLK_I2S>, - <&clk_audss CLK_DOUT_AUD_BUS>; - samsung,idma-addr = <0xc0010000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_bus>; - #sound-dai-cells = <0>; - status = "disabled"; - }; + i2s0: i2s@eee30000 { + compatible = "samsung,s5pv210-i2s"; + reg = <0xeee30000 0x1000>; + interrupt-parent = <&vic2>; + interrupts = <16>; + dma-names = "rx", "tx", "tx-sec"; + dmas = <&pdma1 9>, <&pdma1 10>, <&pdma1 11>; + clock-names = "iis", + "i2s_opclk0", + "i2s_opclk1"; + clocks = <&clk_audss CLK_I2S>, + <&clk_audss CLK_I2S>, + <&clk_audss CLK_DOUT_AUD_BUS>; + samsung,idma-addr = <0xc0010000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_bus>; + #sound-dai-cells = <0>; + status = "disabled"; }; i2s1: i2s@e2100000 { diff --git a/arch/arm/boot/dts/sam9x60.dtsi b/arch/arm/boot/dts/sam9x60.dtsi index 42f76212d472..84066c1298df 100644 --- a/arch/arm/boot/dts/sam9x60.dtsi +++ b/arch/arm/boot/dts/sam9x60.dtsi @@ -32,16 +32,17 @@ }; cpus { - #address-cells = <0>; + #address-cells = <1>; #size-cells = <0>; - cpu { + cpu@0 { compatible = "arm,arm926ej-s"; device_type = "cpu"; + reg = <0>; }; }; - memory { + memory@20000000 { device_type = "memory"; reg = <0x20000000 0x10000000>; }; @@ -61,6 +62,9 @@ sram: sram@300000 { compatible = "mmio-sram"; reg = <0x00300000 0x100000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00300000 0x100000>; }; ahb { diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi index d7f25706892d..2ddc85dff8ce 100644 --- a/arch/arm/boot/dts/sama5d2.dtsi +++ b/arch/arm/boot/dts/sama5d2.dtsi @@ -72,7 +72,7 @@ }; }; - memory { + memory@20000000 { device_type = "memory"; reg = <0x20000000 0x20000000>; }; @@ -94,6 +94,9 @@ ns_sram: sram@200000 { compatible = "mmio-sram"; reg = <0x00200000 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00200000 0x20000>; }; ahb { @@ -106,6 +109,10 @@ compatible = "mmio-sram"; no-memory-wc; reg = <0x00100000 0x2400>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00100000 0x2400>; + }; usb0: gadget@300000 { @@ -535,6 +542,8 @@ compatible = "atmel,at91rm9200-spi"; reg = <0x400 0x200>; interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; + #address-cells = <1>; + #size-cells = <0>; clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; clock-names = "spi_clk"; dmas = <&dma0 @@ -603,6 +612,8 @@ compatible = "atmel,at91rm9200-spi"; reg = <0x400 0x200>; interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>; + #address-cells = <1>; + #size-cells = <0>; clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; clock-names = "spi_clk"; dmas = <&dma0 @@ -810,6 +821,8 @@ compatible = "atmel,at91rm9200-spi"; reg = <0x400 0x200>; interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>; + #address-cells = <1>; + #size-cells = <0>; clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; clock-names = "spi_clk"; dmas = <&dma0 @@ -878,6 +891,8 @@ compatible = "atmel,at91rm9200-spi"; reg = <0x400 0x200>; interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; + #address-cells = <1>; + #size-cells = <0>; clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; clock-names = "spi_clk"; dmas = <&dma0 @@ -947,6 +962,8 @@ compatible = "atmel,at91rm9200-spi"; reg = <0x400 0x200>; interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; + #address-cells = <1>; + #size-cells = <0>; clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; clock-names = "spi_clk"; dmas = <&dma0 diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index 0bb5b6fa0748..86137f8d2b45 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -55,7 +55,7 @@ interrupts = <46 IRQ_TYPE_LEVEL_HIGH 0>; }; - memory { + memory@20000000 { device_type = "memory"; reg = <0x20000000 0x8000000>; }; @@ -83,6 +83,9 @@ sram: sram@300000 { compatible = "mmio-sram"; reg = <0x00300000 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00300000 0x20000>; }; ahb { @@ -1073,6 +1076,9 @@ compatible = "mmio-sram"; no-memory-wc; reg = <0x200000 0x2400>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x200000 0x2400>; }; usb0: gadget@500000 { diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi index 65566e4b78d8..384335635792 100644 --- a/arch/arm/boot/dts/sama5d3xcm.dtsi +++ b/arch/arm/boot/dts/sama5d3xcm.dtsi @@ -14,7 +14,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@20000000 { reg = <0x20000000 0x20000000>; }; diff --git a/arch/arm/boot/dts/sama5d3xcm_cmp.dtsi b/arch/arm/boot/dts/sama5d3xcm_cmp.dtsi index 9d2563602cbe..5579c955f141 100644 --- a/arch/arm/boot/dts/sama5d3xcm_cmp.dtsi +++ b/arch/arm/boot/dts/sama5d3xcm_cmp.dtsi @@ -12,7 +12,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@20000000 { reg = <0x20000000 0x20000000>; }; diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi index 2d9f853ab15f..04f24cf752d3 100644 --- a/arch/arm/boot/dts/sama5d4.dtsi +++ b/arch/arm/boot/dts/sama5d4.dtsi @@ -53,7 +53,7 @@ }; }; - memory { + memory@20000000 { device_type = "memory"; reg = <0x20000000 0x20000000>; }; @@ -81,6 +81,9 @@ ns_sram: sram@210000 { compatible = "mmio-sram"; reg = <0x00210000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00210000 0x10000>; }; ahb { @@ -93,6 +96,9 @@ compatible = "mmio-sram"; no-memory-wc; reg = <0x100000 0x2400>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x100000 0x2400>; }; usb0: gadget@400000 { diff --git a/arch/arm/boot/dts/sd5203.dts b/arch/arm/boot/dts/sd5203.dts new file mode 100644 index 000000000000..3cc9a23910be --- /dev/null +++ b/arch/arm/boot/dts/sd5203.dts @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2020 Hisilicon Limited. + * + * DTS file for Hisilicon SD5203 Board + */ + +/dts-v1/; + +/ { + model = "Hisilicon SD5203"; + compatible = "H836ASDJ", "hisilicon,sd5203"; + interrupt-parent = <&vic>; + #address-cells = <1>; + #size-cells = <1>; + + chosen { + bootargs="console=ttyS0,9600 earlycon=uart8250,mmio32,0x1600d000"; + }; + + aliases { + serial0 = &uart0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0 { + device_type = "cpu"; + compatible = "arm,arm926ej-s"; + reg = <0x0>; + }; + }; + + memory@30000000 { + device_type = "memory"; + reg = <0x30000000 0x8000000>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + + vic: interrupt-controller@10130000 { + compatible = "snps,dw-apb-ictl"; + reg = <0x10130000 0x1000>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + refclk125mhz: refclk125mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + timer0: timer@16002000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x16002000 0x1000>; + interrupts = <4>; + clocks = <&refclk125mhz>; + clock-names = "apb_pclk"; + }; + + timer1: timer@16003000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x16003000 0x1000>; + interrupts = <5>; + clocks = <&refclk125mhz>; + clock-names = "apb_pclk"; + }; + + uart0: serial@1600d000 { + compatible = "snps,dw-apb-uart"; + reg = <0x1600d000 0x1000>; + bus_id = "uart0"; + clocks = <&refclk125mhz>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + interrupts = <17>; + }; + + uart1: serial@1600c000 { + compatible = "snps,dw-apb-uart"; + reg = <0x1600c000 0x1000>; + clocks = <&refclk125mhz>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + interrupts = <16>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi index a4d63125ac56..30c67acc4e35 100644 --- a/arch/arm/boot/dts/sh73a0.dtsi +++ b/arch/arm/boot/dts/sh73a0.dtsi @@ -448,7 +448,7 @@ status = "disabled"; }; - pfc: pin-controller@e6050000 { + pfc: pinctrl@e6050000 { compatible = "renesas,pfc-sh73a0"; reg = <0xe6050000 0x8000>, <0xe605801c 0x1c>; diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi index f187da4485f4..c87b881b2c8b 100644 --- a/arch/arm/boot/dts/spear13xx.dtsi +++ b/arch/arm/boot/dts/spear13xx.dtsi @@ -43,7 +43,7 @@ 0 7 0x04>; }; - L2: l2-cache { + L2: cache-controller { compatible = "arm,pl310-cache"; reg = <0xed000000 0x1000>; cache-unified; diff --git a/arch/arm/boot/dts/ste-href.dtsi b/arch/arm/boot/dts/ste-href.dtsi index 33e3b0b3c53d..ff47cbf6ed3b 100644 --- a/arch/arm/boot/dts/ste-href.dtsi +++ b/arch/arm/boot/dts/ste-href.dtsi @@ -58,16 +58,21 @@ reg = <0x33>; label = "lp5521_pri"; clock-mode = /bits/ 8 <2>; - chan0 { + #address-cells = <1>; + #size-cells = <0>; + chan@0 { + reg = <0>; led-cur = /bits/ 8 <0x2f>; max-cur = /bits/ 8 <0x5f>; linux,default-trigger = "heartbeat"; }; - chan1 { + chan@1 { + reg = <1>; led-cur = /bits/ 8 <0x2f>; max-cur = /bits/ 8 <0x5f>; }; - chan2 { + chan@2 { + reg = <2>; led-cur = /bits/ 8 <0x2f>; max-cur = /bits/ 8 <0x5f>; }; @@ -77,15 +82,20 @@ reg = <0x34>; label = "lp5521_sec"; clock-mode = /bits/ 8 <2>; - chan0 { + #address-cells = <1>; + #size-cells = <0>; + chan@0 { + reg = <0>; led-cur = /bits/ 8 <0x2f>; max-cur = /bits/ 8 <0x5f>; }; - chan1 { + chan@1 { + reg = <1>; led-cur = /bits/ 8 <0x2f>; max-cur = /bits/ 8 <0x5f>; }; - chan2 { + chan@2 { + reg = <2>; led-cur = /bits/ 8 <0x2f>; max-cur = /bits/ 8 <0x5f>; }; diff --git a/arch/arm/boot/dts/ste-ux500-samsung-golden.dts b/arch/arm/boot/dts/ste-ux500-samsung-golden.dts index 1e26b711d43d..a1093cb37dc7 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-golden.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-golden.dts @@ -316,6 +316,28 @@ }; }; }; + + mcde@a0350000 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&dsi_default_mode>; + + dsi-controller@a0351000 { + panel@0 { + compatible = "samsung,s6e63m0"; + reg = <0>; + vdd3-supply = <&panel_reg_3v0>; + vci-supply = <&panel_reg_1v8>; + reset-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; + /* ESD (electrostatic discharge) detection interrupt */ + interrupt-parent = <&gpio2>; + interrupts = <18 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "esd"; + pinctrl-names = "default"; + pinctrl-0 = <&display_default_mode>; + }; + }; + }; }; gpio-keys { @@ -415,6 +437,40 @@ pinctrl-names = "default"; pinctrl-0 = <&wlan_en_default>; }; + + /* MIC5366 GPIO-controlled regulator */ + panel_reg_1v8: regulator-panel-1v8 { + compatible = "regulator-fixed"; + + regulator-name = "panel-fixed-supply"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + /* GPIO219 */ + gpio = <&gpio6 27 GPIO_ACTIVE_HIGH>; + + startup-delay-us = <200>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&panel_reg_default_mode>; + }; + + /* MIC5366 GPIO-controlled regulator */ + panel_reg_3v0: regulator-panel-3v0 { + compatible = "regulator-fixed"; + + regulator-name = "panel-fixed-supply"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + /* GPIO219 */ + gpio = <&gpio6 27 GPIO_ACTIVE_HIGH>; + + startup-delay-us = <200>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&panel_reg_default_mode>; + }; }; &pinctrl { @@ -476,6 +532,41 @@ }; }; + mcde { + dsi_default_mode: dsi_default { + default_mux1 { + /* Mux in VSI0 used for DSI TE */ + function = "lcd"; + groups = + "lcdvsi0_a_1"; /* VSI0 for LCD */ + }; + default_cfg1 { + pins = + "GPIO68_E1"; /* VSI0 */ + ste,config = <&in_nopull>; + }; + }; + }; + + display { + display_default_mode: display_default { + golden_cfg1 { + pins = "GPIO139_C9"; /* MIPI_DSI0_RESET_N */ + ste,config = <&gpio_out_lo>; + }; + golden_cfg2 { + pins = "GPIO82_C1"; /* LDI_ESD_DET */ + ste,config = <&gpio_in_pu>; + }; + }; + panel_reg_default_mode: panel_reg_default { + golden_cfg1 { + pins = "GPIO219_AG10"; /* LCD_PWR_EN */ + ste,config = <&gpio_out_lo>; + }; + }; + }; + proximity { proximity_default: proximity_default { golden_cfg1 { diff --git a/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts b/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts index d6f6ac04a48a..27722c42b61c 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts @@ -108,15 +108,12 @@ }; }; - /* - * FIXME: this is not quite GPIO backlight. This is a - * KTD253 one-wire GPIO-controlled backlight. It can - * work as a GPIO backlight. - */ - gpio_bl: backlight { - compatible = "gpio-backlight"; + ktd253: backlight { + compatible = "kinetic,ktd253"; /* GPIO 69 */ - gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; + /* Default to 13/32 brightness */ + default-brightness = <13>; pinctrl-names = "default"; pinctrl-0 = <&gpio_backlight_default_mode>; }; @@ -409,7 +406,7 @@ reset-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&display_default_mode>; - backlight = <&gpio_bl>; + backlight = <&ktd253>; }; }; }; diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi index 69e2f1e78ed6..7febe19e780d 100644 --- a/arch/arm/boot/dts/stm32h743.dtsi +++ b/arch/arm/boot/dts/stm32h743.dtsi @@ -110,6 +110,7 @@ compatible = "st,stm32h7-spi"; reg = <0x40003800 0x400>; interrupts = <36>; + resets = <&rcc STM32H7_APB1L_RESET(SPI2)>; clocks = <&rcc SPI2_CK>; status = "disabled"; @@ -121,12 +122,13 @@ compatible = "st,stm32h7-spi"; reg = <0x40003c00 0x400>; interrupts = <51>; + resets = <&rcc STM32H7_APB1L_RESET(SPI3)>; clocks = <&rcc SPI3_CK>; status = "disabled"; }; usart2: serial@40004400 { - compatible = "st,stm32f7-uart"; + compatible = "st,stm32h7-uart"; reg = <0x40004400 0x400>; interrupts = <38>; status = "disabled"; @@ -194,7 +196,7 @@ }; usart1: serial@40011000 { - compatible = "st,stm32f7-uart"; + compatible = "st,stm32h7-uart"; reg = <0x40011000 0x400>; interrupts = <37>; status = "disabled"; @@ -207,6 +209,7 @@ compatible = "st,stm32h7-spi"; reg = <0x40013000 0x400>; interrupts = <35>; + resets = <&rcc STM32H7_APB2_RESET(SPI1)>; clocks = <&rcc SPI1_CK>; status = "disabled"; }; @@ -217,6 +220,7 @@ compatible = "st,stm32h7-spi"; reg = <0x40013400 0x400>; interrupts = <84>; + resets = <&rcc STM32H7_APB2_RESET(SPI4)>; clocks = <&rcc SPI4_CK>; status = "disabled"; }; @@ -227,6 +231,7 @@ compatible = "st,stm32h7-spi"; reg = <0x40015000 0x400>; interrupts = <85>; + resets = <&rcc STM32H7_APB2_RESET(SPI5)>; clocks = <&rcc SPI5_CK>; status = "disabled"; }; @@ -329,6 +334,16 @@ status = "disabled"; }; + ltdc: display-controller@50001000 { + compatible = "st,stm32-ltdc"; + reg = <0x50001000 0x200>; + interrupts = <88>, <89>; + resets = <&rcc STM32H7_APB3_RESET(LTDC)>; + clocks = <&rcc LTDC_CK>; + clock-names = "lcd"; + status = "disabled"; + }; + mdma1: dma-controller@52000000 { compatible = "st,stm32h7-mdma"; reg = <0x52000000 0x1000>; @@ -372,6 +387,7 @@ compatible = "st,stm32h7-spi"; reg = <0x58001400 0x400>; interrupts = <86>; + resets = <&rcc STM32H7_APB4_RESET(SPI6)>; clocks = <&rcc SPI6_CK>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index b5a66429670c..d84686e00370 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -1437,6 +1437,24 @@ }; }; + sdmmc2_d47_pins_d: sdmmc2-d47-3 { + pins { + pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ + <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */ + <STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */ + <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */ + }; + }; + + sdmmc2_d47_sleep_pins_d: sdmmc2-d47-sleep-3 { + pins { + pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */ + <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */ + <STM32_PINMUX('E', 5, ANALOG)>, /* SDMMC2_D6 */ + <STM32_PINMUX('C', 7, ANALOG)>; /* SDMMC2_D7 */ + }; + }; + sdmmc3_b4_pins_a: sdmmc3-b4-0 { pins1 { pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */ @@ -1700,6 +1718,14 @@ }; }; + uart8_rtscts_pins_a: uart8rtscts-0 { + pins { + pinmux = <STM32_PINMUX('G', 7, AF8)>, /* UART8_RTS */ + <STM32_PINMUX('G', 10, AF8)>; /* UART8_CTS */ + bias-disable; + }; + }; + spi4_pins_a: spi4-0 { pins { pinmux = <STM32_PINMUX('E', 12, AF5)>, /* SPI4_SCK */ diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index bfe29023fbd5..84757901cd8d 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -23,6 +23,13 @@ }; }; + arm-pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>; + interrupt-parent = <&intc>; + }; + psci { compatible = "arm,psci-1.0"; method = "smc"; @@ -1302,23 +1309,38 @@ dma-requests = <48>; }; - fmc: nand-controller@58002000 { - compatible = "st,stm32mp15-fmc2"; - reg = <0x58002000 0x1000>, - <0x80000000 0x1000>, - <0x88010000 0x1000>, - <0x88020000 0x1000>, - <0x81000000 0x1000>, - <0x89010000 0x1000>, - <0x89020000 0x1000>; - interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; - dmas = <&mdma1 20 0x10 0x12000a02 0x0 0x0>, - <&mdma1 20 0x10 0x12000a08 0x0 0x0>, - <&mdma1 21 0x10 0x12000a0a 0x0 0x0>; - dma-names = "tx", "rx", "ecc"; + fmc: memory-controller@58002000 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "st,stm32mp1-fmc2-ebi"; + reg = <0x58002000 0x1000>; clocks = <&rcc FMC_K>; resets = <&rcc FMC_R>; status = "disabled"; + + ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ + <1 0 0x64000000 0x04000000>, /* EBI CS 2 */ + <2 0 0x68000000 0x04000000>, /* EBI CS 3 */ + <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ + <4 0 0x80000000 0x10000000>; /* NAND */ + + nand-controller@4,0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32mp1-fmc2-nfc"; + reg = <4 0x00000000 0x1000>, + <4 0x08010000 0x1000>, + <4 0x08020000 0x1000>, + <4 0x01000000 0x1000>, + <4 0x09010000 0x1000>, + <4 0x09020000 0x1000>; + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>, + <&mdma1 20 0x2 0x12000a08 0x0 0x0>, + <&mdma1 21 0x2 0x12000a0a 0x0 0x0>; + dma-names = "tx", "rx", "ecc"; + status = "disabled"; + }; }; qspi: spi@58003000 { diff --git a/arch/arm/boot/dts/stm32mp153.dtsi b/arch/arm/boot/dts/stm32mp153.dtsi index 6d9ab08667fc..1c1889b194cf 100644 --- a/arch/arm/boot/dts/stm32mp153.dtsi +++ b/arch/arm/boot/dts/stm32mp153.dtsi @@ -16,6 +16,12 @@ }; }; + arm-pmu { + interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; + soc { m_can1: can@4400e000 { compatible = "bosch,m_can"; diff --git a/arch/arm/boot/dts/stm32mp153c-dhcom-drc02.dts b/arch/arm/boot/dts/stm32mp153c-dhcom-drc02.dts new file mode 100644 index 000000000000..02a39132958e --- /dev/null +++ b/arch/arm/boot/dts/stm32mp153c-dhcom-drc02.dts @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2020 Marek Vasut <marex@denx.de> + * + * DHCOM STM32MP1 variant: + * DHCM-STM32MP153C-C065-R102-F0819-SPI-E2-CAN2-RTC-I-01D2 + * DHCOM PCB number: 587-200 or newer + * DRC02 PCB number: 568-100 or newer + */ +/dts-v1/; + +#include "stm32mp153.dtsi" +#include "stm32mp15xc.dtsi" +#include "stm32mp15xx-dhcom-som.dtsi" +#include "stm32mp15xx-dhcom-drc02.dtsi" + +/ { + model = "DH electronics STM32MP153C DHCOM DRC02"; + compatible = "dh,stm32mp153c-dhcom-drc02", "dh,stm32mp153c-dhcom-som", + "st,stm32mp153"; +}; + +&m_can1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&m_can1_pins_a>; + pinctrl-1 = <&m_can1_sleep_pins_a>; + status = "okay"; +}; + +&m_can2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&m_can2_pins_a>; + pinctrl-1 = <&m_can2_sleep_pins_a>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dts b/arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dts index 197aa98d49e2..d3b81382f97c 100644 --- a/arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dts +++ b/arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dts @@ -4,7 +4,7 @@ * * DHCOM STM32MP1 variant: * DHCM-STM32MP157C-C065-R102-F0819-SPI-E2-CAN2-SDR104-RTC-WBT-T-DSI-I-01D2 - * DHCOR PCB number: 587-200 or newer + * DHCOM PCB number: 587-200 or newer * PDK2 PCB number: 516-400 or newer */ /dts-v1/; @@ -15,7 +15,7 @@ #include "stm32mp15xx-dhcom-pdk2.dtsi" / { - model = "DH Electronics STM32MP157C DHCOM Premium Developer Kit (2)"; + model = "DH electronics STM32MP157C DHCOM Premium Developer Kit (2)"; compatible = "dh,stm32mp157c-dhcom-pdk2", "dh,stm32mp157c-dhcom-som", "st,stm32mp157"; }; diff --git a/arch/arm/boot/dts/stm32mp157c-ed1.dts b/arch/arm/boot/dts/stm32mp157c-ed1.dts index ca109dc18238..2e77ccec3fc1 100644 --- a/arch/arm/boot/dts/stm32mp157c-ed1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ed1.dts @@ -89,6 +89,14 @@ states = <1800000 0x1>, <2900000 0x0>; }; + + vin: vin { + compatible = "regulator-fixed"; + regulator-name = "vin"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; }; &adc { @@ -150,11 +158,18 @@ regulators { compatible = "st,stpmic1-regulators"; + buck1-supply = <&vin>; + buck2-supply = <&vin>; + buck3-supply = <&vin>; + buck4-supply = <&vin>; ldo1-supply = <&v3v3>; ldo2-supply = <&v3v3>; ldo3-supply = <&vdd_ddr>; + ldo4-supply = <&vin>; ldo5-supply = <&v3v3>; ldo6-supply = <&v3v3>; + vref_ddr-supply = <&vin>; + boost-supply = <&vin>; pwr_sw1-supply = <&bst_out>; pwr_sw2-supply = <&bst_out>; diff --git a/arch/arm/boot/dts/stm32mp157c-ev1.dts b/arch/arm/boot/dts/stm32mp157c-ev1.dts index 85628e16d2d5..a55e80ce2602 100644 --- a/arch/arm/boot/dts/stm32mp157c-ev1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ev1.dts @@ -158,14 +158,16 @@ pinctrl-0 = <&fmc_pins_a>; pinctrl-1 = <&fmc_sleep_pins_a>; status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - nand@0 { - reg = <0>; - nand-on-flash-bbt; - #address-cells = <1>; - #size-cells = <1>; + nand-controller@4,0 { + status = "okay"; + + nand@0 { + reg = <0>; + nand-on-flash-bbt; + #address-cells = <1>; + #size-cells = <1>; + }; }; }; diff --git a/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts b/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts index 5700e6b700d3..1e5333fd437f 100644 --- a/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts +++ b/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts @@ -121,8 +121,6 @@ reset-gpios = <&gpiog 0 GPIO_ACTIVE_LOW>; /* ETH_RST# */ interrupt-parent = <&gpioa>; interrupts = <6 IRQ_TYPE_EDGE_FALLING>; /* ETH_MDINT# */ - rxc-skew-ps = <1860>; - txc-skew-ps = <1860>; reset-assert-us = <10000>; reset-deassert-us = <300>; micrel,force-master; @@ -214,6 +212,7 @@ pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_b>; pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_b>; bus-width = <8>; + mmc-ddr-3_3v; no-1-8-v; no-sd; no-sdio; diff --git a/arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi b/arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi new file mode 100644 index 000000000000..6cf49a0a9e69 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi @@ -0,0 +1,276 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2020 Marcin Sloniewski <marcin.sloniewski@gmail.com>. + */ + +/dts-v1/; + +#include "stm32mp157.dtsi" +#include "stm32mp15xc.dtsi" +#include "stm32mp15-pinctrl.dtsi" +#include "stm32mp15xxac-pinctrl.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/mfd/st,stpmic1.h> + +/ { + model = "Seeed Studio Odyssey-STM32MP157C SOM"; + compatible = "seeed,stm32mp157c-odyssey-som", "st,stm32mp157"; + + memory@c0000000 { + device_type = "memory"; + reg = <0xc0000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mcuram2: mcuram2@10000000 { + compatible = "shared-dma-pool"; + reg = <0x10000000 0x40000>; + no-map; + }; + + vdev0vring0: vdev0vring0@10040000 { + compatible = "shared-dma-pool"; + reg = <0x10040000 0x1000>; + no-map; + }; + + vdev0vring1: vdev0vring1@10041000 { + compatible = "shared-dma-pool"; + reg = <0x10041000 0x1000>; + no-map; + }; + + vdev0buffer: vdev0buffer@10042000 { + compatible = "shared-dma-pool"; + reg = <0x10042000 0x4000>; + no-map; + }; + + mcuram: mcuram@30000000 { + compatible = "shared-dma-pool"; + reg = <0x30000000 0x40000>; + no-map; + }; + + retram: retram@38000000 { + compatible = "shared-dma-pool"; + reg = <0x38000000 0x10000>; + no-map; + }; + + gpu_reserved: gpu@d4000000 { + reg = <0xd4000000 0x4000000>; + no-map; + }; + }; + + led { + compatible = "gpio-leds"; + led-blue { + color = <LED_COLOR_ID_BLUE>; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpiog 3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&gpu { + contiguous-area = <&gpu_reserved>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + pmic: stpmic@33 { + compatible = "st,stpmic1"; + reg = <0x33>; + interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + + regulators { + compatible = "st,stpmic1-regulators"; + ldo1-supply = <&v3v3>; + ldo3-supply = <&vdd_ddr>; + ldo6-supply = <&v3v3>; + pwr_sw1-supply = <&bst_out>; + pwr_sw2-supply = <&bst_out>; + + vddcore: buck1 { + regulator-name = "vddcore"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd_ddr: buck2 { + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd: buck3 { + regulator-name = "vdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + st,mask-reset; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + v3v3: buck4 { + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-over-current-protection; + regulator-initial-mode = <0>; + }; + + v1v8_audio: ldo1 { + regulator-name = "v1v8_audio"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + interrupts = <IT_CURLIM_LDO1 0>; + }; + + v3v3_hdmi: ldo2 { + regulator-name = "v3v3_hdmi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + interrupts = <IT_CURLIM_LDO2 0>; + }; + + vtt_ddr: ldo3 { + regulator-name = "vtt_ddr"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <750000>; + regulator-always-on; + regulator-over-current-protection; + }; + + vdd_usb: ldo4 { + regulator-name = "vdd_usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + interrupts = <IT_CURLIM_LDO4 0>; + }; + + vdda: ldo5 { + regulator-name = "vdda"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + interrupts = <IT_CURLIM_LDO5 0>; + regulator-boot-on; + }; + + v1v2_hdmi: ldo6 { + regulator-name = "v1v2_hdmi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + interrupts = <IT_CURLIM_LDO6 0>; + }; + + vref_ddr: vref_ddr { + regulator-name = "vref_ddr"; + regulator-always-on; + regulator-over-current-protection; + }; + + bst_out: boost { + regulator-name = "bst_out"; + interrupts = <IT_OCP_BOOST 0>; + }; + + vbus_otg: pwr_sw1 { + regulator-name = "vbus_otg"; + interrupts = <IT_OCP_OTG 0>; + }; + + vbus_sw: pwr_sw2 { + regulator-name = "vbus_sw"; + interrupts = <IT_OCP_SWOUT 0>; + regulator-active-discharge; + }; + }; + + onkey { + compatible = "st,stpmic1-onkey"; + interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 0>; + interrupt-names = "onkey-falling", "onkey-rising"; + power-off-time-sec = <10>; + }; + + watchdog { + compatible = "st,stpmic1-wdt"; + status = "disabled"; + }; + }; +}; + +&ipcc { + status = "okay"; +}; + +&iwdg2 { + timeout-sec = <32>; + status = "okay"; +}; + +&m4_rproc { + memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, + <&vdev0vring1>, <&vdev0buffer>; + mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; + mbox-names = "vq0", "vq1", "shutdown"; + interrupt-parent = <&exti>; + interrupts = <68 1>; + status = "okay"; +}; + +&rng1 { + status = "okay"; +}; + +&rtc { + status = "okay"; +}; + +&sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_d>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_d>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_d>; + non-removable; + no-sd; + no-sdio; + st,neg-edge; + bus-width = <8>; + vmmc-supply = <&v3v3>; + vqmmc-supply = <&v3v3>; + mmc-ddr-3_3v; + status = "okay"; +}; + diff --git a/arch/arm/boot/dts/stm32mp157c-odyssey.dts b/arch/arm/boot/dts/stm32mp157c-odyssey.dts new file mode 100644 index 000000000000..a7ffec8f1516 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157c-odyssey.dts @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2020 Marcin Sloniewski <marcin.sloniewski@gmail.com>. + */ + +/dts-v1/; + +#include "stm32mp157c-odyssey-som.dtsi" + +/ { + model = "Seeed Studio Odyssey-STM32MP157C Board"; + compatible = "seeed,stm32mp157c-odyssey", + "seeed,stm32mp157c-odyssey-som", "st,stm32mp157"; + + aliases { + ethernet0 = ðernet0; + serial0 = &uart4; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +ðernet0 { + status = "okay"; + pinctrl-0 = <ðernet0_rgmii_pins_a>; + pinctrl-1 = <ðernet0_rgmii_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + phy-mode = "rgmii-id"; + max-speed = <1000>; + phy-handle = <&phy0>; + assigned-clocks = <&rcc ETHCK_K>, <&rcc PLL4_P>; + assigned-clock-parents = <&rcc PLL4_P>; + assigned-clock-rates = <125000000>; /* Clock PLL4 to 750Mhz in ATF/U-Boot */ + st,eth-clk-sel; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy0: ethernet-phy@7 { /* KSZ9031RN */ + reg = <7>; + reset-gpios = <&gpiog 0 GPIO_ACTIVE_LOW>; /* ETH_RST# */ + reset-assert-us = <10000>; + reset-deassert-us = <300>; + }; + }; +}; + +&i2c1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c1_pins_a>; + pinctrl-1 = <&i2c1_sleep_pins_a>; + i2c-scl-rising-time-ns = <100>; + i2c-scl-falling-time-ns = <7>; + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + cd-gpios = <&gpiob 7 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + disable-wp; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&v3v3>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins_a>; + status = "okay"; +}; + diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-drc02.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-drc02.dtsi new file mode 100644 index 000000000000..62ab23824a3e --- /dev/null +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-drc02.dtsi @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2020 Marek Vasut <marex@denx.de> + */ + +#include <dt-bindings/input/input.h> +#include <dt-bindings/pwm/pwm.h> + +/ { + aliases { + serial0 = &uart4; + serial1 = &usart3; + serial2 = &uart8; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&adc { + status = "disabled"; +}; + +&dac { + status = "disabled"; +}; + +&gpiob { + /* + * NOTE: On DRC02, the RS485_RX_En is controlled by a separate + * GPIO line, however the STM32 UART driver assumes RX happens + * during TX anyway and that it only controls drive enable DE + * line. Hence, the RX is always enabled here. + */ + rs485-rx-en { + gpio-hog; + gpios = <8 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "rs485-rx-en"; + }; +}; + +&gpiod { + gpio-line-names = "", "", "", "", + "", "", "", "", + "", "", "", "Out1", + "Out2", "", "", ""; +}; + +&gpioi { + gpio-line-names = "In1", "", "", "", + "", "", "", "", + "In2", "", "", "", + "", "", "", ""; + + /* + * NOTE: The USB Hub on the DRC02 needs a reset signal to be + * pulled high in order to be detected by the USB Controller. + * This signal should be handled by USB power sequencing in + * order to reset the Hub when USB bus is powered down, but + * so far there is no such functionality. + */ + usb-hub { + gpio-hog; + gpios = <2 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "usb-hub-reset"; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c04"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +&i2c5 { /* TP7/TP8 */ + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; +}; + +&sdmmc3 { + /* + * On DRC02, the SoM does not have SDIO WiFi. The pins + * are used for on-board microSD slot instead. + */ + /delete-property/broken-cd; + cd-gpios = <&gpioi 10 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + disable-wp; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins_a>; + cs-gpios = <&gpioz 3 0>; + /* Use PIO for the display */ + /delete-property/dmas; + /delete-property/dma-names; + status = "disabled"; /* Enable once there is display driver */ + /* + * Note: PF3/GPIO_A , PD6/GPIO_B , PG0/GPIO_C , PC6/GPIO_E are + * also connected to the display board connector. + */ +}; + +&usart3 { + pinctrl-names = "default"; + pinctrl-0 = <&usart3_pins_a>; + status = "okay"; +}; + +/* + * Note: PI3 is UART1_RTS and PI5 is UART1_CTS on DRC02 (uart4 of STM32MP1), + * however the STM32MP1 pinmux cannot map them to UART4 . + */ + +&uart8 { /* RS485 */ + linux,rs485-enabled-at-boot-time; + pinctrl-names = "default"; + pinctrl-0 = <&uart8_pins_a>; + rts-gpios = <&gpioe 6 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&usbh_ehci { + phys = <&usbphyc_port0>; + status = "okay"; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; + vdda1v1-supply = <®11>; + vdda1v8-supply = <®18>; +}; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi index 7c4bd615b311..8456f172d4b1 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi @@ -11,7 +11,6 @@ serial0 = &uart4; serial1 = &usart3; serial2 = &uart8; - ethernet0 = ðernet0; }; chosen { @@ -26,23 +25,13 @@ display_bl: display-bl { compatible = "pwm-backlight"; - pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>; + pwms = <&pwm2 3 500000 PWM_POLARITY_INVERTED>; brightness-levels = <0 16 22 30 40 55 75 102 138 188 255>; default-brightness-level = <8>; enable-gpios = <&gpioi 0 GPIO_ACTIVE_HIGH>; status = "okay"; }; - ethernet_vio: vioregulator { - compatible = "regulator-fixed"; - regulator-name = "vio"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpiog 3 GPIO_ACTIVE_LOW>; - regulator-always-on; - regulator-boot-on; - }; - gpio-keys-polled { compatible = "gpio-keys-polled"; #size-cells = <0>; @@ -57,6 +46,16 @@ linux,code = <KEY_A>; gpios = <&gpiof 3 GPIO_ACTIVE_LOW>; }; + + /* + * The EXTi IRQ line 0 is shared with PMIC, + * so mark this as polled GPIO key. + */ + button-2 { + label = "TA3-GPIO-C"; + linux,code = <KEY_C>; + gpios = <&gpiog 0 GPIO_ACTIVE_LOW>; + }; }; gpio-keys { @@ -70,13 +69,6 @@ wakeup-source; }; - button-2 { - label = "TA3-GPIO-C"; - linux,code = <KEY_C>; - gpios = <&gpioi 11 GPIO_ACTIVE_LOW>; - wakeup-source; - }; - button-3 { label = "TA4-GPIO-D"; linux,code = <KEY_D>; @@ -90,7 +82,7 @@ led-0 { label = "green:led5"; - gpios = <&gpiog 2 GPIO_ACTIVE_HIGH>; + gpios = <&gpioc 6 GPIO_ACTIVE_HIGH>; default-state = "off"; }; @@ -141,28 +133,6 @@ status = "okay"; }; -ðernet0 { - status = "okay"; - pinctrl-0 = <ðernet0_rmii_pins_a>; - pinctrl-1 = <ðernet0_rmii_sleep_pins_a>; - pinctrl-names = "default", "sleep"; - phy-mode = "rmii"; - max-speed = <100>; - phy-handle = <&phy0>; - st,eth-ref-clk-sel; - phy-reset-gpios = <&gpioh 15 GPIO_ACTIVE_LOW>; - - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - - phy0: ethernet-phy@1 { - reg = <1>; - }; - }; -}; - &i2c2 { /* Header X22 */ pinctrl-names = "default"; pinctrl-0 = <&i2c2_pins_a>; @@ -304,7 +274,8 @@ &uart8 { pinctrl-names = "default"; - pinctrl-0 = <&uart8_pins_a>; + pinctrl-0 = <&uart8_pins_a &uart8_rtscts_pins_a>; + uart-has-rtscts; status = "okay"; }; @@ -314,9 +285,12 @@ }; &usbotg_hs { - dr_mode = "peripheral"; - phys = <&usbphyc_port1 0>; + dr_mode = "otg"; + pinctrl-0 = <&usbotg_hs_pins_a>; + pinctrl-names = "default"; phy-names = "usb2-phy"; + phys = <&usbphyc_port1 0>; + vbus-supply = <&vbus_otg>; status = "okay"; }; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi index ba905196fb54..f796a6150313 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi @@ -9,6 +9,10 @@ #include <dt-bindings/mfd/st,stpmic1.h> / { + aliases { + ethernet0 = ðernet0; + }; + memory@c0000000 { device_type = "memory"; reg = <0xC0000000 0x40000000>; @@ -55,6 +59,17 @@ no-map; }; }; + + ethernet_vio: vioregulator { + compatible = "regulator-fixed"; + regulator-name = "vio"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpiog 3 GPIO_ACTIVE_LOW>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd>; + }; }; &adc { @@ -94,6 +109,28 @@ status = "okay"; }; +ðernet0 { + status = "okay"; + pinctrl-0 = <ðernet0_rmii_pins_a>; + pinctrl-1 = <ðernet0_rmii_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + phy-mode = "rmii"; + max-speed = <100>; + phy-handle = <&phy0>; + st,eth-ref-clk-sel; + phy-reset-gpios = <&gpioh 3 GPIO_ACTIVE_LOW>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + phy0: ethernet-phy@1 { + reg = <1>; + }; + }; +}; + &i2c4 { pinctrl-names = "default"; pinctrl-0 = <&i2c4_pins_a>; @@ -166,6 +203,7 @@ vdda: ldo1 { regulator-name = "vdda"; + regulator-always-on; regulator-min-microvolt = <2900000>; regulator-max-microvolt = <2900000>; interrupts = <IT_CURLIM_LDO1 0>; @@ -249,7 +287,7 @@ compatible = "ti,tsc2004"; reg = <0x49>; vio-supply = <&v3v3>; - interrupts-extended = <&gpioh 3 IRQ_TYPE_EDGE_FALLING>; + interrupts-extended = <&gpioh 15 IRQ_TYPE_EDGE_FALLING>; }; eeprom@50 { @@ -285,8 +323,8 @@ &qspi { pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>; - pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a &qspi_bk2_sleep_pins_a>; + pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>; + pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>; reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi index 930202742a3f..ec02cee1dd9b 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi @@ -295,9 +295,9 @@ &sdmmc2 { pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_b>; - pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_b>; - pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_b>; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_c>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_c>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_c>; bus-width = <8>; mmc-ddr-1_8v; no-sd; @@ -351,6 +351,7 @@ label = "LS-UART0"; pinctrl-names = "default"; pinctrl-0 = <&uart7_pins_a>; + uart-has-rtscts; status = "okay"; }; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi index 04fbb324a541..803eb8bc9c85 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi @@ -21,6 +21,10 @@ }; }; +&dts { + status = "okay"; +}; + &i2c4 { pinctrl-names = "default"; pinctrl-0 = <&i2c4_pins_a>; diff --git a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi index a5307745719a..93398cfae97e 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi @@ -80,6 +80,14 @@ dais = <&sai2a_port &sai2b_port &i2s2_port>; status = "okay"; }; + + vin: vin { + compatible = "regulator-fixed"; + regulator-name = "vin"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; }; &adc { @@ -240,9 +248,18 @@ regulators { compatible = "st,stpmic1-regulators"; + buck1-supply = <&vin>; + buck2-supply = <&vin>; + buck3-supply = <&vin>; + buck4-supply = <&vin>; ldo1-supply = <&v3v3>; + ldo2-supply = <&vin>; ldo3-supply = <&vdd_ddr>; + ldo4-supply = <&vin>; + ldo5-supply = <&vin>; ldo6-supply = <&v3v3>; + vref_ddr-supply = <&vin>; + boost-supply = <&vin>; pwr_sw1-supply = <&bst_out>; pwr_sw2-supply = <&bst_out>; diff --git a/arch/arm/boot/dts/sun4i-a10-a1000.dts b/arch/arm/boot/dts/sun4i-a10-a1000.dts index 8692b11a83c3..af8ab736fd3c 100644 --- a/arch/arm/boot/dts/sun4i-a10-a1000.dts +++ b/arch/arm/boot/dts/sun4i-a10-a1000.dts @@ -60,6 +60,17 @@ stdout-path = "serial0:115200n8"; }; + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; @@ -133,6 +144,20 @@ status = "okay"; }; +&de { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + &i2c0 { status = "okay"; diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index 0f95a6ef8543..1c5a666c54b5 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -143,7 +143,7 @@ trips { cpu_alert0: cpu-alert0 { /* milliCelsius */ - temperature = <850000>; + temperature = <85000>; hysteresis = <2000>; type = "passive"; }; diff --git a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts index 049e6ab3cf56..73de34ae37fd 100644 --- a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts +++ b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts @@ -154,7 +154,7 @@ pinctrl-names = "default"; pinctrl-0 = <&gmac_rgmii_pins>; phy-handle = <&phy1>; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts b/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts index 32d5d45a35c0..8945dbb114a2 100644 --- a/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts +++ b/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts @@ -130,7 +130,7 @@ pinctrl-names = "default"; pinctrl-0 = <&gmac_rgmii_pins>; phy-handle = <&phy1>; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; phy-supply = <®_gmac_3v3>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts index 8c8dee6ea461..9109ca0919ad 100644 --- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts +++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts @@ -151,7 +151,7 @@ pinctrl-names = "default"; pinctrl-0 = <&gmac_rgmii_pins>; phy-handle = <&phy1>; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun8i-a33-olinuxino.dts b/arch/arm/boot/dts/sun8i-a33-olinuxino.dts index 3d78169cdeed..a1953b2872d0 100644 --- a/arch/arm/boot/dts/sun8i-a33-olinuxino.dts +++ b/arch/arm/boot/dts/sun8i-a33-olinuxino.dts @@ -194,8 +194,8 @@ "Headphone", "Headphone Jack"; /* Board level routing. First 2 routes copied from SoC level */ simple-audio-card,routing = - "Left DAC", "AIF1 Slot 0 Left", - "Right DAC", "AIF1 Slot 0 Right", + "Left DAC", "DACL", + "Right DAC", "DACR", "HP", "HPCOM", "Headphone Jack", "HP", "MIC1", "Microphone Jack", diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi index cfd3858afb3e..c458f5fb124f 100644 --- a/arch/arm/boot/dts/sun8i-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a33.dtsi @@ -189,8 +189,8 @@ simple-audio-card,mclk-fs = <128>; simple-audio-card,aux-devs = <&codec_analog>; simple-audio-card,routing = - "Left DAC", "AIF1 Slot 0 Left", - "Right DAC", "AIF1 Slot 0 Right"; + "Left DAC", "DACL", + "Right DAC", "DACR"; status = "disabled"; simple-audio-card,cpu { diff --git a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts index 9d34eabba121..431f70234d36 100644 --- a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts +++ b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts @@ -131,7 +131,7 @@ pinctrl-0 = <&emac_rgmii_pins>; phy-supply = <®_sw>; phy-handle = <&rgmii_phy>; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; allwinner,rx-delay-ps = <700>; allwinner,tx-delay-ps = <700>; status = "okay"; diff --git a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts index d9be511f054f..d8326a5c681d 100644 --- a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts +++ b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts @@ -183,7 +183,7 @@ pinctrl-0 = <&emac_rgmii_pins>; phy-supply = <®_dldo4>; phy-handle = <&rgmii_phy>; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts index 71fb73208939..babf4cf1b2f6 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts @@ -53,11 +53,6 @@ }; }; -&emac { - /* LEDs changed to active high on the plus */ - /delete-property/ allwinner,leds-active-low; -}; - &mmc1 { vmmc-supply = <®_vcc3v3>; bus-width = <4>; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts index 6dbf7b2e0c13..b6ca45d18e51 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts @@ -67,7 +67,7 @@ pinctrl-0 = <&emac_rgmii_pins>; phy-supply = <®_gmac_3v3>; phy-handle = <&ext_rgmii_phy>; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts index 42d62d1ba1dc..a6a1087a0c9b 100644 --- a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts +++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts @@ -129,7 +129,7 @@ pinctrl-names = "default"; pinctrl-0 = <&gmac_rgmii_pins>; phy-handle = <&phy1>; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; phy-supply = <®_dc1sw>; status = "okay"; }; @@ -164,6 +164,10 @@ #include "axp22x.dtsi" +&ir0 { + status = "okay"; +}; + &mmc0 { vmmc-supply = <®_dcdc1>; bus-width = <4>; @@ -223,16 +227,16 @@ }; ®_dc1sw { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; regulator-name = "vcc-gmac-phy"; }; ®_dcdc1 { regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-3v0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-3v3"; }; ®_dcdc2 { diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi index b782041e0e04..7907569e7b5c 100644 --- a/arch/arm/boot/dts/sun8i-r40.dtsi +++ b/arch/arm/boot/dts/sun8i-r40.dtsi @@ -190,6 +190,29 @@ }; }; + syscon: system-control@1c00000 { + compatible = "allwinner,sun8i-r40-system-control", + "allwinner,sun4i-a10-system-control"; + reg = <0x01c00000 0x30>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sram_c: sram@1d00000 { + compatible = "mmio-sram"; + reg = <0x01d00000 0xd0000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x01d00000 0xd0000>; + + ve_sram: sram-section@0 { + compatible = "allwinner,sun8i-r40-sram-c1", + "allwinner,sun4i-a10-sram-c1"; + reg = <0x000000 0x80000>; + }; + }; + }; + nmi_intc: interrupt-controller@1c00030 { compatible = "allwinner,sun7i-a20-sc-nmi"; interrupt-controller; @@ -198,6 +221,18 @@ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; }; + dma: dma-controller@1c02000 { + compatible = "allwinner,sun8i-r40-dma", + "allwinner,sun50i-a64-dma"; + reg = <0x01c02000 0x1000>; + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_DMA>; + dma-channels = <16>; + dma-requests = <31>; + resets = <&ccu RST_BUS_DMA>; + #dma-cells = <1>; + }; + spi0: spi@1c05000 { compatible = "allwinner,sun8i-r40-spi", "allwinner,sun8i-h3-spi"; @@ -238,6 +273,17 @@ status = "disabled"; }; + video-codec@1c0e000 { + compatible = "allwinner,sun8i-r40-video-engine"; + reg = <0x01c0e000 0x1000>; + clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, + <&ccu CLK_DRAM_VE>; + clock-names = "ahb", "mod", "ram"; + resets = <&ccu RST_BUS_VE>; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; + allwinner,sram = <&ve_sram 1>; + }; + mmc0: mmc@1c0f000 { compatible = "allwinner,sun8i-r40-mmc", "allwinner,sun50i-a64-mmc"; @@ -501,6 +547,16 @@ function = "i2c4"; }; + ir0_pins: ir0-pins { + pins = "PB4"; + function = "ir0"; + }; + + ir1_pins: ir1-pins { + pins = "PB23"; + function = "ir1"; + }; + mmc0_pins: mmc0-pins { pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; @@ -579,6 +635,32 @@ clocks = <&osc24M>; }; + ir0: ir@1c21800 { + compatible = "allwinner,sun8i-r40-ir", + "allwinner,sun6i-a31-ir"; + reg = <0x01c21800 0x400>; + pinctrl-0 = <&ir0_pins>; + pinctrl-names = "default"; + clocks = <&ccu CLK_BUS_IR0>, <&ccu CLK_IR0>; + clock-names = "apb", "ir"; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + resets = <&ccu RST_BUS_IR0>; + status = "disabled"; + }; + + ir1: ir@1c21c00 { + compatible = "allwinner,sun8i-r40-ir", + "allwinner,sun6i-a31-ir"; + reg = <0x01c21c00 0x400>; + pinctrl-0 = <&ir1_pins>; + pinctrl-names = "default"; + clocks = <&ccu CLK_BUS_IR1>, <&ccu CLK_IR1>; + clock-names = "apb", "ir"; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + resets = <&ccu RST_BUS_IR1>; + status = "disabled"; + }; + ths: thermal-sensor@1c24c00 { compatible = "allwinner,sun8i-r40-ths"; reg = <0x01c24c00 0x100>; @@ -743,6 +825,28 @@ #size-cells = <0>; }; + mali: gpu@1c40000 { + compatible = "allwinner,sun8i-r40-mali", "arm,mali-400"; + reg = <0x01c40000 0x10000>; + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "gp", + "gpmmu", + "pp0", + "ppmmu0", + "pp1", + "ppmmu1", + "pmu"; + clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; + clock-names = "bus", "core"; + resets = <&ccu RST_BUS_GPU>; + }; + gmac: ethernet@1c50000 { compatible = "allwinner,sun8i-r40-gmac"; syscon = <&ccu>; diff --git a/arch/arm/boot/dts/sun8i-s3-pinecube.dts b/arch/arm/boot/dts/sun8i-s3-pinecube.dts new file mode 100644 index 000000000000..9bab6b7f4014 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-s3-pinecube.dts @@ -0,0 +1,235 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR X11) +/* + * Copyright 2019 Icenowy Zheng <icenowy@aosc.io> + */ + +/dts-v1/; +#include "sun8i-v3.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> + +/ { + model = "PineCube IP Camera"; + compatible = "pine64,pinecube", "allwinner,sun8i-s3"; + + aliases { + serial0 = &uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led1 { + label = "pine64:ir:led1"; + gpios = <&pio 1 10 GPIO_ACTIVE_LOW>; /* PB10 */ + }; + + led2 { + label = "pine64:ir:led2"; + gpios = <&pio 1 12 GPIO_ACTIVE_LOW>; /* PB12 */ + }; + }; + + reg_vcc5v0: vcc5v0 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_vcc_wifi: vcc-wifi { + compatible = "regulator-fixed"; + regulator-name = "vcc-wifi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pio 1 2 GPIO_ACTIVE_LOW>; /* PB2 WIFI-EN */ + vin-supply = <®_dcdc3>; + startup-delay-us = <200000>; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pio 1 3 GPIO_ACTIVE_LOW>; /* PB3 WIFI-RST */ + post-power-on-delay-ms = <200>; + }; +}; + +&csi1 { + pinctrl-names = "default"; + pinctrl-0 = <&csi1_8bit_pins>; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + csi1_ep: endpoint { + remote-endpoint = <&ov5640_ep>; + bus-width = <8>; + hsync-active = <1>; /* Active high */ + vsync-active = <0>; /* Active low */ + data-active = <1>; /* Active high */ + pclk-sample = <1>; /* Rising */ + }; + }; +}; + +&emac { + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + axp209: pmic@34 { + compatible = "x-powers,axp203", + "x-powers,axp209"; + reg = <0x34>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pe_pins>; + status = "okay"; + + ov5640: camera@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&csi1_mclk_pin>; + clocks = <&ccu CLK_CSI1_MCLK>; + clock-names = "xclk"; + + AVDD-supply = <®_ldo3>; + DOVDD-supply = <®_ldo3>; + DVDD-supply = <®_ldo4>; + reset-gpios = <&pio 4 23 GPIO_ACTIVE_LOW>; /* PE23 */ + powerdown-gpios = <&pio 4 24 GPIO_ACTIVE_HIGH>; /* PE24 */ + + port { + ov5640_ep: endpoint { + remote-endpoint = <&csi1_ep>; + bus-width = <8>; + hsync-active = <1>; /* Active high */ + vsync-active = <0>; /* Active low */ + data-active = <1>; /* Active high */ + pclk-sample = <1>; /* Rising */ + }; + }; + }; +}; + +&lradc { + vref-supply = <®_ldo2>; + status = "okay"; + + button-200 { + label = "Setup"; + linux,code = <KEY_SETUP>; + channel = <0>; + voltage = <190000>; + }; +}; + +&mmc0 { + vmmc-supply = <®_dcdc3>; + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&mmc1 { + vmmc-supply = <®_vcc_wifi>; + vqmmc-supply = <®_dcdc3>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; +}; + +&pio { + vcc-pd-supply = <®_dcdc3>; + vcc-pe-supply = <®_ldo3>; +}; + +#include "axp209.dtsi" + +&ac_power_supply { + status = "okay"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1250000>; + regulator-name = "vdd-sys-cpu-ephy"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-3v3"; +}; + +®_ldo1 { + regulator-name = "vdd-rtc"; +}; + +®_ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_ldo3 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "avdd-dovdd-2v8-csi"; + regulator-soft-start; + regulator-ramp-delay = <1600>; +}; + +®_ldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "dvdd-1v8-csi"; +}; + +&spi0 { + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "winbond,w25q128", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <40000000>; + }; +}; + +&uart2 { + status = "okay"; +}; + +&usb_otg { + dr_mode = "host"; + status = "okay"; +}; + +&usbphy { + usb0_vbus-supply = <®_vcc5v0>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/sun8i-v3.dtsi b/arch/arm/boot/dts/sun8i-v3.dtsi index 6ae8645ade50..ca4672ed2e02 100644 --- a/arch/arm/boot/dts/sun8i-v3.dtsi +++ b/arch/arm/boot/dts/sun8i-v3.dtsi @@ -9,6 +9,19 @@ compatible = "allwinner,sun8i-v3-ccu"; }; +&emac { + /delete-property/ phy-handle; + /delete-property/ phy-mode; +}; + +&mdio_mux { + external_mdio: mdio@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; +}; + &pio { compatible = "allwinner,sun8i-v3-pinctrl"; }; diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi index e5312869c0d2..0c7341676921 100644 --- a/arch/arm/boot/dts/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi @@ -43,12 +43,28 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/sun8i-v3s-ccu.h> #include <dt-bindings/reset/sun8i-v3s-ccu.h> +#include <dt-bindings/clock/sun8i-de2.h> / { #address-cells = <1>; #size-cells = <1>; interrupt-parent = <&gic>; + chosen { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + framebuffer-lcd { + compatible = "allwinner,simple-framebuffer", + "simple-framebuffer"; + allwinner,pipeline = "mixer0-lcd0"; + clocks = <&display_clocks CLK_MIXER0>, + <&ccu CLK_TCON0>; + status = "disabled"; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -138,6 +154,15 @@ }; }; + syscon: system-control@1c00000 { + compatible = "allwinner,sun8i-v3s-system-control", + "allwinner,sun8i-h3-system-control"; + reg = <0x01c00000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + }; + tcon0: lcd-controller@1c0c000 { compatible = "allwinner,sun8i-v3s-tcon"; reg = <0x01c0c000 0x1000>; @@ -234,6 +259,17 @@ #size-cells = <0>; }; + crypto@1c15000 { + compatible = "allwinner,sun8i-v3s-crypto", + "allwinner,sun8i-a33-crypto"; + reg = <0x01c15000 0x1000>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>; + clock-names = "ahb", "mod"; + resets = <&ccu RST_BUS_CE>; + reset-names = "ahb"; + }; + usb_otg: usb@1c19000 { compatible = "allwinner,sun8i-h3-musb"; reg = <0x01c19000 0x0400>; @@ -292,16 +328,41 @@ interrupt-controller; #interrupt-cells = <3>; + /omit-if-no-ref/ + csi1_8bit_pins: csi1-8bit-pins { + pins = "PE0", "PE2", "PE3", "PE8", "PE9", + "PE10", "PE11", "PE12", "PE13", "PE14", + "PE15"; + function = "csi"; + }; + + /omit-if-no-ref/ + csi1_mclk_pin: csi1-mclk-pin { + pins = "PE1"; + function = "csi"; + }; + i2c0_pins: i2c0-pins { pins = "PB6", "PB7"; function = "i2c0"; }; + /omit-if-no-ref/ + i2c1_pe_pins: i2c1-pe-pins { + pins = "PE21", "PE22"; + function = "i2c1"; + }; + uart0_pb_pins: uart0-pb-pins { pins = "PB8", "PB9"; function = "uart0"; }; + uart2_pins: uart2-pins { + pins = "PB0", "PB1"; + function = "uart2"; + }; + mmc0_pins: mmc0-pins { pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; @@ -377,6 +438,8 @@ reg-io-width = <4>; clocks = <&ccu CLK_BUS_UART2>; resets = <&ccu RST_BUS_UART2>; + pinctrl-0 = <&uart2_pins>; + pinctrl-names = "default"; status = "disabled"; }; @@ -404,6 +467,49 @@ #size-cells = <0>; }; + emac: ethernet@1c30000 { + compatible = "allwinner,sun8i-v3s-emac"; + syscon = <&syscon>; + reg = <0x01c30000 0x10000>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + resets = <&ccu RST_BUS_EMAC>; + reset-names = "stmmaceth"; + clocks = <&ccu CLK_BUS_EMAC>; + clock-names = "stmmaceth"; + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + status = "disabled"; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + }; + + mdio_mux: mdio-mux { + compatible = "allwinner,sun8i-h3-mdio-mux"; + #address-cells = <1>; + #size-cells = <0>; + + mdio-parent-bus = <&mdio>; + /* Only one MDIO is usable at the time */ + internal_mdio: mdio@1 { + compatible = "allwinner,sun8i-h3-mdio-internal"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + int_mii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + clocks = <&ccu CLK_BUS_EPHY>; + resets = <&ccu RST_BUS_EPHY>; + }; + }; + }; + }; + spi0: spi@1c68000 { compatible = "allwinner,sun8i-h3-spi"; reg = <0x01c68000 0x1000>; @@ -418,6 +524,18 @@ #size-cells = <0>; }; + csi1: camera@1cb4000 { + compatible = "allwinner,sun8i-v3s-csi"; + reg = <0x01cb4000 0x3000>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_CSI>, + <&ccu CLK_CSI1_SCLK>, + <&ccu CLK_DRAM_CSI>; + clock-names = "bus", "mod", "ram"; + resets = <&ccu RST_BUS_CSI>; + status = "disabled"; + }; + gic: interrupt-controller@1c81000 { compatible = "arm,gic-400"; reg = <0x01c81000 0x1000>, diff --git a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts index d3b337b043a1..484b93df20cb 100644 --- a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts +++ b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts @@ -129,7 +129,7 @@ pinctrl-names = "default"; pinctrl-0 = <&gmac_rgmii_pins>; phy-handle = <&phy1>; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; phy-supply = <®_cldo1>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun9i-a80-optimus.dts b/arch/arm/boot/dts/sun9i-a80-optimus.dts index bbc6335e5631..5c3580d712e4 100644 --- a/arch/arm/boot/dts/sun9i-a80-optimus.dts +++ b/arch/arm/boot/dts/sun9i-a80-optimus.dts @@ -124,7 +124,7 @@ pinctrl-names = "default"; pinctrl-0 = <&gmac_rgmii_pins>; phy-handle = <&phy1>; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; phy-supply = <®_cldo1>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi b/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi index 39263e74fbb5..8e5cb3b3fd68 100644 --- a/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi +++ b/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi @@ -126,7 +126,7 @@ pinctrl-0 = <&emac_rgmii_pins>; phy-supply = <®_gmac_3v3>; phy-handle = <&ext_rgmii_phy>; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; status = "okay"; }; diff --git a/arch/arm/boot/dts/tango4-common.dtsi b/arch/arm/boot/dts/tango4-common.dtsi index 54fd522badfc..d584da314500 100644 --- a/arch/arm/boot/dts/tango4-common.dtsi +++ b/arch/arm/boot/dts/tango4-common.dtsi @@ -51,7 +51,7 @@ }; }; - l2cc: l2-cache-controller@20100000 { + l2cc: cache-controller@20100000 { compatible = "arm,pl310-cache"; reg = <0x20100000 0x1000>; cache-level = <2>; diff --git a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts index 2d683c9a1a5d..a0b829738e8f 100644 --- a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts +++ b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts @@ -14,6 +14,10 @@ compatible = "acer,picasso", "nvidia,tegra20"; aliases { + mmc0 = &sdmmc4; /* eMMC */ + mmc1 = &sdmmc3; /* MicroSD */ + mmc2 = &sdmmc1; /* WiFi */ + rtc0 = &pmic; rtc1 = "/rtc@7000e000"; @@ -314,16 +318,24 @@ nvidia,pins = "drive_ddc", "drive_vi1", "drive_sdio1"; + nvidia,pull-up-strength = <31>; + nvidia,pull-down-strength = <31>; nvidia,schmitt = <TEGRA_PIN_ENABLE>; - nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_4>; + nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; + nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>; }; drive_dbg { nvidia,pins = "drive_dbg", "drive_vi2", "drive_at1", "drive_ao1"; + nvidia,pull-up-strength = <31>; + nvidia,pull-down-strength = <31>; nvidia,schmitt = <TEGRA_PIN_ENABLE>; - nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_4>; + nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; + nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; }; @@ -431,8 +443,6 @@ compatible = "atmel,maxtouch"; reg = <0x4c>; - atmel,cfg_name = "maxtouch-acer-iconia-tab-a500.cfg"; - interrupt-parent = <&gpio>; interrupts = <TEGRA_GPIO(V, 6) IRQ_TYPE_LEVEL_LOW>; @@ -720,13 +730,17 @@ power-off-delay-us = <300>; }; - mmc@c8000000 { + sdmmc1: mmc@c8000000 { status = "okay"; #address-cells = <1>; #size-cells = <0>; - max-frequency = <25000000>; + assigned-clocks = <&tegra_car TEGRA20_CLK_SDMMC1>; + assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_C>; + assigned-clock-rates = <50000000>; + + max-frequency = <50000000>; keep-power-in-suspend; bus-width = <4>; non-removable; @@ -745,7 +759,7 @@ }; }; - mmc@c8000400 { + sdmmc3: mmc@c8000400 { status = "okay"; bus-width = <4>; cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; @@ -754,7 +768,7 @@ vqmmc-supply = <&vdd_3v3_sys>; }; - mmc@c8000600 { + sdmmc4: mmc@c8000600 { status = "okay"; bus-width = <8>; vmmc-supply = <&vcore_emmc>; diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi index 3922517145e7..88ca03f57b3b 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi @@ -2,6 +2,7 @@ #include <dt-bindings/input/gpio-keys.h> #include <dt-bindings/input/input.h> +#include <dt-bindings/power/summit,smb347-charger.h> #include <dt-bindings/thermal/thermal.h> #include "tegra30.dtsi" @@ -10,6 +11,9 @@ / { aliases { + mmc0 = &sdmmc4; /* eMMC */ + mmc1 = &sdmmc3; /* WiFi */ + rtc0 = &pmic; rtc1 = "/rtc@7000e000"; @@ -836,6 +840,24 @@ i2c@7000c400 { clock-frequency = <400000>; status = "okay"; + + touchscreen@10 { + compatible ="elan,ektf3624"; + reg = <0x10>; + + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(H, 4) IRQ_TYPE_LEVEL_LOW>; + + reset-gpios = <&gpio TEGRA_GPIO(H, 6) GPIO_ACTIVE_LOW>; + + vcc33-supply = <&vcc_3v3_ts>; + vccio-supply = <&vcc_3v3_ts>; + + touchscreen-size-x = <2112>; + touchscreen-size-y = <1280>; + touchscreen-swapped-x-y; + touchscreen-inverted-x; + }; }; i2c@7000c500 { @@ -901,9 +923,24 @@ #thermal-sensor-cells = <1>; }; - battery@55 { + fuel-gauge@55 { compatible = "ti,bq27541"; reg = <0x55>; + power-supplies = <&power_supply>; + monitored-battery = <&battery_cell>; + }; + + power_supply: charger@6a { + compatible = "summit,smb347"; + reg = <0x6a>; + + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(V, 1) IRQ_TYPE_EDGE_BOTH>; + + summit,enable-charge-control = <SMB3XX_CHG_ENABLE_PIN_ACTIVE_LOW>; + summit,enable-usb-charging; + + monitored-battery = <&battery_cell>; }; }; @@ -936,12 +973,17 @@ power-off-delay-us = <300>; }; - mmc@78000400 { + sdmmc3: mmc@78000400 { status = "okay"; #address-cells = <1>; #size-cells = <0>; + assigned-clocks = <&tegra_car TEGRA30_CLK_SDMMC3>; + assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_C>; + assigned-clock-rates = <50000000>; + + max-frequency = <50000000>; keep-power-in-suspend; bus-width = <4>; non-removable; @@ -960,7 +1002,7 @@ }; }; - mmc@78000600 { + sdmmc4: mmc@78000600 { status = "okay"; bus-width = <8>; vmmc-supply = <&vcore_emmc>; @@ -993,6 +1035,12 @@ default-brightness-level = <15>; }; + battery_cell: battery-cell { + compatible = "simple-battery"; + constant-charge-current-max-microamp = <1800000>; + operating-range-celsius = <0 45>; + }; + /* PMIC has a built-in 32KHz oscillator which is used by PMC */ clk32k_in: clock@0 { compatible = "fixed-clock"; diff --git a/arch/arm/boot/dts/tny_a9260_common.dtsi b/arch/arm/boot/dts/tny_a9260_common.dtsi index dd6957b20772..70e5635c78ed 100644 --- a/arch/arm/boot/dts/tny_a9260_common.dtsi +++ b/arch/arm/boot/dts/tny_a9260_common.dtsi @@ -10,7 +10,7 @@ bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock6 rw rootfstype=ubifs"; }; - memory { + memory@20000000 { reg = <0x20000000 0x4000000>; }; diff --git a/arch/arm/boot/dts/tny_a9263.dts b/arch/arm/boot/dts/tny_a9263.dts index 2820635952e3..62b7d9f9a926 100644 --- a/arch/arm/boot/dts/tny_a9263.dts +++ b/arch/arm/boot/dts/tny_a9263.dts @@ -15,7 +15,7 @@ bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs"; }; - memory { + memory@20000000 { reg = <0x20000000 0x4000000>; }; diff --git a/arch/arm/boot/dts/usb_a9260.dts b/arch/arm/boot/dts/usb_a9260.dts index ec8cd86b260d..6cfa83921ac2 100644 --- a/arch/arm/boot/dts/usb_a9260.dts +++ b/arch/arm/boot/dts/usb_a9260.dts @@ -16,7 +16,7 @@ bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs"; }; - memory { + memory@20000000 { reg = <0x20000000 0x4000000>; }; diff --git a/arch/arm/boot/dts/usb_a9263.dts b/arch/arm/boot/dts/usb_a9263.dts index e7a705fddda9..8a0cfbfd0c45 100644 --- a/arch/arm/boot/dts/usb_a9263.dts +++ b/arch/arm/boot/dts/usb_a9263.dts @@ -15,7 +15,7 @@ bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs"; }; - memory { + memory@20000000 { reg = <0x20000000 0x4000000>; }; diff --git a/arch/arm/boot/dts/usb_a9g20_common.dtsi b/arch/arm/boot/dts/usb_a9g20_common.dtsi index adbe75024739..7d10b36db1ee 100644 --- a/arch/arm/boot/dts/usb_a9g20_common.dtsi +++ b/arch/arm/boot/dts/usb_a9g20_common.dtsi @@ -14,7 +14,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@20000000 { reg = <0x20000000 0x4000000>; }; diff --git a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi index a88ee5294d35..4f7220b11f2d 100644 --- a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi +++ b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi @@ -280,7 +280,7 @@ reg = <0x0f0000 0x1000>; interrupts = <0>; clocks = <&v2m_refclk32khz>, <&smbclk>; - clock-names = "wdogclk", "apb_pclk"; + clock-names = "wdog_clk", "apb_pclk"; }; v2m_timer01: timer@110000 { diff --git a/arch/arm/boot/dts/vexpress-v2m.dtsi b/arch/arm/boot/dts/vexpress-v2m.dtsi index 5e48b641068a..2ac41ed3a57c 100644 --- a/arch/arm/boot/dts/vexpress-v2m.dtsi +++ b/arch/arm/boot/dts/vexpress-v2m.dtsi @@ -198,7 +198,7 @@ reg = <0x0f000 0x1000>; interrupts = <0>; clocks = <&v2m_refclk32khz>, <&smbclk>; - clock-names = "wdogclk", "apb_pclk"; + clock-names = "wdog_clk", "apb_pclk"; }; v2m_timer01: timer@11000 { diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts index f82fa34c90be..e63c5c0bfb43 100644 --- a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts +++ b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts @@ -87,8 +87,8 @@ status = "disabled"; reg = <0 0x2b060000 0 0x1000>; interrupts = <0 98 4>; - clocks = <&sys_pll>; - clock-names = "apb_pclk"; + clocks = <&sys_pll>, <&sys_pll>; + clock-names = "wdog_clk", "apb_pclk"; }; gic: interrupt-controller@2c001000 { diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts index 3ac95a179452..012d40a7228c 100644 --- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts +++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts @@ -128,7 +128,7 @@ reg = <0 0x2a490000 0 0x1000>; interrupts = <0 98 4>; clocks = <&oscclk6a>, <&oscclk6a>; - clock-names = "wdogclk", "apb_pclk"; + clock-names = "wdog_clk", "apb_pclk"; }; hdlcd@2b000000 { diff --git a/arch/arm/boot/dts/vexpress-v2p-ca9.dts b/arch/arm/boot/dts/vexpress-v2p-ca9.dts index 623246f37448..4c5847955856 100644 --- a/arch/arm/boot/dts/vexpress-v2p-ca9.dts +++ b/arch/arm/boot/dts/vexpress-v2p-ca9.dts @@ -122,8 +122,8 @@ reg = <0x100e4000 0x1000>; interrupts = <0 48 4>, <0 49 4>; - clocks = <&oscclk2>, <&oscclk2>; - clock-names = "timclk", "apb_pclk"; + clocks = <&oscclk2>, <&oscclk2>, <&oscclk2>; + clock-names = "timer0clk", "timer1clk", "apb_pclk"; status = "disabled"; }; @@ -132,7 +132,7 @@ reg = <0x100e5000 0x1000>; interrupts = <0 51 4>; clocks = <&oscclk2>, <&oscclk2>; - clock-names = "wdogclk", "apb_pclk"; + clock-names = "wdog_clk", "apb_pclk"; }; scu@1e000000 { diff --git a/arch/arm/boot/dts/vf610-zii-cfu1.dts b/arch/arm/boot/dts/vf610-zii-cfu1.dts index 64e0e9509226..96495d965163 100644 --- a/arch/arm/boot/dts/vf610-zii-cfu1.dts +++ b/arch/arm/boot/dts/vf610-zii-cfu1.dts @@ -172,7 +172,6 @@ interrupts = <2 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; #interrupt-cells = <2>; - reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; ports { #address-cells = <1>; @@ -226,6 +225,7 @@ compatible = "nxp,pca9554"; reg = <0x22>; gpio-controller; + #gpio-cells = <2>; }; lm75@48 { @@ -356,7 +356,6 @@ pinctrl_switch: switch-grp { fsl,pins = < VF610_PAD_PTB28__GPIO_98 0x3061 - VF610_PAD_PTE2__GPIO_107 0x1042 >; }; diff --git a/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts b/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts index e500911ce0a5..6f1e0f0d4f0a 100644 --- a/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts +++ b/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts @@ -406,6 +406,9 @@ }; }; +&mdio1 { + clock-frequency = <5000000>; +}; &iomuxc { pinctrl_gpio_e6185_eeprom_sel: pinctrl-gpio-e6185-eeprom-spi0 { diff --git a/arch/arm/boot/dts/vf610-zii-spb4.dts b/arch/arm/boot/dts/vf610-zii-spb4.dts index 9e5187ba3fa6..6c6ec46fd015 100644 --- a/arch/arm/boot/dts/vf610-zii-spb4.dts +++ b/arch/arm/boot/dts/vf610-zii-spb4.dts @@ -129,7 +129,6 @@ pinctrl-names = "default"; reg = <0>; eeprom-length = <65536>; - reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; interrupt-parent = <&gpio3>; interrupts = <2 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; @@ -326,7 +325,6 @@ pinctrl_gpio_switch0: pinctrl-gpio-switch0 { fsl,pins = < - VF610_PAD_PTE2__GPIO_107 0x31c2 VF610_PAD_PTB28__GPIO_98 0x219d >; }; diff --git a/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts b/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts index 569614b08f04..73fdace4cb42 100644 --- a/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts +++ b/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts @@ -118,7 +118,6 @@ pinctrl-names = "default"; reg = <0>; eeprom-length = <65536>; - reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; interrupt-parent = <&gpio3>; interrupts = <2 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; @@ -293,7 +292,6 @@ pinctrl_gpio_switch0: pinctrl-gpio-switch0 { fsl,pins = < - VF610_PAD_PTE2__GPIO_107 0x31c2 VF610_PAD_PTB28__GPIO_98 0x219d >; }; diff --git a/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts b/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts index b6b0f302b7b4..fe600ab2e4bd 100644 --- a/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts +++ b/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts @@ -143,7 +143,6 @@ pinctrl-names = "default"; reg = <0>; eeprom-length = <65536>; - reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; interrupt-parent = <&gpio3>; interrupts = <2 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; @@ -333,7 +332,6 @@ pinctrl_gpio_switch0: pinctrl-gpio-switch0 { fsl,pins = < - VF610_PAD_PTE2__GPIO_107 0x31c2 VF610_PAD_PTB28__GPIO_98 0x219d >; }; diff --git a/arch/arm/boot/dts/zx296702.dtsi b/arch/arm/boot/dts/zx296702.dtsi index afd98de029be..f378c661b3bf 100644 --- a/arch/arm/boot/dts/zx296702.dtsi +++ b/arch/arm/boot/dts/zx296702.dtsi @@ -58,7 +58,7 @@ clocks = <&topclk ZX296702_A9_PERIPHCLK>; }; - l2cc: l2-cache-controller@c00000 { + l2cc: cache-controller@c00000 { compatible = "arm,pl310-cache"; reg = <0x00c00000 0x1000>; cache-unified; diff --git a/arch/arm/common/sa1111.c b/arch/arm/common/sa1111.c index c98ebae1aeac..f89c1ea327a2 100644 --- a/arch/arm/common/sa1111.c +++ b/arch/arm/common/sa1111.c @@ -22,7 +22,7 @@ #include <linux/platform_device.h> #include <linux/slab.h> #include <linux/spinlock.h> -#include <linux/dma-mapping.h> +#include <linux/dma-map-ops.h> #include <linux/clk.h> #include <linux/io.h> diff --git a/arch/arm/configs/aspeed_g4_defconfig b/arch/arm/configs/aspeed_g4_defconfig index 303f75a3baec..58d293b63581 100644 --- a/arch/arm/configs/aspeed_g4_defconfig +++ b/arch/arm/configs/aspeed_g4_defconfig @@ -160,7 +160,8 @@ CONFIG_SENSORS_TMP421=y CONFIG_SENSORS_W83773G=y CONFIG_WATCHDOG_SYSFS=y CONFIG_MEDIA_SUPPORT=y -CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_SUPPORT_FILTER=y +CONFIG_MEDIA_PLATFORM_SUPPORT=y CONFIG_V4L_PLATFORM_DRIVERS=y CONFIG_VIDEO_ASPEED=y CONFIG_DRM=y diff --git a/arch/arm/configs/aspeed_g5_defconfig b/arch/arm/configs/aspeed_g5_defconfig index b0d056d49abe..047975eccefb 100644 --- a/arch/arm/configs/aspeed_g5_defconfig +++ b/arch/arm/configs/aspeed_g5_defconfig @@ -128,6 +128,8 @@ CONFIG_INPUT_EVDEV=y CONFIG_KEYBOARD_GPIO=y CONFIG_KEYBOARD_GPIO_POLLED=y # CONFIG_INPUT_MOUSE is not set +CONFIG_INPUT_MISC=y +CONFIG_INPUT_IBM_PANEL=y # CONFIG_SERIO is not set # CONFIG_VT is not set # CONFIG_LEGACY_PTYS is not set @@ -147,10 +149,12 @@ CONFIG_HW_RANDOM_TIMERIOMEM=y # CONFIG_I2C_COMPAT is not set CONFIG_I2C_CHARDEV=y CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_GPIO=y CONFIG_I2C_MUX_PCA9541=y CONFIG_I2C_MUX_PCA954x=y CONFIG_I2C_ASPEED=y CONFIG_I2C_FSI=y +CONFIG_I2C_SLAVE=y CONFIG_SPI=y CONFIG_GPIOLIB=y CONFIG_GPIO_SYSFS=y @@ -175,7 +179,8 @@ CONFIG_SENSORS_TMP421=y CONFIG_SENSORS_W83773G=y CONFIG_WATCHDOG_SYSFS=y CONFIG_MEDIA_SUPPORT=y -CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_SUPPORT_FILTER=y +CONFIG_MEDIA_PLATFORM_SUPPORT=y CONFIG_V4L_PLATFORM_DRIVERS=y CONFIG_VIDEO_ASPEED=y CONFIG_DRM=y diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig index 6e8b5ff0859c..cf82c9d23a08 100644 --- a/arch/arm/configs/exynos_defconfig +++ b/arch/arm/configs/exynos_defconfig @@ -191,11 +191,14 @@ CONFIG_REGULATOR_S2MPS11=y CONFIG_REGULATOR_S5M8767=y CONFIG_REGULATOR_TPS65090=y CONFIG_REGULATOR_WM8994=y +CONFIG_MEDIA_CEC_SUPPORT=y +CONFIG_CEC_SAMSUNG_S5P=m CONFIG_MEDIA_SUPPORT=m +# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set CONFIG_MEDIA_CAMERA_SUPPORT=y -CONFIG_MEDIA_CEC_SUPPORT=y CONFIG_MEDIA_CONTROLLER=y CONFIG_VIDEO_V4L2_SUBDEV_API=y +CONFIG_MEDIA_PLATFORM_SUPPORT=y CONFIG_MEDIA_USB_SUPPORT=y CONFIG_USB_VIDEO_CLASS=m CONFIG_V4L_PLATFORM_DRIVERS=y @@ -210,9 +213,6 @@ CONFIG_VIDEO_SAMSUNG_S5P_MFC=m CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC=m CONFIG_V4L_TEST_DRIVERS=y CONFIG_VIDEO_VIVID=m -CONFIG_CEC_PLATFORM_DRIVERS=y -CONFIG_CEC_SAMSUNG_S5P=m -# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set CONFIG_VIDEO_S5K6A3=m CONFIG_VIDEO_S5C73M3=m CONFIG_DRM=y diff --git a/arch/arm/configs/imx_v4_v5_defconfig b/arch/arm/configs/imx_v4_v5_defconfig index f5f1111f2118..bb70acc6b526 100644 --- a/arch/arm/configs/imx_v4_v5_defconfig +++ b/arch/arm/configs/imx_v4_v5_defconfig @@ -20,9 +20,9 @@ CONFIG_MACH_MX27ADS=y CONFIG_MACH_MX27_3DS=y CONFIG_MACH_IMX27_VISSTRIM_M10=y CONFIG_MACH_PCA100=y -CONFIG_MACH_IMX27_DT=y CONFIG_SOC_IMX1=y CONFIG_SOC_IMX25=y +CONFIG_SOC_IMX27=y CONFIG_AEABI=y CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 @@ -93,6 +93,7 @@ CONFIG_SPI=y CONFIG_SPI_IMX=y CONFIG_SPI_SPIDEV=y CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_MXC=y CONFIG_W1=y CONFIG_W1_MASTER_MXC=y CONFIG_W1_SLAVE_THERM=y diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig index 82d3ffb18e70..221f5c340c86 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig @@ -15,20 +15,8 @@ CONFIG_PERF_EVENTS=y # CONFIG_COMPAT_BRK is not set CONFIG_ARCH_MULTI_V6=y CONFIG_ARCH_MXC=y -CONFIG_MACH_MX31LILLY=y -CONFIG_MACH_MX31LITE=y -CONFIG_MACH_PCM037=y -CONFIG_MACH_PCM037_EET=y -CONFIG_MACH_MX31_3DS=y -CONFIG_MACH_MX31MOBOARD=y -CONFIG_MACH_QONG=y -CONFIG_MACH_ARMADILLO5X0=y -CONFIG_MACH_KZM_ARM11_01=y -CONFIG_MACH_IMX31_DT=y -CONFIG_MACH_IMX35_DT=y -CONFIG_MACH_PCM043=y -CONFIG_MACH_MX35_3DS=y -CONFIG_MACH_VPR200=y +CONFIG_SOC_IMX31=y +CONFIG_SOC_IMX35=y CONFIG_SOC_IMX50=y CONFIG_SOC_IMX51=y CONFIG_SOC_IMX53=y @@ -218,6 +206,9 @@ CONFIG_SPI_GPIO=y CONFIG_SPI_IMX=y CONFIG_SPI_FSL_DSPI=y CONFIG_PINCTRL_IMX8MM=y +CONFIG_PINCTRL_IMX8MN=y +CONFIG_PINCTRL_IMX8MP=y +CONFIG_PINCTRL_IMX8MQ=y CONFIG_GPIO_SYSFS=y CONFIG_GPIO_SIOX=m CONFIG_GPIO_MAX732X=y @@ -226,6 +217,7 @@ CONFIG_GPIO_PCA953X=y CONFIG_GPIO_PCF857X=y CONFIG_GPIO_STMPE=y CONFIG_GPIO_74X164=y +CONFIG_GPIO_MXC=y CONFIG_POWER_RESET=y CONFIG_POWER_RESET_SYSCON=y CONFIG_POWER_RESET_SYSCON_POWEROFF=y @@ -407,6 +399,9 @@ CONFIG_STAGING_MEDIA=y CONFIG_VIDEO_IMX_MEDIA=y CONFIG_COMMON_CLK_PWM=y CONFIG_CLK_IMX8MM=y +CONFIG_CLK_IMX8MN=y +CONFIG_CLK_IMX8MP=y +CONFIG_CLK_IMX8MQ=y CONFIG_SOC_IMX8M=y CONFIG_IIO=y CONFIG_MMA8452=y diff --git a/arch/arm/configs/multi_v5_defconfig b/arch/arm/configs/multi_v5_defconfig index 2724fb3155cd..e00be9faa23b 100644 --- a/arch/arm/configs/multi_v5_defconfig +++ b/arch/arm/configs/multi_v5_defconfig @@ -29,8 +29,8 @@ CONFIG_MACH_MX27ADS=y CONFIG_MACH_MX27_3DS=y CONFIG_MACH_IMX27_VISSTRIM_M10=y CONFIG_MACH_PCA100=y -CONFIG_MACH_IMX27_DT=y CONFIG_SOC_IMX25=y +CONFIG_SOC_IMX27=y CONFIG_ARCH_MVEBU=y CONFIG_MACH_KIRKWOOD=y CONFIG_ARCH_ORION5X=y @@ -166,6 +166,7 @@ CONFIG_SPI_IMX=y CONFIG_SPI_ORION=y CONFIG_GPIO_ASPEED=m CONFIG_GPIO_ASPEED_SGPIO=y +CONFIG_GPIO_MXC=y CONFIG_POWER_RESET=y CONFIG_POWER_RESET_GPIO=y CONFIG_POWER_RESET_QNAP=y diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index e9e76e32f10f..a611b0c1e540 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -43,10 +43,12 @@ CONFIG_SOC_IMX51=y CONFIG_SOC_IMX53=y CONFIG_SOC_IMX6Q=y CONFIG_SOC_IMX6SL=y +CONFIG_SOC_IMX6SLL=y CONFIG_SOC_IMX6SX=y CONFIG_SOC_IMX6UL=y CONFIG_SOC_LS1021A=y CONFIG_SOC_IMX7D=y +CONFIG_SOC_IMX7ULP=y CONFIG_SOC_VF610=y CONFIG_ARCH_KEYSTONE=y CONFIG_ARCH_MEDIATEK=y @@ -182,7 +184,7 @@ CONFIG_PCIEPORTBUS=y CONFIG_PCI_MVEBU=y CONFIG_PCI_TEGRA=y CONFIG_PCI_RCAR_GEN2=y -CONFIG_PCIE_RCAR=y +CONFIG_PCIE_RCAR_HOST=y CONFIG_PCI_DRA7XX_EP=y CONFIG_PCI_ENDPOINT=y CONFIG_PCI_ENDPOINT_CONFIGFS=y @@ -463,6 +465,7 @@ CONFIG_GPIO_PALMAS=y CONFIG_GPIO_TPS6586X=y CONFIG_GPIO_TPS65910=y CONFIG_GPIO_TWL4030=y +CONFIG_GPIO_MXC=y CONFIG_POWER_AVS=y CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_POWER_RESET_AS3722=y @@ -1011,6 +1014,7 @@ CONFIG_EXTCON_MAX14577=m CONFIG_EXTCON_MAX77693=m CONFIG_EXTCON_MAX8997=m CONFIG_TI_AEMIF=y +CONFIG_STM32_FMC2_EBI=y CONFIG_EXYNOS5422_DMC=m CONFIG_IIO=y CONFIG_IIO_SW_TRIGGER=y @@ -1121,6 +1125,7 @@ CONFIG_CRYPTO_USER_API_SKCIPHER=m CONFIG_CRYPTO_USER_API_RNG=m CONFIG_CRYPTO_USER_API_AEAD=m CONFIG_CRYPTO_DEV_SUN4I_SS=m +CONFIG_CRYPTO_DEV_FSL_CAAM=m CONFIG_CRYPTO_DEV_MARVELL_CESA=m CONFIG_CRYPTO_DEV_EXYNOS_RNG=m CONFIG_CRYPTO_DEV_S5P=m diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig index fe383f5a92fb..34793aabdb65 100644 --- a/arch/arm/configs/omap2plus_defconfig +++ b/arch/arm/configs/omap2plus_defconfig @@ -95,7 +95,18 @@ CONFIG_IP_PNP_DHCP=y CONFIG_IP_PNP_BOOTP=y CONFIG_IP_PNP_RARP=y CONFIG_NETFILTER=y +CONFIG_BRIDGE=m +CONFIG_BRIDGE_VLAN_FILTERING=y +CONFIG_VLAN_8021Q=m CONFIG_PHONET=m +CONFIG_NET_SCHED=y +CONFIG_NET_SCH_INGRESS=m +CONFIG_NET_CLS_U32=m +CONFIG_NET_CLS_FLOWER=m +CONFIG_NET_CLS_MATCHALL=m +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_POLICE=m +CONFIG_NET_ACT_GACT=m CONFIG_NET_SWITCHDEV=y CONFIG_CAN=m CONFIG_CAN_C_CAN=m @@ -510,6 +521,7 @@ CONFIG_IIO_ST_ACCEL_3AXIS=m CONFIG_CPCAP_ADC=m CONFIG_INA2XX_ADC=m CONFIG_TI_AM335X_ADC=m +CONFIG_TWL4030_MADC=m CONFIG_SENSORS_ISL29028=m CONFIG_BMP280=m CONFIG_PWM=y diff --git a/arch/arm/configs/realview_defconfig b/arch/arm/configs/realview_defconfig index 70e2c74a9f32..483c400dd391 100644 --- a/arch/arm/configs/realview_defconfig +++ b/arch/arm/configs/realview_defconfig @@ -5,9 +5,6 @@ CONFIG_HIGH_RES_TIMERS=y CONFIG_LOG_BUF_SHIFT=14 CONFIG_PERF_EVENTS=y CONFIG_SLAB=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_BLK_DEV_BSG is not set CONFIG_ARCH_MULTI_V6=y CONFIG_ARCH_REALVIEW=y CONFIG_MACH_REALVIEW_EB=y @@ -20,11 +17,12 @@ CONFIG_MACH_REALVIEW_PB1176=y CONFIG_MACH_REALVIEW_PBA8=y CONFIG_MACH_REALVIEW_PBX=y CONFIG_SMP=y -CONFIG_CMA=y -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_CMDLINE="root=/dev/nfs nfsroot=10.1.69.3:/work/nfsroot ip=dhcp console=ttyAMA0 mem=128M" CONFIG_VFP=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_CMA=y CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y @@ -59,8 +57,12 @@ CONFIG_I2C_VERSATILE=y CONFIG_SPI=y CONFIG_GPIOLIB=y # CONFIG_HWMON is not set +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_DRM=y CONFIG_DRM_PANEL_SIMPLE=y +CONFIG_DRM_DISPLAY_CONNECTOR=y +CONFIG_DRM_SIMPLE_BRIDGE=y CONFIG_DRM_PL111=y CONFIG_FB_MODE_HELPERS=y CONFIG_BACKLIGHT_CLASS_DEVICE=y @@ -78,6 +80,7 @@ CONFIG_MMC=y CONFIG_MMC_ARMMMCI=y CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y +CONFIG_LEDS_SYSCON=y CONFIG_LEDS_TRIGGERS=y CONFIG_LEDS_TRIGGER_HEARTBEAT=y CONFIG_LEDS_TRIGGER_CPU=y @@ -93,10 +96,9 @@ CONFIG_NFS_FS=y CONFIG_ROOT_NFS=y CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ISO8859_1=y -CONFIG_DEBUG_FS=y CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_FS=y CONFIG_DEBUG_KERNEL=y # CONFIG_SCHED_DEBUG is not set # CONFIG_FTRACE is not set CONFIG_DEBUG_USER=y -# CONFIG_CRYPTO_HW is not set diff --git a/arch/arm/configs/shmobile_defconfig b/arch/arm/configs/shmobile_defconfig index bbedc42bb2d9..4a161b3c35b9 100644 --- a/arch/arm/configs/shmobile_defconfig +++ b/arch/arm/configs/shmobile_defconfig @@ -37,7 +37,7 @@ CONFIG_CAN_RCAR=y CONFIG_PCI=y CONFIG_PCI_MSI=y CONFIG_PCI_RCAR_GEN2=y -CONFIG_PCIE_RCAR=y +CONFIG_PCIE_RCAR_HOST=y CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y CONFIG_SIMPLE_PM_BUS=y @@ -64,6 +64,7 @@ CONFIG_KEYBOARD_GPIO=y CONFIG_INPUT_TOUCHSCREEN=y CONFIG_TOUCHSCREEN_EDT_FT5X06=y CONFIG_TOUCHSCREEN_ST1232=y +CONFIG_TOUCHSCREEN_STMPE=y CONFIG_INPUT_MISC=y CONFIG_INPUT_DA9063_ONKEY=y CONFIG_INPUT_ADXL34X=y @@ -104,6 +105,7 @@ CONFIG_RENESAS_WDT=y CONFIG_RENESAS_RZAWDT=y CONFIG_MFD_AS3711=y CONFIG_MFD_DA9063=y +CONFIG_MFD_STMPE=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_AS3711=y CONFIG_REGULATOR_DA9210=y @@ -134,7 +136,6 @@ CONFIG_DRM_SIMPLE_BRIDGE=y CONFIG_DRM_I2C_ADV7511=y CONFIG_DRM_I2C_ADV7511_AUDIO=y CONFIG_FB_SH_MOBILE_LCDC=y -# CONFIG_BACKLIGHT_GENERIC is not set CONFIG_BACKLIGHT_PWM=y CONFIG_BACKLIGHT_AS3711=y CONFIG_SOUND=y diff --git a/arch/arm/configs/versatile_defconfig b/arch/arm/configs/versatile_defconfig index 767935337413..e7ecfb365e91 100644 --- a/arch/arm/configs/versatile_defconfig +++ b/arch/arm/configs/versatile_defconfig @@ -9,8 +9,6 @@ CONFIG_SLAB=y CONFIG_ARCH_VERSATILE=y CONFIG_AEABI=y CONFIG_OABI_COMPAT=y -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_CMDLINE="root=1f03 mem=32M" CONFIG_FPE_NWFPE=y CONFIG_VFP=y @@ -59,6 +57,7 @@ CONFIG_GPIO_PL061=y CONFIG_DRM=y CONFIG_DRM_PANEL_ARM_VERSATILE=y CONFIG_DRM_PANEL_SIMPLE=y +CONFIG_DRM_DISPLAY_CONNECTOR=y CONFIG_DRM_SIMPLE_BRIDGE=y CONFIG_DRM_PL111=y CONFIG_FB_MODE_HELPERS=y @@ -91,8 +90,8 @@ CONFIG_NLS_CODEPAGE_850=m CONFIG_NLS_ISO8859_1=m CONFIG_FONTS=y CONFIG_FONT_ACORN_8x8=y -CONFIG_DEBUG_FS=y CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_FS=y CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_USER=y CONFIG_DEBUG_LL=y diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h index 1d65ed3a2755..e3ea34558ada 100644 --- a/arch/arm/include/asm/cache.h +++ b/arch/arm/include/asm/cache.h @@ -24,6 +24,6 @@ #define ARCH_SLAB_MINALIGN 8 #endif -#define __read_mostly __attribute__((__section__(".data..read_mostly"))) +#define __read_mostly __section(".data..read_mostly") #endif diff --git a/arch/arm/include/asm/cpuidle.h b/arch/arm/include/asm/cpuidle.h index 6b2ff7243b4b..0d67ed682e07 100644 --- a/arch/arm/include/asm/cpuidle.h +++ b/arch/arm/include/asm/cpuidle.h @@ -42,7 +42,7 @@ struct of_cpuidle_method { #define CPUIDLE_METHOD_OF_DECLARE(name, _method, _ops) \ static const struct of_cpuidle_method __cpuidle_method_of_table_##name \ - __used __section(__cpuidle_method_of_table) \ + __used __section("__cpuidle_method_of_table") \ = { .method = _method, .ops = _ops } extern int arm_cpuidle_suspend(int index); diff --git a/arch/arm/include/asm/idmap.h b/arch/arm/include/asm/idmap.h index aab7e8358e6a..baebb67b3512 100644 --- a/arch/arm/include/asm/idmap.h +++ b/arch/arm/include/asm/idmap.h @@ -6,7 +6,7 @@ #include <linux/pgtable.h> /* Tag a function as requiring to be executed via an identity mapping. */ -#define __idmap __section(.idmap.text) noinline notrace +#define __idmap __section(".idmap.text") noinline notrace extern pgd_t *idmap_pgd; diff --git a/arch/arm/include/asm/kprobes.h b/arch/arm/include/asm/kprobes.h index 213607a1f45c..e26a278d301a 100644 --- a/arch/arm/include/asm/kprobes.h +++ b/arch/arm/include/asm/kprobes.h @@ -44,20 +44,20 @@ int kprobe_exceptions_notify(struct notifier_block *self, unsigned long val, void *data); /* optinsn template addresses */ -extern __visible kprobe_opcode_t optprobe_template_entry; -extern __visible kprobe_opcode_t optprobe_template_val; -extern __visible kprobe_opcode_t optprobe_template_call; -extern __visible kprobe_opcode_t optprobe_template_end; -extern __visible kprobe_opcode_t optprobe_template_sub_sp; -extern __visible kprobe_opcode_t optprobe_template_add_sp; -extern __visible kprobe_opcode_t optprobe_template_restore_begin; -extern __visible kprobe_opcode_t optprobe_template_restore_orig_insn; -extern __visible kprobe_opcode_t optprobe_template_restore_end; +extern __visible kprobe_opcode_t optprobe_template_entry[]; +extern __visible kprobe_opcode_t optprobe_template_val[]; +extern __visible kprobe_opcode_t optprobe_template_call[]; +extern __visible kprobe_opcode_t optprobe_template_end[]; +extern __visible kprobe_opcode_t optprobe_template_sub_sp[]; +extern __visible kprobe_opcode_t optprobe_template_add_sp[]; +extern __visible kprobe_opcode_t optprobe_template_restore_begin[]; +extern __visible kprobe_opcode_t optprobe_template_restore_orig_insn[]; +extern __visible kprobe_opcode_t optprobe_template_restore_end[]; #define MAX_OPTIMIZED_LENGTH 4 #define MAX_OPTINSN_SIZE \ - ((unsigned long)&optprobe_template_end - \ - (unsigned long)&optprobe_template_entry) + ((unsigned long)optprobe_template_end - \ + (unsigned long)optprobe_template_entry) #define RELATIVEJUMP_SIZE 4 struct arch_optimized_insn { diff --git a/arch/arm/include/asm/mach/arch.h b/arch/arm/include/asm/mach/arch.h index e7df5a822cab..eec0c0bda766 100644 --- a/arch/arm/include/asm/mach/arch.h +++ b/arch/arm/include/asm/mach/arch.h @@ -81,7 +81,7 @@ extern const struct machine_desc __arch_info_begin[], __arch_info_end[]; #define MACHINE_START(_type,_name) \ static const struct machine_desc __mach_desc_##_type \ __used \ - __attribute__((__section__(".arch.info.init"))) = { \ + __section(".arch.info.init") = { \ .nr = MACH_TYPE_##_type, \ .name = _name, @@ -91,7 +91,7 @@ static const struct machine_desc __mach_desc_##_type \ #define DT_MACHINE_START(_name, _namestr) \ static const struct machine_desc __mach_desc_##_name \ __used \ - __attribute__((__section__(".arch.info.init"))) = { \ + __section(".arch.info.init") = { \ .nr = ~0, \ .name = _namestr, diff --git a/arch/arm/include/asm/mach/pci.h b/arch/arm/include/asm/mach/pci.h index 83d340702680..ea9bd08895b7 100644 --- a/arch/arm/include/asm/mach/pci.h +++ b/arch/arm/include/asm/mach/pci.h @@ -17,10 +17,8 @@ struct pci_host_bridge; struct device; struct hw_pci { - struct msi_controller *msi_ctrl; struct pci_ops *ops; int nr_controllers; - unsigned int io_optional:1; void **private_data; int (*setup)(int nr, struct pci_sys_data *); int (*scan)(int nr, struct pci_host_bridge *); @@ -28,11 +26,6 @@ struct hw_pci { void (*postinit)(void); u8 (*swizzle)(struct pci_dev *dev, u8 *pin); int (*map_irq)(const struct pci_dev *dev, u8 slot, u8 pin); - resource_size_t (*align_resource)(struct pci_dev *dev, - const struct resource *res, - resource_size_t start, - resource_size_t size, - resource_size_t align); }; /* diff --git a/arch/arm/kernel/module.lds b/arch/arm/include/asm/module.lds.h index 79cb6af565e5..0e7cb4e314b4 100644 --- a/arch/arm/kernel/module.lds +++ b/arch/arm/include/asm/module.lds.h @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ +#ifdef CONFIG_ARM_MODULE_PLTS SECTIONS { .plt : { BYTE(0) } .init.plt : { BYTE(0) } } +#endif diff --git a/arch/arm/include/asm/setup.h b/arch/arm/include/asm/setup.h index 67d20712cb48..3ae68a1b3de6 100644 --- a/arch/arm/include/asm/setup.h +++ b/arch/arm/include/asm/setup.h @@ -14,7 +14,7 @@ #include <uapi/asm/setup.h> -#define __tag __used __attribute__((__section__(".taglist.init"))) +#define __tag __used __section(".taglist.init") #define __tagtable(tag, fn) \ static const struct tagtable __tagtable_##fn __tag = { tag, fn } diff --git a/arch/arm/include/asm/smp.h b/arch/arm/include/asm/smp.h index 0ca55a607d0a..5d508f5d56c4 100644 --- a/arch/arm/include/asm/smp.h +++ b/arch/arm/include/asm/smp.h @@ -112,7 +112,7 @@ struct of_cpu_method { #define CPU_METHOD_OF_DECLARE(name, _method, _ops) \ static const struct of_cpu_method __cpu_method_of_table_##name \ - __used __section(__cpu_method_of_table) \ + __used __section("__cpu_method_of_table") \ = { .method = _method, .ops = _ops } /* * set platform specific SMP operations diff --git a/arch/arm/include/asm/tcm.h b/arch/arm/include/asm/tcm.h index b845b10fe29a..d8bd8a4b0ede 100644 --- a/arch/arm/include/asm/tcm.h +++ b/arch/arm/include/asm/tcm.h @@ -16,13 +16,13 @@ #include <linux/compiler.h> /* Tag variables with this */ -#define __tcmdata __section(.tcm.data) +#define __tcmdata __section(".tcm.data") /* Tag constants with this */ -#define __tcmconst __section(.tcm.rodata) +#define __tcmconst __section(".tcm.rodata") /* Tag functions inside TCM called from outside TCM with this */ -#define __tcmfunc __attribute__((long_call)) __section(.tcm.text) noinline +#define __tcmfunc __attribute__((long_call)) __section(".tcm.text") noinline /* Tag function inside TCM called from inside TCM with this */ -#define __tcmlocalfunc __section(.tcm.text) +#define __tcmlocalfunc __section(".tcm.text") void *tcm_alloc(size_t len); void tcm_free(void *addr, size_t len); diff --git a/arch/arm/include/debug/8250.S b/arch/arm/include/debug/8250.S index e4a036f082c2..e3692a37cede 100644 --- a/arch/arm/include/debug/8250.S +++ b/arch/arm/include/debug/8250.S @@ -45,10 +45,11 @@ bne 1002b .endm - .macro waituart,rd,rx -#ifdef CONFIG_DEBUG_UART_8250_FLOW_CONTROL + .macro waituarttxrdy,rd,rx + .endm + + .macro waituartcts,rd,rx 1001: load \rd, [\rx, #UART_MSR << UART_SHIFT] tst \rd, #UART_MSR_CTS beq 1001b -#endif .endm diff --git a/arch/arm/include/debug/asm9260.S b/arch/arm/include/debug/asm9260.S index 0da1eb625331..5a0ce145c44a 100644 --- a/arch/arm/include/debug/asm9260.S +++ b/arch/arm/include/debug/asm9260.S @@ -11,7 +11,10 @@ ldr \rv, = CONFIG_DEBUG_UART_VIRT .endm - .macro waituart,rd,rx + .macro waituarttxrdy,rd,rx + .endm + + .macro waituartcts,rd,rx .endm .macro senduart,rd,rx diff --git a/arch/arm/include/debug/at91.S b/arch/arm/include/debug/at91.S index 6c91cbaaa20b..17722824e2f2 100644 --- a/arch/arm/include/debug/at91.S +++ b/arch/arm/include/debug/at91.S @@ -19,12 +19,15 @@ strb \rd, [\rx, #(AT91_DBGU_THR)] @ Write to Transmitter Holding Register .endm - .macro waituart,rd,rx + .macro waituarttxrdy,rd,rx 1001: ldr \rd, [\rx, #(AT91_DBGU_SR)] @ Read Status Register tst \rd, #AT91_DBGU_TXRDY @ DBGU_TXRDY = 1 when ready to transmit beq 1001b .endm + .macro waituartcts,rd,rx + .endm + .macro busyuart,rd,rx 1001: ldr \rd, [\rx, #(AT91_DBGU_SR)] @ Read Status Register tst \rd, #AT91_DBGU_TXEMPTY @ DBGU_TXEMPTY = 1 when transmission complete diff --git a/arch/arm/include/debug/bcm63xx.S b/arch/arm/include/debug/bcm63xx.S index 06a896227396..da65abb6738d 100644 --- a/arch/arm/include/debug/bcm63xx.S +++ b/arch/arm/include/debug/bcm63xx.S @@ -17,12 +17,15 @@ strb \rd, [\rx, #UART_FIFO_REG] .endm - .macro waituart, rd, rx + .macro waituarttxrdy, rd, rx 1001: ldr \rd, [\rx, #UART_IR_REG] tst \rd, #(1 << UART_IR_TXEMPTY) beq 1001b .endm + .macro waituartcts, rd, rx + .endm + .macro busyuart, rd, rx 1002: ldr \rd, [\rx, #UART_IR_REG] tst \rd, #(1 << UART_IR_TXTRESH) diff --git a/arch/arm/include/debug/brcmstb.S b/arch/arm/include/debug/brcmstb.S index 132a20c4a676..0ff32ffc610c 100644 --- a/arch/arm/include/debug/brcmstb.S +++ b/arch/arm/include/debug/brcmstb.S @@ -32,6 +32,8 @@ #define UARTA_7271 UARTA_7268 #define UARTA_7278 REG_PHYS_ADDR_V7(0x40c000) #define UARTA_7216 UARTA_7278 +#define UARTA_72164 UARTA_7278 +#define UARTA_72165 UARTA_7278 #define UARTA_7364 REG_PHYS_ADDR(0x40b000) #define UARTA_7366 UARTA_7364 #define UARTA_74371 REG_PHYS_ADDR(0x406b00) @@ -84,17 +86,19 @@ ARM_BE8( rev \rv, \rv ) /* Chip specific detection starts here */ 20: checkuart(\rp, \rv, 0x33900000, 3390) 21: checkuart(\rp, \rv, 0x72160000, 7216) -22: checkuart(\rp, \rv, 0x72500000, 7250) -23: checkuart(\rp, \rv, 0x72550000, 7255) -24: checkuart(\rp, \rv, 0x72600000, 7260) -25: checkuart(\rp, \rv, 0x72680000, 7268) -26: checkuart(\rp, \rv, 0x72710000, 7271) -27: checkuart(\rp, \rv, 0x72780000, 7278) -28: checkuart(\rp, \rv, 0x73640000, 7364) -29: checkuart(\rp, \rv, 0x73660000, 7366) -30: checkuart(\rp, \rv, 0x07437100, 74371) -31: checkuart(\rp, \rv, 0x74390000, 7439) -32: checkuart(\rp, \rv, 0x74450000, 7445) +22: checkuart(\rp, \rv, 0x07216400, 72164) +23: checkuart(\rp, \rv, 0x07216500, 72165) +24: checkuart(\rp, \rv, 0x72500000, 7250) +25: checkuart(\rp, \rv, 0x72550000, 7255) +26: checkuart(\rp, \rv, 0x72600000, 7260) +27: checkuart(\rp, \rv, 0x72680000, 7268) +28: checkuart(\rp, \rv, 0x72710000, 7271) +29: checkuart(\rp, \rv, 0x72780000, 7278) +30: checkuart(\rp, \rv, 0x73640000, 7364) +31: checkuart(\rp, \rv, 0x73660000, 7366) +32: checkuart(\rp, \rv, 0x07437100, 74371) +33: checkuart(\rp, \rv, 0x74390000, 7439) +34: checkuart(\rp, \rv, 0x74450000, 7445) /* No valid UART found */ 90: mov \rp, #0 @@ -142,7 +146,10 @@ ARM_BE8( rev \rd, \rd ) bne 1002b .endm - .macro waituart,rd,rx + .macro waituarttxrdy,rd,rx + .endm + + .macro waituartcts,rd,rx .endm /* diff --git a/arch/arm/include/debug/clps711x.S b/arch/arm/include/debug/clps711x.S index 774a67ac3877..a983d12a6515 100644 --- a/arch/arm/include/debug/clps711x.S +++ b/arch/arm/include/debug/clps711x.S @@ -20,7 +20,10 @@ ldr \rp, =CLPS711X_UART_PADDR .endm - .macro waituart,rd,rx + .macro waituartcts,rd,rx + .endm + + .macro waituarttxrdy,rd,rx .endm .macro senduart,rd,rx diff --git a/arch/arm/include/debug/dc21285.S b/arch/arm/include/debug/dc21285.S index d7e8c71706ab..4ec0e5e31704 100644 --- a/arch/arm/include/debug/dc21285.S +++ b/arch/arm/include/debug/dc21285.S @@ -34,5 +34,8 @@ bne 1001b .endm - .macro waituart,rd,rx + .macro waituartcts,rd,rx + .endm + + .macro waituarttxrdy,rd,rx .endm diff --git a/arch/arm/include/debug/digicolor.S b/arch/arm/include/debug/digicolor.S index 256f5f4da275..443674cad76a 100644 --- a/arch/arm/include/debug/digicolor.S +++ b/arch/arm/include/debug/digicolor.S @@ -21,7 +21,10 @@ strb \rd, [\rx, #UA0_EMI_REC] .endm - .macro waituart,rd,rx + .macro waituartcts,rd,rx + .endm + + .macro waituarttxrdy,rd,rx .endm .macro busyuart,rd,rx diff --git a/arch/arm/include/debug/efm32.S b/arch/arm/include/debug/efm32.S index 5ed5028306f4..b0083d6e31e8 100644 --- a/arch/arm/include/debug/efm32.S +++ b/arch/arm/include/debug/efm32.S @@ -29,7 +29,10 @@ strb \rd, [\rx, #UARTn_TXDATA] .endm - .macro waituart,rd,rx + .macro waituartcts,rd,rx + .endm + + .macro waituarttxrdy,rd,rx 1001: ldr \rd, [\rx, #UARTn_STATUS] tst \rd, #UARTn_STATUS_TXBL beq 1001b diff --git a/arch/arm/include/debug/icedcc.S b/arch/arm/include/debug/icedcc.S index 74a0dd036a17..d5e65da8a687 100644 --- a/arch/arm/include/debug/icedcc.S +++ b/arch/arm/include/debug/icedcc.S @@ -23,7 +23,10 @@ beq 1001b .endm - .macro waituart, rd, rx + .macro waituartcts, rd, rx + .endm + + .macro waituarttxrdy, rd, rx mov \rd, #0x2000000 1001: subs \rd, \rd, #1 @@ -47,7 +50,10 @@ beq 1001b .endm - .macro waituart, rd, rx + .macro waituartcts, rd, rx + .endm + + .macro waituarttxrdy, rd, rx mov \rd, #0x10000000 1001: subs \rd, \rd, #1 @@ -72,7 +78,10 @@ .endm - .macro waituart, rd, rx + .macro waituartcts, rd, rx + .endm + + .macro waituarttxrdy, rd, rx mov \rd, #0x2000000 1001: subs \rd, \rd, #1 diff --git a/arch/arm/include/debug/imx.S b/arch/arm/include/debug/imx.S index 1c1b9d1da4c8..bb7b9550580c 100644 --- a/arch/arm/include/debug/imx.S +++ b/arch/arm/include/debug/imx.S @@ -35,7 +35,10 @@ str \rd, [\rx, #0x40] @ TXDATA .endm - .macro waituart,rd,rx + .macro waituartcts,rd,rx + .endm + + .macro waituarttxrdy,rd,rx .endm .macro busyuart,rd,rx diff --git a/arch/arm/include/debug/meson.S b/arch/arm/include/debug/meson.S index 1e501a0054ae..7b60e4401225 100644 --- a/arch/arm/include/debug/meson.S +++ b/arch/arm/include/debug/meson.S @@ -25,7 +25,10 @@ beq 1002b .endm - .macro waituart,rd,rx + .macro waituartcts,rd,rx + .endm + + .macro waituarttxrdy,rd,rx 1001: ldr \rd, [\rx, #MESON_AO_UART_STATUS] tst \rd, #MESON_AO_UART_TX_FIFO_FULL bne 1001b diff --git a/arch/arm/include/debug/msm.S b/arch/arm/include/debug/msm.S index 9405b71461da..530edc74f9a3 100644 --- a/arch/arm/include/debug/msm.S +++ b/arch/arm/include/debug/msm.S @@ -17,7 +17,10 @@ ARM_BE8(rev \rd, \rd ) str \rd, [\rx, #0x70] .endm - .macro waituart, rd, rx + .macro waituartcts,rd,rx + .endm + + .macro waituarttxrdy, rd, rx @ check for TX_EMT in UARTDM_SR ldr \rd, [\rx, #0x08] ARM_BE8(rev \rd, \rd ) diff --git a/arch/arm/include/debug/omap2plus.S b/arch/arm/include/debug/omap2plus.S index b5696a33ba0f..0680be6c79d3 100644 --- a/arch/arm/include/debug/omap2plus.S +++ b/arch/arm/include/debug/omap2plus.S @@ -75,5 +75,8 @@ omap_uart_lsr: .word 0 bne 1001b .endm - .macro waituart,rd,rx + .macro waituartcts,rd,rx + .endm + + .macro waituarttxrdy,rd,rx .endm diff --git a/arch/arm/include/debug/pl01x.S b/arch/arm/include/debug/pl01x.S index a2a553afe7b8..0c7bfa4c10db 100644 --- a/arch/arm/include/debug/pl01x.S +++ b/arch/arm/include/debug/pl01x.S @@ -26,7 +26,10 @@ strb \rd, [\rx, #UART01x_DR] .endm - .macro waituart,rd,rx + .macro waituartcts,rd,rx + .endm + + .macro waituarttxrdy,rd,rx 1001: ldr \rd, [\rx, #UART01x_FR] ARM_BE8( rev \rd, \rd ) tst \rd, #UART01x_FR_TXFF diff --git a/arch/arm/include/debug/renesas-scif.S b/arch/arm/include/debug/renesas-scif.S index 25f06663a9a4..8e433e981bbe 100644 --- a/arch/arm/include/debug/renesas-scif.S +++ b/arch/arm/include/debug/renesas-scif.S @@ -33,7 +33,10 @@ ldr \rv, =SCIF_VIRT .endm - .macro waituart, rd, rx + .macro waituartcts,rd,rx + .endm + + .macro waituarttxrdy, rd, rx 1001: ldrh \rd, [\rx, #FSR] tst \rd, #TDFE beq 1001b diff --git a/arch/arm/include/debug/sa1100.S b/arch/arm/include/debug/sa1100.S index 6109e6058e5b..7968ea52df3d 100644 --- a/arch/arm/include/debug/sa1100.S +++ b/arch/arm/include/debug/sa1100.S @@ -51,7 +51,10 @@ str \rd, [\rx, #UTDR] .endm - .macro waituart,rd,rx + .macro waituartcts,rd,rx + .endm + + .macro waituarttxrdy,rd,rx 1001: ldr \rd, [\rx, #UTSR1] tst \rd, #UTSR1_TNF beq 1001b diff --git a/arch/arm/include/debug/samsung.S b/arch/arm/include/debug/samsung.S index 69201d7fb48f..ab474d564a90 100644 --- a/arch/arm/include/debug/samsung.S +++ b/arch/arm/include/debug/samsung.S @@ -69,7 +69,10 @@ ARM_BE8(rev \rd, \rd) 1002: @ exit busyuart .endm - .macro waituart,rd,rx + .macro waituartcts,rd,rx + .endm + + .macro waituarttxrdy,rd,rx ldr \rd, [\rx, # S3C2410_UFCON] ARM_BE8(rev \rd, \rd) tst \rd, #S3C2410_UFCON_FIFOMODE @ fifo enabled? diff --git a/arch/arm/include/debug/sirf.S b/arch/arm/include/debug/sirf.S index e73e4de0a015..3612c7b9cbe7 100644 --- a/arch/arm/include/debug/sirf.S +++ b/arch/arm/include/debug/sirf.S @@ -29,7 +29,10 @@ .macro busyuart,rd,rx .endm - .macro waituart,rd,rx + .macro waituartcts,rd,rx + .endm + + .macro waituarttxrdy,rd,rx 1001: ldr \rd, [\rx, #SIRF_LLUART_TXFIFO_STATUS] tst \rd, #SIRF_LLUART_TXFIFO_EMPTY beq 1001b diff --git a/arch/arm/include/debug/sti.S b/arch/arm/include/debug/sti.S index 6b42c91f217d..72d052511890 100644 --- a/arch/arm/include/debug/sti.S +++ b/arch/arm/include/debug/sti.S @@ -45,7 +45,10 @@ strb \rd, [\rx, #ASC_TX_BUF_OFF] .endm - .macro waituart,rd,rx + .macro waituartcts,rd,rx + .endm + + .macro waituarttxrdy,rd,rx 1001: ldr \rd, [\rx, #ASC_STA_OFF] tst \rd, #ASC_STA_TX_FULL bne 1001b diff --git a/arch/arm/include/debug/stm32.S b/arch/arm/include/debug/stm32.S index f3c4a37210ed..b6d9df30e37d 100644 --- a/arch/arm/include/debug/stm32.S +++ b/arch/arm/include/debug/stm32.S @@ -27,7 +27,10 @@ strb \rd, [\rx, #STM32_USART_TDR_OFF] .endm -.macro waituart,rd,rx +.macro waituartcts,rd,rx +.endm + +.macro waituarttxrdy,rd,rx 1001: ldr \rd, [\rx, #(STM32_USART_SR_OFF)] @ Read Status Register tst \rd, #STM32_USART_TXE @ TXE = 1 = tx empty beq 1001b diff --git a/arch/arm/include/debug/tegra.S b/arch/arm/include/debug/tegra.S index 2148d0f88591..98daa7f48314 100644 --- a/arch/arm/include/debug/tegra.S +++ b/arch/arm/include/debug/tegra.S @@ -178,15 +178,16 @@ 1002: .endm - .macro waituart, rd, rx -#ifdef FLOW_CONTROL + .macro waituartcts, rd, rx cmp \rx, #0 beq 1002f 1001: ldrb \rd, [\rx, #UART_MSR << UART_SHIFT] tst \rd, #UART_MSR_CTS beq 1001b 1002: -#endif + .endm + + .macro waituarttxrdy,rd,rx .endm /* diff --git a/arch/arm/include/debug/vf.S b/arch/arm/include/debug/vf.S index 854d9bd82770..035bcbf117ab 100644 --- a/arch/arm/include/debug/vf.S +++ b/arch/arm/include/debug/vf.S @@ -29,5 +29,8 @@ beq 1001b @ wait until transmit done .endm - .macro waituart,rd,rx + .macro waituartcts,rd,rx + .endm + + .macro waituarttxrdy,rd,rx .endm diff --git a/arch/arm/include/debug/vt8500.S b/arch/arm/include/debug/vt8500.S index 8dc1df2d91b8..d01094fdbc8c 100644 --- a/arch/arm/include/debug/vt8500.S +++ b/arch/arm/include/debug/vt8500.S @@ -28,7 +28,10 @@ bne 1001b .endm - .macro waituart,rd,rx + .macro waituartcts,rd,rx + .endm + + .macro waituarttxrdy,rd,rx .endm #endif diff --git a/arch/arm/include/debug/zynq.S b/arch/arm/include/debug/zynq.S index 58d77c972fd6..5d42cc35ecf3 100644 --- a/arch/arm/include/debug/zynq.S +++ b/arch/arm/include/debug/zynq.S @@ -33,7 +33,10 @@ strb \rd, [\rx, #UART_FIFO_OFFSET] @ TXDATA .endm - .macro waituart,rd,rx + .macro waituartcts,rd,rx + .endm + + .macro waituarttxrdy,rd,rx 1001: ldr \rd, [\rx, #UART_SR_OFFSET] ARM_BE8( rev \rd, \rd ) tst \rd, #UART_SR_TXEMPTY diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c index eecec16aa708..e7ef2b5bea9c 100644 --- a/arch/arm/kernel/bios32.c +++ b/arch/arm/kernel/bios32.c @@ -394,8 +394,7 @@ static int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) return irq; } -static int pcibios_init_resource(int busnr, struct pci_sys_data *sys, - int io_optional) +static int pcibios_init_resource(int busnr, struct pci_sys_data *sys) { int ret; struct resource_entry *window; @@ -405,14 +404,6 @@ static int pcibios_init_resource(int busnr, struct pci_sys_data *sys, &iomem_resource, sys->mem_offset); } - /* - * If a platform says I/O port support is optional, we don't add - * the default I/O space. The platform is responsible for adding - * any I/O space it needs. - */ - if (io_optional) - return 0; - resource_list_for_each_entry(window, &sys->resources) if (resource_type(window->res) == IORESOURCE_IO) return 0; @@ -462,7 +453,7 @@ static void pcibios_init_hw(struct device *parent, struct hw_pci *hw, if (ret > 0) { - ret = pcibios_init_resource(nr, sys, hw->io_optional); + ret = pcibios_init_resource(nr, sys); if (ret) { pci_free_host_bridge(bridge); break; @@ -480,9 +471,6 @@ static void pcibios_init_hw(struct device *parent, struct hw_pci *hw, bridge->sysdata = sys; bridge->busnr = sys->busnr; bridge->ops = hw->ops; - bridge->msi = hw->msi_ctrl; - bridge->align_resource = - hw->align_resource; ret = pci_scan_root_bus_bridge(bridge); } diff --git a/arch/arm/kernel/cpuidle.c b/arch/arm/kernel/cpuidle.c index 093368e0d020..e1684623e1b2 100644 --- a/arch/arm/kernel/cpuidle.c +++ b/arch/arm/kernel/cpuidle.c @@ -11,7 +11,7 @@ extern struct of_cpuidle_method __cpuidle_method_of_table[]; static const struct of_cpuidle_method __cpuidle_method_of_table_sentinel - __used __section(__cpuidle_method_of_table_end); + __used __section("__cpuidle_method_of_table_end"); static struct cpuidle_ops cpuidle_ops[NR_CPUS] __ro_after_init; diff --git a/arch/arm/kernel/debug.S b/arch/arm/kernel/debug.S index e112072b579d..d92f44bdf438 100644 --- a/arch/arm/kernel/debug.S +++ b/arch/arm/kernel/debug.S @@ -89,11 +89,18 @@ ENTRY(printascii) 2: teq r1, #'\n' bne 3f mov r1, #'\r' - waituart r2, r3 +#ifdef CONFIG_DEBUG_UART_FLOW_CONTROL + waituartcts r2, r3 +#endif + waituarttxrdy r2, r3 senduart r1, r3 busyuart r2, r3 mov r1, #'\n' -3: waituart r2, r3 +3: +#ifdef CONFIG_DEBUG_UART_FLOW_CONTROL + waituartcts r2, r3 +#endif + waituarttxrdy r2, r3 senduart r1, r3 busyuart r2, r3 b 1b diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c index 39c978698406..7f0745a97e20 100644 --- a/arch/arm/kernel/devtree.c +++ b/arch/arm/kernel/devtree.c @@ -29,7 +29,7 @@ extern struct of_cpu_method __cpu_method_of_table[]; static const struct of_cpu_method __cpu_method_of_table_sentinel - __used __section(__cpu_method_of_table_end); + __used __section("__cpu_method_of_table_end"); static int __init set_smp_ops_by_method(struct device_node *node) diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c index 7a4853b1213a..08660ae9dcbc 100644 --- a/arch/arm/kernel/hw_breakpoint.c +++ b/arch/arm/kernel/hw_breakpoint.c @@ -683,6 +683,40 @@ static void disable_single_step(struct perf_event *bp) arch_install_hw_breakpoint(bp); } +/* + * Arm32 hardware does not always report a watchpoint hit address that matches + * one of the watchpoints set. It can also report an address "near" the + * watchpoint if a single instruction access both watched and unwatched + * addresses. There is no straight-forward way, short of disassembling the + * offending instruction, to map that address back to the watchpoint. This + * function computes the distance of the memory access from the watchpoint as a + * heuristic for the likelyhood that a given access triggered the watchpoint. + * + * See this same function in the arm64 platform code, which has the same + * problem. + * + * The function returns the distance of the address from the bytes watched by + * the watchpoint. In case of an exact match, it returns 0. + */ +static u32 get_distance_from_watchpoint(unsigned long addr, u32 val, + struct arch_hw_breakpoint_ctrl *ctrl) +{ + u32 wp_low, wp_high; + u32 lens, lene; + + lens = __ffs(ctrl->len); + lene = __fls(ctrl->len); + + wp_low = val + lens; + wp_high = val + lene; + if (addr < wp_low) + return wp_low - addr; + else if (addr > wp_high) + return addr - wp_high; + else + return 0; +} + static int watchpoint_fault_on_uaccess(struct pt_regs *regs, struct arch_hw_breakpoint *info) { @@ -692,23 +726,25 @@ static int watchpoint_fault_on_uaccess(struct pt_regs *regs, static void watchpoint_handler(unsigned long addr, unsigned int fsr, struct pt_regs *regs) { - int i, access; - u32 val, ctrl_reg, alignment_mask; + int i, access, closest_match = 0; + u32 min_dist = -1, dist; + u32 val, ctrl_reg; struct perf_event *wp, **slots; struct arch_hw_breakpoint *info; struct arch_hw_breakpoint_ctrl ctrl; slots = this_cpu_ptr(wp_on_reg); + /* + * Find all watchpoints that match the reported address. If no exact + * match is found. Attribute the hit to the closest watchpoint. + */ + rcu_read_lock(); for (i = 0; i < core_num_wrps; ++i) { - rcu_read_lock(); - wp = slots[i]; - if (wp == NULL) - goto unlock; + continue; - info = counter_arch_bp(wp); /* * The DFAR is an unknown value on debug architectures prior * to 7.1. Since we only allow a single watchpoint on these @@ -717,33 +753,31 @@ static void watchpoint_handler(unsigned long addr, unsigned int fsr, */ if (debug_arch < ARM_DEBUG_ARCH_V7_1) { BUG_ON(i > 0); + info = counter_arch_bp(wp); info->trigger = wp->attr.bp_addr; } else { - if (info->ctrl.len == ARM_BREAKPOINT_LEN_8) - alignment_mask = 0x7; - else - alignment_mask = 0x3; - - /* Check if the watchpoint value matches. */ - val = read_wb_reg(ARM_BASE_WVR + i); - if (val != (addr & ~alignment_mask)) - goto unlock; - - /* Possible match, check the byte address select. */ - ctrl_reg = read_wb_reg(ARM_BASE_WCR + i); - decode_ctrl_reg(ctrl_reg, &ctrl); - if (!((1 << (addr & alignment_mask)) & ctrl.len)) - goto unlock; - /* Check that the access type matches. */ if (debug_exception_updates_fsr()) { access = (fsr & ARM_FSR_ACCESS_MASK) ? HW_BREAKPOINT_W : HW_BREAKPOINT_R; if (!(access & hw_breakpoint_type(wp))) - goto unlock; + continue; } + val = read_wb_reg(ARM_BASE_WVR + i); + ctrl_reg = read_wb_reg(ARM_BASE_WCR + i); + decode_ctrl_reg(ctrl_reg, &ctrl); + dist = get_distance_from_watchpoint(addr, val, &ctrl); + if (dist < min_dist) { + min_dist = dist; + closest_match = i; + } + /* Is this an exact match? */ + if (dist != 0) + continue; + /* We have a winner. */ + info = counter_arch_bp(wp); info->trigger = addr; } @@ -765,13 +799,23 @@ static void watchpoint_handler(unsigned long addr, unsigned int fsr, * we can single-step over the watchpoint trigger. */ if (!is_default_overflow_handler(wp)) - goto unlock; - + continue; step: enable_single_step(wp, instruction_pointer(regs)); -unlock: - rcu_read_unlock(); } + + if (min_dist > 0 && min_dist != -1) { + /* No exact match found. */ + wp = slots[closest_match]; + info = counter_arch_bp(wp); + info->trigger = addr; + pr_debug("watchpoint fired: address = 0x%x\n", info->trigger); + perf_bp_event(wp, regs); + if (is_default_overflow_handler(wp)) + enable_single_step(wp, instruction_pointer(regs)); + } + + rcu_read_unlock(); } static void watchpoint_single_step_handler(unsigned long pc) diff --git a/arch/arm/kernel/perf_regs.c b/arch/arm/kernel/perf_regs.c index 05fe92aa7d98..0529f90395c9 100644 --- a/arch/arm/kernel/perf_regs.c +++ b/arch/arm/kernel/perf_regs.c @@ -32,8 +32,7 @@ u64 perf_reg_abi(struct task_struct *task) } void perf_get_regs_user(struct perf_regs *regs_user, - struct pt_regs *regs, - struct pt_regs *regs_user_copy) + struct pt_regs *regs) { regs_user->regs = task_pt_regs(current); regs_user->abi = perf_reg_abi(current); diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c index c1892f733f20..585edbfccf6d 100644 --- a/arch/arm/kernel/signal.c +++ b/arch/arm/kernel/signal.c @@ -669,7 +669,6 @@ do_work_pending(struct pt_regs *regs, unsigned int thread_flags, int syscall) } else if (thread_flags & _TIF_UPROBE) { uprobe_notify_resume(regs); } else { - clear_thread_flag(TIF_NOTIFY_RESUME); tracehook_notify_resume(regs); rseq_handle_notify_resume(NULL, regs); } diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S index 5f4922e858d0..f7f4620d59c3 100644 --- a/arch/arm/kernel/vmlinux.lds.S +++ b/arch/arm/kernel/vmlinux.lds.S @@ -41,6 +41,10 @@ SECTIONS #ifndef CONFIG_SMP_ON_UP *(.alt.smp.init) #endif +#ifndef CONFIG_ARM_UNWIND + *(.ARM.exidx) *(.ARM.exidx.*) + *(.ARM.extab) *(.ARM.extab.*) +#endif } . = PAGE_OFFSET + TEXT_OFFSET; diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index 2aab043441e8..120f9aa6fff3 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c @@ -51,10 +51,11 @@ static struct at91_soc_pm soc_pm = { }; static const match_table_t pm_modes __initconst = { - { AT91_PM_STANDBY, "standby" }, - { AT91_PM_ULP0, "ulp0" }, - { AT91_PM_ULP1, "ulp1" }, - { AT91_PM_BACKUP, "backup" }, + { AT91_PM_STANDBY, "standby" }, + { AT91_PM_ULP0, "ulp0" }, + { AT91_PM_ULP0_FAST, "ulp0-fast" }, + { AT91_PM_ULP1, "ulp1" }, + { AT91_PM_BACKUP, "backup" }, { -1, NULL }, }; @@ -557,11 +558,6 @@ static void at91rm9200_idle(void) writel(AT91_PMC_PCK, soc_pm.data.pmc + AT91_PMC_SCDR); } -static void at91sam9x60_idle(void) -{ - cpu_do_idle(); -} - static void at91sam9_idle(void) { writel(AT91_PMC_PCK, soc_pm.data.pmc + AT91_PMC_SCDR); @@ -789,6 +785,51 @@ static const struct of_device_id atmel_pmc_ids[] __initconst = { { /* sentinel */ }, }; +static void __init at91_pm_modes_validate(const int *modes, int len) +{ + u8 i, standby = 0, suspend = 0; + int mode; + + for (i = 0; i < len; i++) { + if (standby && suspend) + break; + + if (modes[i] == soc_pm.data.standby_mode && !standby) { + standby = 1; + continue; + } + + if (modes[i] == soc_pm.data.suspend_mode && !suspend) { + suspend = 1; + continue; + } + } + + if (!standby) { + if (soc_pm.data.suspend_mode == AT91_PM_STANDBY) + mode = AT91_PM_ULP0; + else + mode = AT91_PM_STANDBY; + + pr_warn("AT91: PM: %s mode not supported! Using %s.\n", + pm_modes[soc_pm.data.standby_mode].pattern, + pm_modes[mode].pattern); + soc_pm.data.standby_mode = mode; + } + + if (!suspend) { + if (soc_pm.data.standby_mode == AT91_PM_ULP0) + mode = AT91_PM_STANDBY; + else + mode = AT91_PM_ULP0; + + pr_warn("AT91: PM: %s mode not supported! Using %s.\n", + pm_modes[soc_pm.data.suspend_mode].pattern, + pm_modes[mode].pattern); + soc_pm.data.suspend_mode = mode; + } +} + static void __init at91_pm_init(void (*pm_idle)(void)) { struct device_node *pmc_np; @@ -800,6 +841,7 @@ static void __init at91_pm_init(void (*pm_idle)(void)) pmc_np = of_find_matching_node_and_match(NULL, atmel_pmc_ids, &of_id); soc_pm.data.pmc = of_iomap(pmc_np, 0); + of_node_put(pmc_np); if (!soc_pm.data.pmc) { pr_err("AT91: PM not supported, PMC not found\n"); return; @@ -830,6 +872,14 @@ void __init at91rm9200_pm_init(void) if (!IS_ENABLED(CONFIG_SOC_AT91RM9200)) return; + /* + * Force STANDBY and ULP0 mode to avoid calling + * at91_pm_modes_validate() which may increase booting time. + * Platform supports anyway only STANDBY and ULP0 modes. + */ + soc_pm.data.standby_mode = AT91_PM_STANDBY; + soc_pm.data.suspend_mode = AT91_PM_ULP0; + at91_dt_ramc(); /* @@ -842,12 +892,17 @@ void __init at91rm9200_pm_init(void) void __init sam9x60_pm_init(void) { + static const int modes[] __initconst = { + AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST, AT91_PM_ULP1, + }; + if (!IS_ENABLED(CONFIG_SOC_SAM9X60)) return; + at91_pm_modes_validate(modes, ARRAY_SIZE(modes)); at91_pm_modes_init(); at91_dt_ramc(); - at91_pm_init(at91sam9x60_idle); + at91_pm_init(NULL); soc_pm.ws_ids = sam9x60_ws_ids; soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws; @@ -858,26 +913,46 @@ void __init at91sam9_pm_init(void) if (!IS_ENABLED(CONFIG_SOC_AT91SAM9)) return; + /* + * Force STANDBY and ULP0 mode to avoid calling + * at91_pm_modes_validate() which may increase booting time. + * Platform supports anyway only STANDBY and ULP0 modes. + */ + soc_pm.data.standby_mode = AT91_PM_STANDBY; + soc_pm.data.suspend_mode = AT91_PM_ULP0; + at91_dt_ramc(); at91_pm_init(at91sam9_idle); } void __init sama5_pm_init(void) { + static const int modes[] __initconst = { + AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST, + }; + if (!IS_ENABLED(CONFIG_SOC_SAMA5)) return; + at91_pm_modes_validate(modes, ARRAY_SIZE(modes)); at91_dt_ramc(); at91_pm_init(NULL); } void __init sama5d2_pm_init(void) { + static const int modes[] __initconst = { + AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST, AT91_PM_ULP1, + AT91_PM_BACKUP, + }; + if (!IS_ENABLED(CONFIG_SOC_SAMA5D2)) return; + at91_pm_modes_validate(modes, ARRAY_SIZE(modes)); at91_pm_modes_init(); - sama5_pm_init(); + at91_dt_ramc(); + at91_pm_init(NULL); soc_pm.ws_ids = sama5d2_ws_ids; soc_pm.config_shdwc_ws = at91_sama5d2_config_shdwc_ws; diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h index 218e8d1a30fb..bfb260be371e 100644 --- a/arch/arm/mach-at91/pm.h +++ b/arch/arm/mach-at91/pm.h @@ -19,8 +19,9 @@ #define AT91_PM_STANDBY 0x00 #define AT91_PM_ULP0 0x01 -#define AT91_PM_ULP1 0x02 -#define AT91_PM_BACKUP 0x03 +#define AT91_PM_ULP0_FAST 0x02 +#define AT91_PM_ULP1 0x03 +#define AT91_PM_BACKUP 0x04 #ifndef __ASSEMBLY__ struct at91_pm_data { diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspend.S index be9764e8d3fa..0184de05c1be 100644 --- a/arch/arm/mach-at91/pm_suspend.S +++ b/arch/arm/mach-at91/pm_suspend.S @@ -164,7 +164,22 @@ ENDPROC(at91_backup_mode) .macro at91_pm_ulp0_mode ldr pmc, .pmc_base + ldr tmp2, .pm_mode + ldr tmp3, .mckr_offset + + /* Check if ULP0 fast variant has been requested. */ + cmp tmp2, #AT91_PM_ULP0_FAST + bne 0f + + /* Set highest prescaler for power saving */ + ldr tmp1, [pmc, tmp3] + bic tmp1, tmp1, #AT91_PMC_PRES + orr tmp1, tmp1, #AT91_PMC_PRES_64 + str tmp1, [pmc, tmp3] + wait_mckrdy + b 1f +0: /* Turn off the crystal oscillator */ ldr tmp1, [pmc, #AT91_CKGR_MOR] bic tmp1, tmp1, #AT91_PMC_MOSCEN @@ -192,7 +207,18 @@ ENDPROC(at91_backup_mode) /* Wait for interrupt */ 1: at91_cpu_idle - /* Restore RC oscillator state */ + /* Check if ULP0 fast variant has been requested. */ + cmp tmp2, #AT91_PM_ULP0_FAST + bne 5f + + /* Set lowest prescaler for fast resume. */ + ldr tmp1, [pmc, tmp3] + bic tmp1, tmp1, #AT91_PMC_PRES + str tmp1, [pmc, tmp3] + wait_mckrdy + b 6f + +5: /* Restore RC oscillator state */ ldr tmp1, .saved_osc_status tst tmp1, #AT91_PMC_MOSCRCS beq 4f @@ -216,6 +242,7 @@ ENDPROC(at91_backup_mode) str tmp1, [pmc, #AT91_CKGR_MOR] wait_moscrdy +6: .endm /** @@ -473,23 +500,29 @@ ENDPROC(at91_backup_mode) ENTRY(at91_ulp_mode) ldr pmc, .pmc_base ldr tmp2, .mckr_offset + ldr tmp3, .pm_mode /* Save Master clock setting */ ldr tmp1, [pmc, tmp2] str tmp1, .saved_mckr /* - * Set the Master clock source to slow clock + * Set master clock source to: + * - MAINCK if using ULP0 fast variant + * - slow clock, otherwise */ bic tmp1, tmp1, #AT91_PMC_CSS + cmp tmp3, #AT91_PM_ULP0_FAST + bne save_mck + orr tmp1, tmp1, #AT91_PMC_CSS_MAIN +save_mck: str tmp1, [pmc, tmp2] wait_mckrdy at91_plla_disable - ldr r0, .pm_mode - cmp r0, #AT91_PM_ULP1 + cmp tmp3, #AT91_PM_ULP1 beq ulp1_mode at91_pm_ulp0_mode diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig index 1df0ee01ee02..ae790908fc74 100644 --- a/arch/arm/mach-bcm/Kconfig +++ b/arch/arm/mach-bcm/Kconfig @@ -208,6 +208,7 @@ config ARCH_BRCMSTB select ARM_GIC select ARM_ERRATA_798181 if SMP select HAVE_ARM_ARCH_TIMER + select BCM7038_L1_IRQ select BRCMSTB_L2_IRQ select BCM7120_L2_IRQ select ARCH_HAS_HOLES_MEMORYMODEL diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c index 1076886938b6..a20ba12d876c 100644 --- a/arch/arm/mach-davinci/board-da830-evm.c +++ b/arch/arm/mach-davinci/board-da830-evm.c @@ -306,7 +306,7 @@ static struct davinci_nand_pdata da830_evm_nand_pdata = { .core_chipsel = 1, .parts = da830_evm_nand_partitions, .nr_parts = ARRAY_SIZE(da830_evm_nand_partitions), - .ecc_mode = NAND_ECC_HW, + .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST, .ecc_bits = 4, .bbt_options = NAND_BBT_USE_FLASH, .bbt_td = &da830_evm_nand_bbt_main_descr, diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c index 6751292e5f8f..428012687a80 100644 --- a/arch/arm/mach-davinci/board-da850-evm.c +++ b/arch/arm/mach-davinci/board-da850-evm.c @@ -239,7 +239,7 @@ static struct davinci_nand_pdata da850_evm_nandflash_data = { .core_chipsel = 1, .parts = da850_evm_nandflash_partition, .nr_parts = ARRAY_SIZE(da850_evm_nandflash_partition), - .ecc_mode = NAND_ECC_HW, + .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST, .ecc_bits = 4, .bbt_options = NAND_BBT_USE_FLASH, .timing = &da850_evm_nandflash_timing, diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c index 5113273fda69..3c5a9e3c128a 100644 --- a/arch/arm/mach-davinci/board-dm355-evm.c +++ b/arch/arm/mach-davinci/board-dm355-evm.c @@ -82,7 +82,7 @@ static struct davinci_nand_pdata davinci_nand_data = { .mask_chipsel = BIT(14), .parts = davinci_nand_partitions, .nr_parts = ARRAY_SIZE(davinci_nand_partitions), - .ecc_mode = NAND_ECC_HW, + .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST, .bbt_options = NAND_BBT_USE_FLASH, .ecc_bits = 4, }; diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-davinci/board-dm355-leopard.c index b9e9950dd300..e475b2113e70 100644 --- a/arch/arm/mach-davinci/board-dm355-leopard.c +++ b/arch/arm/mach-davinci/board-dm355-leopard.c @@ -76,7 +76,8 @@ static struct davinci_nand_pdata davinci_nand_data = { .mask_chipsel = BIT(14), .parts = davinci_nand_partitions, .nr_parts = ARRAY_SIZE(davinci_nand_partitions), - .ecc_mode = NAND_ECC_HW_SYNDROME, + .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST, + .ecc_placement = NAND_ECC_PLACEMENT_INTERLEAVED, .ecc_bits = 4, .bbt_options = NAND_BBT_USE_FLASH, }; diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c index 2328b15ac067..bdf31eb77620 100644 --- a/arch/arm/mach-davinci/board-dm365-evm.c +++ b/arch/arm/mach-davinci/board-dm365-evm.c @@ -146,7 +146,7 @@ static struct davinci_nand_pdata davinci_nand_data = { .mask_chipsel = BIT(14), .parts = davinci_nand_partitions, .nr_parts = ARRAY_SIZE(davinci_nand_partitions), - .ecc_mode = NAND_ECC_HW, + .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST, .bbt_options = NAND_BBT_USE_FLASH, .ecc_bits = 4, }; diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c index a5d3708fedf6..7755cccec550 100644 --- a/arch/arm/mach-davinci/board-dm644x-evm.c +++ b/arch/arm/mach-davinci/board-dm644x-evm.c @@ -162,7 +162,7 @@ static struct davinci_nand_pdata davinci_evm_nandflash_data = { .core_chipsel = 0, .parts = davinci_evm_nandflash_partition, .nr_parts = ARRAY_SIZE(davinci_evm_nandflash_partition), - .ecc_mode = NAND_ECC_HW, + .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST, .ecc_bits = 1, .bbt_options = NAND_BBT_USE_FLASH, .timing = &davinci_evm_nandflash_timing, @@ -548,8 +548,7 @@ static const struct property_entry eeprom_properties[] = { */ static struct i2c_client *dm6446evm_msp; -static int dm6446evm_msp_probe(struct i2c_client *client, - const struct i2c_device_id *id) +static int dm6446evm_msp_probe(struct i2c_client *client) { dm6446evm_msp = client; return 0; @@ -569,7 +568,7 @@ static const struct i2c_device_id dm6446evm_msp_ids[] = { static struct i2c_driver dm6446evm_msp_driver = { .driver.name = "dm6446evm_msp", .id_table = dm6446evm_msp_ids, - .probe = dm6446evm_msp_probe, + .probe_new = dm6446evm_msp_probe, .remove = dm6446evm_msp_remove, }; diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c index dd7d60f4139a..952ddabc743e 100644 --- a/arch/arm/mach-davinci/board-dm646x-evm.c +++ b/arch/arm/mach-davinci/board-dm646x-evm.c @@ -91,7 +91,7 @@ static struct davinci_nand_pdata davinci_nand_data = { .mask_ale = 0x40000, .parts = davinci_nand_partitions, .nr_parts = ARRAY_SIZE(davinci_nand_partitions), - .ecc_mode = NAND_ECC_HW, + .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST, .ecc_bits = 1, .options = 0, }; @@ -160,8 +160,7 @@ static struct platform_device davinci_aemif_device = { #define DM646X_EVM_ATA_PWD BIT(1) /* CPLD Register 0 Client: used for I/O Control */ -static int cpld_reg0_probe(struct i2c_client *client, - const struct i2c_device_id *id) +static int cpld_reg0_probe(struct i2c_client *client) { if (HAS_ATA) { u8 data; @@ -197,7 +196,7 @@ static const struct i2c_device_id cpld_reg_ids[] = { static struct i2c_driver dm6467evm_cpld_driver = { .driver.name = "cpld_reg0", .id_table = cpld_reg_ids, - .probe = cpld_reg0_probe, + .probe_new = cpld_reg0_probe, }; /* LEDS */ @@ -397,8 +396,7 @@ static struct snd_platform_data dm646x_evm_snd_data[] = { #ifdef CONFIG_I2C static struct i2c_client *cpld_client; -static int cpld_video_probe(struct i2c_client *client, - const struct i2c_device_id *id) +static int cpld_video_probe(struct i2c_client *client) { cpld_client = client; return 0; @@ -419,7 +417,7 @@ static struct i2c_driver cpld_video_driver = { .driver = { .name = "cpld_video", }, - .probe = cpld_video_probe, + .probe_new = cpld_video_probe, .remove = cpld_video_remove, .id_table = cpld_video_id, }; diff --git a/arch/arm/mach-davinci/board-mityomapl138.c b/arch/arm/mach-davinci/board-mityomapl138.c index 3382b93d9a2a..5205008c8061 100644 --- a/arch/arm/mach-davinci/board-mityomapl138.c +++ b/arch/arm/mach-davinci/board-mityomapl138.c @@ -432,7 +432,7 @@ static struct davinci_nand_pdata mityomapl138_nandflash_data = { .core_chipsel = 1, .parts = mityomapl138_nandflash_partition, .nr_parts = ARRAY_SIZE(mityomapl138_nandflash_partition), - .ecc_mode = NAND_ECC_HW, + .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST, .bbt_options = NAND_BBT_USE_FLASH, .options = NAND_BUSWIDTH_16, .ecc_bits = 1, /* 4 bit mode is not supported with 16 bit NAND */ diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c index 6cf46bbc7e1d..b4843f68bb57 100644 --- a/arch/arm/mach-davinci/board-neuros-osd2.c +++ b/arch/arm/mach-davinci/board-neuros-osd2.c @@ -90,7 +90,7 @@ static struct davinci_nand_pdata davinci_ntosd2_nandflash_data = { .core_chipsel = 0, .parts = davinci_ntosd2_nandflash_partition, .nr_parts = ARRAY_SIZE(davinci_ntosd2_nandflash_partition), - .ecc_mode = NAND_ECC_HW, + .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST, .ecc_bits = 1, .bbt_options = NAND_BBT_USE_FLASH, }; diff --git a/arch/arm/mach-davinci/board-omapl138-hawk.c b/arch/arm/mach-davinci/board-omapl138-hawk.c index 6c79039002c9..88df8011a4e6 100644 --- a/arch/arm/mach-davinci/board-omapl138-hawk.c +++ b/arch/arm/mach-davinci/board-omapl138-hawk.c @@ -206,7 +206,7 @@ static struct davinci_nand_pdata omapl138_hawk_nandflash_data = { .core_chipsel = 1, .parts = omapl138_hawk_nandflash_partition, .nr_parts = ARRAY_SIZE(omapl138_hawk_nandflash_partition), - .ecc_mode = NAND_ECC_HW, + .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST, .ecc_bits = 4, .bbt_options = NAND_BBT_USE_FLASH, .options = NAND_BUSWIDTH_16, diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index f185cd3d4c62..d2d249706ebb 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -24,7 +24,6 @@ menuconfig ARCH_EXYNOS select HAVE_ARM_ARCH_TIMER if ARCH_EXYNOS5 select HAVE_ARM_SCU if SMP select HAVE_S3C2410_I2C if I2C - select HAVE_S3C2410_WATCHDOG if WATCHDOG select HAVE_S3C_RTC if RTC_CLASS select PINCTRL select PINCTRL_EXYNOS diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile index 0fd3fcf8bfb0..53fa363c8e44 100644 --- a/arch/arm/mach-exynos/Makefile +++ b/arch/arm/mach-exynos/Makefile @@ -3,10 +3,6 @@ # Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. # http://www.samsung.com/ -ccflags-$(CONFIG_ARCH_MULTIPLATFORM) += -I$(srctree)/$(src)/include -I$(srctree)/arch/arm/plat-samsung/include - -# Core - obj-$(CONFIG_ARCH_EXYNOS) += exynos.o exynos-smc.o firmware.o obj-$(CONFIG_EXYNOS_CPU_SUSPEND) += pm.o sleep.o diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h index afd988a92836..29eb075b24a4 100644 --- a/arch/arm/mach-exynos/common.h +++ b/arch/arm/mach-exynos/common.h @@ -24,12 +24,12 @@ #define EXYNOS5800_SOC_ID 0xE5422000 #define EXYNOS5_SOC_MASK 0xFFFFF000 -extern unsigned long samsung_cpu_id; +extern unsigned long exynos_cpu_id; #define IS_SAMSUNG_CPU(name, id, mask) \ static inline int is_samsung_##name(void) \ { \ - return ((samsung_cpu_id & mask) == (id & mask)); \ + return ((exynos_cpu_id & mask) == (id & mask)); \ } IS_SAMSUNG_CPU(exynos3250, EXYNOS3250_SOC_ID, EXYNOS3_SOC_MASK) @@ -147,7 +147,7 @@ extern struct cpuidle_exynos_data cpuidle_coupled_exynos_data; extern void exynos_set_delayed_reset_assertion(bool enable); -extern unsigned int samsung_rev(void); +extern unsigned int exynos_rev(void); extern void exynos_core_restart(u32 core_id); extern int exynos_set_boot_addr(u32 core_id, unsigned long boot_addr); extern int exynos_get_boot_addr(u32 core_id, unsigned long *boot_addr); diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c index 36c37444485a..700763e07083 100644 --- a/arch/arm/mach-exynos/exynos.c +++ b/arch/arm/mach-exynos/exynos.c @@ -19,11 +19,12 @@ #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <mach/map.h> -#include <plat/cpu.h> - #include "common.h" +#define S3C_ADDR_BASE 0xF6000000 +#define S3C_ADDR(x) ((void __iomem __force *)S3C_ADDR_BASE + (x)) +#define S5P_VA_CHIPID S3C_ADDR(0x02000000) + static struct platform_device exynos_cpuidle = { .name = "exynos_cpuidle", #ifdef CONFIG_ARM_EXYNOS_CPUIDLE @@ -36,6 +37,14 @@ void __iomem *sysram_base_addr __ro_after_init; phys_addr_t sysram_base_phys __ro_after_init; void __iomem *sysram_ns_base_addr __ro_after_init; +unsigned long exynos_cpu_id; +static unsigned int exynos_cpu_rev; + +unsigned int exynos_rev(void) +{ + return exynos_cpu_rev; +} + void __init exynos_sysram_init(void) { struct device_node *node; @@ -86,7 +95,11 @@ static void __init exynos_init_io(void) of_scan_flat_dt(exynos_fdt_map_chipid, NULL); /* detect cpu id and rev. */ - s5p_init_cpu(S5P_VA_CHIPID); + exynos_cpu_id = readl_relaxed(S5P_VA_CHIPID); + exynos_cpu_rev = exynos_cpu_id & 0xFF; + + pr_info("Samsung CPU ID: 0x%08lx\n", exynos_cpu_id); + } /* @@ -193,8 +206,8 @@ static void __init exynos_dt_fixup(void) } DT_MACHINE_START(EXYNOS_DT, "Samsung Exynos (Flattened Device Tree)") - .l2c_aux_val = 0x3c400000, - .l2c_aux_mask = 0xc20fffff, + .l2c_aux_val = 0x38400000, + .l2c_aux_mask = 0xc60fffff, .smp = smp_ops(exynos_smp_ops), .map_io = exynos_init_io, .init_early = exynos_firmware_init, diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h deleted file mode 100644 index 8d58faa54ff7..000000000000 --- a/arch/arm/mach-exynos/include/mach/map.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com/ - * - * Exynos - Memory map definitions - */ - -#ifndef __ASM_ARCH_MAP_H -#define __ASM_ARCH_MAP_H __FILE__ - -#include <plat/map-base.h> - -#include <plat/map-s5p.h> - -#define EXYNOS_PA_CHIPID 0x10000000 - -#endif /* __ASM_ARCH_MAP_H */ diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c index 0cbbae8bf1f8..d7fedbb2eefe 100644 --- a/arch/arm/mach-exynos/platsmp.c +++ b/arch/arm/mach-exynos/platsmp.c @@ -22,8 +22,6 @@ #include <asm/smp_scu.h> #include <asm/firmware.h> -#include <mach/map.h> - #include "common.h" extern void exynos4_secondary_startup(void); @@ -188,7 +186,7 @@ void exynos_scu_enable(void) static void __iomem *cpu_boot_reg_base(void) { - if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1) + if (soc_is_exynos4210() && exynos_rev() == EXYNOS4210_REV_1_1) return pmu_base_addr + S5P_INFORM5; return sysram_base_addr; } diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c index 78af34cc89cc..30f4e55bf39e 100644 --- a/arch/arm/mach-exynos/pm.c +++ b/arch/arm/mach-exynos/pm.c @@ -26,18 +26,18 @@ static inline void __iomem *exynos_boot_vector_addr(void) { - if (samsung_rev() == EXYNOS4210_REV_1_1) + if (exynos_rev() == EXYNOS4210_REV_1_1) return pmu_base_addr + S5P_INFORM7; - else if (samsung_rev() == EXYNOS4210_REV_1_0) + else if (exynos_rev() == EXYNOS4210_REV_1_0) return sysram_base_addr + 0x24; return pmu_base_addr + S5P_INFORM0; } static inline void __iomem *exynos_boot_vector_flag(void) { - if (samsung_rev() == EXYNOS4210_REV_1_1) + if (exynos_rev() == EXYNOS4210_REV_1_1) return pmu_base_addr + S5P_INFORM6; - else if (samsung_rev() == EXYNOS4210_REV_1_0) + else if (exynos_rev() == EXYNOS4210_REV_1_0) return sysram_base_addr + 0x20; return pmu_base_addr + S5P_INFORM1; } diff --git a/arch/arm/mach-hisi/Kconfig b/arch/arm/mach-hisi/Kconfig index 3b010fe7c0e9..2e980f834a6a 100644 --- a/arch/arm/mach-hisi/Kconfig +++ b/arch/arm/mach-hisi/Kconfig @@ -1,9 +1,9 @@ # SPDX-License-Identifier: GPL-2.0-only config ARCH_HISI bool "Hisilicon SoC Support" - depends on ARCH_MULTI_V7 + depends on ARCH_MULTI_V7 || ARCH_MULTI_V5 select ARM_AMBA - select ARM_GIC + select ARM_GIC if ARCH_MULTI_V7 select ARM_TIMER_SP804 select POWER_RESET select POWER_RESET_HISI @@ -15,6 +15,7 @@ menu "Hisilicon platform type" config ARCH_HI3xxx bool "Hisilicon Hi36xx family" + depends on ARCH_MULTI_V7 select CACHE_L2X0 select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if SMP @@ -25,6 +26,7 @@ config ARCH_HI3xxx config ARCH_HIP01 bool "Hisilicon HIP01 family" + depends on ARCH_MULTI_V7 select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if SMP select ARM_GLOBAL_TIMER @@ -33,6 +35,7 @@ config ARCH_HIP01 config ARCH_HIP04 bool "Hisilicon HiP04 Cortex A15 family" + depends on ARCH_MULTI_V7 select ARM_ERRATA_798181 if SMP select HAVE_ARM_ARCH_TIMER select MCPM if SMP @@ -43,6 +46,7 @@ config ARCH_HIP04 config ARCH_HIX5HD2 bool "Hisilicon X5HD2 family" + depends on ARCH_MULTI_V7 select CACHE_L2X0 select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if SMP @@ -50,6 +54,14 @@ config ARCH_HIX5HD2 select PINCTRL_SINGLE help Support for Hisilicon HIX5HD2 SoC family + +config ARCH_SD5203 + bool "Hisilicon SD5203 family" + depends on ARCH_MULTI_V5 + select DW_APB_ICTL + help + Support for Hisilicon SD5203 SoC family + endmenu endif diff --git a/arch/arm/mach-imx/3ds_debugboard.c b/arch/arm/mach-imx/3ds_debugboard.c deleted file mode 100644 index 0e018000715a..000000000000 --- a/arch/arm/mach-imx/3ds_debugboard.c +++ /dev/null @@ -1,207 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright (C) 2010 Jason Wang <jason77.wang@gmail.com> - */ - -#include <linux/interrupt.h> -#include <linux/irq.h> -#include <linux/irqdomain.h> -#include <linux/io.h> -#include <linux/platform_device.h> -#include <linux/gpio.h> -#include <linux/module.h> -#include <linux/smsc911x.h> -#include <linux/regulator/machine.h> -#include <linux/regulator/fixed.h> -#include "3ds_debugboard.h" -#include "hardware.h" - -/* LAN9217 ethernet base address */ -#define LAN9217_BASE_ADDR(n) (n + 0x0) -/* External UART */ -#define UARTA_BASE_ADDR(n) (n + 0x8000) -#define UARTB_BASE_ADDR(n) (n + 0x10000) - -#define BOARD_IO_ADDR(n) (n + 0x20000) -/* LED switchs */ -#define LED_SWITCH_REG 0x00 -/* buttons */ -#define SWITCH_BUTTONS_REG 0x08 -/* status, interrupt */ -#define INTR_STATUS_REG 0x10 -#define INTR_MASK_REG 0x38 -#define INTR_RESET_REG 0x20 -/* magic word for debug CPLD */ -#define MAGIC_NUMBER1_REG 0x40 -#define MAGIC_NUMBER2_REG 0x48 -/* CPLD code version */ -#define CPLD_CODE_VER_REG 0x50 -/* magic word for debug CPLD */ -#define MAGIC_NUMBER3_REG 0x58 -/* module reset register*/ -#define MODULE_RESET_REG 0x60 -/* CPU ID and Personality ID */ -#define MCU_BOARD_ID_REG 0x68 - -#define MXC_MAX_EXP_IO_LINES 16 - -/* interrupts like external uart , external ethernet etc*/ -#define EXPIO_INT_ENET 0 -#define EXPIO_INT_XUART_A 1 -#define EXPIO_INT_XUART_B 2 -#define EXPIO_INT_BUTTON_A 3 -#define EXPIO_INT_BUTTON_B 4 - -static void __iomem *brd_io; -static struct irq_domain *domain; - -static struct resource smsc911x_resources[] = { - { - .flags = IORESOURCE_MEM, - } , { - .flags = IORESOURCE_IRQ, - }, -}; - -static struct smsc911x_platform_config smsc911x_config = { - .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, - .flags = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY, -}; - -static struct platform_device smsc_lan9217_device = { - .name = "smsc911x", - .id = -1, - .dev = { - .platform_data = &smsc911x_config, - }, - .num_resources = ARRAY_SIZE(smsc911x_resources), - .resource = smsc911x_resources, -}; - -static void mxc_expio_irq_handler(struct irq_desc *desc) -{ - u32 imr_val; - u32 int_valid; - u32 expio_irq; - - /* irq = gpio irq number */ - desc->irq_data.chip->irq_mask(&desc->irq_data); - - imr_val = imx_readw(brd_io + INTR_MASK_REG); - int_valid = imx_readw(brd_io + INTR_STATUS_REG) & ~imr_val; - - expio_irq = 0; - for (; int_valid != 0; int_valid >>= 1, expio_irq++) { - if ((int_valid & 1) == 0) - continue; - generic_handle_irq(irq_find_mapping(domain, expio_irq)); - } - - desc->irq_data.chip->irq_ack(&desc->irq_data); - desc->irq_data.chip->irq_unmask(&desc->irq_data); -} - -/* - * Disable an expio pin's interrupt by setting the bit in the imr. - * Irq is an expio virtual irq number - */ -static void expio_mask_irq(struct irq_data *d) -{ - u16 reg; - u32 expio = d->hwirq; - - reg = imx_readw(brd_io + INTR_MASK_REG); - reg |= (1 << expio); - imx_writew(reg, brd_io + INTR_MASK_REG); -} - -static void expio_ack_irq(struct irq_data *d) -{ - u32 expio = d->hwirq; - - imx_writew(1 << expio, brd_io + INTR_RESET_REG); - imx_writew(0, brd_io + INTR_RESET_REG); - expio_mask_irq(d); -} - -static void expio_unmask_irq(struct irq_data *d) -{ - u16 reg; - u32 expio = d->hwirq; - - reg = imx_readw(brd_io + INTR_MASK_REG); - reg &= ~(1 << expio); - imx_writew(reg, brd_io + INTR_MASK_REG); -} - -static struct irq_chip expio_irq_chip = { - .irq_ack = expio_ack_irq, - .irq_mask = expio_mask_irq, - .irq_unmask = expio_unmask_irq, -}; - -static struct regulator_consumer_supply dummy_supplies[] = { - REGULATOR_SUPPLY("vdd33a", "smsc911x"), - REGULATOR_SUPPLY("vddvario", "smsc911x"), -}; - -int __init mxc_expio_init(u32 base, u32 intr_gpio) -{ - u32 p_irq = gpio_to_irq(intr_gpio); - int irq_base; - int i; - - brd_io = ioremap(BOARD_IO_ADDR(base), SZ_4K); - if (brd_io == NULL) - return -ENOMEM; - - if ((imx_readw(brd_io + MAGIC_NUMBER1_REG) != 0xAAAA) || - (imx_readw(brd_io + MAGIC_NUMBER2_REG) != 0x5555) || - (imx_readw(brd_io + MAGIC_NUMBER3_REG) != 0xCAFE)) { - pr_info("3-Stack Debug board not detected\n"); - iounmap(brd_io); - brd_io = NULL; - return -ENODEV; - } - - pr_info("3-Stack Debug board detected, rev = 0x%04X\n", - readw(brd_io + CPLD_CODE_VER_REG)); - - /* - * Configure INT line as GPIO input - */ - gpio_request(intr_gpio, "expio_pirq"); - gpio_direction_input(intr_gpio); - - /* disable the interrupt and clear the status */ - imx_writew(0, brd_io + INTR_MASK_REG); - imx_writew(0xFFFF, brd_io + INTR_RESET_REG); - imx_writew(0, brd_io + INTR_RESET_REG); - imx_writew(0x1F, brd_io + INTR_MASK_REG); - - irq_base = irq_alloc_descs(-1, 0, MXC_MAX_EXP_IO_LINES, numa_node_id()); - WARN_ON(irq_base < 0); - - domain = irq_domain_add_legacy(NULL, MXC_MAX_EXP_IO_LINES, irq_base, 0, - &irq_domain_simple_ops, NULL); - WARN_ON(!domain); - - for (i = irq_base; i < irq_base + MXC_MAX_EXP_IO_LINES; i++) { - irq_set_chip_and_handler(i, &expio_irq_chip, handle_level_irq); - irq_clear_status_flags(i, IRQ_NOREQUEST); - } - irq_set_irq_type(p_irq, IRQF_TRIGGER_LOW); - irq_set_chained_handler(p_irq, mxc_expio_irq_handler); - - /* Register Lan device on the debugboard */ - regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); - - smsc911x_resources[0].start = LAN9217_BASE_ADDR(base); - smsc911x_resources[0].end = LAN9217_BASE_ADDR(base) + 0x100 - 1; - smsc911x_resources[1].start = irq_find_mapping(domain, EXPIO_INT_ENET); - smsc911x_resources[1].end = irq_find_mapping(domain, EXPIO_INT_ENET); - platform_device_register(&smsc_lan9217_device); - - return 0; -} diff --git a/arch/arm/mach-imx/3ds_debugboard.h b/arch/arm/mach-imx/3ds_debugboard.h deleted file mode 100644 index a4d04d099c61..000000000000 --- a/arch/arm/mach-imx/3ds_debugboard.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -#ifndef __ASM_ARCH_MXC_3DS_DB_H__ -#define __ASM_ARCH_MXC_3DS_DB_H__ - -extern int __init mxc_expio_init(u32 base, u32 intr_gpio); - -#endif /* __ASM_ARCH_MXC_3DS_DB_H__ */ diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index e7d7b90e2cf8..52902782cc5f 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -47,371 +47,26 @@ config HAVE_IMX_SRC def_bool y if SMP select ARCH_HAS_RESET_CONTROLLER -config IMX_HAVE_IOMUX_V1 - bool +if ARCH_MULTI_V6 -config ARCH_MXC_IOMUX_V3 - bool - -config SOC_IMX21 - bool - select CPU_ARM926T - select IMX_HAVE_IOMUX_V1 - select MXC_AVIC - -config SOC_IMX27 - bool - select CPU_ARM926T - select IMX_HAVE_IOMUX_V1 - select MXC_AVIC - select PINCTRL_IMX27 +comment "ARM1136 platforms" config SOC_IMX31 - bool + bool "i.MX31 support" select CPU_V6 select MXC_AVIC + help + This enables support for Freescale i.MX31 processor config SOC_IMX35 - bool - select ARCH_MXC_IOMUX_V3 + bool "i.MX35 support" select MXC_AVIC select PINCTRL_IMX35 - -if ARCH_MULTI_V5 - -comment "MX21 platforms:" - -config MACH_MX21ADS - bool "MX21ADS platform" - select IMX_HAVE_PLATFORM_IMX_FB - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_MXC_MMC - select IMX_HAVE_PLATFORM_MXC_NAND - select SOC_IMX21 - help - Include support for MX21ADS platform. This includes specific - configurations for the board and its peripherals. - -comment "MX27 platforms:" - -config MACH_MX27ADS - bool "MX27ADS platform" - select IMX_HAVE_PLATFORM_IMX_FB - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_MXC_MMC - select IMX_HAVE_PLATFORM_MXC_NAND - select IMX_HAVE_PLATFORM_MXC_W1 - select SOC_IMX27 - help - Include support for MX27ADS platform. This includes specific - configurations for the board and its peripherals. - -config MACH_MX27_3DS - bool "MX27PDK platform" - select IMX_HAVE_PLATFORM_FSL_USB2_UDC - select IMX_HAVE_PLATFORM_IMX2_WDT - select IMX_HAVE_PLATFORM_IMX_FB - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_KEYPAD - select IMX_HAVE_PLATFORM_IMX_SSI - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_MX2_CAMERA - select IMX_HAVE_PLATFORM_MXC_EHCI - select IMX_HAVE_PLATFORM_MXC_MMC - select IMX_HAVE_PLATFORM_SPI_IMX - select MXC_DEBUG_BOARD - select USB_ULPI_VIEWPORT if USB_ULPI - select SOC_IMX27 - help - Include support for MX27PDK platform. This includes specific - configurations for the board and its peripherals. - -config MACH_IMX27_VISSTRIM_M10 - bool "Vista Silicon i.MX27 Visstrim_m10" - select IMX_HAVE_PLATFORM_GPIO_KEYS - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_SSI - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_MX2_CAMERA - select IMX_HAVE_PLATFORM_MX2_EMMA - select IMX_HAVE_PLATFORM_MXC_EHCI - select IMX_HAVE_PLATFORM_MXC_MMC - select LEDS_GPIO_REGISTER - select SOC_IMX27 - help - Include support for Visstrim_m10 platform and its different variants. - This includes specific configurations for the board and its - peripherals. - -config MACH_PCA100 - bool "Phytec phyCARD-s (pca100)" - select IMX_HAVE_PLATFORM_FSL_USB2_UDC - select IMX_HAVE_PLATFORM_IMX2_WDT - select IMX_HAVE_PLATFORM_IMX_FB - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_SSI - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_MXC_EHCI - select IMX_HAVE_PLATFORM_MXC_MMC - select IMX_HAVE_PLATFORM_MXC_NAND - select IMX_HAVE_PLATFORM_MXC_W1 - select IMX_HAVE_PLATFORM_SPI_IMX - select USB_ULPI_VIEWPORT if USB_ULPI - select SOC_IMX27 - help - Include support for phyCARD-s (aka pca100) platform. This - includes specific configurations for the module and its peripherals. - -config MACH_IMX27_DT - bool "Support i.MX27 platforms from device tree" - select SOC_IMX27 - help - Include support for Freescale i.MX27 based platforms - using the device tree for discovery - -endif - -if ARCH_MULTI_V6 - -comment "MX31 platforms:" - -config MACH_MX31ADS - bool "Support MX31ADS platforms" - default y - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_SSI - select IMX_HAVE_PLATFORM_IMX_UART - select SOC_IMX31 - help - Include support for MX31ADS platform. This includes specific - configurations for the board and its peripherals. - -config MACH_MX31ADS_WM1133_EV1 - bool "Support Wolfson Microelectronics 1133-EV1 module" - depends on MACH_MX31ADS - depends on MFD_WM8350_I2C - depends on REGULATOR_WM8350 = y help - Include support for the Wolfson Microelectronics 1133-EV1 PMU - and audio module for the MX31ADS platform. - -config MACH_MX31LILLY - bool "Support MX31 LILLY-1131 platforms (INCO startec)" - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_IPU_CORE - select IMX_HAVE_PLATFORM_MXC_EHCI - select IMX_HAVE_PLATFORM_MXC_MMC - select IMX_HAVE_PLATFORM_SPI_IMX - select USB_ULPI_VIEWPORT if USB_ULPI - select SOC_IMX31 - help - Include support for mx31 based LILLY1131 modules. This includes - specific configurations for the board and its peripherals. - -config MACH_MX31LITE - bool "Support MX31 LITEKIT (LogicPD)" - select IMX_HAVE_PLATFORM_IMX2_WDT - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_MXC_EHCI - select IMX_HAVE_PLATFORM_MXC_MMC - select IMX_HAVE_PLATFORM_MXC_NAND - select IMX_HAVE_PLATFORM_MXC_RTC - select IMX_HAVE_PLATFORM_SPI_IMX - select LEDS_GPIO_REGISTER - select USB_ULPI_VIEWPORT if USB_ULPI - select SOC_IMX31 - help - Include support for MX31 LITEKIT platform. This includes specific - configurations for the board and its peripherals. - -config MACH_PCM037 - bool "Support Phytec pcm037 (i.MX31) platforms" - select IMX_HAVE_PLATFORM_FSL_USB2_UDC - select IMX_HAVE_PLATFORM_IMX2_WDT - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_IPU_CORE - select IMX_HAVE_PLATFORM_MXC_EHCI - select IMX_HAVE_PLATFORM_MXC_MMC - select IMX_HAVE_PLATFORM_MXC_NAND - select IMX_HAVE_PLATFORM_MXC_W1 - select USB_ULPI_VIEWPORT if USB_ULPI - select SOC_IMX31 - help - Include support for Phytec pcm037 platform. This includes - specific configurations for the board and its peripherals. - -config MACH_PCM037_EET - bool "Support pcm037 EET board extensions" - depends on MACH_PCM037 - select IMX_HAVE_PLATFORM_GPIO_KEYS - select IMX_HAVE_PLATFORM_SPI_IMX - help - Add support for PCM037 EET baseboard extensions. If you are using the - OLED display with EET, use "video=mx3fb:CMEL-OLED" kernel - command-line parameter. - -config MACH_MX31_3DS - bool "Support MX31PDK (3DS)" - select IMX_HAVE_PLATFORM_FSL_USB2_UDC - select IMX_HAVE_PLATFORM_IMX2_WDT - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_KEYPAD - select IMX_HAVE_PLATFORM_IMX_SSI - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_IPU_CORE - select IMX_HAVE_PLATFORM_MXC_EHCI - select IMX_HAVE_PLATFORM_MXC_MMC - select IMX_HAVE_PLATFORM_MXC_NAND - select IMX_HAVE_PLATFORM_SPI_IMX - select MXC_DEBUG_BOARD - select USB_ULPI_VIEWPORT if USB_ULPI - select SOC_IMX31 - help - Include support for MX31PDK (3DS) platform. This includes specific - configurations for the board and its peripherals. - -config MACH_MX31_3DS_MXC_NAND_USE_BBT - bool "Make the MXC NAND driver use the in flash Bad Block Table" - depends on MACH_MX31_3DS - depends on MTD_NAND_MXC - help - Enable this if you want that the MXC NAND driver uses the in flash - Bad Block Table to know what blocks are bad instead of scanning the - entire flash looking for bad block markers. - -config MACH_MX31MOBOARD - bool "Support mx31moboard platforms (EPFL Mobots group)" - select IMX_HAVE_PLATFORM_FSL_USB2_UDC - select IMX_HAVE_PLATFORM_IMX2_WDT - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_SSI - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_IPU_CORE - select IMX_HAVE_PLATFORM_MXC_EHCI - select IMX_HAVE_PLATFORM_MXC_MMC - select IMX_HAVE_PLATFORM_SPI_IMX - select LEDS_GPIO_REGISTER - select USB_ULPI_VIEWPORT if USB_ULPI - select SOC_IMX31 - help - Include support for mx31moboard platform. This includes specific - configurations for the board and its peripherals. - -config MACH_QONG - bool "Support Dave/DENX QongEVB-LITE platform" - select IMX_HAVE_PLATFORM_IMX2_WDT - select IMX_HAVE_PLATFORM_IMX_UART - select SOC_IMX31 - help - Include support for Dave/DENX QongEVB-LITE platform. This includes - specific configurations for the board and its peripherals. - -config MACH_ARMADILLO5X0 - bool "Support Atmark Armadillo-500 Development Base Board" - select IMX_HAVE_PLATFORM_GPIO_KEYS - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_IPU_CORE - select IMX_HAVE_PLATFORM_MXC_EHCI - select IMX_HAVE_PLATFORM_MXC_MMC - select IMX_HAVE_PLATFORM_MXC_NAND - select USB_ULPI_VIEWPORT if USB_ULPI - select SOC_IMX31 - help - Include support for Atmark Armadillo-500 platform. This includes - specific configurations for the board and its peripherals. - -config MACH_KZM_ARM11_01 - bool "Support KZM-ARM11-01(Kyoto Microcomputer)" - select IMX_HAVE_PLATFORM_IMX_UART - select SOC_IMX31 - help - Include support for KZM-ARM11-01. This includes specific - configurations for the board and its peripherals. - -config MACH_BUG - bool "Support Buglabs BUGBase platform" - default y - select IMX_HAVE_PLATFORM_IMX_UART - select SOC_IMX31 - help - Include support for BUGBase 1.3 platform. This includes specific - configurations for the board and its peripherals. - -config MACH_IMX31_DT - bool "Support i.MX31 platforms from device tree" - select SOC_IMX31 - help - Include support for Freescale i.MX31 based platforms - using the device tree for discovery. - -comment "MX35 platforms:" - -config MACH_IMX35_DT - bool "Support i.MX35 platforms from device tree" - select SOC_IMX35 - help - Include support for Freescale i.MX35 based platforms - using the device tree for discovery. - -config MACH_PCM043 - bool "Support Phytec pcm043 (i.MX35) platforms" - select IMX_HAVE_PLATFORM_FLEXCAN - select IMX_HAVE_PLATFORM_FSL_USB2_UDC - select IMX_HAVE_PLATFORM_IMX2_WDT - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_SSI - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_IPU_CORE - select IMX_HAVE_PLATFORM_MXC_EHCI - select IMX_HAVE_PLATFORM_MXC_NAND - select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX - select USB_ULPI_VIEWPORT if USB_ULPI - select SOC_IMX35 - help - Include support for Phytec pcm043 platform. This includes - specific configurations for the board and its peripherals. - -config MACH_MX35_3DS - bool "Support MX35PDK platform" - select IMX_HAVE_PLATFORM_FSL_USB2_UDC - select IMX_HAVE_PLATFORM_IMX2_WDT - select IMX_HAVE_PLATFORM_IMX_FB - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_IPU_CORE - select IMX_HAVE_PLATFORM_MXC_EHCI - select IMX_HAVE_PLATFORM_MXC_NAND - select IMX_HAVE_PLATFORM_MXC_RTC - select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX - select MXC_DEBUG_BOARD - select SOC_IMX35 - help - Include support for MX35PDK platform. This includes specific - configurations for the board and its peripherals. - -config MACH_VPR200 - bool "Support VPR200 platform" - select IMX_HAVE_PLATFORM_FSL_USB2_UDC - select IMX_HAVE_PLATFORM_GPIO_KEYS - select IMX_HAVE_PLATFORM_IMX2_WDT - select IMX_HAVE_PLATFORM_IMX_I2C - select IMX_HAVE_PLATFORM_IMX_UART - select IMX_HAVE_PLATFORM_IPU_CORE - select IMX_HAVE_PLATFORM_MXC_EHCI - select IMX_HAVE_PLATFORM_MXC_NAND - select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX - select SOC_IMX35 - help - Include support for VPR200 platform. This includes specific - configurations for the board and its peripherals. + This enables support for Freescale i.MX31 processor endif -comment "Device tree only" - if ARCH_MULTI_V4T config SOC_IMX1 @@ -428,12 +83,20 @@ if ARCH_MULTI_V5 config SOC_IMX25 bool "i.MX25 support" - select ARCH_MXC_IOMUX_V3 select CPU_ARM926T select MXC_AVIC select PINCTRL_IMX25 help This enables support for Freescale i.MX25 processor + +config SOC_IMX27 + bool "i.MX27 support" + select CPU_ARM926T + select MXC_AVIC + select PINCTRL_IMX27 + help + This enables support for Freescale i.MX27 processor + endif if ARCH_MULTI_V7 @@ -541,10 +204,10 @@ config SOC_LS1021A endif -comment "Cortex-A/Cortex-M asymmetric multiprocessing platforms" - if ARCH_MULTI_V7 || ARM_SINGLE_ARMV7M +comment "Cortex-A/Cortex-M asymmetric multiprocessing platforms" + config SOC_IMX7D_CA7 bool select ARM_GIC @@ -607,6 +270,4 @@ endchoice endif -source "arch/arm/mach-imx/devices/Kconfig" - endif diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index e7364e6c8c6b..9cebd360d58e 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -1,22 +1,16 @@ # SPDX-License-Identifier: GPL-2.0 obj-y := cpu.o system.o irq-common.o -obj-$(CONFIG_SOC_IMX21) += mm-imx21.o - obj-$(CONFIG_SOC_IMX25) += cpu-imx25.o mach-imx25.o pm-imx25.o -obj-$(CONFIG_SOC_IMX27) += cpu-imx27.o pm-imx27.o -obj-$(CONFIG_SOC_IMX27) += mm-imx27.o ehci-imx27.o +obj-$(CONFIG_SOC_IMX27) += cpu-imx27.o pm-imx27.o mach-imx27.o -obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o iomux-imx31.o ehci-imx31.o -obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o ehci-imx35.o +obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o mach-imx31.o +obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o mach-imx35.o imx5-pm-$(CONFIG_PM) += pm-imx5.o obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o $(imx5-pm-y) -obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o -obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o - obj-$(CONFIG_MXC_TZIC) += tzic.o obj-$(CONFIG_MXC_AVIC) += avic.o @@ -37,37 +31,6 @@ obj-y += ssi-fiq.o obj-y += ssi-fiq-ksym.o endif -# i.MX21 based machines -obj-$(CONFIG_MACH_MX21ADS) += mach-mx21ads.o - -# i.MX27 based machines -obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o -obj-$(CONFIG_MACH_MX27_3DS) += mach-mx27_3ds.o -obj-$(CONFIG_MACH_IMX27_VISSTRIM_M10) += mach-imx27_visstrim_m10.o -obj-$(CONFIG_MACH_PCA100) += mach-pca100.o -obj-$(CONFIG_MACH_IMX27_DT) += imx27-dt.o - -# i.MX31 based machines -obj-$(CONFIG_MACH_MX31ADS) += mach-mx31ads.o -obj-$(CONFIG_MACH_MX31LILLY) += mach-mx31lilly.o mx31lilly-db.o -obj-$(CONFIG_MACH_MX31LITE) += mach-mx31lite.o mx31lite-db.o -obj-$(CONFIG_MACH_PCM037) += mach-pcm037.o -obj-$(CONFIG_MACH_PCM037_EET) += mach-pcm037_eet.o -obj-$(CONFIG_MACH_MX31_3DS) += mach-mx31_3ds.o -obj-$(CONFIG_MACH_MX31MOBOARD) += mach-mx31moboard.o mx31moboard-devboard.o \ - mx31moboard-marxbot.o mx31moboard-smartbot.o -obj-$(CONFIG_MACH_QONG) += mach-qong.o -obj-$(CONFIG_MACH_ARMADILLO5X0) += mach-armadillo5x0.o -obj-$(CONFIG_MACH_KZM_ARM11_01) += mach-kzm_arm11_01.o -obj-$(CONFIG_MACH_BUG) += mach-bug.o -obj-$(CONFIG_MACH_IMX31_DT) += imx31-dt.o - -# i.MX35 based machines -obj-$(CONFIG_MACH_PCM043) += mach-pcm043.o -obj-$(CONFIG_MACH_MX35_3DS) += mach-mx35_3ds.o -obj-$(CONFIG_MACH_VPR200) += mach-vpr200.o -obj-$(CONFIG_MACH_IMX35_DT) += imx35-dt.o - obj-$(CONFIG_HAVE_IMX_ANATOP) += anatop.o obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o @@ -105,5 +68,3 @@ obj-$(CONFIG_SOC_IMX53) += mach-imx53.o obj-$(CONFIG_SOC_VF610) += mach-vf610.o obj-$(CONFIG_SOC_LS1021A) += mach-ls1021a.o - -obj-y += devices/ diff --git a/arch/arm/mach-imx/board-mx31lilly.h b/arch/arm/mach-imx/board-mx31lilly.h deleted file mode 100644 index 3508c598c588..000000000000 --- a/arch/arm/mach-imx/board-mx31lilly.h +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (C) 2009 Daniel Mack <daniel@caiaq.de> - * - * Based on code for mobots boards, - * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group - */ - -#ifndef __ASM_ARCH_MXC_BOARD_MX31LILLY_H__ -#define __ASM_ARCH_MXC_BOARD_MX31LILLY_H__ - -#ifndef __ASSEMBLY__ - -enum mx31lilly_boards { - MX31LILLY_NOBOARD = 0, - MX31LILLY_DB = 1, -}; - -/* - * This CPU module needs a baseboard to work. After basic initializing - * its own devices, it calls the baseboard's init function. - */ - -extern void mx31lilly_db_init(void); - -#endif - -#endif /* __ASM_ARCH_MXC_BOARD_MX31LILLY_H__ */ diff --git a/arch/arm/mach-imx/board-mx31lite.h b/arch/arm/mach-imx/board-mx31lite.h deleted file mode 100644 index 7d7c6219b25f..000000000000 --- a/arch/arm/mach-imx/board-mx31lite.h +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright (C) 2009 Daniel Mack <daniel@caiaq.de> - * - * Based on code for mobots boards, - * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group - */ - -#ifndef __ASM_ARCH_MXC_BOARD_MX31LITE_H__ -#define __ASM_ARCH_MXC_BOARD_MX31LITE_H__ - -#ifndef __ASSEMBLY__ - -enum mx31lite_boards { - MX31LITE_NOBOARD = 0, - MX31LITE_DB = 1, -}; - -/* - * This CPU module needs a baseboard to work. After basic initializing - * its own devices, it calls the baseboard's init function. - */ - -extern void mx31lite_db_init(void); - -#endif - -#endif /* __ASM_ARCH_MXC_BOARD_MX31LITE_H__ */ diff --git a/arch/arm/mach-imx/board-mx31moboard.h b/arch/arm/mach-imx/board-mx31moboard.h deleted file mode 100644 index 6f3ff4d4ebc1..000000000000 --- a/arch/arm/mach-imx/board-mx31moboard.h +++ /dev/null @@ -1,30 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group - */ - -#ifndef __ASM_ARCH_MXC_BOARD_MX31MOBOARD_H__ -#define __ASM_ARCH_MXC_BOARD_MX31MOBOARD_H__ - -#ifndef __ASSEMBLY__ - -enum mx31moboard_boards { - MX31NOBOARD = 0, - MX31DEVBOARD = 1, - MX31MARXBOT = 2, - MX31SMARTBOT = 3, - MX31EYEBOT = 4, -}; - -/* - * This CPU module needs a baseboard to work. After basic initializing - * its own devices, it calls the baseboard's init function. - */ - -extern void mx31moboard_devboard_init(void); -extern void mx31moboard_marxbot_init(void); -extern void mx31moboard_smartbot_init(int board); - -#endif - -#endif /* __ASM_ARCH_MXC_BOARD_MX31MOBOARD_H__ */ diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h index 72c3fcc32910..2d76e2c6c99e 100644 --- a/arch/arm/mach-imx/common.h +++ b/arch/arm/mach-imx/common.h @@ -17,29 +17,14 @@ struct device_node; enum mxc_cpu_pwr_mode; struct of_device_id; -void mx21_map_io(void); -void mx27_map_io(void); void mx31_map_io(void); void mx35_map_io(void); void imx21_init_early(void); -void imx27_init_early(void); void imx31_init_early(void); void imx35_init_early(void); void mxc_init_irq(void __iomem *); -void mx21_init_irq(void); -void mx27_init_irq(void); void mx31_init_irq(void); void mx35_init_irq(void); -void imx21_soc_init(void); -void imx27_soc_init(void); -void imx31_soc_init(void); -void imx35_soc_init(void); -int mx21_clocks_init(unsigned long lref, unsigned long fref); -int mx27_clocks_init(unsigned long fref); -int mx31_clocks_init(unsigned long fref); -int mx35_clocks_init(void); -struct platform_device *mxc_register_gpio(char *name, int id, - resource_size_t iobase, resource_size_t iosize, int irq, int irq_high); void mxc_set_cpu_type(unsigned int type); void mxc_restart(enum reboot_mode, const char *); void mxc_arch_reset_init(void __iomem *); diff --git a/arch/arm/mach-imx/cpu-imx27.c b/arch/arm/mach-imx/cpu-imx27.c index a969aa71b60f..bf70e13bbe9e 100644 --- a/arch/arm/mach-imx/cpu-imx27.c +++ b/arch/arm/mach-imx/cpu-imx27.c @@ -9,6 +9,7 @@ */ #include <linux/io.h> +#include <linux/of_address.h> #include <linux/module.h> #include "hardware.h" @@ -17,16 +18,23 @@ static int mx27_cpu_rev = -1; static int mx27_cpu_partnumber; #define SYS_CHIP_ID 0x00 /* The offset of CHIP ID register */ +#define SYSCTRL_OFFSET 0x800 /* Offset from CCM base address */ static int mx27_read_cpu_rev(void) { + void __iomem *ccm_base; + struct device_node *np; u32 val; + + np = of_find_compatible_node(NULL, NULL, "fsl,imx27-ccm"); + ccm_base = of_iomap(np, 0); + BUG_ON(!ccm_base); /* * now we have access to the IO registers. As we need * the silicon revision very early we read it here to * avoid any further hooks */ - val = imx_readl(MX27_IO_ADDRESS(MX27_SYSCTRL_BASE_ADDR + SYS_CHIP_ID)); + val = imx_readl(ccm_base + SYSCTRL_OFFSET + SYS_CHIP_ID); mx27_cpu_partnumber = (int)((val >> 12) & 0xFFFF); diff --git a/arch/arm/mach-imx/cpu-imx31.c b/arch/arm/mach-imx/cpu-imx31.c index 3ee684b71006..b9c24b851d1a 100644 --- a/arch/arm/mach-imx/cpu-imx31.c +++ b/arch/arm/mach-imx/cpu-imx31.c @@ -6,6 +6,7 @@ */ #include <linux/module.h> +#include <linux/of_address.h> #include <linux/io.h> #include "common.h" @@ -32,10 +33,16 @@ static struct { static int mx31_read_cpu_rev(void) { + void __iomem *iim_base; + struct device_node *np; u32 i, srev; + np = of_find_compatible_node(NULL, NULL, "fsl,imx31-iim"); + iim_base = of_iomap(np, 0); + BUG_ON(!iim_base); + /* read SREV register from IIM module */ - srev = imx_readl(MX31_IO_ADDRESS(MX31_IIM_BASE_ADDR + MXC_IIMSREV)); + srev = imx_readl(iim_base + MXC_IIMSREV); srev &= 0xff; for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++) diff --git a/arch/arm/mach-imx/cpu-imx35.c b/arch/arm/mach-imx/cpu-imx35.c index ebb3cdabd506..80e7d8ab9f1b 100644 --- a/arch/arm/mach-imx/cpu-imx35.c +++ b/arch/arm/mach-imx/cpu-imx35.c @@ -5,6 +5,7 @@ * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de> */ #include <linux/module.h> +#include <linux/of_address.h> #include <linux/io.h> #include "hardware.h" @@ -14,9 +15,15 @@ static int mx35_cpu_rev = -1; static int mx35_read_cpu_rev(void) { + void __iomem *iim_base; + struct device_node *np; u32 rev; - rev = imx_readl(MX35_IO_ADDRESS(MX35_IIM_BASE_ADDR + MXC_IIMSREV)); + np = of_find_compatible_node(NULL, NULL, "fsl,imx35-iim"); + iim_base = of_iomap(np, 0); + BUG_ON(!iim_base); + + rev = imx_readl(iim_base + MXC_IIMSREV); switch (rev) { case 0x00: return IMX_CHIP_REVISION_1_0; diff --git a/arch/arm/mach-imx/devices-imx21.h b/arch/arm/mach-imx/devices-imx21.h deleted file mode 100644 index 3679d1de84d4..000000000000 --- a/arch/arm/mach-imx/devices-imx21.h +++ /dev/null @@ -1,56 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2010 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - */ -#include "devices/devices-common.h" - -extern const struct imx_imx21_hcd_data imx21_imx21_hcd_data; -#define imx21_add_imx21_hcd(pdata) \ - imx_add_imx21_hcd(&imx21_imx21_hcd_data, pdata) - -extern const struct imx_imx2_wdt_data imx21_imx2_wdt_data; -#define imx21_add_imx2_wdt() \ - imx_add_imx2_wdt(&imx21_imx2_wdt_data) - -extern const struct imx_imx_fb_data imx21_imx_fb_data; -#define imx21_add_imx_fb(pdata) \ - imx_add_imx_fb(&imx21_imx_fb_data, pdata) - -extern const struct imx_imx_i2c_data imx21_imx_i2c_data; -#define imx21_add_imx_i2c(pdata) \ - imx_add_imx_i2c(&imx21_imx_i2c_data, pdata) - -extern const struct imx_imx_keypad_data imx21_imx_keypad_data; -#define imx21_add_imx_keypad(pdata) \ - imx_add_imx_keypad(&imx21_imx_keypad_data, pdata) - -extern const struct imx_imx_ssi_data imx21_imx_ssi_data[]; -#define imx21_add_imx_ssi(id, pdata) \ - imx_add_imx_ssi(&imx21_imx_ssi_data[id], pdata) - -extern const struct imx_imx_uart_1irq_data imx21_imx_uart_data[]; -#define imx21_add_imx_uart(id, pdata) \ - imx_add_imx_uart_1irq(&imx21_imx_uart_data[id], pdata) -#define imx21_add_imx_uart0(pdata) imx21_add_imx_uart(0, pdata) -#define imx21_add_imx_uart1(pdata) imx21_add_imx_uart(1, pdata) -#define imx21_add_imx_uart2(pdata) imx21_add_imx_uart(2, pdata) -#define imx21_add_imx_uart3(pdata) imx21_add_imx_uart(3, pdata) - -extern const struct imx_mxc_mmc_data imx21_mxc_mmc_data[]; -#define imx21_add_mxc_mmc(id, pdata) \ - imx_add_mxc_mmc(&imx21_mxc_mmc_data[id], pdata) - -extern const struct imx_mxc_nand_data imx21_mxc_nand_data; -#define imx21_add_mxc_nand(pdata) \ - imx_add_mxc_nand(&imx21_mxc_nand_data, pdata) - -extern const struct imx_mxc_w1_data imx21_mxc_w1_data; -#define imx21_add_mxc_w1() \ - imx_add_mxc_w1(&imx21_mxc_w1_data) - -extern const struct imx_spi_imx_data imx21_cspi_data[]; -#define imx21_add_cspi(id, pdata) \ - imx_add_spi_imx(&imx21_cspi_data[id], pdata) -#define imx21_add_spi_imx0(pdata) imx21_add_cspi(0, pdata) -#define imx21_add_spi_imx1(pdata) imx21_add_cspi(1, pdata) diff --git a/arch/arm/mach-imx/devices-imx27.h b/arch/arm/mach-imx/devices-imx27.h deleted file mode 100644 index 583a1d773d68..000000000000 --- a/arch/arm/mach-imx/devices-imx27.h +++ /dev/null @@ -1,86 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2010 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - */ -#include "devices/devices-common.h" - -extern const struct imx_fec_data imx27_fec_data; -#define imx27_add_fec(pdata) \ - imx_add_fec(&imx27_fec_data, pdata) - -extern const struct imx_fsl_usb2_udc_data imx27_fsl_usb2_udc_data; -#define imx27_add_fsl_usb2_udc(pdata) \ - imx_add_fsl_usb2_udc(&imx27_fsl_usb2_udc_data, pdata) - -extern const struct imx_imx27_coda_data imx27_coda_data; -#define imx27_add_coda() \ - imx_add_imx27_coda(&imx27_coda_data) - -extern const struct imx_imx2_wdt_data imx27_imx2_wdt_data; -#define imx27_add_imx2_wdt() \ - imx_add_imx2_wdt(&imx27_imx2_wdt_data) - -extern const struct imx_imx_fb_data imx27_imx_fb_data; -#define imx27_add_imx_fb(pdata) \ - imx_add_imx_fb(&imx27_imx_fb_data, pdata) - -extern const struct imx_imx_i2c_data imx27_imx_i2c_data[]; -#define imx27_add_imx_i2c(id, pdata) \ - imx_add_imx_i2c(&imx27_imx_i2c_data[id], pdata) - -extern const struct imx_imx_keypad_data imx27_imx_keypad_data; -#define imx27_add_imx_keypad(pdata) \ - imx_add_imx_keypad(&imx27_imx_keypad_data, pdata) - -extern const struct imx_imx_ssi_data imx27_imx_ssi_data[]; -#define imx27_add_imx_ssi(id, pdata) \ - imx_add_imx_ssi(&imx27_imx_ssi_data[id], pdata) - -extern const struct imx_imx_uart_1irq_data imx27_imx_uart_data[]; -#define imx27_add_imx_uart(id, pdata) \ - imx_add_imx_uart_1irq(&imx27_imx_uart_data[id], pdata) -#define imx27_add_imx_uart0(pdata) imx27_add_imx_uart(0, pdata) -#define imx27_add_imx_uart1(pdata) imx27_add_imx_uart(1, pdata) -#define imx27_add_imx_uart2(pdata) imx27_add_imx_uart(2, pdata) -#define imx27_add_imx_uart3(pdata) imx27_add_imx_uart(3, pdata) -#define imx27_add_imx_uart4(pdata) imx27_add_imx_uart(4, pdata) -#define imx27_add_imx_uart5(pdata) imx27_add_imx_uart(5, pdata) - -extern const struct imx_mx2_camera_data imx27_mx2_camera_data; -#define imx27_add_mx2_camera(pdata) \ - imx_add_mx2_camera(&imx27_mx2_camera_data, pdata) - -extern const struct imx_mx2_emma_data imx27_mx2_emmaprp_data; -#define imx27_add_mx2_emmaprp() \ - imx_add_mx2_emmaprp(&imx27_mx2_emmaprp_data) - -extern const struct imx_mxc_ehci_data imx27_mxc_ehci_otg_data; -#define imx27_add_mxc_ehci_otg(pdata) \ - imx_add_mxc_ehci(&imx27_mxc_ehci_otg_data, pdata) -extern const struct imx_mxc_ehci_data imx27_mxc_ehci_hs_data[]; -#define imx27_add_mxc_ehci_hs(id, pdata) \ - imx_add_mxc_ehci(&imx27_mxc_ehci_hs_data[id - 1], pdata) - -extern const struct imx_mxc_mmc_data imx27_mxc_mmc_data[]; -#define imx27_add_mxc_mmc(id, pdata) \ - imx_add_mxc_mmc(&imx27_mxc_mmc_data[id], pdata) - -extern const struct imx_mxc_nand_data imx27_mxc_nand_data; -#define imx27_add_mxc_nand(pdata) \ - imx_add_mxc_nand(&imx27_mxc_nand_data, pdata) - -extern const struct imx_mxc_w1_data imx27_mxc_w1_data; -#define imx27_add_mxc_w1() \ - imx_add_mxc_w1(&imx27_mxc_w1_data) - -extern const struct imx_spi_imx_data imx27_cspi_data[]; -#define imx27_add_cspi(id, gtable) \ - imx_add_spi_imx(&imx27_cspi_data[id], gtable) -#define imx27_add_spi_imx0(gtable) imx27_add_cspi(0, gtable) -#define imx27_add_spi_imx1(gtable) imx27_add_cspi(1, gtable) -#define imx27_add_spi_imx2(gtable) imx27_add_cspi(2, gtable) - -extern const struct imx_pata_imx_data imx27_pata_imx_data; -#define imx27_add_pata_imx() \ - imx_add_pata_imx(&imx27_pata_imx_data) diff --git a/arch/arm/mach-imx/devices-imx31.h b/arch/arm/mach-imx/devices-imx31.h deleted file mode 100644 index f7cc62372532..000000000000 --- a/arch/arm/mach-imx/devices-imx31.h +++ /dev/null @@ -1,80 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2010 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - */ -#include "devices/devices-common.h" - -extern const struct imx_fsl_usb2_udc_data imx31_fsl_usb2_udc_data; -#define imx31_add_fsl_usb2_udc(pdata) \ - imx_add_fsl_usb2_udc(&imx31_fsl_usb2_udc_data, pdata) - -extern const struct imx_imx2_wdt_data imx31_imx2_wdt_data; -#define imx31_add_imx2_wdt() \ - imx_add_imx2_wdt(&imx31_imx2_wdt_data) - -extern const struct imx_imx_i2c_data imx31_imx_i2c_data[]; -#define imx31_add_imx_i2c(id, pdata) \ - imx_add_imx_i2c(&imx31_imx_i2c_data[id], pdata) -#define imx31_add_imx_i2c0(pdata) imx31_add_imx_i2c(0, pdata) -#define imx31_add_imx_i2c1(pdata) imx31_add_imx_i2c(1, pdata) -#define imx31_add_imx_i2c2(pdata) imx31_add_imx_i2c(2, pdata) - -extern const struct imx_imx_keypad_data imx31_imx_keypad_data; -#define imx31_add_imx_keypad(pdata) \ - imx_add_imx_keypad(&imx31_imx_keypad_data, pdata) - -extern const struct imx_imx_ssi_data imx31_imx_ssi_data[]; -#define imx31_add_imx_ssi(id, pdata) \ - imx_add_imx_ssi(&imx31_imx_ssi_data[id], pdata) - -extern const struct imx_imx_uart_1irq_data imx31_imx_uart_data[]; -#define imx31_add_imx_uart(id, pdata) \ - imx_add_imx_uart_1irq(&imx31_imx_uart_data[id], pdata) -#define imx31_add_imx_uart0(pdata) imx31_add_imx_uart(0, pdata) -#define imx31_add_imx_uart1(pdata) imx31_add_imx_uart(1, pdata) -#define imx31_add_imx_uart2(pdata) imx31_add_imx_uart(2, pdata) -#define imx31_add_imx_uart3(pdata) imx31_add_imx_uart(3, pdata) -#define imx31_add_imx_uart4(pdata) imx31_add_imx_uart(4, pdata) - -extern const struct imx_ipu_core_data imx31_ipu_core_data; -#define imx31_add_ipu_core() \ - imx_add_ipu_core(&imx31_ipu_core_data) -#define imx31_alloc_mx3_camera(pdata) \ - imx_alloc_mx3_camera(&imx31_ipu_core_data, pdata) -#define imx31_add_mx3_sdc_fb(pdata) \ - imx_add_mx3_sdc_fb(&imx31_ipu_core_data, pdata) - -extern const struct imx_mxc_ehci_data imx31_mxc_ehci_otg_data; -#define imx31_add_mxc_ehci_otg(pdata) \ - imx_add_mxc_ehci(&imx31_mxc_ehci_otg_data, pdata) -extern const struct imx_mxc_ehci_data imx31_mxc_ehci_hs_data[]; -#define imx31_add_mxc_ehci_hs(id, pdata) \ - imx_add_mxc_ehci(&imx31_mxc_ehci_hs_data[id - 1], pdata) - -extern const struct imx_mxc_mmc_data imx31_mxc_mmc_data[]; -#define imx31_add_mxc_mmc(id, pdata) \ - imx_add_mxc_mmc(&imx31_mxc_mmc_data[id], pdata) - -extern const struct imx_mxc_nand_data imx31_mxc_nand_data; -#define imx31_add_mxc_nand(pdata) \ - imx_add_mxc_nand(&imx31_mxc_nand_data, pdata) - -extern const struct imx_mxc_rtc_data imx31_mxc_rtc_data; -#define imx31_add_mxc_rtc() \ - imx_add_mxc_rtc(&imx31_mxc_rtc_data) - -extern const struct imx_mxc_w1_data imx31_mxc_w1_data; -#define imx31_add_mxc_w1() \ - imx_add_mxc_w1(&imx31_mxc_w1_data) - -extern const struct imx_spi_imx_data imx31_cspi_data[]; -#define imx31_add_cspi(id, gtable) \ - imx_add_spi_imx(&imx31_cspi_data[id], gtable) -#define imx31_add_spi_imx0(gtable) imx31_add_cspi(0, gtable) -#define imx31_add_spi_imx1(gtable) imx31_add_cspi(1, gtable) -#define imx31_add_spi_imx2(gtable) imx31_add_cspi(2, gtable) - -extern const struct imx_pata_imx_data imx31_pata_imx_data; -#define imx31_add_pata_imx() \ - imx_add_pata_imx(&imx31_pata_imx_data) diff --git a/arch/arm/mach-imx/devices-imx35.h b/arch/arm/mach-imx/devices-imx35.h deleted file mode 100644 index 1b1bdadea15b..000000000000 --- a/arch/arm/mach-imx/devices-imx35.h +++ /dev/null @@ -1,87 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2010 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - */ -#include "devices/devices-common.h" - -extern const struct imx_fec_data imx35_fec_data; -#define imx35_add_fec(pdata) \ - imx_add_fec(&imx35_fec_data, pdata) - -extern const struct imx_fsl_usb2_udc_data imx35_fsl_usb2_udc_data; -#define imx35_add_fsl_usb2_udc(pdata) \ - imx_add_fsl_usb2_udc(&imx35_fsl_usb2_udc_data, pdata) - -extern const struct imx_flexcan_data imx35_flexcan_data[]; -#define imx35_add_flexcan(id) \ - imx_add_flexcan(&imx35_flexcan_data[id]) -#define imx35_add_flexcan0() imx35_add_flexcan(0) -#define imx35_add_flexcan1() imx35_add_flexcan(1) - -extern const struct imx_imx2_wdt_data imx35_imx2_wdt_data; -#define imx35_add_imx2_wdt() \ - imx_add_imx2_wdt(&imx35_imx2_wdt_data) - -extern const struct imx_imx_i2c_data imx35_imx_i2c_data[]; -#define imx35_add_imx_i2c(id, pdata) \ - imx_add_imx_i2c(&imx35_imx_i2c_data[id], pdata) -#define imx35_add_imx_i2c0(pdata) imx35_add_imx_i2c(0, pdata) -#define imx35_add_imx_i2c1(pdata) imx35_add_imx_i2c(1, pdata) -#define imx35_add_imx_i2c2(pdata) imx35_add_imx_i2c(2, pdata) - -extern const struct imx_imx_keypad_data imx35_imx_keypad_data; -#define imx35_add_imx_keypad(pdata) \ - imx_add_imx_keypad(&imx35_imx_keypad_data, pdata) - -extern const struct imx_imx_ssi_data imx35_imx_ssi_data[]; -#define imx35_add_imx_ssi(id, pdata) \ - imx_add_imx_ssi(&imx35_imx_ssi_data[id], pdata) - -extern const struct imx_imx_uart_1irq_data imx35_imx_uart_data[]; -#define imx35_add_imx_uart(id, pdata) \ - imx_add_imx_uart_1irq(&imx35_imx_uart_data[id], pdata) -#define imx35_add_imx_uart0(pdata) imx35_add_imx_uart(0, pdata) -#define imx35_add_imx_uart1(pdata) imx35_add_imx_uart(1, pdata) -#define imx35_add_imx_uart2(pdata) imx35_add_imx_uart(2, pdata) - -extern const struct imx_ipu_core_data imx35_ipu_core_data; -#define imx35_add_ipu_core() \ - imx_add_ipu_core(&imx35_ipu_core_data) -#define imx35_alloc_mx3_camera(pdata) \ - imx_alloc_mx3_camera(&imx35_ipu_core_data, pdata) -#define imx35_add_mx3_sdc_fb(pdata) \ - imx_add_mx3_sdc_fb(&imx35_ipu_core_data, pdata) - -extern const struct imx_mxc_ehci_data imx35_mxc_ehci_otg_data; -#define imx35_add_mxc_ehci_otg(pdata) \ - imx_add_mxc_ehci(&imx35_mxc_ehci_otg_data, pdata) -extern const struct imx_mxc_ehci_data imx35_mxc_ehci_hs_data; -#define imx35_add_mxc_ehci_hs(pdata) \ - imx_add_mxc_ehci(&imx35_mxc_ehci_hs_data, pdata) - -extern const struct imx_mxc_nand_data imx35_mxc_nand_data; -#define imx35_add_mxc_nand(pdata) \ - imx_add_mxc_nand(&imx35_mxc_nand_data, pdata) - -extern const struct imx_mxc_rtc_data imx35_mxc_rtc_data; -#define imx35_add_mxc_rtc() \ - imx_add_mxc_rtc(&imx35_mxc_rtc_data) - -extern const struct imx_mxc_w1_data imx35_mxc_w1_data; -#define imx35_add_mxc_w1() \ - imx_add_mxc_w1(&imx35_mxc_w1_data) - -extern const struct imx_sdhci_esdhc_imx_data imx35_sdhci_esdhc_imx_data[]; -#define imx35_add_sdhci_esdhc_imx(id, pdata) \ - imx_add_sdhci_esdhc_imx(&imx35_sdhci_esdhc_imx_data[id], pdata) - -extern const struct imx_spi_imx_data imx35_cspi_data[]; -#define imx35_add_cspi(id, pdata) \ - imx_add_spi_imx(&imx35_cspi_data[id], pdata) -#define imx35_add_spi_imx0(pdata) imx35_add_cspi(0, pdata) -#define imx35_add_spi_imx1(pdata) imx35_add_cspi(1, pdata) - -extern const struct imx_pata_imx_data imx35_pata_imx_data; -#define imx35_add_pata_imx() \ - imx_add_pata_imx(&imx35_pata_imx_data) diff --git a/arch/arm/mach-imx/devices/Kconfig b/arch/arm/mach-imx/devices/Kconfig deleted file mode 100644 index fdca73d117e6..000000000000 --- a/arch/arm/mach-imx/devices/Kconfig +++ /dev/null @@ -1,71 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -config IMX_HAVE_PLATFORM_FEC - bool - default y if SOC_IMX25 || SOC_IMX27 || SOC_IMX35 - -config IMX_HAVE_PLATFORM_FLEXCAN - bool - -config IMX_HAVE_PLATFORM_FSL_USB2_UDC - bool - -config IMX_HAVE_PLATFORM_GPIO_KEYS - bool - -config IMX_HAVE_PLATFORM_IMX21_HCD - bool - -config IMX_HAVE_PLATFORM_IMX27_CODA - bool - default y if SOC_IMX27 - -config IMX_HAVE_PLATFORM_IMX2_WDT - bool - -config IMX_HAVE_PLATFORM_IMX_FB - bool - -config IMX_HAVE_PLATFORM_IMX_I2C - bool - -config IMX_HAVE_PLATFORM_IMX_KEYPAD - bool - -config IMX_HAVE_PLATFORM_PATA_IMX - bool - -config IMX_HAVE_PLATFORM_IMX_SSI - bool - -config IMX_HAVE_PLATFORM_IMX_UART - bool - -config IMX_HAVE_PLATFORM_IPU_CORE - bool - -config IMX_HAVE_PLATFORM_MX2_CAMERA - bool - -config IMX_HAVE_PLATFORM_MX2_EMMA - bool - -config IMX_HAVE_PLATFORM_MXC_EHCI - bool - -config IMX_HAVE_PLATFORM_MXC_MMC - bool - -config IMX_HAVE_PLATFORM_MXC_NAND - bool - -config IMX_HAVE_PLATFORM_MXC_RTC - bool - -config IMX_HAVE_PLATFORM_MXC_W1 - bool - -config IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX - bool - -config IMX_HAVE_PLATFORM_SPI_IMX - bool diff --git a/arch/arm/mach-imx/devices/Makefile b/arch/arm/mach-imx/devices/Makefile deleted file mode 100644 index e44758aaa11c..000000000000 --- a/arch/arm/mach-imx/devices/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -obj-y := devices.o - -obj-$(CONFIG_IMX_HAVE_PLATFORM_FEC) += platform-fec.o -obj-$(CONFIG_IMX_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o -obj-$(CONFIG_IMX_HAVE_PLATFORM_FSL_USB2_UDC) += platform-fsl-usb2-udc.o -obj-$(CONFIG_IMX_HAVE_PLATFORM_GPIO_KEYS) += platform-gpio_keys.o -obj-y += platform-gpio-mxc.o -obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX21_HCD) += platform-imx21-hcd.o -obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX27_CODA) += platform-imx27-coda.o -obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX2_WDT) += platform-imx2-wdt.o -obj-y += platform-imx-dma.o -obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_FB) += platform-imx-fb.o -obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_I2C) += platform-imx-i2c.o -obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_KEYPAD) += platform-imx-keypad.o -obj-$(CONFIG_IMX_HAVE_PLATFORM_PATA_IMX) += platform-pata_imx.o -obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SSI) += platform-imx-ssi.o -obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UART) += platform-imx-uart.o -obj-$(CONFIG_IMX_HAVE_PLATFORM_IPU_CORE) += platform-ipu-core.o -obj-$(CONFIG_IMX_HAVE_PLATFORM_MX2_CAMERA) += platform-mx2-camera.o -obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_EHCI) += platform-mxc-ehci.o -obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_MMC) += platform-mxc-mmc.o -obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_NAND) += platform-mxc_nand.o -obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_RTC) += platform-mxc_rtc.o -obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_W1) += platform-mxc_w1.o -obj-$(CONFIG_IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX) += platform-sdhci-esdhc-imx.o -obj-$(CONFIG_IMX_HAVE_PLATFORM_SPI_IMX) += platform-spi_imx.o -obj-$(CONFIG_IMX_HAVE_PLATFORM_MX2_EMMA) += platform-mx2-emma.o diff --git a/arch/arm/mach-imx/devices/devices-common.h b/arch/arm/mach-imx/devices/devices-common.h deleted file mode 100644 index 327a1de7dce1..000000000000 --- a/arch/arm/mach-imx/devices/devices-common.h +++ /dev/null @@ -1,293 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2009-2010 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - */ -#include <linux/kernel.h> -#include <linux/platform_device.h> -#include <linux/init.h> -#include <linux/gpio/machine.h> -#include <linux/platform_data/dma-imx-sdma.h> - -extern struct device mxc_aips_bus; -extern struct device mxc_ahb_bus; - -static inline struct platform_device *imx_add_platform_device_dmamask( - const char *name, int id, - const struct resource *res, unsigned int num_resources, - const void *data, size_t size_data, u64 dmamask) -{ - struct platform_device_info pdevinfo = { - .name = name, - .id = id, - .res = res, - .num_res = num_resources, - .data = data, - .size_data = size_data, - .dma_mask = dmamask, - }; - return platform_device_register_full(&pdevinfo); -} - -static inline struct platform_device *imx_add_platform_device( - const char *name, int id, - const struct resource *res, unsigned int num_resources, - const void *data, size_t size_data) -{ - return imx_add_platform_device_dmamask( - name, id, res, num_resources, data, size_data, 0); -} - -#include <linux/fec.h> -struct imx_fec_data { - const char *devid; - resource_size_t iobase; - resource_size_t irq; -}; -struct platform_device *__init imx_add_fec( - const struct imx_fec_data *data, - const struct fec_platform_data *pdata); - -struct imx_flexcan_data { - int id; - resource_size_t iobase; - resource_size_t iosize; - resource_size_t irq; -}; -struct platform_device *__init imx_add_flexcan( - const struct imx_flexcan_data *data); - -#include <linux/fsl_devices.h> -struct imx_fsl_usb2_udc_data { - const char *devid; - resource_size_t iobase; - resource_size_t irq; -}; -struct platform_device *__init imx_add_fsl_usb2_udc( - const struct imx_fsl_usb2_udc_data *data, - const struct fsl_usb2_platform_data *pdata); - -#include <linux/gpio_keys.h> -struct platform_device *__init imx_add_gpio_keys( - const struct gpio_keys_platform_data *pdata); - -#include <linux/platform_data/usb-mx2.h> -struct imx_imx21_hcd_data { - resource_size_t iobase; - resource_size_t irq; -}; -struct platform_device *__init imx_add_imx21_hcd( - const struct imx_imx21_hcd_data *data, - const struct mx21_usbh_platform_data *pdata); - -struct imx_imx27_coda_data { - resource_size_t iobase; - resource_size_t iosize; - resource_size_t irq; -}; -struct platform_device *__init imx_add_imx27_coda( - const struct imx_imx27_coda_data *data); - -struct imx_imx2_wdt_data { - int id; - resource_size_t iobase; - resource_size_t iosize; -}; -struct platform_device *__init imx_add_imx2_wdt( - const struct imx_imx2_wdt_data *data); - -struct imx_imxdi_rtc_data { - resource_size_t iobase; - resource_size_t irq; -}; -struct platform_device *__init imx_add_imxdi_rtc( - const struct imx_imxdi_rtc_data *data); - -#include <linux/platform_data/video-imxfb.h> -struct imx_imx_fb_data { - const char *devid; - resource_size_t iobase; - resource_size_t iosize; - resource_size_t irq; -}; -struct platform_device *__init imx_add_imx_fb( - const struct imx_imx_fb_data *data, - const struct imx_fb_platform_data *pdata); - -#include <linux/platform_data/i2c-imx.h> -struct imx_imx_i2c_data { - const char *devid; - int id; - resource_size_t iobase; - resource_size_t iosize; - resource_size_t irq; -}; -struct platform_device *__init imx_add_imx_i2c( - const struct imx_imx_i2c_data *data, - const struct imxi2c_platform_data *pdata); - -#include <linux/input/matrix_keypad.h> -struct imx_imx_keypad_data { - resource_size_t iobase; - resource_size_t iosize; - resource_size_t irq; -}; -struct platform_device *__init imx_add_imx_keypad( - const struct imx_imx_keypad_data *data, - const struct matrix_keymap_data *pdata); - -#include <linux/platform_data/asoc-imx-ssi.h> -struct imx_imx_ssi_data { - int id; - resource_size_t iobase; - resource_size_t iosize; - resource_size_t irq; - resource_size_t dmatx0; - resource_size_t dmarx0; - resource_size_t dmatx1; - resource_size_t dmarx1; -}; -struct platform_device *__init imx_add_imx_ssi( - const struct imx_imx_ssi_data *data, - const struct imx_ssi_platform_data *pdata); - -#include <linux/platform_data/serial-imx.h> -struct imx_imx_uart_1irq_data { - int id; - resource_size_t iobase; - resource_size_t iosize; - resource_size_t irq; -}; -struct platform_device *__init imx_add_imx_uart_1irq( - const struct imx_imx_uart_1irq_data *data, - const struct imxuart_platform_data *pdata); - -#include <linux/platform_data/video-mx3fb.h> -#include <linux/platform_data/media/camera-mx3.h> -struct imx_ipu_core_data { - resource_size_t iobase; - resource_size_t synirq; - resource_size_t errirq; -}; -struct platform_device *__init imx_add_ipu_core( - const struct imx_ipu_core_data *data); -struct platform_device *__init imx_alloc_mx3_camera( - const struct imx_ipu_core_data *data, - const struct mx3_camera_pdata *pdata); -struct platform_device *__init imx_add_mx3_sdc_fb( - const struct imx_ipu_core_data *data, - struct mx3fb_platform_data *pdata); - -#include <linux/platform_data/media/camera-mx2.h> -struct imx_mx2_camera_data { - const char *devid; - resource_size_t iobasecsi; - resource_size_t iosizecsi; - resource_size_t irqcsi; - resource_size_t iobaseemmaprp; - resource_size_t iosizeemmaprp; - resource_size_t irqemmaprp; -}; -struct platform_device *__init imx_add_mx2_camera( - const struct imx_mx2_camera_data *data, - const struct mx2_camera_platform_data *pdata); - - -struct imx_mx2_emma_data { - resource_size_t iobase; - resource_size_t iosize; - resource_size_t irq; -}; -struct platform_device *__init imx_add_mx2_emmaprp( - const struct imx_mx2_emma_data *data); - -#include <linux/platform_data/usb-ehci-mxc.h> -struct imx_mxc_ehci_data { - int id; - resource_size_t iobase; - resource_size_t irq; -}; -struct platform_device *__init imx_add_mxc_ehci( - const struct imx_mxc_ehci_data *data, - const struct mxc_usbh_platform_data *pdata); - -#include <linux/platform_data/mmc-mxcmmc.h> -struct imx_mxc_mmc_data { - const char *devid; - int id; - resource_size_t iobase; - resource_size_t iosize; - resource_size_t irq; - resource_size_t dmareq; -}; -struct platform_device *__init imx_add_mxc_mmc( - const struct imx_mxc_mmc_data *data, - const struct imxmmc_platform_data *pdata); - -#include <linux/platform_data/mtd-mxc_nand.h> -struct imx_mxc_nand_data { - const char *devid; - /* - * id is traditionally 0, but -1 is more appropriate. We use -1 for new - * machines but don't change existing devices as the nand device usually - * appears in the kernel command line to pass its partitioning. - */ - int id; - resource_size_t iobase; - resource_size_t iosize; - resource_size_t axibase; - resource_size_t irq; -}; -struct platform_device *__init imx_add_mxc_nand( - const struct imx_mxc_nand_data *data, - const struct mxc_nand_platform_data *pdata); - -struct imx_pata_imx_data { - resource_size_t iobase; - resource_size_t iosize; - resource_size_t irq; -}; -struct platform_device *__init imx_add_pata_imx( - const struct imx_pata_imx_data *data); - -/* mxc_rtc */ -struct imx_mxc_rtc_data { - const char *devid; - resource_size_t iobase; - resource_size_t irq; -}; -struct platform_device *__init imx_add_mxc_rtc( - const struct imx_mxc_rtc_data *data); - -/* mxc_w1 */ -struct imx_mxc_w1_data { - resource_size_t iobase; -}; -struct platform_device *__init imx_add_mxc_w1( - const struct imx_mxc_w1_data *data); - -#include <linux/platform_data/mmc-esdhc-imx.h> -struct imx_sdhci_esdhc_imx_data { - const char *devid; - int id; - resource_size_t iobase; - resource_size_t irq; -}; -struct platform_device *__init imx_add_sdhci_esdhc_imx( - const struct imx_sdhci_esdhc_imx_data *data, - const struct esdhc_platform_data *pdata); - -struct imx_spi_imx_data { - const char *devid; - int id; - resource_size_t iobase; - resource_size_t iosize; - int irq; -}; -struct platform_device *__init imx_add_spi_imx( - const struct imx_spi_imx_data *data, struct gpiod_lookup_table *gtable); - -struct platform_device *imx_add_imx_dma(char *name, resource_size_t iobase, - int irq); -struct platform_device *imx_add_imx_sdma(char *name, - resource_size_t iobase, int irq, struct sdma_platform_data *pdata); diff --git a/arch/arm/mach-imx/devices/devices.c b/arch/arm/mach-imx/devices/devices.c deleted file mode 100644 index cd72f0894196..000000000000 --- a/arch/arm/mach-imx/devices/devices.c +++ /dev/null @@ -1,35 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2008 Sascha Hauer, kernel@pengutronix.de - */ - -#include <linux/kernel.h> -#include <linux/slab.h> -#include <linux/init.h> -#include <linux/err.h> -#include <linux/platform_device.h> - -#include "../common.h" -#include "devices-common.h" - -struct device mxc_aips_bus = { - .init_name = "mxc_aips", -}; - -struct device mxc_ahb_bus = { - .init_name = "mxc_ahb", -}; - -int __init mxc_device_init(void) -{ - int ret; - - ret = device_register(&mxc_aips_bus); - if (ret < 0) - goto done; - - ret = device_register(&mxc_ahb_bus); - -done: - return ret; -} diff --git a/arch/arm/mach-imx/devices/platform-fec.c b/arch/arm/mach-imx/devices/platform-fec.c deleted file mode 100644 index 88e853d7fb01..000000000000 --- a/arch/arm/mach-imx/devices/platform-fec.c +++ /dev/null @@ -1,49 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2010 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - */ -#include <linux/dma-mapping.h> -#include <linux/sizes.h> - -#include "../hardware.h" -#include "devices-common.h" - -#define imx_fec_data_entry_single(soc, _devid) \ - { \ - .devid = _devid, \ - .iobase = soc ## _FEC_BASE_ADDR, \ - .irq = soc ## _INT_FEC, \ - } - -#ifdef CONFIG_SOC_IMX27 -const struct imx_fec_data imx27_fec_data __initconst = - imx_fec_data_entry_single(MX27, "imx27-fec"); -#endif /* ifdef CONFIG_SOC_IMX27 */ - -#ifdef CONFIG_SOC_IMX35 -/* i.mx35 has the i.mx27 type fec */ -const struct imx_fec_data imx35_fec_data __initconst = - imx_fec_data_entry_single(MX35, "imx27-fec"); -#endif - -struct platform_device *__init imx_add_fec( - const struct imx_fec_data *data, - const struct fec_platform_data *pdata) -{ - struct resource res[] = { - { - .start = data->iobase, - .end = data->iobase + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = data->irq, - .end = data->irq, - .flags = IORESOURCE_IRQ, - }, - }; - - return imx_add_platform_device_dmamask(data->devid, 0, - res, ARRAY_SIZE(res), - pdata, sizeof(*pdata), DMA_BIT_MASK(32)); -} diff --git a/arch/arm/mach-imx/devices/platform-flexcan.c b/arch/arm/mach-imx/devices/platform-flexcan.c deleted file mode 100644 index e4eed35c1fe2..000000000000 --- a/arch/arm/mach-imx/devices/platform-flexcan.c +++ /dev/null @@ -1,45 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2010 Pengutronix, Marc Kleine-Budde <kernel@pengutronix.de> - */ -#include "../hardware.h" -#include "devices-common.h" - -#define imx_flexcan_data_entry_single(soc, _id, _hwid, _size) \ - { \ - .id = _id, \ - .iobase = soc ## _CAN ## _hwid ## _BASE_ADDR, \ - .iosize = _size, \ - .irq = soc ## _INT_CAN ## _hwid, \ - } - -#define imx_flexcan_data_entry(soc, _id, _hwid, _size) \ - [_id] = imx_flexcan_data_entry_single(soc, _id, _hwid, _size) - -#ifdef CONFIG_SOC_IMX35 -const struct imx_flexcan_data imx35_flexcan_data[] __initconst = { -#define imx35_flexcan_data_entry(_id, _hwid) \ - imx_flexcan_data_entry(MX35, _id, _hwid, SZ_16K) - imx35_flexcan_data_entry(0, 1), - imx35_flexcan_data_entry(1, 2), -}; -#endif /* ifdef CONFIG_SOC_IMX35 */ - -struct platform_device *__init imx_add_flexcan( - const struct imx_flexcan_data *data) -{ - struct resource res[] = { - { - .start = data->iobase, - .end = data->iobase + data->iosize - 1, - .flags = IORESOURCE_MEM, - }, { - .start = data->irq, - .end = data->irq, - .flags = IORESOURCE_IRQ, - }, - }; - - return imx_add_platform_device("flexcan", data->id, - res, ARRAY_SIZE(res), NULL, 0); -} diff --git a/arch/arm/mach-imx/devices/platform-fsl-usb2-udc.c b/arch/arm/mach-imx/devices/platform-fsl-usb2-udc.c deleted file mode 100644 index cc86de4d7acb..000000000000 --- a/arch/arm/mach-imx/devices/platform-fsl-usb2-udc.c +++ /dev/null @@ -1,51 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2010 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - */ -#include <linux/dma-mapping.h> - -#include "../hardware.h" -#include "devices-common.h" - -#define imx_fsl_usb2_udc_data_entry_single(soc, _devid) \ - { \ - .devid = _devid, \ - .iobase = soc ## _USB_OTG_BASE_ADDR, \ - .irq = soc ## _INT_USB_OTG, \ - } - -#ifdef CONFIG_SOC_IMX27 -const struct imx_fsl_usb2_udc_data imx27_fsl_usb2_udc_data __initconst = - imx_fsl_usb2_udc_data_entry_single(MX27, "imx-udc-mx27"); -#endif /* ifdef CONFIG_SOC_IMX27 */ - -#ifdef CONFIG_SOC_IMX31 -const struct imx_fsl_usb2_udc_data imx31_fsl_usb2_udc_data __initconst = - imx_fsl_usb2_udc_data_entry_single(MX31, "imx-udc-mx27"); -#endif /* ifdef CONFIG_SOC_IMX31 */ - -#ifdef CONFIG_SOC_IMX35 -const struct imx_fsl_usb2_udc_data imx35_fsl_usb2_udc_data __initconst = - imx_fsl_usb2_udc_data_entry_single(MX35, "imx-udc-mx27"); -#endif /* ifdef CONFIG_SOC_IMX35 */ - -struct platform_device *__init imx_add_fsl_usb2_udc( - const struct imx_fsl_usb2_udc_data *data, - const struct fsl_usb2_platform_data *pdata) -{ - struct resource res[] = { - { - .start = data->iobase, - .end = data->iobase + SZ_512 - 1, - .flags = IORESOURCE_MEM, - }, { - .start = data->irq, - .end = data->irq, - .flags = IORESOURCE_IRQ, - }, - }; - return imx_add_platform_device_dmamask(data->devid, -1, - res, ARRAY_SIZE(res), - pdata, sizeof(*pdata), DMA_BIT_MASK(32)); -} diff --git a/arch/arm/mach-imx/devices/platform-gpio-mxc.c b/arch/arm/mach-imx/devices/platform-gpio-mxc.c deleted file mode 100644 index 355de845224c..000000000000 --- a/arch/arm/mach-imx/devices/platform-gpio-mxc.c +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2011 Linaro Limited - */ -#include "devices-common.h" -#include "../common.h" - -struct platform_device *__init mxc_register_gpio(char *name, int id, - resource_size_t iobase, resource_size_t iosize, int irq, int irq_high) -{ - struct resource res[] = { - { - .start = iobase, - .end = iobase + iosize - 1, - .flags = IORESOURCE_MEM, - }, { - .start = irq, - .end = irq, - .flags = IORESOURCE_IRQ, - }, { - .start = irq_high, - .end = irq_high, - .flags = IORESOURCE_IRQ, - }, - }; - unsigned int nres; - - nres = irq_high ? ARRAY_SIZE(res) : ARRAY_SIZE(res) - 1; - return platform_device_register_resndata(&mxc_aips_bus, name, id, res, nres, NULL, 0); -} diff --git a/arch/arm/mach-imx/devices/platform-gpio_keys.c b/arch/arm/mach-imx/devices/platform-gpio_keys.c deleted file mode 100644 index 488678403ac8..000000000000 --- a/arch/arm/mach-imx/devices/platform-gpio_keys.c +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. - */ -#include <linux/sizes.h> - -#include "../hardware.h" -#include "devices-common.h" - -struct platform_device *__init imx_add_gpio_keys( - const struct gpio_keys_platform_data *pdata) -{ - return imx_add_platform_device("gpio-keys", -1, NULL, - 0, pdata, sizeof(*pdata)); -} diff --git a/arch/arm/mach-imx/devices/platform-imx-dma.c b/arch/arm/mach-imx/devices/platform-imx-dma.c deleted file mode 100644 index 12656f24ad0d..000000000000 --- a/arch/arm/mach-imx/devices/platform-imx-dma.c +++ /dev/null @@ -1,44 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2010 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - */ -#include "devices-common.h" - -struct platform_device __init __maybe_unused *imx_add_imx_dma(char *name, - resource_size_t iobase, int irq) -{ - struct resource res[] = { - { - .start = iobase, - .end = iobase + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = irq, - .end = irq, - .flags = IORESOURCE_IRQ, - }, - }; - - return platform_device_register_resndata(&mxc_ahb_bus, - name, -1, res, ARRAY_SIZE(res), NULL, 0); -} - -struct platform_device __init __maybe_unused *imx_add_imx_sdma(char *name, - resource_size_t iobase, int irq, struct sdma_platform_data *pdata) -{ - struct resource res[] = { - { - .start = iobase, - .end = iobase + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = irq, - .end = irq, - .flags = IORESOURCE_IRQ, - }, - }; - - return platform_device_register_resndata(&mxc_ahb_bus, name, - -1, res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); -} diff --git a/arch/arm/mach-imx/devices/platform-imx-fb.c b/arch/arm/mach-imx/devices/platform-imx-fb.c deleted file mode 100644 index e553d014506a..000000000000 --- a/arch/arm/mach-imx/devices/platform-imx-fb.c +++ /dev/null @@ -1,47 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2010 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - */ -#include <linux/dma-mapping.h> - -#include "../hardware.h" -#include "devices-common.h" - -#define imx_imx_fb_data_entry_single(soc, _devid, _size) \ - { \ - .devid = _devid, \ - .iobase = soc ## _LCDC_BASE_ADDR, \ - .iosize = _size, \ - .irq = soc ## _INT_LCDC, \ - } - -#ifdef CONFIG_SOC_IMX21 -const struct imx_imx_fb_data imx21_imx_fb_data __initconst = - imx_imx_fb_data_entry_single(MX21, "imx21-fb", SZ_4K); -#endif /* ifdef CONFIG_SOC_IMX21 */ - -#ifdef CONFIG_SOC_IMX27 -const struct imx_imx_fb_data imx27_imx_fb_data __initconst = - imx_imx_fb_data_entry_single(MX27, "imx21-fb", SZ_4K); -#endif /* ifdef CONFIG_SOC_IMX27 */ - -struct platform_device *__init imx_add_imx_fb( - const struct imx_imx_fb_data *data, - const struct imx_fb_platform_data *pdata) -{ - struct resource res[] = { - { - .start = data->iobase, - .end = data->iobase + data->iosize - 1, - .flags = IORESOURCE_MEM, - }, { - .start = data->irq, - .end = data->irq, - .flags = IORESOURCE_IRQ, - }, - }; - return imx_add_platform_device_dmamask(data->devid, 0, - res, ARRAY_SIZE(res), - pdata, sizeof(*pdata), DMA_BIT_MASK(32)); -} diff --git a/arch/arm/mach-imx/devices/platform-imx-i2c.c b/arch/arm/mach-imx/devices/platform-imx-i2c.c deleted file mode 100644 index 81d317bfadd8..000000000000 --- a/arch/arm/mach-imx/devices/platform-imx-i2c.c +++ /dev/null @@ -1,74 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2009-2010 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - */ -#include "../hardware.h" -#include "devices-common.h" - -#define imx_imx_i2c_data_entry_single(soc, _devid, _id, _hwid, _size) \ - { \ - .devid = _devid, \ - .id = _id, \ - .iobase = soc ## _I2C ## _hwid ## _BASE_ADDR, \ - .iosize = _size, \ - .irq = soc ## _INT_I2C ## _hwid, \ - } - -#define imx_imx_i2c_data_entry(soc, _devid, _id, _hwid, _size) \ - [_id] = imx_imx_i2c_data_entry_single(soc, _devid, _id, _hwid, _size) - -#ifdef CONFIG_SOC_IMX21 -const struct imx_imx_i2c_data imx21_imx_i2c_data __initconst = - imx_imx_i2c_data_entry_single(MX21, "imx21-i2c", 0, , SZ_4K); -#endif /* ifdef CONFIG_SOC_IMX21 */ - -#ifdef CONFIG_SOC_IMX27 -const struct imx_imx_i2c_data imx27_imx_i2c_data[] __initconst = { -#define imx27_imx_i2c_data_entry(_id, _hwid) \ - imx_imx_i2c_data_entry(MX27, "imx21-i2c", _id, _hwid, SZ_4K) - imx27_imx_i2c_data_entry(0, 1), - imx27_imx_i2c_data_entry(1, 2), -}; -#endif /* ifdef CONFIG_SOC_IMX27 */ - -#ifdef CONFIG_SOC_IMX31 -const struct imx_imx_i2c_data imx31_imx_i2c_data[] __initconst = { -#define imx31_imx_i2c_data_entry(_id, _hwid) \ - imx_imx_i2c_data_entry(MX31, "imx21-i2c", _id, _hwid, SZ_4K) - imx31_imx_i2c_data_entry(0, 1), - imx31_imx_i2c_data_entry(1, 2), - imx31_imx_i2c_data_entry(2, 3), -}; -#endif /* ifdef CONFIG_SOC_IMX31 */ - -#ifdef CONFIG_SOC_IMX35 -const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst = { -#define imx35_imx_i2c_data_entry(_id, _hwid) \ - imx_imx_i2c_data_entry(MX35, "imx21-i2c", _id, _hwid, SZ_4K) - imx35_imx_i2c_data_entry(0, 1), - imx35_imx_i2c_data_entry(1, 2), - imx35_imx_i2c_data_entry(2, 3), -}; -#endif /* ifdef CONFIG_SOC_IMX35 */ - -struct platform_device *__init imx_add_imx_i2c( - const struct imx_imx_i2c_data *data, - const struct imxi2c_platform_data *pdata) -{ - struct resource res[] = { - { - .start = data->iobase, - .end = data->iobase + data->iosize - 1, - .flags = IORESOURCE_MEM, - }, { - .start = data->irq, - .end = data->irq, - .flags = IORESOURCE_IRQ, - }, - }; - - return imx_add_platform_device(data->devid, data->id, - res, ARRAY_SIZE(res), - pdata, sizeof(*pdata)); -} diff --git a/arch/arm/mach-imx/devices/platform-imx-keypad.c b/arch/arm/mach-imx/devices/platform-imx-keypad.c deleted file mode 100644 index de2e03ec2d89..000000000000 --- a/arch/arm/mach-imx/devices/platform-imx-keypad.c +++ /dev/null @@ -1,54 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2010 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - */ -#include "../hardware.h" -#include "devices-common.h" - -#define imx_imx_keypad_data_entry_single(soc, _size) \ - { \ - .iobase = soc ## _KPP_BASE_ADDR, \ - .iosize = _size, \ - .irq = soc ## _INT_KPP, \ - } - -#ifdef CONFIG_SOC_IMX21 -const struct imx_imx_keypad_data imx21_imx_keypad_data __initconst = - imx_imx_keypad_data_entry_single(MX21, SZ_16); -#endif /* ifdef CONFIG_SOC_IMX21 */ - -#ifdef CONFIG_SOC_IMX27 -const struct imx_imx_keypad_data imx27_imx_keypad_data __initconst = - imx_imx_keypad_data_entry_single(MX27, SZ_16); -#endif /* ifdef CONFIG_SOC_IMX27 */ - -#ifdef CONFIG_SOC_IMX31 -const struct imx_imx_keypad_data imx31_imx_keypad_data __initconst = - imx_imx_keypad_data_entry_single(MX31, SZ_16); -#endif /* ifdef CONFIG_SOC_IMX31 */ - -#ifdef CONFIG_SOC_IMX35 -const struct imx_imx_keypad_data imx35_imx_keypad_data __initconst = - imx_imx_keypad_data_entry_single(MX35, SZ_16); -#endif /* ifdef CONFIG_SOC_IMX35 */ - -struct platform_device *__init imx_add_imx_keypad( - const struct imx_imx_keypad_data *data, - const struct matrix_keymap_data *pdata) -{ - struct resource res[] = { - { - .start = data->iobase, - .end = data->iobase + data->iosize - 1, - .flags = IORESOURCE_MEM, - }, { - .start = data->irq, - .end = data->irq, - .flags = IORESOURCE_IRQ, - }, - }; - - return imx_add_platform_device("imx-keypad", -1, - res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); -} diff --git a/arch/arm/mach-imx/devices/platform-imx-ssi.c b/arch/arm/mach-imx/devices/platform-imx-ssi.c deleted file mode 100644 index ed8c66438af0..000000000000 --- a/arch/arm/mach-imx/devices/platform-imx-ssi.c +++ /dev/null @@ -1,86 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2010 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - */ -#include "../hardware.h" -#include "devices-common.h" - -#define imx_imx_ssi_data_entry(soc, _id, _hwid, _size) \ - [_id] = { \ - .id = _id, \ - .iobase = soc ## _SSI ## _hwid ## _BASE_ADDR, \ - .iosize = _size, \ - .irq = soc ## _INT_SSI ## _hwid, \ - .dmatx0 = soc ## _DMA_REQ_SSI ## _hwid ## _TX0, \ - .dmarx0 = soc ## _DMA_REQ_SSI ## _hwid ## _RX0, \ - .dmatx1 = soc ## _DMA_REQ_SSI ## _hwid ## _TX1, \ - .dmarx1 = soc ## _DMA_REQ_SSI ## _hwid ## _RX1, \ - } - -#ifdef CONFIG_SOC_IMX21 -const struct imx_imx_ssi_data imx21_imx_ssi_data[] __initconst = { -#define imx21_imx_ssi_data_entry(_id, _hwid) \ - imx_imx_ssi_data_entry(MX21, _id, _hwid, SZ_4K) - imx21_imx_ssi_data_entry(0, 1), - imx21_imx_ssi_data_entry(1, 2), -}; -#endif /* ifdef CONFIG_SOC_IMX21 */ - -#ifdef CONFIG_SOC_IMX27 -const struct imx_imx_ssi_data imx27_imx_ssi_data[] __initconst = { -#define imx27_imx_ssi_data_entry(_id, _hwid) \ - imx_imx_ssi_data_entry(MX27, _id, _hwid, SZ_4K) - imx27_imx_ssi_data_entry(0, 1), - imx27_imx_ssi_data_entry(1, 2), -}; -#endif /* ifdef CONFIG_SOC_IMX27 */ - -#ifdef CONFIG_SOC_IMX31 -const struct imx_imx_ssi_data imx31_imx_ssi_data[] __initconst = { -#define imx31_imx_ssi_data_entry(_id, _hwid) \ - imx_imx_ssi_data_entry(MX31, _id, _hwid, SZ_4K) - imx31_imx_ssi_data_entry(0, 1), - imx31_imx_ssi_data_entry(1, 2), -}; -#endif /* ifdef CONFIG_SOC_IMX31 */ - -#ifdef CONFIG_SOC_IMX35 -const struct imx_imx_ssi_data imx35_imx_ssi_data[] __initconst = { -#define imx35_imx_ssi_data_entry(_id, _hwid) \ - imx_imx_ssi_data_entry(MX35, _id, _hwid, SZ_4K) - imx35_imx_ssi_data_entry(0, 1), - imx35_imx_ssi_data_entry(1, 2), -}; -#endif /* ifdef CONFIG_SOC_IMX35 */ - -struct platform_device *__init imx_add_imx_ssi( - const struct imx_imx_ssi_data *data, - const struct imx_ssi_platform_data *pdata) -{ - struct resource res[] = { - { - .start = data->iobase, - .end = data->iobase + data->iosize - 1, - .flags = IORESOURCE_MEM, - }, { - .start = data->irq, - .end = data->irq, - .flags = IORESOURCE_IRQ, - }, -#define DMARES(_name) { \ - .name = #_name, \ - .start = data->dma ## _name, \ - .end = data->dma ## _name, \ - .flags = IORESOURCE_DMA, \ -} - DMARES(tx0), - DMARES(rx0), - DMARES(tx1), - DMARES(rx1), - }; - - return imx_add_platform_device("imx-ssi", data->id, - res, ARRAY_SIZE(res), - pdata, sizeof(*pdata)); -} diff --git a/arch/arm/mach-imx/devices/platform-imx-uart.c b/arch/arm/mach-imx/devices/platform-imx-uart.c deleted file mode 100644 index c8f01deedd80..000000000000 --- a/arch/arm/mach-imx/devices/platform-imx-uart.c +++ /dev/null @@ -1,92 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2009-2010 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - */ -#include "../hardware.h" -#include "devices-common.h" - -#define imx_imx_uart_3irq_data_entry(soc, _id, _hwid, _size) \ - [_id] = { \ - .id = _id, \ - .iobase = soc ## _UART ## _hwid ## _BASE_ADDR, \ - .iosize = _size, \ - .irqrx = soc ## _INT_UART ## _hwid ## RX, \ - .irqtx = soc ## _INT_UART ## _hwid ## TX, \ - .irqrts = soc ## _INT_UART ## _hwid ## RTS, \ - } - -#define imx_imx_uart_1irq_data_entry(soc, _id, _hwid, _size) \ - [_id] = { \ - .id = _id, \ - .iobase = soc ## _UART ## _hwid ## _BASE_ADDR, \ - .iosize = _size, \ - .irq = soc ## _INT_UART ## _hwid, \ - } - -#ifdef CONFIG_SOC_IMX21 -const struct imx_imx_uart_1irq_data imx21_imx_uart_data[] __initconst = { -#define imx21_imx_uart_data_entry(_id, _hwid) \ - imx_imx_uart_1irq_data_entry(MX21, _id, _hwid, SZ_4K) - imx21_imx_uart_data_entry(0, 1), - imx21_imx_uart_data_entry(1, 2), - imx21_imx_uart_data_entry(2, 3), - imx21_imx_uart_data_entry(3, 4), -}; -#endif - -#ifdef CONFIG_SOC_IMX27 -const struct imx_imx_uart_1irq_data imx27_imx_uart_data[] __initconst = { -#define imx27_imx_uart_data_entry(_id, _hwid) \ - imx_imx_uart_1irq_data_entry(MX27, _id, _hwid, SZ_4K) - imx27_imx_uart_data_entry(0, 1), - imx27_imx_uart_data_entry(1, 2), - imx27_imx_uart_data_entry(2, 3), - imx27_imx_uart_data_entry(3, 4), - imx27_imx_uart_data_entry(4, 5), - imx27_imx_uart_data_entry(5, 6), -}; -#endif /* ifdef CONFIG_SOC_IMX27 */ - -#ifdef CONFIG_SOC_IMX31 -const struct imx_imx_uart_1irq_data imx31_imx_uart_data[] __initconst = { -#define imx31_imx_uart_data_entry(_id, _hwid) \ - imx_imx_uart_1irq_data_entry(MX31, _id, _hwid, SZ_4K) - imx31_imx_uart_data_entry(0, 1), - imx31_imx_uart_data_entry(1, 2), - imx31_imx_uart_data_entry(2, 3), - imx31_imx_uart_data_entry(3, 4), - imx31_imx_uart_data_entry(4, 5), -}; -#endif /* ifdef CONFIG_SOC_IMX31 */ - -#ifdef CONFIG_SOC_IMX35 -const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst = { -#define imx35_imx_uart_data_entry(_id, _hwid) \ - imx_imx_uart_1irq_data_entry(MX35, _id, _hwid, SZ_16K) - imx35_imx_uart_data_entry(0, 1), - imx35_imx_uart_data_entry(1, 2), - imx35_imx_uart_data_entry(2, 3), -}; -#endif /* ifdef CONFIG_SOC_IMX35 */ - -struct platform_device *__init imx_add_imx_uart_1irq( - const struct imx_imx_uart_1irq_data *data, - const struct imxuart_platform_data *pdata) -{ - struct resource res[] = { - { - .start = data->iobase, - .end = data->iobase + data->iosize - 1, - .flags = IORESOURCE_MEM, - }, { - .start = data->irq, - .end = data->irq, - .flags = IORESOURCE_IRQ, - }, - }; - - /* i.mx21 type uart runs on all i.mx except i.mx1 */ - return imx_add_platform_device("imx21-uart", data->id, - res, ARRAY_SIZE(res), pdata, sizeof(*pdata)); -} diff --git a/arch/arm/mach-imx/devices/platform-imx2-wdt.c b/arch/arm/mach-imx/devices/platform-imx2-wdt.c deleted file mode 100644 index fdd355ae4d5f..000000000000 --- a/arch/arm/mach-imx/devices/platform-imx2-wdt.c +++ /dev/null @@ -1,52 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2010 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - */ -#include <linux/sizes.h> - -#include "../hardware.h" -#include "devices-common.h" - -#define imx_imx2_wdt_data_entry_single(soc, _id, _hwid, _size) \ - { \ - .id = _id, \ - .iobase = soc ## _WDOG ## _hwid ## _BASE_ADDR, \ - .iosize = _size, \ - } -#define imx_imx2_wdt_data_entry(soc, _id, _hwid, _size) \ - [_id] = imx_imx2_wdt_data_entry_single(soc, _id, _hwid, _size) - -#ifdef CONFIG_SOC_IMX21 -const struct imx_imx2_wdt_data imx21_imx2_wdt_data __initconst = - imx_imx2_wdt_data_entry_single(MX21, 0, , SZ_4K); -#endif /* ifdef CONFIG_SOC_IMX21 */ - -#ifdef CONFIG_SOC_IMX27 -const struct imx_imx2_wdt_data imx27_imx2_wdt_data __initconst = - imx_imx2_wdt_data_entry_single(MX27, 0, , SZ_4K); -#endif /* ifdef CONFIG_SOC_IMX27 */ - -#ifdef CONFIG_SOC_IMX31 -const struct imx_imx2_wdt_data imx31_imx2_wdt_data __initconst = - imx_imx2_wdt_data_entry_single(MX31, 0, , SZ_16K); -#endif /* ifdef CONFIG_SOC_IMX31 */ - -#ifdef CONFIG_SOC_IMX35 -const struct imx_imx2_wdt_data imx35_imx2_wdt_data __initconst = - imx_imx2_wdt_data_entry_single(MX35, 0, , SZ_16K); -#endif /* ifdef CONFIG_SOC_IMX35 */ - -struct platform_device *__init imx_add_imx2_wdt( - const struct imx_imx2_wdt_data *data) -{ - struct resource res[] = { - { - .start = data->iobase, - .end = data->iobase + data->iosize - 1, - .flags = IORESOURCE_MEM, - }, - }; - return imx_add_platform_device("imx2-wdt", data->id, - res, ARRAY_SIZE(res), NULL, 0); -} diff --git a/arch/arm/mach-imx/devices/platform-imx21-hcd.c b/arch/arm/mach-imx/devices/platform-imx21-hcd.c deleted file mode 100644 index f55763c36d26..000000000000 --- a/arch/arm/mach-imx/devices/platform-imx21-hcd.c +++ /dev/null @@ -1,38 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2010 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - */ -#include "../hardware.h" -#include "devices-common.h" - -#define imx_imx21_hcd_data_entry_single(soc) \ - { \ - .iobase = soc ## _USBOTG_BASE_ADDR, \ - .irq = soc ## _INT_USBHOST, \ - } - -#ifdef CONFIG_SOC_IMX21 -const struct imx_imx21_hcd_data imx21_imx21_hcd_data __initconst = - imx_imx21_hcd_data_entry_single(MX21); -#endif /* ifdef CONFIG_SOC_IMX21 */ - -struct platform_device *__init imx_add_imx21_hcd( - const struct imx_imx21_hcd_data *data, - const struct mx21_usbh_platform_data *pdata) -{ - struct resource res[] = { - { - .start = data->iobase, - .end = data->iobase + SZ_8K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = data->irq, - .end = data->irq, - .flags = IORESOURCE_IRQ, - }, - }; - return imx_add_platform_device_dmamask("imx21-hcd", 0, - res, ARRAY_SIZE(res), - pdata, sizeof(*pdata), DMA_BIT_MASK(32)); -} diff --git a/arch/arm/mach-imx/devices/platform-imx27-coda.c b/arch/arm/mach-imx/devices/platform-imx27-coda.c deleted file mode 100644 index 66a116e6c6bc..000000000000 --- a/arch/arm/mach-imx/devices/platform-imx27-coda.c +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2012 Vista Silicon - * Javier Martin <javier.martin@vista-silicon.com> - */ - -#include "../hardware.h" -#include "devices-common.h" - -#ifdef CONFIG_SOC_IMX27 -const struct imx_imx27_coda_data imx27_coda_data __initconst = { - .iobase = MX27_VPU_BASE_ADDR, - .iosize = SZ_512, - .irq = MX27_INT_VPU, -}; -#endif - -struct platform_device *__init imx_add_imx27_coda( - const struct imx_imx27_coda_data *data) -{ - struct resource res[] = { - { - .start = data->iobase, - .end = data->iobase + data->iosize - 1, - .flags = IORESOURCE_MEM, - }, { - .start = data->irq, - .end = data->irq, - .flags = IORESOURCE_IRQ, - }, - }; - return imx_add_platform_device_dmamask("coda-imx27", 0, res, 2, NULL, - 0, DMA_BIT_MASK(32)); -} diff --git a/arch/arm/mach-imx/devices/platform-ipu-core.c b/arch/arm/mach-imx/devices/platform-ipu-core.c deleted file mode 100644 index b4290760f49f..000000000000 --- a/arch/arm/mach-imx/devices/platform-ipu-core.c +++ /dev/null @@ -1,127 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2011 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - */ -#include <linux/dma-mapping.h> - -#include "../hardware.h" -#include "devices-common.h" - -#define imx_ipu_core_entry_single(soc) \ -{ \ - .iobase = soc ## _IPU_CTRL_BASE_ADDR, \ - .synirq = soc ## _INT_IPU_SYN, \ - .errirq = soc ## _INT_IPU_ERR, \ -} - -#ifdef CONFIG_SOC_IMX31 -const struct imx_ipu_core_data imx31_ipu_core_data __initconst = - imx_ipu_core_entry_single(MX31); -#endif - -#ifdef CONFIG_SOC_IMX35 -const struct imx_ipu_core_data imx35_ipu_core_data __initconst = - imx_ipu_core_entry_single(MX35); -#endif - -static struct platform_device *imx_ipu_coredev __initdata; - -struct platform_device *__init imx_add_ipu_core( - const struct imx_ipu_core_data *data) -{ - /* The resource order is important! */ - struct resource res[] = { - { - .start = data->iobase, - .end = data->iobase + 0x5f, - .flags = IORESOURCE_MEM, - }, { - .start = data->iobase + 0x88, - .end = data->iobase + 0xb3, - .flags = IORESOURCE_MEM, - }, { - .start = data->synirq, - .end = data->synirq, - .flags = IORESOURCE_IRQ, - }, { - .start = data->errirq, - .end = data->errirq, - .flags = IORESOURCE_IRQ, - }, - }; - - return imx_ipu_coredev = imx_add_platform_device("ipu-core", -1, - res, ARRAY_SIZE(res), NULL, 0); -} - -struct platform_device *__init imx_alloc_mx3_camera( - const struct imx_ipu_core_data *data, - const struct mx3_camera_pdata *pdata) -{ - struct resource res[] = { - { - .start = data->iobase + 0x60, - .end = data->iobase + 0x87, - .flags = IORESOURCE_MEM, - }, - }; - int ret = -ENOMEM; - struct platform_device *pdev; - - if (IS_ERR_OR_NULL(imx_ipu_coredev)) - return ERR_PTR(-ENODEV); - - pdev = platform_device_alloc("mx3-camera", 0); - if (!pdev) - return ERR_PTR(-ENOMEM); - - pdev->dev.dma_mask = kmalloc(sizeof(*pdev->dev.dma_mask), GFP_KERNEL); - if (!pdev->dev.dma_mask) - goto err; - - *pdev->dev.dma_mask = DMA_BIT_MASK(32); - pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32); - - ret = platform_device_add_resources(pdev, res, ARRAY_SIZE(res)); - if (ret) - goto err; - - if (pdata) { - struct mx3_camera_pdata *copied_pdata; - - ret = platform_device_add_data(pdev, pdata, sizeof(*pdata)); - if (ret) { -err: - kfree(pdev->dev.dma_mask); - platform_device_put(pdev); - return ERR_PTR(-ENODEV); - } - copied_pdata = dev_get_platdata(&pdev->dev); - copied_pdata->dma_dev = &imx_ipu_coredev->dev; - } - - return pdev; -} - -struct platform_device *__init imx_add_mx3_sdc_fb( - const struct imx_ipu_core_data *data, - struct mx3fb_platform_data *pdata) -{ - struct resource res[] = { - { - .start = data->iobase + 0xb4, - .end = data->iobase + 0x1bf, - .flags = IORESOURCE_MEM, - }, - }; - - if (IS_ERR_OR_NULL(imx_ipu_coredev)) - return ERR_PTR(-ENODEV); - - pdata->dma_dev = &imx_ipu_coredev->dev; - - return imx_add_platform_device_dmamask("mx3_sdc_fb", -1, - res, ARRAY_SIZE(res), pdata, sizeof(*pdata), - DMA_BIT_MASK(32)); -} diff --git a/arch/arm/mach-imx/devices/platform-mx2-camera.c b/arch/arm/mach-imx/devices/platform-mx2-camera.c deleted file mode 100644 index 5375f8b3d079..000000000000 --- a/arch/arm/mach-imx/devices/platform-mx2-camera.c +++ /dev/null @@ -1,59 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2010 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - */ -#include "../hardware.h" -#include "devices-common.h" - -#define imx_mx2_camera_data_entry_single(soc, _devid) \ - { \ - .devid = _devid, \ - .iobasecsi = soc ## _CSI_BASE_ADDR, \ - .iosizecsi = SZ_4K, \ - .irqcsi = soc ## _INT_CSI, \ - } -#define imx_mx2_camera_data_entry_single_emma(soc, _devid) \ - { \ - .devid = _devid, \ - .iobasecsi = soc ## _CSI_BASE_ADDR, \ - .iosizecsi = SZ_32, \ - .irqcsi = soc ## _INT_CSI, \ - .iobaseemmaprp = soc ## _EMMAPRP_BASE_ADDR, \ - .iosizeemmaprp = SZ_32, \ - .irqemmaprp = soc ## _INT_EMMAPRP, \ - } - -#ifdef CONFIG_SOC_IMX27 -const struct imx_mx2_camera_data imx27_mx2_camera_data __initconst = - imx_mx2_camera_data_entry_single_emma(MX27, "imx27-camera"); -#endif /* ifdef CONFIG_SOC_IMX27 */ - -struct platform_device *__init imx_add_mx2_camera( - const struct imx_mx2_camera_data *data, - const struct mx2_camera_platform_data *pdata) -{ - struct resource res[] = { - { - .start = data->iobasecsi, - .end = data->iobasecsi + data->iosizecsi - 1, - .flags = IORESOURCE_MEM, - }, { - .start = data->irqcsi, - .end = data->irqcsi, - .flags = IORESOURCE_IRQ, - }, { - .start = data->iobaseemmaprp, - .end = data->iobaseemmaprp + data->iosizeemmaprp - 1, - .flags = IORESOURCE_MEM, - }, { - .start = data->irqemmaprp, - .end = data->irqemmaprp, - .flags = IORESOURCE_IRQ, - }, - }; - return imx_add_platform_device_dmamask(data->devid, 0, - res, data->iobaseemmaprp ? 4 : 2, - pdata, sizeof(*pdata), DMA_BIT_MASK(32)); -} - diff --git a/arch/arm/mach-imx/devices/platform-mx2-emma.c b/arch/arm/mach-imx/devices/platform-mx2-emma.c deleted file mode 100644 index 20f28ba16f36..000000000000 --- a/arch/arm/mach-imx/devices/platform-mx2-emma.c +++ /dev/null @@ -1,37 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2010 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - */ -#include "../hardware.h" -#include "devices-common.h" - -#define imx_mx2_emmaprp_data_entry_single(soc) \ - { \ - .iobase = soc ## _EMMAPRP_BASE_ADDR, \ - .iosize = SZ_256, \ - .irq = soc ## _INT_EMMAPRP, \ - } - -#ifdef CONFIG_SOC_IMX27 -const struct imx_mx2_emma_data imx27_mx2_emmaprp_data __initconst = - imx_mx2_emmaprp_data_entry_single(MX27); -#endif /* ifdef CONFIG_SOC_IMX27 */ - -struct platform_device *__init imx_add_mx2_emmaprp( - const struct imx_mx2_emma_data *data) -{ - struct resource res[] = { - { - .start = data->iobase, - .end = data->iobase + data->iosize - 1, - .flags = IORESOURCE_MEM, - }, { - .start = data->irq, - .end = data->irq, - .flags = IORESOURCE_IRQ, - }, - }; - return imx_add_platform_device_dmamask("m2m-emmaprp", 0, - res, 2, NULL, 0, DMA_BIT_MASK(32)); -} diff --git a/arch/arm/mach-imx/devices/platform-mxc-ehci.c b/arch/arm/mach-imx/devices/platform-mxc-ehci.c deleted file mode 100644 index d9d7cc71633f..000000000000 --- a/arch/arm/mach-imx/devices/platform-mxc-ehci.c +++ /dev/null @@ -1,61 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2010 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - */ -#include <linux/dma-mapping.h> - -#include "../hardware.h" -#include "devices-common.h" - -#define imx_mxc_ehci_data_entry_single(soc, _id, hs) \ - { \ - .id = _id, \ - .iobase = soc ## _USB_ ## hs ## _BASE_ADDR, \ - .irq = soc ## _INT_USB_ ## hs, \ - } - -#ifdef CONFIG_SOC_IMX27 -const struct imx_mxc_ehci_data imx27_mxc_ehci_otg_data __initconst = - imx_mxc_ehci_data_entry_single(MX27, 0, OTG); -const struct imx_mxc_ehci_data imx27_mxc_ehci_hs_data[] __initconst = { - imx_mxc_ehci_data_entry_single(MX27, 1, HS1), - imx_mxc_ehci_data_entry_single(MX27, 2, HS2), -}; -#endif /* ifdef CONFIG_SOC_IMX27 */ - -#ifdef CONFIG_SOC_IMX31 -const struct imx_mxc_ehci_data imx31_mxc_ehci_otg_data __initconst = - imx_mxc_ehci_data_entry_single(MX31, 0, OTG); -const struct imx_mxc_ehci_data imx31_mxc_ehci_hs_data[] __initconst = { - imx_mxc_ehci_data_entry_single(MX31, 1, HS1), - imx_mxc_ehci_data_entry_single(MX31, 2, HS2), -}; -#endif /* ifdef CONFIG_SOC_IMX31 */ - -#ifdef CONFIG_SOC_IMX35 -const struct imx_mxc_ehci_data imx35_mxc_ehci_otg_data __initconst = - imx_mxc_ehci_data_entry_single(MX35, 0, OTG); -const struct imx_mxc_ehci_data imx35_mxc_ehci_hs_data __initconst = - imx_mxc_ehci_data_entry_single(MX35, 1, HS); -#endif /* ifdef CONFIG_SOC_IMX35 */ - -struct platform_device *__init imx_add_mxc_ehci( - const struct imx_mxc_ehci_data *data, - const struct mxc_usbh_platform_data *pdata) -{ - struct resource res[] = { - { - .start = data->iobase, - .end = data->iobase + SZ_512 - 1, - .flags = IORESOURCE_MEM, - }, { - .start = data->irq, - .end = data->irq, - .flags = IORESOURCE_IRQ, - }, - }; - return imx_add_platform_device_dmamask("mxc-ehci", data->id, - res, ARRAY_SIZE(res), - pdata, sizeof(*pdata), DMA_BIT_MASK(32)); -} diff --git a/arch/arm/mach-imx/devices/platform-mxc-mmc.c b/arch/arm/mach-imx/devices/platform-mxc-mmc.c deleted file mode 100644 index cd4c502bc152..000000000000 --- a/arch/arm/mach-imx/devices/platform-mxc-mmc.c +++ /dev/null @@ -1,72 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2010 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - */ -#include <linux/dma-mapping.h> - -#include "../hardware.h" -#include "devices-common.h" - -#define imx_mxc_mmc_data_entry_single(soc, _devid, _id, _hwid, _size) \ - { \ - .devid = _devid, \ - .id = _id, \ - .iobase = soc ## _SDHC ## _hwid ## _BASE_ADDR, \ - .iosize = _size, \ - .irq = soc ## _INT_SDHC ## _hwid, \ - .dmareq = soc ## _DMA_REQ_SDHC ## _hwid, \ - } -#define imx_mxc_mmc_data_entry(soc, _devid, _id, _hwid, _size) \ - [_id] = imx_mxc_mmc_data_entry_single(soc, _devid, _id, _hwid, _size) - -#ifdef CONFIG_SOC_IMX21 -const struct imx_mxc_mmc_data imx21_mxc_mmc_data[] __initconst = { -#define imx21_mxc_mmc_data_entry(_id, _hwid) \ - imx_mxc_mmc_data_entry(MX21, "imx21-mmc", _id, _hwid, SZ_4K) - imx21_mxc_mmc_data_entry(0, 1), - imx21_mxc_mmc_data_entry(1, 2), -}; -#endif /* ifdef CONFIG_SOC_IMX21 */ - -#ifdef CONFIG_SOC_IMX27 -const struct imx_mxc_mmc_data imx27_mxc_mmc_data[] __initconst = { -#define imx27_mxc_mmc_data_entry(_id, _hwid) \ - imx_mxc_mmc_data_entry(MX27, "imx21-mmc", _id, _hwid, SZ_4K) - imx27_mxc_mmc_data_entry(0, 1), - imx27_mxc_mmc_data_entry(1, 2), -}; -#endif /* ifdef CONFIG_SOC_IMX27 */ - -#ifdef CONFIG_SOC_IMX31 -const struct imx_mxc_mmc_data imx31_mxc_mmc_data[] __initconst = { -#define imx31_mxc_mmc_data_entry(_id, _hwid) \ - imx_mxc_mmc_data_entry(MX31, "imx31-mmc", _id, _hwid, SZ_16K) - imx31_mxc_mmc_data_entry(0, 1), - imx31_mxc_mmc_data_entry(1, 2), -}; -#endif /* ifdef CONFIG_SOC_IMX31 */ - -struct platform_device *__init imx_add_mxc_mmc( - const struct imx_mxc_mmc_data *data, - const struct imxmmc_platform_data *pdata) -{ - struct resource res[] = { - { - .start = data->iobase, - .end = data->iobase + data->iosize - 1, - .flags = IORESOURCE_MEM, - }, { - .start = data->irq, - .end = data->irq, - .flags = IORESOURCE_IRQ, - }, { - .start = data->dmareq, - .end = data->dmareq, - .flags = IORESOURCE_DMA, - }, - }; - return imx_add_platform_device_dmamask(data->devid, data->id, - res, ARRAY_SIZE(res), - pdata, sizeof(*pdata), DMA_BIT_MASK(32)); -} diff --git a/arch/arm/mach-imx/devices/platform-mxc_nand.c b/arch/arm/mach-imx/devices/platform-mxc_nand.c deleted file mode 100644 index 0f5f741f897f..000000000000 --- a/arch/arm/mach-imx/devices/platform-mxc_nand.c +++ /dev/null @@ -1,72 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2009-2010 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - */ -#include <linux/sizes.h> - -#include "../hardware.h" -#include "devices-common.h" - -#define imx_mxc_nand_data_entry_single(soc, _devid, _size) \ - { \ - .devid = _devid, \ - .iobase = soc ## _NFC_BASE_ADDR, \ - .iosize = _size, \ - .irq = soc ## _INT_NFC \ - } - -#define imx_mxc_nandv3_data_entry_single(soc, _devid, _size) \ - { \ - .devid = _devid, \ - .id = -1, \ - .iobase = soc ## _NFC_BASE_ADDR, \ - .iosize = _size, \ - .axibase = soc ## _NFC_AXI_BASE_ADDR, \ - .irq = soc ## _INT_NFC \ - } - -#ifdef CONFIG_SOC_IMX21 -const struct imx_mxc_nand_data imx21_mxc_nand_data __initconst = - imx_mxc_nand_data_entry_single(MX21, "imx21-nand", SZ_4K); -#endif /* ifdef CONFIG_SOC_IMX21 */ - -#ifdef CONFIG_SOC_IMX27 -const struct imx_mxc_nand_data imx27_mxc_nand_data __initconst = - imx_mxc_nand_data_entry_single(MX27, "imx27-nand", SZ_4K); -#endif /* ifdef CONFIG_SOC_IMX27 */ - -#ifdef CONFIG_SOC_IMX31 -const struct imx_mxc_nand_data imx31_mxc_nand_data __initconst = - imx_mxc_nand_data_entry_single(MX31, "imx27-nand", SZ_4K); -#endif - -#ifdef CONFIG_SOC_IMX35 -const struct imx_mxc_nand_data imx35_mxc_nand_data __initconst = - imx_mxc_nand_data_entry_single(MX35, "imx25-nand", SZ_8K); -#endif - -struct platform_device *__init imx_add_mxc_nand( - const struct imx_mxc_nand_data *data, - const struct mxc_nand_platform_data *pdata) -{ - /* AXI has to come first, that's how the mxc_nand driver expect it */ - struct resource res[] = { - { - .start = data->iobase, - .end = data->iobase + data->iosize - 1, - .flags = IORESOURCE_MEM, - }, { - .start = data->irq, - .end = data->irq, - .flags = IORESOURCE_IRQ, - }, { - .start = data->axibase, - .end = data->axibase + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, - }; - return imx_add_platform_device(data->devid, data->id, - res, ARRAY_SIZE(res) - !data->axibase, - pdata, sizeof(*pdata)); -} diff --git a/arch/arm/mach-imx/devices/platform-mxc_rtc.c b/arch/arm/mach-imx/devices/platform-mxc_rtc.c deleted file mode 100644 index 0c746de1dd1d..000000000000 --- a/arch/arm/mach-imx/devices/platform-mxc_rtc.c +++ /dev/null @@ -1,43 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2010-2011 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - */ -#include "../hardware.h" -#include "devices-common.h" - -#define imx_mxc_rtc_data_entry_single(soc, _devid) \ - { \ - .devid = _devid, \ - .iobase = soc ## _RTC_BASE_ADDR, \ - .irq = soc ## _INT_RTC, \ - } - -#ifdef CONFIG_SOC_IMX31 -const struct imx_mxc_rtc_data imx31_mxc_rtc_data __initconst = - imx_mxc_rtc_data_entry_single(MX31, "imx21-rtc"); -#endif /* ifdef CONFIG_SOC_IMX31 */ - -#ifdef CONFIG_SOC_IMX35 -const struct imx_mxc_rtc_data imx35_mxc_rtc_data __initconst = - imx_mxc_rtc_data_entry_single(MX35, "imx21-rtc"); -#endif /* ifdef CONFIG_SOC_IMX35 */ - -struct platform_device *__init imx_add_mxc_rtc( - const struct imx_mxc_rtc_data *data) -{ - struct resource res[] = { - { - .start = data->iobase, - .end = data->iobase + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = data->irq, - .end = data->irq, - .flags = IORESOURCE_IRQ, - }, - }; - - return imx_add_platform_device(data->devid, -1, - res, ARRAY_SIZE(res), NULL, 0); -} diff --git a/arch/arm/mach-imx/devices/platform-mxc_w1.c b/arch/arm/mach-imx/devices/platform-mxc_w1.c deleted file mode 100644 index ab42c6b0542c..000000000000 --- a/arch/arm/mach-imx/devices/platform-mxc_w1.c +++ /dev/null @@ -1,47 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2010 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - */ -#include "../hardware.h" -#include "devices-common.h" - -#define imx_mxc_w1_data_entry_single(soc) \ - { \ - .iobase = soc ## _OWIRE_BASE_ADDR, \ - } - -#ifdef CONFIG_SOC_IMX21 -const struct imx_mxc_w1_data imx21_mxc_w1_data __initconst = - imx_mxc_w1_data_entry_single(MX21); -#endif /* ifdef CONFIG_SOC_IMX21 */ - -#ifdef CONFIG_SOC_IMX27 -const struct imx_mxc_w1_data imx27_mxc_w1_data __initconst = - imx_mxc_w1_data_entry_single(MX27); -#endif /* ifdef CONFIG_SOC_IMX27 */ - -#ifdef CONFIG_SOC_IMX31 -const struct imx_mxc_w1_data imx31_mxc_w1_data __initconst = - imx_mxc_w1_data_entry_single(MX31); -#endif /* ifdef CONFIG_SOC_IMX31 */ - -#ifdef CONFIG_SOC_IMX35 -const struct imx_mxc_w1_data imx35_mxc_w1_data __initconst = - imx_mxc_w1_data_entry_single(MX35); -#endif /* ifdef CONFIG_SOC_IMX35 */ - -struct platform_device *__init imx_add_mxc_w1( - const struct imx_mxc_w1_data *data) -{ - struct resource res[] = { - { - .start = data->iobase, - .end = data->iobase + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - }; - - return imx_add_platform_device("mxc_w1", 0, - res, ARRAY_SIZE(res), NULL, 0); -} diff --git a/arch/arm/mach-imx/devices/platform-pata_imx.c b/arch/arm/mach-imx/devices/platform-pata_imx.c deleted file mode 100644 index 0e985fffba78..000000000000 --- a/arch/arm/mach-imx/devices/platform-pata_imx.c +++ /dev/null @@ -1,45 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -#include "../hardware.h" -#include "devices-common.h" - -#define imx_pata_imx_data_entry_single(soc, _size) \ - { \ - .iobase = soc ## _ATA_BASE_ADDR, \ - .iosize = _size, \ - .irq = soc ## _INT_ATA, \ - } - -#ifdef CONFIG_SOC_IMX27 -const struct imx_pata_imx_data imx27_pata_imx_data __initconst = - imx_pata_imx_data_entry_single(MX27, SZ_4K); -#endif /* ifdef CONFIG_SOC_IMX27 */ - -#ifdef CONFIG_SOC_IMX31 -const struct imx_pata_imx_data imx31_pata_imx_data __initconst = - imx_pata_imx_data_entry_single(MX31, SZ_16K); -#endif /* ifdef CONFIG_SOC_IMX31 */ - -#ifdef CONFIG_SOC_IMX35 -const struct imx_pata_imx_data imx35_pata_imx_data __initconst = - imx_pata_imx_data_entry_single(MX35, SZ_16K); -#endif /* ifdef CONFIG_SOC_IMX35 */ - -struct platform_device *__init imx_add_pata_imx( - const struct imx_pata_imx_data *data) -{ - struct resource res[] = { - { - .start = data->iobase, - .end = data->iobase + data->iosize - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = data->irq, - .end = data->irq, - .flags = IORESOURCE_IRQ, - }, - }; - return imx_add_platform_device("pata_imx", -1, - res, ARRAY_SIZE(res), NULL, 0); -} - diff --git a/arch/arm/mach-imx/devices/platform-sdhci-esdhc-imx.c b/arch/arm/mach-imx/devices/platform-sdhci-esdhc-imx.c deleted file mode 100644 index 40c261071144..000000000000 --- a/arch/arm/mach-imx/devices/platform-sdhci-esdhc-imx.c +++ /dev/null @@ -1,64 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2010 Pengutronix, Wolfram Sang <kernel@pengutronix.de> - */ - -#include <linux/platform_data/mmc-esdhc-imx.h> - -#include "../hardware.h" -#include "devices-common.h" - -#define imx_sdhci_esdhc_imx_data_entry_single(soc, _devid, _id, hwid) \ - { \ - .devid = _devid, \ - .id = _id, \ - .iobase = soc ## _ESDHC ## hwid ## _BASE_ADDR, \ - .irq = soc ## _INT_ESDHC ## hwid, \ - } - -#define imx_sdhci_esdhc_imx_data_entry(soc, devid, id, hwid) \ - [id] = imx_sdhci_esdhc_imx_data_entry_single(soc, devid, id, hwid) - -#ifdef CONFIG_SOC_IMX35 -const struct imx_sdhci_esdhc_imx_data -imx35_sdhci_esdhc_imx_data[] __initconst = { -#define imx35_sdhci_esdhc_imx_data_entry(_id, _hwid) \ - imx_sdhci_esdhc_imx_data_entry(MX35, "sdhci-esdhc-imx35", _id, _hwid) - imx35_sdhci_esdhc_imx_data_entry(0, 1), - imx35_sdhci_esdhc_imx_data_entry(1, 2), - imx35_sdhci_esdhc_imx_data_entry(2, 3), -}; -#endif /* ifdef CONFIG_SOC_IMX35 */ - -static const struct esdhc_platform_data default_esdhc_pdata __initconst = { - .wp_type = ESDHC_WP_NONE, - .cd_type = ESDHC_CD_NONE, -}; - -struct platform_device *__init imx_add_sdhci_esdhc_imx( - const struct imx_sdhci_esdhc_imx_data *data, - const struct esdhc_platform_data *pdata) -{ - struct resource res[] = { - { - .start = data->iobase, - .end = data->iobase + SZ_16K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = data->irq, - .end = data->irq, - .flags = IORESOURCE_IRQ, - }, - }; - - /* - * If machine does not provide pdata, use the default one - * which means no WP/CD support - */ - if (!pdata) - pdata = &default_esdhc_pdata; - - return imx_add_platform_device_dmamask(data->devid, data->id, res, - ARRAY_SIZE(res), pdata, sizeof(*pdata), - DMA_BIT_MASK(32)); -} diff --git a/arch/arm/mach-imx/devices/platform-spi_imx.c b/arch/arm/mach-imx/devices/platform-spi_imx.c deleted file mode 100644 index 27747bf628a3..000000000000 --- a/arch/arm/mach-imx/devices/platform-spi_imx.c +++ /dev/null @@ -1,78 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2009-2010 Pengutronix - * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> - */ -#include <linux/gpio/machine.h> -#include "../hardware.h" -#include "devices-common.h" - -#define imx_spi_imx_data_entry_single(soc, type, _devid, _id, hwid, _size) \ - { \ - .devid = _devid, \ - .id = _id, \ - .iobase = soc ## _ ## type ## hwid ## _BASE_ADDR, \ - .iosize = _size, \ - .irq = soc ## _INT_ ## type ## hwid, \ - } - -#define imx_spi_imx_data_entry(soc, type, devid, id, hwid, size) \ - [id] = imx_spi_imx_data_entry_single(soc, type, devid, id, hwid, size) - -#ifdef CONFIG_SOC_IMX21 -const struct imx_spi_imx_data imx21_cspi_data[] __initconst = { -#define imx21_cspi_data_entry(_id, _hwid) \ - imx_spi_imx_data_entry(MX21, CSPI, "imx21-cspi", _id, _hwid, SZ_4K) - imx21_cspi_data_entry(0, 1), - imx21_cspi_data_entry(1, 2), -}; -#endif - -#ifdef CONFIG_SOC_IMX27 -const struct imx_spi_imx_data imx27_cspi_data[] __initconst = { -#define imx27_cspi_data_entry(_id, _hwid) \ - imx_spi_imx_data_entry(MX27, CSPI, "imx27-cspi", _id, _hwid, SZ_4K) - imx27_cspi_data_entry(0, 1), - imx27_cspi_data_entry(1, 2), - imx27_cspi_data_entry(2, 3), -}; -#endif /* ifdef CONFIG_SOC_IMX27 */ - -#ifdef CONFIG_SOC_IMX31 -const struct imx_spi_imx_data imx31_cspi_data[] __initconst = { -#define imx31_cspi_data_entry(_id, _hwid) \ - imx_spi_imx_data_entry(MX31, CSPI, "imx31-cspi", _id, _hwid, SZ_4K) - imx31_cspi_data_entry(0, 1), - imx31_cspi_data_entry(1, 2), - imx31_cspi_data_entry(2, 3), -}; -#endif /* ifdef CONFIG_SOC_IMX31 */ - -#ifdef CONFIG_SOC_IMX35 -const struct imx_spi_imx_data imx35_cspi_data[] __initconst = { -#define imx35_cspi_data_entry(_id, _hwid) \ - imx_spi_imx_data_entry(MX35, CSPI, "imx35-cspi", _id, _hwid, SZ_4K) - imx35_cspi_data_entry(0, 1), - imx35_cspi_data_entry(1, 2), -}; -#endif /* ifdef CONFIG_SOC_IMX35 */ - -struct platform_device *__init imx_add_spi_imx( - const struct imx_spi_imx_data *data, struct gpiod_lookup_table *gtable) -{ - struct resource res[] = { - { - .start = data->iobase, - .end = data->iobase + data->iosize - 1, - .flags = IORESOURCE_MEM, - }, { - .start = data->irq, - .end = data->irq, - .flags = IORESOURCE_IRQ, - }, - }; - if (gtable) - gpiod_add_lookup_table(gtable); - return imx_add_platform_device(data->devid, data->id, - res, ARRAY_SIZE(res), NULL, 0); -} diff --git a/arch/arm/mach-imx/ehci-imx27.c b/arch/arm/mach-imx/ehci-imx27.c deleted file mode 100644 index 83962ce75983..000000000000 --- a/arch/arm/mach-imx/ehci-imx27.c +++ /dev/null @@ -1,74 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de> - * Copyright (C) 2010 Freescale Semiconductor, Inc. - */ - -#include <linux/platform_device.h> -#include <linux/io.h> -#include <linux/platform_data/usb-ehci-mxc.h> - -#include "ehci.h" -#include "hardware.h" - -#define USBCTRL_OTGBASE_OFFSET 0x600 - -#define MX27_OTG_SIC_SHIFT 29 -#define MX27_OTG_SIC_MASK (0x3 << MX27_OTG_SIC_SHIFT) -#define MX27_OTG_PM_BIT (1 << 24) - -#define MX27_H2_SIC_SHIFT 21 -#define MX27_H2_SIC_MASK (0x3 << MX27_H2_SIC_SHIFT) -#define MX27_H2_PM_BIT (1 << 16) -#define MX27_H2_DT_BIT (1 << 5) - -#define MX27_H1_SIC_SHIFT 13 -#define MX27_H1_SIC_MASK (0x3 << MX27_H1_SIC_SHIFT) -#define MX27_H1_PM_BIT (1 << 8) -#define MX27_H1_DT_BIT (1 << 4) - -int mx27_initialize_usb_hw(int port, unsigned int flags) -{ - unsigned int v; - - v = readl(MX27_IO_ADDRESS(MX27_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); - - switch (port) { - case 0: /* OTG port */ - v &= ~(MX27_OTG_SIC_MASK | MX27_OTG_PM_BIT); - v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX27_OTG_SIC_SHIFT; - - if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) - v |= MX27_OTG_PM_BIT; - break; - case 1: /* H1 port */ - v &= ~(MX27_H1_SIC_MASK | MX27_H1_PM_BIT | MX27_H1_DT_BIT); - v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX27_H1_SIC_SHIFT; - - if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) - v |= MX27_H1_PM_BIT; - - if (!(flags & MXC_EHCI_TTL_ENABLED)) - v |= MX27_H1_DT_BIT; - - break; - case 2: /* H2 port */ - v &= ~(MX27_H2_SIC_MASK | MX27_H2_PM_BIT | MX27_H2_DT_BIT); - v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX27_H2_SIC_SHIFT; - - if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) - v |= MX27_H2_PM_BIT; - - if (!(flags & MXC_EHCI_TTL_ENABLED)) - v |= MX27_H2_DT_BIT; - - break; - default: - return -EINVAL; - } - - writel(v, MX27_IO_ADDRESS(MX27_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); - - return 0; -} - diff --git a/arch/arm/mach-imx/ehci-imx31.c b/arch/arm/mach-imx/ehci-imx31.c deleted file mode 100644 index d6d794d53a63..000000000000 --- a/arch/arm/mach-imx/ehci-imx31.c +++ /dev/null @@ -1,74 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de> - * Copyright (C) 2010 Freescale Semiconductor, Inc. - */ - -#include <linux/platform_device.h> -#include <linux/io.h> -#include <linux/platform_data/usb-ehci-mxc.h> - -#include "ehci.h" -#include "hardware.h" - -#define USBCTRL_OTGBASE_OFFSET 0x600 - -#define MX31_OTG_SIC_SHIFT 29 -#define MX31_OTG_SIC_MASK (0x3 << MX31_OTG_SIC_SHIFT) -#define MX31_OTG_PM_BIT (1 << 24) - -#define MX31_H2_SIC_SHIFT 21 -#define MX31_H2_SIC_MASK (0x3 << MX31_H2_SIC_SHIFT) -#define MX31_H2_PM_BIT (1 << 16) -#define MX31_H2_DT_BIT (1 << 5) - -#define MX31_H1_SIC_SHIFT 13 -#define MX31_H1_SIC_MASK (0x3 << MX31_H1_SIC_SHIFT) -#define MX31_H1_PM_BIT (1 << 8) -#define MX31_H1_DT_BIT (1 << 4) - -int mx31_initialize_usb_hw(int port, unsigned int flags) -{ - unsigned int v; - - v = readl(MX31_IO_ADDRESS(MX31_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); - - switch (port) { - case 0: /* OTG port */ - v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT); - v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_OTG_SIC_SHIFT; - - if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) - v |= MX31_OTG_PM_BIT; - - break; - case 1: /* H1 port */ - v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT | MX31_H1_DT_BIT); - v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H1_SIC_SHIFT; - - if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) - v |= MX31_H1_PM_BIT; - - if (!(flags & MXC_EHCI_TTL_ENABLED)) - v |= MX31_H1_DT_BIT; - - break; - case 2: /* H2 port */ - v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT | MX31_H2_DT_BIT); - v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H2_SIC_SHIFT; - - if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) - v |= MX31_H2_PM_BIT; - - if (!(flags & MXC_EHCI_TTL_ENABLED)) - v |= MX31_H2_DT_BIT; - - break; - default: - return -EINVAL; - } - - writel(v, MX31_IO_ADDRESS(MX31_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); - - return 0; -} diff --git a/arch/arm/mach-imx/ehci-imx35.c b/arch/arm/mach-imx/ehci-imx35.c deleted file mode 100644 index e6ba965c5c5b..000000000000 --- a/arch/arm/mach-imx/ehci-imx35.c +++ /dev/null @@ -1,89 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de> - * Copyright (C) 2010 Freescale Semiconductor, Inc. - */ - -#include <linux/platform_device.h> -#include <linux/io.h> -#include <linux/platform_data/usb-ehci-mxc.h> - -#include "ehci.h" -#include "hardware.h" - -#define USBCTRL_OTGBASE_OFFSET 0x600 - -#define MX35_OTG_SIC_SHIFT 29 -#define MX35_OTG_SIC_MASK (0x3 << MX35_OTG_SIC_SHIFT) -#define MX35_OTG_PM_BIT (1 << 24) -#define MX35_OTG_PP_BIT (1 << 11) -#define MX35_OTG_OCPOL_BIT (1 << 3) - -#define MX35_H1_SIC_SHIFT 21 -#define MX35_H1_SIC_MASK (0x3 << MX35_H1_SIC_SHIFT) -#define MX35_H1_PP_BIT (1 << 18) -#define MX35_H1_PM_BIT (1 << 16) -#define MX35_H1_IPPUE_UP_BIT (1 << 7) -#define MX35_H1_IPPUE_DOWN_BIT (1 << 6) -#define MX35_H1_TLL_BIT (1 << 5) -#define MX35_H1_USBTE_BIT (1 << 4) -#define MX35_H1_OCPOL_BIT (1 << 2) - -int mx35_initialize_usb_hw(int port, unsigned int flags) -{ - unsigned int v; - - v = readl(MX35_IO_ADDRESS(MX35_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); - - switch (port) { - case 0: /* OTG port */ - v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT | MX35_OTG_PP_BIT | - MX35_OTG_OCPOL_BIT); - v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_OTG_SIC_SHIFT; - - if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) - v |= MX35_OTG_PM_BIT; - - if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) - v |= MX35_OTG_PP_BIT; - - if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)) - v |= MX35_OTG_OCPOL_BIT; - - break; - case 1: /* H1 port */ - v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_PP_BIT | - MX35_H1_OCPOL_BIT | MX35_H1_TLL_BIT | MX35_H1_USBTE_BIT | - MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT); - v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_H1_SIC_SHIFT; - - if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) - v |= MX35_H1_PM_BIT; - - if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) - v |= MX35_H1_PP_BIT; - - if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)) - v |= MX35_H1_OCPOL_BIT; - - if (!(flags & MXC_EHCI_TTL_ENABLED)) - v |= MX35_H1_TLL_BIT; - - if (flags & MXC_EHCI_INTERNAL_PHY) - v |= MX35_H1_USBTE_BIT; - - if (flags & MXC_EHCI_IPPUE_DOWN) - v |= MX35_H1_IPPUE_DOWN_BIT; - - if (flags & MXC_EHCI_IPPUE_UP) - v |= MX35_H1_IPPUE_UP_BIT; - - break; - default: - return -EINVAL; - } - - writel(v, MX35_IO_ADDRESS(MX35_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); - - return 0; -} diff --git a/arch/arm/mach-imx/ehci.h b/arch/arm/mach-imx/ehci.h deleted file mode 100644 index b7ad6175f5bf..000000000000 --- a/arch/arm/mach-imx/ehci.h +++ /dev/null @@ -1,44 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __MACH_IMX_EHCI_H -#define __MACH_IMX_EHCI_H - -/* values for portsc field */ -#define MXC_EHCI_PHY_LOW_POWER_SUSPEND (1 << 23) -#define MXC_EHCI_FORCE_FS (1 << 24) -#define MXC_EHCI_UTMI_8BIT (0 << 28) -#define MXC_EHCI_UTMI_16BIT (1 << 28) -#define MXC_EHCI_SERIAL (1 << 29) -#define MXC_EHCI_MODE_UTMI (0 << 30) -#define MXC_EHCI_MODE_PHILIPS (1 << 30) -#define MXC_EHCI_MODE_ULPI (2 << 30) -#define MXC_EHCI_MODE_SERIAL (3 << 30) - -/* values for flags field */ -#define MXC_EHCI_INTERFACE_DIFF_UNI (0 << 0) -#define MXC_EHCI_INTERFACE_DIFF_BI (1 << 0) -#define MXC_EHCI_INTERFACE_SINGLE_UNI (2 << 0) -#define MXC_EHCI_INTERFACE_SINGLE_BI (3 << 0) -#define MXC_EHCI_INTERFACE_MASK (0xf) - -#define MXC_EHCI_POWER_PINS_ENABLED (1 << 5) -#define MXC_EHCI_PWR_PIN_ACTIVE_HIGH (1 << 6) -#define MXC_EHCI_OC_PIN_ACTIVE_LOW (1 << 7) -#define MXC_EHCI_TTL_ENABLED (1 << 8) - -#define MXC_EHCI_INTERNAL_PHY (1 << 9) -#define MXC_EHCI_IPPUE_DOWN (1 << 10) -#define MXC_EHCI_IPPUE_UP (1 << 11) -#define MXC_EHCI_WAKEUP_ENABLED (1 << 12) -#define MXC_EHCI_ITC_NO_THRESHOLD (1 << 13) - -#define MXC_USBCTRL_OFFSET 0 -#define MXC_USB_PHY_CTR_FUNC_OFFSET 0x8 -#define MXC_USB_PHY_CTR_FUNC2_OFFSET 0xc -#define MXC_USBH2CTRL_OFFSET 0x14 - -int mx25_initialize_usb_hw(int port, unsigned int flags); -int mx31_initialize_usb_hw(int port, unsigned int flags); -int mx35_initialize_usb_hw(int port, unsigned int flags); -int mx27_initialize_usb_hw(int port, unsigned int flags); - -#endif /* __MACH_IMX_EHCI_H */ diff --git a/arch/arm/mach-imx/hardware.h b/arch/arm/mach-imx/hardware.h index 92c5a9c9f94b..7acf7ce467ed 100644 --- a/arch/arm/mach-imx/hardware.h +++ b/arch/arm/mach-imx/hardware.h @@ -97,7 +97,6 @@ #include "mx31.h" #include "mx35.h" #include "mx2x.h" -#include "mx21.h" #include "mx27.h" #define imx_map_entry(soc, name, _type) { \ diff --git a/arch/arm/mach-imx/imx27-dt.c b/arch/arm/mach-imx/imx27-dt.c deleted file mode 100644 index 29d97bd64381..000000000000 --- a/arch/arm/mach-imx/imx27-dt.c +++ /dev/null @@ -1,26 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2012 Sascha Hauer, Pengutronix - */ - -#include <linux/irq.h> -#include <linux/of_irq.h> -#include <linux/of_platform.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> - -#include "common.h" -#include "mx27.h" - -static const char * const imx27_dt_board_compat[] __initconst = { - "fsl,imx27", - NULL -}; - -DT_MACHINE_START(IMX27_DT, "Freescale i.MX27 (Device Tree Support)") - .map_io = mx27_map_io, - .init_early = imx27_init_early, - .init_irq = mx27_init_irq, - .init_late = imx27_pm_init, - .dt_compat = imx27_dt_board_compat, -MACHINE_END diff --git a/arch/arm/mach-imx/iomux-imx31.c b/arch/arm/mach-imx/iomux-imx31.c deleted file mode 100644 index abfc306655c8..000000000000 --- a/arch/arm/mach-imx/iomux-imx31.c +++ /dev/null @@ -1,161 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> - * Copyright (C) 2009 by Valentin Longchamp <valentin.longchamp@epfl.ch> - */ -#include <linux/gpio.h> -#include <linux/module.h> -#include <linux/spinlock.h> -#include <linux/io.h> -#include <linux/kernel.h> - -#include "hardware.h" -#include "iomux-mx3.h" - -/* - * IOMUX register (base) addresses - */ -#define IOMUX_BASE MX31_IO_ADDRESS(MX31_IOMUXC_BASE_ADDR) -#define IOMUXINT_OBS1 (IOMUX_BASE + 0x000) -#define IOMUXINT_OBS2 (IOMUX_BASE + 0x004) -#define IOMUXGPR (IOMUX_BASE + 0x008) -#define IOMUXSW_MUX_CTL (IOMUX_BASE + 0x00C) -#define IOMUXSW_PAD_CTL (IOMUX_BASE + 0x154) - -static DEFINE_SPINLOCK(gpio_mux_lock); - -#define IOMUX_REG_MASK (IOMUX_PADNUM_MASK & ~0x3) - -static DECLARE_BITMAP(mxc_pin_alloc_map, NB_PORTS * 32); -/* - * set the mode for a IOMUX pin. - */ -void mxc_iomux_mode(unsigned int pin_mode) -{ - u32 field; - u32 l; - u32 mode; - void __iomem *reg; - - reg = IOMUXSW_MUX_CTL + (pin_mode & IOMUX_REG_MASK); - field = pin_mode & 0x3; - mode = (pin_mode & IOMUX_MODE_MASK) >> IOMUX_MODE_SHIFT; - - spin_lock(&gpio_mux_lock); - - l = imx_readl(reg); - l &= ~(0xff << (field * 8)); - l |= mode << (field * 8); - imx_writel(l, reg); - - spin_unlock(&gpio_mux_lock); -} - -/* - * This function configures the pad value for a IOMUX pin. - */ -void mxc_iomux_set_pad(enum iomux_pins pin, u32 config) -{ - u32 field, l; - void __iomem *reg; - - pin &= IOMUX_PADNUM_MASK; - reg = IOMUXSW_PAD_CTL + (pin + 2) / 3 * 4; - field = (pin + 2) % 3; - - pr_debug("%s: reg offset = 0x%x, field = %d\n", - __func__, (pin + 2) / 3, field); - - spin_lock(&gpio_mux_lock); - - l = imx_readl(reg); - l &= ~(0x1ff << (field * 10)); - l |= config << (field * 10); - imx_writel(l, reg); - - spin_unlock(&gpio_mux_lock); -} - -/* - * allocs a single pin: - * - reserves the pin so that it is not claimed by another driver - * - setups the iomux according to the configuration - */ -int mxc_iomux_alloc_pin(unsigned int pin, const char *label) -{ - unsigned pad = pin & IOMUX_PADNUM_MASK; - - if (pad >= (PIN_MAX + 1)) { - printk(KERN_ERR "mxc_iomux: Attempt to request nonexistent pin %u for \"%s\"\n", - pad, label ? label : "?"); - return -EINVAL; - } - - if (test_and_set_bit(pad, mxc_pin_alloc_map)) { - printk(KERN_ERR "mxc_iomux: pin %u already used. Allocation for \"%s\" failed\n", - pad, label ? label : "?"); - return -EBUSY; - } - mxc_iomux_mode(pin); - - return 0; -} - -int mxc_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count, - const char *label) -{ - const unsigned int *p = pin_list; - int i; - int ret = -EINVAL; - - for (i = 0; i < count; i++) { - ret = mxc_iomux_alloc_pin(*p, label); - if (ret) - goto setup_error; - p++; - } - return 0; - -setup_error: - mxc_iomux_release_multiple_pins(pin_list, i); - return ret; -} - -void mxc_iomux_release_pin(unsigned int pin) -{ - unsigned pad = pin & IOMUX_PADNUM_MASK; - - if (pad < (PIN_MAX + 1)) - clear_bit(pad, mxc_pin_alloc_map); -} - -void mxc_iomux_release_multiple_pins(const unsigned int *pin_list, int count) -{ - const unsigned int *p = pin_list; - int i; - - for (i = 0; i < count; i++) { - mxc_iomux_release_pin(*p); - p++; - } -} - -/* - * This function enables/disables the general purpose function for a particular - * signal. - */ -void mxc_iomux_set_gpr(enum iomux_gp_func gp, bool en) -{ - u32 l; - - spin_lock(&gpio_mux_lock); - l = imx_readl(IOMUXGPR); - if (en) - l |= gp; - else - l &= ~gp; - - imx_writel(l, IOMUXGPR); - spin_unlock(&gpio_mux_lock); -} diff --git a/arch/arm/mach-imx/iomux-mx21.h b/arch/arm/mach-imx/iomux-mx21.h deleted file mode 100644 index 6eab3478fb80..000000000000 --- a/arch/arm/mach-imx/iomux-mx21.h +++ /dev/null @@ -1,109 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de> - */ -#ifndef __MACH_IOMUX_MX21_H__ -#define __MACH_IOMUX_MX21_H__ - -#include "iomux-mx2x.h" -#include "iomux-v1.h" - -/* Primary GPIO pin functions */ - -#define PB22_PF_USBH1_BYP (GPIO_PORTB | GPIO_PF | 22) -#define PB25_PF_USBH1_ON (GPIO_PORTB | GPIO_PF | 25) -#define PC5_PF_USBOTG_SDA (GPIO_PORTC | GPIO_PF | 5) -#define PC6_PF_USBOTG_SCL (GPIO_PORTC | GPIO_PF | 6) -#define PC7_PF_USBOTG_ON (GPIO_PORTC | GPIO_PF | 7) -#define PC8_PF_USBOTG_FS (GPIO_PORTC | GPIO_PF | 8) -#define PC9_PF_USBOTG_OE (GPIO_PORTC | GPIO_PF | 9) -#define PC10_PF_USBOTG_TXDM (GPIO_PORTC | GPIO_PF | 10) -#define PC11_PF_USBOTG_TXDP (GPIO_PORTC | GPIO_PF | 11) -#define PC12_PF_USBOTG_RXDM (GPIO_PORTC | GPIO_PF | 12) -#define PC13_PF_USBOTG_RXDP (GPIO_PORTC | GPIO_PF | 13) -#define PC16_PF_SAP_FS (GPIO_PORTC | GPIO_PF | 16) -#define PC17_PF_SAP_RXD (GPIO_PORTC | GPIO_PF | 17) -#define PC18_PF_SAP_TXD (GPIO_PORTC | GPIO_PF | 18) -#define PC19_PF_SAP_CLK (GPIO_PORTC | GPIO_PF | 19) -#define PE0_PF_TEST_WB2 (GPIO_PORTE | GPIO_PF | 0) -#define PE1_PF_TEST_WB1 (GPIO_PORTE | GPIO_PF | 1) -#define PE2_PF_TEST_WB0 (GPIO_PORTE | GPIO_PF | 2) -#define PF1_PF_NFCE (GPIO_PORTF | GPIO_PF | 1) -#define PF3_PF_NFCLE (GPIO_PORTF | GPIO_PF | 3) -#define PF7_PF_NFIO0 (GPIO_PORTF | GPIO_PF | 7) -#define PF8_PF_NFIO1 (GPIO_PORTF | GPIO_PF | 8) -#define PF9_PF_NFIO2 (GPIO_PORTF | GPIO_PF | 9) -#define PF10_PF_NFIO3 (GPIO_PORTF | GPIO_PF | 10) -#define PF11_PF_NFIO4 (GPIO_PORTF | GPIO_PF | 11) -#define PF12_PF_NFIO5 (GPIO_PORTF | GPIO_PF | 12) -#define PF13_PF_NFIO6 (GPIO_PORTF | GPIO_PF | 13) -#define PF14_PF_NFIO7 (GPIO_PORTF | GPIO_PF | 14) -#define PF16_PF_RES (GPIO_PORTF | GPIO_PF | 16) - -/* Alternate GPIO pin functions */ - -#define PA5_AF_BMI_CLK_CS (GPIO_PORTA | GPIO_AF | 5) -#define PA6_AF_BMI_D0 (GPIO_PORTA | GPIO_AF | 6) -#define PA7_AF_BMI_D1 (GPIO_PORTA | GPIO_AF | 7) -#define PA8_AF_BMI_D2 (GPIO_PORTA | GPIO_AF | 8) -#define PA9_AF_BMI_D3 (GPIO_PORTA | GPIO_AF | 9) -#define PA10_AF_BMI_D4 (GPIO_PORTA | GPIO_AF | 10) -#define PA11_AF_BMI_D5 (GPIO_PORTA | GPIO_AF | 11) -#define PA12_AF_BMI_D6 (GPIO_PORTA | GPIO_AF | 12) -#define PA13_AF_BMI_D7 (GPIO_PORTA | GPIO_AF | 13) -#define PA14_AF_BMI_D8 (GPIO_PORTA | GPIO_AF | 14) -#define PA15_AF_BMI_D9 (GPIO_PORTA | GPIO_AF | 15) -#define PA16_AF_BMI_D10 (GPIO_PORTA | GPIO_AF | 16) -#define PA17_AF_BMI_D11 (GPIO_PORTA | GPIO_AF | 17) -#define PA18_AF_BMI_D12 (GPIO_PORTA | GPIO_AF | 18) -#define PA19_AF_BMI_D13 (GPIO_PORTA | GPIO_AF | 19) -#define PA20_AF_BMI_D14 (GPIO_PORTA | GPIO_AF | 20) -#define PA21_AF_BMI_D15 (GPIO_PORTA | GPIO_AF | 21) -#define PA22_AF_BMI_READ_REQ (GPIO_PORTA | GPIO_AF | 22) -#define PA23_AF_BMI_WRITE (GPIO_PORTA | GPIO_AF | 23) -#define PA29_AF_BMI_RX_FULL (GPIO_PORTA | GPIO_AF | 29) -#define PA30_AF_BMI_READ (GPIO_PORTA | GPIO_AF | 30) - -/* AIN GPIO pin functions */ - -#define PC14_AIN_SYS_CLK (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 14) -#define PD21_AIN_USBH2_FS (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 21) -#define PD22_AIN_USBH2_OE (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 22) -#define PD23_AIN_USBH2_TXDM (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 23) -#define PD24_AIN_USBH2_TXDP (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 24) -#define PE8_AIN_IR_TXD (GPIO_PORTE | GPIO_AIN | GPIO_OUT | 8) -#define PF0_AIN_PC_RST (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 0) -#define PF1_AIN_PC_CE1 (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 1) -#define PF2_AIN_PC_CE2 (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 2) -#define PF3_AIN_PC_POE (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 3) -#define PF4_AIN_PC_OE (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 4) -#define PF5_AIN_PC_RW (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 5) - -/* BIN GPIO pin functions */ - -#define PC14_BIN_SYS_CLK (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 14) -#define PD27_BIN_EXT_DMA_GRANT (GPIO_PORTD | GPIO_BIN | GPIO_OUT | 27) - -/* CIN GPIO pin functions */ - -#define PB26_CIN_USBH1_RXDAT (GPIO_PORTB | GPIO_CIN | GPIO_OUT | 26) - -/* AOUT GPIO pin functions */ - -#define PA29_AOUT_BMI_WAIT (GPIO_PORTA | GPIO_AOUT | GPIO_IN | 29) -#define PD19_AOUT_USBH2_RXDM (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 19) -#define PD20_AOUT_USBH2_RXDP (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 20) -#define PD25_AOUT_EXT_DMAREQ (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 25) -#define PD26_AOUT_USBOTG_RXDAT (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 26) -#define PE9_AOUT_IR_RXD (GPIO_PORTE | GPIO_AOUT | GPIO_IN | 9) -#define PF6_AOUT_PC_BVD2 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 6) -#define PF7_AOUT_PC_BVD1 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 7) -#define PF8_AOUT_PC_VS2 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 8) -#define PF9_AOUT_PC_VS1 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 9) -#define PF10_AOUT_PC_WP (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 10) -#define PF11_AOUT_PC_READY (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 11) -#define PF12_AOUT_PC_WAIT (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 12) -#define PF13_AOUT_PC_CD2 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 13) -#define PF14_AOUT_PC_CD1 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 14) - -#endif /* ifndef __MACH_IOMUX_MX21_H__ */ diff --git a/arch/arm/mach-imx/iomux-mx27.h b/arch/arm/mach-imx/iomux-mx27.h deleted file mode 100644 index 4d848d1ef1e3..000000000000 --- a/arch/arm/mach-imx/iomux-mx27.h +++ /dev/null @@ -1,192 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> - * Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de> - */ -#ifndef __MACH_IOMUX_MX27_H__ -#define __MACH_IOMUX_MX27_H__ - -#include "iomux-mx2x.h" -#include "iomux-v1.h" - -/* Primary GPIO pin functions */ - -#define PA0_PF_USBH2_CLK (GPIO_PORTA | GPIO_PF | 0) -#define PA1_PF_USBH2_DIR (GPIO_PORTA | GPIO_PF | 1) -#define PA2_PF_USBH2_DATA7 (GPIO_PORTA | GPIO_PF | 2) -#define PA3_PF_USBH2_NXT (GPIO_PORTA | GPIO_PF | 3) -#define PA4_PF_USBH2_STP (GPIO_PORTA | GPIO_PF | 4) -#define PB22_PF_USBH1_SUSP (GPIO_PORTB | GPIO_PF | 22) -#define PB25_PF_USBH1_RCV (GPIO_PORTB | GPIO_PF | 25) -#define PC5_PF_I2C2_SDA (GPIO_PORTC | GPIO_PF | GPIO_IN | 5) -#define PC6_PF_I2C2_SCL (GPIO_PORTC | GPIO_PF | GPIO_IN | 6) -#define PC7_PF_USBOTG_DATA5 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 7) -#define PC8_PF_USBOTG_DATA6 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 8) -#define PC9_PF_USBOTG_DATA0 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 9) -#define PC10_PF_USBOTG_DATA2 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 10) -#define PC11_PF_USBOTG_DATA1 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 11) -#define PC12_PF_USBOTG_DATA4 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 12) -#define PC13_PF_USBOTG_DATA3 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 13) -#define PC16_PF_SSI4_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 16) -#define PC17_PF_SSI4_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 17) -#define PC18_PF_SSI4_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 18) -#define PC19_PF_SSI4_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 19) -#define PD0_PF_SD3_CMD (GPIO_PORTD | GPIO_PF | 0) -#define PD1_PF_SD3_CLK (GPIO_PORTD | GPIO_PF | 1) -#define PD2_PF_ATA_DATA0 (GPIO_PORTD | GPIO_PF | 2) -#define PD3_PF_ATA_DATA1 (GPIO_PORTD | GPIO_PF | 3) -#define PD4_PF_ATA_DATA2 (GPIO_PORTD | GPIO_PF | 4) -#define PD5_PF_ATA_DATA3 (GPIO_PORTD | GPIO_PF | 5) -#define PD6_PF_ATA_DATA4 (GPIO_PORTD | GPIO_PF | 6) -#define PD7_PF_ATA_DATA5 (GPIO_PORTD | GPIO_PF | 7) -#define PD8_PF_ATA_DATA6 (GPIO_PORTD | GPIO_PF | 8) -#define PD9_PF_ATA_DATA7 (GPIO_PORTD | GPIO_PF | 9) -#define PD10_PF_ATA_DATA8 (GPIO_PORTD | GPIO_PF | 10) -#define PD11_PF_ATA_DATA9 (GPIO_PORTD | GPIO_PF | 11) -#define PD12_PF_ATA_DATA10 (GPIO_PORTD | GPIO_PF | 12) -#define PD13_PF_ATA_DATA11 (GPIO_PORTD | GPIO_PF | 13) -#define PD14_PF_ATA_DATA12 (GPIO_PORTD | GPIO_PF | 14) -#define PD15_PF_ATA_DATA13 (GPIO_PORTD | GPIO_PF | 15) -#define PD16_PF_ATA_DATA14 (GPIO_PORTD | GPIO_PF | 16) -#define PE0_PF_USBOTG_NXT (GPIO_PORTE | GPIO_PF | GPIO_OUT | 0) -#define PE1_PF_USBOTG_STP (GPIO_PORTE | GPIO_PF | GPIO_OUT | 1) -#define PE2_PF_USBOTG_DIR (GPIO_PORTE | GPIO_PF | GPIO_OUT | 2) -#define PE24_PF_USBOTG_CLK (GPIO_PORTE | GPIO_PF | GPIO_OUT | 24) -#define PE25_PF_USBOTG_DATA7 (GPIO_PORTE | GPIO_PF | GPIO_OUT | 25) -#define PF1_PF_NFCLE (GPIO_PORTF | GPIO_PF | 1) -#define PF3_PF_NFCE (GPIO_PORTF | GPIO_PF | 3) -#define PF7_PF_PC_POE (GPIO_PORTF | GPIO_PF | 7) -#define PF8_PF_PC_RW (GPIO_PORTF | GPIO_PF | 8) -#define PF9_PF_PC_IOIS16 (GPIO_PORTF | GPIO_PF | 9) -#define PF10_PF_PC_RST (GPIO_PORTF | GPIO_PF | 10) -#define PF11_PF_PC_BVD2 (GPIO_PORTF | GPIO_PF | 11) -#define PF12_PF_PC_BVD1 (GPIO_PORTF | GPIO_PF | 12) -#define PF13_PF_PC_VS2 (GPIO_PORTF | GPIO_PF | 13) -#define PF14_PF_PC_VS1 (GPIO_PORTF | GPIO_PF | 14) -#define PF16_PF_PC_PWRON (GPIO_PORTF | GPIO_PF | 16) -#define PF17_PF_PC_READY (GPIO_PORTF | GPIO_PF | 17) -#define PF18_PF_PC_WAIT (GPIO_PORTF | GPIO_PF | 18) -#define PF19_PF_PC_CD2 (GPIO_PORTF | GPIO_PF | 19) -#define PF20_PF_PC_CD1 (GPIO_PORTF | GPIO_PF | 20) -#define PF23_PF_ATA_DATA15 (GPIO_PORTF | GPIO_PF | 23) - -/* Alternate GPIO pin functions */ - -#define PB4_AF_MSHC_DATA0 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 4) -#define PB5_AF_MSHC_DATA1 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 5) -#define PB6_AF_MSHC_DATA2 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 6) -#define PB7_AF_MSHC_DATA4 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 7) -#define PB8_AF_MSHC_BS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 8) -#define PB9_AF_MSHC_SCLK (GPIO_PORTB | GPIO_AF | GPIO_OUT | 9) -#define PB10_AF_UART6_TXD (GPIO_PORTB | GPIO_AF | GPIO_OUT | 10) -#define PB11_AF_UART6_RXD (GPIO_PORTB | GPIO_AF | GPIO_IN | 11) -#define PB12_AF_UART6_CTS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 12) -#define PB13_AF_UART6_RTS (GPIO_PORTB | GPIO_AF | GPIO_IN | 13) -#define PB18_AF_UART5_TXD (GPIO_PORTB | GPIO_AF | GPIO_OUT | 18) -#define PB19_AF_UART5_RXD (GPIO_PORTB | GPIO_AF | GPIO_IN | 19) -#define PB20_AF_UART5_CTS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 20) -#define PB21_AF_UART5_RTS (GPIO_PORTB | GPIO_AF | GPIO_IN | 21) -#define PC8_AF_FEC_MDIO (GPIO_PORTC | GPIO_AF | GPIO_IN | 8) -#define PC24_AF_GPT5_TOUT (GPIO_PORTC | GPIO_AF | 24) -#define PC25_AF_GPT5_TIN (GPIO_PORTC | GPIO_AF | 25) -#define PC26_AF_GPT4_TOUT (GPIO_PORTC | GPIO_AF | 26) -#define PC27_AF_GPT4_TIN (GPIO_PORTC | GPIO_AF | 27) -#define PD1_AF_ETMTRACE_PKT15 (GPIO_PORTD | GPIO_AF | 1) -#define PD6_AF_ETMTRACE_PKT14 (GPIO_PORTD | GPIO_AF | 6) -#define PD7_AF_ETMTRACE_PKT13 (GPIO_PORTD | GPIO_AF | 7) -#define PD9_AF_ETMTRACE_PKT12 (GPIO_PORTD | GPIO_AF | 9) -#define PD2_AF_SD3_D0 (GPIO_PORTD | GPIO_AF | 2) -#define PD3_AF_SD3_D1 (GPIO_PORTD | GPIO_AF | 3) -#define PD4_AF_SD3_D2 (GPIO_PORTD | GPIO_AF | 4) -#define PD5_AF_SD3_D3 (GPIO_PORTD | GPIO_AF | 5) -#define PD8_AF_FEC_MDIO (GPIO_PORTD | GPIO_AF | GPIO_IN | 8) -#define PD10_AF_ETMTRACE_PKT11 (GPIO_PORTD | GPIO_AF | 10) -#define PD11_AF_ETMTRACE_PKT10 (GPIO_PORTD | GPIO_AF | 11) -#define PD12_AF_ETMTRACE_PKT9 (GPIO_PORTD | GPIO_AF | 12) -#define PD13_AF_ETMTRACE_PKT8 (GPIO_PORTD | GPIO_AF | 13) -#define PD14_AF_ETMTRACE_PKT7 (GPIO_PORTD | GPIO_AF | 14) -#define PD15_AF_ETMTRACE_PKT6 (GPIO_PORTD | GPIO_AF | 15) -#define PD16_AF_ETMTRACE_PKT5 (GPIO_PORTD | GPIO_AF | 16) -#define PF1_AF_ETMTRACE_PKT0 (GPIO_PORTF | GPIO_AF | 1) -#define PF3_AF_ETMTRACE_PKT2 (GPIO_PORTF | GPIO_AF | 3) -#define PF5_AF_ETMPIPESTAT11 (GPIO_PORTF | GPIO_AF | 5) -#define PF7_AF_ATA_BUFFER_EN (GPIO_PORTF | GPIO_AF | 7) -#define PF8_AF_ATA_IORDY (GPIO_PORTF | GPIO_AF | 8) -#define PF9_AF_ATA_INTRQ (GPIO_PORTF | GPIO_AF | 9) -#define PF10_AF_ATA_RESET (GPIO_PORTF | GPIO_AF | 10) -#define PF11_AF_ATA_DMACK (GPIO_PORTF | GPIO_AF | 11) -#define PF12_AF_ATA_DMAREQ (GPIO_PORTF | GPIO_AF | 12) -#define PF13_AF_ATA_DA0 (GPIO_PORTF | GPIO_AF | 13) -#define PF14_AF_ATA_DA1 (GPIO_PORTF | GPIO_AF | 14) -#define PF15_AF_ETMTRACE_SYNC (GPIO_PORTF | GPIO_AF | 15) -#define PF16_AF_ATA_DA2 (GPIO_PORTF | GPIO_AF | 16) -#define PF17_AF_ATA_CS0 (GPIO_PORTF | GPIO_AF | 17) -#define PF18_AF_ATA_CS1 (GPIO_PORTF | GPIO_AF | 18) -#define PF19_AF_ATA_DIOW (GPIO_PORTF | GPIO_AF | 19) -#define PF20_AF_ATA_DIOR (GPIO_PORTF | GPIO_AF | 20) -#define PF22_AF_ETMTRACE_CLK (GPIO_PORTF | GPIO_AF | 22) -#define PF23_AF_ETMTRACE_PKT4 (GPIO_PORTF | GPIO_AF | 23) - -/* AIN GPIO pin functions */ - -#define PC14_AIN_SSI1_MCLK (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 14) -#define PC15_AIN_GPT6_TOUT (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 15) -#define PD0_AIN_FEC_TXD0 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 0) -#define PD1_AIN_FEC_TXD1 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 1) -#define PD2_AIN_FEC_TXD2 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 2) -#define PD3_AIN_FEC_TXD3 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 3) -#define PD9_AIN_FEC_MDC (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 9) -#define PD16_AIN_FEC_TX_ER (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 16) -#define PD27_AIN_EXT_DMA_GRANT (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 27) -#define PF23_AIN_FEC_TX_EN (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 23) - -/* BIN GPIO pin functions */ - -#define PC14_BIN_SSI2_MCLK (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 14) - -/* CIN GPIO pin functions */ - -#define PD2_CIN_SLCDC1_DAT0 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 2) -#define PD3_CIN_SLCDC1_DAT1 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 3) -#define PD4_CIN_SLCDC1_DAT2 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 4) -#define PD5_CIN_SLCDC1_DAT3 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 5) -#define PD6_CIN_SLCDC1_DAT4 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 6) -#define PD7_CIN_SLCDC1_DAT5 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 7) -#define PD8_CIN_SLCDC1_DAT6 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 8) -#define PD9_CIN_SLCDC1_DAT7 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 9) -#define PD10_CIN_SLCDC1_DAT8 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 10) -#define PD11_CIN_SLCDC1_DAT9 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 11) -#define PD12_CIN_SLCDC1_DAT10 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 12) -#define PD13_CIN_SLCDC1_DAT11 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 13) -#define PD14_CIN_SLCDC1_DAT12 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 14) -#define PD15_CIN_SLCDC1_DAT13 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 15) -#define PD16_CIN_SLCDC1_DAT14 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 16) -#define PD23_CIN_SLCDC1_DAT15 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 23) -#define PF27_CIN_EXT_DMA_GRANT (GPIO_PORTF | GPIO_CIN | GPIO_OUT | 27) -/* LCDC_TESTx on PBxx omitted, because it's not clear what they do */ - -/* AOUT GPIO pin functions */ - -#define PC14_AOUT_GPT6_TIN (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 14) -#define PD4_AOUT_FEC_RX_ER (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 4) -#define PD5_AOUT_FEC_RXD1 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 5) -#define PD6_AOUT_FEC_RXD2 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 6) -#define PD7_AOUT_FEC_RXD3 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 7) -#define PD10_AOUT_FEC_CRS (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 10) -#define PD11_AOUT_FEC_TX_CLK (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 11) -#define PD12_AOUT_FEC_RXD0 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 12) -#define PD13_AOUT_FEC_RX_DV (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 13) -#define PD14_AOUT_FEC_RX_CLK (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 14) -#define PD15_AOUT_FEC_COL (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 15) - -/* BOUT GPIO pin functions */ - -#define PC17_BOUT_PC_IOIS16 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 17) -#define PC18_BOUT_PC_BVD2 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 18) -#define PC19_BOUT_PC_BVD1 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 19) -#define PC28_BOUT_PC_BVD2 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 28) -#define PC29_BOUT_PC_VS1 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 29) -#define PC30_BOUT_PC_READY (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 30) -#define PC31_BOUT_PC_WAIT (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 31) - -#endif /* __MACH_IOMUX_MX27_H__ */ diff --git a/arch/arm/mach-imx/iomux-mx2x.h b/arch/arm/mach-imx/iomux-mx2x.h deleted file mode 100644 index ce6b6d20a4f0..000000000000 --- a/arch/arm/mach-imx/iomux-mx2x.h +++ /dev/null @@ -1,217 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> - * Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de> - */ -#ifndef __MACH_IOMUX_MX2x_H__ -#define __MACH_IOMUX_MX2x_H__ - -/* Primary GPIO pin functions */ - -#define PA5_PF_LSCLK (GPIO_PORTA | GPIO_PF | GPIO_OUT | 5) -#define PA6_PF_LD0 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 6) -#define PA7_PF_LD1 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 7) -#define PA8_PF_LD2 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 8) -#define PA9_PF_LD3 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 9) -#define PA10_PF_LD4 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 10) -#define PA11_PF_LD5 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 11) -#define PA12_PF_LD6 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 12) -#define PA13_PF_LD7 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 13) -#define PA14_PF_LD8 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 14) -#define PA15_PF_LD9 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 15) -#define PA16_PF_LD10 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 16) -#define PA17_PF_LD11 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 17) -#define PA18_PF_LD12 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 18) -#define PA19_PF_LD13 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 19) -#define PA20_PF_LD14 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 20) -#define PA21_PF_LD15 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 21) -#define PA22_PF_LD16 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 22) -#define PA23_PF_LD17 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 23) -#define PA24_PF_REV (GPIO_PORTA | GPIO_PF | GPIO_OUT | 24) -#define PA25_PF_CLS (GPIO_PORTA | GPIO_PF | GPIO_OUT | 25) -#define PA26_PF_PS (GPIO_PORTA | GPIO_PF | GPIO_OUT | 26) -#define PA27_PF_SPL_SPR (GPIO_PORTA | GPIO_PF | GPIO_OUT | 27) -#define PA28_PF_HSYNC (GPIO_PORTA | GPIO_PF | GPIO_OUT | 28) -#define PA29_PF_VSYNC (GPIO_PORTA | GPIO_PF | GPIO_OUT | 29) -#define PA30_PF_CONTRAST (GPIO_PORTA | GPIO_PF | GPIO_OUT | 30) -#define PA31_PF_OE_ACD (GPIO_PORTA | GPIO_PF | GPIO_OUT | 31) -#define PB4_PF_SD2_D0 (GPIO_PORTB | GPIO_PF | 4) -#define PB5_PF_SD2_D1 (GPIO_PORTB | GPIO_PF | 5) -#define PB6_PF_SD2_D2 (GPIO_PORTB | GPIO_PF | 6) -#define PB7_PF_SD2_D3 (GPIO_PORTB | GPIO_PF | 7) -#define PB8_PF_SD2_CMD (GPIO_PORTB | GPIO_PF | 8) -#define PB9_PF_SD2_CLK (GPIO_PORTB | GPIO_PF | 9) -#define PB10_PF_CSI_D0 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 10) -#define PB11_PF_CSI_D1 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 11) -#define PB12_PF_CSI_D2 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 12) -#define PB13_PF_CSI_D3 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 13) -#define PB14_PF_CSI_D4 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 14) -#define PB15_PF_CSI_MCLK (GPIO_PORTB | GPIO_PF | GPIO_OUT | 15) -#define PB16_PF_CSI_PIXCLK (GPIO_PORTB | GPIO_PF | GPIO_OUT | 16) -#define PB17_PF_CSI_D5 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 17) -#define PB18_PF_CSI_D6 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 18) -#define PB19_PF_CSI_D7 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 19) -#define PB20_PF_CSI_VSYNC (GPIO_PORTB | GPIO_PF | GPIO_OUT | 20) -#define PB21_PF_CSI_HSYNC (GPIO_PORTB | GPIO_PF | GPIO_OUT | 21) -#define PB23_PF_USB_PWR (GPIO_PORTB | GPIO_PF | 23) -#define PB24_PF_USB_OC (GPIO_PORTB | GPIO_PF | 24) -#define PB26_PF_USBH1_FS (GPIO_PORTB | GPIO_PF | 26) -#define PB27_PF_USBH1_OE (GPIO_PORTB | GPIO_PF | 27) -#define PB28_PF_USBH1_TXDM (GPIO_PORTB | GPIO_PF | 28) -#define PB29_PF_USBH1_TXDP (GPIO_PORTB | GPIO_PF | 29) -#define PB30_PF_USBH1_RXDM (GPIO_PORTB | GPIO_PF | 30) -#define PB31_PF_USBH1_RXDP (GPIO_PORTB | GPIO_PF | 31) -#define PC14_PF_TOUT (GPIO_PORTC | GPIO_PF | 14) -#define PC15_PF_TIN (GPIO_PORTC | GPIO_PF | 15) -#define PC20_PF_SSI1_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 20) -#define PC21_PF_SSI1_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 21) -#define PC22_PF_SSI1_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 22) -#define PC23_PF_SSI1_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 23) -#define PC24_PF_SSI2_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 24) -#define PC25_PF_SSI2_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 25) -#define PC26_PF_SSI2_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 26) -#define PC27_PF_SSI2_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 27) -#define PC28_PF_SSI3_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 28) -#define PC29_PF_SSI3_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 29) -#define PC30_PF_SSI3_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 30) -#define PC31_PF_SSI3_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 31) -#define PD17_PF_I2C_DATA (GPIO_PORTD | GPIO_PF | GPIO_OUT | 17) -#define PD18_PF_I2C_CLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 18) -#define PD19_PF_CSPI2_SS2 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 19) -#define PD20_PF_CSPI2_SS1 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 20) -#define PD21_PF_CSPI2_SS0 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 21) -#define PD22_PF_CSPI2_SCLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 22) -#define PD23_PF_CSPI2_MISO (GPIO_PORTD | GPIO_PF | GPIO_IN | 23) -#define PD24_PF_CSPI2_MOSI (GPIO_PORTD | GPIO_PF | GPIO_OUT | 24) -#define PD25_PF_CSPI1_RDY (GPIO_PORTD | GPIO_PF | GPIO_OUT | 25) -#define PD26_PF_CSPI1_SS2 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 26) -#define PD27_PF_CSPI1_SS1 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 27) -#define PD28_PF_CSPI1_SS0 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 28) -#define PD29_PF_CSPI1_SCLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 29) -#define PD30_PF_CSPI1_MISO (GPIO_PORTD | GPIO_PF | GPIO_IN | 30) -#define PD31_PF_CSPI1_MOSI (GPIO_PORTD | GPIO_PF | GPIO_OUT | 31) -#define PE3_PF_UART2_CTS (GPIO_PORTE | GPIO_PF | GPIO_OUT | 3) -#define PE4_PF_UART2_RTS (GPIO_PORTE | GPIO_PF | GPIO_IN | 4) -#define PE5_PF_PWMO (GPIO_PORTE | GPIO_PF | 5) -#define PE6_PF_UART2_TXD (GPIO_PORTE | GPIO_PF | GPIO_OUT | 6) -#define PE7_PF_UART2_RXD (GPIO_PORTE | GPIO_PF | GPIO_IN | 7) -#define PE8_PF_UART3_TXD (GPIO_PORTE | GPIO_PF | GPIO_OUT | 8) -#define PE9_PF_UART3_RXD (GPIO_PORTE | GPIO_PF | GPIO_IN | 9) -#define PE10_PF_UART3_CTS (GPIO_PORTE | GPIO_PF | GPIO_OUT | 10) -#define PE11_PF_UART3_RTS (GPIO_PORTE | GPIO_PF | GPIO_IN | 11) -#define PE12_PF_UART1_TXD (GPIO_PORTE | GPIO_PF | GPIO_OUT | 12) -#define PE13_PF_UART1_RXD (GPIO_PORTE | GPIO_PF | GPIO_IN | 13) -#define PE14_PF_UART1_CTS (GPIO_PORTE | GPIO_PF | GPIO_OUT | 14) -#define PE15_PF_UART1_RTS (GPIO_PORTE | GPIO_PF | GPIO_IN | 15) -#define PE16_PF_RTCK (GPIO_PORTE | GPIO_PF | GPIO_OUT | 16) -#define PE17_PF_RESET_OUT (GPIO_PORTE | GPIO_PF | 17) -#define PE18_PF_SD1_D0 (GPIO_PORTE | GPIO_PF | 18) -#define PE19_PF_SD1_D1 (GPIO_PORTE | GPIO_PF | 19) -#define PE20_PF_SD1_D2 (GPIO_PORTE | GPIO_PF | 20) -#define PE21_PF_SD1_D3 (GPIO_PORTE | GPIO_PF | 21) -#define PE22_PF_SD1_CMD (GPIO_PORTE | GPIO_PF | 22) -#define PE23_PF_SD1_CLK (GPIO_PORTE | GPIO_PF | 23) -#define PF0_PF_NRFB (GPIO_PORTF | GPIO_PF | 0) -#define PF2_PF_NFWP (GPIO_PORTF | GPIO_PF | 2) -#define PF4_PF_NFALE (GPIO_PORTF | GPIO_PF | 4) -#define PF5_PF_NFRE (GPIO_PORTF | GPIO_PF | 5) -#define PF6_PF_NFWE (GPIO_PORTF | GPIO_PF | 6) -#define PF15_PF_CLKO (GPIO_PORTF | GPIO_PF | 15) -#define PF21_PF_CS4 (GPIO_PORTF | GPIO_PF | 21) -#define PF22_PF_CS5 (GPIO_PORTF | GPIO_PF | 22) - -/* Alternate GPIO pin functions */ - -#define PB26_AF_UART4_RTS (GPIO_PORTB | GPIO_AF | GPIO_IN | 26) -#define PB28_AF_UART4_TXD (GPIO_PORTB | GPIO_AF | GPIO_OUT | 28) -#define PB29_AF_UART4_CTS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 29) -#define PB31_AF_UART4_RXD (GPIO_PORTB | GPIO_AF | GPIO_IN | 31) -#define PC28_AF_SLCDC2_D0 (GPIO_PORTC | GPIO_AF | 28) -#define PC29_AF_SLCDC2_RS (GPIO_PORTC | GPIO_AF | 29) -#define PC30_AF_SLCDC2_CS (GPIO_PORTC | GPIO_AF | 30) -#define PC31_AF_SLCDC2_CLK (GPIO_PORTC | GPIO_AF | 31) -#define PD19_AF_USBH2_DATA4 (GPIO_PORTD | GPIO_AF | 19) -#define PD20_AF_USBH2_DATA3 (GPIO_PORTD | GPIO_AF | 20) -#define PD21_AF_USBH2_DATA6 (GPIO_PORTD | GPIO_AF | 21) -#define PD22_AF_USBH2_DATA0 (GPIO_PORTD | GPIO_AF | 22) -#define PD23_AF_USBH2_DATA2 (GPIO_PORTD | GPIO_AF | 23) -#define PD24_AF_USBH2_DATA1 (GPIO_PORTD | GPIO_AF | 24) -#define PD26_AF_USBH2_DATA5 (GPIO_PORTD | GPIO_AF | 26) -#define PE0_AF_KP_COL6 (GPIO_PORTE | GPIO_AF | 0) -#define PE1_AF_KP_ROW6 (GPIO_PORTE | GPIO_AF | 1) -#define PE2_AF_KP_ROW7 (GPIO_PORTE | GPIO_AF | 2) -#define PE3_AF_KP_COL7 (GPIO_PORTE | GPIO_AF | 3) -#define PE4_AF_KP_ROW7 (GPIO_PORTE | GPIO_AF | 4) -#define PE6_AF_KP_COL6 (GPIO_PORTE | GPIO_AF | 6) -#define PE7_AF_KP_ROW6 (GPIO_PORTE | GPIO_AF | 7) -#define PE16_AF_OWIRE (GPIO_PORTE | GPIO_AF | 16) -#define PE18_AF_CSPI3_MISO (GPIO_PORTE | GPIO_AF | GPIO_IN | 18) -#define PE21_AF_CSPI3_SS (GPIO_PORTE | GPIO_AF | GPIO_OUT | 21) -#define PE22_AF_CSPI3_MOSI (GPIO_PORTE | GPIO_AF | GPIO_OUT | 22) -#define PE23_AF_CSPI3_SCLK (GPIO_PORTE | GPIO_AF | GPIO_OUT | 23) - -/* AIN GPIO pin functions */ - -#define PA6_AIN_SLCDC1_DAT0 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 6) -#define PA7_AIN_SLCDC1_DAT1 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 7) -#define PA8_AIN_SLCDC1_DAT2 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 8) -#define PA0_AIN_SLCDC1_DAT3 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 0) -#define PA11_AIN_SLCDC1_DAT5 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 11) -#define PA13_AIN_SLCDC1_DAT7 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 13) -#define PA15_AIN_SLCDC1_DAT9 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 15) -#define PA17_AIN_SLCDC1_DAT11 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 17) -#define PA19_AIN_SLCDC1_DAT13 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 19) -#define PA21_AIN_SLCDC1_DAT15 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 21) -#define PA22_AIN_EXT_DMAGRANT (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 22) -#define PA24_AIN_SLCDC1_D0 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 24) -#define PA25_AIN_SLCDC1_RS (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 25) -#define PA26_AIN_SLCDC1_CS (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 26) -#define PA27_AIN_SLCDC1_CLK (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 27) -#define PB6_AIN_SLCDC1_D0 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 6) -#define PB7_AIN_SLCDC1_RS (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 7) -#define PB8_AIN_SLCDC1_CS (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 8) -#define PB9_AIN_SLCDC1_CLK (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 9) -#define PB25_AIN_SLCDC1_DAT0 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 25) -#define PB26_AIN_SLCDC1_DAT1 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 26) -#define PB27_AIN_SLCDC1_DAT2 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 27) -#define PB28_AIN_SLCDC1_DAT3 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 28) -#define PB29_AIN_SLCDC1_DAT4 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 29) -#define PB30_AIN_SLCDC1_DAT5 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 30) -#define PB31_AIN_SLCDC1_DAT6 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 31) -#define PC5_AIN_SLCDC1_DAT7 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 5) -#define PC6_AIN_SLCDC1_DAT8 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 6) -#define PC7_AIN_SLCDC1_DAT9 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 7) -#define PC8_AIN_SLCDC1_DAT10 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 8) -#define PC9_AIN_SLCDC1_DAT11 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 9) -#define PC10_AIN_SLCDC1_DAT12 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 10) -#define PC11_AIN_SLCDC1_DAT13 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 11) -#define PC12_AIN_SLCDC1_DAT14 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 12) -#define PC13_AIN_SLCDC1_DAT15 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 13) -#define PE5_AIN_PC_SPKOUT (GPIO_PORTE | GPIO_AIN | GPIO_OUT | 5) - -/* BIN GPIO pin functions */ - -#define PE5_BIN_TOUT2 (GPIO_PORTE | GPIO_BIN | GPIO_OUT | 5) - -/* CIN GPIO pin functions */ - -#define PA14_CIN_SLCDC1_DAT0 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 14) -#define PA15_CIN_SLCDC1_DAT1 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 15) -#define PA16_CIN_SLCDC1_DAT2 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 16) -#define PA17_CIN_SLCDC1_DAT3 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 17) -#define PA18_CIN_SLCDC1_DAT4 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 18) -#define PA19_CIN_SLCDC1_DAT5 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 19) -#define PA20_CIN_SLCDC1_DAT6 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 20) -#define PA21_CIN_SLCDC1_DAT7 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 21) -#define PB30_CIN_UART4_CTS (GPIO_PORTB | GPIO_CIN | GPIO_OUT | 30) -#define PE5_CIN_TOUT3 (GPIO_PORTE | GPIO_CIN | GPIO_OUT | 5) - -/* AOUT GPIO pin functions */ - -#define PB29_AOUT_UART4_RXD (GPIO_PORTB | GPIO_AOUT | GPIO_IN | 29) -#define PB31_AOUT_UART4_RTS (GPIO_PORTB | GPIO_AOUT | GPIO_IN | 31) -#define PC8_AOUT_USBOTG_TXR_INT (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 8) -#define PC15_AOUT_WKGD (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 15) -#define PF21_AOUT_DTACK (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 21) - -#endif /* ifndef __MACH_IOMUX_MX2x_H__ */ diff --git a/arch/arm/mach-imx/iomux-mx3.h b/arch/arm/mach-imx/iomux-mx3.h deleted file mode 100644 index 99270a183d47..000000000000 --- a/arch/arm/mach-imx/iomux-mx3.h +++ /dev/null @@ -1,706 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> - */ -#ifndef __MACH_IOMUX_MX3_H__ -#define __MACH_IOMUX_MX3_H__ - -#include <linux/types.h> -/* - * various IOMUX output functions - */ - -#define IOMUX_OCONFIG_GPIO (0 << 4) /* used as GPIO */ -#define IOMUX_OCONFIG_FUNC (1 << 4) /* used as function */ -#define IOMUX_OCONFIG_ALT1 (2 << 4) /* used as alternate function 1 */ -#define IOMUX_OCONFIG_ALT2 (3 << 4) /* used as alternate function 2 */ -#define IOMUX_OCONFIG_ALT3 (4 << 4) /* used as alternate function 3 */ -#define IOMUX_OCONFIG_ALT4 (5 << 4) /* used as alternate function 4 */ -#define IOMUX_OCONFIG_ALT5 (6 << 4) /* used as alternate function 5 */ -#define IOMUX_OCONFIG_ALT6 (7 << 4) /* used as alternate function 6 */ -#define IOMUX_ICONFIG_NONE 0 /* not configured for input */ -#define IOMUX_ICONFIG_GPIO 1 /* used as GPIO */ -#define IOMUX_ICONFIG_FUNC 2 /* used as function */ -#define IOMUX_ICONFIG_ALT1 4 /* used as alternate function 1 */ -#define IOMUX_ICONFIG_ALT2 8 /* used as alternate function 2 */ - -#define IOMUX_CONFIG_GPIO (IOMUX_OCONFIG_GPIO | IOMUX_ICONFIG_GPIO) -#define IOMUX_CONFIG_FUNC (IOMUX_OCONFIG_FUNC | IOMUX_ICONFIG_FUNC) -#define IOMUX_CONFIG_ALT1 (IOMUX_OCONFIG_ALT1 | IOMUX_ICONFIG_ALT1) -#define IOMUX_CONFIG_ALT2 (IOMUX_OCONFIG_ALT2 | IOMUX_ICONFIG_ALT2) - -/* - * various IOMUX pad functions - */ -enum iomux_pad_config { - PAD_CTL_NOLOOPBACK = 0x0 << 9, - PAD_CTL_LOOPBACK = 0x1 << 9, - PAD_CTL_PKE_NONE = 0x0 << 8, - PAD_CTL_PKE_ENABLE = 0x1 << 8, - PAD_CTL_PUE_KEEPER = 0x0 << 7, - PAD_CTL_PUE_PUD = 0x1 << 7, - PAD_CTL_100K_PD = 0x0 << 5, - PAD_CTL_100K_PU = 0x1 << 5, - PAD_CTL_47K_PU = 0x2 << 5, - PAD_CTL_22K_PU = 0x3 << 5, - PAD_CTL_HYS_CMOS = 0x0 << 4, - PAD_CTL_HYS_SCHMITZ = 0x1 << 4, - PAD_CTL_ODE_CMOS = 0x0 << 3, - PAD_CTL_ODE_OpenDrain = 0x1 << 3, - PAD_CTL_DRV_NORMAL = 0x0 << 1, - PAD_CTL_DRV_HIGH = 0x1 << 1, - PAD_CTL_DRV_MAX = 0x2 << 1, - PAD_CTL_SRE_SLOW = 0x0 << 0, - PAD_CTL_SRE_FAST = 0x1 << 0 -}; - -/* - * various IOMUX general purpose functions - */ -enum iomux_gp_func { - MUX_PGP_FIRI = 1 << 0, - MUX_DDR_MODE = 1 << 1, - MUX_PGP_CSPI_BB = 1 << 2, - MUX_PGP_ATA_1 = 1 << 3, - MUX_PGP_ATA_2 = 1 << 4, - MUX_PGP_ATA_3 = 1 << 5, - MUX_PGP_ATA_4 = 1 << 6, - MUX_PGP_ATA_5 = 1 << 7, - MUX_PGP_ATA_6 = 1 << 8, - MUX_PGP_ATA_7 = 1 << 9, - MUX_PGP_ATA_8 = 1 << 10, - MUX_PGP_UH2 = 1 << 11, - MUX_SDCTL_CSD0_SEL = 1 << 12, - MUX_SDCTL_CSD1_SEL = 1 << 13, - MUX_CSPI1_UART3 = 1 << 14, - MUX_EXTDMAREQ2_MBX_SEL = 1 << 15, - MUX_TAMPER_DETECT_EN = 1 << 16, - MUX_PGP_USB_4WIRE = 1 << 17, - MUX_PGP_USB_COMMON = 1 << 18, - MUX_SDHC_MEMSTICK1 = 1 << 19, - MUX_SDHC_MEMSTICK2 = 1 << 20, - MUX_PGP_SPLL_BYP = 1 << 21, - MUX_PGP_UPLL_BYP = 1 << 22, - MUX_PGP_MSHC1_CLK_SEL = 1 << 23, - MUX_PGP_MSHC2_CLK_SEL = 1 << 24, - MUX_CSPI3_UART5_SEL = 1 << 25, - MUX_PGP_ATA_9 = 1 << 26, - MUX_PGP_USB_SUSPEND = 1 << 27, - MUX_PGP_USB_OTG_LOOPBACK = 1 << 28, - MUX_PGP_USB_HS1_LOOPBACK = 1 << 29, - MUX_PGP_USB_HS2_LOOPBACK = 1 << 30, - MUX_CLKO_DDR_MODE = 1 << 31, -}; - -/* - * setups a single pin: - * - reserves the pin so that it is not claimed by another driver - * - setups the iomux according to the configuration - * - if the pin is configured as a GPIO, we claim it through kernel gpiolib - */ -int mxc_iomux_alloc_pin(unsigned int pin, const char *label); -/* - * setups multiple pins - * convenient way to call the above function with tables - */ -int mxc_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count, - const char *label); - -/* - * releases a single pin: - * - make it available for a future use by another driver - * - frees the GPIO if the pin was configured as GPIO - * - DOES NOT reconfigure the IOMUX in its reset state - */ -void mxc_iomux_release_pin(unsigned int pin); -/* - * releases multiple pins - * convenvient way to call the above function with tables - */ -void mxc_iomux_release_multiple_pins(const unsigned int *pin_list, int count); - -/* - * This function enables/disables the general purpose function for a particular - * signal. - */ -void mxc_iomux_set_gpr(enum iomux_gp_func, bool en); - -/* - * This function only configures the iomux hardware. - * It is called by the setup functions and should not be called directly anymore. - * It is here visible for backward compatibility - */ -void mxc_iomux_mode(unsigned int pin_mode); - -#define IOMUX_PADNUM_MASK 0x1ff -#define IOMUX_GPIONUM_SHIFT 9 -#define IOMUX_GPIONUM_MASK (0xff << IOMUX_GPIONUM_SHIFT) -#define IOMUX_MODE_SHIFT 17 -#define IOMUX_MODE_MASK (0xff << IOMUX_MODE_SHIFT) - -#define IOMUX_PIN(gpionum, padnum) \ - (((gpionum << IOMUX_GPIONUM_SHIFT) & IOMUX_GPIONUM_MASK) | \ - (padnum & IOMUX_PADNUM_MASK)) - -#define IOMUX_MODE(pin, mode) (pin | mode << IOMUX_MODE_SHIFT) - -#define IOMUX_TO_GPIO(iomux_pin) \ - ((iomux_pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT) - -/* - * This enumeration is constructed based on the Section - * "sw_pad_ctl & sw_mux_ctl details" of the MX31 IC Spec. Each enumerated - * value is constructed based on the rules described above. - */ - -enum iomux_pins { - MX31_PIN_TTM_PAD = IOMUX_PIN(0xff, 0), - MX31_PIN_CSPI3_SPI_RDY = IOMUX_PIN(0xff, 1), - MX31_PIN_CSPI3_SCLK = IOMUX_PIN(0xff, 2), - MX31_PIN_CSPI3_MISO = IOMUX_PIN(0xff, 3), - MX31_PIN_CSPI3_MOSI = IOMUX_PIN(0xff, 4), - MX31_PIN_CLKSS = IOMUX_PIN(0xff, 5), - MX31_PIN_CE_CONTROL = IOMUX_PIN(0xff, 6), - MX31_PIN_ATA_RESET_B = IOMUX_PIN(95, 7), - MX31_PIN_ATA_DMACK = IOMUX_PIN(94, 8), - MX31_PIN_ATA_DIOW = IOMUX_PIN(93, 9), - MX31_PIN_ATA_DIOR = IOMUX_PIN(92, 10), - MX31_PIN_ATA_CS1 = IOMUX_PIN(91, 11), - MX31_PIN_ATA_CS0 = IOMUX_PIN(90, 12), - MX31_PIN_SD1_DATA3 = IOMUX_PIN(63, 13), - MX31_PIN_SD1_DATA2 = IOMUX_PIN(62, 14), - MX31_PIN_SD1_DATA1 = IOMUX_PIN(61, 15), - MX31_PIN_SD1_DATA0 = IOMUX_PIN(60, 16), - MX31_PIN_SD1_CLK = IOMUX_PIN(59, 17), - MX31_PIN_SD1_CMD = IOMUX_PIN(58, 18), - MX31_PIN_D3_SPL = IOMUX_PIN(0xff, 19), - MX31_PIN_D3_CLS = IOMUX_PIN(0xff, 20), - MX31_PIN_D3_REV = IOMUX_PIN(0xff, 21), - MX31_PIN_CONTRAST = IOMUX_PIN(0xff, 22), - MX31_PIN_VSYNC3 = IOMUX_PIN(0xff, 23), - MX31_PIN_READ = IOMUX_PIN(0xff, 24), - MX31_PIN_WRITE = IOMUX_PIN(0xff, 25), - MX31_PIN_PAR_RS = IOMUX_PIN(0xff, 26), - MX31_PIN_SER_RS = IOMUX_PIN(89, 27), - MX31_PIN_LCS1 = IOMUX_PIN(88, 28), - MX31_PIN_LCS0 = IOMUX_PIN(87, 29), - MX31_PIN_SD_D_CLK = IOMUX_PIN(86, 30), - MX31_PIN_SD_D_IO = IOMUX_PIN(85, 31), - MX31_PIN_SD_D_I = IOMUX_PIN(84, 32), - MX31_PIN_DRDY0 = IOMUX_PIN(0xff, 33), - MX31_PIN_FPSHIFT = IOMUX_PIN(0xff, 34), - MX31_PIN_HSYNC = IOMUX_PIN(0xff, 35), - MX31_PIN_VSYNC0 = IOMUX_PIN(0xff, 36), - MX31_PIN_LD17 = IOMUX_PIN(0xff, 37), - MX31_PIN_LD16 = IOMUX_PIN(0xff, 38), - MX31_PIN_LD15 = IOMUX_PIN(0xff, 39), - MX31_PIN_LD14 = IOMUX_PIN(0xff, 40), - MX31_PIN_LD13 = IOMUX_PIN(0xff, 41), - MX31_PIN_LD12 = IOMUX_PIN(0xff, 42), - MX31_PIN_LD11 = IOMUX_PIN(0xff, 43), - MX31_PIN_LD10 = IOMUX_PIN(0xff, 44), - MX31_PIN_LD9 = IOMUX_PIN(0xff, 45), - MX31_PIN_LD8 = IOMUX_PIN(0xff, 46), - MX31_PIN_LD7 = IOMUX_PIN(0xff, 47), - MX31_PIN_LD6 = IOMUX_PIN(0xff, 48), - MX31_PIN_LD5 = IOMUX_PIN(0xff, 49), - MX31_PIN_LD4 = IOMUX_PIN(0xff, 50), - MX31_PIN_LD3 = IOMUX_PIN(0xff, 51), - MX31_PIN_LD2 = IOMUX_PIN(0xff, 52), - MX31_PIN_LD1 = IOMUX_PIN(0xff, 53), - MX31_PIN_LD0 = IOMUX_PIN(0xff, 54), - MX31_PIN_USBH2_DATA1 = IOMUX_PIN(0xff, 55), - MX31_PIN_USBH2_DATA0 = IOMUX_PIN(0xff, 56), - MX31_PIN_USBH2_NXT = IOMUX_PIN(0xff, 57), - MX31_PIN_USBH2_STP = IOMUX_PIN(0xff, 58), - MX31_PIN_USBH2_DIR = IOMUX_PIN(0xff, 59), - MX31_PIN_USBH2_CLK = IOMUX_PIN(0xff, 60), - MX31_PIN_USBOTG_DATA7 = IOMUX_PIN(0xff, 61), - MX31_PIN_USBOTG_DATA6 = IOMUX_PIN(0xff, 62), - MX31_PIN_USBOTG_DATA5 = IOMUX_PIN(0xff, 63), - MX31_PIN_USBOTG_DATA4 = IOMUX_PIN(0xff, 64), - MX31_PIN_USBOTG_DATA3 = IOMUX_PIN(0xff, 65), - MX31_PIN_USBOTG_DATA2 = IOMUX_PIN(0xff, 66), - MX31_PIN_USBOTG_DATA1 = IOMUX_PIN(0xff, 67), - MX31_PIN_USBOTG_DATA0 = IOMUX_PIN(0xff, 68), - MX31_PIN_USBOTG_NXT = IOMUX_PIN(0xff, 69), - MX31_PIN_USBOTG_STP = IOMUX_PIN(0xff, 70), - MX31_PIN_USBOTG_DIR = IOMUX_PIN(0xff, 71), - MX31_PIN_USBOTG_CLK = IOMUX_PIN(0xff, 72), - MX31_PIN_USB_BYP = IOMUX_PIN(31, 73), - MX31_PIN_USB_OC = IOMUX_PIN(30, 74), - MX31_PIN_USB_PWR = IOMUX_PIN(29, 75), - MX31_PIN_SJC_MOD = IOMUX_PIN(0xff, 76), - MX31_PIN_DE_B = IOMUX_PIN(0xff, 77), - MX31_PIN_TRSTB = IOMUX_PIN(0xff, 78), - MX31_PIN_TDO = IOMUX_PIN(0xff, 79), - MX31_PIN_TDI = IOMUX_PIN(0xff, 80), - MX31_PIN_TMS = IOMUX_PIN(0xff, 81), - MX31_PIN_TCK = IOMUX_PIN(0xff, 82), - MX31_PIN_RTCK = IOMUX_PIN(0xff, 83), - MX31_PIN_KEY_COL7 = IOMUX_PIN(57, 84), - MX31_PIN_KEY_COL6 = IOMUX_PIN(56, 85), - MX31_PIN_KEY_COL5 = IOMUX_PIN(55, 86), - MX31_PIN_KEY_COL4 = IOMUX_PIN(54, 87), - MX31_PIN_KEY_COL3 = IOMUX_PIN(0xff, 88), - MX31_PIN_KEY_COL2 = IOMUX_PIN(0xff, 89), - MX31_PIN_KEY_COL1 = IOMUX_PIN(0xff, 90), - MX31_PIN_KEY_COL0 = IOMUX_PIN(0xff, 91), - MX31_PIN_KEY_ROW7 = IOMUX_PIN(53, 92), - MX31_PIN_KEY_ROW6 = IOMUX_PIN(52, 93), - MX31_PIN_KEY_ROW5 = IOMUX_PIN(51, 94), - MX31_PIN_KEY_ROW4 = IOMUX_PIN(50, 95), - MX31_PIN_KEY_ROW3 = IOMUX_PIN(0xff, 96), - MX31_PIN_KEY_ROW2 = IOMUX_PIN(0xff, 97), - MX31_PIN_KEY_ROW1 = IOMUX_PIN(0xff, 98), - MX31_PIN_KEY_ROW0 = IOMUX_PIN(0xff, 99), - MX31_PIN_BATT_LINE = IOMUX_PIN(49, 100), - MX31_PIN_CTS2 = IOMUX_PIN(0xff, 101), - MX31_PIN_RTS2 = IOMUX_PIN(0xff, 102), - MX31_PIN_TXD2 = IOMUX_PIN(28, 103), - MX31_PIN_RXD2 = IOMUX_PIN(27, 104), - MX31_PIN_DTR_DCE2 = IOMUX_PIN(48, 105), - MX31_PIN_DCD_DTE1 = IOMUX_PIN(47, 106), - MX31_PIN_RI_DTE1 = IOMUX_PIN(46, 107), - MX31_PIN_DSR_DTE1 = IOMUX_PIN(45, 108), - MX31_PIN_DTR_DTE1 = IOMUX_PIN(44, 109), - MX31_PIN_DCD_DCE1 = IOMUX_PIN(43, 110), - MX31_PIN_RI_DCE1 = IOMUX_PIN(42, 111), - MX31_PIN_DSR_DCE1 = IOMUX_PIN(41, 112), - MX31_PIN_DTR_DCE1 = IOMUX_PIN(40, 113), - MX31_PIN_CTS1 = IOMUX_PIN(39, 114), - MX31_PIN_RTS1 = IOMUX_PIN(38, 115), - MX31_PIN_TXD1 = IOMUX_PIN(37, 116), - MX31_PIN_RXD1 = IOMUX_PIN(36, 117), - MX31_PIN_CSPI2_SPI_RDY = IOMUX_PIN(0xff, 118), - MX31_PIN_CSPI2_SCLK = IOMUX_PIN(0xff, 119), - MX31_PIN_CSPI2_SS2 = IOMUX_PIN(0xff, 120), - MX31_PIN_CSPI2_SS1 = IOMUX_PIN(0xff, 121), - MX31_PIN_CSPI2_SS0 = IOMUX_PIN(0xff, 122), - MX31_PIN_CSPI2_MISO = IOMUX_PIN(0xff, 123), - MX31_PIN_CSPI2_MOSI = IOMUX_PIN(0xff, 124), - MX31_PIN_CSPI1_SPI_RDY = IOMUX_PIN(0xff, 125), - MX31_PIN_CSPI1_SCLK = IOMUX_PIN(0xff, 126), - MX31_PIN_CSPI1_SS2 = IOMUX_PIN(0xff, 127), - MX31_PIN_CSPI1_SS1 = IOMUX_PIN(0xff, 128), - MX31_PIN_CSPI1_SS0 = IOMUX_PIN(0xff, 129), - MX31_PIN_CSPI1_MISO = IOMUX_PIN(0xff, 130), - MX31_PIN_CSPI1_MOSI = IOMUX_PIN(0xff, 131), - MX31_PIN_SFS6 = IOMUX_PIN(26, 132), - MX31_PIN_SCK6 = IOMUX_PIN(25, 133), - MX31_PIN_SRXD6 = IOMUX_PIN(24, 134), - MX31_PIN_STXD6 = IOMUX_PIN(23, 135), - MX31_PIN_SFS5 = IOMUX_PIN(0xff, 136), - MX31_PIN_SCK5 = IOMUX_PIN(0xff, 137), - MX31_PIN_SRXD5 = IOMUX_PIN(22, 138), - MX31_PIN_STXD5 = IOMUX_PIN(21, 139), - MX31_PIN_SFS4 = IOMUX_PIN(0xff, 140), - MX31_PIN_SCK4 = IOMUX_PIN(0xff, 141), - MX31_PIN_SRXD4 = IOMUX_PIN(20, 142), - MX31_PIN_STXD4 = IOMUX_PIN(19, 143), - MX31_PIN_SFS3 = IOMUX_PIN(0xff, 144), - MX31_PIN_SCK3 = IOMUX_PIN(0xff, 145), - MX31_PIN_SRXD3 = IOMUX_PIN(18, 146), - MX31_PIN_STXD3 = IOMUX_PIN(17, 147), - MX31_PIN_I2C_DAT = IOMUX_PIN(0xff, 148), - MX31_PIN_I2C_CLK = IOMUX_PIN(0xff, 149), - MX31_PIN_CSI_PIXCLK = IOMUX_PIN(83, 150), - MX31_PIN_CSI_HSYNC = IOMUX_PIN(82, 151), - MX31_PIN_CSI_VSYNC = IOMUX_PIN(81, 152), - MX31_PIN_CSI_MCLK = IOMUX_PIN(80, 153), - MX31_PIN_CSI_D15 = IOMUX_PIN(79, 154), - MX31_PIN_CSI_D14 = IOMUX_PIN(78, 155), - MX31_PIN_CSI_D13 = IOMUX_PIN(77, 156), - MX31_PIN_CSI_D12 = IOMUX_PIN(76, 157), - MX31_PIN_CSI_D11 = IOMUX_PIN(75, 158), - MX31_PIN_CSI_D10 = IOMUX_PIN(74, 159), - MX31_PIN_CSI_D9 = IOMUX_PIN(73, 160), - MX31_PIN_CSI_D8 = IOMUX_PIN(72, 161), - MX31_PIN_CSI_D7 = IOMUX_PIN(71, 162), - MX31_PIN_CSI_D6 = IOMUX_PIN(70, 163), - MX31_PIN_CSI_D5 = IOMUX_PIN(69, 164), - MX31_PIN_CSI_D4 = IOMUX_PIN(68, 165), - MX31_PIN_M_GRANT = IOMUX_PIN(0xff, 166), - MX31_PIN_M_REQUEST = IOMUX_PIN(0xff, 167), - MX31_PIN_PC_POE = IOMUX_PIN(0xff, 168), - MX31_PIN_PC_RW_B = IOMUX_PIN(0xff, 169), - MX31_PIN_IOIS16 = IOMUX_PIN(0xff, 170), - MX31_PIN_PC_RST = IOMUX_PIN(0xff, 171), - MX31_PIN_PC_BVD2 = IOMUX_PIN(0xff, 172), - MX31_PIN_PC_BVD1 = IOMUX_PIN(0xff, 173), - MX31_PIN_PC_VS2 = IOMUX_PIN(0xff, 174), - MX31_PIN_PC_VS1 = IOMUX_PIN(0xff, 175), - MX31_PIN_PC_PWRON = IOMUX_PIN(0xff, 176), - MX31_PIN_PC_READY = IOMUX_PIN(0xff, 177), - MX31_PIN_PC_WAIT_B = IOMUX_PIN(0xff, 178), - MX31_PIN_PC_CD2_B = IOMUX_PIN(0xff, 179), - MX31_PIN_PC_CD1_B = IOMUX_PIN(0xff, 180), - MX31_PIN_D0 = IOMUX_PIN(0xff, 181), - MX31_PIN_D1 = IOMUX_PIN(0xff, 182), - MX31_PIN_D2 = IOMUX_PIN(0xff, 183), - MX31_PIN_D3 = IOMUX_PIN(0xff, 184), - MX31_PIN_D4 = IOMUX_PIN(0xff, 185), - MX31_PIN_D5 = IOMUX_PIN(0xff, 186), - MX31_PIN_D6 = IOMUX_PIN(0xff, 187), - MX31_PIN_D7 = IOMUX_PIN(0xff, 188), - MX31_PIN_D8 = IOMUX_PIN(0xff, 189), - MX31_PIN_D9 = IOMUX_PIN(0xff, 190), - MX31_PIN_D10 = IOMUX_PIN(0xff, 191), - MX31_PIN_D11 = IOMUX_PIN(0xff, 192), - MX31_PIN_D12 = IOMUX_PIN(0xff, 193), - MX31_PIN_D13 = IOMUX_PIN(0xff, 194), - MX31_PIN_D14 = IOMUX_PIN(0xff, 195), - MX31_PIN_D15 = IOMUX_PIN(0xff, 196), - MX31_PIN_NFRB = IOMUX_PIN(16, 197), - MX31_PIN_NFCE_B = IOMUX_PIN(15, 198), - MX31_PIN_NFWP_B = IOMUX_PIN(14, 199), - MX31_PIN_NFCLE = IOMUX_PIN(13, 200), - MX31_PIN_NFALE = IOMUX_PIN(12, 201), - MX31_PIN_NFRE_B = IOMUX_PIN(11, 202), - MX31_PIN_NFWE_B = IOMUX_PIN(10, 203), - MX31_PIN_SDQS3 = IOMUX_PIN(0xff, 204), - MX31_PIN_SDQS2 = IOMUX_PIN(0xff, 205), - MX31_PIN_SDQS1 = IOMUX_PIN(0xff, 206), - MX31_PIN_SDQS0 = IOMUX_PIN(0xff, 207), - MX31_PIN_SDCLK_B = IOMUX_PIN(0xff, 208), - MX31_PIN_SDCLK = IOMUX_PIN(0xff, 209), - MX31_PIN_SDCKE1 = IOMUX_PIN(0xff, 210), - MX31_PIN_SDCKE0 = IOMUX_PIN(0xff, 211), - MX31_PIN_SDWE = IOMUX_PIN(0xff, 212), - MX31_PIN_CAS = IOMUX_PIN(0xff, 213), - MX31_PIN_RAS = IOMUX_PIN(0xff, 214), - MX31_PIN_RW = IOMUX_PIN(0xff, 215), - MX31_PIN_BCLK = IOMUX_PIN(0xff, 216), - MX31_PIN_LBA = IOMUX_PIN(0xff, 217), - MX31_PIN_ECB = IOMUX_PIN(0xff, 218), - MX31_PIN_CS5 = IOMUX_PIN(0xff, 219), - MX31_PIN_CS4 = IOMUX_PIN(0xff, 220), - MX31_PIN_CS3 = IOMUX_PIN(0xff, 221), - MX31_PIN_CS2 = IOMUX_PIN(0xff, 222), - MX31_PIN_CS1 = IOMUX_PIN(0xff, 223), - MX31_PIN_CS0 = IOMUX_PIN(0xff, 224), - MX31_PIN_OE = IOMUX_PIN(0xff, 225), - MX31_PIN_EB1 = IOMUX_PIN(0xff, 226), - MX31_PIN_EB0 = IOMUX_PIN(0xff, 227), - MX31_PIN_DQM3 = IOMUX_PIN(0xff, 228), - MX31_PIN_DQM2 = IOMUX_PIN(0xff, 229), - MX31_PIN_DQM1 = IOMUX_PIN(0xff, 230), - MX31_PIN_DQM0 = IOMUX_PIN(0xff, 231), - MX31_PIN_SD31 = IOMUX_PIN(0xff, 232), - MX31_PIN_SD30 = IOMUX_PIN(0xff, 233), - MX31_PIN_SD29 = IOMUX_PIN(0xff, 234), - MX31_PIN_SD28 = IOMUX_PIN(0xff, 235), - MX31_PIN_SD27 = IOMUX_PIN(0xff, 236), - MX31_PIN_SD26 = IOMUX_PIN(0xff, 237), - MX31_PIN_SD25 = IOMUX_PIN(0xff, 238), - MX31_PIN_SD24 = IOMUX_PIN(0xff, 239), - MX31_PIN_SD23 = IOMUX_PIN(0xff, 240), - MX31_PIN_SD22 = IOMUX_PIN(0xff, 241), - MX31_PIN_SD21 = IOMUX_PIN(0xff, 242), - MX31_PIN_SD20 = IOMUX_PIN(0xff, 243), - MX31_PIN_SD19 = IOMUX_PIN(0xff, 244), - MX31_PIN_SD18 = IOMUX_PIN(0xff, 245), - MX31_PIN_SD17 = IOMUX_PIN(0xff, 246), - MX31_PIN_SD16 = IOMUX_PIN(0xff, 247), - MX31_PIN_SD15 = IOMUX_PIN(0xff, 248), - MX31_PIN_SD14 = IOMUX_PIN(0xff, 249), - MX31_PIN_SD13 = IOMUX_PIN(0xff, 250), - MX31_PIN_SD12 = IOMUX_PIN(0xff, 251), - MX31_PIN_SD11 = IOMUX_PIN(0xff, 252), - MX31_PIN_SD10 = IOMUX_PIN(0xff, 253), - MX31_PIN_SD9 = IOMUX_PIN(0xff, 254), - MX31_PIN_SD8 = IOMUX_PIN(0xff, 255), - MX31_PIN_SD7 = IOMUX_PIN(0xff, 256), - MX31_PIN_SD6 = IOMUX_PIN(0xff, 257), - MX31_PIN_SD5 = IOMUX_PIN(0xff, 258), - MX31_PIN_SD4 = IOMUX_PIN(0xff, 259), - MX31_PIN_SD3 = IOMUX_PIN(0xff, 260), - MX31_PIN_SD2 = IOMUX_PIN(0xff, 261), - MX31_PIN_SD1 = IOMUX_PIN(0xff, 262), - MX31_PIN_SD0 = IOMUX_PIN(0xff, 263), - MX31_PIN_SDBA0 = IOMUX_PIN(0xff, 264), - MX31_PIN_SDBA1 = IOMUX_PIN(0xff, 265), - MX31_PIN_A25 = IOMUX_PIN(0xff, 266), - MX31_PIN_A24 = IOMUX_PIN(0xff, 267), - MX31_PIN_A23 = IOMUX_PIN(0xff, 268), - MX31_PIN_A22 = IOMUX_PIN(0xff, 269), - MX31_PIN_A21 = IOMUX_PIN(0xff, 270), - MX31_PIN_A20 = IOMUX_PIN(0xff, 271), - MX31_PIN_A19 = IOMUX_PIN(0xff, 272), - MX31_PIN_A18 = IOMUX_PIN(0xff, 273), - MX31_PIN_A17 = IOMUX_PIN(0xff, 274), - MX31_PIN_A16 = IOMUX_PIN(0xff, 275), - MX31_PIN_A14 = IOMUX_PIN(0xff, 276), - MX31_PIN_A15 = IOMUX_PIN(0xff, 277), - MX31_PIN_A13 = IOMUX_PIN(0xff, 278), - MX31_PIN_A12 = IOMUX_PIN(0xff, 279), - MX31_PIN_A11 = IOMUX_PIN(0xff, 280), - MX31_PIN_MA10 = IOMUX_PIN(0xff, 281), - MX31_PIN_A10 = IOMUX_PIN(0xff, 282), - MX31_PIN_A9 = IOMUX_PIN(0xff, 283), - MX31_PIN_A8 = IOMUX_PIN(0xff, 284), - MX31_PIN_A7 = IOMUX_PIN(0xff, 285), - MX31_PIN_A6 = IOMUX_PIN(0xff, 286), - MX31_PIN_A5 = IOMUX_PIN(0xff, 287), - MX31_PIN_A4 = IOMUX_PIN(0xff, 288), - MX31_PIN_A3 = IOMUX_PIN(0xff, 289), - MX31_PIN_A2 = IOMUX_PIN(0xff, 290), - MX31_PIN_A1 = IOMUX_PIN(0xff, 291), - MX31_PIN_A0 = IOMUX_PIN(0xff, 292), - MX31_PIN_VPG1 = IOMUX_PIN(0xff, 293), - MX31_PIN_VPG0 = IOMUX_PIN(0xff, 294), - MX31_PIN_DVFS1 = IOMUX_PIN(0xff, 295), - MX31_PIN_DVFS0 = IOMUX_PIN(0xff, 296), - MX31_PIN_VSTBY = IOMUX_PIN(0xff, 297), - MX31_PIN_POWER_FAIL = IOMUX_PIN(0xff, 298), - MX31_PIN_CKIL = IOMUX_PIN(0xff, 299), - MX31_PIN_BOOT_MODE4 = IOMUX_PIN(0xff, 300), - MX31_PIN_BOOT_MODE3 = IOMUX_PIN(0xff, 301), - MX31_PIN_BOOT_MODE2 = IOMUX_PIN(0xff, 302), - MX31_PIN_BOOT_MODE1 = IOMUX_PIN(0xff, 303), - MX31_PIN_BOOT_MODE0 = IOMUX_PIN(0xff, 304), - MX31_PIN_CLKO = IOMUX_PIN(0xff, 305), - MX31_PIN_POR_B = IOMUX_PIN(0xff, 306), - MX31_PIN_RESET_IN_B = IOMUX_PIN(0xff, 307), - MX31_PIN_CKIH = IOMUX_PIN(0xff, 308), - MX31_PIN_SIMPD0 = IOMUX_PIN(35, 309), - MX31_PIN_SRX0 = IOMUX_PIN(34, 310), - MX31_PIN_STX0 = IOMUX_PIN(33, 311), - MX31_PIN_SVEN0 = IOMUX_PIN(32, 312), - MX31_PIN_SRST0 = IOMUX_PIN(67, 313), - MX31_PIN_SCLK0 = IOMUX_PIN(66, 314), - MX31_PIN_GPIO3_1 = IOMUX_PIN(65, 315), - MX31_PIN_GPIO3_0 = IOMUX_PIN(64, 316), - MX31_PIN_GPIO1_6 = IOMUX_PIN( 6, 317), - MX31_PIN_GPIO1_5 = IOMUX_PIN( 5, 318), - MX31_PIN_GPIO1_4 = IOMUX_PIN( 4, 319), - MX31_PIN_GPIO1_3 = IOMUX_PIN( 3, 320), - MX31_PIN_GPIO1_2 = IOMUX_PIN( 2, 321), - MX31_PIN_GPIO1_1 = IOMUX_PIN( 1, 322), - MX31_PIN_GPIO1_0 = IOMUX_PIN( 0, 323), - MX31_PIN_PWMO = IOMUX_PIN( 9, 324), - MX31_PIN_WATCHDOG_RST = IOMUX_PIN(0xff, 325), - MX31_PIN_COMPARE = IOMUX_PIN( 8, 326), - MX31_PIN_CAPTURE = IOMUX_PIN( 7, 327), -}; - -#define PIN_MAX 327 -#define NB_PORTS 12 /* NB_PINS/32, we chose 32 pins per "PORT" */ - -/* - * Convenience values for use with mxc_iomux_mode() - * - * Format here is MX31_PIN_(pin name)__(function) - */ -#define MX31_PIN_CSPI3_MOSI__RXD3 IOMUX_MODE(MX31_PIN_CSPI3_MOSI, IOMUX_CONFIG_ALT1) -#define MX31_PIN_CSPI3_MISO__TXD3 IOMUX_MODE(MX31_PIN_CSPI3_MISO, IOMUX_CONFIG_ALT1) -#define MX31_PIN_CSPI3_SCLK__RTS3 IOMUX_MODE(MX31_PIN_CSPI3_SCLK, IOMUX_CONFIG_ALT1) -#define MX31_PIN_CSPI3_SPI_RDY__CTS3 IOMUX_MODE(MX31_PIN_CSPI3_SPI_RDY, IOMUX_CONFIG_ALT1) -#define MX31_PIN_CTS1__CTS1 IOMUX_MODE(MX31_PIN_CTS1, IOMUX_CONFIG_FUNC) -#define MX31_PIN_RTS1__RTS1 IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_FUNC) -#define MX31_PIN_RTS1__SFS IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_ALT2) -#define MX31_PIN_TXD1__TXD1 IOMUX_MODE(MX31_PIN_TXD1, IOMUX_CONFIG_FUNC) -#define MX31_PIN_TXD1__SCK IOMUX_MODE(MX31_PIN_TXD1, IOMUX_CONFIG_ALT2) -#define MX31_PIN_RXD1__RXD1 IOMUX_MODE(MX31_PIN_RXD1, IOMUX_CONFIG_FUNC) -#define MX31_PIN_RXD1__STXDA IOMUX_MODE(MX31_PIN_RXD1, IOMUX_CONFIG_ALT2) -#define MX31_PIN_DCD_DCE1__DCD_DCE1 IOMUX_MODE(MX31_PIN_DCD_DCE1, IOMUX_CONFIG_FUNC) -#define MX31_PIN_RI_DCE1__RI_DCE1 IOMUX_MODE(MX31_PIN_RI_DCE1, IOMUX_CONFIG_FUNC) -#define MX31_PIN_DSR_DCE1__DSR_DCE1 IOMUX_MODE(MX31_PIN_DSR_DCE1, IOMUX_CONFIG_FUNC) -#define MX31_PIN_DTR_DCE1__DTR_DCE1 IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_FUNC) -#define MX31_PIN_DTR_DCE1__SRXDA IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_ALT2) -#define MX31_PIN_CTS2__CTS2 IOMUX_MODE(MX31_PIN_CTS2, IOMUX_CONFIG_FUNC) -#define MX31_PIN_RTS2__RTS2 IOMUX_MODE(MX31_PIN_RTS2, IOMUX_CONFIG_FUNC) -#define MX31_PIN_TXD2__TXD2 IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_FUNC) -#define MX31_PIN_RXD2__RXD2 IOMUX_MODE(MX31_PIN_RXD2, IOMUX_CONFIG_FUNC) -#define MX31_PIN_DCD_DTE1__DCD_DTE2 IOMUX_MODE(MX31_PIN_DCD_DTE1, IOMUX_CONFIG_ALT1) -#define MX31_PIN_RI_DTE1__RI_DTE2 IOMUX_MODE(MX31_PIN_RI_DTE1, IOMUX_CONFIG_ALT1) -#define MX31_PIN_DSR_DTE1__DSR_DTE2 IOMUX_MODE(MX31_PIN_DSR_DTE1, IOMUX_CONFIG_ALT1) -#define MX31_PIN_DTR_DTE1__DTR_DTE2 IOMUX_MODE(MX31_PIN_DTR_DTE1, IOMUX_OCONFIG_ALT3 | IOMUX_ICONFIG_NONE) -#define MX31_PIN_PC_RST__CTS5 IOMUX_MODE(MX31_PIN_PC_RST, IOMUX_CONFIG_ALT2) -#define MX31_PIN_PC_VS2__RTS5 IOMUX_MODE(MX31_PIN_PC_VS2, IOMUX_CONFIG_ALT2) -#define MX31_PIN_PC_BVD2__TXD5 IOMUX_MODE(MX31_PIN_PC_BVD2, IOMUX_CONFIG_ALT2) -#define MX31_PIN_PC_BVD1__RXD5 IOMUX_MODE(MX31_PIN_PC_BVD1, IOMUX_CONFIG_ALT2) -#define MX31_PIN_CSPI1_MOSI__MOSI IOMUX_MODE(MX31_PIN_CSPI1_MOSI, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSPI1_MISO__MISO IOMUX_MODE(MX31_PIN_CSPI1_MISO, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSPI1_SCLK__SCLK IOMUX_MODE(MX31_PIN_CSPI1_SCLK, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSPI1_SPI_RDY__SPI_RDY IOMUX_MODE(MX31_PIN_CSPI1_SPI_RDY, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSPI1_SS0__SS0 IOMUX_MODE(MX31_PIN_CSPI1_SS0, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSPI1_SS1__SS1 IOMUX_MODE(MX31_PIN_CSPI1_SS1, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSPI1_SS2__SS2 IOMUX_MODE(MX31_PIN_CSPI1_SS2, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSPI2_MOSI__MOSI IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSPI2_MOSI__SCL IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_ALT1) -#define MX31_PIN_CSPI2_MISO__MISO IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSPI2_MISO__SDA IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_ALT1) -#define MX31_PIN_CSPI2_SCLK__SCLK IOMUX_MODE(MX31_PIN_CSPI2_SCLK, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSPI2_SPI_RDY__SPI_RDY IOMUX_MODE(MX31_PIN_CSPI2_SPI_RDY, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSPI2_SS0__SS0 IOMUX_MODE(MX31_PIN_CSPI2_SS0, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSPI2_SS1__SS1 IOMUX_MODE(MX31_PIN_CSPI2_SS1, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSPI2_SS2__SS2 IOMUX_MODE(MX31_PIN_CSPI2_SS2, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSPI3_MOSI__MOSI IOMUX_MODE(MX31_PIN_CSPI3_MOSI, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSPI3_MISO__MISO IOMUX_MODE(MX31_PIN_CSPI3_MISO, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSPI3_SCLK__SCLK IOMUX_MODE(MX31_PIN_CSPI3_SCLK, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSPI3_SPI_RDY__SPI_RDY IOMUX_MODE(MX31_PIN_CSPI3_SPI_RDY, IOMUX_CONFIG_FUNC) -#define MX31_PIN_BATT_LINE__OWIRE IOMUX_MODE(MX31_PIN_BATT_LINE, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CS4__CS4 IOMUX_MODE(MX31_PIN_CS4, IOMUX_CONFIG_FUNC) -#define MX31_PIN_SD1_DATA3__SD1_DATA3 IOMUX_MODE(MX31_PIN_SD1_DATA3, IOMUX_CONFIG_FUNC) -#define MX31_PIN_SD1_DATA2__SD1_DATA2 IOMUX_MODE(MX31_PIN_SD1_DATA2, IOMUX_CONFIG_FUNC) -#define MX31_PIN_SD1_DATA1__SD1_DATA1 IOMUX_MODE(MX31_PIN_SD1_DATA1, IOMUX_CONFIG_FUNC) -#define MX31_PIN_SD1_DATA0__SD1_DATA0 IOMUX_MODE(MX31_PIN_SD1_DATA0, IOMUX_CONFIG_FUNC) -#define MX31_PIN_SD1_CLK__SD1_CLK IOMUX_MODE(MX31_PIN_SD1_CLK, IOMUX_CONFIG_FUNC) -#define MX31_PIN_SD1_CMD__SD1_CMD IOMUX_MODE(MX31_PIN_SD1_CMD, IOMUX_CONFIG_FUNC) -#define MX31_PIN_ATA_CS0__GPIO3_26 IOMUX_MODE(MX31_PIN_ATA_CS0, IOMUX_CONFIG_GPIO) -#define MX31_PIN_ATA_CS1__GPIO3_27 IOMUX_MODE(MX31_PIN_ATA_CS1, IOMUX_CONFIG_GPIO) -#define MX31_PIN_PC_PWRON__SD2_DATA3 IOMUX_MODE(MX31_PIN_PC_PWRON, IOMUX_CONFIG_ALT1) -#define MX31_PIN_PC_VS1__SD2_DATA2 IOMUX_MODE(MX31_PIN_PC_VS1, IOMUX_CONFIG_ALT1) -#define MX31_PIN_PC_READY__SD2_DATA1 IOMUX_MODE(MX31_PIN_PC_READY, IOMUX_CONFIG_ALT1) -#define MX31_PIN_PC_WAIT_B__SD2_DATA0 IOMUX_MODE(MX31_PIN_PC_WAIT_B, IOMUX_CONFIG_ALT1) -#define MX31_PIN_PC_CD2_B__SD2_CLK IOMUX_MODE(MX31_PIN_PC_CD2_B, IOMUX_CONFIG_ALT1) -#define MX31_PIN_PC_CD1_B__SD2_CMD IOMUX_MODE(MX31_PIN_PC_CD1_B, IOMUX_CONFIG_ALT1) -#define MX31_PIN_ATA_DIOR__GPIO3_28 IOMUX_MODE(MX31_PIN_ATA_DIOR, IOMUX_CONFIG_GPIO) -#define MX31_PIN_ATA_DIOW__GPIO3_29 IOMUX_MODE(MX31_PIN_ATA_DIOW, IOMUX_CONFIG_GPIO) -#define MX31_PIN_LD0__LD0 IOMUX_MODE(MX31_PIN_LD0, IOMUX_CONFIG_FUNC) -#define MX31_PIN_LD1__LD1 IOMUX_MODE(MX31_PIN_LD1, IOMUX_CONFIG_FUNC) -#define MX31_PIN_LD2__LD2 IOMUX_MODE(MX31_PIN_LD2, IOMUX_CONFIG_FUNC) -#define MX31_PIN_LD3__LD3 IOMUX_MODE(MX31_PIN_LD3, IOMUX_CONFIG_FUNC) -#define MX31_PIN_LD4__LD4 IOMUX_MODE(MX31_PIN_LD4, IOMUX_CONFIG_FUNC) -#define MX31_PIN_LD5__LD5 IOMUX_MODE(MX31_PIN_LD5, IOMUX_CONFIG_FUNC) -#define MX31_PIN_LD6__LD6 IOMUX_MODE(MX31_PIN_LD6, IOMUX_CONFIG_FUNC) -#define MX31_PIN_LD7__LD7 IOMUX_MODE(MX31_PIN_LD7, IOMUX_CONFIG_FUNC) -#define MX31_PIN_LD8__LD8 IOMUX_MODE(MX31_PIN_LD8, IOMUX_CONFIG_FUNC) -#define MX31_PIN_LD9__LD9 IOMUX_MODE(MX31_PIN_LD9, IOMUX_CONFIG_FUNC) -#define MX31_PIN_LD10__LD10 IOMUX_MODE(MX31_PIN_LD10, IOMUX_CONFIG_FUNC) -#define MX31_PIN_LD11__LD11 IOMUX_MODE(MX31_PIN_LD11, IOMUX_CONFIG_FUNC) -#define MX31_PIN_LD12__LD12 IOMUX_MODE(MX31_PIN_LD12, IOMUX_CONFIG_FUNC) -#define MX31_PIN_LD13__LD13 IOMUX_MODE(MX31_PIN_LD13, IOMUX_CONFIG_FUNC) -#define MX31_PIN_LD14__LD14 IOMUX_MODE(MX31_PIN_LD14, IOMUX_CONFIG_FUNC) -#define MX31_PIN_LD15__LD15 IOMUX_MODE(MX31_PIN_LD15, IOMUX_CONFIG_FUNC) -#define MX31_PIN_LD16__LD16 IOMUX_MODE(MX31_PIN_LD16, IOMUX_CONFIG_FUNC) -#define MX31_PIN_LD17__LD17 IOMUX_MODE(MX31_PIN_LD17, IOMUX_CONFIG_FUNC) -#define MX31_PIN_VSYNC3__VSYNC3 IOMUX_MODE(MX31_PIN_VSYNC3, IOMUX_CONFIG_FUNC) -#define MX31_PIN_HSYNC__HSYNC IOMUX_MODE(MX31_PIN_HSYNC, IOMUX_CONFIG_FUNC) -#define MX31_PIN_FPSHIFT__FPSHIFT IOMUX_MODE(MX31_PIN_FPSHIFT, IOMUX_CONFIG_FUNC) -#define MX31_PIN_DRDY0__DRDY0 IOMUX_MODE(MX31_PIN_DRDY0, IOMUX_CONFIG_FUNC) -#define MX31_PIN_D3_REV__D3_REV IOMUX_MODE(MX31_PIN_D3_REV, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CONTRAST__CONTRAST IOMUX_MODE(MX31_PIN_CONTRAST, IOMUX_CONFIG_FUNC) -#define MX31_PIN_D3_SPL__D3_SPL IOMUX_MODE(MX31_PIN_D3_SPL, IOMUX_CONFIG_FUNC) -#define MX31_PIN_D3_CLS__D3_CLS IOMUX_MODE(MX31_PIN_D3_CLS, IOMUX_CONFIG_FUNC) -#define MX31_PIN_GPIO1_1__GPIO IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO) -#define MX31_PIN_DCD_DTE1__I2C2_SDA IOMUX_MODE(MX31_PIN_DCD_DTE1, IOMUX_CONFIG_ALT2) -#define MX31_PIN_RI_DTE1__I2C2_SCL IOMUX_MODE(MX31_PIN_RI_DTE1, IOMUX_CONFIG_ALT2) -#define MX31_PIN_CSPI2_SS2__I2C3_SDA IOMUX_MODE(MX31_PIN_CSPI2_SS2, IOMUX_CONFIG_ALT1) -#define MX31_PIN_CSPI2_SCLK__I2C3_SCL IOMUX_MODE(MX31_PIN_CSPI2_SCLK, IOMUX_CONFIG_ALT1) -#define MX31_PIN_CSI_D4__CSI_D4 IOMUX_MODE(MX31_PIN_CSI_D4, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSI_D5__CSI_D5 IOMUX_MODE(MX31_PIN_CSI_D5, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSI_D6__CSI_D6 IOMUX_MODE(MX31_PIN_CSI_D6, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSI_D7__CSI_D7 IOMUX_MODE(MX31_PIN_CSI_D7, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSI_D8__CSI_D8 IOMUX_MODE(MX31_PIN_CSI_D8, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSI_D9__CSI_D9 IOMUX_MODE(MX31_PIN_CSI_D9, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSI_D10__CSI_D10 IOMUX_MODE(MX31_PIN_CSI_D10, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSI_D11__CSI_D11 IOMUX_MODE(MX31_PIN_CSI_D11, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSI_D12__CSI_D12 IOMUX_MODE(MX31_PIN_CSI_D12, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSI_D13__CSI_D13 IOMUX_MODE(MX31_PIN_CSI_D13, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSI_D14__CSI_D14 IOMUX_MODE(MX31_PIN_CSI_D14, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSI_D15__CSI_D15 IOMUX_MODE(MX31_PIN_CSI_D15, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSI_HSYNC__CSI_HSYNC IOMUX_MODE(MX31_PIN_CSI_HSYNC, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSI_MCLK__CSI_MCLK IOMUX_MODE(MX31_PIN_CSI_MCLK, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSI_PIXCLK__CSI_PIXCLK IOMUX_MODE(MX31_PIN_CSI_PIXCLK, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSI_VSYNC__CSI_VSYNC IOMUX_MODE(MX31_PIN_CSI_VSYNC, IOMUX_CONFIG_FUNC) -#define MX31_PIN_GPIO3_0__GPIO3_0 IOMUX_MODE(MX31_PIN_GPIO3_0, IOMUX_CONFIG_GPIO) -#define MX31_PIN_GPIO3_1__GPIO3_1 IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO) -#define MX31_PIN_TXD2__GPIO1_28 IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_GPIO) -#define MX31_PIN_CSI_D4__GPIO3_4 IOMUX_MODE(MX31_PIN_CSI_D4, IOMUX_CONFIG_GPIO) -#define MX31_PIN_CSI_D5__GPIO3_5 IOMUX_MODE(MX31_PIN_CSI_D5, IOMUX_CONFIG_GPIO) -#define MX31_PIN_USBOTG_DATA0__USBOTG_DATA0 IOMUX_MODE(MX31_PIN_USBOTG_DATA0, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_DATA1__USBOTG_DATA1 IOMUX_MODE(MX31_PIN_USBOTG_DATA1, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_DATA2__USBOTG_DATA2 IOMUX_MODE(MX31_PIN_USBOTG_DATA2, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_DATA3__USBOTG_DATA3 IOMUX_MODE(MX31_PIN_USBOTG_DATA3, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_DATA4__USBOTG_DATA4 IOMUX_MODE(MX31_PIN_USBOTG_DATA4, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_DATA5__USBOTG_DATA5 IOMUX_MODE(MX31_PIN_USBOTG_DATA5, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_DATA6__USBOTG_DATA6 IOMUX_MODE(MX31_PIN_USBOTG_DATA6, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_DATA7__USBOTG_DATA7 IOMUX_MODE(MX31_PIN_USBOTG_DATA7, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_CLK__USBOTG_CLK IOMUX_MODE(MX31_PIN_USBOTG_CLK, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_DIR__USBOTG_DIR IOMUX_MODE(MX31_PIN_USBOTG_DIR, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_NXT__USBOTG_NXT IOMUX_MODE(MX31_PIN_USBOTG_NXT, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_STP__USBOTG_STP IOMUX_MODE(MX31_PIN_USBOTG_STP, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSPI1_MOSI__USBH1_RXDM IOMUX_MODE(MX31_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT1) -#define MX31_PIN_CSPI1_MISO__USBH1_RXDP IOMUX_MODE(MX31_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT1) -#define MX31_PIN_CSPI1_SS0__USBH1_TXDM IOMUX_MODE(MX31_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT1) -#define MX31_PIN_CSPI1_SS1__USBH1_TXDP IOMUX_MODE(MX31_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT1) -#define MX31_PIN_CSPI1_SS2__USBH1_RCV IOMUX_MODE(MX31_PIN_CSPI1_SS2, IOMUX_CONFIG_ALT1) -#define MX31_PIN_CSPI1_SCLK__USBH1_OEB IOMUX_MODE(MX31_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT1) -#define MX31_PIN_CSPI1_SPI_RDY__USBH1_FS IOMUX_MODE(MX31_PIN_CSPI1_SPI_RDY, IOMUX_CONFIG_ALT1) -#define MX31_PIN_SFS6__USBH1_SUSPEND IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_FUNC) -#define MX31_PIN_NFRE_B__GPIO1_11 IOMUX_MODE(MX31_PIN_NFRE_B, IOMUX_CONFIG_GPIO) -#define MX31_PIN_NFALE__GPIO1_12 IOMUX_MODE(MX31_PIN_NFALE, IOMUX_CONFIG_GPIO) -#define MX31_PIN_USBH2_DATA0__USBH2_DATA0 IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBH2_DATA1__USBH2_DATA1 IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC) -#define MX31_PIN_STXD3__USBH2_DATA2 IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC) -#define MX31_PIN_SRXD3__USBH2_DATA3 IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC) -#define MX31_PIN_SCK3__USBH2_DATA4 IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC) -#define MX31_PIN_SFS3__USBH2_DATA5 IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC) -#define MX31_PIN_STXD6__USBH2_DATA6 IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC) -#define MX31_PIN_SRXD6__USBH2_DATA7 IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBH2_CLK__USBH2_CLK IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBH2_DIR__USBH2_DIR IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBH2_NXT__USBH2_NXT IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBH2_STP__USBH2_STP IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC) -#define MX31_PIN_SCK6__GPIO1_25 IOMUX_MODE(MX31_PIN_SCK6, IOMUX_CONFIG_GPIO) -#define MX31_PIN_USB_OC__GPIO1_30 IOMUX_MODE(MX31_PIN_USB_OC, IOMUX_CONFIG_GPIO) -#define MX31_PIN_I2C_DAT__I2C1_SDA IOMUX_MODE(MX31_PIN_I2C_DAT, IOMUX_CONFIG_FUNC) -#define MX31_PIN_I2C_CLK__I2C1_SCL IOMUX_MODE(MX31_PIN_I2C_CLK, IOMUX_CONFIG_FUNC) -#define MX31_PIN_GPIO1_0__GPIO1_0 IOMUX_MODE(MX31_PIN_GPIO1_0, IOMUX_CONFIG_GPIO) -#define MX31_PIN_SVEN0__GPIO2_0 IOMUX_MODE(MX31_PIN_SVEN0, IOMUX_CONFIG_GPIO) -#define MX31_PIN_STX0__GPIO2_1 IOMUX_MODE(MX31_PIN_STX0, IOMUX_CONFIG_GPIO) -#define MX31_PIN_SRX0__GPIO2_2 IOMUX_MODE(MX31_PIN_SRX0, IOMUX_CONFIG_GPIO) -#define MX31_PIN_SIMPD0__GPIO2_3 IOMUX_MODE(MX31_PIN_SIMPD0, IOMUX_CONFIG_GPIO) -#define MX31_PIN_DTR_DCE1__GPIO2_8 IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_GPIO) -#define MX31_PIN_DSR_DCE1__GPIO2_9 IOMUX_MODE(MX31_PIN_DSR_DCE1, IOMUX_CONFIG_GPIO) -#define MX31_PIN_RI_DCE1__GPIO2_10 IOMUX_MODE(MX31_PIN_RI_DCE1, IOMUX_CONFIG_GPIO) -#define MX31_PIN_DCD_DCE1__GPIO2_11 IOMUX_MODE(MX31_PIN_DCD_DCE1, IOMUX_CONFIG_GPIO) -#define MX31_PIN_STXD5__GPIO1_21 IOMUX_MODE(MX31_PIN_STXD5, IOMUX_CONFIG_GPIO) -#define MX31_PIN_SRXD5__GPIO1_22 IOMUX_MODE(MX31_PIN_SRXD5, IOMUX_CONFIG_GPIO) -#define MX31_PIN_GPIO1_3__GPIO1_3 IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO) -#define MX31_PIN_CSPI2_SS1__CSPI3_SS1 IOMUX_MODE(MX31_PIN_CSPI2_SS1, IOMUX_CONFIG_ALT1) -#define MX31_PIN_RTS1__GPIO2_6 IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_GPIO) -#define MX31_PIN_CTS1__GPIO2_7 IOMUX_MODE(MX31_PIN_CTS1, IOMUX_CONFIG_GPIO) -#define MX31_PIN_LCS0__GPIO3_23 IOMUX_MODE(MX31_PIN_LCS0, IOMUX_CONFIG_GPIO) -#define MX31_PIN_STXD4__STXD4 IOMUX_MODE(MX31_PIN_STXD4, IOMUX_CONFIG_FUNC) -#define MX31_PIN_SRXD4__SRXD4 IOMUX_MODE(MX31_PIN_SRXD4, IOMUX_CONFIG_FUNC) -#define MX31_PIN_SCK4__SCK4 IOMUX_MODE(MX31_PIN_SCK4, IOMUX_CONFIG_FUNC) -#define MX31_PIN_SFS4__SFS4 IOMUX_MODE(MX31_PIN_SFS4, IOMUX_CONFIG_FUNC) -#define MX31_PIN_STXD5__STXD5 IOMUX_MODE(MX31_PIN_STXD5, IOMUX_CONFIG_FUNC) -#define MX31_PIN_SRXD5__SRXD5 IOMUX_MODE(MX31_PIN_SRXD5, IOMUX_CONFIG_FUNC) -#define MX31_PIN_SCK5__SCK5 IOMUX_MODE(MX31_PIN_SCK5, IOMUX_CONFIG_FUNC) -#define MX31_PIN_SFS5__SFS5 IOMUX_MODE(MX31_PIN_SFS5, IOMUX_CONFIG_FUNC) -#define MX31_PIN_KEY_ROW0_KEY_ROW0 IOMUX_MODE(MX31_PIN_KEY_ROW0, IOMUX_CONFIG_FUNC) -#define MX31_PIN_KEY_ROW1_KEY_ROW1 IOMUX_MODE(MX31_PIN_KEY_ROW1, IOMUX_CONFIG_FUNC) -#define MX31_PIN_KEY_ROW2_KEY_ROW2 IOMUX_MODE(MX31_PIN_KEY_ROW2, IOMUX_CONFIG_FUNC) -#define MX31_PIN_KEY_ROW3_KEY_ROW3 IOMUX_MODE(MX31_PIN_KEY_ROW3, IOMUX_CONFIG_FUNC) -#define MX31_PIN_KEY_ROW4_KEY_ROW4 IOMUX_MODE(MX31_PIN_KEY_ROW4, IOMUX_CONFIG_FUNC) -#define MX31_PIN_KEY_ROW4_GPIO IOMUX_MODE(MX31_PIN_KEY_ROW4, IOMUX_CONFIG_GPIO) -#define MX31_PIN_KEY_ROW5_KEY_ROW5 IOMUX_MODE(MX31_PIN_KEY_ROW5, IOMUX_CONFIG_FUNC) -#define MX31_PIN_KEY_ROW6_KEY_ROW6 IOMUX_MODE(MX31_PIN_KEY_ROW6, IOMUX_CONFIG_FUNC) -#define MX31_PIN_KEY_ROW7_KEY_ROW7 IOMUX_MODE(MX31_PIN_KEY_ROW7, IOMUX_CONFIG_FUNC) -#define MX31_PIN_KEY_COL0_KEY_COL0 IOMUX_MODE(MX31_PIN_KEY_COL0, IOMUX_CONFIG_FUNC) -#define MX31_PIN_KEY_COL1_KEY_COL1 IOMUX_MODE(MX31_PIN_KEY_COL1, IOMUX_CONFIG_FUNC) -#define MX31_PIN_KEY_COL2_KEY_COL2 IOMUX_MODE(MX31_PIN_KEY_COL2, IOMUX_CONFIG_FUNC) -#define MX31_PIN_KEY_COL3_KEY_COL3 IOMUX_MODE(MX31_PIN_KEY_COL3, IOMUX_CONFIG_FUNC) -#define MX31_PIN_KEY_COL4_KEY_COL4 IOMUX_MODE(MX31_PIN_KEY_COL4, IOMUX_CONFIG_FUNC) -#define MX31_PIN_KEY_COL5_KEY_COL5 IOMUX_MODE(MX31_PIN_KEY_COL5, IOMUX_CONFIG_FUNC) -#define MX31_PIN_KEY_COL6_KEY_COL6 IOMUX_MODE(MX31_PIN_KEY_COL6, IOMUX_CONFIG_FUNC) -#define MX31_PIN_KEY_COL7_KEY_COL7 IOMUX_MODE(MX31_PIN_KEY_COL7, IOMUX_CONFIG_FUNC) -#define MX31_PIN_WATCHDOG_RST__WATCHDOG_RST IOMUX_MODE(MX31_PIN_WATCHDOG_RST, IOMUX_CONFIG_FUNC) - - -/* - * XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed with cspi2_ss0, - * cspi2_ss1, cspi1_ss0 cspi1_ss1 - */ - -/* - * This function configures the pad value for a IOMUX pin. - */ -void mxc_iomux_set_pad(enum iomux_pins, u32); - -#endif /* ifndef __MACH_IOMUX_MX3_H__ */ diff --git a/arch/arm/mach-imx/iomux-mx35.h b/arch/arm/mach-imx/iomux-mx35.h deleted file mode 100644 index 7fb5259b3ee0..000000000000 --- a/arch/arm/mach-imx/iomux-mx35.h +++ /dev/null @@ -1,1254 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH <armlinux@phytec.de> - */ - -#ifndef __MACH_IOMUX_MX35_H__ -#define __MACH_IOMUX_MX35_H__ - -#include "iomux-v3.h" - -/* - * The naming convention for the pad modes is MX35_PAD_<padname>__<padmode> - * If <padname> or <padmode> refers to a GPIO, it is named - * GPIO_<unit>_<num> see also iomux-v3.h - */ - -/* PAD MUX ALT INPSE PATH */ -#define MX35_PAD_CAPTURE__GPT_CAPIN1 IOMUX_PAD(0x328, 0x004, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CAPTURE__GPT_CMPOUT2 IOMUX_PAD(0x328, 0x004, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CAPTURE__CSPI2_SS1 IOMUX_PAD(0x328, 0x004, 2, 0x7f4, 0, NO_PAD_CTRL) -#define MX35_PAD_CAPTURE__EPIT1_EPITO IOMUX_PAD(0x328, 0x004, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CAPTURE__CCM_CLK32K IOMUX_PAD(0x328, 0x004, 4, 0x7d0, 0, NO_PAD_CTRL) -#define MX35_PAD_CAPTURE__GPIO1_4 IOMUX_PAD(0x328, 0x004, 5, 0x850, 0, NO_PAD_CTRL) - -#define MX35_PAD_COMPARE__GPT_CMPOUT1 IOMUX_PAD(0x32c, 0x008, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_COMPARE__GPT_CAPIN2 IOMUX_PAD(0x32c, 0x008, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_COMPARE__GPT_CMPOUT3 IOMUX_PAD(0x32c, 0x008, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_COMPARE__EPIT2_EPITO IOMUX_PAD(0x32c, 0x008, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_COMPARE__GPIO1_5 IOMUX_PAD(0x32c, 0x008, 5, 0x854, 0, NO_PAD_CTRL) -#define MX35_PAD_COMPARE__SDMA_EXTDMA_2 IOMUX_PAD(0x32c, 0x008, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_WDOG_RST__WDOG_WDOG_B IOMUX_PAD(0x330, 0x00c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_WDOG_RST__IPU_FLASH_STROBE IOMUX_PAD(0x330, 0x00c, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_WDOG_RST__GPIO1_6 IOMUX_PAD(0x330, 0x00c, 5, 0x858, 0, NO_PAD_CTRL) - -#define MX35_PAD_GPIO1_0__GPIO1_0 IOMUX_PAD(0x334, 0x010, 0, 0x82c, 0, NO_PAD_CTRL) -#define MX35_PAD_GPIO1_0__CCM_PMIC_RDY IOMUX_PAD(0x334, 0x010, 1, 0x7d4, 0, NO_PAD_CTRL) -#define MX35_PAD_GPIO1_0__OWIRE_LINE IOMUX_PAD(0x334, 0x010, 2, 0x990, 0, NO_PAD_CTRL) -#define MX35_PAD_GPIO1_0__SDMA_EXTDMA_0 IOMUX_PAD(0x334, 0x010, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_GPIO1_1__GPIO1_1 IOMUX_PAD(0x338, 0x014, 0, 0x838, 0, NO_PAD_CTRL) -#define MX35_PAD_GPIO1_1__PWM_PWMO IOMUX_PAD(0x338, 0x014, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_GPIO1_1__CSPI1_SS2 IOMUX_PAD(0x338, 0x014, 3, 0x7d8, 0, NO_PAD_CTRL) -#define MX35_PAD_GPIO1_1__SCC_TAMPER_DETECT IOMUX_PAD(0x338, 0x014, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_GPIO1_1__SDMA_EXTDMA_1 IOMUX_PAD(0x338, 0x014, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_GPIO2_0__GPIO2_0 IOMUX_PAD(0x33c, 0x018, 0, 0x868, 0, NO_PAD_CTRL) -#define MX35_PAD_GPIO2_0__USB_TOP_USBOTG_CLK IOMUX_PAD(0x33c, 0x018, 1, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_GPIO3_0__GPIO3_0 IOMUX_PAD(0x340, 0x01c, 0, 0x8e8, 0, NO_PAD_CTRL) -#define MX35_PAD_GPIO3_0__USB_TOP_USBH2_CLK IOMUX_PAD(0x340, 0x01c, 1, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_RESET_IN_B__CCM_RESET_IN_B IOMUX_PAD(0x344, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_POR_B__CCM_POR_B IOMUX_PAD(0x348, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CLKO__CCM_CLKO IOMUX_PAD(0x34c, 0x020, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CLKO__GPIO1_8 IOMUX_PAD(0x34c, 0x020, 5, 0x860, 0, NO_PAD_CTRL) - -#define MX35_PAD_BOOT_MODE0__CCM_BOOT_MODE_0 IOMUX_PAD(0x350, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_BOOT_MODE1__CCM_BOOT_MODE_1 IOMUX_PAD(0x354, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CLK_MODE0__CCM_CLK_MODE_0 IOMUX_PAD(0x358, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CLK_MODE1__CCM_CLK_MODE_1 IOMUX_PAD(0x35c, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_POWER_FAIL__CCM_DSM_WAKEUP_INT_26 IOMUX_PAD(0x360, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_VSTBY__CCM_VSTBY IOMUX_PAD(0x364, 0x024, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_VSTBY__GPIO1_7 IOMUX_PAD(0x364, 0x024, 5, 0x85c, 0, NO_PAD_CTRL) - -#define MX35_PAD_A0__EMI_EIM_DA_L_0 IOMUX_PAD(0x368, 0x028, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A1__EMI_EIM_DA_L_1 IOMUX_PAD(0x36c, 0x02c, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A2__EMI_EIM_DA_L_2 IOMUX_PAD(0x370, 0x030, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A3__EMI_EIM_DA_L_3 IOMUX_PAD(0x374, 0x034, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A4__EMI_EIM_DA_L_4 IOMUX_PAD(0x378, 0x038, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A5__EMI_EIM_DA_L_5 IOMUX_PAD(0x37c, 0x03c, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A6__EMI_EIM_DA_L_6 IOMUX_PAD(0x380, 0x040, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A7__EMI_EIM_DA_L_7 IOMUX_PAD(0x384, 0x044, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A8__EMI_EIM_DA_H_8 IOMUX_PAD(0x388, 0x048, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A9__EMI_EIM_DA_H_9 IOMUX_PAD(0x38c, 0x04c, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A10__EMI_EIM_DA_H_10 IOMUX_PAD(0x390, 0x050, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_MA10__EMI_MA10 IOMUX_PAD(0x394, 0x054, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A11__EMI_EIM_DA_H_11 IOMUX_PAD(0x398, 0x058, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A12__EMI_EIM_DA_H_12 IOMUX_PAD(0x39c, 0x05c, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A13__EMI_EIM_DA_H_13 IOMUX_PAD(0x3a0, 0x060, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A14__EMI_EIM_DA_H2_14 IOMUX_PAD(0x3a4, 0x064, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A15__EMI_EIM_DA_H2_15 IOMUX_PAD(0x3a8, 0x068, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A16__EMI_EIM_A_16 IOMUX_PAD(0x3ac, 0x06c, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A17__EMI_EIM_A_17 IOMUX_PAD(0x3b0, 0x070, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A18__EMI_EIM_A_18 IOMUX_PAD(0x3b4, 0x074, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A19__EMI_EIM_A_19 IOMUX_PAD(0x3b8, 0x078, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A20__EMI_EIM_A_20 IOMUX_PAD(0x3bc, 0x07c, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A21__EMI_EIM_A_21 IOMUX_PAD(0x3c0, 0x080, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A22__EMI_EIM_A_22 IOMUX_PAD(0x3c4, 0x084, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A23__EMI_EIM_A_23 IOMUX_PAD(0x3c8, 0x088, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A24__EMI_EIM_A_24 IOMUX_PAD(0x3cc, 0x08c, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_A25__EMI_EIM_A_25 IOMUX_PAD(0x3d0, 0x090, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SDBA1__EMI_EIM_SDBA1 IOMUX_PAD(0x3d4, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SDBA0__EMI_EIM_SDBA0 IOMUX_PAD(0x3d8, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD0__EMI_DRAM_D_0 IOMUX_PAD(0x3dc, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD1__EMI_DRAM_D_1 IOMUX_PAD(0x3e0, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD2__EMI_DRAM_D_2 IOMUX_PAD(0x3e4, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD3__EMI_DRAM_D_3 IOMUX_PAD(0x3e8, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD4__EMI_DRAM_D_4 IOMUX_PAD(0x3ec, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD5__EMI_DRAM_D_5 IOMUX_PAD(0x3f0, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD6__EMI_DRAM_D_6 IOMUX_PAD(0x3f4, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD7__EMI_DRAM_D_7 IOMUX_PAD(0x3f8, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD8__EMI_DRAM_D_8 IOMUX_PAD(0x3fc, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD9__EMI_DRAM_D_9 IOMUX_PAD(0x400, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD10__EMI_DRAM_D_10 IOMUX_PAD(0x404, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD11__EMI_DRAM_D_11 IOMUX_PAD(0x408, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD12__EMI_DRAM_D_12 IOMUX_PAD(0x40c, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD13__EMI_DRAM_D_13 IOMUX_PAD(0x410, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD14__EMI_DRAM_D_14 IOMUX_PAD(0x414, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD15__EMI_DRAM_D_15 IOMUX_PAD(0x418, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD16__EMI_DRAM_D_16 IOMUX_PAD(0x41c, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD17__EMI_DRAM_D_17 IOMUX_PAD(0x420, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD18__EMI_DRAM_D_18 IOMUX_PAD(0x424, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD19__EMI_DRAM_D_19 IOMUX_PAD(0x428, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD20__EMI_DRAM_D_20 IOMUX_PAD(0x42c, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD21__EMI_DRAM_D_21 IOMUX_PAD(0x430, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD22__EMI_DRAM_D_22 IOMUX_PAD(0x434, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD23__EMI_DRAM_D_23 IOMUX_PAD(0x438, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD24__EMI_DRAM_D_24 IOMUX_PAD(0x43c, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD25__EMI_DRAM_D_25 IOMUX_PAD(0x440, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD26__EMI_DRAM_D_26 IOMUX_PAD(0x444, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD27__EMI_DRAM_D_27 IOMUX_PAD(0x448, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD28__EMI_DRAM_D_28 IOMUX_PAD(0x44c, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD29__EMI_DRAM_D_29 IOMUX_PAD(0x450, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD30__EMI_DRAM_D_30 IOMUX_PAD(0x454, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD31__EMI_DRAM_D_31 IOMUX_PAD(0x458, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_DQM0__EMI_DRAM_DQM_0 IOMUX_PAD(0x45c, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_DQM1__EMI_DRAM_DQM_1 IOMUX_PAD(0x460, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_DQM2__EMI_DRAM_DQM_2 IOMUX_PAD(0x464, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_DQM3__EMI_DRAM_DQM_3 IOMUX_PAD(0x468, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_EB0__EMI_EIM_EB0_B IOMUX_PAD(0x46c, 0x094, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_EB1__EMI_EIM_EB1_B IOMUX_PAD(0x470, 0x098, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_OE__EMI_EIM_OE IOMUX_PAD(0x474, 0x09c, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CS0__EMI_EIM_CS0 IOMUX_PAD(0x478, 0x0a0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CS1__EMI_EIM_CS1 IOMUX_PAD(0x47c, 0x0a4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CS1__EMI_NANDF_CE3 IOMUX_PAD(0x47c, 0x0a4, 3, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CS2__EMI_EIM_CS2 IOMUX_PAD(0x480, 0x0a8, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CS3__EMI_EIM_CS3 IOMUX_PAD(0x484, 0x0ac, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CS4__EMI_EIM_CS4 IOMUX_PAD(0x488, 0x0b0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CS4__EMI_DTACK_B IOMUX_PAD(0x488, 0x0b0, 1, 0x800, 0, NO_PAD_CTRL) -#define MX35_PAD_CS4__EMI_NANDF_CE1 IOMUX_PAD(0x488, 0x0b0, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CS4__GPIO1_20 IOMUX_PAD(0x488, 0x0b0, 5, 0x83c, 0, NO_PAD_CTRL) - -#define MX35_PAD_CS5__EMI_EIM_CS5 IOMUX_PAD(0x48c, 0x0b4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CS5__CSPI2_SS2 IOMUX_PAD(0x48c, 0x0b4, 1, 0x7f8, 0, NO_PAD_CTRL) -#define MX35_PAD_CS5__CSPI1_SS2 IOMUX_PAD(0x48c, 0x0b4, 2, 0x7d8, 1, NO_PAD_CTRL) -#define MX35_PAD_CS5__EMI_NANDF_CE2 IOMUX_PAD(0x48c, 0x0b4, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CS5__GPIO1_21 IOMUX_PAD(0x48c, 0x0b4, 5, 0x840, 0, NO_PAD_CTRL) - -#define MX35_PAD_NF_CE0__EMI_NANDF_CE0 IOMUX_PAD(0x490, 0x0b8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_NF_CE0__GPIO1_22 IOMUX_PAD(0x490, 0x0b8, 5, 0x844, 0, NO_PAD_CTRL) - -#define MX35_PAD_ECB__EMI_EIM_ECB IOMUX_PAD(0x494, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LBA__EMI_EIM_LBA IOMUX_PAD(0x498, 0x0bc, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_BCLK__EMI_EIM_BCLK IOMUX_PAD(0x49c, 0x0c0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_RW__EMI_EIM_RW IOMUX_PAD(0x4a0, 0x0c4, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_RAS__EMI_DRAM_RAS IOMUX_PAD(0x4a4, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CAS__EMI_DRAM_CAS IOMUX_PAD(0x4a8, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SDWE__EMI_DRAM_SDWE IOMUX_PAD(0x4ac, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SDCKE0__EMI_DRAM_SDCKE_0 IOMUX_PAD(0x4b0, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SDCKE1__EMI_DRAM_SDCKE_1 IOMUX_PAD(0x4b4, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SDCLK__EMI_DRAM_SDCLK IOMUX_PAD(0x4b8, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SDQS0__EMI_DRAM_SDQS_0 IOMUX_PAD(0x4bc, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SDQS1__EMI_DRAM_SDQS_1 IOMUX_PAD(0x4c0, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SDQS2__EMI_DRAM_SDQS_2 IOMUX_PAD(0x4c4, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SDQS3__EMI_DRAM_SDQS_3 IOMUX_PAD(0x4c8, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_NFWE_B__EMI_NANDF_WE_B IOMUX_PAD(0x4cc, 0x0c8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_NFWE_B__USB_TOP_USBH2_DATA_3 IOMUX_PAD(0x4cc, 0x0c8, 1, 0x9d8, 0, NO_PAD_CTRL) -#define MX35_PAD_NFWE_B__IPU_DISPB_D0_VSYNC IOMUX_PAD(0x4cc, 0x0c8, 2, 0x924, 0, NO_PAD_CTRL) -#define MX35_PAD_NFWE_B__GPIO2_18 IOMUX_PAD(0x4cc, 0x0c8, 5, 0x88c, 0, NO_PAD_CTRL) -#define MX35_PAD_NFWE_B__ARM11P_TOP_TRACE_0 IOMUX_PAD(0x4cc, 0x0c8, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_NFRE_B__EMI_NANDF_RE_B IOMUX_PAD(0x4d0, 0x0cc, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_NFRE_B__USB_TOP_USBH2_DIR IOMUX_PAD(0x4d0, 0x0cc, 1, 0x9ec, 0, NO_PAD_CTRL) -#define MX35_PAD_NFRE_B__IPU_DISPB_BCLK IOMUX_PAD(0x4d0, 0x0cc, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_NFRE_B__GPIO2_19 IOMUX_PAD(0x4d0, 0x0cc, 5, 0x890, 0, NO_PAD_CTRL) -#define MX35_PAD_NFRE_B__ARM11P_TOP_TRACE_1 IOMUX_PAD(0x4d0, 0x0cc, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_NFALE__EMI_NANDF_ALE IOMUX_PAD(0x4d4, 0x0d0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_NFALE__USB_TOP_USBH2_STP IOMUX_PAD(0x4d4, 0x0d0, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_NFALE__IPU_DISPB_CS0 IOMUX_PAD(0x4d4, 0x0d0, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_NFALE__GPIO2_20 IOMUX_PAD(0x4d4, 0x0d0, 5, 0x898, 0, NO_PAD_CTRL) -#define MX35_PAD_NFALE__ARM11P_TOP_TRACE_2 IOMUX_PAD(0x4d4, 0x0d0, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_NFCLE__EMI_NANDF_CLE IOMUX_PAD(0x4d8, 0x0d4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_NFCLE__USB_TOP_USBH2_NXT IOMUX_PAD(0x4d8, 0x0d4, 1, 0x9f0, 0, NO_PAD_CTRL) -#define MX35_PAD_NFCLE__IPU_DISPB_PAR_RS IOMUX_PAD(0x4d8, 0x0d4, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_NFCLE__GPIO2_21 IOMUX_PAD(0x4d8, 0x0d4, 5, 0x89c, 0, NO_PAD_CTRL) -#define MX35_PAD_NFCLE__ARM11P_TOP_TRACE_3 IOMUX_PAD(0x4d8, 0x0d4, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_NFWP_B__EMI_NANDF_WP_B IOMUX_PAD(0x4dc, 0x0d8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_NFWP_B__USB_TOP_USBH2_DATA_7 IOMUX_PAD(0x4dc, 0x0d8, 1, 0x9e8, 0, NO_PAD_CTRL) -#define MX35_PAD_NFWP_B__IPU_DISPB_WR IOMUX_PAD(0x4dc, 0x0d8, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_NFWP_B__GPIO2_22 IOMUX_PAD(0x4dc, 0x0d8, 5, 0x8a0, 0, NO_PAD_CTRL) -#define MX35_PAD_NFWP_B__ARM11P_TOP_TRCTL IOMUX_PAD(0x4dc, 0x0d8, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_NFRB__EMI_NANDF_RB IOMUX_PAD(0x4e0, 0x0dc, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_NFRB__IPU_DISPB_RD IOMUX_PAD(0x4e0, 0x0dc, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_NFRB__GPIO2_23 IOMUX_PAD(0x4e0, 0x0dc, 5, 0x8a4, 0, NO_PAD_CTRL) -#define MX35_PAD_NFRB__ARM11P_TOP_TRCLK IOMUX_PAD(0x4e0, 0x0dc, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D15__EMI_EIM_D_15 IOMUX_PAD(0x4e4, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D14__EMI_EIM_D_14 IOMUX_PAD(0x4e8, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D13__EMI_EIM_D_13 IOMUX_PAD(0x4ec, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D12__EMI_EIM_D_12 IOMUX_PAD(0x4f0, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D11__EMI_EIM_D_11 IOMUX_PAD(0x4f4, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D10__EMI_EIM_D_10 IOMUX_PAD(0x4f8, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D9__EMI_EIM_D_9 IOMUX_PAD(0x4fc, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D8__EMI_EIM_D_8 IOMUX_PAD(0x500, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D7__EMI_EIM_D_7 IOMUX_PAD(0x504, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D6__EMI_EIM_D_6 IOMUX_PAD(0x508, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D5__EMI_EIM_D_5 IOMUX_PAD(0x50c, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D4__EMI_EIM_D_4 IOMUX_PAD(0x510, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D3__EMI_EIM_D_3 IOMUX_PAD(0x514, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D2__EMI_EIM_D_2 IOMUX_PAD(0x518, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D1__EMI_EIM_D_1 IOMUX_PAD(0x51c, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D0__EMI_EIM_D_0 IOMUX_PAD(0x520, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CSI_D8__IPU_CSI_D_8 IOMUX_PAD(0x524, 0x0e0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_D8__KPP_COL_0 IOMUX_PAD(0x524, 0x0e0, 1, 0x950, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_D8__GPIO1_20 IOMUX_PAD(0x524, 0x0e0, 5, 0x83c, 1, NO_PAD_CTRL) -#define MX35_PAD_CSI_D8__ARM11P_TOP_EVNTBUS_13 IOMUX_PAD(0x524, 0x0e0, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CSI_D9__IPU_CSI_D_9 IOMUX_PAD(0x528, 0x0e4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_D9__KPP_COL_1 IOMUX_PAD(0x528, 0x0e4, 1, 0x954, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_D9__GPIO1_21 IOMUX_PAD(0x528, 0x0e4, 5, 0x840, 1, NO_PAD_CTRL) -#define MX35_PAD_CSI_D9__ARM11P_TOP_EVNTBUS_14 IOMUX_PAD(0x528, 0x0e4, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CSI_D10__IPU_CSI_D_10 IOMUX_PAD(0x52c, 0x0e8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_D10__KPP_COL_2 IOMUX_PAD(0x52c, 0x0e8, 1, 0x958, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_D10__GPIO1_22 IOMUX_PAD(0x52c, 0x0e8, 5, 0x844, 1, NO_PAD_CTRL) -#define MX35_PAD_CSI_D10__ARM11P_TOP_EVNTBUS_15 IOMUX_PAD(0x52c, 0x0e8, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CSI_D11__IPU_CSI_D_11 IOMUX_PAD(0x530, 0x0ec, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_D11__KPP_COL_3 IOMUX_PAD(0x530, 0x0ec, 1, 0x95c, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_D11__GPIO1_23 IOMUX_PAD(0x530, 0x0ec, 5, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CSI_D12__IPU_CSI_D_12 IOMUX_PAD(0x534, 0x0f0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_D12__KPP_ROW_0 IOMUX_PAD(0x534, 0x0f0, 1, 0x970, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_D12__GPIO1_24 IOMUX_PAD(0x534, 0x0f0, 5, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CSI_D13__IPU_CSI_D_13 IOMUX_PAD(0x538, 0x0f4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_D13__KPP_ROW_1 IOMUX_PAD(0x538, 0x0f4, 1, 0x974, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_D13__GPIO1_25 IOMUX_PAD(0x538, 0x0f4, 5, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CSI_D14__IPU_CSI_D_14 IOMUX_PAD(0x53c, 0x0f8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_D14__KPP_ROW_2 IOMUX_PAD(0x53c, 0x0f8, 1, 0x978, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_D14__GPIO1_26 IOMUX_PAD(0x53c, 0x0f8, 5, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CSI_D15__IPU_CSI_D_15 IOMUX_PAD(0x540, 0x0fc, 0, 0x97c, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_D15__KPP_ROW_3 IOMUX_PAD(0x540, 0x0fc, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_D15__GPIO1_27 IOMUX_PAD(0x540, 0x0fc, 5, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CSI_MCLK__IPU_CSI_MCLK IOMUX_PAD(0x544, 0x100, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_MCLK__GPIO1_28 IOMUX_PAD(0x544, 0x100, 5, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CSI_VSYNC__IPU_CSI_VSYNC IOMUX_PAD(0x548, 0x104, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_VSYNC__GPIO1_29 IOMUX_PAD(0x548, 0x104, 5, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CSI_HSYNC__IPU_CSI_HSYNC IOMUX_PAD(0x54c, 0x108, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_HSYNC__GPIO1_30 IOMUX_PAD(0x54c, 0x108, 5, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CSI_PIXCLK__IPU_CSI_PIXCLK IOMUX_PAD(0x550, 0x10c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSI_PIXCLK__GPIO1_31 IOMUX_PAD(0x550, 0x10c, 5, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_I2C1_CLK__I2C1_SCL IOMUX_PAD(0x554, 0x110, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_I2C1_CLK__GPIO2_24 IOMUX_PAD(0x554, 0x110, 5, 0x8a8, 0, NO_PAD_CTRL) -#define MX35_PAD_I2C1_CLK__CCM_USB_BYP_CLK IOMUX_PAD(0x554, 0x110, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_I2C1_DAT__I2C1_SDA IOMUX_PAD(0x558, 0x114, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_I2C1_DAT__GPIO2_25 IOMUX_PAD(0x558, 0x114, 5, 0x8ac, 0, NO_PAD_CTRL) - -#define MX35_PAD_I2C2_CLK__I2C2_SCL IOMUX_PAD(0x55c, 0x118, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_I2C2_CLK__CAN1_TXCAN IOMUX_PAD(0x55c, 0x118, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR IOMUX_PAD(0x55c, 0x118, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_I2C2_CLK__GPIO2_26 IOMUX_PAD(0x55c, 0x118, 5, 0x8b0, 0, NO_PAD_CTRL) -#define MX35_PAD_I2C2_CLK__SDMA_DEBUG_BUS_DEVICE_2 IOMUX_PAD(0x55c, 0x118, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_I2C2_DAT__I2C2_SDA IOMUX_PAD(0x560, 0x11c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_I2C2_DAT__CAN1_RXCAN IOMUX_PAD(0x560, 0x11c, 1, 0x7c8, 0, NO_PAD_CTRL) -#define MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC IOMUX_PAD(0x560, 0x11c, 2, 0x9f4, 0, NO_PAD_CTRL) -#define MX35_PAD_I2C2_DAT__GPIO2_27 IOMUX_PAD(0x560, 0x11c, 5, 0x8b4, 0, NO_PAD_CTRL) -#define MX35_PAD_I2C2_DAT__SDMA_DEBUG_BUS_DEVICE_3 IOMUX_PAD(0x560, 0x11c, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_STXD4__AUDMUX_AUD4_TXD IOMUX_PAD(0x564, 0x120, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_STXD4__GPIO2_28 IOMUX_PAD(0x564, 0x120, 5, 0x8b8, 0, NO_PAD_CTRL) -#define MX35_PAD_STXD4__ARM11P_TOP_ARM_COREASID0 IOMUX_PAD(0x564, 0x120, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SRXD4__AUDMUX_AUD4_RXD IOMUX_PAD(0x568, 0x124, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SRXD4__GPIO2_29 IOMUX_PAD(0x568, 0x124, 5, 0x8bc, 0, NO_PAD_CTRL) -#define MX35_PAD_SRXD4__ARM11P_TOP_ARM_COREASID1 IOMUX_PAD(0x568, 0x124, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SCK4__AUDMUX_AUD4_TXC IOMUX_PAD(0x56c, 0x128, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SCK4__GPIO2_30 IOMUX_PAD(0x56c, 0x128, 5, 0x8c4, 0, NO_PAD_CTRL) -#define MX35_PAD_SCK4__ARM11P_TOP_ARM_COREASID2 IOMUX_PAD(0x56c, 0x128, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS IOMUX_PAD(0x570, 0x12c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_STXFS4__GPIO2_31 IOMUX_PAD(0x570, 0x12c, 5, 0x8c8, 0, NO_PAD_CTRL) -#define MX35_PAD_STXFS4__ARM11P_TOP_ARM_COREASID3 IOMUX_PAD(0x570, 0x12c, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_STXD5__AUDMUX_AUD5_TXD IOMUX_PAD(0x574, 0x130, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_STXD5__SPDIF_SPDIF_OUT1 IOMUX_PAD(0x574, 0x130, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_STXD5__CSPI2_MOSI IOMUX_PAD(0x574, 0x130, 2, 0x7ec, 0, NO_PAD_CTRL) -#define MX35_PAD_STXD5__GPIO1_0 IOMUX_PAD(0x574, 0x130, 5, 0x82c, 1, NO_PAD_CTRL) -#define MX35_PAD_STXD5__ARM11P_TOP_ARM_COREASID4 IOMUX_PAD(0x574, 0x130, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SRXD5__AUDMUX_AUD5_RXD IOMUX_PAD(0x578, 0x134, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SRXD5__SPDIF_SPDIF_IN1 IOMUX_PAD(0x578, 0x134, 1, 0x998, 0, NO_PAD_CTRL) -#define MX35_PAD_SRXD5__CSPI2_MISO IOMUX_PAD(0x578, 0x134, 2, 0x7e8, 0, NO_PAD_CTRL) -#define MX35_PAD_SRXD5__GPIO1_1 IOMUX_PAD(0x578, 0x134, 5, 0x838, 1, NO_PAD_CTRL) -#define MX35_PAD_SRXD5__ARM11P_TOP_ARM_COREASID5 IOMUX_PAD(0x578, 0x134, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SCK5__AUDMUX_AUD5_TXC IOMUX_PAD(0x57c, 0x138, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SCK5__SPDIF_SPDIF_EXTCLK IOMUX_PAD(0x57c, 0x138, 1, 0x994, 0, NO_PAD_CTRL) -#define MX35_PAD_SCK5__CSPI2_SCLK IOMUX_PAD(0x57c, 0x138, 2, 0x7e0, 0, NO_PAD_CTRL) -#define MX35_PAD_SCK5__GPIO1_2 IOMUX_PAD(0x57c, 0x138, 5, 0x848, 0, NO_PAD_CTRL) -#define MX35_PAD_SCK5__ARM11P_TOP_ARM_COREASID6 IOMUX_PAD(0x57c, 0x138, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_STXFS5__AUDMUX_AUD5_TXFS IOMUX_PAD(0x580, 0x13c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_STXFS5__CSPI2_RDY IOMUX_PAD(0x580, 0x13c, 2, 0x7e4, 0, NO_PAD_CTRL) -#define MX35_PAD_STXFS5__GPIO1_3 IOMUX_PAD(0x580, 0x13c, 5, 0x84c, 0, NO_PAD_CTRL) -#define MX35_PAD_STXFS5__ARM11P_TOP_ARM_COREASID7 IOMUX_PAD(0x580, 0x13c, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SCKR__ESAI_SCKR IOMUX_PAD(0x584, 0x140, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SCKR__GPIO1_4 IOMUX_PAD(0x584, 0x140, 5, 0x850, 1, NO_PAD_CTRL) -#define MX35_PAD_SCKR__ARM11P_TOP_EVNTBUS_10 IOMUX_PAD(0x584, 0x140, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_FSR__ESAI_FSR IOMUX_PAD(0x588, 0x144, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FSR__GPIO1_5 IOMUX_PAD(0x588, 0x144, 5, 0x854, 1, NO_PAD_CTRL) -#define MX35_PAD_FSR__ARM11P_TOP_EVNTBUS_11 IOMUX_PAD(0x588, 0x144, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_HCKR__ESAI_HCKR IOMUX_PAD(0x58c, 0x148, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_HCKR__AUDMUX_AUD5_RXFS IOMUX_PAD(0x58c, 0x148, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_HCKR__CSPI2_SS0 IOMUX_PAD(0x58c, 0x148, 2, 0x7f0, 0, NO_PAD_CTRL) -#define MX35_PAD_HCKR__IPU_FLASH_STROBE IOMUX_PAD(0x58c, 0x148, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_HCKR__GPIO1_6 IOMUX_PAD(0x58c, 0x148, 5, 0x858, 1, NO_PAD_CTRL) -#define MX35_PAD_HCKR__ARM11P_TOP_EVNTBUS_12 IOMUX_PAD(0x58c, 0x148, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SCKT__ESAI_SCKT IOMUX_PAD(0x590, 0x14c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SCKT__GPIO1_7 IOMUX_PAD(0x590, 0x14c, 5, 0x85c, 1, NO_PAD_CTRL) -#define MX35_PAD_SCKT__IPU_CSI_D_0 IOMUX_PAD(0x590, 0x14c, 6, 0x930, 0, NO_PAD_CTRL) -#define MX35_PAD_SCKT__KPP_ROW_2 IOMUX_PAD(0x590, 0x14c, 7, 0x978, 1, NO_PAD_CTRL) - -#define MX35_PAD_FST__ESAI_FST IOMUX_PAD(0x594, 0x150, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FST__GPIO1_8 IOMUX_PAD(0x594, 0x150, 5, 0x860, 1, NO_PAD_CTRL) -#define MX35_PAD_FST__IPU_CSI_D_1 IOMUX_PAD(0x594, 0x150, 6, 0x934, 0, NO_PAD_CTRL) -#define MX35_PAD_FST__KPP_ROW_3 IOMUX_PAD(0x594, 0x150, 7, 0x97c, 1, NO_PAD_CTRL) - -#define MX35_PAD_HCKT__ESAI_HCKT IOMUX_PAD(0x598, 0x154, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_HCKT__AUDMUX_AUD5_RXC IOMUX_PAD(0x598, 0x154, 1, 0x7a8, 0, NO_PAD_CTRL) -#define MX35_PAD_HCKT__GPIO1_9 IOMUX_PAD(0x598, 0x154, 5, 0x864, 0, NO_PAD_CTRL) -#define MX35_PAD_HCKT__IPU_CSI_D_2 IOMUX_PAD(0x598, 0x154, 6, 0x938, 0, NO_PAD_CTRL) -#define MX35_PAD_HCKT__KPP_COL_3 IOMUX_PAD(0x598, 0x154, 7, 0x95c, 1, NO_PAD_CTRL) - -#define MX35_PAD_TX5_RX0__ESAI_TX5_RX0 IOMUX_PAD(0x59c, 0x158, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX5_RX0__AUDMUX_AUD4_RXC IOMUX_PAD(0x59c, 0x158, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX5_RX0__CSPI2_SS2 IOMUX_PAD(0x59c, 0x158, 2, 0x7f8, 1, NO_PAD_CTRL) -#define MX35_PAD_TX5_RX0__CAN2_TXCAN IOMUX_PAD(0x59c, 0x158, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX5_RX0__UART2_DTR IOMUX_PAD(0x59c, 0x158, 4, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX5_RX0__GPIO1_10 IOMUX_PAD(0x59c, 0x158, 5, 0x830, 0, NO_PAD_CTRL) -#define MX35_PAD_TX5_RX0__EMI_M3IF_CHOSEN_MASTER_0 IOMUX_PAD(0x59c, 0x158, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_TX4_RX1__ESAI_TX4_RX1 IOMUX_PAD(0x5a0, 0x15c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX4_RX1__AUDMUX_AUD4_RXFS IOMUX_PAD(0x5a0, 0x15c, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX4_RX1__CSPI2_SS3 IOMUX_PAD(0x5a0, 0x15c, 2, 0x7fc, 0, NO_PAD_CTRL) -#define MX35_PAD_TX4_RX1__CAN2_RXCAN IOMUX_PAD(0x5a0, 0x15c, 3, 0x7cc, 0, NO_PAD_CTRL) -#define MX35_PAD_TX4_RX1__UART2_DSR IOMUX_PAD(0x5a0, 0x15c, 4, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX4_RX1__GPIO1_11 IOMUX_PAD(0x5a0, 0x15c, 5, 0x834, 0, NO_PAD_CTRL) -#define MX35_PAD_TX4_RX1__IPU_CSI_D_3 IOMUX_PAD(0x5a0, 0x15c, 6, 0x93c, 0, NO_PAD_CTRL) -#define MX35_PAD_TX4_RX1__KPP_ROW_0 IOMUX_PAD(0x5a0, 0x15c, 7, 0x970, 1, NO_PAD_CTRL) - -#define MX35_PAD_TX3_RX2__ESAI_TX3_RX2 IOMUX_PAD(0x5a4, 0x160, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX3_RX2__I2C3_SCL IOMUX_PAD(0x5a4, 0x160, 1, 0x91c, 0, NO_PAD_CTRL) -#define MX35_PAD_TX3_RX2__EMI_NANDF_CE1 IOMUX_PAD(0x5a4, 0x160, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX3_RX2__GPIO1_12 IOMUX_PAD(0x5a4, 0x160, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX3_RX2__IPU_CSI_D_4 IOMUX_PAD(0x5a4, 0x160, 6, 0x940, 0, NO_PAD_CTRL) -#define MX35_PAD_TX3_RX2__KPP_ROW_1 IOMUX_PAD(0x5a4, 0x160, 7, 0x974, 1, NO_PAD_CTRL) - -#define MX35_PAD_TX2_RX3__ESAI_TX2_RX3 IOMUX_PAD(0x5a8, 0x164, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX2_RX3__I2C3_SDA IOMUX_PAD(0x5a8, 0x164, 1, 0x920, 0, NO_PAD_CTRL) -#define MX35_PAD_TX2_RX3__EMI_NANDF_CE2 IOMUX_PAD(0x5a8, 0x164, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX2_RX3__GPIO1_13 IOMUX_PAD(0x5a8, 0x164, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX2_RX3__IPU_CSI_D_5 IOMUX_PAD(0x5a8, 0x164, 6, 0x944, 0, NO_PAD_CTRL) -#define MX35_PAD_TX2_RX3__KPP_COL_0 IOMUX_PAD(0x5a8, 0x164, 7, 0x950, 1, NO_PAD_CTRL) - -#define MX35_PAD_TX1__ESAI_TX1 IOMUX_PAD(0x5ac, 0x168, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX1__CCM_PMIC_RDY IOMUX_PAD(0x5ac, 0x168, 1, 0x7d4, 1, NO_PAD_CTRL) -#define MX35_PAD_TX1__CSPI1_SS2 IOMUX_PAD(0x5ac, 0x168, 2, 0x7d8, 2, NO_PAD_CTRL) -#define MX35_PAD_TX1__EMI_NANDF_CE3 IOMUX_PAD(0x5ac, 0x168, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX1__UART2_RI IOMUX_PAD(0x5ac, 0x168, 4, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX1__GPIO1_14 IOMUX_PAD(0x5ac, 0x168, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX1__IPU_CSI_D_6 IOMUX_PAD(0x5ac, 0x168, 6, 0x948, 0, NO_PAD_CTRL) -#define MX35_PAD_TX1__KPP_COL_1 IOMUX_PAD(0x5ac, 0x168, 7, 0x954, 1, NO_PAD_CTRL) - -#define MX35_PAD_TX0__ESAI_TX0 IOMUX_PAD(0x5b0, 0x16c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX0__SPDIF_SPDIF_EXTCLK IOMUX_PAD(0x5b0, 0x16c, 1, 0x994, 1, NO_PAD_CTRL) -#define MX35_PAD_TX0__CSPI1_SS3 IOMUX_PAD(0x5b0, 0x16c, 2, 0x7dc, 0, NO_PAD_CTRL) -#define MX35_PAD_TX0__EMI_DTACK_B IOMUX_PAD(0x5b0, 0x16c, 3, 0x800, 1, NO_PAD_CTRL) -#define MX35_PAD_TX0__UART2_DCD IOMUX_PAD(0x5b0, 0x16c, 4, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX0__GPIO1_15 IOMUX_PAD(0x5b0, 0x16c, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TX0__IPU_CSI_D_7 IOMUX_PAD(0x5b0, 0x16c, 6, 0x94c, 0, NO_PAD_CTRL) -#define MX35_PAD_TX0__KPP_COL_2 IOMUX_PAD(0x5b0, 0x16c, 7, 0x958, 1, NO_PAD_CTRL) - -#define MX35_PAD_CSPI1_MOSI__CSPI1_MOSI IOMUX_PAD(0x5b4, 0x170, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_MOSI__GPIO1_16 IOMUX_PAD(0x5b4, 0x170, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_MOSI__ECT_CTI_TRIG_OUT1_2 IOMUX_PAD(0x5b4, 0x170, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CSPI1_MISO__CSPI1_MISO IOMUX_PAD(0x5b8, 0x174, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_MISO__GPIO1_17 IOMUX_PAD(0x5b8, 0x174, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_MISO__ECT_CTI_TRIG_OUT1_3 IOMUX_PAD(0x5b8, 0x174, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CSPI1_SS0__CSPI1_SS0 IOMUX_PAD(0x5bc, 0x178, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_SS0__OWIRE_LINE IOMUX_PAD(0x5bc, 0x178, 1, 0x990, 1, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_SS0__CSPI2_SS3 IOMUX_PAD(0x5bc, 0x178, 2, 0x7fc, 1, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_SS0__GPIO1_18 IOMUX_PAD(0x5bc, 0x178, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_SS0__ECT_CTI_TRIG_OUT1_4 IOMUX_PAD(0x5bc, 0x178, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CSPI1_SS1__CSPI1_SS1 IOMUX_PAD(0x5c0, 0x17c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_SS1__PWM_PWMO IOMUX_PAD(0x5c0, 0x17c, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_SS1__CCM_CLK32K IOMUX_PAD(0x5c0, 0x17c, 2, 0x7d0, 1, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_SS1__GPIO1_19 IOMUX_PAD(0x5c0, 0x17c, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_SS1__IPU_DIAGB_29 IOMUX_PAD(0x5c0, 0x17c, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_SS1__ECT_CTI_TRIG_OUT1_5 IOMUX_PAD(0x5c0, 0x17c, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CSPI1_SCLK__CSPI1_SCLK IOMUX_PAD(0x5c4, 0x180, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_SCLK__GPIO3_4 IOMUX_PAD(0x5c4, 0x180, 5, 0x904, 0, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_SCLK__IPU_DIAGB_30 IOMUX_PAD(0x5c4, 0x180, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_SCLK__EMI_M3IF_CHOSEN_MASTER_1 IOMUX_PAD(0x5c4, 0x180, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CSPI1_SPI_RDY__CSPI1_RDY IOMUX_PAD(0x5c8, 0x184, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_SPI_RDY__GPIO3_5 IOMUX_PAD(0x5c8, 0x184, 5, 0x908, 0, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_SPI_RDY__IPU_DIAGB_31 IOMUX_PAD(0x5c8, 0x184, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CSPI1_SPI_RDY__EMI_M3IF_CHOSEN_MASTER_2 IOMUX_PAD(0x5c8, 0x184, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_RXD1__UART1_RXD_MUX IOMUX_PAD(0x5cc, 0x188, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_RXD1__CSPI2_MOSI IOMUX_PAD(0x5cc, 0x188, 1, 0x7ec, 1, NO_PAD_CTRL) -#define MX35_PAD_RXD1__KPP_COL_4 IOMUX_PAD(0x5cc, 0x188, 4, 0x960, 0, NO_PAD_CTRL) -#define MX35_PAD_RXD1__GPIO3_6 IOMUX_PAD(0x5cc, 0x188, 5, 0x90c, 0, NO_PAD_CTRL) -#define MX35_PAD_RXD1__ARM11P_TOP_EVNTBUS_16 IOMUX_PAD(0x5cc, 0x188, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_TXD1__UART1_TXD_MUX IOMUX_PAD(0x5d0, 0x18c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TXD1__CSPI2_MISO IOMUX_PAD(0x5d0, 0x18c, 1, 0x7e8, 1, NO_PAD_CTRL) -#define MX35_PAD_TXD1__KPP_COL_5 IOMUX_PAD(0x5d0, 0x18c, 4, 0x964, 0, NO_PAD_CTRL) -#define MX35_PAD_TXD1__GPIO3_7 IOMUX_PAD(0x5d0, 0x18c, 5, 0x910, 0, NO_PAD_CTRL) -#define MX35_PAD_TXD1__ARM11P_TOP_EVNTBUS_17 IOMUX_PAD(0x5d0, 0x18c, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_RTS1__UART1_RTS IOMUX_PAD(0x5d4, 0x190, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_RTS1__CSPI2_SCLK IOMUX_PAD(0x5d4, 0x190, 1, 0x7e0, 1, NO_PAD_CTRL) -#define MX35_PAD_RTS1__I2C3_SCL IOMUX_PAD(0x5d4, 0x190, 2, 0x91c, 1, NO_PAD_CTRL) -#define MX35_PAD_RTS1__IPU_CSI_D_0 IOMUX_PAD(0x5d4, 0x190, 3, 0x930, 1, NO_PAD_CTRL) -#define MX35_PAD_RTS1__KPP_COL_6 IOMUX_PAD(0x5d4, 0x190, 4, 0x968, 0, NO_PAD_CTRL) -#define MX35_PAD_RTS1__GPIO3_8 IOMUX_PAD(0x5d4, 0x190, 5, 0x914, 0, NO_PAD_CTRL) -#define MX35_PAD_RTS1__EMI_NANDF_CE1 IOMUX_PAD(0x5d4, 0x190, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_RTS1__ARM11P_TOP_EVNTBUS_18 IOMUX_PAD(0x5d4, 0x190, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CTS1__UART1_CTS IOMUX_PAD(0x5d8, 0x194, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CTS1__CSPI2_RDY IOMUX_PAD(0x5d8, 0x194, 1, 0x7e4, 1, NO_PAD_CTRL) -#define MX35_PAD_CTS1__I2C3_SDA IOMUX_PAD(0x5d8, 0x194, 2, 0x920, 1, NO_PAD_CTRL) -#define MX35_PAD_CTS1__IPU_CSI_D_1 IOMUX_PAD(0x5d8, 0x194, 3, 0x934, 1, NO_PAD_CTRL) -#define MX35_PAD_CTS1__KPP_COL_7 IOMUX_PAD(0x5d8, 0x194, 4, 0x96c, 0, NO_PAD_CTRL) -#define MX35_PAD_CTS1__GPIO3_9 IOMUX_PAD(0x5d8, 0x194, 5, 0x918, 0, NO_PAD_CTRL) -#define MX35_PAD_CTS1__EMI_NANDF_CE2 IOMUX_PAD(0x5d8, 0x194, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CTS1__ARM11P_TOP_EVNTBUS_19 IOMUX_PAD(0x5d8, 0x194, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_RXD2__UART2_RXD_MUX IOMUX_PAD(0x5dc, 0x198, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_RXD2__KPP_ROW_4 IOMUX_PAD(0x5dc, 0x198, 4, 0x980, 0, NO_PAD_CTRL) -#define MX35_PAD_RXD2__GPIO3_10 IOMUX_PAD(0x5dc, 0x198, 5, 0x8ec, 0, NO_PAD_CTRL) - -#define MX35_PAD_TXD2__UART2_TXD_MUX IOMUX_PAD(0x5e0, 0x19c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_TXD2__SPDIF_SPDIF_EXTCLK IOMUX_PAD(0x5e0, 0x19c, 1, 0x994, 2, NO_PAD_CTRL) -#define MX35_PAD_TXD2__KPP_ROW_5 IOMUX_PAD(0x5e0, 0x19c, 4, 0x984, 0, NO_PAD_CTRL) -#define MX35_PAD_TXD2__GPIO3_11 IOMUX_PAD(0x5e0, 0x19c, 5, 0x8f0, 0, NO_PAD_CTRL) - -#define MX35_PAD_RTS2__UART2_RTS IOMUX_PAD(0x5e4, 0x1a0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_RTS2__SPDIF_SPDIF_IN1 IOMUX_PAD(0x5e4, 0x1a0, 1, 0x998, 1, NO_PAD_CTRL) -#define MX35_PAD_RTS2__CAN2_RXCAN IOMUX_PAD(0x5e4, 0x1a0, 2, 0x7cc, 1, NO_PAD_CTRL) -#define MX35_PAD_RTS2__IPU_CSI_D_2 IOMUX_PAD(0x5e4, 0x1a0, 3, 0x938, 1, NO_PAD_CTRL) -#define MX35_PAD_RTS2__KPP_ROW_6 IOMUX_PAD(0x5e4, 0x1a0, 4, 0x988, 0, NO_PAD_CTRL) -#define MX35_PAD_RTS2__GPIO3_12 IOMUX_PAD(0x5e4, 0x1a0, 5, 0x8f4, 0, NO_PAD_CTRL) -#define MX35_PAD_RTS2__AUDMUX_AUD5_RXC IOMUX_PAD(0x5e4, 0x1a0, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_RTS2__UART3_RXD_MUX IOMUX_PAD(0x5e4, 0x1a0, 7, 0x9a0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CTS2__UART2_CTS IOMUX_PAD(0x5e8, 0x1a4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CTS2__SPDIF_SPDIF_OUT1 IOMUX_PAD(0x5e8, 0x1a4, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CTS2__CAN2_TXCAN IOMUX_PAD(0x5e8, 0x1a4, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CTS2__IPU_CSI_D_3 IOMUX_PAD(0x5e8, 0x1a4, 3, 0x93c, 1, NO_PAD_CTRL) -#define MX35_PAD_CTS2__KPP_ROW_7 IOMUX_PAD(0x5e8, 0x1a4, 4, 0x98c, 0, NO_PAD_CTRL) -#define MX35_PAD_CTS2__GPIO3_13 IOMUX_PAD(0x5e8, 0x1a4, 5, 0x8f8, 0, NO_PAD_CTRL) -#define MX35_PAD_CTS2__AUDMUX_AUD5_RXFS IOMUX_PAD(0x5e8, 0x1a4, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CTS2__UART3_TXD_MUX IOMUX_PAD(0x5e8, 0x1a4, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_RTCK__ARM11P_TOP_RTCK IOMUX_PAD(0x5ec, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_TCK__SJC_TCK IOMUX_PAD(0x5f0, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_TMS__SJC_TMS IOMUX_PAD(0x5f4, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_TDI__SJC_TDI IOMUX_PAD(0x5f8, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_TDO__SJC_TDO IOMUX_PAD(0x5fc, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_TRSTB__SJC_TRSTB IOMUX_PAD(0x600, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_DE_B__SJC_DE_B IOMUX_PAD(0x604, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SJC_MOD__SJC_MOD IOMUX_PAD(0x608, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR IOMUX_PAD(0x60c, 0x1a8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_USBOTG_PWR__USB_TOP_USBH2_PWR IOMUX_PAD(0x60c, 0x1a8, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_USBOTG_PWR__GPIO3_14 IOMUX_PAD(0x60c, 0x1a8, 5, 0x8fc, 0, NO_PAD_CTRL) - -#define MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC IOMUX_PAD(0x610, 0x1ac, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_USBOTG_OC__USB_TOP_USBH2_OC IOMUX_PAD(0x610, 0x1ac, 1, 0x9f4, 1, NO_PAD_CTRL) -#define MX35_PAD_USBOTG_OC__GPIO3_15 IOMUX_PAD(0x610, 0x1ac, 5, 0x900, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD0__IPU_DISPB_DAT_0 IOMUX_PAD(0x614, 0x1b0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD0__GPIO2_0 IOMUX_PAD(0x614, 0x1b0, 5, 0x868, 1, NO_PAD_CTRL) -#define MX35_PAD_LD0__SDMA_SDMA_DEBUG_PC_0 IOMUX_PAD(0x614, 0x1b0, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD1__IPU_DISPB_DAT_1 IOMUX_PAD(0x618, 0x1b4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD1__GPIO2_1 IOMUX_PAD(0x618, 0x1b4, 5, 0x894, 0, NO_PAD_CTRL) -#define MX35_PAD_LD1__SDMA_SDMA_DEBUG_PC_1 IOMUX_PAD(0x618, 0x1b4, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD2__IPU_DISPB_DAT_2 IOMUX_PAD(0x61c, 0x1b8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD2__GPIO2_2 IOMUX_PAD(0x61c, 0x1b8, 5, 0x8c0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD2__SDMA_SDMA_DEBUG_PC_2 IOMUX_PAD(0x61c, 0x1b8, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD3__IPU_DISPB_DAT_3 IOMUX_PAD(0x620, 0x1bc, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD3__GPIO2_3 IOMUX_PAD(0x620, 0x1bc, 5, 0x8cc, 0, NO_PAD_CTRL) -#define MX35_PAD_LD3__SDMA_SDMA_DEBUG_PC_3 IOMUX_PAD(0x620, 0x1bc, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD4__IPU_DISPB_DAT_4 IOMUX_PAD(0x624, 0x1c0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD4__GPIO2_4 IOMUX_PAD(0x624, 0x1c0, 5, 0x8d0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD4__SDMA_SDMA_DEBUG_PC_4 IOMUX_PAD(0x624, 0x1c0, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD5__IPU_DISPB_DAT_5 IOMUX_PAD(0x628, 0x1c4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD5__GPIO2_5 IOMUX_PAD(0x628, 0x1c4, 5, 0x8d4, 0, NO_PAD_CTRL) -#define MX35_PAD_LD5__SDMA_SDMA_DEBUG_PC_5 IOMUX_PAD(0x628, 0x1c4, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD6__IPU_DISPB_DAT_6 IOMUX_PAD(0x62c, 0x1c8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD6__GPIO2_6 IOMUX_PAD(0x62c, 0x1c8, 5, 0x8d8, 0, NO_PAD_CTRL) -#define MX35_PAD_LD6__SDMA_SDMA_DEBUG_PC_6 IOMUX_PAD(0x62c, 0x1c8, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD7__IPU_DISPB_DAT_7 IOMUX_PAD(0x630, 0x1cc, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD7__GPIO2_7 IOMUX_PAD(0x630, 0x1cc, 5, 0x8dc, 0, NO_PAD_CTRL) -#define MX35_PAD_LD7__SDMA_SDMA_DEBUG_PC_7 IOMUX_PAD(0x630, 0x1cc, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD8__IPU_DISPB_DAT_8 IOMUX_PAD(0x634, 0x1d0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD8__GPIO2_8 IOMUX_PAD(0x634, 0x1d0, 5, 0x8e0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD8__SDMA_SDMA_DEBUG_PC_8 IOMUX_PAD(0x634, 0x1d0, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD9__IPU_DISPB_DAT_9 IOMUX_PAD(0x638, 0x1d4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD9__GPIO2_9 IOMUX_PAD(0x638, 0x1d4, 5, 0x8e4, 0, NO_PAD_CTRL) -#define MX35_PAD_LD9__SDMA_SDMA_DEBUG_PC_9 IOMUX_PAD(0x638, 0x1d4, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD10__IPU_DISPB_DAT_10 IOMUX_PAD(0x63c, 0x1d8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD10__GPIO2_10 IOMUX_PAD(0x63c, 0x1d8, 5, 0x86c, 0, NO_PAD_CTRL) -#define MX35_PAD_LD10__SDMA_SDMA_DEBUG_PC_10 IOMUX_PAD(0x63c, 0x1d8, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD11__IPU_DISPB_DAT_11 IOMUX_PAD(0x640, 0x1dc, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD11__GPIO2_11 IOMUX_PAD(0x640, 0x1dc, 5, 0x870, 0, NO_PAD_CTRL) -#define MX35_PAD_LD11__SDMA_SDMA_DEBUG_PC_11 IOMUX_PAD(0x640, 0x1dc, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD11__ARM11P_TOP_TRACE_4 IOMUX_PAD(0x640, 0x1dc, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD12__IPU_DISPB_DAT_12 IOMUX_PAD(0x644, 0x1e0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD12__GPIO2_12 IOMUX_PAD(0x644, 0x1e0, 5, 0x874, 0, NO_PAD_CTRL) -#define MX35_PAD_LD12__SDMA_SDMA_DEBUG_PC_12 IOMUX_PAD(0x644, 0x1e0, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD12__ARM11P_TOP_TRACE_5 IOMUX_PAD(0x644, 0x1e0, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD13__IPU_DISPB_DAT_13 IOMUX_PAD(0x648, 0x1e4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD13__GPIO2_13 IOMUX_PAD(0x648, 0x1e4, 5, 0x878, 0, NO_PAD_CTRL) -#define MX35_PAD_LD13__SDMA_SDMA_DEBUG_PC_13 IOMUX_PAD(0x648, 0x1e4, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD13__ARM11P_TOP_TRACE_6 IOMUX_PAD(0x648, 0x1e4, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD14__IPU_DISPB_DAT_14 IOMUX_PAD(0x64c, 0x1e8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD14__GPIO2_14 IOMUX_PAD(0x64c, 0x1e8, 5, 0x87c, 0, NO_PAD_CTRL) -#define MX35_PAD_LD14__SDMA_SDMA_DEBUG_EVENT_CHANNEL_0 IOMUX_PAD(0x64c, 0x1e8, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD14__ARM11P_TOP_TRACE_7 IOMUX_PAD(0x64c, 0x1e8, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD15__IPU_DISPB_DAT_15 IOMUX_PAD(0x650, 0x1ec, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD15__GPIO2_15 IOMUX_PAD(0x650, 0x1ec, 5, 0x880, 0, NO_PAD_CTRL) -#define MX35_PAD_LD15__SDMA_SDMA_DEBUG_EVENT_CHANNEL_1 IOMUX_PAD(0x650, 0x1ec, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD15__ARM11P_TOP_TRACE_8 IOMUX_PAD(0x650, 0x1ec, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD16__IPU_DISPB_DAT_16 IOMUX_PAD(0x654, 0x1f0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD16__IPU_DISPB_D12_VSYNC IOMUX_PAD(0x654, 0x1f0, 2, 0x928, 0, NO_PAD_CTRL) -#define MX35_PAD_LD16__GPIO2_16 IOMUX_PAD(0x654, 0x1f0, 5, 0x884, 0, NO_PAD_CTRL) -#define MX35_PAD_LD16__SDMA_SDMA_DEBUG_EVENT_CHANNEL_2 IOMUX_PAD(0x654, 0x1f0, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD16__ARM11P_TOP_TRACE_9 IOMUX_PAD(0x654, 0x1f0, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD17__IPU_DISPB_DAT_17 IOMUX_PAD(0x658, 0x1f4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD17__IPU_DISPB_CS2 IOMUX_PAD(0x658, 0x1f4, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD17__GPIO2_17 IOMUX_PAD(0x658, 0x1f4, 5, 0x888, 0, NO_PAD_CTRL) -#define MX35_PAD_LD17__SDMA_SDMA_DEBUG_EVENT_CHANNEL_3 IOMUX_PAD(0x658, 0x1f4, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD17__ARM11P_TOP_TRACE_10 IOMUX_PAD(0x658, 0x1f4, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD18__IPU_DISPB_DAT_18 IOMUX_PAD(0x65c, 0x1f8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD18__IPU_DISPB_D0_VSYNC IOMUX_PAD(0x65c, 0x1f8, 1, 0x924, 1, NO_PAD_CTRL) -#define MX35_PAD_LD18__IPU_DISPB_D12_VSYNC IOMUX_PAD(0x65c, 0x1f8, 2, 0x928, 1, NO_PAD_CTRL) -#define MX35_PAD_LD18__ESDHC3_CMD IOMUX_PAD(0x65c, 0x1f8, 3, 0x818, 0, NO_PAD_CTRL) -#define MX35_PAD_LD18__USB_TOP_USBOTG_DATA_3 IOMUX_PAD(0x65c, 0x1f8, 4, 0x9b0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD18__GPIO3_24 IOMUX_PAD(0x65c, 0x1f8, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD18__SDMA_SDMA_DEBUG_EVENT_CHANNEL_4 IOMUX_PAD(0x65c, 0x1f8, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD18__ARM11P_TOP_TRACE_11 IOMUX_PAD(0x65c, 0x1f8, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD19__IPU_DISPB_DAT_19 IOMUX_PAD(0x660, 0x1fc, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD19__IPU_DISPB_BCLK IOMUX_PAD(0x660, 0x1fc, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD19__IPU_DISPB_CS1 IOMUX_PAD(0x660, 0x1fc, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD19__ESDHC3_CLK IOMUX_PAD(0x660, 0x1fc, 3, 0x814, 0, NO_PAD_CTRL) -#define MX35_PAD_LD19__USB_TOP_USBOTG_DIR IOMUX_PAD(0x660, 0x1fc, 4, 0x9c4, 0, NO_PAD_CTRL) -#define MX35_PAD_LD19__GPIO3_25 IOMUX_PAD(0x660, 0x1fc, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD19__SDMA_SDMA_DEBUG_EVENT_CHANNEL_5 IOMUX_PAD(0x660, 0x1fc, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD19__ARM11P_TOP_TRACE_12 IOMUX_PAD(0x660, 0x1fc, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD20__IPU_DISPB_DAT_20 IOMUX_PAD(0x664, 0x200, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD20__IPU_DISPB_CS0 IOMUX_PAD(0x664, 0x200, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD20__IPU_DISPB_SD_CLK IOMUX_PAD(0x664, 0x200, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD20__ESDHC3_DAT0 IOMUX_PAD(0x664, 0x200, 3, 0x81c, 0, NO_PAD_CTRL) -#define MX35_PAD_LD20__GPIO3_26 IOMUX_PAD(0x664, 0x200, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD20__SDMA_SDMA_DEBUG_CORE_STATUS_3 IOMUX_PAD(0x664, 0x200, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD20__ARM11P_TOP_TRACE_13 IOMUX_PAD(0x664, 0x200, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD21__IPU_DISPB_DAT_21 IOMUX_PAD(0x668, 0x204, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD21__IPU_DISPB_PAR_RS IOMUX_PAD(0x668, 0x204, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD21__IPU_DISPB_SER_RS IOMUX_PAD(0x668, 0x204, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD21__ESDHC3_DAT1 IOMUX_PAD(0x668, 0x204, 3, 0x820, 0, NO_PAD_CTRL) -#define MX35_PAD_LD21__USB_TOP_USBOTG_STP IOMUX_PAD(0x668, 0x204, 4, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD21__GPIO3_27 IOMUX_PAD(0x668, 0x204, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD21__SDMA_DEBUG_EVENT_CHANNEL_SEL IOMUX_PAD(0x668, 0x204, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD21__ARM11P_TOP_TRACE_14 IOMUX_PAD(0x668, 0x204, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD22__IPU_DISPB_DAT_22 IOMUX_PAD(0x66c, 0x208, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD22__IPU_DISPB_WR IOMUX_PAD(0x66c, 0x208, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD22__IPU_DISPB_SD_D_I IOMUX_PAD(0x66c, 0x208, 2, 0x92c, 0, NO_PAD_CTRL) -#define MX35_PAD_LD22__ESDHC3_DAT2 IOMUX_PAD(0x66c, 0x208, 3, 0x824, 0, NO_PAD_CTRL) -#define MX35_PAD_LD22__USB_TOP_USBOTG_NXT IOMUX_PAD(0x66c, 0x208, 4, 0x9c8, 0, NO_PAD_CTRL) -#define MX35_PAD_LD22__GPIO3_28 IOMUX_PAD(0x66c, 0x208, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD22__SDMA_DEBUG_BUS_ERROR IOMUX_PAD(0x66c, 0x208, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD22__ARM11P_TOP_TRCTL IOMUX_PAD(0x66c, 0x208, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_LD23__IPU_DISPB_DAT_23 IOMUX_PAD(0x670, 0x20c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD23__IPU_DISPB_RD IOMUX_PAD(0x670, 0x20c, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD23__IPU_DISPB_SD_D_IO IOMUX_PAD(0x670, 0x20c, 2, 0x92c, 1, NO_PAD_CTRL) -#define MX35_PAD_LD23__ESDHC3_DAT3 IOMUX_PAD(0x670, 0x20c, 3, 0x828, 0, NO_PAD_CTRL) -#define MX35_PAD_LD23__USB_TOP_USBOTG_DATA_7 IOMUX_PAD(0x670, 0x20c, 4, 0x9c0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD23__GPIO3_29 IOMUX_PAD(0x670, 0x20c, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD23__SDMA_DEBUG_MATCHED_DMBUS IOMUX_PAD(0x670, 0x20c, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_LD23__ARM11P_TOP_TRCLK IOMUX_PAD(0x670, 0x20c, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC IOMUX_PAD(0x674, 0x210, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_HSYNC__IPU_DISPB_SD_D_IO IOMUX_PAD(0x674, 0x210, 2, 0x92c, 2, NO_PAD_CTRL) -#define MX35_PAD_D3_HSYNC__GPIO3_30 IOMUX_PAD(0x674, 0x210, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_HSYNC__SDMA_DEBUG_RTBUFFER_WRITE IOMUX_PAD(0x674, 0x210, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_HSYNC__ARM11P_TOP_TRACE_15 IOMUX_PAD(0x674, 0x210, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK IOMUX_PAD(0x678, 0x214, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_FPSHIFT__IPU_DISPB_SD_CLK IOMUX_PAD(0x678, 0x214, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_FPSHIFT__GPIO3_31 IOMUX_PAD(0x678, 0x214, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_FPSHIFT__SDMA_SDMA_DEBUG_CORE_STATUS_0 IOMUX_PAD(0x678, 0x214, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_FPSHIFT__ARM11P_TOP_TRACE_16 IOMUX_PAD(0x678, 0x214, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY IOMUX_PAD(0x67c, 0x218, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_DRDY__IPU_DISPB_SD_D_O IOMUX_PAD(0x67c, 0x218, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_DRDY__GPIO1_0 IOMUX_PAD(0x67c, 0x218, 5, 0x82c, 2, NO_PAD_CTRL) -#define MX35_PAD_D3_DRDY__SDMA_SDMA_DEBUG_CORE_STATUS_1 IOMUX_PAD(0x67c, 0x218, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_DRDY__ARM11P_TOP_TRACE_17 IOMUX_PAD(0x67c, 0x218, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_CONTRAST__IPU_DISPB_CONTR IOMUX_PAD(0x680, 0x21c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CONTRAST__GPIO1_1 IOMUX_PAD(0x680, 0x21c, 5, 0x838, 2, NO_PAD_CTRL) -#define MX35_PAD_CONTRAST__SDMA_SDMA_DEBUG_CORE_STATUS_2 IOMUX_PAD(0x680, 0x21c, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_CONTRAST__ARM11P_TOP_TRACE_18 IOMUX_PAD(0x680, 0x21c, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC IOMUX_PAD(0x684, 0x220, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_VSYNC__IPU_DISPB_CS1 IOMUX_PAD(0x684, 0x220, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_VSYNC__GPIO1_2 IOMUX_PAD(0x684, 0x220, 5, 0x848, 1, NO_PAD_CTRL) -#define MX35_PAD_D3_VSYNC__SDMA_DEBUG_YIELD IOMUX_PAD(0x684, 0x220, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_VSYNC__ARM11P_TOP_TRACE_19 IOMUX_PAD(0x684, 0x220, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D3_REV__IPU_DISPB_D3_REV IOMUX_PAD(0x688, 0x224, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_REV__IPU_DISPB_SER_RS IOMUX_PAD(0x688, 0x224, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_REV__GPIO1_3 IOMUX_PAD(0x688, 0x224, 5, 0x84c, 1, NO_PAD_CTRL) -#define MX35_PAD_D3_REV__SDMA_DEBUG_BUS_RWB IOMUX_PAD(0x688, 0x224, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_REV__ARM11P_TOP_TRACE_20 IOMUX_PAD(0x688, 0x224, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS IOMUX_PAD(0x68c, 0x228, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_CLS__IPU_DISPB_CS2 IOMUX_PAD(0x68c, 0x228, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_CLS__GPIO1_4 IOMUX_PAD(0x68c, 0x228, 5, 0x850, 2, NO_PAD_CTRL) -#define MX35_PAD_D3_CLS__SDMA_DEBUG_BUS_DEVICE_0 IOMUX_PAD(0x68c, 0x228, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_CLS__ARM11P_TOP_TRACE_21 IOMUX_PAD(0x68c, 0x228, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_D3_SPL__IPU_DISPB_D3_SPL IOMUX_PAD(0x690, 0x22c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_SPL__IPU_DISPB_D12_VSYNC IOMUX_PAD(0x690, 0x22c, 2, 0x928, 2, NO_PAD_CTRL) -#define MX35_PAD_D3_SPL__GPIO1_5 IOMUX_PAD(0x690, 0x22c, 5, 0x854, 2, NO_PAD_CTRL) -#define MX35_PAD_D3_SPL__SDMA_DEBUG_BUS_DEVICE_1 IOMUX_PAD(0x690, 0x22c, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_D3_SPL__ARM11P_TOP_TRACE_22 IOMUX_PAD(0x690, 0x22c, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD1_CMD__ESDHC1_CMD IOMUX_PAD(0x694, 0x230, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_CMD__MSHC_SCLK IOMUX_PAD(0x694, 0x230, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_CMD__IPU_DISPB_D0_VSYNC IOMUX_PAD(0x694, 0x230, 3, 0x924, 2, NO_PAD_CTRL) -#define MX35_PAD_SD1_CMD__USB_TOP_USBOTG_DATA_4 IOMUX_PAD(0x694, 0x230, 4, 0x9b4, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_CMD__GPIO1_6 IOMUX_PAD(0x694, 0x230, 5, 0x858, 2, NO_PAD_CTRL) -#define MX35_PAD_SD1_CMD__ARM11P_TOP_TRCTL IOMUX_PAD(0x694, 0x230, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD1_CLK__ESDHC1_CLK IOMUX_PAD(0x698, 0x234, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_CLK__MSHC_BS IOMUX_PAD(0x698, 0x234, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_CLK__IPU_DISPB_BCLK IOMUX_PAD(0x698, 0x234, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_CLK__USB_TOP_USBOTG_DATA_5 IOMUX_PAD(0x698, 0x234, 4, 0x9b8, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_CLK__GPIO1_7 IOMUX_PAD(0x698, 0x234, 5, 0x85c, 2, NO_PAD_CTRL) -#define MX35_PAD_SD1_CLK__ARM11P_TOP_TRCLK IOMUX_PAD(0x698, 0x234, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD1_DATA0__ESDHC1_DAT0 IOMUX_PAD(0x69c, 0x238, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA0__MSHC_DATA_0 IOMUX_PAD(0x69c, 0x238, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA0__IPU_DISPB_CS0 IOMUX_PAD(0x69c, 0x238, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA0__USB_TOP_USBOTG_DATA_6 IOMUX_PAD(0x69c, 0x238, 4, 0x9bc, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA0__GPIO1_8 IOMUX_PAD(0x69c, 0x238, 5, 0x860, 2, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA0__ARM11P_TOP_TRACE_23 IOMUX_PAD(0x69c, 0x238, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD1_DATA1__ESDHC1_DAT1 IOMUX_PAD(0x6a0, 0x23c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA1__MSHC_DATA_1 IOMUX_PAD(0x6a0, 0x23c, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA1__IPU_DISPB_PAR_RS IOMUX_PAD(0x6a0, 0x23c, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA1__USB_TOP_USBOTG_DATA_0 IOMUX_PAD(0x6a0, 0x23c, 4, 0x9a4, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA1__GPIO1_9 IOMUX_PAD(0x6a0, 0x23c, 5, 0x864, 1, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA1__ARM11P_TOP_TRACE_24 IOMUX_PAD(0x6a0, 0x23c, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD1_DATA2__ESDHC1_DAT2 IOMUX_PAD(0x6a4, 0x240, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA2__MSHC_DATA_2 IOMUX_PAD(0x6a4, 0x240, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA2__IPU_DISPB_WR IOMUX_PAD(0x6a4, 0x240, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA2__USB_TOP_USBOTG_DATA_1 IOMUX_PAD(0x6a4, 0x240, 4, 0x9a8, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA2__GPIO1_10 IOMUX_PAD(0x6a4, 0x240, 5, 0x830, 1, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA2__ARM11P_TOP_TRACE_25 IOMUX_PAD(0x6a4, 0x240, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD1_DATA3__ESDHC1_DAT3 IOMUX_PAD(0x6a8, 0x244, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA3__MSHC_DATA_3 IOMUX_PAD(0x6a8, 0x244, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA3__IPU_DISPB_RD IOMUX_PAD(0x6a8, 0x244, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA3__USB_TOP_USBOTG_DATA_2 IOMUX_PAD(0x6a8, 0x244, 4, 0x9ac, 0, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA3__GPIO1_11 IOMUX_PAD(0x6a8, 0x244, 5, 0x834, 1, NO_PAD_CTRL) -#define MX35_PAD_SD1_DATA3__ARM11P_TOP_TRACE_26 IOMUX_PAD(0x6a8, 0x244, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD2_CMD__ESDHC2_CMD IOMUX_PAD(0x6ac, 0x248, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_CMD__I2C3_SCL IOMUX_PAD(0x6ac, 0x248, 1, 0x91c, 2, NO_PAD_CTRL) -#define MX35_PAD_SD2_CMD__ESDHC1_DAT4 IOMUX_PAD(0x6ac, 0x248, 2, 0x804, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_CMD__IPU_CSI_D_2 IOMUX_PAD(0x6ac, 0x248, 3, 0x938, 2, NO_PAD_CTRL) -#define MX35_PAD_SD2_CMD__USB_TOP_USBH2_DATA_4 IOMUX_PAD(0x6ac, 0x248, 4, 0x9dc, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_CMD__GPIO2_0 IOMUX_PAD(0x6ac, 0x248, 5, 0x868, 2, NO_PAD_CTRL) -#define MX35_PAD_SD2_CMD__SPDIF_SPDIF_OUT1 IOMUX_PAD(0x6ac, 0x248, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_CMD__IPU_DISPB_D12_VSYNC IOMUX_PAD(0x6ac, 0x248, 7, 0x928, 3, NO_PAD_CTRL) - -#define MX35_PAD_SD2_CLK__ESDHC2_CLK IOMUX_PAD(0x6b0, 0x24c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_CLK__I2C3_SDA IOMUX_PAD(0x6b0, 0x24c, 1, 0x920, 2, NO_PAD_CTRL) -#define MX35_PAD_SD2_CLK__ESDHC1_DAT5 IOMUX_PAD(0x6b0, 0x24c, 2, 0x808, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_CLK__IPU_CSI_D_3 IOMUX_PAD(0x6b0, 0x24c, 3, 0x93c, 2, NO_PAD_CTRL) -#define MX35_PAD_SD2_CLK__USB_TOP_USBH2_DATA_5 IOMUX_PAD(0x6b0, 0x24c, 4, 0x9e0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_CLK__GPIO2_1 IOMUX_PAD(0x6b0, 0x24c, 5, 0x894, 1, NO_PAD_CTRL) -#define MX35_PAD_SD2_CLK__SPDIF_SPDIF_IN1 IOMUX_PAD(0x6b0, 0x24c, 6, 0x998, 2, NO_PAD_CTRL) -#define MX35_PAD_SD2_CLK__IPU_DISPB_CS2 IOMUX_PAD(0x6b0, 0x24c, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_SD2_DATA0__ESDHC2_DAT0 IOMUX_PAD(0x6b4, 0x250, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA0__UART3_RXD_MUX IOMUX_PAD(0x6b4, 0x250, 1, 0x9a0, 1, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA0__ESDHC1_DAT6 IOMUX_PAD(0x6b4, 0x250, 2, 0x80c, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA0__IPU_CSI_D_4 IOMUX_PAD(0x6b4, 0x250, 3, 0x940, 1, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA0__USB_TOP_USBH2_DATA_6 IOMUX_PAD(0x6b4, 0x250, 4, 0x9e4, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA0__GPIO2_2 IOMUX_PAD(0x6b4, 0x250, 5, 0x8c0, 1, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA0__SPDIF_SPDIF_EXTCLK IOMUX_PAD(0x6b4, 0x250, 6, 0x994, 3, NO_PAD_CTRL) - -#define MX35_PAD_SD2_DATA1__ESDHC2_DAT1 IOMUX_PAD(0x6b8, 0x254, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA1__UART3_TXD_MUX IOMUX_PAD(0x6b8, 0x254, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA1__ESDHC1_DAT7 IOMUX_PAD(0x6b8, 0x254, 2, 0x810, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA1__IPU_CSI_D_5 IOMUX_PAD(0x6b8, 0x254, 3, 0x944, 1, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA1__USB_TOP_USBH2_DATA_0 IOMUX_PAD(0x6b8, 0x254, 4, 0x9cc, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA1__GPIO2_3 IOMUX_PAD(0x6b8, 0x254, 5, 0x8cc, 1, NO_PAD_CTRL) - -#define MX35_PAD_SD2_DATA2__ESDHC2_DAT2 IOMUX_PAD(0x6bc, 0x258, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA2__UART3_RTS IOMUX_PAD(0x6bc, 0x258, 1, 0x99c, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA2__CAN1_RXCAN IOMUX_PAD(0x6bc, 0x258, 2, 0x7c8, 1, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA2__IPU_CSI_D_6 IOMUX_PAD(0x6bc, 0x258, 3, 0x948, 1, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA2__USB_TOP_USBH2_DATA_1 IOMUX_PAD(0x6bc, 0x258, 4, 0x9d0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA2__GPIO2_4 IOMUX_PAD(0x6bc, 0x258, 5, 0x8d0, 1, NO_PAD_CTRL) - -#define MX35_PAD_SD2_DATA3__ESDHC2_DAT3 IOMUX_PAD(0x6c0, 0x25c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA3__UART3_CTS IOMUX_PAD(0x6c0, 0x25c, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA3__CAN1_TXCAN IOMUX_PAD(0x6c0, 0x25c, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA3__IPU_CSI_D_7 IOMUX_PAD(0x6c0, 0x25c, 3, 0x94c, 1, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA3__USB_TOP_USBH2_DATA_2 IOMUX_PAD(0x6c0, 0x25c, 4, 0x9d4, 0, NO_PAD_CTRL) -#define MX35_PAD_SD2_DATA3__GPIO2_5 IOMUX_PAD(0x6c0, 0x25c, 5, 0x8d4, 1, NO_PAD_CTRL) - -#define MX35_PAD_ATA_CS0__ATA_CS0 IOMUX_PAD(0x6c4, 0x260, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_CS0__CSPI1_SS3 IOMUX_PAD(0x6c4, 0x260, 1, 0x7dc, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_CS0__IPU_DISPB_CS1 IOMUX_PAD(0x6c4, 0x260, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_CS0__GPIO2_6 IOMUX_PAD(0x6c4, 0x260, 5, 0x8d8, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_CS0__IPU_DIAGB_0 IOMUX_PAD(0x6c4, 0x260, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_CS0__ARM11P_TOP_MAX1_HMASTER_0 IOMUX_PAD(0x6c4, 0x260, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_CS1__ATA_CS1 IOMUX_PAD(0x6c8, 0x264, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_CS1__IPU_DISPB_CS2 IOMUX_PAD(0x6c8, 0x264, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_CS1__CSPI2_SS0 IOMUX_PAD(0x6c8, 0x264, 4, 0x7f0, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_CS1__GPIO2_7 IOMUX_PAD(0x6c8, 0x264, 5, 0x8dc, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_CS1__IPU_DIAGB_1 IOMUX_PAD(0x6c8, 0x264, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_CS1__ARM11P_TOP_MAX1_HMASTER_1 IOMUX_PAD(0x6c8, 0x264, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DIOR__ATA_DIOR IOMUX_PAD(0x6cc, 0x268, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DIOR__ESDHC3_DAT0 IOMUX_PAD(0x6cc, 0x268, 1, 0x81c, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DIOR__USB_TOP_USBOTG_DIR IOMUX_PAD(0x6cc, 0x268, 2, 0x9c4, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DIOR__IPU_DISPB_BE0 IOMUX_PAD(0x6cc, 0x268, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DIOR__CSPI2_SS1 IOMUX_PAD(0x6cc, 0x268, 4, 0x7f4, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DIOR__GPIO2_8 IOMUX_PAD(0x6cc, 0x268, 5, 0x8e0, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DIOR__IPU_DIAGB_2 IOMUX_PAD(0x6cc, 0x268, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DIOR__ARM11P_TOP_MAX1_HMASTER_2 IOMUX_PAD(0x6cc, 0x268, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DIOW__ATA_DIOW IOMUX_PAD(0x6d0, 0x26c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DIOW__ESDHC3_DAT1 IOMUX_PAD(0x6d0, 0x26c, 1, 0x820, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DIOW__USB_TOP_USBOTG_STP IOMUX_PAD(0x6d0, 0x26c, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DIOW__IPU_DISPB_BE1 IOMUX_PAD(0x6d0, 0x26c, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DIOW__CSPI2_MOSI IOMUX_PAD(0x6d0, 0x26c, 4, 0x7ec, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_DIOW__GPIO2_9 IOMUX_PAD(0x6d0, 0x26c, 5, 0x8e4, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DIOW__IPU_DIAGB_3 IOMUX_PAD(0x6d0, 0x26c, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DIOW__ARM11P_TOP_MAX1_HMASTER_3 IOMUX_PAD(0x6d0, 0x26c, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DMACK__ATA_DMACK IOMUX_PAD(0x6d4, 0x270, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DMACK__ESDHC3_DAT2 IOMUX_PAD(0x6d4, 0x270, 1, 0x824, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DMACK__USB_TOP_USBOTG_NXT IOMUX_PAD(0x6d4, 0x270, 2, 0x9c8, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DMACK__CSPI2_MISO IOMUX_PAD(0x6d4, 0x270, 4, 0x7e8, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_DMACK__GPIO2_10 IOMUX_PAD(0x6d4, 0x270, 5, 0x86c, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DMACK__IPU_DIAGB_4 IOMUX_PAD(0x6d4, 0x270, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DMACK__ARM11P_TOP_MAX0_HMASTER_0 IOMUX_PAD(0x6d4, 0x270, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_RESET_B__ATA_RESET_B IOMUX_PAD(0x6d8, 0x274, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_RESET_B__ESDHC3_DAT3 IOMUX_PAD(0x6d8, 0x274, 1, 0x828, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_RESET_B__USB_TOP_USBOTG_DATA_0 IOMUX_PAD(0x6d8, 0x274, 2, 0x9a4, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_RESET_B__IPU_DISPB_SD_D_O IOMUX_PAD(0x6d8, 0x274, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_RESET_B__CSPI2_RDY IOMUX_PAD(0x6d8, 0x274, 4, 0x7e4, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_RESET_B__GPIO2_11 IOMUX_PAD(0x6d8, 0x274, 5, 0x870, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_RESET_B__IPU_DIAGB_5 IOMUX_PAD(0x6d8, 0x274, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_RESET_B__ARM11P_TOP_MAX0_HMASTER_1 IOMUX_PAD(0x6d8, 0x274, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_IORDY__ATA_IORDY IOMUX_PAD(0x6dc, 0x278, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_IORDY__ESDHC3_DAT4 IOMUX_PAD(0x6dc, 0x278, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_IORDY__USB_TOP_USBOTG_DATA_1 IOMUX_PAD(0x6dc, 0x278, 2, 0x9a8, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_IORDY__IPU_DISPB_SD_D_IO IOMUX_PAD(0x6dc, 0x278, 3, 0x92c, 3, NO_PAD_CTRL) -#define MX35_PAD_ATA_IORDY__ESDHC2_DAT4 IOMUX_PAD(0x6dc, 0x278, 4, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_IORDY__GPIO2_12 IOMUX_PAD(0x6dc, 0x278, 5, 0x874, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_IORDY__IPU_DIAGB_6 IOMUX_PAD(0x6dc, 0x278, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_IORDY__ARM11P_TOP_MAX0_HMASTER_2 IOMUX_PAD(0x6dc, 0x278, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DATA0__ATA_DATA_0 IOMUX_PAD(0x6e0, 0x27c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA0__ESDHC3_DAT5 IOMUX_PAD(0x6e0, 0x27c, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA0__USB_TOP_USBOTG_DATA_2 IOMUX_PAD(0x6e0, 0x27c, 2, 0x9ac, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA0__IPU_DISPB_D12_VSYNC IOMUX_PAD(0x6e0, 0x27c, 3, 0x928, 4, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA0__ESDHC2_DAT5 IOMUX_PAD(0x6e0, 0x27c, 4, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA0__GPIO2_13 IOMUX_PAD(0x6e0, 0x27c, 5, 0x878, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA0__IPU_DIAGB_7 IOMUX_PAD(0x6e0, 0x27c, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA0__ARM11P_TOP_MAX0_HMASTER_3 IOMUX_PAD(0x6e0, 0x27c, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DATA1__ATA_DATA_1 IOMUX_PAD(0x6e4, 0x280, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA1__ESDHC3_DAT6 IOMUX_PAD(0x6e4, 0x280, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA1__USB_TOP_USBOTG_DATA_3 IOMUX_PAD(0x6e4, 0x280, 2, 0x9b0, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA1__IPU_DISPB_SD_CLK IOMUX_PAD(0x6e4, 0x280, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA1__ESDHC2_DAT6 IOMUX_PAD(0x6e4, 0x280, 4, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA1__GPIO2_14 IOMUX_PAD(0x6e4, 0x280, 5, 0x87c, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA1__IPU_DIAGB_8 IOMUX_PAD(0x6e4, 0x280, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA1__ARM11P_TOP_TRACE_27 IOMUX_PAD(0x6e4, 0x280, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DATA2__ATA_DATA_2 IOMUX_PAD(0x6e8, 0x284, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA2__ESDHC3_DAT7 IOMUX_PAD(0x6e8, 0x284, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA2__USB_TOP_USBOTG_DATA_4 IOMUX_PAD(0x6e8, 0x284, 2, 0x9b4, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA2__IPU_DISPB_SER_RS IOMUX_PAD(0x6e8, 0x284, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA2__ESDHC2_DAT7 IOMUX_PAD(0x6e8, 0x284, 4, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA2__GPIO2_15 IOMUX_PAD(0x6e8, 0x284, 5, 0x880, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA2__IPU_DIAGB_9 IOMUX_PAD(0x6e8, 0x284, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA2__ARM11P_TOP_TRACE_28 IOMUX_PAD(0x6e8, 0x284, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DATA3__ATA_DATA_3 IOMUX_PAD(0x6ec, 0x288, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA3__ESDHC3_CLK IOMUX_PAD(0x6ec, 0x288, 1, 0x814, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA3__USB_TOP_USBOTG_DATA_5 IOMUX_PAD(0x6ec, 0x288, 2, 0x9b8, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA3__CSPI2_SCLK IOMUX_PAD(0x6ec, 0x288, 4, 0x7e0, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA3__GPIO2_16 IOMUX_PAD(0x6ec, 0x288, 5, 0x884, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA3__IPU_DIAGB_10 IOMUX_PAD(0x6ec, 0x288, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA3__ARM11P_TOP_TRACE_29 IOMUX_PAD(0x6ec, 0x288, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DATA4__ATA_DATA_4 IOMUX_PAD(0x6f0, 0x28c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA4__ESDHC3_CMD IOMUX_PAD(0x6f0, 0x28c, 1, 0x818, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA4__USB_TOP_USBOTG_DATA_6 IOMUX_PAD(0x6f0, 0x28c, 2, 0x9bc, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA4__GPIO2_17 IOMUX_PAD(0x6f0, 0x28c, 5, 0x888, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA4__IPU_DIAGB_11 IOMUX_PAD(0x6f0, 0x28c, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA4__ARM11P_TOP_TRACE_30 IOMUX_PAD(0x6f0, 0x28c, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DATA5__ATA_DATA_5 IOMUX_PAD(0x6f4, 0x290, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA5__USB_TOP_USBOTG_DATA_7 IOMUX_PAD(0x6f4, 0x290, 2, 0x9c0, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA5__GPIO2_18 IOMUX_PAD(0x6f4, 0x290, 5, 0x88c, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA5__IPU_DIAGB_12 IOMUX_PAD(0x6f4, 0x290, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA5__ARM11P_TOP_TRACE_31 IOMUX_PAD(0x6f4, 0x290, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DATA6__ATA_DATA_6 IOMUX_PAD(0x6f8, 0x294, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA6__CAN1_TXCAN IOMUX_PAD(0x6f8, 0x294, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA6__UART1_DTR IOMUX_PAD(0x6f8, 0x294, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA6__AUDMUX_AUD6_TXD IOMUX_PAD(0x6f8, 0x294, 3, 0x7b4, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA6__GPIO2_19 IOMUX_PAD(0x6f8, 0x294, 5, 0x890, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA6__IPU_DIAGB_13 IOMUX_PAD(0x6f8, 0x294, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DATA7__ATA_DATA_7 IOMUX_PAD(0x6fc, 0x298, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA7__CAN1_RXCAN IOMUX_PAD(0x6fc, 0x298, 1, 0x7c8, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA7__UART1_DSR IOMUX_PAD(0x6fc, 0x298, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA7__AUDMUX_AUD6_RXD IOMUX_PAD(0x6fc, 0x298, 3, 0x7b0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA7__GPIO2_20 IOMUX_PAD(0x6fc, 0x298, 5, 0x898, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA7__IPU_DIAGB_14 IOMUX_PAD(0x6fc, 0x298, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DATA8__ATA_DATA_8 IOMUX_PAD(0x700, 0x29c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA8__UART3_RTS IOMUX_PAD(0x700, 0x29c, 1, 0x99c, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA8__UART1_RI IOMUX_PAD(0x700, 0x29c, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA8__AUDMUX_AUD6_TXC IOMUX_PAD(0x700, 0x29c, 3, 0x7c0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA8__GPIO2_21 IOMUX_PAD(0x700, 0x29c, 5, 0x89c, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA8__IPU_DIAGB_15 IOMUX_PAD(0x700, 0x29c, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DATA9__ATA_DATA_9 IOMUX_PAD(0x704, 0x2a0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA9__UART3_CTS IOMUX_PAD(0x704, 0x2a0, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA9__UART1_DCD IOMUX_PAD(0x704, 0x2a0, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA9__AUDMUX_AUD6_TXFS IOMUX_PAD(0x704, 0x2a0, 3, 0x7c4, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA9__GPIO2_22 IOMUX_PAD(0x704, 0x2a0, 5, 0x8a0, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA9__IPU_DIAGB_16 IOMUX_PAD(0x704, 0x2a0, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DATA10__ATA_DATA_10 IOMUX_PAD(0x708, 0x2a4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA10__UART3_RXD_MUX IOMUX_PAD(0x708, 0x2a4, 1, 0x9a0, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA10__AUDMUX_AUD6_RXC IOMUX_PAD(0x708, 0x2a4, 3, 0x7b8, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA10__GPIO2_23 IOMUX_PAD(0x708, 0x2a4, 5, 0x8a4, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA10__IPU_DIAGB_17 IOMUX_PAD(0x708, 0x2a4, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DATA11__ATA_DATA_11 IOMUX_PAD(0x70c, 0x2a8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA11__UART3_TXD_MUX IOMUX_PAD(0x70c, 0x2a8, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA11__AUDMUX_AUD6_RXFS IOMUX_PAD(0x70c, 0x2a8, 3, 0x7bc, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA11__GPIO2_24 IOMUX_PAD(0x70c, 0x2a8, 5, 0x8a8, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA11__IPU_DIAGB_18 IOMUX_PAD(0x70c, 0x2a8, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DATA12__ATA_DATA_12 IOMUX_PAD(0x710, 0x2ac, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA12__I2C3_SCL IOMUX_PAD(0x710, 0x2ac, 1, 0x91c, 3, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA12__GPIO2_25 IOMUX_PAD(0x710, 0x2ac, 5, 0x8ac, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA12__IPU_DIAGB_19 IOMUX_PAD(0x710, 0x2ac, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DATA13__ATA_DATA_13 IOMUX_PAD(0x714, 0x2b0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA13__I2C3_SDA IOMUX_PAD(0x714, 0x2b0, 1, 0x920, 3, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA13__GPIO2_26 IOMUX_PAD(0x714, 0x2b0, 5, 0x8b0, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA13__IPU_DIAGB_20 IOMUX_PAD(0x714, 0x2b0, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DATA14__ATA_DATA_14 IOMUX_PAD(0x718, 0x2b4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA14__IPU_CSI_D_0 IOMUX_PAD(0x718, 0x2b4, 1, 0x930, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA14__KPP_ROW_0 IOMUX_PAD(0x718, 0x2b4, 3, 0x970, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA14__GPIO2_27 IOMUX_PAD(0x718, 0x2b4, 5, 0x8b4, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA14__IPU_DIAGB_21 IOMUX_PAD(0x718, 0x2b4, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DATA15__ATA_DATA_15 IOMUX_PAD(0x71c, 0x2b8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA15__IPU_CSI_D_1 IOMUX_PAD(0x71c, 0x2b8, 1, 0x934, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA15__KPP_ROW_1 IOMUX_PAD(0x71c, 0x2b8, 3, 0x974, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA15__GPIO2_28 IOMUX_PAD(0x71c, 0x2b8, 5, 0x8b8, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DATA15__IPU_DIAGB_22 IOMUX_PAD(0x71c, 0x2b8, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_INTRQ__ATA_INTRQ IOMUX_PAD(0x720, 0x2bc, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_INTRQ__IPU_CSI_D_2 IOMUX_PAD(0x720, 0x2bc, 1, 0x938, 3, NO_PAD_CTRL) -#define MX35_PAD_ATA_INTRQ__KPP_ROW_2 IOMUX_PAD(0x720, 0x2bc, 3, 0x978, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_INTRQ__GPIO2_29 IOMUX_PAD(0x720, 0x2bc, 5, 0x8bc, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_INTRQ__IPU_DIAGB_23 IOMUX_PAD(0x720, 0x2bc, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_BUFF_EN__ATA_BUFFER_EN IOMUX_PAD(0x724, 0x2c0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_BUFF_EN__IPU_CSI_D_3 IOMUX_PAD(0x724, 0x2c0, 1, 0x93c, 3, NO_PAD_CTRL) -#define MX35_PAD_ATA_BUFF_EN__KPP_ROW_3 IOMUX_PAD(0x724, 0x2c0, 3, 0x97c, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_BUFF_EN__GPIO2_30 IOMUX_PAD(0x724, 0x2c0, 5, 0x8c4, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_BUFF_EN__IPU_DIAGB_24 IOMUX_PAD(0x724, 0x2c0, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DMARQ__ATA_DMARQ IOMUX_PAD(0x728, 0x2c4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DMARQ__IPU_CSI_D_4 IOMUX_PAD(0x728, 0x2c4, 1, 0x940, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_DMARQ__KPP_COL_0 IOMUX_PAD(0x728, 0x2c4, 3, 0x950, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_DMARQ__GPIO2_31 IOMUX_PAD(0x728, 0x2c4, 5, 0x8c8, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DMARQ__IPU_DIAGB_25 IOMUX_PAD(0x728, 0x2c4, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DMARQ__ECT_CTI_TRIG_IN1_4 IOMUX_PAD(0x728, 0x2c4, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DA0__ATA_DA_0 IOMUX_PAD(0x72c, 0x2c8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DA0__IPU_CSI_D_5 IOMUX_PAD(0x72c, 0x2c8, 1, 0x944, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_DA0__KPP_COL_1 IOMUX_PAD(0x72c, 0x2c8, 3, 0x954, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_DA0__GPIO3_0 IOMUX_PAD(0x72c, 0x2c8, 5, 0x8e8, 1, NO_PAD_CTRL) -#define MX35_PAD_ATA_DA0__IPU_DIAGB_26 IOMUX_PAD(0x72c, 0x2c8, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DA0__ECT_CTI_TRIG_IN1_5 IOMUX_PAD(0x72c, 0x2c8, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DA1__ATA_DA_1 IOMUX_PAD(0x730, 0x2cc, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DA1__IPU_CSI_D_6 IOMUX_PAD(0x730, 0x2cc, 1, 0x948, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_DA1__KPP_COL_2 IOMUX_PAD(0x730, 0x2cc, 3, 0x958, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_DA1__GPIO3_1 IOMUX_PAD(0x730, 0x2cc, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DA1__IPU_DIAGB_27 IOMUX_PAD(0x730, 0x2cc, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DA1__ECT_CTI_TRIG_IN1_6 IOMUX_PAD(0x730, 0x2cc, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_ATA_DA2__ATA_DA_2 IOMUX_PAD(0x734, 0x2d0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DA2__IPU_CSI_D_7 IOMUX_PAD(0x734, 0x2d0, 1, 0x94c, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_DA2__KPP_COL_3 IOMUX_PAD(0x734, 0x2d0, 3, 0x95c, 2, NO_PAD_CTRL) -#define MX35_PAD_ATA_DA2__GPIO3_2 IOMUX_PAD(0x734, 0x2d0, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DA2__IPU_DIAGB_28 IOMUX_PAD(0x734, 0x2d0, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_ATA_DA2__ECT_CTI_TRIG_IN1_7 IOMUX_PAD(0x734, 0x2d0, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_MLB_CLK__MLB_MLBCLK IOMUX_PAD(0x738, 0x2d4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_MLB_CLK__GPIO3_3 IOMUX_PAD(0x738, 0x2d4, 5, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_MLB_DAT__MLB_MLBDAT IOMUX_PAD(0x73c, 0x2d8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_MLB_DAT__GPIO3_4 IOMUX_PAD(0x73c, 0x2d8, 5, 0x904, 1, NO_PAD_CTRL) - -#define MX35_PAD_MLB_SIG__MLB_MLBSIG IOMUX_PAD(0x740, 0x2dc, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_MLB_SIG__GPIO3_5 IOMUX_PAD(0x740, 0x2dc, 5, 0x908, 1, NO_PAD_CTRL) - -#define MX35_PAD_FEC_TX_CLK__FEC_TX_CLK IOMUX_PAD(0x744, 0x2e0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_CLK__ESDHC1_DAT4 IOMUX_PAD(0x744, 0x2e0, 1, 0x804, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_CLK__UART3_RXD_MUX IOMUX_PAD(0x744, 0x2e0, 2, 0x9a0, 3, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_CLK__USB_TOP_USBH2_DIR IOMUX_PAD(0x744, 0x2e0, 3, 0x9ec, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_CLK__CSPI2_MOSI IOMUX_PAD(0x744, 0x2e0, 4, 0x7ec, 3, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_CLK__GPIO3_6 IOMUX_PAD(0x744, 0x2e0, 5, 0x90c, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_CLK__IPU_DISPB_D12_VSYNC IOMUX_PAD(0x744, 0x2e0, 6, 0x928, 5, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_CLK__ARM11P_TOP_EVNTBUS_0 IOMUX_PAD(0x744, 0x2e0, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_FEC_RX_CLK__FEC_RX_CLK IOMUX_PAD(0x748, 0x2e4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_CLK__ESDHC1_DAT5 IOMUX_PAD(0x748, 0x2e4, 1, 0x808, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_CLK__UART3_TXD_MUX IOMUX_PAD(0x748, 0x2e4, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_CLK__USB_TOP_USBH2_STP IOMUX_PAD(0x748, 0x2e4, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_CLK__CSPI2_MISO IOMUX_PAD(0x748, 0x2e4, 4, 0x7e8, 3, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_CLK__GPIO3_7 IOMUX_PAD(0x748, 0x2e4, 5, 0x910, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_CLK__IPU_DISPB_SD_D_I IOMUX_PAD(0x748, 0x2e4, 6, 0x92c, 4, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_CLK__ARM11P_TOP_EVNTBUS_1 IOMUX_PAD(0x748, 0x2e4, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_FEC_RX_DV__FEC_RX_DV IOMUX_PAD(0x74c, 0x2e8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_DV__ESDHC1_DAT6 IOMUX_PAD(0x74c, 0x2e8, 1, 0x80c, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_DV__UART3_RTS IOMUX_PAD(0x74c, 0x2e8, 2, 0x99c, 2, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_DV__USB_TOP_USBH2_NXT IOMUX_PAD(0x74c, 0x2e8, 3, 0x9f0, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_DV__CSPI2_SCLK IOMUX_PAD(0x74c, 0x2e8, 4, 0x7e0, 3, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_DV__GPIO3_8 IOMUX_PAD(0x74c, 0x2e8, 5, 0x914, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_DV__IPU_DISPB_SD_CLK IOMUX_PAD(0x74c, 0x2e8, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_DV__ARM11P_TOP_EVNTBUS_2 IOMUX_PAD(0x74c, 0x2e8, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_FEC_COL__FEC_COL IOMUX_PAD(0x750, 0x2ec, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_COL__ESDHC1_DAT7 IOMUX_PAD(0x750, 0x2ec, 1, 0x810, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_COL__UART3_CTS IOMUX_PAD(0x750, 0x2ec, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_COL__USB_TOP_USBH2_DATA_0 IOMUX_PAD(0x750, 0x2ec, 3, 0x9cc, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_COL__CSPI2_RDY IOMUX_PAD(0x750, 0x2ec, 4, 0x7e4, 3, NO_PAD_CTRL) -#define MX35_PAD_FEC_COL__GPIO3_9 IOMUX_PAD(0x750, 0x2ec, 5, 0x918, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_COL__IPU_DISPB_SER_RS IOMUX_PAD(0x750, 0x2ec, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_COL__ARM11P_TOP_EVNTBUS_3 IOMUX_PAD(0x750, 0x2ec, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_FEC_RDATA0__FEC_RDATA_0 IOMUX_PAD(0x754, 0x2f0, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA0__PWM_PWMO IOMUX_PAD(0x754, 0x2f0, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA0__UART3_DTR IOMUX_PAD(0x754, 0x2f0, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA0__USB_TOP_USBH2_DATA_1 IOMUX_PAD(0x754, 0x2f0, 3, 0x9d0, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA0__CSPI2_SS0 IOMUX_PAD(0x754, 0x2f0, 4, 0x7f0, 2, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA0__GPIO3_10 IOMUX_PAD(0x754, 0x2f0, 5, 0x8ec, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA0__IPU_DISPB_CS1 IOMUX_PAD(0x754, 0x2f0, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA0__ARM11P_TOP_EVNTBUS_4 IOMUX_PAD(0x754, 0x2f0, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_FEC_TDATA0__FEC_TDATA_0 IOMUX_PAD(0x758, 0x2f4, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA0__SPDIF_SPDIF_OUT1 IOMUX_PAD(0x758, 0x2f4, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA0__UART3_DSR IOMUX_PAD(0x758, 0x2f4, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA0__USB_TOP_USBH2_DATA_2 IOMUX_PAD(0x758, 0x2f4, 3, 0x9d4, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA0__CSPI2_SS1 IOMUX_PAD(0x758, 0x2f4, 4, 0x7f4, 2, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA0__GPIO3_11 IOMUX_PAD(0x758, 0x2f4, 5, 0x8f0, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA0__IPU_DISPB_CS0 IOMUX_PAD(0x758, 0x2f4, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA0__ARM11P_TOP_EVNTBUS_5 IOMUX_PAD(0x758, 0x2f4, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_FEC_TX_EN__FEC_TX_EN IOMUX_PAD(0x75c, 0x2f8, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_EN__SPDIF_SPDIF_IN1 IOMUX_PAD(0x75c, 0x2f8, 1, 0x998, 3, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_EN__UART3_RI IOMUX_PAD(0x75c, 0x2f8, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_EN__USB_TOP_USBH2_DATA_3 IOMUX_PAD(0x75c, 0x2f8, 3, 0x9d8, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_EN__GPIO3_12 IOMUX_PAD(0x75c, 0x2f8, 5, 0x8f4, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_EN__IPU_DISPB_PAR_RS IOMUX_PAD(0x75c, 0x2f8, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_EN__ARM11P_TOP_EVNTBUS_6 IOMUX_PAD(0x75c, 0x2f8, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_FEC_MDC__FEC_MDC IOMUX_PAD(0x760, 0x2fc, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_MDC__CAN2_TXCAN IOMUX_PAD(0x760, 0x2fc, 1, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_MDC__UART3_DCD IOMUX_PAD(0x760, 0x2fc, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_MDC__USB_TOP_USBH2_DATA_4 IOMUX_PAD(0x760, 0x2fc, 3, 0x9dc, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_MDC__GPIO3_13 IOMUX_PAD(0x760, 0x2fc, 5, 0x8f8, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_MDC__IPU_DISPB_WR IOMUX_PAD(0x760, 0x2fc, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_MDC__ARM11P_TOP_EVNTBUS_7 IOMUX_PAD(0x760, 0x2fc, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_FEC_MDIO__FEC_MDIO IOMUX_PAD(0x764, 0x300, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_MDIO__CAN2_RXCAN IOMUX_PAD(0x764, 0x300, 1, 0x7cc, 2, NO_PAD_CTRL) -#define MX35_PAD_FEC_MDIO__USB_TOP_USBH2_DATA_5 IOMUX_PAD(0x764, 0x300, 3, 0x9e0, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_MDIO__GPIO3_14 IOMUX_PAD(0x764, 0x300, 5, 0x8fc, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_MDIO__IPU_DISPB_RD IOMUX_PAD(0x764, 0x300, 6, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_MDIO__ARM11P_TOP_EVNTBUS_8 IOMUX_PAD(0x764, 0x300, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_FEC_TX_ERR__FEC_TX_ERR IOMUX_PAD(0x768, 0x304, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_ERR__OWIRE_LINE IOMUX_PAD(0x768, 0x304, 1, 0x990, 2, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_ERR__SPDIF_SPDIF_EXTCLK IOMUX_PAD(0x768, 0x304, 2, 0x994, 4, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_ERR__USB_TOP_USBH2_DATA_6 IOMUX_PAD(0x768, 0x304, 3, 0x9e4, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_ERR__GPIO3_15 IOMUX_PAD(0x768, 0x304, 5, 0x900, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_ERR__IPU_DISPB_D0_VSYNC IOMUX_PAD(0x768, 0x304, 6, 0x924, 3, NO_PAD_CTRL) -#define MX35_PAD_FEC_TX_ERR__ARM11P_TOP_EVNTBUS_9 IOMUX_PAD(0x768, 0x304, 7, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_FEC_RX_ERR__FEC_RX_ERR IOMUX_PAD(0x76c, 0x308, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_ERR__IPU_CSI_D_0 IOMUX_PAD(0x76c, 0x308, 1, 0x930, 3, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_ERR__USB_TOP_USBH2_DATA_7 IOMUX_PAD(0x76c, 0x308, 3, 0x9e8, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_ERR__KPP_COL_4 IOMUX_PAD(0x76c, 0x308, 4, 0x960, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_ERR__GPIO3_16 IOMUX_PAD(0x76c, 0x308, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_RX_ERR__IPU_DISPB_SD_D_IO IOMUX_PAD(0x76c, 0x308, 6, 0x92c, 5, NO_PAD_CTRL) - -#define MX35_PAD_FEC_CRS__FEC_CRS IOMUX_PAD(0x770, 0x30c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_CRS__IPU_CSI_D_1 IOMUX_PAD(0x770, 0x30c, 1, 0x934, 3, NO_PAD_CTRL) -#define MX35_PAD_FEC_CRS__USB_TOP_USBH2_PWR IOMUX_PAD(0x770, 0x30c, 3, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_CRS__KPP_COL_5 IOMUX_PAD(0x770, 0x30c, 4, 0x964, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_CRS__GPIO3_17 IOMUX_PAD(0x770, 0x30c, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_CRS__IPU_FLASH_STROBE IOMUX_PAD(0x770, 0x30c, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_FEC_RDATA1__FEC_RDATA_1 IOMUX_PAD(0x774, 0x310, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA1__IPU_CSI_D_2 IOMUX_PAD(0x774, 0x310, 1, 0x938, 4, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA1__AUDMUX_AUD6_RXC IOMUX_PAD(0x774, 0x310, 2, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA1__USB_TOP_USBH2_OC IOMUX_PAD(0x774, 0x310, 3, 0x9f4, 2, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA1__KPP_COL_6 IOMUX_PAD(0x774, 0x310, 4, 0x968, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA1__GPIO3_18 IOMUX_PAD(0x774, 0x310, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA1__IPU_DISPB_BE0 IOMUX_PAD(0x774, 0x310, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_FEC_TDATA1__FEC_TDATA_1 IOMUX_PAD(0x778, 0x314, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA1__IPU_CSI_D_3 IOMUX_PAD(0x778, 0x314, 1, 0x93c, 4, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA1__AUDMUX_AUD6_RXFS IOMUX_PAD(0x778, 0x314, 2, 0x7bc, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA1__KPP_COL_7 IOMUX_PAD(0x778, 0x314, 4, 0x96c, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA1__GPIO3_19 IOMUX_PAD(0x778, 0x314, 5, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA1__IPU_DISPB_BE1 IOMUX_PAD(0x778, 0x314, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_FEC_RDATA2__FEC_RDATA_2 IOMUX_PAD(0x77c, 0x318, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA2__IPU_CSI_D_4 IOMUX_PAD(0x77c, 0x318, 1, 0x940, 3, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA2__AUDMUX_AUD6_TXD IOMUX_PAD(0x77c, 0x318, 2, 0x7b4, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA2__KPP_ROW_4 IOMUX_PAD(0x77c, 0x318, 4, 0x980, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA2__GPIO3_20 IOMUX_PAD(0x77c, 0x318, 5, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_FEC_TDATA2__FEC_TDATA_2 IOMUX_PAD(0x780, 0x31c, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA2__IPU_CSI_D_5 IOMUX_PAD(0x780, 0x31c, 1, 0x944, 3, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA2__AUDMUX_AUD6_RXD IOMUX_PAD(0x780, 0x31c, 2, 0x7b0, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA2__KPP_ROW_5 IOMUX_PAD(0x780, 0x31c, 4, 0x984, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA2__GPIO3_21 IOMUX_PAD(0x780, 0x31c, 5, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_FEC_RDATA3__FEC_RDATA_3 IOMUX_PAD(0x784, 0x320, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA3__IPU_CSI_D_6 IOMUX_PAD(0x784, 0x320, 1, 0x948, 3, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA3__AUDMUX_AUD6_TXC IOMUX_PAD(0x784, 0x320, 2, 0x7c0, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA3__KPP_ROW_6 IOMUX_PAD(0x784, 0x320, 4, 0x988, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_RDATA3__GPIO3_22 IOMUX_PAD(0x784, 0x320, 6, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_FEC_TDATA3__FEC_TDATA_3 IOMUX_PAD(0x788, 0x324, 0, 0x0, 0, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA3__IPU_CSI_D_7 IOMUX_PAD(0x788, 0x324, 1, 0x94c, 3, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA3__AUDMUX_AUD6_TXFS IOMUX_PAD(0x788, 0x324, 2, 0x7c4, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA3__KPP_ROW_7 IOMUX_PAD(0x788, 0x324, 4, 0x98c, 1, NO_PAD_CTRL) -#define MX35_PAD_FEC_TDATA3__GPIO3_23 IOMUX_PAD(0x788, 0x324, 5, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_EXT_ARMCLK__CCM_EXT_ARMCLK IOMUX_PAD(0x78c, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - -#define MX35_PAD_TEST_MODE__TCU_TEST_MODE IOMUX_PAD(0x790, 0x0, 0, 0x0, 0, NO_PAD_CTRL) - - -#endif /* __MACH_IOMUX_MX35_H__ */ diff --git a/arch/arm/mach-imx/iomux-v1.c b/arch/arm/mach-imx/iomux-v1.c deleted file mode 100644 index a4bec3b9b2b3..000000000000 --- a/arch/arm/mach-imx/iomux-v1.c +++ /dev/null @@ -1,174 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * arch/arm/plat-mxc/iomux-v1.c - * - * Copyright (C) 2004 Sascha Hauer, Synertronixx GmbH - * Copyright (C) 2009 Uwe Kleine-Koenig, Pengutronix - * - * Common code for i.MX1, i.MX21 and i.MX27 - */ - -#include <linux/errno.h> -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/module.h> -#include <linux/string.h> -#include <linux/gpio.h> - -#include <asm/mach/map.h> - -#include "hardware.h" -#include "iomux-v1.h" - -static void __iomem *imx_iomuxv1_baseaddr; -static unsigned imx_iomuxv1_numports; - -static inline unsigned long imx_iomuxv1_readl(unsigned offset) -{ - return imx_readl(imx_iomuxv1_baseaddr + offset); -} - -static inline void imx_iomuxv1_writel(unsigned long val, unsigned offset) -{ - imx_writel(val, imx_iomuxv1_baseaddr + offset); -} - -static inline void imx_iomuxv1_rmwl(unsigned offset, - unsigned long mask, unsigned long value) -{ - unsigned long reg = imx_iomuxv1_readl(offset); - - reg &= ~mask; - reg |= value; - - imx_iomuxv1_writel(reg, offset); -} - -static inline void imx_iomuxv1_set_puen( - unsigned int port, unsigned int pin, int on) -{ - unsigned long mask = 1 << pin; - - imx_iomuxv1_rmwl(MXC_PUEN(port), mask, on ? mask : 0); -} - -static inline void imx_iomuxv1_set_ddir( - unsigned int port, unsigned int pin, int out) -{ - unsigned long mask = 1 << pin; - - imx_iomuxv1_rmwl(MXC_DDIR(port), mask, out ? mask : 0); -} - -static inline void imx_iomuxv1_set_gpr( - unsigned int port, unsigned int pin, int af) -{ - unsigned long mask = 1 << pin; - - imx_iomuxv1_rmwl(MXC_GPR(port), mask, af ? mask : 0); -} - -static inline void imx_iomuxv1_set_gius( - unsigned int port, unsigned int pin, int inuse) -{ - unsigned long mask = 1 << pin; - - imx_iomuxv1_rmwl(MXC_GIUS(port), mask, inuse ? mask : 0); -} - -static inline void imx_iomuxv1_set_ocr( - unsigned int port, unsigned int pin, unsigned int ocr) -{ - unsigned long shift = (pin & 0xf) << 1; - unsigned long mask = 3 << shift; - unsigned long value = ocr << shift; - unsigned long offset = pin < 16 ? MXC_OCR1(port) : MXC_OCR2(port); - - imx_iomuxv1_rmwl(offset, mask, value); -} - -static inline void imx_iomuxv1_set_iconfa( - unsigned int port, unsigned int pin, unsigned int aout) -{ - unsigned long shift = (pin & 0xf) << 1; - unsigned long mask = 3 << shift; - unsigned long value = aout << shift; - unsigned long offset = pin < 16 ? MXC_ICONFA1(port) : MXC_ICONFA2(port); - - imx_iomuxv1_rmwl(offset, mask, value); -} - -static inline void imx_iomuxv1_set_iconfb( - unsigned int port, unsigned int pin, unsigned int bout) -{ - unsigned long shift = (pin & 0xf) << 1; - unsigned long mask = 3 << shift; - unsigned long value = bout << shift; - unsigned long offset = pin < 16 ? MXC_ICONFB1(port) : MXC_ICONFB2(port); - - imx_iomuxv1_rmwl(offset, mask, value); -} - -int mxc_gpio_mode(int gpio_mode) -{ - unsigned int pin = gpio_mode & GPIO_PIN_MASK; - unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> GPIO_OCR_SHIFT; - unsigned int aout = (gpio_mode >> GPIO_AOUT_SHIFT) & 3; - unsigned int bout = (gpio_mode >> GPIO_BOUT_SHIFT) & 3; - - if (port >= imx_iomuxv1_numports) - return -EINVAL; - - /* Pullup enable */ - imx_iomuxv1_set_puen(port, pin, gpio_mode & GPIO_PUEN); - - /* Data direction */ - imx_iomuxv1_set_ddir(port, pin, gpio_mode & GPIO_OUT); - - /* Primary / alternate function */ - imx_iomuxv1_set_gpr(port, pin, gpio_mode & GPIO_AF); - - /* use as gpio? */ - imx_iomuxv1_set_gius(port, pin, !(gpio_mode & (GPIO_PF | GPIO_AF))); - - imx_iomuxv1_set_ocr(port, pin, ocr); - - imx_iomuxv1_set_iconfa(port, pin, aout); - - imx_iomuxv1_set_iconfb(port, pin, bout); - - return 0; -} - -static int imx_iomuxv1_setup_multiple(const int *list, unsigned count) -{ - size_t i; - int ret = 0; - - for (i = 0; i < count; ++i) { - ret = mxc_gpio_mode(list[i]); - - if (ret) - return ret; - } - - return ret; -} - -int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count, - const char *label) -{ - int ret; - - ret = imx_iomuxv1_setup_multiple(pin_list, count); - return ret; -} - -int __init imx_iomuxv1_init(void __iomem *base, int numports) -{ - imx_iomuxv1_baseaddr = base; - imx_iomuxv1_numports = numports; - - return 0; -} diff --git a/arch/arm/mach-imx/iomux-v1.h b/arch/arm/mach-imx/iomux-v1.h deleted file mode 100644 index b94852970c7f..000000000000 --- a/arch/arm/mach-imx/iomux-v1.h +++ /dev/null @@ -1,81 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> - * Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de> - */ -#ifndef __MACH_IOMUX_V1_H__ -#define __MACH_IOMUX_V1_H__ - -/* -* GPIO Module and I/O Multiplexer -* x = 0..3 for reg_A, reg_B, reg_C, reg_D -*/ -#define MXC_DDIR(x) (0x00 + ((x) << 8)) -#define MXC_OCR1(x) (0x04 + ((x) << 8)) -#define MXC_OCR2(x) (0x08 + ((x) << 8)) -#define MXC_ICONFA1(x) (0x0c + ((x) << 8)) -#define MXC_ICONFA2(x) (0x10 + ((x) << 8)) -#define MXC_ICONFB1(x) (0x14 + ((x) << 8)) -#define MXC_ICONFB2(x) (0x18 + ((x) << 8)) -#define MXC_DR(x) (0x1c + ((x) << 8)) -#define MXC_GIUS(x) (0x20 + ((x) << 8)) -#define MXC_SSR(x) (0x24 + ((x) << 8)) -#define MXC_ICR1(x) (0x28 + ((x) << 8)) -#define MXC_ICR2(x) (0x2c + ((x) << 8)) -#define MXC_IMR(x) (0x30 + ((x) << 8)) -#define MXC_ISR(x) (0x34 + ((x) << 8)) -#define MXC_GPR(x) (0x38 + ((x) << 8)) -#define MXC_SWR(x) (0x3c + ((x) << 8)) -#define MXC_PUEN(x) (0x40 + ((x) << 8)) - -#define MX1_NUM_GPIO_PORT 4 -#define MX21_NUM_GPIO_PORT 6 -#define MX27_NUM_GPIO_PORT 6 - -#define GPIO_PIN_MASK 0x1f - -#define GPIO_PORT_SHIFT 5 -#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT) - -#define GPIO_PORTA (0 << GPIO_PORT_SHIFT) -#define GPIO_PORTB (1 << GPIO_PORT_SHIFT) -#define GPIO_PORTC (2 << GPIO_PORT_SHIFT) -#define GPIO_PORTD (3 << GPIO_PORT_SHIFT) -#define GPIO_PORTE (4 << GPIO_PORT_SHIFT) -#define GPIO_PORTF (5 << GPIO_PORT_SHIFT) - -#define GPIO_OUT (1 << 8) -#define GPIO_IN (0 << 8) -#define GPIO_PUEN (1 << 9) - -#define GPIO_PF (1 << 10) -#define GPIO_AF (1 << 11) - -#define GPIO_OCR_SHIFT 12 -#define GPIO_OCR_MASK (3 << GPIO_OCR_SHIFT) -#define GPIO_AIN (0 << GPIO_OCR_SHIFT) -#define GPIO_BIN (1 << GPIO_OCR_SHIFT) -#define GPIO_CIN (2 << GPIO_OCR_SHIFT) -#define GPIO_GPIO (3 << GPIO_OCR_SHIFT) - -#define GPIO_AOUT_SHIFT 14 -#define GPIO_AOUT_MASK (3 << GPIO_AOUT_SHIFT) -#define GPIO_AOUT (0 << GPIO_AOUT_SHIFT) -#define GPIO_AOUT_ISR (1 << GPIO_AOUT_SHIFT) -#define GPIO_AOUT_0 (2 << GPIO_AOUT_SHIFT) -#define GPIO_AOUT_1 (3 << GPIO_AOUT_SHIFT) - -#define GPIO_BOUT_SHIFT 16 -#define GPIO_BOUT_MASK (3 << GPIO_BOUT_SHIFT) -#define GPIO_BOUT (0 << GPIO_BOUT_SHIFT) -#define GPIO_BOUT_ISR (1 << GPIO_BOUT_SHIFT) -#define GPIO_BOUT_0 (2 << GPIO_BOUT_SHIFT) -#define GPIO_BOUT_1 (3 << GPIO_BOUT_SHIFT) - -extern int mxc_gpio_mode(int gpio_mode); -extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count, - const char *label); - -extern int imx_iomuxv1_init(void __iomem *base, int numports); - -#endif /* __MACH_IOMUX_V1_H__ */ diff --git a/arch/arm/mach-imx/iomux-v3.c b/arch/arm/mach-imx/iomux-v3.c deleted file mode 100644 index 043cf3c7cacf..000000000000 --- a/arch/arm/mach-imx/iomux-v3.c +++ /dev/null @@ -1,65 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> - * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH, - * <armlinux@phytec.de> - */ -#include <linux/errno.h> -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/module.h> -#include <linux/string.h> -#include <linux/gpio.h> - -#include <asm/mach/map.h> - -#include "hardware.h" -#include "iomux-v3.h" - -static void __iomem *base; - -/* - * configures a single pad in the iomuxer - */ -int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t pad) -{ - u32 mux_ctrl_ofs = (pad & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT; - u32 mux_mode = (pad & MUX_MODE_MASK) >> MUX_MODE_SHIFT; - u32 sel_input_ofs = (pad & MUX_SEL_INPUT_OFS_MASK) >> MUX_SEL_INPUT_OFS_SHIFT; - u32 sel_input = (pad & MUX_SEL_INPUT_MASK) >> MUX_SEL_INPUT_SHIFT; - u32 pad_ctrl_ofs = (pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT; - u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT; - - if (mux_ctrl_ofs) - imx_writel(mux_mode, base + mux_ctrl_ofs); - - if (sel_input_ofs) - imx_writel(sel_input, base + sel_input_ofs); - - if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs) - imx_writel(pad_ctrl, base + pad_ctrl_ofs); - - return 0; -} - -int mxc_iomux_v3_setup_multiple_pads(const iomux_v3_cfg_t *pad_list, - unsigned count) -{ - const iomux_v3_cfg_t *p = pad_list; - int i; - int ret; - - for (i = 0; i < count; i++) { - ret = mxc_iomux_v3_setup_pad(*p); - if (ret) - return ret; - p++; - } - return 0; -} - -void mxc_iomux_v3_init(void __iomem *iomux_v3_base) -{ - base = iomux_v3_base; -} diff --git a/arch/arm/mach-imx/iomux-v3.h b/arch/arm/mach-imx/iomux-v3.h deleted file mode 100644 index 7db8ec926ff1..000000000000 --- a/arch/arm/mach-imx/iomux-v3.h +++ /dev/null @@ -1,130 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH, - * <armlinux@phytec.de> - */ - -#ifndef __MACH_IOMUX_V3_H__ -#define __MACH_IOMUX_V3_H__ - -/* - * build IOMUX_PAD structure - * - * This iomux scheme is based around pads, which are the physical balls - * on the processor. - * - * - Each pad has a pad control register (IOMUXC_SW_PAD_CTRL_x) which controls - * things like driving strength and pullup/pulldown. - * - Each pad can have but not necessarily does have an output routing register - * (IOMUXC_SW_MUX_CTL_PAD_x). - * - Each pad can have but not necessarily does have an input routing register - * (IOMUXC_x_SELECT_INPUT) - * - * The three register sets do not have a fixed offset to each other, - * hence we order this table by pad control registers (which all pads - * have) and put the optional i/o routing registers into additional - * fields. - * - * The naming convention for the pad modes is MX35_PAD_<padname>__<padmode> - * If <padname> or <padmode> refers to a GPIO, it is named - * GPIO_<unit>_<num> - * - * IOMUX/PAD Bit field definitions - * - * MUX_CTRL_OFS: 0..11 (12) - * PAD_CTRL_OFS: 12..23 (12) - * SEL_INPUT_OFS: 24..35 (12) - * MUX_MODE + SION: 36..40 (5) - * PAD_CTRL + NO_PAD_CTRL: 41..57 (17) - * SEL_INP: 58..61 (4) - * reserved: 63 (1) -*/ - -typedef u64 iomux_v3_cfg_t; - -#define MUX_CTRL_OFS_SHIFT 0 -#define MUX_CTRL_OFS_MASK ((iomux_v3_cfg_t)0xfff << MUX_CTRL_OFS_SHIFT) -#define MUX_PAD_CTRL_OFS_SHIFT 12 -#define MUX_PAD_CTRL_OFS_MASK ((iomux_v3_cfg_t)0xfff << MUX_PAD_CTRL_OFS_SHIFT) -#define MUX_SEL_INPUT_OFS_SHIFT 24 -#define MUX_SEL_INPUT_OFS_MASK ((iomux_v3_cfg_t)0xfff << MUX_SEL_INPUT_OFS_SHIFT) - -#define MUX_MODE_SHIFT 36 -#define MUX_MODE_MASK ((iomux_v3_cfg_t)0x1f << MUX_MODE_SHIFT) -#define MUX_PAD_CTRL_SHIFT 41 -#define MUX_PAD_CTRL_MASK ((iomux_v3_cfg_t)0x1ffff << MUX_PAD_CTRL_SHIFT) -#define MUX_SEL_INPUT_SHIFT 58 -#define MUX_SEL_INPUT_MASK ((iomux_v3_cfg_t)0xf << MUX_SEL_INPUT_SHIFT) - -#define MUX_PAD_CTRL(x) ((iomux_v3_cfg_t)(x) << MUX_PAD_CTRL_SHIFT) - -#define IOMUX_PAD(_pad_ctrl_ofs, _mux_ctrl_ofs, _mux_mode, _sel_input_ofs, \ - _sel_input, _pad_ctrl) \ - (((iomux_v3_cfg_t)(_mux_ctrl_ofs) << MUX_CTRL_OFS_SHIFT) | \ - ((iomux_v3_cfg_t)(_mux_mode) << MUX_MODE_SHIFT) | \ - ((iomux_v3_cfg_t)(_pad_ctrl_ofs) << MUX_PAD_CTRL_OFS_SHIFT) | \ - ((iomux_v3_cfg_t)(_pad_ctrl) << MUX_PAD_CTRL_SHIFT) | \ - ((iomux_v3_cfg_t)(_sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT) | \ - ((iomux_v3_cfg_t)(_sel_input) << MUX_SEL_INPUT_SHIFT)) - -#define NEW_PAD_CTRL(cfg, pad) (((cfg) & ~MUX_PAD_CTRL_MASK) | MUX_PAD_CTRL(pad)) -/* - * Use to set PAD control - */ - -#define NO_PAD_CTRL (1 << 16) -#define PAD_CTL_DVS (1 << 13) -#define PAD_CTL_HYS (1 << 8) - -#define PAD_CTL_PKE (1 << 7) -#define PAD_CTL_PUE (1 << 6 | PAD_CTL_PKE) -#define PAD_CTL_PUS_100K_DOWN (0 << 4 | PAD_CTL_PUE) -#define PAD_CTL_PUS_47K_UP (1 << 4 | PAD_CTL_PUE) -#define PAD_CTL_PUS_100K_UP (2 << 4 | PAD_CTL_PUE) -#define PAD_CTL_PUS_22K_UP (3 << 4 | PAD_CTL_PUE) - -#define PAD_CTL_ODE (1 << 3) - -#define PAD_CTL_DSE_LOW (0 << 1) -#define PAD_CTL_DSE_MED (1 << 1) -#define PAD_CTL_DSE_HIGH (2 << 1) -#define PAD_CTL_DSE_MAX (3 << 1) - -#define PAD_CTL_SRE_FAST (1 << 0) -#define PAD_CTL_SRE_SLOW (0 << 0) - -#define IOMUX_CONFIG_SION (0x1 << 4) - -#define MX51_NUM_GPIO_PORT 4 - -#define GPIO_PIN_MASK 0x1f - -#define GPIO_PORT_SHIFT 5 -#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT) - -#define GPIO_PORTA (0 << GPIO_PORT_SHIFT) -#define GPIO_PORTB (1 << GPIO_PORT_SHIFT) -#define GPIO_PORTC (2 << GPIO_PORT_SHIFT) -#define GPIO_PORTD (3 << GPIO_PORT_SHIFT) -#define GPIO_PORTE (4 << GPIO_PORT_SHIFT) -#define GPIO_PORTF (5 << GPIO_PORT_SHIFT) - -/* - * setups a single pad in the iomuxer - */ -int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t pad); - -/* - * setups multiple pads - * convenient way to call the above function with tables - */ -int mxc_iomux_v3_setup_multiple_pads(const iomux_v3_cfg_t *pad_list, - unsigned count); - -/* - * Initialise the iomux controller - */ -void mxc_iomux_v3_init(void __iomem *iomux_v3_base); - -#endif /* __MACH_IOMUX_V3_H__*/ - diff --git a/arch/arm/mach-imx/mach-armadillo5x0.c b/arch/arm/mach-imx/mach-armadillo5x0.c deleted file mode 100644 index 4d9a56fb6989..000000000000 --- a/arch/arm/mach-imx/mach-armadillo5x0.c +++ /dev/null @@ -1,562 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * armadillo5x0.c - * - * Copyright 2009 Alberto Panizzo <maramaopercheseimorto@gmail.com> - * updates in http://alberdroid.blogspot.com/ - * - * Based on Atmark Techno, Inc. armadillo 500 BSP 2008 - * Based on mx31ads.c and pcm037.c Great Work! - */ - -#include <linux/types.h> -#include <linux/init.h> -#include <linux/clk.h> -#include <linux/platform_device.h> -#include <linux/gpio.h> -#include <linux/smsc911x.h> -#include <linux/interrupt.h> -#include <linux/irq.h> -#include <linux/mtd/physmap.h> -#include <linux/io.h> -#include <linux/input.h> -#include <linux/i2c.h> -#include <linux/usb/otg.h> -#include <linux/usb/ulpi.h> -#include <linux/delay.h> -#include <linux/regulator/machine.h> -#include <linux/regulator/fixed.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> -#include <asm/memory.h> -#include <asm/mach/map.h> - -#include "common.h" -#include "devices-imx31.h" -#include "crmregs-imx3.h" -#include "ehci.h" -#include "hardware.h" -#include "iomux-mx3.h" -#include "ulpi.h" - -static int armadillo5x0_pins[] = { - /* UART1 */ - MX31_PIN_CTS1__CTS1, - MX31_PIN_RTS1__RTS1, - MX31_PIN_TXD1__TXD1, - MX31_PIN_RXD1__RXD1, - /* UART2 */ - MX31_PIN_CTS2__CTS2, - MX31_PIN_RTS2__RTS2, - MX31_PIN_TXD2__TXD2, - MX31_PIN_RXD2__RXD2, - /* LAN9118_IRQ */ - IOMUX_MODE(MX31_PIN_GPIO1_0, IOMUX_CONFIG_GPIO), - /* SDHC1 */ - MX31_PIN_SD1_DATA3__SD1_DATA3, - MX31_PIN_SD1_DATA2__SD1_DATA2, - MX31_PIN_SD1_DATA1__SD1_DATA1, - MX31_PIN_SD1_DATA0__SD1_DATA0, - MX31_PIN_SD1_CLK__SD1_CLK, - MX31_PIN_SD1_CMD__SD1_CMD, - /* Framebuffer */ - MX31_PIN_LD0__LD0, - MX31_PIN_LD1__LD1, - MX31_PIN_LD2__LD2, - MX31_PIN_LD3__LD3, - MX31_PIN_LD4__LD4, - MX31_PIN_LD5__LD5, - MX31_PIN_LD6__LD6, - MX31_PIN_LD7__LD7, - MX31_PIN_LD8__LD8, - MX31_PIN_LD9__LD9, - MX31_PIN_LD10__LD10, - MX31_PIN_LD11__LD11, - MX31_PIN_LD12__LD12, - MX31_PIN_LD13__LD13, - MX31_PIN_LD14__LD14, - MX31_PIN_LD15__LD15, - MX31_PIN_LD16__LD16, - MX31_PIN_LD17__LD17, - MX31_PIN_VSYNC3__VSYNC3, - MX31_PIN_HSYNC__HSYNC, - MX31_PIN_FPSHIFT__FPSHIFT, - MX31_PIN_DRDY0__DRDY0, - IOMUX_MODE(MX31_PIN_LCS1, IOMUX_CONFIG_GPIO), /*ADV7125_PSAVE*/ - /* I2C2 */ - MX31_PIN_CSPI2_MOSI__SCL, - MX31_PIN_CSPI2_MISO__SDA, - /* OTG */ - MX31_PIN_USBOTG_DATA0__USBOTG_DATA0, - MX31_PIN_USBOTG_DATA1__USBOTG_DATA1, - MX31_PIN_USBOTG_DATA2__USBOTG_DATA2, - MX31_PIN_USBOTG_DATA3__USBOTG_DATA3, - MX31_PIN_USBOTG_DATA4__USBOTG_DATA4, - MX31_PIN_USBOTG_DATA5__USBOTG_DATA5, - MX31_PIN_USBOTG_DATA6__USBOTG_DATA6, - MX31_PIN_USBOTG_DATA7__USBOTG_DATA7, - MX31_PIN_USBOTG_CLK__USBOTG_CLK, - MX31_PIN_USBOTG_DIR__USBOTG_DIR, - MX31_PIN_USBOTG_NXT__USBOTG_NXT, - MX31_PIN_USBOTG_STP__USBOTG_STP, - /* USB host 2 */ - IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC), -}; - -/* USB */ - -#define OTG_RESET IOMUX_TO_GPIO(MX31_PIN_STXD4) -#define USBH2_RESET IOMUX_TO_GPIO(MX31_PIN_SCK6) -#define USBH2_CS IOMUX_TO_GPIO(MX31_PIN_GPIO1_3) - -#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ - PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) - -static int usbotg_init(struct platform_device *pdev) -{ - int err; - - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG); - - /* Chip already enabled by hardware */ - /* OTG phy reset*/ - err = gpio_request(OTG_RESET, "USB-OTG-RESET"); - if (err) { - pr_err("Failed to request the usb otg reset gpio\n"); - return err; - } - - err = gpio_direction_output(OTG_RESET, 1/*HIGH*/); - if (err) { - pr_err("Failed to reset the usb otg phy\n"); - goto otg_free_reset; - } - - gpio_set_value(OTG_RESET, 0/*LOW*/); - mdelay(5); - gpio_set_value(OTG_RESET, 1/*HIGH*/); - mdelay(10); - - return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED | - MXC_EHCI_INTERFACE_DIFF_UNI); - -otg_free_reset: - gpio_free(OTG_RESET); - return err; -} - -static int usbh2_init(struct platform_device *pdev) -{ - int err; - - mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG); - - mxc_iomux_set_gpr(MUX_PGP_UH2, true); - - - /* Enable the chip */ - err = gpio_request(USBH2_CS, "USB-H2-CS"); - if (err) { - pr_err("Failed to request the usb host 2 CS gpio\n"); - return err; - } - - err = gpio_direction_output(USBH2_CS, 0/*Enabled*/); - if (err) { - pr_err("Failed to drive the usb host 2 CS gpio\n"); - goto h2_free_cs; - } - - /* H2 phy reset*/ - err = gpio_request(USBH2_RESET, "USB-H2-RESET"); - if (err) { - pr_err("Failed to request the usb host 2 reset gpio\n"); - goto h2_free_cs; - } - - err = gpio_direction_output(USBH2_RESET, 1/*HIGH*/); - if (err) { - pr_err("Failed to reset the usb host 2 phy\n"); - goto h2_free_reset; - } - - gpio_set_value(USBH2_RESET, 0/*LOW*/); - mdelay(5); - gpio_set_value(USBH2_RESET, 1/*HIGH*/); - mdelay(10); - - return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED | - MXC_EHCI_INTERFACE_DIFF_UNI); - -h2_free_reset: - gpio_free(USBH2_RESET); -h2_free_cs: - gpio_free(USBH2_CS); - return err; -} - -static struct mxc_usbh_platform_data usbotg_pdata __initdata = { - .init = usbotg_init, - .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, -}; - -static struct mxc_usbh_platform_data usbh2_pdata __initdata = { - .init = usbh2_init, - .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, -}; - -/* RTC over I2C*/ -#define ARMADILLO5X0_RTC_GPIO IOMUX_TO_GPIO(MX31_PIN_SRXD4) - -static struct i2c_board_info armadillo5x0_i2c_rtc = { - I2C_BOARD_INFO("s35390a", 0x30), -}; - -/* GPIO BUTTONS */ -static struct gpio_keys_button armadillo5x0_buttons[] = { - { - .code = KEY_ENTER, /*28*/ - .gpio = IOMUX_TO_GPIO(MX31_PIN_SCLK0), - .active_low = 1, - .desc = "menu", - .wakeup = 1, - }, { - .code = KEY_BACK, /*158*/ - .gpio = IOMUX_TO_GPIO(MX31_PIN_SRST0), - .active_low = 1, - .desc = "back", - .wakeup = 1, - } -}; - -static const struct gpio_keys_platform_data - armadillo5x0_button_data __initconst = { - .buttons = armadillo5x0_buttons, - .nbuttons = ARRAY_SIZE(armadillo5x0_buttons), -}; - -/* - * NAND Flash - */ -static const struct mxc_nand_platform_data -armadillo5x0_nand_board_info __initconst = { - .width = 1, - .hw_ecc = 1, -}; - -/* - * MTD NOR Flash - */ -static struct mtd_partition armadillo5x0_nor_flash_partitions[] = { - { - .name = "nor.bootloader", - .offset = 0x00000000, - .size = 4*32*1024, - }, { - .name = "nor.kernel", - .offset = MTDPART_OFS_APPEND, - .size = 16*128*1024, - }, { - .name = "nor.userland", - .offset = MTDPART_OFS_APPEND, - .size = 110*128*1024, - }, { - .name = "nor.config", - .offset = MTDPART_OFS_APPEND, - .size = 1*128*1024, - }, -}; - -static const struct physmap_flash_data - armadillo5x0_nor_flash_pdata __initconst = { - .width = 2, - .parts = armadillo5x0_nor_flash_partitions, - .nr_parts = ARRAY_SIZE(armadillo5x0_nor_flash_partitions), -}; - -static const struct resource armadillo5x0_nor_flash_resource __initconst = { - .flags = IORESOURCE_MEM, - .start = MX31_CS0_BASE_ADDR, - .end = MX31_CS0_BASE_ADDR + SZ_64M - 1, -}; - -/* - * FB support - */ -static const struct fb_videomode fb_modedb[] = { - { /* 640x480 @ 60 Hz */ - .name = "CRT-VGA", - .refresh = 60, - .xres = 640, - .yres = 480, - .pixclock = 39721, - .left_margin = 35, - .right_margin = 115, - .upper_margin = 43, - .lower_margin = 1, - .hsync_len = 10, - .vsync_len = 1, - .sync = FB_SYNC_OE_ACT_HIGH, - .vmode = FB_VMODE_NONINTERLACED, - .flag = 0, - }, {/* 800x600 @ 56 Hz */ - .name = "CRT-SVGA", - .refresh = 56, - .xres = 800, - .yres = 600, - .pixclock = 30000, - .left_margin = 30, - .right_margin = 108, - .upper_margin = 13, - .lower_margin = 10, - .hsync_len = 10, - .vsync_len = 1, - .sync = FB_SYNC_OE_ACT_HIGH | FB_SYNC_HOR_HIGH_ACT | - FB_SYNC_VERT_HIGH_ACT, - .vmode = FB_VMODE_NONINTERLACED, - .flag = 0, - }, -}; - -static struct mx3fb_platform_data mx3fb_pdata __initdata = { - .name = "CRT-VGA", - .mode = fb_modedb, - .num_modes = ARRAY_SIZE(fb_modedb), -}; - -/* - * SDHC 1 - * MMC support - */ -static int armadillo5x0_sdhc1_get_ro(struct device *dev) -{ - return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_ATA_RESET_B)); -} - -static int armadillo5x0_sdhc1_init(struct device *dev, - irq_handler_t detect_irq, void *data) -{ - int ret; - int gpio_det, gpio_wp; - - gpio_det = IOMUX_TO_GPIO(MX31_PIN_ATA_DMACK); - gpio_wp = IOMUX_TO_GPIO(MX31_PIN_ATA_RESET_B); - - ret = gpio_request(gpio_det, "sdhc-card-detect"); - if (ret) - return ret; - - gpio_direction_input(gpio_det); - - ret = gpio_request(gpio_wp, "sdhc-write-protect"); - if (ret) - goto err_gpio_free; - - gpio_direction_input(gpio_wp); - - /* When supported the trigger type have to be BOTH */ - ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_ATA_DMACK)), - detect_irq, IRQF_TRIGGER_FALLING, - "sdhc-detect", data); - - if (ret) - goto err_gpio_free_2; - - return 0; - -err_gpio_free_2: - gpio_free(gpio_wp); - -err_gpio_free: - gpio_free(gpio_det); - - return ret; - -} - -static void armadillo5x0_sdhc1_exit(struct device *dev, void *data) -{ - free_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_ATA_DMACK)), data); - gpio_free(IOMUX_TO_GPIO(MX31_PIN_ATA_DMACK)); - gpio_free(IOMUX_TO_GPIO(MX31_PIN_ATA_RESET_B)); -} - -static const struct imxmmc_platform_data sdhc_pdata __initconst = { - .get_ro = armadillo5x0_sdhc1_get_ro, - .init = armadillo5x0_sdhc1_init, - .exit = armadillo5x0_sdhc1_exit, -}; - -/* - * SMSC 9118 - * Network support - */ -static struct resource armadillo5x0_smc911x_resources[] = { - { - .start = MX31_CS3_BASE_ADDR, - .end = MX31_CS3_BASE_ADDR + SZ_32M - 1, - .flags = IORESOURCE_MEM, - }, { - /* irq number is run-time assigned */ - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, - }, -}; - -static struct smsc911x_platform_config smsc911x_info = { - .flags = SMSC911X_USE_16BIT, - .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, - .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, -}; - -static struct platform_device armadillo5x0_smc911x_device = { - .name = "smsc911x", - .id = -1, - .num_resources = ARRAY_SIZE(armadillo5x0_smc911x_resources), - .resource = armadillo5x0_smc911x_resources, - .dev = { - .platform_data = &smsc911x_info, - }, -}; - -/* UART device data */ -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static struct platform_device *devices[] __initdata = { - &armadillo5x0_smc911x_device, -}; - -static struct regulator_consumer_supply dummy_supplies[] = { - REGULATOR_SUPPLY("vdd33a", "smsc911x"), - REGULATOR_SUPPLY("vddvario", "smsc911x"), -}; - -/* - * Perform board specific initializations - */ -static void __init armadillo5x0_init(void) -{ - imx31_soc_init(); - - mxc_iomux_setup_multiple_pins(armadillo5x0_pins, - ARRAY_SIZE(armadillo5x0_pins), "armadillo5x0"); - - regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); - - imx31_add_imx_i2c1(NULL); - - /* Register UART */ - imx31_add_imx_uart0(&uart_pdata); - imx31_add_imx_uart1(&uart_pdata); - - /* Register FB */ - imx31_add_ipu_core(); - imx31_add_mx3_sdc_fb(&mx3fb_pdata); - - /* Register NOR Flash */ - platform_device_register_resndata(NULL, "physmap-flash", -1, - &armadillo5x0_nor_flash_resource, 1, - &armadillo5x0_nor_flash_pdata, - sizeof(armadillo5x0_nor_flash_pdata)); - - /* Register NAND Flash */ - imx31_add_mxc_nand(&armadillo5x0_nand_board_info); - - /* set NAND page size to 2k if not configured via boot mode pins */ - imx_writel(imx_readl(mx3_ccm_base + MXC_CCM_RCSR) | (1 << 30), - mx3_ccm_base + MXC_CCM_RCSR); -} - -static void __init armadillo5x0_late(void) -{ - armadillo5x0_smc911x_resources[1].start = - gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_0)); - armadillo5x0_smc911x_resources[1].end = - gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_0)); - platform_add_devices(devices, ARRAY_SIZE(devices)); - - imx_add_gpio_keys(&armadillo5x0_button_data); - - /* SMSC9118 IRQ pin */ - gpio_direction_input(MX31_PIN_GPIO1_0); - - /* Register SDHC */ - imx31_add_mxc_mmc(0, &sdhc_pdata); - - /* RTC */ - /* Get RTC IRQ and register the chip */ - if (!gpio_request(ARMADILLO5X0_RTC_GPIO, "rtc")) { - if (!gpio_direction_input(ARMADILLO5X0_RTC_GPIO)) - armadillo5x0_i2c_rtc.irq = - gpio_to_irq(ARMADILLO5X0_RTC_GPIO); - else - gpio_free(ARMADILLO5X0_RTC_GPIO); - } - - if (armadillo5x0_i2c_rtc.irq == 0) - pr_warn("armadillo5x0_init: failed to get RTC IRQ\n"); - i2c_register_board_info(1, &armadillo5x0_i2c_rtc, 1); - - /* USB */ - usbotg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | - ULPI_OTG_DRVVBUS_EXT); - if (usbotg_pdata.otg) - imx31_add_mxc_ehci_otg(&usbotg_pdata); - usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | - ULPI_OTG_DRVVBUS_EXT); - if (usbh2_pdata.otg) - imx31_add_mxc_ehci_hs(2, &usbh2_pdata); -} - -static void __init armadillo5x0_timer_init(void) -{ - mx31_clocks_init(26000000); -} - -MACHINE_START(ARMADILLO5X0, "Armadillo-500") - /* Maintainer: Alberto Panizzo */ - .atag_offset = 0x100, - .map_io = mx31_map_io, - .init_early = imx31_init_early, - .init_irq = mx31_init_irq, - .init_time = armadillo5x0_timer_init, - .init_machine = armadillo5x0_init, - .init_late = armadillo5x0_late, - .restart = mxc_restart, -MACHINE_END diff --git a/arch/arm/mach-imx/mach-bug.c b/arch/arm/mach-imx/mach-bug.c deleted file mode 100644 index 3929208600f2..000000000000 --- a/arch/arm/mach-imx/mach-bug.c +++ /dev/null @@ -1,54 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (C) 2000 Deep Blue Solutions Ltd - * Copyright (C) 2002 Shane Nay (shane@minirl.com) - * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2011 Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/platform_device.h> - -#include <asm/mach/time.h> -#include <asm/mach/arch.h> -#include <asm/mach-types.h> - -#include "common.h" -#include "devices-imx31.h" -#include "hardware.h" -#include "iomux-mx3.h" - -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static const unsigned int bug_pins[] __initconst = { - MX31_PIN_PC_RST__CTS5, - MX31_PIN_PC_VS2__RTS5, - MX31_PIN_PC_BVD2__TXD5, - MX31_PIN_PC_BVD1__RXD5, -}; - -static void __init bug_board_init(void) -{ - imx31_soc_init(); - - mxc_iomux_setup_multiple_pins(bug_pins, - ARRAY_SIZE(bug_pins), "uart-4"); - imx31_add_imx_uart4(&uart_pdata); -} - -static void __init bug_timer_init(void) -{ - mx31_clocks_init(26000000); -} - -MACHINE_START(BUG, "BugLabs BUGBase") - .map_io = mx31_map_io, - .init_early = imx31_init_early, - .init_irq = mx31_init_irq, - .init_time = bug_timer_init, - .init_machine = bug_board_init, - .restart = mxc_restart, -MACHINE_END diff --git a/arch/arm/mach-imx/mach-imx27.c b/arch/arm/mach-imx/mach-imx27.c new file mode 100644 index 000000000000..262422a9c196 --- /dev/null +++ b/arch/arm/mach-imx/mach-imx27.c @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2012 Sascha Hauer, Pengutronix + */ + +#include <linux/init.h> +#include <linux/irq.h> +#include <linux/of_address.h> +#include <linux/of_irq.h> +#include <linux/of_platform.h> +#include <linux/mm.h> +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <asm/mach/time.h> + +#include "common.h" +#include "hardware.h" +#include "mx27.h" + +/* MX27 memory map definition */ +static struct map_desc imx27_io_desc[] __initdata = { + /* + * this fixed mapping covers: + * - AIPI1 + * - AIPI2 + * - AITC + * - ROM Patch + * - and some reserved space + */ + imx_map_entry(MX27, AIPI, MT_DEVICE), + /* + * this fixed mapping covers: + * - CSI + * - ATA + */ + imx_map_entry(MX27, SAHB1, MT_DEVICE), + /* + * this fixed mapping covers: + * - EMI + */ + imx_map_entry(MX27, X_MEMC, MT_DEVICE), +}; + +/* + * Initialize the memory map. It is called during the + * system startup to create static physical to virtual + * memory map for the IO modules. + */ +static void __init mx27_map_io(void) +{ + iotable_init(imx27_io_desc, ARRAY_SIZE(imx27_io_desc)); +} + +static void __init imx27_init_early(void) +{ + mxc_set_cpu_type(MXC_CPU_MX27); +} + +static void __init mx27_init_irq(void) +{ + void __iomem *avic_base; + struct device_node *np; + + np = of_find_compatible_node(NULL, NULL, "fsl,avic"); + avic_base = of_iomap(np, 0); + BUG_ON(!avic_base); + mxc_init_irq(avic_base); +} + +static const char * const imx27_dt_board_compat[] __initconst = { + "fsl,imx27", + NULL +}; + +DT_MACHINE_START(IMX27_DT, "Freescale i.MX27 (Device Tree Support)") + .map_io = mx27_map_io, + .init_early = imx27_init_early, + .init_irq = mx27_init_irq, + .init_late = imx27_pm_init, + .dt_compat = imx27_dt_board_compat, +MACHINE_END diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c deleted file mode 100644 index a329e50928b6..000000000000 --- a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c +++ /dev/null @@ -1,562 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * mach-imx27_visstrim_m10.c - * - * Copyright 2010 Javier Martin <javier.martin@vista-silicon.com> - * - * Based on mach-pcm038.c, mach-pca100.c, mach-mx27ads.c and others. - */ - -#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt - -#include <linux/platform_device.h> -#include <linux/mtd/physmap.h> -#include <linux/i2c.h> -#include <linux/platform_data/pca953x.h> -#include <linux/input.h> -#include <linux/gpio.h> -#include <linux/delay.h> -#include <linux/dma-map-ops.h> -#include <linux/leds.h> -#include <linux/platform_data/asoc-mx27vis.h> -#include <sound/tlv320aic32x4.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> -#include <asm/system_info.h> -#include <asm/memblock.h> - -#include "common.h" -#include "devices-imx27.h" -#include "ehci.h" -#include "hardware.h" -#include "iomux-mx27.h" - -#define TVP5150_RSTN (GPIO_PORTC + 18) -#define TVP5150_PWDN (GPIO_PORTC + 19) -#define OTG_PHY_CS_GPIO (GPIO_PORTF + 17) -#define SDHC1_IRQ_GPIO IMX_GPIO_NR(2, 25) - -#define VERSION_MASK 0x7 -#define MOTHERBOARD_SHIFT 4 -#define EXPBOARD_SHIFT 0 - -#define MOTHERBOARD_BIT2 (GPIO_PORTD + 31) -#define MOTHERBOARD_BIT1 (GPIO_PORTD + 30) -#define MOTHERBOARD_BIT0 (GPIO_PORTD + 29) - -#define EXPBOARD_BIT2 (GPIO_PORTD + 25) -#define EXPBOARD_BIT1 (GPIO_PORTD + 27) -#define EXPBOARD_BIT0 (GPIO_PORTD + 28) - -#define AMP_GAIN_0 (GPIO_PORTF + 9) -#define AMP_GAIN_1 (GPIO_PORTF + 8) -#define AMP_MUTE_SDL (GPIO_PORTE + 5) -#define AMP_MUTE_SDR (GPIO_PORTF + 7) - -static const int visstrim_m10_pins[] __initconst = { - /* UART1 (console) */ - PE12_PF_UART1_TXD, - PE13_PF_UART1_RXD, - PE14_PF_UART1_CTS, - PE15_PF_UART1_RTS, - /* FEC */ - PD0_AIN_FEC_TXD0, - PD1_AIN_FEC_TXD1, - PD2_AIN_FEC_TXD2, - PD3_AIN_FEC_TXD3, - PD4_AOUT_FEC_RX_ER, - PD5_AOUT_FEC_RXD1, - PD6_AOUT_FEC_RXD2, - PD7_AOUT_FEC_RXD3, - PD8_AF_FEC_MDIO, - PD9_AIN_FEC_MDC, - PD10_AOUT_FEC_CRS, - PD11_AOUT_FEC_TX_CLK, - PD12_AOUT_FEC_RXD0, - PD13_AOUT_FEC_RX_DV, - PD14_AOUT_FEC_RX_CLK, - PD15_AOUT_FEC_COL, - PD16_AIN_FEC_TX_ER, - PF23_AIN_FEC_TX_EN, - /* SSI1 */ - PC20_PF_SSI1_FS, - PC21_PF_SSI1_RXD, - PC22_PF_SSI1_TXD, - PC23_PF_SSI1_CLK, - /* SDHC1 */ - PE18_PF_SD1_D0, - PE19_PF_SD1_D1, - PE20_PF_SD1_D2, - PE21_PF_SD1_D3, - PE22_PF_SD1_CMD, - PE23_PF_SD1_CLK, - /* Both I2Cs */ - PD17_PF_I2C_DATA, - PD18_PF_I2C_CLK, - PC5_PF_I2C2_SDA, - PC6_PF_I2C2_SCL, - /* USB OTG */ - OTG_PHY_CS_GPIO | GPIO_GPIO | GPIO_OUT, - PC9_PF_USBOTG_DATA0, - PC11_PF_USBOTG_DATA1, - PC10_PF_USBOTG_DATA2, - PC13_PF_USBOTG_DATA3, - PC12_PF_USBOTG_DATA4, - PC7_PF_USBOTG_DATA5, - PC8_PF_USBOTG_DATA6, - PE25_PF_USBOTG_DATA7, - PE24_PF_USBOTG_CLK, - PE2_PF_USBOTG_DIR, - PE0_PF_USBOTG_NXT, - PE1_PF_USBOTG_STP, - PB23_PF_USB_PWR, - PB24_PF_USB_OC, - /* CSI */ - TVP5150_RSTN | GPIO_GPIO | GPIO_OUT, - TVP5150_PWDN | GPIO_GPIO | GPIO_OUT, - PB10_PF_CSI_D0, - PB11_PF_CSI_D1, - PB12_PF_CSI_D2, - PB13_PF_CSI_D3, - PB14_PF_CSI_D4, - PB15_PF_CSI_MCLK, - PB16_PF_CSI_PIXCLK, - PB17_PF_CSI_D5, - PB18_PF_CSI_D6, - PB19_PF_CSI_D7, - PB20_PF_CSI_VSYNC, - PB21_PF_CSI_HSYNC, - /* mother board version */ - MOTHERBOARD_BIT2 | GPIO_GPIO | GPIO_IN | GPIO_PUEN, - MOTHERBOARD_BIT1 | GPIO_GPIO | GPIO_IN | GPIO_PUEN, - MOTHERBOARD_BIT0 | GPIO_GPIO | GPIO_IN | GPIO_PUEN, - /* expansion board version */ - EXPBOARD_BIT2 | GPIO_GPIO | GPIO_IN | GPIO_PUEN, - EXPBOARD_BIT1 | GPIO_GPIO | GPIO_IN | GPIO_PUEN, - EXPBOARD_BIT0 | GPIO_GPIO | GPIO_IN | GPIO_PUEN, - /* Audio AMP control */ - AMP_GAIN_0 | GPIO_GPIO | GPIO_OUT, - AMP_GAIN_1 | GPIO_GPIO | GPIO_OUT, - AMP_MUTE_SDL | GPIO_GPIO | GPIO_OUT, - AMP_MUTE_SDR | GPIO_GPIO | GPIO_OUT, -}; - -static struct gpio visstrim_m10_version_gpios[] = { - { EXPBOARD_BIT0, GPIOF_IN, "exp-version-0" }, - { EXPBOARD_BIT1, GPIOF_IN, "exp-version-1" }, - { EXPBOARD_BIT2, GPIOF_IN, "exp-version-2" }, - { MOTHERBOARD_BIT0, GPIOF_IN, "mother-version-0" }, - { MOTHERBOARD_BIT1, GPIOF_IN, "mother-version-1" }, - { MOTHERBOARD_BIT2, GPIOF_IN, "mother-version-2" }, -}; - -static const struct gpio visstrim_m10_gpios[] __initconst = { - { - .gpio = TVP5150_RSTN, - .flags = GPIOF_DIR_OUT | GPIOF_INIT_HIGH, - .label = "tvp5150_rstn", - }, - { - .gpio = TVP5150_PWDN, - .flags = GPIOF_DIR_OUT | GPIOF_INIT_LOW, - .label = "tvp5150_pwdn", - }, - { - .gpio = OTG_PHY_CS_GPIO, - .flags = GPIOF_DIR_OUT | GPIOF_INIT_LOW, - .label = "usbotg_cs", - }, - { - .gpio = AMP_GAIN_0, - .flags = GPIOF_DIR_OUT, - .label = "amp-gain-0", - }, - { - .gpio = AMP_GAIN_1, - .flags = GPIOF_DIR_OUT, - .label = "amp-gain-1", - }, - { - .gpio = AMP_MUTE_SDL, - .flags = GPIOF_DIR_OUT, - .label = "amp-mute-sdl", - }, - { - .gpio = AMP_MUTE_SDR, - .flags = GPIOF_DIR_OUT, - .label = "amp-mute-sdr", - }, -}; - -/* Camera */ -static struct mx2_camera_platform_data visstrim_camera = { - .flags = MX2_CAMERA_CCIR | MX2_CAMERA_CCIR_INTERLACE | - MX2_CAMERA_PCLK_SAMPLE_RISING, - .clk = 100000, -}; - -static phys_addr_t mx2_camera_base __initdata; -#define MX2_CAMERA_BUF_SIZE SZ_8M - -static void __init visstrim_analog_camera_init(void) -{ - struct platform_device *pdev; - - gpio_set_value(TVP5150_PWDN, 1); - ndelay(1); - gpio_set_value(TVP5150_RSTN, 0); - ndelay(500); - gpio_set_value(TVP5150_RSTN, 1); - ndelay(200000); - - pdev = imx27_add_mx2_camera(&visstrim_camera); - if (IS_ERR(pdev)) - return; - - dma_declare_coherent_memory(&pdev->dev, mx2_camera_base, - mx2_camera_base, MX2_CAMERA_BUF_SIZE); -} - -static void __init visstrim_reserve(void) -{ - /* reserve 4 MiB for mx2-camera */ - mx2_camera_base = arm_memblock_steal(3 * MX2_CAMERA_BUF_SIZE, - MX2_CAMERA_BUF_SIZE); -} - -/* GPIOs used as events for applications */ -static struct gpio_keys_button visstrim_gpio_keys[] = { - { - .type = EV_KEY, - .code = KEY_RESTART, - .gpio = (GPIO_PORTC + 15), - .desc = "Default config", - .active_low = 0, - .wakeup = 1, - }, - { - .type = EV_KEY, - .code = KEY_RECORD, - .gpio = (GPIO_PORTF + 14), - .desc = "Record", - .active_low = 0, - .wakeup = 1, - }, - { - .type = EV_KEY, - .code = KEY_STOP, - .gpio = (GPIO_PORTF + 13), - .desc = "Stop", - .active_low = 0, - .wakeup = 1, - } -}; - -static const struct gpio_keys_platform_data - visstrim_gpio_keys_platform_data __initconst = { - .buttons = visstrim_gpio_keys, - .nbuttons = ARRAY_SIZE(visstrim_gpio_keys), -}; - -/* led */ -static const struct gpio_led visstrim_m10_leds[] __initconst = { - { - .name = "visstrim:ld0", - .default_trigger = "nand-disk", - .gpio = (GPIO_PORTC + 29), - }, - { - .name = "visstrim:ld1", - .default_trigger = "nand-disk", - .gpio = (GPIO_PORTC + 24), - }, - { - .name = "visstrim:ld2", - .default_trigger = "nand-disk", - .gpio = (GPIO_PORTC + 28), - }, - { - .name = "visstrim:ld3", - .default_trigger = "nand-disk", - .gpio = (GPIO_PORTC + 25), - }, -}; - -static const struct gpio_led_platform_data visstrim_m10_led_data __initconst = { - .leds = visstrim_m10_leds, - .num_leds = ARRAY_SIZE(visstrim_m10_leds), -}; - -/* Visstrim_SM10 has a microSD slot connected to sdhc1 */ -static int visstrim_m10_sdhc1_init(struct device *dev, - irq_handler_t detect_irq, void *data) -{ - int ret; - - ret = request_irq(gpio_to_irq(SDHC1_IRQ_GPIO), detect_irq, - IRQF_TRIGGER_FALLING, "mmc-detect", data); - return ret; -} - -static void visstrim_m10_sdhc1_exit(struct device *dev, void *data) -{ - free_irq(gpio_to_irq(SDHC1_IRQ_GPIO), data); -} - -static const struct imxmmc_platform_data visstrim_m10_sdhc_pdata __initconst = { - .init = visstrim_m10_sdhc1_init, - .exit = visstrim_m10_sdhc1_exit, -}; - -/* Visstrim_SM10 NOR flash */ -static struct physmap_flash_data visstrim_m10_flash_data = { - .width = 2, -}; - -static struct resource visstrim_m10_flash_resource = { - .start = 0xc0000000, - .end = 0xc0000000 + SZ_64M - 1, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device visstrim_m10_nor_mtd_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &visstrim_m10_flash_data, - }, - .num_resources = 1, - .resource = &visstrim_m10_flash_resource, -}; - -static struct platform_device *platform_devices[] __initdata = { - &visstrim_m10_nor_mtd_device, -}; - -/* Visstrim_M10 uses UART0 as console */ -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -/* I2C */ -static const struct imxi2c_platform_data visstrim_m10_i2c_data __initconst = { - .bitrate = 100000, -}; - -static struct pca953x_platform_data visstrim_m10_pca9555_pdata = { - .gpio_base = 240, /* After MX27 internal GPIOs */ - .invert = 0, -}; - -static struct aic32x4_pdata visstrim_m10_aic32x4_pdata = { - .power_cfg = AIC32X4_PWR_MICBIAS_2075_LDOIN | - AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE | - AIC32X4_PWR_AIC32X4_LDO_ENABLE | - AIC32X4_PWR_CMMODE_LDOIN_RANGE_18_36 | - AIC32X4_PWR_CMMODE_HP_LDOIN_POWERED, - .micpga_routing = AIC32X4_MICPGA_ROUTE_LMIC_IN2R_10K | - AIC32X4_MICPGA_ROUTE_RMIC_IN1L_10K, - .swapdacs = false, -}; - -static struct i2c_board_info visstrim_m10_i2c_devices[] = { - { - I2C_BOARD_INFO("pca9555", 0x20), - .platform_data = &visstrim_m10_pca9555_pdata, - }, - { - I2C_BOARD_INFO("tlv320aic32x4", 0x18), - .platform_data = &visstrim_m10_aic32x4_pdata, - }, - { - I2C_BOARD_INFO("m41t00", 0x68), - } -}; - -/* USB OTG */ -static int otg_phy_init(struct platform_device *pdev) -{ - return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED); -} - -static const struct mxc_usbh_platform_data -visstrim_m10_usbotg_pdata __initconst = { - .init = otg_phy_init, - .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, -}; - -/* SSI */ -static const struct imx_ssi_platform_data visstrim_m10_ssi_pdata __initconst = { - .flags = IMX_SSI_DMA | IMX_SSI_SYN, -}; - -/* coda */ - -static void __init visstrim_coda_init(void) -{ - struct platform_device *pdev; - - pdev = imx27_add_coda(); - dma_declare_coherent_memory(&pdev->dev, - mx2_camera_base + MX2_CAMERA_BUF_SIZE, - mx2_camera_base + MX2_CAMERA_BUF_SIZE, - MX2_CAMERA_BUF_SIZE); -} - -/* DMA deinterlace */ -static struct platform_device visstrim_deinterlace = { - .name = "m2m-deinterlace", - .id = 0, -}; - -static void __init visstrim_deinterlace_init(void) -{ - int ret = -ENOMEM; - struct platform_device *pdev = &visstrim_deinterlace; - - ret = platform_device_register(pdev); - - dma_declare_coherent_memory(&pdev->dev, - mx2_camera_base + 2 * MX2_CAMERA_BUF_SIZE, - mx2_camera_base + 2 * MX2_CAMERA_BUF_SIZE, - MX2_CAMERA_BUF_SIZE); -} - -/* Emma-PrP for format conversion */ -static void __init visstrim_emmaprp_init(void) -{ - struct platform_device *pdev; - int ret; - - pdev = imx27_add_mx2_emmaprp(); - if (IS_ERR(pdev)) - return; - - /* - * Use the same memory area as the analog camera since both - * devices are, by nature, exclusive. - */ - ret = dma_declare_coherent_memory(&pdev->dev, - mx2_camera_base, mx2_camera_base, - MX2_CAMERA_BUF_SIZE); - if (ret) - pr_err("Failed to declare memory for emmaprp\n"); -} - -/* Audio */ -static const struct snd_mx27vis_platform_data snd_mx27vis_pdata __initconst = { - .amp_gain0_gpio = AMP_GAIN_0, - .amp_gain1_gpio = AMP_GAIN_1, - .amp_mutel_gpio = AMP_MUTE_SDL, - .amp_muter_gpio = AMP_MUTE_SDR, -}; - -static void __init visstrim_m10_revision(void) -{ - int exp_version = 0; - int mo_version = 0; - int ret; - - ret = gpio_request_array(visstrim_m10_version_gpios, - ARRAY_SIZE(visstrim_m10_version_gpios)); - if (ret) { - pr_err("Failed to request version gpios"); - return; - } - - /* Get expansion board version (negative logic) */ - exp_version |= !gpio_get_value(EXPBOARD_BIT2) << 2; - exp_version |= !gpio_get_value(EXPBOARD_BIT1) << 1; - exp_version |= !gpio_get_value(EXPBOARD_BIT0); - - /* Get mother board version (negative logic) */ - mo_version |= !gpio_get_value(MOTHERBOARD_BIT2) << 2; - mo_version |= !gpio_get_value(MOTHERBOARD_BIT1) << 1; - mo_version |= !gpio_get_value(MOTHERBOARD_BIT0); - - system_rev = 0x27000; - system_rev |= (mo_version << MOTHERBOARD_SHIFT); - system_rev |= (exp_version << EXPBOARD_SHIFT); -} - -static void __init visstrim_m10_board_init(void) -{ - int ret; - - imx27_soc_init(); - visstrim_m10_revision(); - - ret = mxc_gpio_setup_multiple_pins(visstrim_m10_pins, - ARRAY_SIZE(visstrim_m10_pins), "VISSTRIM_M10"); - if (ret) - pr_err("Failed to setup pins (%d)\n", ret); - - imx27_add_imx_ssi(0, &visstrim_m10_ssi_pdata); - imx27_add_imx_uart0(&uart_pdata); - - imx27_add_imx_i2c(0, &visstrim_m10_i2c_data); - imx27_add_imx_i2c(1, &visstrim_m10_i2c_data); - i2c_register_board_info(0, visstrim_m10_i2c_devices, - ARRAY_SIZE(visstrim_m10_i2c_devices)); - - imx27_add_mxc_mmc(0, &visstrim_m10_sdhc_pdata); - imx27_add_mxc_ehci_otg(&visstrim_m10_usbotg_pdata); - imx27_add_fec(NULL); - - platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); -} - -static void __init visstrim_m10_late_init(void) -{ - int mo_version, ret; - - ret = gpio_request_array(visstrim_m10_gpios, - ARRAY_SIZE(visstrim_m10_gpios)); - if (ret) - pr_err("Failed to request gpios (%d)\n", ret); - - imx_add_gpio_keys(&visstrim_gpio_keys_platform_data); - - imx_add_platform_device("mx27vis", 0, NULL, 0, &snd_mx27vis_pdata, - sizeof(snd_mx27vis_pdata)); - - gpio_led_register_device(0, &visstrim_m10_led_data); - - /* Use mother board version to decide what video devices we shall use */ - mo_version = (system_rev >> MOTHERBOARD_SHIFT) & VERSION_MASK; - if (mo_version & 0x1) { - visstrim_emmaprp_init(); - - /* - * Despite not being used, tvp5150 must be - * powered on to avoid I2C problems. To minimize - * power consupmtion keep reset enabled. - */ - gpio_set_value(TVP5150_PWDN, 1); - ndelay(1); - gpio_set_value(TVP5150_RSTN, 0); - } else { - visstrim_deinterlace_init(); - visstrim_analog_camera_init(); - } - - visstrim_coda_init(); -} - -static void __init visstrim_m10_timer_init(void) -{ - mx27_clocks_init((unsigned long)25000000); -} - -MACHINE_START(IMX27_VISSTRIM_M10, "Vista Silicon Visstrim_M10") - .atag_offset = 0x100, - .reserve = visstrim_reserve, - .map_io = mx27_map_io, - .init_early = imx27_init_early, - .init_irq = mx27_init_irq, - .init_time = visstrim_m10_timer_init, - .init_machine = visstrim_m10_board_init, - .init_late = visstrim_m10_late_init, - .restart = mxc_restart, -MACHINE_END diff --git a/arch/arm/mach-imx/imx31-dt.c b/arch/arm/mach-imx/mach-imx31.c index dc69dfe600df..dc69dfe600df 100644 --- a/arch/arm/mach-imx/imx31-dt.c +++ b/arch/arm/mach-imx/mach-imx31.c diff --git a/arch/arm/mach-imx/imx35-dt.c b/arch/arm/mach-imx/mach-imx35.c index ec5c3068715c..ec5c3068715c 100644 --- a/arch/arm/mach-imx/imx35-dt.c +++ b/arch/arm/mach-imx/mach-imx35.c diff --git a/arch/arm/mach-imx/mach-imx7ulp.c b/arch/arm/mach-imx/mach-imx7ulp.c index 128cf4c92aab..445256e6a4a0 100644 --- a/arch/arm/mach-imx/mach-imx7ulp.c +++ b/arch/arm/mach-imx/mach-imx7ulp.c @@ -67,6 +67,9 @@ static const char *const imx7ulp_dt_compat[] __initconst = { static void __init imx7ulp_init_late(void) { + if (IS_ENABLED(CONFIG_ARM_IMX_CPUFREQ_DT)) + platform_device_register_simple("imx-cpufreq-dt", -1, NULL, 0); + imx7ulp_cpuidle_init(); } diff --git a/arch/arm/mach-imx/mach-kzm_arm11_01.c b/arch/arm/mach-imx/mach-kzm_arm11_01.c deleted file mode 100644 index 63f7f78a77af..000000000000 --- a/arch/arm/mach-imx/mach-kzm_arm11_01.c +++ /dev/null @@ -1,291 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * KZM-ARM11-01 support - * Copyright (C) 2009 Yoichi Yuasa <yuasa@linux-mips.org> - * - * based on code for MX31ADS, - * Copyright (C) 2000 Deep Blue Solutions Ltd - * Copyright (C) 2002 Shane Nay (shane@minirl.com) - * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -#include <linux/gpio.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/serial_8250.h> -#include <linux/smsc911x.h> -#include <linux/types.h> -#include <linux/regulator/machine.h> -#include <linux/regulator/fixed.h> - -#include <asm/irq.h> -#include <asm/mach-types.h> -#include <asm/memory.h> -#include <asm/setup.h> -#include <asm/mach/arch.h> -#include <asm/mach/irq.h> -#include <asm/mach/map.h> -#include <asm/mach/time.h> - -#include "common.h" -#include "devices-imx31.h" -#include "hardware.h" -#include "iomux-mx3.h" - -#define KZM_ARM11_IO_ADDRESS(x) (IOMEM( \ - IMX_IO_P2V_MODULE(x, MX31_CS4) ?: \ - IMX_IO_P2V_MODULE(x, MX31_CS5)) ?: \ - MX31_IO_ADDRESS(x)) - -/* - * KZM-ARM11-01 Board Control Registers on FPGA - */ -#define KZM_ARM11_CTL1 (MX31_CS4_BASE_ADDR + 0x1000) -#define KZM_ARM11_CTL2 (MX31_CS4_BASE_ADDR + 0x1001) -#define KZM_ARM11_RSW1 (MX31_CS4_BASE_ADDR + 0x1002) -#define KZM_ARM11_BACK_LIGHT (MX31_CS4_BASE_ADDR + 0x1004) -#define KZM_ARM11_FPGA_REV (MX31_CS4_BASE_ADDR + 0x1008) -#define KZM_ARM11_7SEG_LED (MX31_CS4_BASE_ADDR + 0x1010) -#define KZM_ARM11_LEDS (MX31_CS4_BASE_ADDR + 0x1020) -#define KZM_ARM11_DIPSW2 (MX31_CS4_BASE_ADDR + 0x1003) - -/* - * External UART for touch panel on FPGA - */ -#define KZM_ARM11_16550 (MX31_CS4_BASE_ADDR + 0x1050) - -#if IS_ENABLED(CONFIG_SERIAL_8250) -/* - * KZM-ARM11-01 has an external UART on FPGA - */ -static struct plat_serial8250_port serial_platform_data[] = { - { - .membase = KZM_ARM11_IO_ADDRESS(KZM_ARM11_16550), - .mapbase = KZM_ARM11_16550, - /* irq number is run-time assigned */ - .irqflags = IRQ_TYPE_EDGE_RISING, - .uartclk = 14745600, - .regshift = 0, - .iotype = UPIO_MEM, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | - UPF_BUGGY_UART, - }, - {}, -}; - -static struct resource serial8250_resources[] = { - { - .start = KZM_ARM11_16550, - .end = KZM_ARM11_16550 + 0x10, - .flags = IORESOURCE_MEM, - }, - { - /* irq number is run-time assigned */ - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device serial_device = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = serial_platform_data, - }, - .num_resources = ARRAY_SIZE(serial8250_resources), - .resource = serial8250_resources, -}; - -static int __init kzm_init_ext_uart(void) -{ - u8 tmp; - - /* - * GPIO 1-1: external UART interrupt line - */ - mxc_iomux_mode(IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO)); - gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1), "ext-uart-int"); - gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1)); - - /* - * Unmask UART interrupt - */ - tmp = __raw_readb(KZM_ARM11_IO_ADDRESS(KZM_ARM11_CTL1)); - tmp |= 0x2; - __raw_writeb(tmp, KZM_ARM11_IO_ADDRESS(KZM_ARM11_CTL1)); - - serial_platform_data[0].irq = - gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1)); - serial8250_resources[1].start = - gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1)); - serial8250_resources[1].end = - gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1)); - - return platform_device_register(&serial_device); -} -#else -static inline int kzm_init_ext_uart(void) -{ - return 0; -} -#endif - -/* - * SMSC LAN9118 - */ -#if IS_ENABLED(CONFIG_SMSC911X) -static struct smsc911x_platform_config kzm_smsc9118_config = { - .phy_interface = PHY_INTERFACE_MODE_MII, - .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH, - .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, - .flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS, -}; - -static struct resource kzm_smsc9118_resources[] = { - { - .start = MX31_CS5_BASE_ADDR, - .end = MX31_CS5_BASE_ADDR + SZ_128K - 1, - .flags = IORESOURCE_MEM, - }, - { - /* irq number is run-time assigned */ - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, - }, -}; - -static struct platform_device kzm_smsc9118_device = { - .name = "smsc911x", - .id = -1, - .num_resources = ARRAY_SIZE(kzm_smsc9118_resources), - .resource = kzm_smsc9118_resources, - .dev = { - .platform_data = &kzm_smsc9118_config, - }, -}; - -static struct regulator_consumer_supply dummy_supplies[] = { - REGULATOR_SUPPLY("vdd33a", "smsc911x"), - REGULATOR_SUPPLY("vddvario", "smsc911x"), -}; - -static int __init kzm_init_smsc9118(void) -{ - /* - * GPIO 1-2: SMSC9118 interrupt line - */ - mxc_iomux_mode(IOMUX_MODE(MX31_PIN_GPIO1_2, IOMUX_CONFIG_GPIO)); - gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_2), "smsc9118-int"); - gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_2)); - - regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); - - kzm_smsc9118_resources[1].start = - gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_2)); - kzm_smsc9118_resources[1].end = - gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_2)); - - return platform_device_register(&kzm_smsc9118_device); -} -#else -static inline int kzm_init_smsc9118(void) -{ - return 0; -} -#endif - -#if IS_ENABLED(CONFIG_SERIAL_IMX) -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static void __init kzm_init_imx_uart(void) -{ - imx31_add_imx_uart0(&uart_pdata); - imx31_add_imx_uart1(&uart_pdata); -} -#else -static inline void kzm_init_imx_uart(void) -{ -} -#endif - -static int kzm_pins[] __initdata = { - MX31_PIN_CTS1__CTS1, - MX31_PIN_RTS1__RTS1, - MX31_PIN_TXD1__TXD1, - MX31_PIN_RXD1__RXD1, - MX31_PIN_DCD_DCE1__DCD_DCE1, - MX31_PIN_RI_DCE1__RI_DCE1, - MX31_PIN_DSR_DCE1__DSR_DCE1, - MX31_PIN_DTR_DCE1__DTR_DCE1, - MX31_PIN_CTS2__CTS2, - MX31_PIN_RTS2__RTS2, - MX31_PIN_TXD2__TXD2, - MX31_PIN_RXD2__RXD2, - MX31_PIN_DCD_DTE1__DCD_DTE2, - MX31_PIN_RI_DTE1__RI_DTE2, - MX31_PIN_DSR_DTE1__DSR_DTE2, - MX31_PIN_DTR_DTE1__DTR_DTE2, -}; - -/* - * Board specific initialization. - */ -static void __init kzm_board_init(void) -{ - imx31_soc_init(); - - mxc_iomux_setup_multiple_pins(kzm_pins, - ARRAY_SIZE(kzm_pins), "kzm"); - kzm_init_imx_uart(); - - pr_info("Clock input source is 26MHz\n"); -} - -static void __init kzm_late_init(void) -{ - kzm_init_ext_uart(); - kzm_init_smsc9118(); -} - -/* - * This structure defines static mappings for the kzm-arm11-01 board. - */ -static struct map_desc kzm_io_desc[] __initdata = { - { - .virtual = (unsigned long)MX31_CS4_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR), - .length = MX31_CS4_SIZE, - .type = MT_DEVICE - }, - { - .virtual = (unsigned long)MX31_CS5_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(MX31_CS5_BASE_ADDR), - .length = MX31_CS5_SIZE, - .type = MT_DEVICE - }, -}; - -/* - * Set up static virtual mappings. - */ -static void __init kzm_map_io(void) -{ - mx31_map_io(); - iotable_init(kzm_io_desc, ARRAY_SIZE(kzm_io_desc)); -} - -static void __init kzm_timer_init(void) -{ - mx31_clocks_init(26000000); -} - -MACHINE_START(KZM_ARM11_01, "Kyoto Microcomputer Co., Ltd. KZM-ARM11-01") - .atag_offset = 0x100, - .map_io = kzm_map_io, - .init_early = imx31_init_early, - .init_irq = mx31_init_irq, - .init_time = kzm_timer_init, - .init_machine = kzm_board_init, - .init_late = kzm_late_init, - .restart = mxc_restart, -MACHINE_END diff --git a/arch/arm/mach-imx/mach-mx21ads.c b/arch/arm/mach-imx/mach-mx21ads.c deleted file mode 100644 index ec011e89eb9e..000000000000 --- a/arch/arm/mach-imx/mach-mx21ads.c +++ /dev/null @@ -1,338 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (C) 2000 Deep Blue Solutions Ltd - * Copyright (C) 2002 Shane Nay (shane@minirl.com) - * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -#include <linux/platform_device.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/physmap.h> -#include <linux/gpio/driver.h> -#include <linux/gpio/machine.h> -#include <linux/gpio.h> -#include <linux/regulator/fixed.h> -#include <linux/regulator/machine.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> - -#include "common.h" -#include "devices-imx21.h" -#include "hardware.h" -#include "iomux-mx21.h" - -#define MX21ADS_CS8900A_REG (MX21_CS1_BASE_ADDR + 0x000000) -#define MX21ADS_ST16C255_IOBASE_REG (MX21_CS1_BASE_ADDR + 0x200000) -#define MX21ADS_VERSION_REG (MX21_CS1_BASE_ADDR + 0x400000) -#define MX21ADS_IO_REG (MX21_CS1_BASE_ADDR + 0x800000) - -#define MX21ADS_MMC_CD IMX_GPIO_NR(4, 25) -#define MX21ADS_CS8900A_IRQ_GPIO IMX_GPIO_NR(5, 11) -#define MX21ADS_MMGPIO_BASE (6 * 32) - -/* MX21ADS_IO_REG bit definitions */ -#define MX21ADS_IO_SD_WP (MX21ADS_MMGPIO_BASE + 0) -#define MX21ADS_IO_TP6 (MX21ADS_IO_SD_WP) -#define MX21ADS_IO_SW_SEL (MX21ADS_MMGPIO_BASE + 1) -#define MX21ADS_IO_TP7 (MX21ADS_IO_SW_SEL) -#define MX21ADS_IO_RESET_E_UART (MX21ADS_MMGPIO_BASE + 2) -#define MX21ADS_IO_RESET_BASE (MX21ADS_MMGPIO_BASE + 3) -#define MX21ADS_IO_CSI_CTL2 (MX21ADS_MMGPIO_BASE + 4) -#define MX21ADS_IO_CSI_CTL1 (MX21ADS_MMGPIO_BASE + 5) -#define MX21ADS_IO_CSI_CTL0 (MX21ADS_MMGPIO_BASE + 6) -#define MX21ADS_IO_UART1_EN (MX21ADS_MMGPIO_BASE + 7) -#define MX21ADS_IO_UART4_EN (MX21ADS_MMGPIO_BASE + 8) -#define MX21ADS_IO_LCDON (MX21ADS_MMGPIO_BASE + 9) -#define MX21ADS_IO_IRDA_EN (MX21ADS_MMGPIO_BASE + 10) -#define MX21ADS_IO_IRDA_FIR_SEL (MX21ADS_MMGPIO_BASE + 11) -#define MX21ADS_IO_IRDA_MD0_B (MX21ADS_MMGPIO_BASE + 12) -#define MX21ADS_IO_IRDA_MD1 (MX21ADS_MMGPIO_BASE + 13) -#define MX21ADS_IO_LED4_ON (MX21ADS_MMGPIO_BASE + 14) -#define MX21ADS_IO_LED3_ON (MX21ADS_MMGPIO_BASE + 15) - -static const int mx21ads_pins[] __initconst = { - - /* CS8900A */ - (GPIO_PORTE | GPIO_GPIO | GPIO_IN | 11), - - /* UART1 */ - PE12_PF_UART1_TXD, - PE13_PF_UART1_RXD, - PE14_PF_UART1_CTS, - PE15_PF_UART1_RTS, - - /* UART3 (IrDA) - only TXD and RXD */ - PE8_PF_UART3_TXD, - PE9_PF_UART3_RXD, - - /* UART4 */ - PB26_AF_UART4_RTS, - PB28_AF_UART4_TXD, - PB29_AF_UART4_CTS, - PB31_AF_UART4_RXD, - - /* LCDC */ - PA5_PF_LSCLK, - PA6_PF_LD0, - PA7_PF_LD1, - PA8_PF_LD2, - PA9_PF_LD3, - PA10_PF_LD4, - PA11_PF_LD5, - PA12_PF_LD6, - PA13_PF_LD7, - PA14_PF_LD8, - PA15_PF_LD9, - PA16_PF_LD10, - PA17_PF_LD11, - PA18_PF_LD12, - PA19_PF_LD13, - PA20_PF_LD14, - PA21_PF_LD15, - PA22_PF_LD16, - PA24_PF_REV, /* Sharp panel dedicated signal */ - PA25_PF_CLS, /* Sharp panel dedicated signal */ - PA26_PF_PS, /* Sharp panel dedicated signal */ - PA27_PF_SPL_SPR, /* Sharp panel dedicated signal */ - PA28_PF_HSYNC, - PA29_PF_VSYNC, - PA30_PF_CONTRAST, - PA31_PF_OE_ACD, - - /* MMC/SDHC */ - PE18_PF_SD1_D0, - PE19_PF_SD1_D1, - PE20_PF_SD1_D2, - PE21_PF_SD1_D3, - PE22_PF_SD1_CMD, - PE23_PF_SD1_CLK, - - /* NFC */ - PF0_PF_NRFB, - PF1_PF_NFCE, - PF2_PF_NFWP, - PF3_PF_NFCLE, - PF4_PF_NFALE, - PF5_PF_NFRE, - PF6_PF_NFWE, - PF7_PF_NFIO0, - PF8_PF_NFIO1, - PF9_PF_NFIO2, - PF10_PF_NFIO3, - PF11_PF_NFIO4, - PF12_PF_NFIO5, - PF13_PF_NFIO6, - PF14_PF_NFIO7, -}; - -/* ADS's NOR flash: 2x AM29BDS128HE9VKI on 32-bit bus */ -static struct physmap_flash_data mx21ads_flash_data = { - .width = 4, -}; - -static struct resource mx21ads_flash_resource = - DEFINE_RES_MEM(MX21_CS0_BASE_ADDR, SZ_32M); - -static struct platform_device mx21ads_nor_mtd_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &mx21ads_flash_data, - }, - .num_resources = 1, - .resource = &mx21ads_flash_resource, -}; - -static struct resource mx21ads_cs8900_resources[] __initdata = { - DEFINE_RES_MEM(MX21ADS_CS8900A_REG, SZ_1K), - /* irq number is run-time assigned */ - DEFINE_RES_IRQ(-1), -}; - -static const struct platform_device_info mx21ads_cs8900_devinfo __initconst = { - .name = "cs89x0", - .id = 0, - .res = mx21ads_cs8900_resources, - .num_res = ARRAY_SIZE(mx21ads_cs8900_resources), -}; - -static const struct imxuart_platform_data uart_pdata_rts __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static const struct imxuart_platform_data uart_pdata_norts __initconst = { -}; - -static struct resource mx21ads_mmgpio_resource = - DEFINE_RES_MEM_NAMED(MX21ADS_IO_REG, SZ_2, "dat"); - -static struct bgpio_pdata mx21ads_mmgpio_pdata = { - .label = "mx21ads-mmgpio", - .base = MX21ADS_MMGPIO_BASE, - .ngpio = 16, -}; - -static struct platform_device mx21ads_mmgpio = { - .name = "basic-mmio-gpio", - .id = PLATFORM_DEVID_AUTO, - .resource = &mx21ads_mmgpio_resource, - .num_resources = 1, - .dev = { - .platform_data = &mx21ads_mmgpio_pdata, - }, -}; - -static struct regulator_consumer_supply mx21ads_lcd_regulator_consumer = - REGULATOR_SUPPLY("lcd", "imx-fb.0"); - -static struct regulator_init_data mx21ads_lcd_regulator_init_data = { - .constraints = { - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - }, - .consumer_supplies = &mx21ads_lcd_regulator_consumer, - .num_consumer_supplies = 1, -}; - -static struct fixed_voltage_config mx21ads_lcd_regulator_pdata = { - .supply_name = "LCD", - .microvolts = 3300000, - .init_data = &mx21ads_lcd_regulator_init_data, -}; - -static struct platform_device mx21ads_lcd_regulator = { - .name = "reg-fixed-voltage", - .id = PLATFORM_DEVID_AUTO, - .dev = { - .platform_data = &mx21ads_lcd_regulator_pdata, - }, -}; - -static struct gpiod_lookup_table mx21ads_lcd_regulator_gpiod_table = { - .dev_id = "reg-fixed-voltage.0", /* Let's hope ID 0 is what we get */ - .table = { - GPIO_LOOKUP("mx21ads-mmgpio", 9, NULL, GPIO_ACTIVE_HIGH), - { }, - }, -}; - -/* - * Connected is a portrait Sharp-QVGA display - * of type: LQ035Q7DB02 - */ -static struct imx_fb_videomode mx21ads_modes[] = { - { - .mode = { - .name = "Sharp-LQ035Q7", - .refresh = 60, - .xres = 240, - .yres = 320, - .pixclock = 188679, /* in ps (5.3MHz) */ - .hsync_len = 2, - .left_margin = 6, - .right_margin = 16, - .vsync_len = 1, - .upper_margin = 8, - .lower_margin = 10, - }, - .pcr = 0xfb108bc7, - .bpp = 16, - }, -}; - -static const struct imx_fb_platform_data mx21ads_fb_data __initconst = { - .mode = mx21ads_modes, - .num_modes = ARRAY_SIZE(mx21ads_modes), - - .pwmr = 0x00a903ff, - .lscr1 = 0x00120300, - .dmacr = 0x00020008, -}; - -static int mx21ads_sdhc_get_ro(struct device *dev) -{ - return gpio_get_value(MX21ADS_IO_SD_WP); -} - -static int mx21ads_sdhc_init(struct device *dev, irq_handler_t detect_irq, - void *data) -{ - int ret; - - ret = gpio_request(MX21ADS_IO_SD_WP, "mmc-ro"); - if (ret) - return ret; - - return request_irq(gpio_to_irq(MX21ADS_MMC_CD), detect_irq, - IRQF_TRIGGER_FALLING, "mmc-detect", data); -} - -static void mx21ads_sdhc_exit(struct device *dev, void *data) -{ - free_irq(gpio_to_irq(MX21ADS_MMC_CD), data); - gpio_free(MX21ADS_IO_SD_WP); -} - -static const struct imxmmc_platform_data mx21ads_sdhc_pdata __initconst = { - .ocr_avail = MMC_VDD_29_30 | MMC_VDD_30_31, /* 3.0V */ - .get_ro = mx21ads_sdhc_get_ro, - .init = mx21ads_sdhc_init, - .exit = mx21ads_sdhc_exit, -}; - -static const struct mxc_nand_platform_data -mx21ads_nand_board_info __initconst = { - .width = 1, - .hw_ecc = 1, -}; - -static struct platform_device *platform_devices[] __initdata = { - &mx21ads_mmgpio, - &mx21ads_lcd_regulator, - &mx21ads_nor_mtd_device, -}; - -static void __init mx21ads_board_init(void) -{ - imx21_soc_init(); - - mxc_gpio_setup_multiple_pins(mx21ads_pins, ARRAY_SIZE(mx21ads_pins), - "mx21ads"); - - imx21_add_imx_uart0(&uart_pdata_rts); - imx21_add_imx_uart2(&uart_pdata_norts); - imx21_add_imx_uart3(&uart_pdata_rts); - imx21_add_mxc_nand(&mx21ads_nand_board_info); - - imx21_add_imx_fb(&mx21ads_fb_data); -} - -static void __init mx21ads_late_init(void) -{ - imx21_add_mxc_mmc(0, &mx21ads_sdhc_pdata); - - gpiod_add_lookup_table(&mx21ads_lcd_regulator_gpiod_table); - platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); - - mx21ads_cs8900_resources[1].start = - gpio_to_irq(MX21ADS_CS8900A_IRQ_GPIO); - mx21ads_cs8900_resources[1].end = - gpio_to_irq(MX21ADS_CS8900A_IRQ_GPIO); - platform_device_register_full(&mx21ads_cs8900_devinfo); -} - -static void __init mx21ads_timer_init(void) -{ - mx21_clocks_init(32768, 26000000); -} - -MACHINE_START(MX21ADS, "Freescale i.MX21ADS") - /* maintainer: Freescale Semiconductor, Inc. */ - .atag_offset = 0x100, - .map_io = mx21_map_io, - .init_early = imx21_init_early, - .init_irq = mx21_init_irq, - .init_time = mx21ads_timer_init, - .init_machine = mx21ads_board_init, - .init_late = mx21ads_late_init, - .restart = mxc_restart, -MACHINE_END diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c deleted file mode 100644 index 2db4475b7f85..000000000000 --- a/arch/arm/mach-imx/mach-mx27_3ds.c +++ /dev/null @@ -1,470 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. - * - * Author: Fabio Estevam <fabio.estevam@freescale.com> - */ - -/* - * This machine is known as: - * - i.MX27 3-Stack Development System - * - i.MX27 Platform Development Kit (i.MX27 PDK) - */ - -#include <linux/platform_device.h> -#include <linux/gpio.h> -#include <linux/gpio/machine.h> -#include <linux/irq.h> -#include <linux/usb/otg.h> -#include <linux/usb/ulpi.h> -#include <linux/delay.h> -#include <linux/mfd/mc13783.h> -#include <linux/spi/spi.h> -#include <linux/regulator/machine.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> - -#include "3ds_debugboard.h" -#include "common.h" -#include "devices-imx27.h" -#include "ehci.h" -#include "hardware.h" -#include "iomux-mx27.h" -#include "ulpi.h" - -#define SD1_EN_GPIO IMX_GPIO_NR(2, 25) -#define OTG_PHY_RESET_GPIO IMX_GPIO_NR(2, 23) -#define SPI2_SS0 IMX_GPIO_NR(4, 21) -#define PMIC_INT IMX_GPIO_NR(3, 14) -#define SPI1_SS0 IMX_GPIO_NR(4, 28) -#define SD1_CD IMX_GPIO_NR(2, 26) -#define LCD_RESET IMX_GPIO_NR(1, 3) -#define LCD_ENABLE IMX_GPIO_NR(1, 31) - -static const int mx27pdk_pins[] __initconst = { - /* UART1 */ - PE12_PF_UART1_TXD, - PE13_PF_UART1_RXD, - PE14_PF_UART1_CTS, - PE15_PF_UART1_RTS, - /* FEC */ - PD0_AIN_FEC_TXD0, - PD1_AIN_FEC_TXD1, - PD2_AIN_FEC_TXD2, - PD3_AIN_FEC_TXD3, - PD4_AOUT_FEC_RX_ER, - PD5_AOUT_FEC_RXD1, - PD6_AOUT_FEC_RXD2, - PD7_AOUT_FEC_RXD3, - PD8_AF_FEC_MDIO, - PD9_AIN_FEC_MDC, - PD10_AOUT_FEC_CRS, - PD11_AOUT_FEC_TX_CLK, - PD12_AOUT_FEC_RXD0, - PD13_AOUT_FEC_RX_DV, - PD14_AOUT_FEC_RX_CLK, - PD15_AOUT_FEC_COL, - PD16_AIN_FEC_TX_ER, - PF23_AIN_FEC_TX_EN, - /* SDHC1 */ - PE18_PF_SD1_D0, - PE19_PF_SD1_D1, - PE20_PF_SD1_D2, - PE21_PF_SD1_D3, - PE22_PF_SD1_CMD, - PE23_PF_SD1_CLK, - SD1_EN_GPIO | GPIO_GPIO | GPIO_OUT, - /* OTG */ - OTG_PHY_RESET_GPIO | GPIO_GPIO | GPIO_OUT, - PC7_PF_USBOTG_DATA5, - PC8_PF_USBOTG_DATA6, - PC9_PF_USBOTG_DATA0, - PC10_PF_USBOTG_DATA2, - PC11_PF_USBOTG_DATA1, - PC12_PF_USBOTG_DATA4, - PC13_PF_USBOTG_DATA3, - PE0_PF_USBOTG_NXT, - PE1_PF_USBOTG_STP, - PE2_PF_USBOTG_DIR, - PE24_PF_USBOTG_CLK, - PE25_PF_USBOTG_DATA7, - /* CSPI1 */ - PD31_PF_CSPI1_MOSI, - PD30_PF_CSPI1_MISO, - PD29_PF_CSPI1_SCLK, - PD25_PF_CSPI1_RDY, - SPI1_SS0 | GPIO_GPIO | GPIO_OUT, - /* CSPI2 */ - PD22_PF_CSPI2_SCLK, - PD23_PF_CSPI2_MISO, - PD24_PF_CSPI2_MOSI, - SPI2_SS0 | GPIO_GPIO | GPIO_OUT, - /* I2C1 */ - PD17_PF_I2C_DATA, - PD18_PF_I2C_CLK, - /* PMIC INT */ - PMIC_INT | GPIO_GPIO | GPIO_IN, - /* LCD */ - PA5_PF_LSCLK, - PA6_PF_LD0, - PA7_PF_LD1, - PA8_PF_LD2, - PA9_PF_LD3, - PA10_PF_LD4, - PA11_PF_LD5, - PA12_PF_LD6, - PA13_PF_LD7, - PA14_PF_LD8, - PA15_PF_LD9, - PA16_PF_LD10, - PA17_PF_LD11, - PA18_PF_LD12, - PA19_PF_LD13, - PA20_PF_LD14, - PA21_PF_LD15, - PA22_PF_LD16, - PA23_PF_LD17, - PA28_PF_HSYNC, - PA29_PF_VSYNC, - PA30_PF_CONTRAST, - LCD_ENABLE | GPIO_GPIO | GPIO_OUT, - LCD_RESET | GPIO_GPIO | GPIO_OUT, - /* SSI4 */ - PC16_PF_SSI4_FS, - PC17_PF_SSI4_RXD, - PC18_PF_SSI4_TXD, - PC19_PF_SSI4_CLK, -}; - -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -/* - * Matrix keyboard - */ - -static const uint32_t mx27_3ds_keymap[] = { - KEY(0, 0, KEY_UP), - KEY(0, 1, KEY_DOWN), - KEY(1, 0, KEY_RIGHT), - KEY(1, 1, KEY_LEFT), - KEY(1, 2, KEY_ENTER), - KEY(2, 0, KEY_F6), - KEY(2, 1, KEY_F8), - KEY(2, 2, KEY_F9), - KEY(2, 3, KEY_F10), -}; - -static const struct matrix_keymap_data mx27_3ds_keymap_data __initconst = { - .keymap = mx27_3ds_keymap, - .keymap_size = ARRAY_SIZE(mx27_3ds_keymap), -}; - -static int mx27_3ds_sdhc1_init(struct device *dev, irq_handler_t detect_irq, - void *data) -{ - return request_irq(gpio_to_irq(SD1_CD), detect_irq, - IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, "sdhc1-card-detect", data); -} - -static void mx27_3ds_sdhc1_exit(struct device *dev, void *data) -{ - free_irq(gpio_to_irq(SD1_CD), data); -} - -static const struct imxmmc_platform_data sdhc1_pdata __initconst = { - .init = mx27_3ds_sdhc1_init, - .exit = mx27_3ds_sdhc1_exit, -}; - -static void mx27_3ds_sdhc1_enable_level_translator(void) -{ - /* Turn on TXB0108 OE pin */ - gpio_request(SD1_EN_GPIO, "sd1_enable"); - gpio_direction_output(SD1_EN_GPIO, 1); -} - - -static int otg_phy_init(void) -{ - gpio_request(OTG_PHY_RESET_GPIO, "usb-otg-reset"); - gpio_direction_output(OTG_PHY_RESET_GPIO, 0); - mdelay(1); - gpio_set_value(OTG_PHY_RESET_GPIO, 1); - return 0; -} - -static int mx27_3ds_otg_init(struct platform_device *pdev) -{ - return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI); -} - -static struct mxc_usbh_platform_data otg_pdata __initdata = { - .init = mx27_3ds_otg_init, - .portsc = MXC_EHCI_MODE_ULPI, -}; - -static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { - .operating_mode = FSL_USB2_DR_DEVICE, - .phy_mode = FSL_USB2_PHY_ULPI, -}; - -static bool otg_mode_host __initdata; - -static int __init mx27_3ds_otg_mode(char *options) -{ - if (!strcmp(options, "host")) - otg_mode_host = true; - else if (!strcmp(options, "device")) - otg_mode_host = false; - else - pr_info("otg_mode neither \"host\" nor \"device\". " - "Defaulting to device\n"); - return 1; -} -__setup("otg_mode=", mx27_3ds_otg_mode); - -/* Regulators */ -static struct regulator_init_data gpo_init = { - .constraints = { - .boot_on = 1, - .always_on = 1, - } -}; - -static struct regulator_consumer_supply vmmc1_consumers[] = { - REGULATOR_SUPPLY("vcore", "spi0.0"), -}; - -static struct regulator_init_data vmmc1_init = { - .constraints = { - .min_uV = 2800000, - .max_uV = 2800000, - .apply_uV = 1, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(vmmc1_consumers), - .consumer_supplies = vmmc1_consumers, -}; - -static struct regulator_consumer_supply vgen_consumers[] = { - REGULATOR_SUPPLY("vdd", "spi0.0"), -}; - -static struct regulator_init_data vgen_init = { - .constraints = { - .min_uV = 1800000, - .max_uV = 1800000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, - }, - .num_consumer_supplies = ARRAY_SIZE(vgen_consumers), - .consumer_supplies = vgen_consumers, -}; - -static struct mc13xxx_regulator_init_data mx27_3ds_regulators[] = { - { - .id = MC13783_REG_VMMC1, - .init_data = &vmmc1_init, - }, { - .id = MC13783_REG_VGEN, - .init_data = &vgen_init, - }, { - .id = MC13783_REG_GPO1, /* Turn on 1.8V */ - .init_data = &gpo_init, - }, { - .id = MC13783_REG_GPO3, /* Turn on 3.3V */ - .init_data = &gpo_init, - }, -}; - -/* MC13783 */ -static struct mc13xxx_codec_platform_data mx27_3ds_codec = { - .dac_ssi_port = MC13783_SSI1_PORT, - .adc_ssi_port = MC13783_SSI1_PORT, -}; - -static struct mc13xxx_platform_data mc13783_pdata = { - .regulators = { - .regulators = mx27_3ds_regulators, - .num_regulators = ARRAY_SIZE(mx27_3ds_regulators), - - }, - .flags = MC13XXX_USE_TOUCHSCREEN | MC13XXX_USE_RTC | - MC13XXX_USE_CODEC, - .codec = &mx27_3ds_codec, -}; - -static struct imx_ssi_platform_data mx27_3ds_ssi_pdata = { - .flags = IMX_SSI_DMA | IMX_SSI_NET, -}; - -/* SPI */ -static struct gpiod_lookup_table mx27_spi1_gpiod_table = { - .dev_id = "imx27-cspi.0", /* Actual device name for spi1 */ - .table = { - /* - * The i.MX27 has the i.MX21 GPIO controller, the SPI1 CS GPIO - * SPI1_SS0 is numbered IMX_GPIO_NR(4, 28). - * - * This is in "bank 4" which is subtracted by one in the macro - * so this is actually bank 3 on "imx21-gpio.3". - */ - GPIO_LOOKUP_IDX("imx21-gpio.3", 28, "cs", 0, GPIO_ACTIVE_LOW), - { }, - }, -}; - -static struct gpiod_lookup_table mx27_spi2_gpiod_table = { - .dev_id = "imx27-cspi.1", /* Actual device name for spi2 */ - .table = { - /* - * The i.MX27 has the i.MX21 GPIO controller, the SPI2 CS GPIO - * SPI2_SS0 is numbered IMX_GPIO_NR(4, 21). - * - * This is in "bank 4" which is subtracted by one in the macro - * so this is actually bank 3 on "imx21-gpio.3". - */ - GPIO_LOOKUP_IDX("imx21-gpio.3", 21, "cs", 0, GPIO_ACTIVE_LOW), - { }, - }, -}; - -static struct imx_fb_videomode mx27_3ds_modes[] = { - { /* 480x640 @ 60 Hz */ - .mode = { - .name = "Epson-VGA", - .refresh = 60, - .xres = 480, - .yres = 640, - .pixclock = 41701, - .left_margin = 20, - .right_margin = 41, - .upper_margin = 10, - .lower_margin = 5, - .hsync_len = 20, - .vsync_len = 10, - .sync = FB_SYNC_OE_ACT_HIGH | - FB_SYNC_CLK_INVERT, - .vmode = FB_VMODE_NONINTERLACED, - .flag = 0, - }, - .bpp = 16, - .pcr = 0xFAC08B82, - }, -}; - -static const struct imx_fb_platform_data mx27_3ds_fb_data __initconst = { - .mode = mx27_3ds_modes, - .num_modes = ARRAY_SIZE(mx27_3ds_modes), - .pwmr = 0x00A903FF, - .lscr1 = 0x00120300, - .dmacr = 0x00020010, -}; - -/* LCD */ -static struct gpiod_lookup_table mx27_3ds_lcd_gpiod_table = { - .dev_id = "spi0.0", /* Bus 0 chipselect 0 */ - .table = { - /* - * The i.MX27 has the i.MX21 GPIO controller, the GPIOs - * numbered IMX_GPIO_NR(1, 3) and IMX_GPIO_NR(1, 31) - * are in "bank 1" which is subtracted by one in the macro - * so these are actually bank 0 on "imx21-gpio.0". - */ - GPIO_LOOKUP("imx21-gpio.0", 3, "reset", GPIO_ACTIVE_HIGH), - GPIO_LOOKUP("imx21-gpio.0", 31, "enable", GPIO_ACTIVE_HIGH), - { }, - }, -}; - -static struct spi_board_info mx27_3ds_spi_devs[] __initdata = { - { - .modalias = "mc13783", - .max_speed_hz = 1000000, - .bus_num = 1, - .chip_select = 0, /* SS0 */ - .platform_data = &mc13783_pdata, - /* irq number is run-time assigned */ - .mode = SPI_CS_HIGH, - }, { - .modalias = "l4f00242t03", - .max_speed_hz = 5000000, - .bus_num = 0, - .chip_select = 0, /* SS0 */ - }, -}; - -static const struct imxi2c_platform_data mx27_3ds_i2c0_data __initconst = { - .bitrate = 100000, -}; - -static void __init mx27pdk_init(void) -{ - imx27_soc_init(); - - mxc_gpio_setup_multiple_pins(mx27pdk_pins, ARRAY_SIZE(mx27pdk_pins), - "mx27pdk"); - imx27_add_imx_uart0(&uart_pdata); - imx27_add_fec(NULL); - imx27_add_imx_keypad(&mx27_3ds_keymap_data); - imx27_add_imx2_wdt(); - - imx27_add_spi_imx1(&mx27_spi2_gpiod_table); - imx27_add_spi_imx0(&mx27_spi1_gpiod_table); - - imx27_add_imx_i2c(0, &mx27_3ds_i2c0_data); - imx27_add_imx_fb(&mx27_3ds_fb_data); - - imx27_add_imx_ssi(0, &mx27_3ds_ssi_pdata); -} - -static void __init mx27pdk_late_init(void) -{ - mx27_3ds_sdhc1_enable_level_translator(); - imx27_add_mxc_mmc(0, &sdhc1_pdata); - - otg_phy_init(); - - if (otg_mode_host) { - otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | - ULPI_OTG_DRVVBUS_EXT); - - if (otg_pdata.otg) - imx27_add_mxc_ehci_otg(&otg_pdata); - } - - if (!otg_mode_host) - imx27_add_fsl_usb2_udc(&otg_device_pdata); - - gpiod_add_lookup_table(&mx27_3ds_lcd_gpiod_table); - mx27_3ds_spi_devs[0].irq = gpio_to_irq(PMIC_INT); - spi_register_board_info(mx27_3ds_spi_devs, - ARRAY_SIZE(mx27_3ds_spi_devs)); - - if (mxc_expio_init(MX27_CS5_BASE_ADDR, IMX_GPIO_NR(3, 28))) - pr_warn("Init of the debugboard failed, all devices on the debugboard are unusable.\n"); - - - imx_add_platform_device("imx_mc13783", 0, NULL, 0, NULL, 0); -} - -static void __init mx27pdk_timer_init(void) -{ - mx27_clocks_init(26000000); -} - -MACHINE_START(MX27_3DS, "Freescale MX27PDK") - /* maintainer: Freescale Semiconductor, Inc. */ - .atag_offset = 0x100, - .map_io = mx27_map_io, - .init_early = imx27_init_early, - .init_irq = mx27_init_irq, - .init_time = mx27pdk_timer_init, - .init_machine = mx27pdk_init, - .init_late = mx27pdk_late_init, - .restart = mxc_restart, -MACHINE_END diff --git a/arch/arm/mach-imx/mach-mx27ads.c b/arch/arm/mach-imx/mach-mx27ads.c deleted file mode 100644 index ba202f95bcdf..000000000000 --- a/arch/arm/mach-imx/mach-mx27ads.c +++ /dev/null @@ -1,407 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (C) 2000 Deep Blue Solutions Ltd - * Copyright (C) 2002 Shane Nay (shane@minirl.com) - * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved. - */ -#include <linux/gpio/driver.h> -/* Needed for gpio_to_irq() */ -#include <linux/gpio.h> -#include <linux/gpio/machine.h> -#include <linux/platform_device.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/map.h> -#include <linux/mtd/partitions.h> -#include <linux/mtd/physmap.h> -#include <linux/i2c.h> -#include <linux/irq.h> - -#include <linux/regulator/fixed.h> -#include <linux/regulator/machine.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> -#include <asm/mach/map.h> - -#include "common.h" -#include "devices-imx27.h" -#include "hardware.h" -#include "iomux-mx27.h" - -/* - * Base address of PBC controller, CS4 - */ -#define PBC_BASE_ADDRESS 0xf4300000 -#define PBC_REG_ADDR(offset) (void __force __iomem *) \ - (PBC_BASE_ADDRESS + (offset)) - -/* When the PBC address connection is fixed in h/w, defined as 1 */ -#define PBC_ADDR_SH 0 - -/* Offsets for the PBC Controller register */ -/* - * PBC Board version register offset - */ -#define PBC_VERSION_REG PBC_REG_ADDR(0x00000 >> PBC_ADDR_SH) -/* - * PBC Board control register 1 set address. - */ -#define PBC_BCTRL1_SET_REG PBC_REG_ADDR(0x00008 >> PBC_ADDR_SH) -/* - * PBC Board control register 1 clear address. - */ -#define PBC_BCTRL1_CLEAR_REG PBC_REG_ADDR(0x0000C >> PBC_ADDR_SH) - -/* PBC Board Control Register 1 bit definitions */ -#define PBC_BCTRL1_LCDON 0x0800 /* Enable the LCD */ - -/* to determine the correct external crystal reference */ -#define CKIH_27MHZ_BIT_SET (1 << 3) - -static const int mx27ads_pins[] __initconst = { - /* UART0 */ - PE12_PF_UART1_TXD, - PE13_PF_UART1_RXD, - PE14_PF_UART1_CTS, - PE15_PF_UART1_RTS, - /* UART1 */ - PE3_PF_UART2_CTS, - PE4_PF_UART2_RTS, - PE6_PF_UART2_TXD, - PE7_PF_UART2_RXD, - /* UART2 */ - PE8_PF_UART3_TXD, - PE9_PF_UART3_RXD, - PE10_PF_UART3_CTS, - PE11_PF_UART3_RTS, - /* UART3 */ - PB26_AF_UART4_RTS, - PB28_AF_UART4_TXD, - PB29_AF_UART4_CTS, - PB31_AF_UART4_RXD, - /* UART4 */ - PB18_AF_UART5_TXD, - PB19_AF_UART5_RXD, - PB20_AF_UART5_CTS, - PB21_AF_UART5_RTS, - /* UART5 */ - PB10_AF_UART6_TXD, - PB12_AF_UART6_CTS, - PB11_AF_UART6_RXD, - PB13_AF_UART6_RTS, - /* FEC */ - PD0_AIN_FEC_TXD0, - PD1_AIN_FEC_TXD1, - PD2_AIN_FEC_TXD2, - PD3_AIN_FEC_TXD3, - PD4_AOUT_FEC_RX_ER, - PD5_AOUT_FEC_RXD1, - PD6_AOUT_FEC_RXD2, - PD7_AOUT_FEC_RXD3, - PD8_AF_FEC_MDIO, - PD9_AIN_FEC_MDC, - PD10_AOUT_FEC_CRS, - PD11_AOUT_FEC_TX_CLK, - PD12_AOUT_FEC_RXD0, - PD13_AOUT_FEC_RX_DV, - PD14_AOUT_FEC_RX_CLK, - PD15_AOUT_FEC_COL, - PD16_AIN_FEC_TX_ER, - PF23_AIN_FEC_TX_EN, - /* I2C2 */ - PC5_PF_I2C2_SDA, - PC6_PF_I2C2_SCL, - /* FB */ - PA5_PF_LSCLK, - PA6_PF_LD0, - PA7_PF_LD1, - PA8_PF_LD2, - PA9_PF_LD3, - PA10_PF_LD4, - PA11_PF_LD5, - PA12_PF_LD6, - PA13_PF_LD7, - PA14_PF_LD8, - PA15_PF_LD9, - PA16_PF_LD10, - PA17_PF_LD11, - PA18_PF_LD12, - PA19_PF_LD13, - PA20_PF_LD14, - PA21_PF_LD15, - PA22_PF_LD16, - PA23_PF_LD17, - PA24_PF_REV, - PA25_PF_CLS, - PA26_PF_PS, - PA27_PF_SPL_SPR, - PA28_PF_HSYNC, - PA29_PF_VSYNC, - PA30_PF_CONTRAST, - PA31_PF_OE_ACD, - /* OWIRE */ - PE16_AF_OWIRE, - /* SDHC1*/ - PE18_PF_SD1_D0, - PE19_PF_SD1_D1, - PE20_PF_SD1_D2, - PE21_PF_SD1_D3, - PE22_PF_SD1_CMD, - PE23_PF_SD1_CLK, - /* SDHC2*/ - PB4_PF_SD2_D0, - PB5_PF_SD2_D1, - PB6_PF_SD2_D2, - PB7_PF_SD2_D3, - PB8_PF_SD2_CMD, - PB9_PF_SD2_CLK, -}; - -static const struct mxc_nand_platform_data -mx27ads_nand_board_info __initconst = { - .width = 1, - .hw_ecc = 1, -}; - -/* ADS's NOR flash */ -static struct physmap_flash_data mx27ads_flash_data = { - .width = 2, -}; - -static struct resource mx27ads_flash_resource = { - .start = 0xc0000000, - .end = 0xc0000000 + 0x02000000 - 1, - .flags = IORESOURCE_MEM, - -}; - -static struct platform_device mx27ads_nor_mtd_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &mx27ads_flash_data, - }, - .num_resources = 1, - .resource = &mx27ads_flash_resource, -}; - -static const struct imxi2c_platform_data mx27ads_i2c1_data __initconst = { - .bitrate = 100000, -}; - -static struct i2c_board_info mx27ads_i2c_devices[] = { -}; - -static void vgpio_set(struct gpio_chip *chip, unsigned offset, int value) -{ - if (value) - imx_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_SET_REG); - else - imx_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_CLEAR_REG); -} - -static int vgpio_dir_out(struct gpio_chip *chip, unsigned offset, int value) -{ - return 0; -} - -#define MX27ADS_LCD_GPIO (6 * 32) - -static struct regulator_consumer_supply mx27ads_lcd_regulator_consumer = - REGULATOR_SUPPLY("lcd", "imx-fb.0"); - -static struct regulator_init_data mx27ads_lcd_regulator_init_data = { - .constraints = { - .valid_ops_mask = REGULATOR_CHANGE_STATUS, -}, - .consumer_supplies = &mx27ads_lcd_regulator_consumer, - .num_consumer_supplies = 1, -}; - -static struct fixed_voltage_config mx27ads_lcd_regulator_pdata = { - .supply_name = "LCD", - .microvolts = 3300000, - .init_data = &mx27ads_lcd_regulator_init_data, -}; - -static struct gpiod_lookup_table mx27ads_lcd_regulator_gpiod_table = { - .dev_id = "reg-fixed-voltage.0", /* Let's hope ID 0 is what we get */ - .table = { - GPIO_LOOKUP("LCD", 0, NULL, GPIO_ACTIVE_LOW), - { }, - }, -}; - -static void __init mx27ads_regulator_init(void) -{ - struct gpio_chip *vchip; - - vchip = kzalloc(sizeof(*vchip), GFP_KERNEL); - vchip->owner = THIS_MODULE; - vchip->label = "LCD"; - vchip->base = MX27ADS_LCD_GPIO; - vchip->ngpio = 1; - vchip->direction_output = vgpio_dir_out; - vchip->set = vgpio_set; - gpiochip_add_data(vchip, NULL); - - gpiod_add_lookup_table(&mx27ads_lcd_regulator_gpiod_table); - - platform_device_register_data(NULL, "reg-fixed-voltage", - PLATFORM_DEVID_AUTO, - &mx27ads_lcd_regulator_pdata, - sizeof(mx27ads_lcd_regulator_pdata)); -} - -static struct imx_fb_videomode mx27ads_modes[] = { - { - .mode = { - .name = "Sharp-LQ035Q7", - .refresh = 60, - .xres = 240, - .yres = 320, - .pixclock = 188679, /* in ps (5.3MHz) */ - .hsync_len = 1, - .left_margin = 9, - .right_margin = 16, - .vsync_len = 1, - .upper_margin = 7, - .lower_margin = 9, - }, - .bpp = 16, - .pcr = 0xFB008BC0, - }, -}; - -static const struct imx_fb_platform_data mx27ads_fb_data __initconst = { - .mode = mx27ads_modes, - .num_modes = ARRAY_SIZE(mx27ads_modes), - - /* - * - HSYNC active high - * - VSYNC active high - * - clk notenabled while idle - * - clock inverted - * - data not inverted - * - data enable low active - * - enable sharp mode - */ - .pwmr = 0x00A903FF, - .lscr1 = 0x00120300, - .dmacr = 0x00020010, -}; - -static int mx27ads_sdhc1_init(struct device *dev, irq_handler_t detect_irq, - void *data) -{ - return request_irq(gpio_to_irq(IMX_GPIO_NR(5, 21)), detect_irq, - IRQF_TRIGGER_RISING, "sdhc1-card-detect", data); -} - -static int mx27ads_sdhc2_init(struct device *dev, irq_handler_t detect_irq, - void *data) -{ - return request_irq(gpio_to_irq(IMX_GPIO_NR(2, 7)), detect_irq, - IRQF_TRIGGER_RISING, "sdhc2-card-detect", data); -} - -static void mx27ads_sdhc1_exit(struct device *dev, void *data) -{ - free_irq(gpio_to_irq(IMX_GPIO_NR(5, 21)), data); -} - -static void mx27ads_sdhc2_exit(struct device *dev, void *data) -{ - free_irq(gpio_to_irq(IMX_GPIO_NR(2, 7)), data); -} - -static const struct imxmmc_platform_data sdhc1_pdata __initconst = { - .init = mx27ads_sdhc1_init, - .exit = mx27ads_sdhc1_exit, -}; - -static const struct imxmmc_platform_data sdhc2_pdata __initconst = { - .init = mx27ads_sdhc2_init, - .exit = mx27ads_sdhc2_exit, -}; - -static struct platform_device *platform_devices[] __initdata = { - &mx27ads_nor_mtd_device, -}; - -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static void __init mx27ads_board_init(void) -{ - imx27_soc_init(); - - mxc_gpio_setup_multiple_pins(mx27ads_pins, ARRAY_SIZE(mx27ads_pins), - "mx27ads"); - - imx27_add_imx_uart0(&uart_pdata); - imx27_add_imx_uart1(&uart_pdata); - imx27_add_imx_uart2(&uart_pdata); - imx27_add_imx_uart3(&uart_pdata); - imx27_add_imx_uart4(&uart_pdata); - imx27_add_imx_uart5(&uart_pdata); - imx27_add_mxc_nand(&mx27ads_nand_board_info); - - /* only the i2c master 1 is used on this CPU card */ - i2c_register_board_info(1, mx27ads_i2c_devices, - ARRAY_SIZE(mx27ads_i2c_devices)); - imx27_add_imx_i2c(1, &mx27ads_i2c1_data); - imx27_add_imx_fb(&mx27ads_fb_data); - - imx27_add_fec(NULL); - imx27_add_mxc_w1(); -} - -static void __init mx27ads_late_init(void) -{ - mx27ads_regulator_init(); - - imx27_add_mxc_mmc(0, &sdhc1_pdata); - imx27_add_mxc_mmc(1, &sdhc2_pdata); - - platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); -} - -static void __init mx27ads_timer_init(void) -{ - unsigned long fref = 26000000; - - if ((imx_readw(PBC_VERSION_REG) & CKIH_27MHZ_BIT_SET) == 0) - fref = 27000000; - - mx27_clocks_init(fref); -} - -static struct map_desc mx27ads_io_desc[] __initdata = { - { - .virtual = PBC_BASE_ADDRESS, - .pfn = __phys_to_pfn(MX27_CS4_BASE_ADDR), - .length = SZ_1M, - .type = MT_DEVICE, - }, -}; - -static void __init mx27ads_map_io(void) -{ - mx27_map_io(); - iotable_init(mx27ads_io_desc, ARRAY_SIZE(mx27ads_io_desc)); -} - -MACHINE_START(MX27ADS, "Freescale i.MX27ADS") - /* maintainer: Freescale Semiconductor, Inc. */ - .atag_offset = 0x100, - .map_io = mx27ads_map_io, - .init_early = imx27_init_early, - .init_irq = mx27_init_irq, - .init_time = mx27ads_timer_init, - .init_machine = mx27ads_board_init, - .init_late = mx27ads_late_init, - .restart = mxc_restart, -MACHINE_END diff --git a/arch/arm/mach-imx/mach-mx31_3ds.c b/arch/arm/mach-imx/mach-mx31_3ds.c deleted file mode 100644 index 23e63d3b4c6a..000000000000 --- a/arch/arm/mach-imx/mach-mx31_3ds.c +++ /dev/null @@ -1,615 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -#include <linux/delay.h> -#include <linux/dma-mapping.h> -#include <linux/types.h> -#include <linux/init.h> -#include <linux/clk.h> -#include <linux/irq.h> -#include <linux/gpio.h> -#include <linux/gpio/machine.h> -#include <linux/platform_device.h> -#include <linux/mfd/mc13783.h> -#include <linux/spi/spi.h> -#include <linux/regulator/machine.h> -#include <linux/usb/otg.h> -#include <linux/usb/ulpi.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> -#include <asm/memory.h> -#include <asm/mach/map.h> - -#include "3ds_debugboard.h" -#include "common.h" -#include "devices-imx31.h" -#include "ehci.h" -#include "hardware.h" -#include "iomux-mx3.h" -#include "ulpi.h" - -static int mx31_3ds_pins[] = { - /* UART1 */ - MX31_PIN_CTS1__CTS1, - MX31_PIN_RTS1__RTS1, - MX31_PIN_TXD1__TXD1, - MX31_PIN_RXD1__RXD1, - IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO), - /*SPI0*/ - IOMUX_MODE(MX31_PIN_DSR_DCE1, IOMUX_CONFIG_ALT1), - IOMUX_MODE(MX31_PIN_RI_DCE1, IOMUX_CONFIG_ALT1), - /* SPI 1 */ - MX31_PIN_CSPI2_SCLK__SCLK, - MX31_PIN_CSPI2_MOSI__MOSI, - MX31_PIN_CSPI2_MISO__MISO, - MX31_PIN_CSPI2_SPI_RDY__SPI_RDY, - MX31_PIN_CSPI2_SS0__SS0, - MX31_PIN_CSPI2_SS2__SS2, /*CS for MC13783 */ - /* MC13783 IRQ */ - IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO), - /* USB OTG reset */ - IOMUX_MODE(MX31_PIN_USB_PWR, IOMUX_CONFIG_GPIO), - /* USB OTG */ - MX31_PIN_USBOTG_DATA0__USBOTG_DATA0, - MX31_PIN_USBOTG_DATA1__USBOTG_DATA1, - MX31_PIN_USBOTG_DATA2__USBOTG_DATA2, - MX31_PIN_USBOTG_DATA3__USBOTG_DATA3, - MX31_PIN_USBOTG_DATA4__USBOTG_DATA4, - MX31_PIN_USBOTG_DATA5__USBOTG_DATA5, - MX31_PIN_USBOTG_DATA6__USBOTG_DATA6, - MX31_PIN_USBOTG_DATA7__USBOTG_DATA7, - MX31_PIN_USBOTG_CLK__USBOTG_CLK, - MX31_PIN_USBOTG_DIR__USBOTG_DIR, - MX31_PIN_USBOTG_NXT__USBOTG_NXT, - MX31_PIN_USBOTG_STP__USBOTG_STP, - /*Keyboard*/ - MX31_PIN_KEY_ROW0_KEY_ROW0, - MX31_PIN_KEY_ROW1_KEY_ROW1, - MX31_PIN_KEY_ROW2_KEY_ROW2, - MX31_PIN_KEY_COL0_KEY_COL0, - MX31_PIN_KEY_COL1_KEY_COL1, - MX31_PIN_KEY_COL2_KEY_COL2, - MX31_PIN_KEY_COL3_KEY_COL3, - /* USB Host 2 */ - IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_PC_VS2, IOMUX_CONFIG_ALT1), - IOMUX_MODE(MX31_PIN_PC_BVD1, IOMUX_CONFIG_ALT1), - IOMUX_MODE(MX31_PIN_PC_BVD2, IOMUX_CONFIG_ALT1), - IOMUX_MODE(MX31_PIN_PC_RST, IOMUX_CONFIG_ALT1), - IOMUX_MODE(MX31_PIN_IOIS16, IOMUX_CONFIG_ALT1), - IOMUX_MODE(MX31_PIN_PC_RW_B, IOMUX_CONFIG_ALT1), - /* USB Host2 reset */ - IOMUX_MODE(MX31_PIN_USB_BYP, IOMUX_CONFIG_GPIO), - /* I2C1 */ - MX31_PIN_I2C_CLK__I2C1_SCL, - MX31_PIN_I2C_DAT__I2C1_SDA, - /* SDHC1 */ - MX31_PIN_SD1_DATA3__SD1_DATA3, - MX31_PIN_SD1_DATA2__SD1_DATA2, - MX31_PIN_SD1_DATA1__SD1_DATA1, - MX31_PIN_SD1_DATA0__SD1_DATA0, - MX31_PIN_SD1_CLK__SD1_CLK, - MX31_PIN_SD1_CMD__SD1_CMD, - MX31_PIN_GPIO3_1__GPIO3_1, /* Card detect */ - MX31_PIN_GPIO3_0__GPIO3_0, /* OE */ - /* Framebuffer */ - MX31_PIN_LD0__LD0, - MX31_PIN_LD1__LD1, - MX31_PIN_LD2__LD2, - MX31_PIN_LD3__LD3, - MX31_PIN_LD4__LD4, - MX31_PIN_LD5__LD5, - MX31_PIN_LD6__LD6, - MX31_PIN_LD7__LD7, - MX31_PIN_LD8__LD8, - MX31_PIN_LD9__LD9, - MX31_PIN_LD10__LD10, - MX31_PIN_LD11__LD11, - MX31_PIN_LD12__LD12, - MX31_PIN_LD13__LD13, - MX31_PIN_LD14__LD14, - MX31_PIN_LD15__LD15, - MX31_PIN_LD16__LD16, - MX31_PIN_LD17__LD17, - MX31_PIN_VSYNC3__VSYNC3, - MX31_PIN_HSYNC__HSYNC, - MX31_PIN_FPSHIFT__FPSHIFT, - MX31_PIN_CONTRAST__CONTRAST, - /* SSI */ - MX31_PIN_STXD4__STXD4, - MX31_PIN_SRXD4__SRXD4, - MX31_PIN_SCK4__SCK4, - MX31_PIN_SFS4__SFS4, -}; - -/* - * FB support - */ -static const struct fb_videomode fb_modedb[] = { - { /* 480x640 @ 60 Hz */ - .name = "Epson-VGA", - .refresh = 60, - .xres = 480, - .yres = 640, - .pixclock = 41701, - .left_margin = 20, - .right_margin = 41, - .upper_margin = 10, - .lower_margin = 5, - .hsync_len = 20, - .vsync_len = 10, - .sync = FB_SYNC_OE_ACT_HIGH | FB_SYNC_CLK_INVERT, - .vmode = FB_VMODE_NONINTERLACED, - .flag = 0, - }, -}; - -static struct mx3fb_platform_data mx3fb_pdata __initdata = { - .name = "Epson-VGA", - .mode = fb_modedb, - .num_modes = ARRAY_SIZE(fb_modedb), -}; - -/* LCD */ -static struct gpiod_lookup_table mx31_3ds_lcd_gpiod_table = { - .dev_id = "spi0.2", /* Bus 0 chipselect 2 */ - .table = { - /* - * "reset" has IOMUX_TO_GPIO(IOMUX_PIN(88, 28)). - * The macro only shifts 88 to bits 9..16 and then - * mask it and shift it back. The GPIO number is 88. - * 88 is 2*32+24 - */ - GPIO_LOOKUP("imx31-gpio.2", 24, "reset", GPIO_ACTIVE_HIGH), - /* - * Same reasoning as above for - * IOMUX_TO_GPIO(IOMUX_PIN(89, 27), pin 89 is 2*32+25. - */ - GPIO_LOOKUP("imx31-gpio.2", 25, "enable", GPIO_ACTIVE_HIGH), - { }, - }, -}; - -/* - * Support for SD card slot in personality board - */ -#define MX31_3DS_GPIO_SDHC1_CD IOMUX_TO_GPIO(MX31_PIN_GPIO3_1) -#define MX31_3DS_GPIO_SDHC1_BE IOMUX_TO_GPIO(MX31_PIN_GPIO3_0) - -static struct gpio mx31_3ds_sdhc1_gpios[] = { - { MX31_3DS_GPIO_SDHC1_CD, GPIOF_IN, "sdhc1-card-detect" }, - { MX31_3DS_GPIO_SDHC1_BE, GPIOF_OUT_INIT_LOW, "sdhc1-bus-en" }, -}; - -static int mx31_3ds_sdhc1_init(struct device *dev, - irq_handler_t detect_irq, - void *data) -{ - int ret; - - ret = gpio_request_array(mx31_3ds_sdhc1_gpios, - ARRAY_SIZE(mx31_3ds_sdhc1_gpios)); - if (ret) { - pr_warn("Unable to request the SD/MMC GPIOs.\n"); - return ret; - } - - ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)), - detect_irq, - IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, - "sdhc1-detect", data); - if (ret) { - pr_warn("Unable to request the SD/MMC card-detect IRQ.\n"); - goto gpio_free; - } - - return 0; - -gpio_free: - gpio_free_array(mx31_3ds_sdhc1_gpios, - ARRAY_SIZE(mx31_3ds_sdhc1_gpios)); - return ret; -} - -static void mx31_3ds_sdhc1_exit(struct device *dev, void *data) -{ - free_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)), data); - gpio_free_array(mx31_3ds_sdhc1_gpios, - ARRAY_SIZE(mx31_3ds_sdhc1_gpios)); -} - -static void mx31_3ds_sdhc1_setpower(struct device *dev, unsigned int vdd) -{ - /* - * While the voltage stuff is done by the driver, activate the - * Buffer Enable Pin only if there is a card in slot to fix the card - * voltage issue caused by bi-directional chip TXB0108 on 3Stack. - * Done here because at this stage we have for sure a debounced value - * of the presence of the card, showed by the value of vdd. - * 7 == ilog2(MMC_VDD_165_195) - */ - if (vdd > 7) - gpio_set_value(MX31_3DS_GPIO_SDHC1_BE, 1); - else - gpio_set_value(MX31_3DS_GPIO_SDHC1_BE, 0); -} - -static struct imxmmc_platform_data sdhc1_pdata = { - .init = mx31_3ds_sdhc1_init, - .exit = mx31_3ds_sdhc1_exit, - .setpower = mx31_3ds_sdhc1_setpower, -}; - -/* - * Matrix keyboard - */ - -static const uint32_t mx31_3ds_keymap[] = { - KEY(0, 0, KEY_UP), - KEY(0, 1, KEY_DOWN), - KEY(1, 0, KEY_RIGHT), - KEY(1, 1, KEY_LEFT), - KEY(1, 2, KEY_ENTER), - KEY(2, 0, KEY_F6), - KEY(2, 1, KEY_F8), - KEY(2, 2, KEY_F9), - KEY(2, 3, KEY_F10), -}; - -static const struct matrix_keymap_data mx31_3ds_keymap_data __initconst = { - .keymap = mx31_3ds_keymap, - .keymap_size = ARRAY_SIZE(mx31_3ds_keymap), -}; - -/* Regulators */ -static struct regulator_init_data pwgtx_init = { - .constraints = { - .boot_on = 1, - .always_on = 1, - }, -}; - -static struct regulator_init_data gpo_init = { - .constraints = { - .boot_on = 1, - .always_on = 1, - } -}; - -static struct regulator_consumer_supply vmmc2_consumers[] = { - REGULATOR_SUPPLY("vmmc", "imx31-mmc.0"), -}; - -static struct regulator_init_data vmmc2_init = { - .constraints = { - .min_uV = 3000000, - .max_uV = 3000000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(vmmc2_consumers), - .consumer_supplies = vmmc2_consumers, -}; - -static struct regulator_consumer_supply vmmc1_consumers[] = { - REGULATOR_SUPPLY("vcore", "spi0.0"), -}; - -static struct regulator_init_data vmmc1_init = { - .constraints = { - .min_uV = 2800000, - .max_uV = 2800000, - .apply_uV = 1, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(vmmc1_consumers), - .consumer_supplies = vmmc1_consumers, -}; - -static struct regulator_consumer_supply vgen_consumers[] = { - REGULATOR_SUPPLY("vdd", "spi0.0"), -}; - -static struct regulator_init_data vgen_init = { - .constraints = { - .min_uV = 1800000, - .max_uV = 1800000, - .apply_uV = 1, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(vgen_consumers), - .consumer_supplies = vgen_consumers, -}; - -static struct mc13xxx_regulator_init_data mx31_3ds_regulators[] = { - { - .id = MC13783_REG_PWGT1SPI, /* Power Gate for ARM core. */ - .init_data = &pwgtx_init, - }, { - .id = MC13783_REG_PWGT2SPI, /* Power Gate for L2 Cache. */ - .init_data = &pwgtx_init, - }, { - - .id = MC13783_REG_GPO1, /* Turn on 1.8V */ - .init_data = &gpo_init, - }, { - .id = MC13783_REG_GPO3, /* Turn on 3.3V */ - .init_data = &gpo_init, - }, { - .id = MC13783_REG_VMMC2, /* Power MMC/SD, WiFi/Bluetooth. */ - .init_data = &vmmc2_init, - }, { - .id = MC13783_REG_VMMC1, /* Power LCD, CMOS, FM, GPS, Accel. */ - .init_data = &vmmc1_init, - }, { - .id = MC13783_REG_VGEN, /* Power LCD */ - .init_data = &vgen_init, - }, -}; - -/* MC13783 */ -static struct mc13xxx_codec_platform_data mx31_3ds_codec = { - .dac_ssi_port = MC13783_SSI1_PORT, - .adc_ssi_port = MC13783_SSI1_PORT, -}; - -static struct mc13xxx_platform_data mc13783_pdata = { - .regulators = { - .regulators = mx31_3ds_regulators, - .num_regulators = ARRAY_SIZE(mx31_3ds_regulators), - }, - .codec = &mx31_3ds_codec, - .flags = MC13XXX_USE_TOUCHSCREEN | MC13XXX_USE_RTC | MC13XXX_USE_CODEC, - -}; - -static struct imx_ssi_platform_data mx31_3ds_ssi_pdata = { - .flags = IMX_SSI_DMA | IMX_SSI_NET, -}; - -static struct spi_board_info mx31_3ds_spi_devs[] __initdata = { - { - .modalias = "mc13783", - .max_speed_hz = 1000000, - .bus_num = 1, - .chip_select = 2, /* SS2 */ - .platform_data = &mc13783_pdata, - /* irq number is run-time assigned */ - .mode = SPI_CS_HIGH, - }, { - .modalias = "l4f00242t03", - .max_speed_hz = 5000000, - .bus_num = 0, - .chip_select = 2, /* SS2 */ - }, -}; - -/* - * NAND Flash - */ -static const struct mxc_nand_platform_data -mx31_3ds_nand_board_info __initconst = { - .width = 1, - .hw_ecc = 1, -#ifdef CONFIG_MACH_MX31_3DS_MXC_NAND_USE_BBT - .flash_bbt = 1, -#endif -}; - -/* - * USB OTG - */ - -#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ - PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) - -#define USBOTG_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_PWR) -#define USBH2_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_BYP) - -static int mx31_3ds_usbotg_init(void) -{ - int err; - - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG); - - err = gpio_request(USBOTG_RST_B, "otgusb-reset"); - if (err) { - pr_err("Failed to request the USB OTG reset gpio\n"); - return err; - } - - err = gpio_direction_output(USBOTG_RST_B, 0); - if (err) { - pr_err("Failed to drive the USB OTG reset gpio\n"); - goto usbotg_free_reset; - } - - mdelay(1); - gpio_set_value(USBOTG_RST_B, 1); - return 0; - -usbotg_free_reset: - gpio_free(USBOTG_RST_B); - return err; -} - -static int mx31_3ds_otg_init(struct platform_device *pdev) -{ - return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED); -} - -static int mx31_3ds_host2_init(struct platform_device *pdev) -{ - int err; - - mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_PC_VS2, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_PC_BVD1, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_PC_BVD2, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_PC_RST, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_IOIS16, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_PC_RW_B, USB_PAD_CFG); - - err = gpio_request(USBH2_RST_B, "usbh2-reset"); - if (err) { - pr_err("Failed to request the USB Host 2 reset gpio\n"); - return err; - } - - err = gpio_direction_output(USBH2_RST_B, 0); - if (err) { - pr_err("Failed to drive the USB Host 2 reset gpio\n"); - goto usbotg_free_reset; - } - - mdelay(1); - gpio_set_value(USBH2_RST_B, 1); - - mdelay(10); - - return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED); - -usbotg_free_reset: - gpio_free(USBH2_RST_B); - return err; -} - -static struct mxc_usbh_platform_data otg_pdata __initdata = { - .init = mx31_3ds_otg_init, - .portsc = MXC_EHCI_MODE_ULPI, -}; - -static struct mxc_usbh_platform_data usbh2_pdata __initdata = { - .init = mx31_3ds_host2_init, - .portsc = MXC_EHCI_MODE_ULPI, -}; - -static const struct fsl_usb2_platform_data usbotg_pdata __initconst = { - .operating_mode = FSL_USB2_DR_DEVICE, - .phy_mode = FSL_USB2_PHY_ULPI, -}; - -static bool otg_mode_host __initdata; - -static int __init mx31_3ds_otg_mode(char *options) -{ - if (!strcmp(options, "host")) - otg_mode_host = true; - else if (!strcmp(options, "device")) - otg_mode_host = false; - else - pr_info("otg_mode neither \"host\" nor \"device\". " - "Defaulting to device\n"); - return 1; -} -__setup("otg_mode=", mx31_3ds_otg_mode); - -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static const struct imxi2c_platform_data mx31_3ds_i2c0_data __initconst = { - .bitrate = 100000, -}; - -static void __init mx31_3ds_init(void) -{ - imx31_soc_init(); - - /* Configure SPI1 IOMUX */ - mxc_iomux_set_gpr(MUX_PGP_CSPI_BB, true); - - mxc_iomux_setup_multiple_pins(mx31_3ds_pins, ARRAY_SIZE(mx31_3ds_pins), - "mx31_3ds"); - - imx31_add_imx_uart0(&uart_pdata); - imx31_add_mxc_nand(&mx31_3ds_nand_board_info); - - imx31_add_spi_imx1(NULL); - - imx31_add_imx_keypad(&mx31_3ds_keymap_data); - - imx31_add_imx2_wdt(); - imx31_add_imx_i2c0(&mx31_3ds_i2c0_data); - - imx31_add_spi_imx0(NULL); - imx31_add_ipu_core(); - imx31_add_mx3_sdc_fb(&mx3fb_pdata); - - imx31_add_imx_ssi(0, &mx31_3ds_ssi_pdata); - - imx_add_platform_device("imx_mc13783", 0, NULL, 0, NULL, 0); -} - -static void __init mx31_3ds_late(void) -{ - gpiod_add_lookup_table(&mx31_3ds_lcd_gpiod_table); - mx31_3ds_spi_devs[0].irq = gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3)); - spi_register_board_info(mx31_3ds_spi_devs, - ARRAY_SIZE(mx31_3ds_spi_devs)); - - mx31_3ds_usbotg_init(); - if (otg_mode_host) { - otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | - ULPI_OTG_DRVVBUS_EXT); - if (otg_pdata.otg) - imx31_add_mxc_ehci_otg(&otg_pdata); - } - usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | - ULPI_OTG_DRVVBUS_EXT); - if (usbh2_pdata.otg) - imx31_add_mxc_ehci_hs(2, &usbh2_pdata); - - if (!otg_mode_host) - imx31_add_fsl_usb2_udc(&usbotg_pdata); - - if (mxc_expio_init(MX31_CS5_BASE_ADDR, IOMUX_TO_GPIO(MX31_PIN_GPIO1_1))) - printk(KERN_WARNING "Init of the debug board failed, all " - "devices on the debug board are unusable.\n"); - - imx31_add_mxc_mmc(0, &sdhc1_pdata); -} - -static void __init mx31_3ds_timer_init(void) -{ - mx31_clocks_init(26000000); -} - -MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)") - /* Maintainer: Freescale Semiconductor, Inc. */ - .atag_offset = 0x100, - .map_io = mx31_map_io, - .init_early = imx31_init_early, - .init_irq = mx31_init_irq, - .init_time = mx31_3ds_timer_init, - .init_machine = mx31_3ds_init, - .init_late = mx31_3ds_late, - .restart = mxc_restart, -MACHINE_END diff --git a/arch/arm/mach-imx/mach-mx31ads.c b/arch/arm/mach-imx/mach-mx31ads.c deleted file mode 100644 index 49783385bccf..000000000000 --- a/arch/arm/mach-imx/mach-mx31ads.c +++ /dev/null @@ -1,579 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (C) 2000 Deep Blue Solutions Ltd - * Copyright (C) 2002 Shane Nay (shane@minirl.com) - * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -#include <linux/types.h> -#include <linux/init.h> -#include <linux/clk.h> -#include <linux/serial_8250.h> -#include <linux/gpio.h> -#include <linux/i2c.h> -#include <linux/irq.h> -#include <linux/irqdomain.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> -#include <asm/memory.h> -#include <asm/mach/map.h> - -#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1 -#include <linux/mfd/wm8350/audio.h> -#include <linux/mfd/wm8350/core.h> -#include <linux/mfd/wm8350/pmic.h> -#endif - -#include "common.h" -#include "devices-imx31.h" -#include "hardware.h" -#include "iomux-mx3.h" - -/* Base address of PBC controller */ -#define PBC_BASE_ADDRESS MX31_CS4_BASE_ADDR_VIRT - -/* PBC Board interrupt status register */ -#define PBC_INTSTATUS 0x000016 - -/* PBC Board interrupt current status register */ -#define PBC_INTCURR_STATUS 0x000018 - -/* PBC Interrupt mask register set address */ -#define PBC_INTMASK_SET 0x00001A - -/* PBC Interrupt mask register clear address */ -#define PBC_INTMASK_CLEAR 0x00001C - -/* External UART A */ -#define PBC_SC16C652_UARTA 0x010000 - -/* External UART B */ -#define PBC_SC16C652_UARTB 0x010010 - -#define PBC_INTSTATUS_REG (PBC_INTSTATUS + PBC_BASE_ADDRESS) -#define PBC_INTMASK_SET_REG (PBC_INTMASK_SET + PBC_BASE_ADDRESS) -#define PBC_INTMASK_CLEAR_REG (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS) - -#define EXPIO_INT_XUART_INTA 10 -#define EXPIO_INT_XUART_INTB 11 - -#define MXC_MAX_EXP_IO_LINES 16 - -/* CS8900 */ -#define EXPIO_INT_ENET_INT 8 -#define CS4_CS8900_MMIO_START 0x20000 - -static struct irq_domain *domain; - -/* - * The serial port definition structure. - */ -static struct plat_serial8250_port serial_platform_data[] = { - { - .membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTA), - .mapbase = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTA), - .uartclk = 14745600, - .regshift = 0, - .iotype = UPIO_MEM, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ, - }, { - .membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTB), - .mapbase = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTB), - .uartclk = 14745600, - .regshift = 0, - .iotype = UPIO_MEM, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ, - }, - {}, -}; - -static struct platform_device serial_device = { - .name = "serial8250", - .id = 0, - .dev = { - .platform_data = serial_platform_data, - }, -}; - -static struct resource mx31ads_cs8900_resources[] __initdata = { - DEFINE_RES_MEM(MX31_CS4_BASE_ADDR + CS4_CS8900_MMIO_START, SZ_64K), - DEFINE_RES_IRQ(-1), -}; - -static const struct platform_device_info mx31ads_cs8900_devinfo __initconst = { - .name = "cs89x0", - .id = 0, - .res = mx31ads_cs8900_resources, - .num_res = ARRAY_SIZE(mx31ads_cs8900_resources), -}; - -static int __init mxc_init_extuart(void) -{ - serial_platform_data[0].irq = irq_find_mapping(domain, - EXPIO_INT_XUART_INTA); - serial_platform_data[1].irq = irq_find_mapping(domain, - EXPIO_INT_XUART_INTB); - return platform_device_register(&serial_device); -} - -static void __init mxc_init_ext_ethernet(void) -{ - mx31ads_cs8900_resources[1].start = - irq_find_mapping(domain, EXPIO_INT_ENET_INT); - mx31ads_cs8900_resources[1].end = - irq_find_mapping(domain, EXPIO_INT_ENET_INT); - platform_device_register_full( - (struct platform_device_info *)&mx31ads_cs8900_devinfo); -} - -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static unsigned int uart_pins[] = { - MX31_PIN_CTS1__CTS1, - MX31_PIN_RTS1__RTS1, - MX31_PIN_TXD1__TXD1, - MX31_PIN_RXD1__RXD1 -}; - -static inline void mxc_init_imx_uart(void) -{ - mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins), "uart-0"); - imx31_add_imx_uart0(&uart_pdata); -} - -static void mx31ads_expio_irq_handler(struct irq_desc *desc) -{ - u32 imr_val; - u32 int_valid; - u32 expio_irq; - - imr_val = imx_readw(PBC_INTMASK_SET_REG); - int_valid = imx_readw(PBC_INTSTATUS_REG) & imr_val; - - expio_irq = 0; - for (; int_valid != 0; int_valid >>= 1, expio_irq++) { - if ((int_valid & 1) == 0) - continue; - - generic_handle_irq(irq_find_mapping(domain, expio_irq)); - } -} - -/* - * Disable an expio pin's interrupt by setting the bit in the imr. - * @param d an expio virtual irq description - */ -static void expio_mask_irq(struct irq_data *d) -{ - u32 expio = d->hwirq; - /* mask the interrupt */ - imx_writew(1 << expio, PBC_INTMASK_CLEAR_REG); - imx_readw(PBC_INTMASK_CLEAR_REG); -} - -/* - * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr. - * @param d an expio virtual irq description - */ -static void expio_ack_irq(struct irq_data *d) -{ - u32 expio = d->hwirq; - /* clear the interrupt status */ - imx_writew(1 << expio, PBC_INTSTATUS_REG); -} - -/* - * Enable a expio pin's interrupt by clearing the bit in the imr. - * @param d an expio virtual irq description - */ -static void expio_unmask_irq(struct irq_data *d) -{ - u32 expio = d->hwirq; - /* unmask the interrupt */ - imx_writew(1 << expio, PBC_INTMASK_SET_REG); -} - -static struct irq_chip expio_irq_chip = { - .name = "EXPIO(CPLD)", - .irq_ack = expio_ack_irq, - .irq_mask = expio_mask_irq, - .irq_unmask = expio_unmask_irq, -}; - -static void __init mx31ads_init_expio(void) -{ - int irq_base; - int i, irq; - - printk(KERN_INFO "MX31ADS EXPIO(CPLD) hardware\n"); - - /* - * Configure INT line as GPIO input - */ - mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_GPIO1_4, IOMUX_CONFIG_GPIO), "expio"); - - /* disable the interrupt and clear the status */ - imx_writew(0xFFFF, PBC_INTMASK_CLEAR_REG); - imx_writew(0xFFFF, PBC_INTSTATUS_REG); - - irq_base = irq_alloc_descs(-1, 0, MXC_MAX_EXP_IO_LINES, numa_node_id()); - WARN_ON(irq_base < 0); - - domain = irq_domain_add_legacy(NULL, MXC_MAX_EXP_IO_LINES, irq_base, 0, - &irq_domain_simple_ops, NULL); - WARN_ON(!domain); - - for (i = irq_base; i < irq_base + MXC_MAX_EXP_IO_LINES; i++) { - irq_set_chip_and_handler(i, &expio_irq_chip, handle_level_irq); - irq_clear_status_flags(i, IRQ_NOREQUEST); - } - irq = gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_4)); - irq_set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH); - irq_set_chained_handler(irq, mx31ads_expio_irq_handler); -} - -#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1 -/* This section defines setup for the Wolfson Microelectronics - * 1133-EV1 PMU/audio board. When other PMU boards are supported the - * regulator definitions may be shared with them, but for now they can - * only be used with this board so would generate warnings about - * unused statics and some of the configuration is specific to this - * module. - */ - -/* CPU */ -static struct regulator_consumer_supply sw1a_consumers[] = { - { - .supply = "cpu_vcc", - } -}; - -static struct regulator_init_data sw1a_data = { - .constraints = { - .name = "SW1A", - .min_uV = 1275000, - .max_uV = 1600000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_MODE, - .valid_modes_mask = REGULATOR_MODE_NORMAL | - REGULATOR_MODE_FAST, - .state_mem = { - .uV = 1400000, - .mode = REGULATOR_MODE_NORMAL, - .enabled = 1, - }, - .initial_state = PM_SUSPEND_MEM, - .always_on = 1, - .boot_on = 1, - }, - .num_consumer_supplies = ARRAY_SIZE(sw1a_consumers), - .consumer_supplies = sw1a_consumers, -}; - -/* System IO - High */ -static struct regulator_init_data viohi_data = { - .constraints = { - .name = "VIOHO", - .min_uV = 2800000, - .max_uV = 2800000, - .state_mem = { - .uV = 2800000, - .mode = REGULATOR_MODE_NORMAL, - .enabled = 1, - }, - .initial_state = PM_SUSPEND_MEM, - .always_on = 1, - .boot_on = 1, - }, -}; - -/* System IO - Low */ -static struct regulator_init_data violo_data = { - .constraints = { - .name = "VIOLO", - .min_uV = 1800000, - .max_uV = 1800000, - .state_mem = { - .uV = 1800000, - .mode = REGULATOR_MODE_NORMAL, - .enabled = 1, - }, - .initial_state = PM_SUSPEND_MEM, - .always_on = 1, - .boot_on = 1, - }, -}; - -/* DDR RAM */ -static struct regulator_init_data sw2a_data = { - .constraints = { - .name = "SW2A", - .min_uV = 1800000, - .max_uV = 1800000, - .valid_modes_mask = REGULATOR_MODE_NORMAL, - .state_mem = { - .uV = 1800000, - .mode = REGULATOR_MODE_NORMAL, - .enabled = 1, - }, - .state_disk = { - .mode = REGULATOR_MODE_NORMAL, - .enabled = 0, - }, - .always_on = 1, - .boot_on = 1, - .initial_state = PM_SUSPEND_MEM, - }, -}; - -static struct regulator_init_data ldo1_data = { - .constraints = { - .name = "VCAM/VMMC1/VMMC2", - .min_uV = 2800000, - .max_uV = 2800000, - .valid_modes_mask = REGULATOR_MODE_NORMAL, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .apply_uV = 1, - }, -}; - -static struct regulator_consumer_supply ldo2_consumers[] = { - { .supply = "AVDD", .dev_name = "1-001a" }, - { .supply = "HPVDD", .dev_name = "1-001a" }, -}; - -/* CODEC and SIM */ -static struct regulator_init_data ldo2_data = { - .constraints = { - .name = "VESIM/VSIM/AVDD", - .min_uV = 3300000, - .max_uV = 3300000, - .valid_modes_mask = REGULATOR_MODE_NORMAL, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .apply_uV = 1, - }, - .num_consumer_supplies = ARRAY_SIZE(ldo2_consumers), - .consumer_supplies = ldo2_consumers, -}; - -/* General */ -static struct regulator_init_data vdig_data = { - .constraints = { - .name = "VDIG", - .min_uV = 1500000, - .max_uV = 1500000, - .valid_modes_mask = REGULATOR_MODE_NORMAL, - .apply_uV = 1, - .always_on = 1, - .boot_on = 1, - }, -}; - -/* Tranceivers */ -static struct regulator_init_data ldo4_data = { - .constraints = { - .name = "VRF1/CVDD_2.775", - .min_uV = 2500000, - .max_uV = 2500000, - .valid_modes_mask = REGULATOR_MODE_NORMAL, - .apply_uV = 1, - .always_on = 1, - .boot_on = 1, - }, -}; - -static struct wm8350_led_platform_data wm8350_led_data = { - .name = "wm8350:white", - .default_trigger = "heartbeat", - .max_uA = 27899, -}; - -static struct wm8350_audio_platform_data imx32ads_wm8350_setup = { - .vmid_discharge_msecs = 1000, - .drain_msecs = 30, - .cap_discharge_msecs = 700, - .vmid_charge_msecs = 700, - .vmid_s_curve = WM8350_S_CURVE_SLOW, - .dis_out4 = WM8350_DISCHARGE_SLOW, - .dis_out3 = WM8350_DISCHARGE_SLOW, - .dis_out2 = WM8350_DISCHARGE_SLOW, - .dis_out1 = WM8350_DISCHARGE_SLOW, - .vroi_out4 = WM8350_TIE_OFF_500R, - .vroi_out3 = WM8350_TIE_OFF_500R, - .vroi_out2 = WM8350_TIE_OFF_500R, - .vroi_out1 = WM8350_TIE_OFF_500R, - .vroi_enable = 0, - .codec_current_on = WM8350_CODEC_ISEL_1_0, - .codec_current_standby = WM8350_CODEC_ISEL_0_5, - .codec_current_charge = WM8350_CODEC_ISEL_1_5, -}; - -static int mx31_wm8350_init(struct wm8350 *wm8350) -{ - wm8350_gpio_config(wm8350, 0, WM8350_GPIO_DIR_IN, - WM8350_GPIO0_PWR_ON_IN, WM8350_GPIO_ACTIVE_LOW, - WM8350_GPIO_PULL_UP, WM8350_GPIO_INVERT_OFF, - WM8350_GPIO_DEBOUNCE_ON); - - wm8350_gpio_config(wm8350, 3, WM8350_GPIO_DIR_IN, - WM8350_GPIO3_PWR_OFF_IN, WM8350_GPIO_ACTIVE_HIGH, - WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF, - WM8350_GPIO_DEBOUNCE_ON); - - wm8350_gpio_config(wm8350, 4, WM8350_GPIO_DIR_IN, - WM8350_GPIO4_MR_IN, WM8350_GPIO_ACTIVE_HIGH, - WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF, - WM8350_GPIO_DEBOUNCE_OFF); - - wm8350_gpio_config(wm8350, 7, WM8350_GPIO_DIR_IN, - WM8350_GPIO7_HIBERNATE_IN, WM8350_GPIO_ACTIVE_HIGH, - WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF, - WM8350_GPIO_DEBOUNCE_OFF); - - wm8350_gpio_config(wm8350, 6, WM8350_GPIO_DIR_OUT, - WM8350_GPIO6_SDOUT_OUT, WM8350_GPIO_ACTIVE_HIGH, - WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF, - WM8350_GPIO_DEBOUNCE_OFF); - - wm8350_gpio_config(wm8350, 8, WM8350_GPIO_DIR_OUT, - WM8350_GPIO8_VCC_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW, - WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF, - WM8350_GPIO_DEBOUNCE_OFF); - - wm8350_gpio_config(wm8350, 9, WM8350_GPIO_DIR_OUT, - WM8350_GPIO9_BATT_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW, - WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF, - WM8350_GPIO_DEBOUNCE_OFF); - - wm8350_register_regulator(wm8350, WM8350_DCDC_1, &sw1a_data); - wm8350_register_regulator(wm8350, WM8350_DCDC_3, &viohi_data); - wm8350_register_regulator(wm8350, WM8350_DCDC_4, &violo_data); - wm8350_register_regulator(wm8350, WM8350_DCDC_6, &sw2a_data); - wm8350_register_regulator(wm8350, WM8350_LDO_1, &ldo1_data); - wm8350_register_regulator(wm8350, WM8350_LDO_2, &ldo2_data); - wm8350_register_regulator(wm8350, WM8350_LDO_3, &vdig_data); - wm8350_register_regulator(wm8350, WM8350_LDO_4, &ldo4_data); - - /* LEDs */ - wm8350_dcdc_set_slot(wm8350, WM8350_DCDC_5, 1, 1, - WM8350_DC5_ERRACT_SHUTDOWN_CONV); - wm8350_isink_set_flash(wm8350, WM8350_ISINK_A, - WM8350_ISINK_FLASH_DISABLE, - WM8350_ISINK_FLASH_TRIG_BIT, - WM8350_ISINK_FLASH_DUR_32MS, - WM8350_ISINK_FLASH_ON_INSTANT, - WM8350_ISINK_FLASH_OFF_INSTANT, - WM8350_ISINK_FLASH_MODE_EN); - wm8350_dcdc25_set_mode(wm8350, WM8350_DCDC_5, - WM8350_ISINK_MODE_BOOST, - WM8350_ISINK_ILIM_NORMAL, - WM8350_DC5_RMP_20V, - WM8350_DC5_FBSRC_ISINKA); - wm8350_register_led(wm8350, 0, WM8350_DCDC_5, WM8350_ISINK_A, - &wm8350_led_data); - - wm8350->codec.platform_data = &imx32ads_wm8350_setup; - - regulator_has_full_constraints(); - - return 0; -} - -static struct wm8350_platform_data __initdata mx31_wm8350_pdata = { - .init = mx31_wm8350_init, -}; -#endif - -static struct i2c_board_info __initdata mx31ads_i2c1_devices[] = { -#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1 - { - I2C_BOARD_INFO("wm8350", 0x1a), - .platform_data = &mx31_wm8350_pdata, - /* irq number is run-time assigned */ - }, -#endif -}; - -static void __init mxc_init_i2c(void) -{ -#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1 - mx31ads_i2c1_devices[0].irq = - gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3)); -#endif - i2c_register_board_info(1, mx31ads_i2c1_devices, - ARRAY_SIZE(mx31ads_i2c1_devices)); - - mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_ALT1)); - mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_ALT1)); - - imx31_add_imx_i2c1(NULL); -} - -static unsigned int ssi_pins[] = { - MX31_PIN_SFS5__SFS5, - MX31_PIN_SCK5__SCK5, - MX31_PIN_SRXD5__SRXD5, - MX31_PIN_STXD5__STXD5, -}; - -static void __init mxc_init_audio(void) -{ - imx31_add_imx_ssi(0, NULL); - mxc_iomux_setup_multiple_pins(ssi_pins, ARRAY_SIZE(ssi_pins), "ssi"); -} - -/* - * Static mappings, starting from the CS4 start address up to the start address - * of the CS8900. - */ -static struct map_desc mx31ads_io_desc[] __initdata = { - { - .virtual = (unsigned long)MX31_CS4_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR), - .length = CS4_CS8900_MMIO_START, - .type = MT_DEVICE - }, -}; - -static void __init mx31ads_map_io(void) -{ - mx31_map_io(); - iotable_init(mx31ads_io_desc, ARRAY_SIZE(mx31ads_io_desc)); -} - -static void __init mx31ads_init(void) -{ - imx31_soc_init(); - - mxc_init_imx_uart(); - mxc_init_audio(); -} - -static void __init mx31ads_late(void) -{ - mx31ads_init_expio(); - mxc_init_extuart(); - mxc_init_i2c(); - mxc_init_ext_ethernet(); -} - -static void __init mx31ads_timer_init(void) -{ - mx31_clocks_init(26000000); -} - -MACHINE_START(MX31ADS, "Freescale MX31ADS") - /* Maintainer: Freescale Semiconductor, Inc. */ - .atag_offset = 0x100, - .map_io = mx31ads_map_io, - .init_early = imx31_init_early, - .init_irq = mx31_init_irq, - .init_time = mx31ads_timer_init, - .init_machine = mx31ads_init, - .init_late = mx31ads_late, - .restart = mxc_restart, -MACHINE_END diff --git a/arch/arm/mach-imx/mach-mx31lilly.c b/arch/arm/mach-imx/mach-mx31lilly.c deleted file mode 100644 index 4b955ccc92cd..000000000000 --- a/arch/arm/mach-imx/mach-mx31lilly.c +++ /dev/null @@ -1,312 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * LILLY-1131 module support - * - * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de> - * - * based on code for other MX31 boards, - * - * Copyright 2005-2007 Freescale Semiconductor - * Copyright (c) 2009 Alberto Panizzo <maramaopercheseimorto@gmail.com> - * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group - */ - -#include <linux/types.h> -#include <linux/init.h> -#include <linux/clk.h> -#include <linux/gpio.h> -#include <linux/delay.h> -#include <linux/platform_device.h> -#include <linux/interrupt.h> -#include <linux/moduleparam.h> -#include <linux/smsc911x.h> -#include <linux/mtd/physmap.h> -#include <linux/spi/spi.h> -#include <linux/mfd/mc13783.h> -#include <linux/usb/otg.h> -#include <linux/usb/ulpi.h> -#include <linux/regulator/machine.h> -#include <linux/regulator/fixed.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> -#include <asm/mach/map.h> - -#include "board-mx31lilly.h" -#include "common.h" -#include "devices-imx31.h" -#include "ehci.h" -#include "hardware.h" -#include "iomux-mx3.h" -#include "ulpi.h" - -/* - * This file contains module-specific initialization routines for LILLY-1131. - * Initialization of peripherals found on the baseboard is implemented in the - * appropriate baseboard support code. - */ - -static unsigned int mx31lilly_pins[] __initdata = { - MX31_PIN_CTS1__CTS1, - MX31_PIN_RTS1__RTS1, - MX31_PIN_TXD1__TXD1, - MX31_PIN_RXD1__RXD1, - MX31_PIN_CTS2__CTS2, - MX31_PIN_RTS2__RTS2, - MX31_PIN_TXD2__TXD2, - MX31_PIN_RXD2__RXD2, - MX31_PIN_CSPI3_MOSI__RXD3, - MX31_PIN_CSPI3_MISO__TXD3, - MX31_PIN_CSPI3_SCLK__RTS3, - MX31_PIN_CSPI3_SPI_RDY__CTS3, -}; - -/* UART */ -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -/* SMSC ethernet support */ - -static struct resource smsc91x_resources[] = { - { - .start = MX31_CS4_BASE_ADDR, - .end = MX31_CS4_BASE_ADDR + 0xffff, - .flags = IORESOURCE_MEM, - }, - { - /* irq number is run-time assigned */ - .flags = IORESOURCE_IRQ | IRQF_TRIGGER_FALLING, - } -}; - -static struct smsc911x_platform_config smsc911x_config = { - .phy_interface = PHY_INTERFACE_MODE_MII, - .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, - .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN, - .flags = SMSC911X_USE_32BIT | - SMSC911X_SAVE_MAC_ADDRESS | - SMSC911X_FORCE_INTERNAL_PHY, -}; - -static struct platform_device smsc91x_device = { - .name = "smsc911x", - .id = -1, - .num_resources = ARRAY_SIZE(smsc91x_resources), - .resource = smsc91x_resources, - .dev = { - .platform_data = &smsc911x_config, - } -}; - -/* NOR flash */ -static struct physmap_flash_data nor_flash_data = { - .width = 2, -}; - -static struct resource nor_flash_resource = { - .start = 0xa0000000, - .end = 0xa1ffffff, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device physmap_flash_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &nor_flash_data, - }, - .resource = &nor_flash_resource, - .num_resources = 1, -}; - -/* USB */ - -#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ - PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) - -static int usbh1_init(struct platform_device *pdev) -{ - int pins[] = { - MX31_PIN_CSPI1_MOSI__USBH1_RXDM, - MX31_PIN_CSPI1_MISO__USBH1_RXDP, - MX31_PIN_CSPI1_SS0__USBH1_TXDM, - MX31_PIN_CSPI1_SS1__USBH1_TXDP, - MX31_PIN_CSPI1_SS2__USBH1_RCV, - MX31_PIN_CSPI1_SCLK__USBH1_OEB, - MX31_PIN_CSPI1_SPI_RDY__USBH1_FS, - }; - - mxc_iomux_setup_multiple_pins(pins, ARRAY_SIZE(pins), "USB H1"); - - mxc_iomux_set_pad(MX31_PIN_CSPI1_MOSI, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_CSPI1_MISO, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_CSPI1_SS0, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_CSPI1_SS1, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_CSPI1_SS2, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_CSPI1_SCLK, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_CSPI1_SPI_RDY, USB_PAD_CFG); - - mxc_iomux_set_gpr(MUX_PGP_USB_SUSPEND, true); - - mdelay(10); - - return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED | - MXC_EHCI_INTERFACE_SINGLE_UNI); -} - -static int usbh2_init(struct platform_device *pdev) -{ - int pins[] = { - MX31_PIN_USBH2_DATA0__USBH2_DATA0, - MX31_PIN_USBH2_DATA1__USBH2_DATA1, - MX31_PIN_USBH2_CLK__USBH2_CLK, - MX31_PIN_USBH2_DIR__USBH2_DIR, - MX31_PIN_USBH2_NXT__USBH2_NXT, - MX31_PIN_USBH2_STP__USBH2_STP, - }; - - mxc_iomux_setup_multiple_pins(pins, ARRAY_SIZE(pins), "USB H2"); - - mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG); - - mxc_iomux_set_gpr(MUX_PGP_UH2, true); - - /* chip select */ - mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_GPIO), - "USBH2_CS"); - gpio_request(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), "USBH2 CS"); - gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), 0); - - mdelay(10); - - return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED); -} - -static const struct mxc_usbh_platform_data usbh1_pdata __initconst = { - .init = usbh1_init, - .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL, -}; - -static struct mxc_usbh_platform_data usbh2_pdata __initdata = { - .init = usbh2_init, - .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, -}; - -static void __init lilly1131_usb_init(void) -{ - imx31_add_mxc_ehci_hs(1, &usbh1_pdata); - - usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | - ULPI_OTG_DRVVBUS_EXT); - if (usbh2_pdata.otg) - imx31_add_mxc_ehci_hs(2, &usbh2_pdata); -} - -static struct mc13xxx_platform_data mc13783_pdata __initdata = { - .flags = MC13XXX_USE_RTC | MC13XXX_USE_TOUCHSCREEN, -}; - -static struct spi_board_info mc13783_dev __initdata = { - .modalias = "mc13783", - .max_speed_hz = 1000000, - .bus_num = 1, - .chip_select = 0, - .platform_data = &mc13783_pdata, - /* irq number is run-time assigned */ -}; - -static struct platform_device *devices[] __initdata = { - &smsc91x_device, - &physmap_flash_device, -}; - -static int mx31lilly_baseboard; -core_param(mx31lilly_baseboard, mx31lilly_baseboard, int, 0444); - -static struct regulator_consumer_supply dummy_supplies[] = { - REGULATOR_SUPPLY("vdd33a", "smsc911x"), - REGULATOR_SUPPLY("vddvario", "smsc911x"), -}; - -static void __init mx31lilly_board_init(void) -{ - imx31_soc_init(); - - mxc_iomux_setup_multiple_pins(mx31lilly_pins, - ARRAY_SIZE(mx31lilly_pins), "mx31lily"); - - imx31_add_imx_uart0(&uart_pdata); - imx31_add_imx_uart1(&uart_pdata); - imx31_add_imx_uart2(&uart_pdata); - - mxc_iomux_alloc_pin(MX31_PIN_CS4__CS4, "Ethernet CS"); - - /* SPI */ - mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SCLK__SCLK, "SPI1_CLK"); - mxc_iomux_alloc_pin(MX31_PIN_CSPI1_MOSI__MOSI, "SPI1_TX"); - mxc_iomux_alloc_pin(MX31_PIN_CSPI1_MISO__MISO, "SPI1_RX"); - mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SPI_RDY__SPI_RDY, "SPI1_RDY"); - mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SS0__SS0, "SPI1_SS0"); - mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SS1__SS1, "SPI1_SS1"); - mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SS2__SS2, "SPI1_SS2"); - - mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SCLK__SCLK, "SPI2_CLK"); - mxc_iomux_alloc_pin(MX31_PIN_CSPI2_MOSI__MOSI, "SPI2_TX"); - mxc_iomux_alloc_pin(MX31_PIN_CSPI2_MISO__MISO, "SPI2_RX"); - mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SPI_RDY__SPI_RDY, "SPI2_RDY"); - mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SS0__SS0, "SPI2_SS0"); - mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SS1__SS1, "SPI2_SS1"); - mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SS2__SS2, "SPI2_SS2"); - - imx31_add_spi_imx0(NULL); - imx31_add_spi_imx1(NULL); - - regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); -} - -static void __init mx31lilly_late_init(void) -{ - if (mx31lilly_baseboard == MX31LILLY_DB) - mx31lilly_db_init(); - - mc13783_dev.irq = gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3)); - spi_register_board_info(&mc13783_dev, 1); - - smsc91x_resources[1].start = - gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_0)); - smsc91x_resources[1].end = - gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_0)); - platform_add_devices(devices, ARRAY_SIZE(devices)); - - /* USB */ - lilly1131_usb_init(); -} - -static void __init mx31lilly_timer_init(void) -{ - mx31_clocks_init(26000000); -} - -MACHINE_START(LILLY1131, "INCO startec LILLY-1131") - .atag_offset = 0x100, - .map_io = mx31_map_io, - .init_early = imx31_init_early, - .init_irq = mx31_init_irq, - .init_time = mx31lilly_timer_init, - .init_machine = mx31lilly_board_init, - .init_late = mx31lilly_late_init, - .restart = mxc_restart, -MACHINE_END diff --git a/arch/arm/mach-imx/mach-mx31lite.c b/arch/arm/mach-imx/mach-mx31lite.c deleted file mode 100644 index aaccf52f7ac1..000000000000 --- a/arch/arm/mach-imx/mach-mx31lite.c +++ /dev/null @@ -1,290 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (C) 2000 Deep Blue Solutions Ltd - * Copyright (C) 2002 Shane Nay (shane@minirl.com) - * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright (C) 2009 Daniel Mack <daniel@caiaq.de> - */ - -#include <linux/types.h> -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/memory.h> -#include <linux/platform_device.h> -#include <linux/gpio.h> -#include <linux/moduleparam.h> -#include <linux/smsc911x.h> -#include <linux/mfd/mc13783.h> -#include <linux/spi/spi.h> -#include <linux/usb/otg.h> -#include <linux/usb/ulpi.h> -#include <linux/mtd/physmap.h> -#include <linux/delay.h> -#include <linux/regulator/machine.h> -#include <linux/regulator/fixed.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> -#include <asm/mach/map.h> -#include <asm/page.h> -#include <asm/setup.h> - -#include "board-mx31lite.h" -#include "common.h" -#include "devices-imx31.h" -#include "ehci.h" -#include "hardware.h" -#include "iomux-mx3.h" -#include "ulpi.h" - -/* - * This file contains the module-specific initialization routines. - */ - -static unsigned int mx31lite_pins[] = { - /* UART1 */ - MX31_PIN_CTS1__CTS1, - MX31_PIN_RTS1__RTS1, - MX31_PIN_TXD1__TXD1, - MX31_PIN_RXD1__RXD1, - /* SPI 0 */ - MX31_PIN_CSPI1_SCLK__SCLK, - MX31_PIN_CSPI1_MOSI__MOSI, - MX31_PIN_CSPI1_MISO__MISO, - MX31_PIN_CSPI1_SPI_RDY__SPI_RDY, - MX31_PIN_CSPI1_SS0__SS0, - MX31_PIN_CSPI1_SS1__SS1, - MX31_PIN_CSPI1_SS2__SS2, - /* LAN9117 IRQ pin */ - IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_GPIO), - /* SPI 1 */ - MX31_PIN_CSPI2_SCLK__SCLK, - MX31_PIN_CSPI2_MOSI__MOSI, - MX31_PIN_CSPI2_MISO__MISO, - MX31_PIN_CSPI2_SPI_RDY__SPI_RDY, - MX31_PIN_CSPI2_SS0__SS0, - MX31_PIN_CSPI2_SS1__SS1, - MX31_PIN_CSPI2_SS2__SS2, -}; - -/* UART */ -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static const struct mxc_nand_platform_data -mx31lite_nand_board_info __initconst = { - .width = 1, - .hw_ecc = 1, -}; - -static struct smsc911x_platform_config smsc911x_config = { - .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, - .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, - .flags = SMSC911X_USE_16BIT, -}; - -static struct resource smsc911x_resources[] = { - { - .start = MX31_CS4_BASE_ADDR, - .end = MX31_CS4_BASE_ADDR + 0x100, - .flags = IORESOURCE_MEM, - }, { - /* irq number is run-time assigned */ - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device smsc911x_device = { - .name = "smsc911x", - .id = -1, - .num_resources = ARRAY_SIZE(smsc911x_resources), - .resource = smsc911x_resources, - .dev = { - .platform_data = &smsc911x_config, - }, -}; - -static struct mc13xxx_platform_data mc13783_pdata __initdata = { - .flags = MC13XXX_USE_RTC, -}; - -static struct spi_board_info mc13783_spi_dev __initdata = { - .modalias = "mc13783", - .max_speed_hz = 1000000, - .bus_num = 1, - .chip_select = 0, - .platform_data = &mc13783_pdata, - /* irq number is run-time assigned */ -}; - -/* - * USB - */ - -#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ - PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) - -static int usbh2_init(struct platform_device *pdev) -{ - int pins[] = { - MX31_PIN_USBH2_DATA0__USBH2_DATA0, - MX31_PIN_USBH2_DATA1__USBH2_DATA1, - MX31_PIN_USBH2_CLK__USBH2_CLK, - MX31_PIN_USBH2_DIR__USBH2_DIR, - MX31_PIN_USBH2_NXT__USBH2_NXT, - MX31_PIN_USBH2_STP__USBH2_STP, - }; - - mxc_iomux_setup_multiple_pins(pins, ARRAY_SIZE(pins), "USB H2"); - - mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG); - - mxc_iomux_set_gpr(MUX_PGP_UH2, true); - - /* chip select */ - mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_GPIO), - "USBH2_CS"); - gpio_request(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), "USBH2 CS"); - gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), 0); - - mdelay(10); - - return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED); -} - -static struct mxc_usbh_platform_data usbh2_pdata __initdata = { - .init = usbh2_init, - .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, -}; - -/* - * NOR flash - */ - -static struct physmap_flash_data nor_flash_data = { - .width = 2, -}; - -static struct resource nor_flash_resource = { - .start = 0xa0000000, - .end = 0xa1ffffff, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device physmap_flash_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &nor_flash_data, - }, - .resource = &nor_flash_resource, - .num_resources = 1, -}; - -/* - * This structure defines the MX31 memory map. - */ -static struct map_desc mx31lite_io_desc[] __initdata = { - { - .virtual = (unsigned long)MX31_CS4_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR), - .length = MX31_CS4_SIZE, - .type = MT_DEVICE - } -}; - -/* - * Set up static virtual mappings. - */ -static void __init mx31lite_map_io(void) -{ - mx31_map_io(); - iotable_init(mx31lite_io_desc, ARRAY_SIZE(mx31lite_io_desc)); -} - -static int mx31lite_baseboard; -core_param(mx31lite_baseboard, mx31lite_baseboard, int, 0444); - -static struct regulator_consumer_supply dummy_supplies[] = { - REGULATOR_SUPPLY("vdd33a", "smsc911x"), - REGULATOR_SUPPLY("vddvario", "smsc911x"), -}; - -static void __init mx31lite_init(void) -{ - imx31_soc_init(); - - mxc_iomux_setup_multiple_pins(mx31lite_pins, ARRAY_SIZE(mx31lite_pins), - "mx31lite"); - - imx31_add_imx_uart0(&uart_pdata); - imx31_add_spi_imx0(NULL); - - /* NOR and NAND flash */ - platform_device_register(&physmap_flash_device); - imx31_add_mxc_nand(&mx31lite_nand_board_info); - - imx31_add_spi_imx1(NULL); - - regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); -} - -static void __init mx31lite_late(void) -{ - int ret; - - if (mx31lite_baseboard == MX31LITE_DB) - mx31lite_db_init(); - - mc13783_spi_dev.irq = gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3)); - spi_register_board_info(&mc13783_spi_dev, 1); - - /* USB */ - usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | - ULPI_OTG_DRVVBUS_EXT); - if (usbh2_pdata.otg) - imx31_add_mxc_ehci_hs(2, &usbh2_pdata); - - /* SMSC9117 IRQ pin */ - ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_SFS6), "sms9117-irq"); - if (ret) - pr_warn("could not get LAN irq gpio\n"); - else { - gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_SFS6)); - smsc911x_resources[1].start = - gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_SFS6)); - smsc911x_resources[1].end = - gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_SFS6)); - platform_device_register(&smsc911x_device); - } -} - -static void __init mx31lite_timer_init(void) -{ - mx31_clocks_init(26000000); -} - -MACHINE_START(MX31LITE, "LogicPD i.MX31 SOM") - /* Maintainer: Freescale Semiconductor, Inc. */ - .atag_offset = 0x100, - .map_io = mx31lite_map_io, - .init_early = imx31_init_early, - .init_irq = mx31_init_irq, - .init_time = mx31lite_timer_init, - .init_machine = mx31lite_init, - .init_late = mx31lite_late, - .restart = mxc_restart, -MACHINE_END diff --git a/arch/arm/mach-imx/mach-mx31moboard.c b/arch/arm/mach-imx/mach-mx31moboard.c deleted file mode 100644 index 7f780ad2d459..000000000000 --- a/arch/arm/mach-imx/mach-mx31moboard.c +++ /dev/null @@ -1,581 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (C) 2008 Valentin Longchamp, EPFL Mobots group - */ - -#include <linux/delay.h> -#include <linux/dma-map-ops.h> -#include <linux/gfp.h> -#include <linux/gpio.h> -#include <linux/init.h> -#include <linux/interrupt.h> -#include <linux/moduleparam.h> -#include <linux/leds.h> -#include <linux/memory.h> -#include <linux/mtd/physmap.h> -#include <linux/mtd/partitions.h> -#include <linux/platform_device.h> -#include <linux/regulator/machine.h> -#include <linux/mfd/mc13783.h> -#include <linux/spi/spi.h> -#include <linux/types.h> -#include <linux/memblock.h> -#include <linux/clk.h> -#include <linux/io.h> -#include <linux/err.h> -#include <linux/input.h> - -#include <linux/usb/otg.h> -#include <linux/usb/ulpi.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> -#include <asm/mach/map.h> -#include <asm/memblock.h> -#include <linux/platform_data/asoc-imx-ssi.h> - -#include "board-mx31moboard.h" -#include "common.h" -#include "devices-imx31.h" -#include "ehci.h" -#include "hardware.h" -#include "iomux-mx3.h" -#include "ulpi.h" - -static unsigned int moboard_pins[] = { - /* UART0 */ - MX31_PIN_TXD1__TXD1, MX31_PIN_RXD1__RXD1, - MX31_PIN_CTS1__GPIO2_7, - /* UART4 */ - MX31_PIN_PC_RST__CTS5, MX31_PIN_PC_VS2__RTS5, - MX31_PIN_PC_BVD2__TXD5, MX31_PIN_PC_BVD1__RXD5, - /* I2C0 */ - MX31_PIN_I2C_DAT__I2C1_SDA, MX31_PIN_I2C_CLK__I2C1_SCL, - /* I2C1 */ - MX31_PIN_DCD_DTE1__I2C2_SDA, MX31_PIN_RI_DTE1__I2C2_SCL, - /* SDHC1 */ - MX31_PIN_SD1_DATA3__SD1_DATA3, MX31_PIN_SD1_DATA2__SD1_DATA2, - MX31_PIN_SD1_DATA1__SD1_DATA1, MX31_PIN_SD1_DATA0__SD1_DATA0, - MX31_PIN_SD1_CLK__SD1_CLK, MX31_PIN_SD1_CMD__SD1_CMD, - MX31_PIN_ATA_CS0__GPIO3_26, MX31_PIN_ATA_CS1__GPIO3_27, - /* USB reset */ - MX31_PIN_GPIO1_0__GPIO1_0, - /* USB OTG */ - MX31_PIN_USBOTG_DATA0__USBOTG_DATA0, - MX31_PIN_USBOTG_DATA1__USBOTG_DATA1, - MX31_PIN_USBOTG_DATA2__USBOTG_DATA2, - MX31_PIN_USBOTG_DATA3__USBOTG_DATA3, - MX31_PIN_USBOTG_DATA4__USBOTG_DATA4, - MX31_PIN_USBOTG_DATA5__USBOTG_DATA5, - MX31_PIN_USBOTG_DATA6__USBOTG_DATA6, - MX31_PIN_USBOTG_DATA7__USBOTG_DATA7, - MX31_PIN_USBOTG_CLK__USBOTG_CLK, MX31_PIN_USBOTG_DIR__USBOTG_DIR, - MX31_PIN_USBOTG_NXT__USBOTG_NXT, MX31_PIN_USBOTG_STP__USBOTG_STP, - MX31_PIN_USB_OC__GPIO1_30, - /* USB H2 */ - MX31_PIN_USBH2_DATA0__USBH2_DATA0, - MX31_PIN_USBH2_DATA1__USBH2_DATA1, - MX31_PIN_STXD3__USBH2_DATA2, MX31_PIN_SRXD3__USBH2_DATA3, - MX31_PIN_SCK3__USBH2_DATA4, MX31_PIN_SFS3__USBH2_DATA5, - MX31_PIN_STXD6__USBH2_DATA6, MX31_PIN_SRXD6__USBH2_DATA7, - MX31_PIN_USBH2_CLK__USBH2_CLK, MX31_PIN_USBH2_DIR__USBH2_DIR, - MX31_PIN_USBH2_NXT__USBH2_NXT, MX31_PIN_USBH2_STP__USBH2_STP, - MX31_PIN_SCK6__GPIO1_25, - /* LEDs */ - MX31_PIN_SVEN0__GPIO2_0, MX31_PIN_STX0__GPIO2_1, - MX31_PIN_SRX0__GPIO2_2, MX31_PIN_SIMPD0__GPIO2_3, - /* SPI1 */ - MX31_PIN_CSPI2_MOSI__MOSI, MX31_PIN_CSPI2_MISO__MISO, - MX31_PIN_CSPI2_SCLK__SCLK, MX31_PIN_CSPI2_SPI_RDY__SPI_RDY, - MX31_PIN_CSPI2_SS0__SS0, MX31_PIN_CSPI2_SS2__SS2, - /* Atlas IRQ */ - MX31_PIN_GPIO1_3__GPIO1_3, - /* SPI2 */ - MX31_PIN_CSPI3_MOSI__MOSI, MX31_PIN_CSPI3_MISO__MISO, - MX31_PIN_CSPI3_SCLK__SCLK, MX31_PIN_CSPI3_SPI_RDY__SPI_RDY, - MX31_PIN_CSPI2_SS1__CSPI3_SS1, - /* SSI */ - MX31_PIN_STXD4__STXD4, MX31_PIN_SRXD4__SRXD4, - MX31_PIN_SCK4__SCK4, MX31_PIN_SFS4__SFS4, -}; - -static struct physmap_flash_data mx31moboard_flash_data = { - .width = 2, -}; - -static struct resource mx31moboard_flash_resource = { - .start = 0xa0000000, - .end = 0xa1ffffff, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device mx31moboard_flash = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &mx31moboard_flash_data, - }, - .resource = &mx31moboard_flash_resource, - .num_resources = 1, -}; - -static void __init moboard_uart0_init(void) -{ - if (!gpio_request(IOMUX_TO_GPIO(MX31_PIN_CTS1), "uart0-cts-hack")) { - gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_CTS1), 0); - gpio_free(IOMUX_TO_GPIO(MX31_PIN_CTS1)); - } -} - -static const struct imxuart_platform_data uart0_pdata __initconst = { -}; - -static const struct imxuart_platform_data uart4_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static const struct imxi2c_platform_data moboard_i2c0_data __initconst = { - .bitrate = 400000, -}; - -static const struct imxi2c_platform_data moboard_i2c1_data __initconst = { - .bitrate = 100000, -}; - -static struct regulator_consumer_supply sdhc_consumers[] = { - { - .dev_name = "imx31-mmc.0", - .supply = "sdhc0_vcc", - }, - { - .dev_name = "imx31-mmc.1", - .supply = "sdhc1_vcc", - }, -}; - -static struct regulator_init_data sdhc_vreg_data = { - .constraints = { - .min_uV = 2700000, - .max_uV = 3000000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS, - .valid_modes_mask = REGULATOR_MODE_NORMAL | - REGULATOR_MODE_FAST, - .always_on = 0, - .boot_on = 1, - }, - .num_consumer_supplies = ARRAY_SIZE(sdhc_consumers), - .consumer_supplies = sdhc_consumers, -}; - -static struct regulator_consumer_supply cam_consumers[] = { - { - .dev_name = "mx3_camera.0", - .supply = "cam_vcc", - }, -}; - -static struct regulator_init_data cam_vreg_data = { - .constraints = { - .min_uV = 2700000, - .max_uV = 3000000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS, - .valid_modes_mask = REGULATOR_MODE_NORMAL | - REGULATOR_MODE_FAST, - .always_on = 0, - .boot_on = 1, - }, - .num_consumer_supplies = ARRAY_SIZE(cam_consumers), - .consumer_supplies = cam_consumers, -}; - -static struct mc13xxx_regulator_init_data moboard_regulators[] = { - { - .id = MC13783_REG_VMMC1, - .init_data = &sdhc_vreg_data, - }, - { - .id = MC13783_REG_VCAM, - .init_data = &cam_vreg_data, - }, -}; - -static struct mc13xxx_led_platform_data moboard_led[] = { - { - .id = MC13783_LED_R1, - .name = "coreboard-led-4:red", - }, - { - .id = MC13783_LED_G1, - .name = "coreboard-led-4:green", - }, - { - .id = MC13783_LED_B1, - .name = "coreboard-led-4:blue", - }, - { - .id = MC13783_LED_R2, - .name = "coreboard-led-5:red", - }, - { - .id = MC13783_LED_G2, - .name = "coreboard-led-5:green", - }, - { - .id = MC13783_LED_B2, - .name = "coreboard-led-5:blue", - }, -}; - -static struct mc13xxx_leds_platform_data moboard_leds = { - .num_leds = ARRAY_SIZE(moboard_led), - .led = moboard_led, - .led_control[0] = MC13783_LED_C0_ENABLE | MC13783_LED_C0_ABMODE(0), - .led_control[1] = MC13783_LED_C1_SLEWLIM, - .led_control[2] = MC13783_LED_C2_SLEWLIM, - .led_control[3] = MC13783_LED_C3_PERIOD(0) | - MC13783_LED_C3_CURRENT_R1(2) | - MC13783_LED_C3_CURRENT_G1(2) | - MC13783_LED_C3_CURRENT_B1(2), - .led_control[4] = MC13783_LED_C4_PERIOD(0) | - MC13783_LED_C4_CURRENT_R2(3) | - MC13783_LED_C4_CURRENT_G2(3) | - MC13783_LED_C4_CURRENT_B2(3), -}; - -static struct mc13xxx_buttons_platform_data moboard_buttons = { - .b1on_flags = MC13783_BUTTON_DBNC_750MS | MC13783_BUTTON_ENABLE | - MC13783_BUTTON_POL_INVERT, - .b1on_key = KEY_POWER, -}; - -static struct mc13xxx_codec_platform_data moboard_codec = { - .dac_ssi_port = MC13783_SSI1_PORT, - .adc_ssi_port = MC13783_SSI1_PORT, -}; - -static struct mc13xxx_platform_data moboard_pmic = { - .regulators = { - .regulators = moboard_regulators, - .num_regulators = ARRAY_SIZE(moboard_regulators), - }, - .leds = &moboard_leds, - .buttons = &moboard_buttons, - .codec = &moboard_codec, - .flags = MC13XXX_USE_RTC | MC13XXX_USE_ADC | MC13XXX_USE_CODEC, -}; - -static struct imx_ssi_platform_data moboard_ssi_pdata = { - .flags = IMX_SSI_DMA | IMX_SSI_NET, -}; - -static struct spi_board_info moboard_spi_board_info[] __initdata = { - { - .modalias = "mc13783", - /* irq number is run-time assigned */ - .max_speed_hz = 300000, - .bus_num = 1, - .chip_select = 0, - .platform_data = &moboard_pmic, - .mode = SPI_CS_HIGH, - }, -}; - -#define SDHC1_CD IOMUX_TO_GPIO(MX31_PIN_ATA_CS0) -#define SDHC1_WP IOMUX_TO_GPIO(MX31_PIN_ATA_CS1) - -static int moboard_sdhc1_get_ro(struct device *dev) -{ - return !gpio_get_value(SDHC1_WP); -} - -static int moboard_sdhc1_init(struct device *dev, irq_handler_t detect_irq, - void *data) -{ - int ret; - - ret = gpio_request(SDHC1_CD, "sdhc-detect"); - if (ret) - return ret; - - gpio_direction_input(SDHC1_CD); - - ret = gpio_request(SDHC1_WP, "sdhc-wp"); - if (ret) - goto err_gpio_free; - gpio_direction_input(SDHC1_WP); - - ret = request_irq(gpio_to_irq(SDHC1_CD), detect_irq, - IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, - "sdhc1-card-detect", data); - if (ret) - goto err_gpio_free_2; - - return 0; - -err_gpio_free_2: - gpio_free(SDHC1_WP); -err_gpio_free: - gpio_free(SDHC1_CD); - - return ret; -} - -static void moboard_sdhc1_exit(struct device *dev, void *data) -{ - free_irq(gpio_to_irq(SDHC1_CD), data); - gpio_free(SDHC1_WP); - gpio_free(SDHC1_CD); -} - -static const struct imxmmc_platform_data sdhc1_pdata __initconst = { - .get_ro = moboard_sdhc1_get_ro, - .init = moboard_sdhc1_init, - .exit = moboard_sdhc1_exit, -}; - -/* - * this pin is dedicated for all mx31moboard systems, so we do it here - */ -#define USB_RESET_B IOMUX_TO_GPIO(MX31_PIN_GPIO1_0) -#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ - PAD_CTL_ODE_CMOS) - -#define OTG_EN_B IOMUX_TO_GPIO(MX31_PIN_USB_OC) -#define USBH2_EN_B IOMUX_TO_GPIO(MX31_PIN_SCK6) - -static void usb_xcvr_reset(void) -{ - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG | PAD_CTL_100K_PD); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG | PAD_CTL_100K_PD); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG | PAD_CTL_100K_PD); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG | PAD_CTL_100K_PD); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG | PAD_CTL_100K_PD); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG | PAD_CTL_100K_PD); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG | PAD_CTL_100K_PD); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG | PAD_CTL_100K_PD); - mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG | PAD_CTL_100K_PU); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG | PAD_CTL_100K_PU); - mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG | PAD_CTL_100K_PU); - mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG | PAD_CTL_100K_PU); - - mxc_iomux_set_gpr(MUX_PGP_UH2, true); - mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG | PAD_CTL_100K_PU); - mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG | PAD_CTL_100K_PU); - mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG | PAD_CTL_100K_PU); - mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG | PAD_CTL_100K_PU); - mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG | PAD_CTL_100K_PD); - mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG | PAD_CTL_100K_PD); - mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG | PAD_CTL_100K_PD); - mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG | PAD_CTL_100K_PD); - mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG | PAD_CTL_100K_PD); - mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG | PAD_CTL_100K_PD); - mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG | PAD_CTL_100K_PD); - mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG | PAD_CTL_100K_PD); - - gpio_request(OTG_EN_B, "usb-udc-en"); - gpio_direction_output(OTG_EN_B, 0); - gpio_request(USBH2_EN_B, "usbh2-en"); - gpio_direction_output(USBH2_EN_B, 0); - - gpio_request(USB_RESET_B, "usb-reset"); - gpio_direction_output(USB_RESET_B, 0); - mdelay(1); - gpio_set_value(USB_RESET_B, 1); - mdelay(1); -} - -static int moboard_usbh2_init_hw(struct platform_device *pdev) -{ - return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED); -} - -static struct mxc_usbh_platform_data usbh2_pdata __initdata = { - .init = moboard_usbh2_init_hw, - .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, -}; - -static int __init moboard_usbh2_init(void) -{ - struct platform_device *pdev; - - usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | - ULPI_OTG_DRVVBUS_EXT); - if (!usbh2_pdata.otg) - return -ENODEV; - - pdev = imx31_add_mxc_ehci_hs(2, &usbh2_pdata); - - return PTR_ERR_OR_ZERO(pdev); -} - -static const struct gpio_led mx31moboard_leds[] __initconst = { - { - .name = "coreboard-led-0:red:running", - .default_trigger = "heartbeat", - .gpio = IOMUX_TO_GPIO(MX31_PIN_SVEN0), - }, { - .name = "coreboard-led-1:red", - .gpio = IOMUX_TO_GPIO(MX31_PIN_STX0), - }, { - .name = "coreboard-led-2:red", - .gpio = IOMUX_TO_GPIO(MX31_PIN_SRX0), - }, { - .name = "coreboard-led-3:red", - .gpio = IOMUX_TO_GPIO(MX31_PIN_SIMPD0), - }, -}; - -static const struct gpio_led_platform_data mx31moboard_led_pdata __initconst = { - .num_leds = ARRAY_SIZE(mx31moboard_leds), - .leds = mx31moboard_leds, -}; - -static struct platform_device *devices[] __initdata = { - &mx31moboard_flash, -}; - -static struct mx3_camera_pdata camera_pdata __initdata = { - .flags = MX3_CAMERA_DATAWIDTH_8 | MX3_CAMERA_DATAWIDTH_10, - .mclk_10khz = 4800, -}; - -static phys_addr_t mx3_camera_base __initdata; -#define MX3_CAMERA_BUF_SIZE SZ_4M - -static int __init mx31moboard_init_cam(void) -{ - int ret; - struct platform_device *pdev; - - imx31_add_ipu_core(); - - pdev = imx31_alloc_mx3_camera(&camera_pdata); - if (IS_ERR(pdev)) - return PTR_ERR(pdev); - - ret = dma_declare_coherent_memory(&pdev->dev, - mx3_camera_base, mx3_camera_base, - MX3_CAMERA_BUF_SIZE); - if (ret) - goto err; - - ret = platform_device_add(pdev); - if (ret) -err: - platform_device_put(pdev); - - return ret; - -} - -static void mx31moboard_poweroff(void) -{ - struct clk *clk = clk_get_sys("imx2-wdt.0", NULL); - - if (!IS_ERR(clk)) - clk_prepare_enable(clk); - - mxc_iomux_mode(MX31_PIN_WATCHDOG_RST__WATCHDOG_RST); - - imx_writew(1 << 6 | 1 << 2, MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR)); -} - -static int mx31moboard_baseboard; -core_param(mx31moboard_baseboard, mx31moboard_baseboard, int, 0444); - -/* - * Board specific initialization. - */ -static void __init mx31moboard_init(void) -{ - imx31_soc_init(); - - mxc_iomux_setup_multiple_pins(moboard_pins, ARRAY_SIZE(moboard_pins), - "moboard"); - - platform_add_devices(devices, ARRAY_SIZE(devices)); - - imx31_add_imx2_wdt(); - - imx31_add_imx_uart0(&uart0_pdata); - imx31_add_imx_uart4(&uart4_pdata); - - imx31_add_imx_i2c0(&moboard_i2c0_data); - imx31_add_imx_i2c1(&moboard_i2c1_data); - - imx31_add_spi_imx1(NULL); - imx31_add_spi_imx2(NULL); - - mx31moboard_init_cam(); - - imx31_add_imx_ssi(0, &moboard_ssi_pdata); - - pm_power_off = mx31moboard_poweroff; -} - -static void __init mx31moboard_late(void) -{ - gpio_led_register_device(-1, &mx31moboard_led_pdata); - - moboard_uart0_init(); - - gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3), "pmic-irq"); - gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3)); - moboard_spi_board_info[0].irq = - gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3)); - spi_register_board_info(moboard_spi_board_info, - ARRAY_SIZE(moboard_spi_board_info)); - - imx31_add_mxc_mmc(0, &sdhc1_pdata); - - usb_xcvr_reset(); - moboard_usbh2_init(); - - imx_add_platform_device("imx_mc13783", 0, NULL, 0, NULL, 0); - - switch (mx31moboard_baseboard) { - case MX31NOBOARD: - break; - case MX31DEVBOARD: - mx31moboard_devboard_init(); - break; - case MX31MARXBOT: - mx31moboard_marxbot_init(); - break; - case MX31SMARTBOT: - case MX31EYEBOT: - mx31moboard_smartbot_init(mx31moboard_baseboard); - break; - default: - printk(KERN_ERR "Illegal mx31moboard_baseboard type %d\n", - mx31moboard_baseboard); - } -} - -static void __init mx31moboard_timer_init(void) -{ - mx31_clocks_init(26000000); -} - -static void __init mx31moboard_reserve(void) -{ - /* reserve 4 MiB for mx3-camera */ - mx3_camera_base = arm_memblock_steal(MX3_CAMERA_BUF_SIZE, - MX3_CAMERA_BUF_SIZE); -} - -MACHINE_START(MX31MOBOARD, "EPFL Mobots mx31moboard") - /* Maintainer: Philippe Retornaz, EPFL Mobots group */ - .atag_offset = 0x100, - .reserve = mx31moboard_reserve, - .map_io = mx31_map_io, - .init_early = imx31_init_early, - .init_irq = mx31_init_irq, - .init_time = mx31moboard_timer_init, - .init_machine = mx31moboard_init, - .init_late = mx31moboard_late, - .restart = mxc_restart, -MACHINE_END diff --git a/arch/arm/mach-imx/mach-mx35_3ds.c b/arch/arm/mach-imx/mach-mx35_3ds.c deleted file mode 100644 index 802e0abe4568..000000000000 --- a/arch/arm/mach-imx/mach-mx35_3ds.c +++ /dev/null @@ -1,516 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright (C) 2009 Marc Kleine-Budde, Pengutronix - * - * Author: Fabio Estevam <fabio.estevam@freescale.com> - * - * Copyright (C) 2011 Meprolight, Ltd. - * Alex Gershgorin <alexg@meprolight.com> - * - * Modified from i.MX31 3-Stack Development System - */ - -/* - * This machine is known as: - * - i.MX35 3-Stack Development System - * - i.MX35 Platform Development Kit (i.MX35 PDK) - */ - -#include <linux/types.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/memory.h> -#include <linux/gpio.h> -#include <linux/usb/otg.h> - -#include <linux/mtd/physmap.h> -#include <linux/mfd/mc13892.h> -#include <linux/regulator/machine.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> -#include <asm/mach/map.h> - -#include <video/platform_lcd.h> - -#include "3ds_debugboard.h" -#include "common.h" -#include "devices-imx35.h" -#include "ehci.h" -#include "hardware.h" -#include "iomux-mx35.h" - -#define GPIO_MC9S08DZ60_GPS_ENABLE 0 -#define GPIO_MC9S08DZ60_HDD_ENABLE 4 -#define GPIO_MC9S08DZ60_WIFI_ENABLE 5 -#define GPIO_MC9S08DZ60_LCD_ENABLE 6 -#define GPIO_MC9S08DZ60_SPEAKER_ENABLE 8 - -static const struct fb_videomode fb_modedb[] = { - { - /* 800x480 @ 55 Hz */ - .name = "Ceramate-CLAA070VC01", - .refresh = 55, - .xres = 800, - .yres = 480, - .pixclock = 40000, - .left_margin = 40, - .right_margin = 40, - .upper_margin = 5, - .lower_margin = 5, - .hsync_len = 20, - .vsync_len = 10, - .sync = FB_SYNC_OE_ACT_HIGH, - .vmode = FB_VMODE_NONINTERLACED, - .flag = 0, - }, -}; - -static struct mx3fb_platform_data mx3fb_pdata __initdata = { - .name = "Ceramate-CLAA070VC01", - .mode = fb_modedb, - .num_modes = ARRAY_SIZE(fb_modedb), -}; - -static struct i2c_board_info __initdata i2c_devices_3ds[] = { - { - I2C_BOARD_INFO("mc9s08dz60", 0x69), - }, -}; - -static int lcd_power_gpio = -ENXIO; - -static int mc9s08dz60_gpiochip_match(struct gpio_chip *chip, void *data) -{ - return !strcmp(chip->label, data); -} - -static void mx35_3ds_lcd_set_power( - struct plat_lcd_data *pd, unsigned int power) -{ - struct gpio_chip *chip; - - if (!gpio_is_valid(lcd_power_gpio)) { - chip = gpiochip_find( - "mc9s08dz60", mc9s08dz60_gpiochip_match); - if (chip) { - lcd_power_gpio = - chip->base + GPIO_MC9S08DZ60_LCD_ENABLE; - if (gpio_request(lcd_power_gpio, "lcd_power") < 0) { - pr_err("error: gpio already requested!\n"); - lcd_power_gpio = -ENXIO; - } - } else { - pr_err("error: didn't find mc9s08dz60 gpio chip\n"); - } - } - - if (gpio_is_valid(lcd_power_gpio)) - gpio_set_value_cansleep(lcd_power_gpio, power); -} - -static struct plat_lcd_data mx35_3ds_lcd_data = { - .set_power = mx35_3ds_lcd_set_power, -}; - -static struct platform_device mx35_3ds_lcd = { - .name = "platform-lcd", - .dev.platform_data = &mx35_3ds_lcd_data, -}; - -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static struct physmap_flash_data mx35pdk_flash_data = { - .width = 2, -}; - -static struct resource mx35pdk_flash_resource = { - .start = MX35_CS0_BASE_ADDR, - .end = MX35_CS0_BASE_ADDR + SZ_64M - 1, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device mx35pdk_flash = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &mx35pdk_flash_data, - }, - .resource = &mx35pdk_flash_resource, - .num_resources = 1, -}; - -static const struct mxc_nand_platform_data mx35pdk_nand_board_info __initconst = { - .width = 1, - .hw_ecc = 1, - .flash_bbt = 1, -}; - -static struct platform_device *devices[] __initdata = { - &mx35pdk_flash, -}; - -static const iomux_v3_cfg_t mx35pdk_pads[] __initconst = { - /* UART1 */ - MX35_PAD_CTS1__UART1_CTS, - MX35_PAD_RTS1__UART1_RTS, - MX35_PAD_TXD1__UART1_TXD_MUX, - MX35_PAD_RXD1__UART1_RXD_MUX, - /* FEC */ - MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, - MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, - MX35_PAD_FEC_RX_DV__FEC_RX_DV, - MX35_PAD_FEC_COL__FEC_COL, - MX35_PAD_FEC_RDATA0__FEC_RDATA_0, - MX35_PAD_FEC_TDATA0__FEC_TDATA_0, - MX35_PAD_FEC_TX_EN__FEC_TX_EN, - MX35_PAD_FEC_MDC__FEC_MDC, - MX35_PAD_FEC_MDIO__FEC_MDIO, - MX35_PAD_FEC_TX_ERR__FEC_TX_ERR, - MX35_PAD_FEC_RX_ERR__FEC_RX_ERR, - MX35_PAD_FEC_CRS__FEC_CRS, - MX35_PAD_FEC_RDATA1__FEC_RDATA_1, - MX35_PAD_FEC_TDATA1__FEC_TDATA_1, - MX35_PAD_FEC_RDATA2__FEC_RDATA_2, - MX35_PAD_FEC_TDATA2__FEC_TDATA_2, - MX35_PAD_FEC_RDATA3__FEC_RDATA_3, - MX35_PAD_FEC_TDATA3__FEC_TDATA_3, - /* USBOTG */ - MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR, - MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC, - /* USBH1 */ - MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR, - MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC, - /* SDCARD */ - MX35_PAD_SD1_CMD__ESDHC1_CMD, - MX35_PAD_SD1_CLK__ESDHC1_CLK, - MX35_PAD_SD1_DATA0__ESDHC1_DAT0, - MX35_PAD_SD1_DATA1__ESDHC1_DAT1, - MX35_PAD_SD1_DATA2__ESDHC1_DAT2, - MX35_PAD_SD1_DATA3__ESDHC1_DAT3, - /* I2C1 */ - MX35_PAD_I2C1_CLK__I2C1_SCL, - MX35_PAD_I2C1_DAT__I2C1_SDA, - /* Display */ - MX35_PAD_LD0__IPU_DISPB_DAT_0, - MX35_PAD_LD1__IPU_DISPB_DAT_1, - MX35_PAD_LD2__IPU_DISPB_DAT_2, - MX35_PAD_LD3__IPU_DISPB_DAT_3, - MX35_PAD_LD4__IPU_DISPB_DAT_4, - MX35_PAD_LD5__IPU_DISPB_DAT_5, - MX35_PAD_LD6__IPU_DISPB_DAT_6, - MX35_PAD_LD7__IPU_DISPB_DAT_7, - MX35_PAD_LD8__IPU_DISPB_DAT_8, - MX35_PAD_LD9__IPU_DISPB_DAT_9, - MX35_PAD_LD10__IPU_DISPB_DAT_10, - MX35_PAD_LD11__IPU_DISPB_DAT_11, - MX35_PAD_LD12__IPU_DISPB_DAT_12, - MX35_PAD_LD13__IPU_DISPB_DAT_13, - MX35_PAD_LD14__IPU_DISPB_DAT_14, - MX35_PAD_LD15__IPU_DISPB_DAT_15, - MX35_PAD_LD16__IPU_DISPB_DAT_16, - MX35_PAD_LD17__IPU_DISPB_DAT_17, - MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC, - MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK, - MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY, - MX35_PAD_CONTRAST__IPU_DISPB_CONTR, - MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC, - MX35_PAD_D3_REV__IPU_DISPB_D3_REV, - MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS, - /*PMIC IRQ*/ - MX35_PAD_GPIO2_0__GPIO2_0, -}; - -static struct regulator_consumer_supply sw1_consumers[] = { - { - .supply = "cpu_vcc", - } -}; - -static struct regulator_consumer_supply vcam_consumers[] = { - /* sgtl5000 */ - REGULATOR_SUPPLY("VDDA", "0-000a"), -}; - -static struct regulator_init_data sw1_init = { - .constraints = { - .name = "SW1", - .min_uV = 600000, - .max_uV = 1375000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, - .valid_modes_mask = 0, - .always_on = 1, - .boot_on = 1, - }, - .num_consumer_supplies = ARRAY_SIZE(sw1_consumers), - .consumer_supplies = sw1_consumers, -}; - -static struct regulator_init_data sw2_init = { - .constraints = { - .name = "SW2", - .always_on = 1, - .boot_on = 1, - } -}; - -static struct regulator_init_data sw3_init = { - .constraints = { - .name = "SW3", - .always_on = 1, - .boot_on = 1, - } -}; - -static struct regulator_init_data sw4_init = { - .constraints = { - .name = "SW4", - .always_on = 1, - .boot_on = 1, - } -}; - -static struct regulator_init_data viohi_init = { - .constraints = { - .name = "VIOHI", - .boot_on = 1, - } -}; - -static struct regulator_init_data vusb_init = { - .constraints = { - .name = "VUSB", - .boot_on = 1, - } -}; - -static struct regulator_init_data vdig_init = { - .constraints = { - .name = "VDIG", - .boot_on = 1, - } -}; - -static struct regulator_init_data vpll_init = { - .constraints = { - .name = "VPLL", - .boot_on = 1, - } -}; - -static struct regulator_init_data vusb2_init = { - .constraints = { - .name = "VUSB2", - .boot_on = 1, - } -}; - -static struct regulator_init_data vvideo_init = { - .constraints = { - .name = "VVIDEO", - .boot_on = 1 - } -}; - -static struct regulator_init_data vcam_init = { - .constraints = { - .name = "VCAM", - .min_uV = 2500000, - .max_uV = 3000000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_MODE, - .valid_modes_mask = REGULATOR_MODE_FAST | REGULATOR_MODE_NORMAL, - .boot_on = 1 - }, - .num_consumer_supplies = ARRAY_SIZE(vcam_consumers), - .consumer_supplies = vcam_consumers, -}; - -static struct regulator_init_data vgen1_init = { - .constraints = { - .name = "VGEN1", - } -}; - -static struct regulator_init_data vgen2_init = { - .constraints = { - .name = "VGEN2", - .boot_on = 1, - } -}; - -static struct regulator_init_data vgen3_init = { - .constraints = { - .name = "VGEN3", - } -}; - -static struct mc13xxx_regulator_init_data mx35_3ds_regulators[] = { - { .id = MC13892_SW1, .init_data = &sw1_init }, - { .id = MC13892_SW2, .init_data = &sw2_init }, - { .id = MC13892_SW3, .init_data = &sw3_init }, - { .id = MC13892_SW4, .init_data = &sw4_init }, - { .id = MC13892_VIOHI, .init_data = &viohi_init }, - { .id = MC13892_VPLL, .init_data = &vpll_init }, - { .id = MC13892_VDIG, .init_data = &vdig_init }, - { .id = MC13892_VUSB2, .init_data = &vusb2_init }, - { .id = MC13892_VVIDEO, .init_data = &vvideo_init }, - { .id = MC13892_VCAM, .init_data = &vcam_init }, - { .id = MC13892_VGEN1, .init_data = &vgen1_init }, - { .id = MC13892_VGEN2, .init_data = &vgen2_init }, - { .id = MC13892_VGEN3, .init_data = &vgen3_init }, - { .id = MC13892_VUSB, .init_data = &vusb_init }, -}; - -static struct mc13xxx_platform_data mx35_3ds_mc13892_data = { - .flags = MC13XXX_USE_RTC | MC13XXX_USE_TOUCHSCREEN, - .regulators = { - .num_regulators = ARRAY_SIZE(mx35_3ds_regulators), - .regulators = mx35_3ds_regulators, - }, -}; - -#define GPIO_PMIC_INT IMX_GPIO_NR(2, 0) - -static struct i2c_board_info mx35_3ds_i2c_mc13892 = { - - I2C_BOARD_INFO("mc13892", 0x08), - .platform_data = &mx35_3ds_mc13892_data, - /* irq number is run-time assigned */ -}; - -static void __init imx35_3ds_init_mc13892(void) -{ - int ret = gpio_request_one(GPIO_PMIC_INT, GPIOF_DIR_IN, "pmic irq"); - - if (ret) { - pr_err("failed to get pmic irq: %d\n", ret); - return; - } - - mx35_3ds_i2c_mc13892.irq = gpio_to_irq(GPIO_PMIC_INT); - i2c_register_board_info(0, &mx35_3ds_i2c_mc13892, 1); -} - -static int mx35_3ds_otg_init(struct platform_device *pdev) -{ - return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERNAL_PHY); -} - -/* OTG config */ -static const struct fsl_usb2_platform_data usb_otg_pdata __initconst = { - .operating_mode = FSL_USB2_DR_DEVICE, - .phy_mode = FSL_USB2_PHY_UTMI_WIDE, - .workaround = FLS_USB2_WORKAROUND_ENGCM09152, -/* - * ENGCM09152 also requires a hardware change. - * Please check the MX35 Chip Errata document for details. - */ -}; - -static struct mxc_usbh_platform_data otg_pdata __initdata = { - .init = mx35_3ds_otg_init, - .portsc = MXC_EHCI_MODE_UTMI, -}; - -static int mx35_3ds_usbh_init(struct platform_device *pdev) -{ - return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_SINGLE_UNI | - MXC_EHCI_INTERNAL_PHY); -} - -/* USB HOST config */ -static const struct mxc_usbh_platform_data usb_host_pdata __initconst = { - .init = mx35_3ds_usbh_init, - .portsc = MXC_EHCI_MODE_SERIAL, -}; - -static bool otg_mode_host __initdata; - -static int __init mx35_3ds_otg_mode(char *options) -{ - if (!strcmp(options, "host")) - otg_mode_host = true; - else if (!strcmp(options, "device")) - otg_mode_host = false; - else - pr_info("otg_mode neither \"host\" nor \"device\". " - "Defaulting to device\n"); - return 1; -} -__setup("otg_mode=", mx35_3ds_otg_mode); - -static const struct imxi2c_platform_data mx35_3ds_i2c0_data __initconst = { - .bitrate = 100000, -}; - -/* - * Board specific initialization. - */ -static void __init mx35_3ds_init(void) -{ - imx35_soc_init(); - - mxc_iomux_v3_setup_multiple_pads(mx35pdk_pads, ARRAY_SIZE(mx35pdk_pads)); - - imx35_add_fec(NULL); - imx35_add_imx2_wdt(); - imx35_add_mxc_rtc(); - platform_add_devices(devices, ARRAY_SIZE(devices)); - - imx35_add_imx_uart0(&uart_pdata); - - if (otg_mode_host) - imx35_add_mxc_ehci_otg(&otg_pdata); - - imx35_add_mxc_ehci_hs(&usb_host_pdata); - - if (!otg_mode_host) - imx35_add_fsl_usb2_udc(&usb_otg_pdata); - - imx35_add_mxc_nand(&mx35pdk_nand_board_info); - imx35_add_sdhci_esdhc_imx(0, NULL); - - imx35_add_imx_i2c0(&mx35_3ds_i2c0_data); - - i2c_register_board_info( - 0, i2c_devices_3ds, ARRAY_SIZE(i2c_devices_3ds)); - - imx35_add_ipu_core(); -} - -static void __init mx35_3ds_late_init(void) -{ - struct platform_device *imx35_fb_pdev; - - if (mxc_expio_init(MX35_CS5_BASE_ADDR, IMX_GPIO_NR(1, 1))) - pr_warn("Init of the debugboard failed, all " - "devices on the debugboard are unusable.\n"); - - imx35_fb_pdev = imx35_add_mx3_sdc_fb(&mx3fb_pdata); - mx35_3ds_lcd.dev.parent = &imx35_fb_pdev->dev; - platform_device_register(&mx35_3ds_lcd); - - imx35_3ds_init_mc13892(); -} - -static void __init mx35pdk_timer_init(void) -{ - mx35_clocks_init(); -} - -MACHINE_START(MX35_3DS, "Freescale MX35PDK") - /* Maintainer: Freescale Semiconductor, Inc */ - .atag_offset = 0x100, - .map_io = mx35_map_io, - .init_early = imx35_init_early, - .init_irq = mx35_init_irq, - .init_time = mx35pdk_timer_init, - .init_machine = mx35_3ds_init, - .init_late = mx35_3ds_late_init, - .restart = mxc_restart, -MACHINE_END diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c deleted file mode 100644 index 27a3678e0658..000000000000 --- a/arch/arm/mach-imx/mach-pca100.c +++ /dev/null @@ -1,426 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2007 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix - * Copyright (C) 2009 Sascha Hauer (kernel@pengutronix.de) - */ - -#include <linux/platform_device.h> -#include <linux/io.h> -#include <linux/i2c.h> -#include <linux/property.h> -#include <linux/dma-mapping.h> -#include <linux/spi/spi.h> -#include <linux/spi/eeprom.h> -#include <linux/irq.h> -#include <linux/delay.h> -#include <linux/gpio.h> -#include <linux/gpio/machine.h> -#include <linux/usb/otg.h> -#include <linux/usb/ulpi.h> - -#include <asm/mach/arch.h> -#include <asm/mach-types.h> -#include <asm/mach/time.h> - -#include "common.h" -#include "devices-imx27.h" -#include "ehci.h" -#include "hardware.h" -#include "iomux-mx27.h" -#include "ulpi.h" - -#define OTG_PHY_CS_GPIO (GPIO_PORTB + 23) -#define USBH2_PHY_CS_GPIO (GPIO_PORTB + 24) -#define SPI1_SS0 (GPIO_PORTD + 28) -#define SPI1_SS1 (GPIO_PORTD + 27) -#define SD2_CD (GPIO_PORTC + 29) - -static const int pca100_pins[] __initconst = { - /* UART1 */ - PE12_PF_UART1_TXD, - PE13_PF_UART1_RXD, - PE14_PF_UART1_CTS, - PE15_PF_UART1_RTS, - /* SDHC */ - PB4_PF_SD2_D0, - PB5_PF_SD2_D1, - PB6_PF_SD2_D2, - PB7_PF_SD2_D3, - PB8_PF_SD2_CMD, - PB9_PF_SD2_CLK, - SD2_CD | GPIO_GPIO | GPIO_IN, - /* FEC */ - PD0_AIN_FEC_TXD0, - PD1_AIN_FEC_TXD1, - PD2_AIN_FEC_TXD2, - PD3_AIN_FEC_TXD3, - PD4_AOUT_FEC_RX_ER, - PD5_AOUT_FEC_RXD1, - PD6_AOUT_FEC_RXD2, - PD7_AOUT_FEC_RXD3, - PD8_AF_FEC_MDIO, - PD9_AIN_FEC_MDC, - PD10_AOUT_FEC_CRS, - PD11_AOUT_FEC_TX_CLK, - PD12_AOUT_FEC_RXD0, - PD13_AOUT_FEC_RX_DV, - PD14_AOUT_FEC_RX_CLK, - PD15_AOUT_FEC_COL, - PD16_AIN_FEC_TX_ER, - PF23_AIN_FEC_TX_EN, - /* SSI1 */ - PC20_PF_SSI1_FS, - PC21_PF_SSI1_RXD, - PC22_PF_SSI1_TXD, - PC23_PF_SSI1_CLK, - /* onboard I2C */ - PC5_PF_I2C2_SDA, - PC6_PF_I2C2_SCL, - /* external I2C */ - PD17_PF_I2C_DATA, - PD18_PF_I2C_CLK, - /* SPI1 */ - PD25_PF_CSPI1_RDY, - PD29_PF_CSPI1_SCLK, - PD30_PF_CSPI1_MISO, - PD31_PF_CSPI1_MOSI, - /* OTG */ - OTG_PHY_CS_GPIO | GPIO_GPIO | GPIO_OUT, - PC7_PF_USBOTG_DATA5, - PC8_PF_USBOTG_DATA6, - PC9_PF_USBOTG_DATA0, - PC10_PF_USBOTG_DATA2, - PC11_PF_USBOTG_DATA1, - PC12_PF_USBOTG_DATA4, - PC13_PF_USBOTG_DATA3, - PE0_PF_USBOTG_NXT, - PE1_PF_USBOTG_STP, - PE2_PF_USBOTG_DIR, - PE24_PF_USBOTG_CLK, - PE25_PF_USBOTG_DATA7, - /* USBH2 */ - USBH2_PHY_CS_GPIO | GPIO_GPIO | GPIO_OUT, - PA0_PF_USBH2_CLK, - PA1_PF_USBH2_DIR, - PA2_PF_USBH2_DATA7, - PA3_PF_USBH2_NXT, - PA4_PF_USBH2_STP, - PD19_AF_USBH2_DATA4, - PD20_AF_USBH2_DATA3, - PD21_AF_USBH2_DATA6, - PD22_AF_USBH2_DATA0, - PD23_AF_USBH2_DATA2, - PD24_AF_USBH2_DATA1, - PD26_AF_USBH2_DATA5, - /* display */ - PA5_PF_LSCLK, - PA6_PF_LD0, - PA7_PF_LD1, - PA8_PF_LD2, - PA9_PF_LD3, - PA10_PF_LD4, - PA11_PF_LD5, - PA12_PF_LD6, - PA13_PF_LD7, - PA14_PF_LD8, - PA15_PF_LD9, - PA16_PF_LD10, - PA17_PF_LD11, - PA18_PF_LD12, - PA19_PF_LD13, - PA20_PF_LD14, - PA21_PF_LD15, - PA22_PF_LD16, - PA23_PF_LD17, - PA26_PF_PS, - PA28_PF_HSYNC, - PA29_PF_VSYNC, - PA31_PF_OE_ACD, - /* free GPIO */ - GPIO_PORTC | 31 | GPIO_GPIO | GPIO_IN, /* GPIO0_IRQ */ - GPIO_PORTC | 25 | GPIO_GPIO | GPIO_IN, /* GPIO1_IRQ */ - GPIO_PORTE | 5 | GPIO_GPIO | GPIO_IN, /* GPIO2_IRQ */ -}; - -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static const struct mxc_nand_platform_data -pca100_nand_board_info __initconst = { - .width = 1, - .hw_ecc = 1, -}; - -static const struct imxi2c_platform_data pca100_i2c1_data __initconst = { - .bitrate = 100000, -}; - -static const struct property_entry board_eeprom_properties[] = { - PROPERTY_ENTRY_U32("pagesize", 32), - { } -}; - -static struct i2c_board_info pca100_i2c_devices[] = { - { - I2C_BOARD_INFO("24c32", 0x52), /* E0=0, E1=1, E2=0 */ - .properties = board_eeprom_properties, - }, { - I2C_BOARD_INFO("pcf8563", 0x51), - }, { - I2C_BOARD_INFO("lm75", 0x4a), - } -}; - -static struct spi_eeprom at25320 = { - .name = "at25320an", - .byte_len = 4096, - .page_size = 32, - .flags = EE_ADDR2, -}; - -static struct spi_board_info pca100_spi_board_info[] __initdata = { - { - .modalias = "at25", - .max_speed_hz = 30000, - .bus_num = 0, - .chip_select = 1, - .platform_data = &at25320, - }, -}; - -static struct gpiod_lookup_table pca100_spi0_gpiod_table = { - .dev_id = "imx27-cspi.0", /* Actual device name for spi0 */ - .table = { - /* - * The i.MX27 has the i.MX21 GPIO controller, port D is - * bank 3 and thus named "imx21-gpio.3". - * SPI1_SS0 is GPIO_PORTD + 28 - * SPI1_SS1 is GPIO_PORTD + 27 - */ - GPIO_LOOKUP_IDX("imx21-gpio.3", 28, "cs", 0, GPIO_ACTIVE_LOW), - GPIO_LOOKUP_IDX("imx21-gpio.3", 27, "cs", 1, GPIO_ACTIVE_LOW), - { }, - }, -}; - -static void pca100_ac97_warm_reset(struct snd_ac97 *ac97) -{ - mxc_gpio_mode(GPIO_PORTC | 20 | GPIO_GPIO | GPIO_OUT); - gpio_set_value(GPIO_PORTC + 20, 1); - udelay(2); - gpio_set_value(GPIO_PORTC + 20, 0); - mxc_gpio_mode(PC20_PF_SSI1_FS); - msleep(2); -} - -static void pca100_ac97_cold_reset(struct snd_ac97 *ac97) -{ - mxc_gpio_mode(GPIO_PORTC | 20 | GPIO_GPIO | GPIO_OUT); /* FS */ - gpio_set_value(GPIO_PORTC + 20, 0); - mxc_gpio_mode(GPIO_PORTC | 22 | GPIO_GPIO | GPIO_OUT); /* TX */ - gpio_set_value(GPIO_PORTC + 22, 0); - mxc_gpio_mode(GPIO_PORTC | 28 | GPIO_GPIO | GPIO_OUT); /* reset */ - gpio_set_value(GPIO_PORTC + 28, 0); - udelay(10); - gpio_set_value(GPIO_PORTC + 28, 1); - mxc_gpio_mode(PC20_PF_SSI1_FS); - mxc_gpio_mode(PC22_PF_SSI1_TXD); - msleep(2); -} - -static const struct imx_ssi_platform_data pca100_ssi_pdata __initconst = { - .ac97_reset = pca100_ac97_cold_reset, - .ac97_warm_reset = pca100_ac97_warm_reset, - .flags = IMX_SSI_USE_AC97, -}; - -static int pca100_sdhc2_init(struct device *dev, irq_handler_t detect_irq, - void *data) -{ - int ret; - - ret = request_irq(gpio_to_irq(IMX_GPIO_NR(3, 29)), detect_irq, - IRQF_TRIGGER_FALLING, "imx-mmc-detect", data); - if (ret) - printk(KERN_ERR - "pca100: Failed to request irq for sd/mmc detection\n"); - - return ret; -} - -static void pca100_sdhc2_exit(struct device *dev, void *data) -{ - free_irq(gpio_to_irq(IMX_GPIO_NR(3, 29)), data); -} - -static const struct imxmmc_platform_data sdhc_pdata __initconst = { - .init = pca100_sdhc2_init, - .exit = pca100_sdhc2_exit, -}; - -static int otg_phy_init(struct platform_device *pdev) -{ - gpio_set_value(OTG_PHY_CS_GPIO, 0); - - mdelay(10); - - return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI); -} - -static struct mxc_usbh_platform_data otg_pdata __initdata = { - .init = otg_phy_init, - .portsc = MXC_EHCI_MODE_ULPI, -}; - -static int usbh2_phy_init(struct platform_device *pdev) -{ - gpio_set_value(USBH2_PHY_CS_GPIO, 0); - - mdelay(10); - - return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI); -} - -static struct mxc_usbh_platform_data usbh2_pdata __initdata = { - .init = usbh2_phy_init, - .portsc = MXC_EHCI_MODE_ULPI, -}; - -static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { - .operating_mode = FSL_USB2_DR_DEVICE, - .phy_mode = FSL_USB2_PHY_ULPI, -}; - -static bool otg_mode_host __initdata; - -static int __init pca100_otg_mode(char *options) -{ - if (!strcmp(options, "host")) - otg_mode_host = true; - else if (!strcmp(options, "device")) - otg_mode_host = false; - else - pr_info("otg_mode neither \"host\" nor \"device\". " - "Defaulting to device\n"); - return 1; -} -__setup("otg_mode=", pca100_otg_mode); - -/* framebuffer info */ -static struct imx_fb_videomode pca100_fb_modes[] = { - { - .mode = { - .name = "EMERGING-ETV570G0DHU", - .refresh = 60, - .xres = 640, - .yres = 480, - .pixclock = 39722, /* in ps (25.175 MHz) */ - .hsync_len = 30, - .left_margin = 114, - .right_margin = 16, - .vsync_len = 3, - .upper_margin = 32, - .lower_margin = 0, - }, - /* - * TFT - * Pixel pol active high - * HSYNC active low - * VSYNC active low - * use HSYNC for ACD count - * line clock disable while idle - * always enable line clock even if no data - */ - .pcr = 0xf0c08080, - .bpp = 16, - }, -}; - -static const struct imx_fb_platform_data pca100_fb_data __initconst = { - .mode = pca100_fb_modes, - .num_modes = ARRAY_SIZE(pca100_fb_modes), - - .pwmr = 0x00A903FF, - .lscr1 = 0x00120300, - .dmacr = 0x00020010, -}; - -static void __init pca100_init(void) -{ - int ret; - - imx27_soc_init(); - - ret = mxc_gpio_setup_multiple_pins(pca100_pins, - ARRAY_SIZE(pca100_pins), "PCA100"); - if (ret) - printk(KERN_ERR "pca100: Failed to setup pins (%d)\n", ret); - - imx27_add_imx_uart0(&uart_pdata); - - imx27_add_mxc_nand(&pca100_nand_board_info); - - /* only the i2c master 1 is used on this CPU card */ - i2c_register_board_info(1, pca100_i2c_devices, - ARRAY_SIZE(pca100_i2c_devices)); - - imx27_add_imx_i2c(1, &pca100_i2c1_data); - - mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_IN); - mxc_gpio_mode(GPIO_PORTD | 27 | GPIO_GPIO | GPIO_IN); - spi_register_board_info(pca100_spi_board_info, - ARRAY_SIZE(pca100_spi_board_info)); - imx27_add_spi_imx0(&pca100_spi0_gpiod_table); - - imx27_add_imx_fb(&pca100_fb_data); - - imx27_add_fec(NULL); - imx27_add_imx2_wdt(); - imx27_add_mxc_w1(); -} - -static void __init pca100_late_init(void) -{ - imx27_add_imx_ssi(0, &pca100_ssi_pdata); - - imx27_add_mxc_mmc(1, &sdhc_pdata); - - gpio_request(OTG_PHY_CS_GPIO, "usb-otg-cs"); - gpio_direction_output(OTG_PHY_CS_GPIO, 1); - gpio_request(USBH2_PHY_CS_GPIO, "usb-host2-cs"); - gpio_direction_output(USBH2_PHY_CS_GPIO, 1); - - if (otg_mode_host) { - otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | - ULPI_OTG_DRVVBUS_EXT); - - if (otg_pdata.otg) - imx27_add_mxc_ehci_otg(&otg_pdata); - } else { - gpio_set_value(OTG_PHY_CS_GPIO, 0); - imx27_add_fsl_usb2_udc(&otg_device_pdata); - } - - usbh2_pdata.otg = imx_otg_ulpi_create( - ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); - - if (usbh2_pdata.otg) - imx27_add_mxc_ehci_hs(2, &usbh2_pdata); -} - -static void __init pca100_timer_init(void) -{ - mx27_clocks_init(26000000); -} - -MACHINE_START(PCA100, "phyCARD-i.MX27") - .atag_offset = 0x100, - .map_io = mx27_map_io, - .init_early = imx27_init_early, - .init_irq = mx27_init_irq, - .init_machine = pca100_init, - .init_late = pca100_late_init, - .init_time = pca100_timer_init, - .restart = mxc_restart, -MACHINE_END diff --git a/arch/arm/mach-imx/mach-pcm037.c b/arch/arm/mach-imx/mach-pcm037.c deleted file mode 100644 index c7d23e9d4f8b..000000000000 --- a/arch/arm/mach-imx/mach-pcm037.c +++ /dev/null @@ -1,585 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (C) 2008 Sascha Hauer, Pengutronix - */ - -#include <linux/types.h> -#include <linux/init.h> -#include <linux/dma-mapping.h> -#include <linux/platform_device.h> -#include <linux/mtd/physmap.h> -#include <linux/mtd/plat-ram.h> -#include <linux/memory.h> -#include <linux/gpio.h> -#include <linux/smsc911x.h> -#include <linux/interrupt.h> -#include <linux/i2c.h> -#include <linux/property.h> -#include <linux/delay.h> -#include <linux/spi/spi.h> -#include <linux/irq.h> -#include <linux/can/platform/sja1000.h> -#include <linux/usb/otg.h> -#include <linux/usb/ulpi.h> -#include <linux/gfp.h> -#include <linux/regulator/machine.h> -#include <linux/regulator/fixed.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> -#include <asm/mach/map.h> - -#include "common.h" -#include "devices-imx31.h" -#include "ehci.h" -#include "hardware.h" -#include "iomux-mx3.h" -#include "pcm037.h" -#include "ulpi.h" - -static enum pcm037_board_variant pcm037_instance = PCM037_PCM970; - -static int __init pcm037_variant_setup(char *str) -{ - if (!strcmp("eet", str)) - pcm037_instance = PCM037_EET; - else if (strcmp("pcm970", str)) - pr_warn("Unknown pcm037 baseboard variant %s\n", str); - - return 1; -} - -/* Supported values: "pcm970" (default) and "eet" */ -__setup("pcm037_variant=", pcm037_variant_setup); - -enum pcm037_board_variant pcm037_variant(void) -{ - return pcm037_instance; -} - -/* UART1 with RTS/CTS handshake signals */ -static unsigned int pcm037_uart1_handshake_pins[] = { - MX31_PIN_CTS1__CTS1, - MX31_PIN_RTS1__RTS1, - MX31_PIN_TXD1__TXD1, - MX31_PIN_RXD1__RXD1, -}; - -/* UART1 without RTS/CTS handshake signals */ -static unsigned int pcm037_uart1_pins[] = { - MX31_PIN_TXD1__TXD1, - MX31_PIN_RXD1__RXD1, -}; - -static unsigned int pcm037_pins[] = { - /* I2C */ - MX31_PIN_CSPI2_MOSI__SCL, - MX31_PIN_CSPI2_MISO__SDA, - MX31_PIN_CSPI2_SS2__I2C3_SDA, - MX31_PIN_CSPI2_SCLK__I2C3_SCL, - /* SDHC1 */ - MX31_PIN_SD1_DATA3__SD1_DATA3, - MX31_PIN_SD1_DATA2__SD1_DATA2, - MX31_PIN_SD1_DATA1__SD1_DATA1, - MX31_PIN_SD1_DATA0__SD1_DATA0, - MX31_PIN_SD1_CLK__SD1_CLK, - MX31_PIN_SD1_CMD__SD1_CMD, - IOMUX_MODE(MX31_PIN_SCK6, IOMUX_CONFIG_GPIO), /* card detect */ - IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_GPIO), /* write protect */ - /* SPI1 */ - MX31_PIN_CSPI1_MOSI__MOSI, - MX31_PIN_CSPI1_MISO__MISO, - MX31_PIN_CSPI1_SCLK__SCLK, - MX31_PIN_CSPI1_SPI_RDY__SPI_RDY, - MX31_PIN_CSPI1_SS0__SS0, - MX31_PIN_CSPI1_SS1__SS1, - MX31_PIN_CSPI1_SS2__SS2, - /* UART2 */ - MX31_PIN_TXD2__TXD2, - MX31_PIN_RXD2__RXD2, - MX31_PIN_CTS2__CTS2, - MX31_PIN_RTS2__RTS2, - /* UART3 */ - MX31_PIN_CSPI3_MOSI__RXD3, - MX31_PIN_CSPI3_MISO__TXD3, - MX31_PIN_CSPI3_SCLK__RTS3, - MX31_PIN_CSPI3_SPI_RDY__CTS3, - /* LAN9217 irq pin */ - IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO), - /* Onewire */ - MX31_PIN_BATT_LINE__OWIRE, - /* Framebuffer */ - MX31_PIN_LD0__LD0, - MX31_PIN_LD1__LD1, - MX31_PIN_LD2__LD2, - MX31_PIN_LD3__LD3, - MX31_PIN_LD4__LD4, - MX31_PIN_LD5__LD5, - MX31_PIN_LD6__LD6, - MX31_PIN_LD7__LD7, - MX31_PIN_LD8__LD8, - MX31_PIN_LD9__LD9, - MX31_PIN_LD10__LD10, - MX31_PIN_LD11__LD11, - MX31_PIN_LD12__LD12, - MX31_PIN_LD13__LD13, - MX31_PIN_LD14__LD14, - MX31_PIN_LD15__LD15, - MX31_PIN_LD16__LD16, - MX31_PIN_LD17__LD17, - MX31_PIN_VSYNC3__VSYNC3, - MX31_PIN_HSYNC__HSYNC, - MX31_PIN_FPSHIFT__FPSHIFT, - MX31_PIN_DRDY0__DRDY0, - MX31_PIN_D3_REV__D3_REV, - MX31_PIN_CONTRAST__CONTRAST, - MX31_PIN_D3_SPL__D3_SPL, - MX31_PIN_D3_CLS__D3_CLS, - MX31_PIN_LCS0__GPIO3_23, - /* GPIO */ - IOMUX_MODE(MX31_PIN_ATA_DMACK, IOMUX_CONFIG_GPIO), - /* OTG */ - MX31_PIN_USBOTG_DATA0__USBOTG_DATA0, - MX31_PIN_USBOTG_DATA1__USBOTG_DATA1, - MX31_PIN_USBOTG_DATA2__USBOTG_DATA2, - MX31_PIN_USBOTG_DATA3__USBOTG_DATA3, - MX31_PIN_USBOTG_DATA4__USBOTG_DATA4, - MX31_PIN_USBOTG_DATA5__USBOTG_DATA5, - MX31_PIN_USBOTG_DATA6__USBOTG_DATA6, - MX31_PIN_USBOTG_DATA7__USBOTG_DATA7, - MX31_PIN_USBOTG_CLK__USBOTG_CLK, - MX31_PIN_USBOTG_DIR__USBOTG_DIR, - MX31_PIN_USBOTG_NXT__USBOTG_NXT, - MX31_PIN_USBOTG_STP__USBOTG_STP, - /* USB host 2 */ - IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC), - IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC), -}; - -static struct physmap_flash_data pcm037_flash_data = { - .width = 2, -}; - -static struct resource pcm037_flash_resource = { - .start = 0xa0000000, - .end = 0xa1ffffff, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device pcm037_flash = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &pcm037_flash_data, - }, - .resource = &pcm037_flash_resource, - .num_resources = 1, -}; - -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static struct resource smsc911x_resources[] = { - { - .start = MX31_CS1_BASE_ADDR + 0x300, - .end = MX31_CS1_BASE_ADDR + 0x300 + SZ_64K - 1, - .flags = IORESOURCE_MEM, - }, { - /* irq number is run-time assigned */ - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, - }, -}; - -static struct smsc911x_platform_config smsc911x_info = { - .flags = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY | - SMSC911X_SAVE_MAC_ADDRESS, - .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, - .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN, - .phy_interface = PHY_INTERFACE_MODE_MII, -}; - -static struct platform_device pcm037_eth = { - .name = "smsc911x", - .id = -1, - .num_resources = ARRAY_SIZE(smsc911x_resources), - .resource = smsc911x_resources, - .dev = { - .platform_data = &smsc911x_info, - }, -}; - -static struct platdata_mtd_ram pcm038_sram_data = { - .bankwidth = 2, -}; - -static struct resource pcm038_sram_resource = { - .start = MX31_CS4_BASE_ADDR, - .end = MX31_CS4_BASE_ADDR + 512 * 1024 - 1, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device pcm037_sram_device = { - .name = "mtd-ram", - .id = 0, - .dev = { - .platform_data = &pcm038_sram_data, - }, - .num_resources = 1, - .resource = &pcm038_sram_resource, -}; - -static const struct mxc_nand_platform_data -pcm037_nand_board_info __initconst = { - .width = 1, - .hw_ecc = 1, -}; - -static const struct imxi2c_platform_data pcm037_i2c1_data __initconst = { - .bitrate = 100000, -}; - -static const struct imxi2c_platform_data pcm037_i2c2_data __initconst = { - .bitrate = 20000, -}; - -static const struct property_entry board_eeprom_properties[] = { - PROPERTY_ENTRY_U32("pagesize", 32), - { } -}; - -static struct i2c_board_info pcm037_i2c_devices[] = { - { - I2C_BOARD_INFO("24c32", 0x52), /* E0=0, E1=1, E2=0 */ - .properties = board_eeprom_properties, - }, { - I2C_BOARD_INFO("pcf8563", 0x51), - } -}; - -/* Not connected by default */ -#ifdef PCM970_SDHC_RW_SWITCH -static int pcm970_sdhc1_get_ro(struct device *dev) -{ - return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_SFS6)); -} -#endif - -#define SDHC1_GPIO_WP IOMUX_TO_GPIO(MX31_PIN_SFS6) -#define SDHC1_GPIO_DET IOMUX_TO_GPIO(MX31_PIN_SCK6) - -static int pcm970_sdhc1_init(struct device *dev, irq_handler_t detect_irq, - void *data) -{ - int ret; - - ret = gpio_request(SDHC1_GPIO_DET, "sdhc-detect"); - if (ret) - return ret; - - gpio_direction_input(SDHC1_GPIO_DET); - -#ifdef PCM970_SDHC_RW_SWITCH - ret = gpio_request(SDHC1_GPIO_WP, "sdhc-wp"); - if (ret) - goto err_gpio_free; - gpio_direction_input(SDHC1_GPIO_WP); -#endif - - ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_SCK6)), detect_irq, - IRQF_TRIGGER_FALLING, "sdhc-detect", data); - if (ret) - goto err_gpio_free_2; - - return 0; - -err_gpio_free_2: -#ifdef PCM970_SDHC_RW_SWITCH - gpio_free(SDHC1_GPIO_WP); -err_gpio_free: -#endif - gpio_free(SDHC1_GPIO_DET); - - return ret; -} - -static void pcm970_sdhc1_exit(struct device *dev, void *data) -{ - free_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_SCK6)), data); - gpio_free(SDHC1_GPIO_DET); - gpio_free(SDHC1_GPIO_WP); -} - -static const struct imxmmc_platform_data sdhc_pdata __initconst = { -#ifdef PCM970_SDHC_RW_SWITCH - .get_ro = pcm970_sdhc1_get_ro, -#endif - .init = pcm970_sdhc1_init, - .exit = pcm970_sdhc1_exit, -}; - -static struct platform_device *devices[] __initdata = { - &pcm037_flash, - &pcm037_sram_device, -}; - -static const struct fb_videomode fb_modedb[] = { - { - /* 240x320 @ 60 Hz Sharp */ - .name = "Sharp-LQ035Q7DH06-QVGA", - .refresh = 60, - .xres = 240, - .yres = 320, - .pixclock = 185925, - .left_margin = 9, - .right_margin = 16, - .upper_margin = 7, - .lower_margin = 9, - .hsync_len = 1, - .vsync_len = 1, - .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE | - FB_SYNC_CLK_INVERT | FB_SYNC_CLK_IDLE_EN, - .vmode = FB_VMODE_NONINTERLACED, - .flag = 0, - }, { - /* 240x320 @ 60 Hz */ - .name = "TX090", - .refresh = 60, - .xres = 240, - .yres = 320, - .pixclock = 38255, - .left_margin = 144, - .right_margin = 0, - .upper_margin = 7, - .lower_margin = 40, - .hsync_len = 96, - .vsync_len = 1, - .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH, - .vmode = FB_VMODE_NONINTERLACED, - .flag = 0, - }, { - /* 240x320 @ 60 Hz */ - .name = "CMEL-OLED", - .refresh = 60, - .xres = 240, - .yres = 320, - .pixclock = 185925, - .left_margin = 9, - .right_margin = 16, - .upper_margin = 7, - .lower_margin = 9, - .hsync_len = 1, - .vsync_len = 1, - .sync = FB_SYNC_OE_ACT_HIGH | FB_SYNC_CLK_INVERT, - .vmode = FB_VMODE_NONINTERLACED, - .flag = 0, - }, -}; - -static struct mx3fb_platform_data mx3fb_pdata = { - .name = "Sharp-LQ035Q7DH06-QVGA", - .mode = fb_modedb, - .num_modes = ARRAY_SIZE(fb_modedb), -}; - -static struct resource pcm970_sja1000_resources[] = { - { - .start = MX31_CS5_BASE_ADDR, - .end = MX31_CS5_BASE_ADDR + 0x100 - 1, - .flags = IORESOURCE_MEM, - }, { - /* irq number is run-time assigned */ - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, - }, -}; - -static struct sja1000_platform_data pcm970_sja1000_platform_data = { - .osc_freq = 16000000, - .ocr = OCR_TX1_PULLDOWN | OCR_TX0_PUSHPULL, - .cdr = CDR_CBP, -}; - -static struct platform_device pcm970_sja1000 = { - .name = "sja1000_platform", - .dev = { - .platform_data = &pcm970_sja1000_platform_data, - }, - .resource = pcm970_sja1000_resources, - .num_resources = ARRAY_SIZE(pcm970_sja1000_resources), -}; - -static int pcm037_otg_init(struct platform_device *pdev) -{ - return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI); -} - -static struct mxc_usbh_platform_data otg_pdata __initdata = { - .init = pcm037_otg_init, - .portsc = MXC_EHCI_MODE_ULPI, -}; - -static int pcm037_usbh2_init(struct platform_device *pdev) -{ - return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI); -} - -static struct mxc_usbh_platform_data usbh2_pdata __initdata = { - .init = pcm037_usbh2_init, - .portsc = MXC_EHCI_MODE_ULPI, -}; - -static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { - .operating_mode = FSL_USB2_DR_DEVICE, - .phy_mode = FSL_USB2_PHY_ULPI, -}; - -static bool otg_mode_host __initdata; - -static int __init pcm037_otg_mode(char *options) -{ - if (!strcmp(options, "host")) - otg_mode_host = true; - else if (!strcmp(options, "device")) - otg_mode_host = false; - else - pr_info("otg_mode neither \"host\" nor \"device\". " - "Defaulting to device\n"); - return 1; -} -__setup("otg_mode=", pcm037_otg_mode); - -static struct regulator_consumer_supply dummy_supplies[] = { - REGULATOR_SUPPLY("vdd33a", "smsc911x"), - REGULATOR_SUPPLY("vddvario", "smsc911x"), -}; - -/* - * Board specific initialization. - */ -static void __init pcm037_init(void) -{ - imx31_soc_init(); - - regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); - - mxc_iomux_set_gpr(MUX_PGP_UH2, 1); - - mxc_iomux_setup_multiple_pins(pcm037_pins, ARRAY_SIZE(pcm037_pins), - "pcm037"); - -#define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS \ - | PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) - - mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, H2_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, H2_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, H2_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_STP, H2_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, H2_PAD_CFG); /* USBH2_DATA0 */ - mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, H2_PAD_CFG); /* USBH2_DATA1 */ - mxc_iomux_set_pad(MX31_PIN_SRXD6, H2_PAD_CFG); /* USBH2_DATA2 */ - mxc_iomux_set_pad(MX31_PIN_STXD6, H2_PAD_CFG); /* USBH2_DATA3 */ - mxc_iomux_set_pad(MX31_PIN_SFS3, H2_PAD_CFG); /* USBH2_DATA4 */ - mxc_iomux_set_pad(MX31_PIN_SCK3, H2_PAD_CFG); /* USBH2_DATA5 */ - mxc_iomux_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG); /* USBH2_DATA6 */ - mxc_iomux_set_pad(MX31_PIN_STXD3, H2_PAD_CFG); /* USBH2_DATA7 */ - - if (pcm037_variant() == PCM037_EET) - mxc_iomux_setup_multiple_pins(pcm037_uart1_pins, - ARRAY_SIZE(pcm037_uart1_pins), "pcm037_uart1"); - else - mxc_iomux_setup_multiple_pins(pcm037_uart1_handshake_pins, - ARRAY_SIZE(pcm037_uart1_handshake_pins), - "pcm037_uart1"); - - platform_add_devices(devices, ARRAY_SIZE(devices)); - - imx31_add_imx2_wdt(); - imx31_add_imx_uart0(&uart_pdata); - /* XXX: should't this have .flags = 0 (i.e. no RTSCTS) on PCM037_EET? */ - imx31_add_imx_uart1(&uart_pdata); - imx31_add_imx_uart2(&uart_pdata); - - imx31_add_mxc_w1(); - - /* I2C adapters and devices */ - i2c_register_board_info(1, pcm037_i2c_devices, - ARRAY_SIZE(pcm037_i2c_devices)); - - imx31_add_imx_i2c1(&pcm037_i2c1_data); - imx31_add_imx_i2c2(&pcm037_i2c2_data); - - imx31_add_mxc_nand(&pcm037_nand_board_info); - imx31_add_ipu_core(); - imx31_add_mx3_sdc_fb(&mx3fb_pdata); - - if (otg_mode_host) { - otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | - ULPI_OTG_DRVVBUS_EXT); - if (otg_pdata.otg) - imx31_add_mxc_ehci_otg(&otg_pdata); - } - - usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | - ULPI_OTG_DRVVBUS_EXT); - if (usbh2_pdata.otg) - imx31_add_mxc_ehci_hs(2, &usbh2_pdata); - - if (!otg_mode_host) - imx31_add_fsl_usb2_udc(&otg_device_pdata); -} - -static void __init pcm037_timer_init(void) -{ - mx31_clocks_init(26000000); -} - -static void __init pcm037_init_late(void) -{ - int ret; - - /* LAN9217 IRQ pin */ - ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1), "lan9217-irq"); - if (!ret) { - gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)); - smsc911x_resources[1].start = - gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)); - smsc911x_resources[1].end = - gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)); - platform_device_register(&pcm037_eth); - } else { - pr_warn("could not get LAN irq gpio\n"); - } - - imx31_add_mxc_mmc(0, &sdhc_pdata); - - pcm970_sja1000_resources[1].start = - gpio_to_irq(IOMUX_TO_GPIO(IOMUX_PIN(48, 105))); - pcm970_sja1000_resources[1].end = - gpio_to_irq(IOMUX_TO_GPIO(IOMUX_PIN(48, 105))); - platform_device_register(&pcm970_sja1000); - - pcm037_eet_init_devices(); -} - -MACHINE_START(PCM037, "Phytec Phycore pcm037") - /* Maintainer: Pengutronix */ - .atag_offset = 0x100, - .map_io = mx31_map_io, - .init_early = imx31_init_early, - .init_irq = mx31_init_irq, - .init_time = pcm037_timer_init, - .init_machine = pcm037_init, - .init_late = pcm037_init_late, - .restart = mxc_restart, -MACHINE_END diff --git a/arch/arm/mach-imx/mach-pcm037_eet.c b/arch/arm/mach-imx/mach-pcm037_eet.c deleted file mode 100644 index 8b0e03a595c1..000000000000 --- a/arch/arm/mach-imx/mach-pcm037_eet.c +++ /dev/null @@ -1,166 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2009 - * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de> - */ -#include <linux/gpio.h> -#include <linux/input.h> -#include <linux/platform_device.h> -#include <linux/spi/spi.h> - -#include <asm/mach-types.h> - -#include "pcm037.h" -#include "common.h" -#include "devices-imx31.h" -#include "iomux-mx3.h" - -static unsigned int pcm037_eet_pins[] = { - /* Reserve and hardwire GPIO 57 high - S6E63D6 chipselect */ - IOMUX_MODE(MX31_PIN_KEY_COL7, IOMUX_CONFIG_GPIO), - /* GPIO keys */ - IOMUX_MODE(MX31_PIN_GPIO1_0, IOMUX_CONFIG_GPIO), /* 0 */ - IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO), /* 1 */ - IOMUX_MODE(MX31_PIN_GPIO1_2, IOMUX_CONFIG_GPIO), /* 2 */ - IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO), /* 3 */ - IOMUX_MODE(MX31_PIN_SVEN0, IOMUX_CONFIG_GPIO), /* 32 */ - IOMUX_MODE(MX31_PIN_STX0, IOMUX_CONFIG_GPIO), /* 33 */ - IOMUX_MODE(MX31_PIN_SRX0, IOMUX_CONFIG_GPIO), /* 34 */ - IOMUX_MODE(MX31_PIN_SIMPD0, IOMUX_CONFIG_GPIO), /* 35 */ - IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_GPIO), /* 38 */ - IOMUX_MODE(MX31_PIN_CTS1, IOMUX_CONFIG_GPIO), /* 39 */ - IOMUX_MODE(MX31_PIN_KEY_ROW4, IOMUX_CONFIG_GPIO), /* 50 */ - IOMUX_MODE(MX31_PIN_KEY_ROW5, IOMUX_CONFIG_GPIO), /* 51 */ - IOMUX_MODE(MX31_PIN_KEY_ROW6, IOMUX_CONFIG_GPIO), /* 52 */ - IOMUX_MODE(MX31_PIN_KEY_ROW7, IOMUX_CONFIG_GPIO), /* 53 */ - - /* LEDs */ - IOMUX_MODE(MX31_PIN_DTR_DTE1, IOMUX_CONFIG_GPIO), /* 44 */ - IOMUX_MODE(MX31_PIN_DSR_DTE1, IOMUX_CONFIG_GPIO), /* 45 */ - IOMUX_MODE(MX31_PIN_KEY_COL5, IOMUX_CONFIG_GPIO), /* 55 */ - IOMUX_MODE(MX31_PIN_KEY_COL6, IOMUX_CONFIG_GPIO), /* 56 */ -}; - -/* SPI */ -static struct spi_board_info pcm037_spi_dev[] = { - { - .modalias = "dac124s085", - .max_speed_hz = 400000, - .bus_num = 0, - .chip_select = 1, /* Index in pcm037_spi1_cs[] */ - .mode = SPI_CPHA, - }, -}; - -/* GPIO-keys input device */ -static struct gpio_keys_button pcm037_gpio_keys[] = { - { - .type = EV_KEY, - .code = KEY_L, - .gpio = 0, - .desc = "Wheel Manual", - .wakeup = 0, - }, { - .type = EV_KEY, - .code = KEY_A, - .gpio = 1, - .desc = "Wheel AF", - .wakeup = 0, - }, { - .type = EV_KEY, - .code = KEY_V, - .gpio = 2, - .desc = "Wheel View", - .wakeup = 0, - }, { - .type = EV_KEY, - .code = KEY_M, - .gpio = 3, - .desc = "Wheel Menu", - .wakeup = 0, - }, { - .type = EV_KEY, - .code = KEY_UP, - .gpio = 32, - .desc = "Nav Pad Up", - .wakeup = 0, - }, { - .type = EV_KEY, - .code = KEY_RIGHT, - .gpio = 33, - .desc = "Nav Pad Right", - .wakeup = 0, - }, { - .type = EV_KEY, - .code = KEY_DOWN, - .gpio = 34, - .desc = "Nav Pad Down", - .wakeup = 0, - }, { - .type = EV_KEY, - .code = KEY_LEFT, - .gpio = 35, - .desc = "Nav Pad Left", - .wakeup = 0, - }, { - .type = EV_KEY, - .code = KEY_ENTER, - .gpio = 38, - .desc = "Nav Pad Ok", - .wakeup = 0, - }, { - .type = EV_KEY, - .code = KEY_O, - .gpio = 39, - .desc = "Wheel Off", - .wakeup = 0, - }, { - .type = EV_KEY, - .code = BTN_FORWARD, - .gpio = 50, - .desc = "Focus Forward", - .wakeup = 0, - }, { - .type = EV_KEY, - .code = BTN_BACK, - .gpio = 51, - .desc = "Focus Backward", - .wakeup = 0, - }, { - .type = EV_KEY, - .code = BTN_MIDDLE, - .gpio = 52, - .desc = "Release Half", - .wakeup = 0, - }, { - .type = EV_KEY, - .code = BTN_EXTRA, - .gpio = 53, - .desc = "Release Full", - .wakeup = 0, - }, -}; - -static const struct gpio_keys_platform_data - pcm037_gpio_keys_platform_data __initconst = { - .buttons = pcm037_gpio_keys, - .nbuttons = ARRAY_SIZE(pcm037_gpio_keys), - .rep = 0, /* No auto-repeat */ -}; - -int __init pcm037_eet_init_devices(void) -{ - if (pcm037_variant() != PCM037_EET) - return 0; - - mxc_iomux_setup_multiple_pins(pcm037_eet_pins, - ARRAY_SIZE(pcm037_eet_pins), "pcm037_eet"); - - /* SPI */ - spi_register_board_info(pcm037_spi_dev, ARRAY_SIZE(pcm037_spi_dev)); - imx31_add_spi_imx0(NULL); - - imx_add_gpio_keys(&pcm037_gpio_keys_platform_data); - - return 0; -} diff --git a/arch/arm/mach-imx/mach-pcm043.c b/arch/arm/mach-imx/mach-pcm043.c deleted file mode 100644 index 017a50113005..000000000000 --- a/arch/arm/mach-imx/mach-pcm043.c +++ /dev/null @@ -1,412 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (C) 2009 Sascha Hauer, Pengutronix - */ - -#include <linux/types.h> -#include <linux/init.h> - -#include <linux/platform_device.h> -#include <linux/mtd/physmap.h> -#include <linux/mtd/plat-ram.h> -#include <linux/memory.h> -#include <linux/gpio.h> -#include <linux/gpio/machine.h> -#include <linux/smc911x.h> -#include <linux/interrupt.h> -#include <linux/delay.h> -#include <linux/i2c.h> -#include <linux/property.h> -#include <linux/usb/otg.h> -#include <linux/usb/ulpi.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> -#include <asm/mach/map.h> - -#include "common.h" -#include "devices-imx35.h" -#include "ehci.h" -#include "hardware.h" -#include "iomux-mx35.h" -#include "ulpi.h" - -static const struct fb_videomode fb_modedb[] = { - { - /* 240x320 @ 60 Hz */ - .name = "Sharp-LQ035Q7", - .refresh = 60, - .xres = 240, - .yres = 320, - .pixclock = 185925, - .left_margin = 9, - .right_margin = 16, - .upper_margin = 7, - .lower_margin = 9, - .hsync_len = 1, - .vsync_len = 1, - .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE | FB_SYNC_CLK_INVERT | FB_SYNC_CLK_IDLE_EN, - .vmode = FB_VMODE_NONINTERLACED, - .flag = 0, - }, { - /* 240x320 @ 60 Hz */ - .name = "TX090", - .refresh = 60, - .xres = 240, - .yres = 320, - .pixclock = 38255, - .left_margin = 144, - .right_margin = 0, - .upper_margin = 7, - .lower_margin = 40, - .hsync_len = 96, - .vsync_len = 1, - .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH, - .vmode = FB_VMODE_NONINTERLACED, - .flag = 0, - }, -}; - -static struct mx3fb_platform_data mx3fb_pdata __initdata = { - .name = "Sharp-LQ035Q7", - .mode = fb_modedb, - .num_modes = ARRAY_SIZE(fb_modedb), -}; - -static struct physmap_flash_data pcm043_flash_data = { - .width = 2, -}; - -static struct resource pcm043_flash_resource = { - .start = 0xa0000000, - .end = 0xa1ffffff, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device pcm043_flash = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &pcm043_flash_data, - }, - .resource = &pcm043_flash_resource, - .num_resources = 1, -}; - -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static const struct imxi2c_platform_data pcm043_i2c0_data __initconst = { - .bitrate = 50000, -}; - -static const struct property_entry board_eeprom_properties[] = { - PROPERTY_ENTRY_U32("pagesize", 32), - { } -}; - -static struct i2c_board_info pcm043_i2c_devices[] = { - { - I2C_BOARD_INFO("24c32", 0x52), /* E0=0, E1=1, E2=0 */ - .properties = board_eeprom_properties, - }, { - I2C_BOARD_INFO("pcf8563", 0x51), - }, -}; - -static struct platform_device *devices[] __initdata = { - &pcm043_flash, -}; - -static const iomux_v3_cfg_t pcm043_pads[] __initconst = { - /* UART1 */ - MX35_PAD_CTS1__UART1_CTS, - MX35_PAD_RTS1__UART1_RTS, - MX35_PAD_TXD1__UART1_TXD_MUX, - MX35_PAD_RXD1__UART1_RXD_MUX, - /* UART2 */ - MX35_PAD_CTS2__UART2_CTS, - MX35_PAD_RTS2__UART2_RTS, - MX35_PAD_TXD2__UART2_TXD_MUX, - MX35_PAD_RXD2__UART2_RXD_MUX, - /* FEC */ - MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, - MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, - MX35_PAD_FEC_RX_DV__FEC_RX_DV, - MX35_PAD_FEC_COL__FEC_COL, - MX35_PAD_FEC_RDATA0__FEC_RDATA_0, - MX35_PAD_FEC_TDATA0__FEC_TDATA_0, - MX35_PAD_FEC_TX_EN__FEC_TX_EN, - MX35_PAD_FEC_MDC__FEC_MDC, - MX35_PAD_FEC_MDIO__FEC_MDIO, - MX35_PAD_FEC_TX_ERR__FEC_TX_ERR, - MX35_PAD_FEC_RX_ERR__FEC_RX_ERR, - MX35_PAD_FEC_CRS__FEC_CRS, - MX35_PAD_FEC_RDATA1__FEC_RDATA_1, - MX35_PAD_FEC_TDATA1__FEC_TDATA_1, - MX35_PAD_FEC_RDATA2__FEC_RDATA_2, - MX35_PAD_FEC_TDATA2__FEC_TDATA_2, - MX35_PAD_FEC_RDATA3__FEC_RDATA_3, - MX35_PAD_FEC_TDATA3__FEC_TDATA_3, - /* I2C1 */ - MX35_PAD_I2C1_CLK__I2C1_SCL, - MX35_PAD_I2C1_DAT__I2C1_SDA, - /* Display */ - MX35_PAD_LD0__IPU_DISPB_DAT_0, - MX35_PAD_LD1__IPU_DISPB_DAT_1, - MX35_PAD_LD2__IPU_DISPB_DAT_2, - MX35_PAD_LD3__IPU_DISPB_DAT_3, - MX35_PAD_LD4__IPU_DISPB_DAT_4, - MX35_PAD_LD5__IPU_DISPB_DAT_5, - MX35_PAD_LD6__IPU_DISPB_DAT_6, - MX35_PAD_LD7__IPU_DISPB_DAT_7, - MX35_PAD_LD8__IPU_DISPB_DAT_8, - MX35_PAD_LD9__IPU_DISPB_DAT_9, - MX35_PAD_LD10__IPU_DISPB_DAT_10, - MX35_PAD_LD11__IPU_DISPB_DAT_11, - MX35_PAD_LD12__IPU_DISPB_DAT_12, - MX35_PAD_LD13__IPU_DISPB_DAT_13, - MX35_PAD_LD14__IPU_DISPB_DAT_14, - MX35_PAD_LD15__IPU_DISPB_DAT_15, - MX35_PAD_LD16__IPU_DISPB_DAT_16, - MX35_PAD_LD17__IPU_DISPB_DAT_17, - MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC, - MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK, - MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY, - MX35_PAD_CONTRAST__IPU_DISPB_CONTR, - MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC, - MX35_PAD_D3_REV__IPU_DISPB_D3_REV, - MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS, - /* gpio */ - MX35_PAD_ATA_CS0__GPIO2_6, - /* USB host */ - MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR, - MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC, - /* SSI */ - MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS, - MX35_PAD_STXD4__AUDMUX_AUD4_TXD, - MX35_PAD_SRXD4__AUDMUX_AUD4_RXD, - MX35_PAD_SCK4__AUDMUX_AUD4_TXC, - /* CAN2 */ - MX35_PAD_TX5_RX0__CAN2_TXCAN, - MX35_PAD_TX4_RX1__CAN2_RXCAN, - /* esdhc */ - MX35_PAD_SD1_CMD__ESDHC1_CMD, - MX35_PAD_SD1_CLK__ESDHC1_CLK, - MX35_PAD_SD1_DATA0__ESDHC1_DAT0, - MX35_PAD_SD1_DATA1__ESDHC1_DAT1, - MX35_PAD_SD1_DATA2__ESDHC1_DAT2, - MX35_PAD_SD1_DATA3__ESDHC1_DAT3, - MX35_PAD_ATA_DATA10__GPIO2_23, /* WriteProtect */ - MX35_PAD_ATA_DATA11__GPIO2_24, /* CardDetect */ -}; - -#define AC97_GPIO_TXFS IMX_GPIO_NR(2, 31) -#define AC97_GPIO_TXD IMX_GPIO_NR(2, 28) -#define AC97_GPIO_RESET IMX_GPIO_NR(2, 0) - -static void pcm043_ac97_warm_reset(struct snd_ac97 *ac97) -{ - iomux_v3_cfg_t txfs_gpio = MX35_PAD_STXFS4__GPIO2_31; - iomux_v3_cfg_t txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS; - int ret; - - ret = gpio_request(AC97_GPIO_TXFS, "SSI"); - if (ret) { - printk("failed to get GPIO_TXFS: %d\n", ret); - return; - } - - mxc_iomux_v3_setup_pad(txfs_gpio); - - /* warm reset */ - gpio_direction_output(AC97_GPIO_TXFS, 1); - udelay(2); - gpio_set_value(AC97_GPIO_TXFS, 0); - - gpio_free(AC97_GPIO_TXFS); - mxc_iomux_v3_setup_pad(txfs); -} - -static void pcm043_ac97_cold_reset(struct snd_ac97 *ac97) -{ - iomux_v3_cfg_t txfs_gpio = MX35_PAD_STXFS4__GPIO2_31; - iomux_v3_cfg_t txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS; - iomux_v3_cfg_t txd_gpio = MX35_PAD_STXD4__GPIO2_28; - iomux_v3_cfg_t txd = MX35_PAD_STXD4__AUDMUX_AUD4_TXD; - iomux_v3_cfg_t reset_gpio = MX35_PAD_SD2_CMD__GPIO2_0; - int ret; - - ret = gpio_request(AC97_GPIO_TXFS, "SSI"); - if (ret) - goto err1; - - ret = gpio_request(AC97_GPIO_TXD, "SSI"); - if (ret) - goto err2; - - ret = gpio_request(AC97_GPIO_RESET, "SSI"); - if (ret) - goto err3; - - mxc_iomux_v3_setup_pad(txfs_gpio); - mxc_iomux_v3_setup_pad(txd_gpio); - mxc_iomux_v3_setup_pad(reset_gpio); - - gpio_direction_output(AC97_GPIO_TXFS, 0); - gpio_direction_output(AC97_GPIO_TXD, 0); - - /* cold reset */ - gpio_direction_output(AC97_GPIO_RESET, 0); - udelay(10); - gpio_direction_output(AC97_GPIO_RESET, 1); - - mxc_iomux_v3_setup_pad(txd); - mxc_iomux_v3_setup_pad(txfs); - - gpio_free(AC97_GPIO_RESET); -err3: - gpio_free(AC97_GPIO_TXD); -err2: - gpio_free(AC97_GPIO_TXFS); -err1: - if (ret) - printk("%s failed with %d\n", __func__, ret); - mdelay(1); -} - -static const struct imx_ssi_platform_data pcm043_ssi_pdata __initconst = { - .ac97_reset = pcm043_ac97_cold_reset, - .ac97_warm_reset = pcm043_ac97_warm_reset, - .flags = IMX_SSI_USE_AC97, -}; - -static const struct mxc_nand_platform_data -pcm037_nand_board_info __initconst = { - .width = 1, - .hw_ecc = 1, -}; - -static int pcm043_otg_init(struct platform_device *pdev) -{ - return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI); -} - -static struct mxc_usbh_platform_data otg_pdata __initdata = { - .init = pcm043_otg_init, - .portsc = MXC_EHCI_MODE_UTMI, -}; - -static int pcm043_usbh1_init(struct platform_device *pdev) -{ - return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_SINGLE_UNI | - MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN); -} - -static const struct mxc_usbh_platform_data usbh1_pdata __initconst = { - .init = pcm043_usbh1_init, - .portsc = MXC_EHCI_MODE_SERIAL, -}; - -static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { - .operating_mode = FSL_USB2_DR_DEVICE, - .phy_mode = FSL_USB2_PHY_UTMI, -}; - -static bool otg_mode_host __initdata; - -static int __init pcm043_otg_mode(char *options) -{ - if (!strcmp(options, "host")) - otg_mode_host = true; - else if (!strcmp(options, "device")) - otg_mode_host = false; - else - pr_info("otg_mode neither \"host\" nor \"device\". " - "Defaulting to device\n"); - return 1; -} -__setup("otg_mode=", pcm043_otg_mode); - -static struct esdhc_platform_data sd1_pdata = { - .wp_type = ESDHC_WP_GPIO, - .cd_type = ESDHC_CD_GPIO, -}; - -static struct gpiod_lookup_table sd1_gpio_table = { - .dev_id = "sdhci-esdhc-imx35.0", - .table = { - /* Card detect: bank 2 offset 24 */ - GPIO_LOOKUP("imx35-gpio.2", 24, "cd", GPIO_ACTIVE_LOW), - /* Write protect: bank 2 offset 23 */ - GPIO_LOOKUP("imx35-gpio.2", 23, "wp", GPIO_ACTIVE_LOW), - { }, - }, -}; - -/* - * Board specific initialization. - */ -static void __init pcm043_init(void) -{ - imx35_soc_init(); - - mxc_iomux_v3_setup_multiple_pads(pcm043_pads, ARRAY_SIZE(pcm043_pads)); - - imx35_add_fec(NULL); - platform_add_devices(devices, ARRAY_SIZE(devices)); - imx35_add_imx2_wdt(); - - imx35_add_imx_uart0(&uart_pdata); - imx35_add_mxc_nand(&pcm037_nand_board_info); - - imx35_add_imx_uart1(&uart_pdata); - - i2c_register_board_info(0, pcm043_i2c_devices, - ARRAY_SIZE(pcm043_i2c_devices)); - - imx35_add_imx_i2c0(&pcm043_i2c0_data); - - imx35_add_ipu_core(); - imx35_add_mx3_sdc_fb(&mx3fb_pdata); - - if (otg_mode_host) { - otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | - ULPI_OTG_DRVVBUS_EXT); - if (otg_pdata.otg) - imx35_add_mxc_ehci_otg(&otg_pdata); - } - imx35_add_mxc_ehci_hs(&usbh1_pdata); - - if (!otg_mode_host) - imx35_add_fsl_usb2_udc(&otg_device_pdata); - - imx35_add_flexcan1(); -} - -static void __init pcm043_late_init(void) -{ - imx35_add_imx_ssi(0, &pcm043_ssi_pdata); - - gpiod_add_lookup_table(&sd1_gpio_table); - imx35_add_sdhci_esdhc_imx(0, &sd1_pdata); -} - -static void __init pcm043_timer_init(void) -{ - mx35_clocks_init(); -} - -MACHINE_START(PCM043, "Phytec Phycore pcm043") - /* Maintainer: Pengutronix */ - .atag_offset = 0x100, - .map_io = mx35_map_io, - .init_early = imx35_init_early, - .init_irq = mx35_init_irq, - .init_time = pcm043_timer_init, - .init_machine = pcm043_init, - .init_late = pcm043_late_init, - .restart = mxc_restart, -MACHINE_END diff --git a/arch/arm/mach-imx/mach-qong.c b/arch/arm/mach-imx/mach-qong.c deleted file mode 100644 index 5b362da2dc09..000000000000 --- a/arch/arm/mach-imx/mach-qong.c +++ /dev/null @@ -1,262 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (C) 2009 Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com> - */ - -#include <linux/types.h> -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/memory.h> -#include <linux/platform_device.h> -#include <linux/mtd/physmap.h> -#include <linux/mtd/platnand.h> -#include <linux/gpio.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> -#include <asm/mach/map.h> -#include <asm/page.h> -#include <asm/setup.h> - -#include "common.h" -#include "devices-imx31.h" -#include "hardware.h" -#include "iomux-mx3.h" - -/* FPGA defines */ -#define QONG_FPGA_VERSION(major, minor, rev) \ - (((major & 0xF) << 12) | ((minor & 0xF) << 8) | (rev & 0xFF)) - -#define QONG_FPGA_BASEADDR MX31_CS1_BASE_ADDR -#define QONG_FPGA_PERIPH_SIZE (1 << 24) - -#define QONG_FPGA_CTRL_BASEADDR QONG_FPGA_BASEADDR -#define QONG_FPGA_CTRL_SIZE 0x10 -/* FPGA control registers */ -#define QONG_FPGA_CTRL_VERSION 0x00 - -#define QONG_DNET_ID 1 -#define QONG_DNET_BASEADDR \ - (QONG_FPGA_BASEADDR + QONG_DNET_ID * QONG_FPGA_PERIPH_SIZE) -#define QONG_DNET_SIZE 0x00001000 - -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static int uart_pins[] = { - MX31_PIN_CTS1__CTS1, - MX31_PIN_RTS1__RTS1, - MX31_PIN_TXD1__TXD1, - MX31_PIN_RXD1__RXD1 -}; - -static inline void __init mxc_init_imx_uart(void) -{ - mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins), - "uart-0"); - imx31_add_imx_uart0(&uart_pdata); -} - -static struct resource dnet_resources[] = { - { - .name = "dnet-memory", - .start = QONG_DNET_BASEADDR, - .end = QONG_DNET_BASEADDR + QONG_DNET_SIZE - 1, - .flags = IORESOURCE_MEM, - }, { - /* irq number is run-time assigned */ - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device dnet_device = { - .name = "dnet", - .id = -1, - .num_resources = ARRAY_SIZE(dnet_resources), - .resource = dnet_resources, -}; - -static int __init qong_init_dnet(void) -{ - int ret; - - dnet_resources[1].start = - gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1)); - dnet_resources[1].end = - gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1)); - ret = platform_device_register(&dnet_device); - return ret; -} - -/* MTD NOR flash */ - -static struct physmap_flash_data qong_flash_data = { - .width = 2, -}; - -static struct resource qong_flash_resource = { - .start = MX31_CS0_BASE_ADDR, - .end = MX31_CS0_BASE_ADDR + SZ_128M - 1, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device qong_nor_mtd_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &qong_flash_data, - }, - .resource = &qong_flash_resource, - .num_resources = 1, -}; - -static void qong_init_nor_mtd(void) -{ - (void)platform_device_register(&qong_nor_mtd_device); -} - -/* - * Hardware specific access to control-lines - */ -static void qong_nand_cmd_ctrl(struct nand_chip *nand_chip, int cmd, - unsigned int ctrl) -{ - if (cmd == NAND_CMD_NONE) - return; - - if (ctrl & NAND_CLE) - writeb(cmd, nand_chip->legacy.IO_ADDR_W + (1 << 24)); - else - writeb(cmd, nand_chip->legacy.IO_ADDR_W + (1 << 23)); -} - -/* - * Read the Device Ready pin. - */ -static int qong_nand_device_ready(struct nand_chip *chip) -{ - return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_NFRB)); -} - -static void qong_nand_select_chip(struct nand_chip *chip, int cs) -{ - if (cs >= 0) - gpio_set_value(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), 0); - else - gpio_set_value(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), 1); -} - -static struct platform_nand_data qong_nand_data = { - .chip = { - .nr_chips = 1, - .chip_delay = 20, - .options = 0, - }, - .ctrl = { - .cmd_ctrl = qong_nand_cmd_ctrl, - .dev_ready = qong_nand_device_ready, - .select_chip = qong_nand_select_chip, - } -}; - -static struct resource qong_nand_resource = { - .start = MX31_CS3_BASE_ADDR, - .end = MX31_CS3_BASE_ADDR + SZ_32M - 1, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device qong_nand_device = { - .name = "gen_nand", - .id = -1, - .dev = { - .platform_data = &qong_nand_data, - }, - .num_resources = 1, - .resource = &qong_nand_resource, -}; - -static void __init qong_init_nand_mtd(void) -{ - /* init CS */ - imx_writel(0x00004f00, MX31_IO_ADDRESS(MX31_WEIM_CSCRxU(3))); - imx_writel(0x20013b31, MX31_IO_ADDRESS(MX31_WEIM_CSCRxL(3))); - imx_writel(0x00020800, MX31_IO_ADDRESS(MX31_WEIM_CSCRxA(3))); - - mxc_iomux_set_gpr(MUX_SDCTL_CSD1_SEL, true); - - /* enable pin */ - mxc_iomux_mode(IOMUX_MODE(MX31_PIN_NFCE_B, IOMUX_CONFIG_GPIO)); - if (!gpio_request(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), "nand_enable")) - gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), 0); - - /* ready/busy pin */ - mxc_iomux_mode(IOMUX_MODE(MX31_PIN_NFRB, IOMUX_CONFIG_GPIO)); - if (!gpio_request(IOMUX_TO_GPIO(MX31_PIN_NFRB), "nand_rdy")) - gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_NFRB)); - - /* write protect pin */ - mxc_iomux_mode(IOMUX_MODE(MX31_PIN_NFWP_B, IOMUX_CONFIG_GPIO)); - if (!gpio_request(IOMUX_TO_GPIO(MX31_PIN_NFWP_B), "nand_wp")) - gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_NFWP_B)); - - platform_device_register(&qong_nand_device); -} - -static void __init qong_init_fpga(void) -{ - void __iomem *regs; - u32 fpga_ver; - - regs = ioremap(QONG_FPGA_CTRL_BASEADDR, QONG_FPGA_CTRL_SIZE); - if (!regs) { - printk(KERN_ERR "%s: failed to map registers, aborting.\n", - __func__); - return; - } - - fpga_ver = readl(regs + QONG_FPGA_CTRL_VERSION); - iounmap(regs); - printk(KERN_INFO "Qong FPGA version %d.%d.%d\n", - (fpga_ver & 0xF000) >> 12, - (fpga_ver & 0x0F00) >> 8, fpga_ver & 0x00FF); - if (fpga_ver < QONG_FPGA_VERSION(0, 8, 7)) { - printk(KERN_ERR "qong: Unexpected FPGA version, FPGA-based " - "devices won't be registered!\n"); - return; - } - - /* register FPGA-based devices */ - qong_init_nand_mtd(); - qong_init_dnet(); -} - -/* - * Board specific initialization. - */ -static void __init qong_init(void) -{ - imx31_soc_init(); - - mxc_init_imx_uart(); - qong_init_nor_mtd(); - imx31_add_imx2_wdt(); -} - -static void __init qong_timer_init(void) -{ - mx31_clocks_init(26000000); -} - -MACHINE_START(QONG, "Dave/DENX QongEVB-LITE") - /* Maintainer: DENX Software Engineering GmbH */ - .atag_offset = 0x100, - .map_io = mx31_map_io, - .init_early = imx31_init_early, - .init_irq = mx31_init_irq, - .init_time = qong_timer_init, - .init_machine = qong_init, - .init_late = qong_init_fpga, - .restart = mxc_restart, -MACHINE_END diff --git a/arch/arm/mach-imx/mach-vpr200.c b/arch/arm/mach-imx/mach-vpr200.c deleted file mode 100644 index fae5a41b5f6c..000000000000 --- a/arch/arm/mach-imx/mach-vpr200.c +++ /dev/null @@ -1,306 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright (C) 2009 Marc Kleine-Budde, Pengutronix - * Copyright 2010 Creative Product Design - * - * Derived from mx35 3stack. - * Original author: Fabio Estevam <fabio.estevam@freescale.com> - */ - -#include <linux/types.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/mtd/physmap.h> -#include <linux/memory.h> -#include <linux/gpio.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/time.h> - -#include <linux/i2c.h> -#include <linux/mfd/mc13xxx.h> - -#include "common.h" -#include "devices-imx35.h" -#include "ehci.h" -#include "hardware.h" -#include "iomux-mx35.h" - -#define GPIO_LCDPWR IMX_GPIO_NR(1, 2) -#define GPIO_PMIC_INT IMX_GPIO_NR(2, 0) - -#define GPIO_BUTTON1 IMX_GPIO_NR(1, 4) -#define GPIO_BUTTON2 IMX_GPIO_NR(1, 5) -#define GPIO_BUTTON3 IMX_GPIO_NR(1, 7) -#define GPIO_BUTTON4 IMX_GPIO_NR(1, 8) -#define GPIO_BUTTON5 IMX_GPIO_NR(1, 9) -#define GPIO_BUTTON6 IMX_GPIO_NR(1, 10) -#define GPIO_BUTTON7 IMX_GPIO_NR(1, 11) -#define GPIO_BUTTON8 IMX_GPIO_NR(1, 12) - -static const struct fb_videomode fb_modedb[] = { - { - /* 800x480 @ 60 Hz */ - .name = "PT0708048", - .refresh = 60, - .xres = 800, - .yres = 480, - .pixclock = KHZ2PICOS(33260), - .left_margin = 50, - .right_margin = 156, - .upper_margin = 10, - .lower_margin = 10, - .hsync_len = 1, /* note: DE only display */ - .vsync_len = 1, /* note: DE only display */ - .sync = FB_SYNC_CLK_IDLE_EN | FB_SYNC_OE_ACT_HIGH, - .vmode = FB_VMODE_NONINTERLACED, - .flag = 0, - }, { - /* 800x480 @ 60 Hz */ - .name = "CTP-CLAA070LC0ACW", - .refresh = 60, - .xres = 800, - .yres = 480, - .pixclock = KHZ2PICOS(27000), - .left_margin = 50, - .right_margin = 50, /* whole line should have 900 clocks */ - .upper_margin = 10, - .lower_margin = 10, /* whole frame should have 500 lines */ - .hsync_len = 1, /* note: DE only display */ - .vsync_len = 1, /* note: DE only display */ - .sync = FB_SYNC_CLK_IDLE_EN | FB_SYNC_OE_ACT_HIGH, - .vmode = FB_VMODE_NONINTERLACED, - .flag = 0, - } -}; - -static struct mx3fb_platform_data mx3fb_pdata __initdata = { - .name = "PT0708048", - .mode = fb_modedb, - .num_modes = ARRAY_SIZE(fb_modedb), -}; - -static struct physmap_flash_data vpr200_flash_data = { - .width = 2, -}; - -static struct resource vpr200_flash_resource = { - .start = MX35_CS0_BASE_ADDR, - .end = MX35_CS0_BASE_ADDR + SZ_64M - 1, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device vpr200_flash = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &vpr200_flash_data, - }, - .resource = &vpr200_flash_resource, - .num_resources = 1, -}; - -static const struct mxc_nand_platform_data - vpr200_nand_board_info __initconst = { - .width = 1, - .hw_ecc = 1, - .flash_bbt = 1, -}; - -#define VPR_KEY_DEBOUNCE 500 -static struct gpio_keys_button vpr200_gpio_keys_table[] = { - {KEY_F2, GPIO_BUTTON1, 1, "vpr-keys: F2", 0, VPR_KEY_DEBOUNCE}, - {KEY_F3, GPIO_BUTTON2, 1, "vpr-keys: F3", 0, VPR_KEY_DEBOUNCE}, - {KEY_F4, GPIO_BUTTON3, 1, "vpr-keys: F4", 0, VPR_KEY_DEBOUNCE}, - {KEY_F5, GPIO_BUTTON4, 1, "vpr-keys: F5", 0, VPR_KEY_DEBOUNCE}, - {KEY_F6, GPIO_BUTTON5, 1, "vpr-keys: F6", 0, VPR_KEY_DEBOUNCE}, - {KEY_F7, GPIO_BUTTON6, 1, "vpr-keys: F7", 0, VPR_KEY_DEBOUNCE}, - {KEY_F8, GPIO_BUTTON7, 1, "vpr-keys: F8", 1, VPR_KEY_DEBOUNCE}, - {KEY_F9, GPIO_BUTTON8, 1, "vpr-keys: F9", 1, VPR_KEY_DEBOUNCE}, -}; - -static const struct gpio_keys_platform_data - vpr200_gpio_keys_data __initconst = { - .buttons = vpr200_gpio_keys_table, - .nbuttons = ARRAY_SIZE(vpr200_gpio_keys_table), -}; - -static struct mc13xxx_platform_data vpr200_pmic = { - .flags = MC13XXX_USE_ADC | MC13XXX_USE_TOUCHSCREEN, -}; - -static const struct imxi2c_platform_data vpr200_i2c0_data __initconst = { - .bitrate = 50000, -}; - -static struct i2c_board_info vpr200_i2c_devices[] = { - { - I2C_BOARD_INFO("24c02", 0x50), /* E0=0, E1=0, E2=0 */ - }, { - I2C_BOARD_INFO("mc13892", 0x08), - .platform_data = &vpr200_pmic, - /* irq number is run-time assigned */ - } -}; - -static const iomux_v3_cfg_t vpr200_pads[] __initconst = { - /* UART1 */ - MX35_PAD_TXD1__UART1_TXD_MUX, - MX35_PAD_RXD1__UART1_RXD_MUX, - /* UART3 */ - MX35_PAD_ATA_DATA10__UART3_RXD_MUX, - MX35_PAD_ATA_DATA11__UART3_TXD_MUX, - /* FEC */ - MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, - MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, - MX35_PAD_FEC_RX_DV__FEC_RX_DV, - MX35_PAD_FEC_COL__FEC_COL, - MX35_PAD_FEC_RDATA0__FEC_RDATA_0, - MX35_PAD_FEC_TDATA0__FEC_TDATA_0, - MX35_PAD_FEC_TX_EN__FEC_TX_EN, - MX35_PAD_FEC_MDC__FEC_MDC, - MX35_PAD_FEC_MDIO__FEC_MDIO, - MX35_PAD_FEC_TX_ERR__FEC_TX_ERR, - MX35_PAD_FEC_RX_ERR__FEC_RX_ERR, - MX35_PAD_FEC_CRS__FEC_CRS, - MX35_PAD_FEC_RDATA1__FEC_RDATA_1, - MX35_PAD_FEC_TDATA1__FEC_TDATA_1, - MX35_PAD_FEC_RDATA2__FEC_RDATA_2, - MX35_PAD_FEC_TDATA2__FEC_TDATA_2, - MX35_PAD_FEC_RDATA3__FEC_RDATA_3, - MX35_PAD_FEC_TDATA3__FEC_TDATA_3, - /* Display */ - MX35_PAD_LD0__IPU_DISPB_DAT_0, - MX35_PAD_LD1__IPU_DISPB_DAT_1, - MX35_PAD_LD2__IPU_DISPB_DAT_2, - MX35_PAD_LD3__IPU_DISPB_DAT_3, - MX35_PAD_LD4__IPU_DISPB_DAT_4, - MX35_PAD_LD5__IPU_DISPB_DAT_5, - MX35_PAD_LD6__IPU_DISPB_DAT_6, - MX35_PAD_LD7__IPU_DISPB_DAT_7, - MX35_PAD_LD8__IPU_DISPB_DAT_8, - MX35_PAD_LD9__IPU_DISPB_DAT_9, - MX35_PAD_LD10__IPU_DISPB_DAT_10, - MX35_PAD_LD11__IPU_DISPB_DAT_11, - MX35_PAD_LD12__IPU_DISPB_DAT_12, - MX35_PAD_LD13__IPU_DISPB_DAT_13, - MX35_PAD_LD14__IPU_DISPB_DAT_14, - MX35_PAD_LD15__IPU_DISPB_DAT_15, - MX35_PAD_LD16__IPU_DISPB_DAT_16, - MX35_PAD_LD17__IPU_DISPB_DAT_17, - MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK, - MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY, - MX35_PAD_CONTRAST__IPU_DISPB_CONTR, - /* LCD Enable */ - MX35_PAD_D3_VSYNC__GPIO1_2, - /* USBOTG */ - MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR, - MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC, - /* SDCARD */ - MX35_PAD_SD1_CMD__ESDHC1_CMD, - MX35_PAD_SD1_CLK__ESDHC1_CLK, - MX35_PAD_SD1_DATA0__ESDHC1_DAT0, - MX35_PAD_SD1_DATA1__ESDHC1_DAT1, - MX35_PAD_SD1_DATA2__ESDHC1_DAT2, - MX35_PAD_SD1_DATA3__ESDHC1_DAT3, - /* PMIC */ - MX35_PAD_GPIO2_0__GPIO2_0, - /* GPIO keys */ - MX35_PAD_SCKR__GPIO1_4, - MX35_PAD_COMPARE__GPIO1_5, - MX35_PAD_SCKT__GPIO1_7, - MX35_PAD_FST__GPIO1_8, - MX35_PAD_HCKT__GPIO1_9, - MX35_PAD_TX5_RX0__GPIO1_10, - MX35_PAD_TX4_RX1__GPIO1_11, - MX35_PAD_TX3_RX2__GPIO1_12, -}; - -/* USB Device config */ -static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { - .operating_mode = FSL_USB2_DR_DEVICE, - .phy_mode = FSL_USB2_PHY_UTMI, - .workaround = FLS_USB2_WORKAROUND_ENGCM09152, -}; - -static int vpr200_usbh_init(struct platform_device *pdev) -{ - return mx35_initialize_usb_hw(pdev->id, - MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY); -} - -/* USB HOST config */ -static const struct mxc_usbh_platform_data usb_host_pdata __initconst = { - .init = vpr200_usbh_init, - .portsc = MXC_EHCI_MODE_SERIAL, -}; - -static struct platform_device *devices[] __initdata = { - &vpr200_flash, -}; - -/* - * Board specific initialization. - */ -static void __init vpr200_board_init(void) -{ - imx35_soc_init(); - - mxc_iomux_v3_setup_multiple_pads(vpr200_pads, ARRAY_SIZE(vpr200_pads)); - - imx35_add_fec(NULL); - imx35_add_imx2_wdt(); - - imx35_add_imx_uart0(NULL); - imx35_add_imx_uart2(NULL); - - imx35_add_ipu_core(); - imx35_add_mx3_sdc_fb(&mx3fb_pdata); - - imx35_add_fsl_usb2_udc(&otg_device_pdata); - imx35_add_mxc_ehci_hs(&usb_host_pdata); - - imx35_add_mxc_nand(&vpr200_nand_board_info); - imx35_add_sdhci_esdhc_imx(0, NULL); -} - -static void __init vpr200_late_init(void) -{ - imx_add_gpio_keys(&vpr200_gpio_keys_data); - - platform_add_devices(devices, ARRAY_SIZE(devices)); - - if (0 != gpio_request(GPIO_LCDPWR, "LCDPWR")) - printk(KERN_WARNING "vpr200: Couldn't get LCDPWR gpio\n"); - else - gpio_direction_output(GPIO_LCDPWR, 0); - - if (0 != gpio_request(GPIO_PMIC_INT, "PMIC_INT")) - printk(KERN_WARNING "vpr200: Couldn't get PMIC_INT gpio\n"); - else - gpio_direction_input(GPIO_PMIC_INT); - - vpr200_i2c_devices[1].irq = gpio_to_irq(GPIO_PMIC_INT); - i2c_register_board_info(0, vpr200_i2c_devices, - ARRAY_SIZE(vpr200_i2c_devices)); - - imx35_add_imx_i2c0(&vpr200_i2c0_data); -} - -static void __init vpr200_timer_init(void) -{ - mx35_clocks_init(); -} - -MACHINE_START(VPR200, "VPR200") - /* Maintainer: Creative Product Design */ - .map_io = mx35_map_io, - .init_early = imx35_init_early, - .init_irq = mx35_init_irq, - .init_time = vpr200_timer_init, - .init_machine = vpr200_board_init, - .init_late = vpr200_late_init, - .restart = mxc_restart, -MACHINE_END diff --git a/arch/arm/mach-imx/mm-imx21.c b/arch/arm/mach-imx/mm-imx21.c deleted file mode 100644 index b834026e4615..000000000000 --- a/arch/arm/mach-imx/mm-imx21.c +++ /dev/null @@ -1,84 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * arch/arm/mach-imx/mm-imx21.c - * - * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) - */ - -#include <linux/mm.h> -#include <linux/init.h> -#include <linux/pinctrl/machine.h> -#include <asm/mach/map.h> - -#include "common.h" -#include "devices/devices-common.h" -#include "hardware.h" -#include "iomux-v1.h" - -/* MX21 memory map definition */ -static struct map_desc imx21_io_desc[] __initdata = { - /* - * this fixed mapping covers: - * - AIPI1 - * - AIPI2 - * - AITC - * - ROM Patch - * - and some reserved space - */ - imx_map_entry(MX21, AIPI, MT_DEVICE), - /* - * this fixed mapping covers: - * - CSI - * - ATA - */ - imx_map_entry(MX21, SAHB1, MT_DEVICE), - /* - * this fixed mapping covers: - * - EMI - */ - imx_map_entry(MX21, X_MEMC, MT_DEVICE), -}; - -/* - * Initialize the memory map. It is called during the - * system startup to create static physical to virtual - * memory map for the IO modules. - */ -void __init mx21_map_io(void) -{ - iotable_init(imx21_io_desc, ARRAY_SIZE(imx21_io_desc)); -} - -void __init imx21_init_early(void) -{ - mxc_set_cpu_type(MXC_CPU_MX21); - imx_iomuxv1_init(MX21_IO_ADDRESS(MX21_GPIO_BASE_ADDR), - MX21_NUM_GPIO_PORT); -} - -void __init mx21_init_irq(void) -{ - mxc_init_irq(MX21_IO_ADDRESS(MX21_AVIC_BASE_ADDR)); -} - -static const struct resource imx21_audmux_res[] __initconst = { - DEFINE_RES_MEM(MX21_AUDMUX_BASE_ADDR, SZ_4K), -}; - -void __init imx21_soc_init(void) -{ - mxc_arch_reset_init(MX21_IO_ADDRESS(MX21_WDOG_BASE_ADDR)); - mxc_device_init(); - - mxc_register_gpio("imx21-gpio", 0, MX21_GPIO1_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0); - mxc_register_gpio("imx21-gpio", 1, MX21_GPIO2_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0); - mxc_register_gpio("imx21-gpio", 2, MX21_GPIO3_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0); - mxc_register_gpio("imx21-gpio", 3, MX21_GPIO4_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0); - mxc_register_gpio("imx21-gpio", 4, MX21_GPIO5_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0); - mxc_register_gpio("imx21-gpio", 5, MX21_GPIO6_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0); - - pinctrl_provide_dummies(); - imx_add_imx_dma("imx21-dma", MX21_DMA_BASE_ADDR, MX21_INT_DMACH0); - platform_device_register_simple("imx21-audmux", 0, imx21_audmux_res, - ARRAY_SIZE(imx21_audmux_res)); -} diff --git a/arch/arm/mach-imx/mm-imx27.c b/arch/arm/mach-imx/mm-imx27.c deleted file mode 100644 index 2717614f101d..000000000000 --- a/arch/arm/mach-imx/mm-imx27.c +++ /dev/null @@ -1,88 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * arch/arm/mach-imx/mm-imx27.c - * - * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) - */ - -#include <linux/mm.h> -#include <linux/init.h> -#include <linux/pinctrl/machine.h> -#include <asm/mach/map.h> - -#include "common.h" -#include "devices/devices-common.h" -#include "hardware.h" -#include "iomux-v1.h" - -/* MX27 memory map definition */ -static struct map_desc imx27_io_desc[] __initdata = { - /* - * this fixed mapping covers: - * - AIPI1 - * - AIPI2 - * - AITC - * - ROM Patch - * - and some reserved space - */ - imx_map_entry(MX27, AIPI, MT_DEVICE), - /* - * this fixed mapping covers: - * - CSI - * - ATA - */ - imx_map_entry(MX27, SAHB1, MT_DEVICE), - /* - * this fixed mapping covers: - * - EMI - */ - imx_map_entry(MX27, X_MEMC, MT_DEVICE), -}; - -/* - * Initialize the memory map. It is called during the - * system startup to create static physical to virtual - * memory map for the IO modules. - */ -void __init mx27_map_io(void) -{ - iotable_init(imx27_io_desc, ARRAY_SIZE(imx27_io_desc)); -} - -void __init imx27_init_early(void) -{ - mxc_set_cpu_type(MXC_CPU_MX27); - imx_iomuxv1_init(MX27_IO_ADDRESS(MX27_GPIO_BASE_ADDR), - MX27_NUM_GPIO_PORT); -} - -void __init mx27_init_irq(void) -{ - mxc_init_irq(MX27_IO_ADDRESS(MX27_AVIC_BASE_ADDR)); -} - -static const struct resource imx27_audmux_res[] __initconst = { - DEFINE_RES_MEM(MX27_AUDMUX_BASE_ADDR, SZ_4K), -}; - -void __init imx27_soc_init(void) -{ - mxc_arch_reset_init(MX27_IO_ADDRESS(MX27_WDOG_BASE_ADDR)); - mxc_device_init(); - - /* i.mx27 has the i.mx21 type gpio */ - mxc_register_gpio("imx21-gpio", 0, MX27_GPIO1_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0); - mxc_register_gpio("imx21-gpio", 1, MX27_GPIO2_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0); - mxc_register_gpio("imx21-gpio", 2, MX27_GPIO3_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0); - mxc_register_gpio("imx21-gpio", 3, MX27_GPIO4_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0); - mxc_register_gpio("imx21-gpio", 4, MX27_GPIO5_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0); - mxc_register_gpio("imx21-gpio", 5, MX27_GPIO6_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0); - - pinctrl_provide_dummies(); - imx_add_imx_dma("imx27-dma", MX27_DMA_BASE_ADDR, MX27_INT_DMACH0); - /* imx27 has the imx21 type audmux */ - platform_device_register_simple("imx21-audmux", 0, imx27_audmux_res, - ARRAY_SIZE(imx27_audmux_res)); - - imx27_pm_init(); -} diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c index ea2d58a63903..5056438e5b42 100644 --- a/arch/arm/mach-imx/mm-imx3.c +++ b/arch/arm/mach-imx/mm-imx3.c @@ -11,6 +11,7 @@ #include <linux/init.h> #include <linux/err.h> #include <linux/io.h> +#include <linux/of_address.h> #include <linux/pinctrl/machine.h> #include <asm/system_misc.h> @@ -19,9 +20,7 @@ #include "common.h" #include "crmregs-imx3.h" -#include "devices/devices-common.h" #include "hardware.h" -#include "iomux-v3.h" void __iomem *mx3_ccm_base; @@ -71,40 +70,6 @@ static void __iomem *imx3_ioremap_caller(phys_addr_t phys_addr, size_t size, return __arm_ioremap_caller(phys_addr, size, mtype, caller); } -static void __init imx3_init_l2x0(void) -{ -#ifdef CONFIG_CACHE_L2X0 - void __iomem *l2x0_base; - void __iomem *clkctl_base; - -/* - * First of all, we must repair broken chip settings. There are some - * i.MX35 CPUs in the wild, comming with bogus L2 cache settings. These - * misconfigured CPUs will run amok immediately when the L2 cache gets enabled. - * Workaraound is to setup the correct register setting prior enabling the - * L2 cache. This should not hurt already working CPUs, as they are using the - * same value. - */ -#define L2_MEM_VAL 0x10 - - clkctl_base = ioremap(MX35_CLKCTL_BASE_ADDR, 4096); - if (clkctl_base != NULL) { - writel(0x00000515, clkctl_base + L2_MEM_VAL); - iounmap(clkctl_base); - } else { - pr_err("L2 cache: Cannot fix timing. Trying to continue without\n"); - } - - l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096); - if (!l2x0_base) { - printk(KERN_ERR "remapping L2 cache area failed\n"); - return; - } - - l2x0_init(l2x0_base, 0x00030024, 0x00000000); -#endif -} - #ifdef CONFIG_SOC_IMX31 static struct map_desc mx31_io_desc[] __initdata = { imx_map_entry(MX31, X_MEMC, MT_DEVICE), @@ -135,70 +100,26 @@ static void imx31_idle(void) void __init imx31_init_early(void) { + struct device_node *np; + mxc_set_cpu_type(MXC_CPU_MX31); arch_ioremap_caller = imx3_ioremap_caller; arm_pm_idle = imx31_idle; - mx3_ccm_base = MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR); + np = of_find_compatible_node(NULL, NULL, "fsl,imx31-ccm"); + mx3_ccm_base = of_iomap(np, 0); + BUG_ON(!mx3_ccm_base); } void __init mx31_init_irq(void) { - mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR)); -} - -static struct sdma_script_start_addrs imx31_to1_sdma_script __initdata = { - .per_2_per_addr = 1677, -}; - -static struct sdma_script_start_addrs imx31_to2_sdma_script __initdata = { - .ap_2_ap_addr = 423, - .ap_2_bp_addr = 829, - .bp_2_ap_addr = 1029, -}; - -static struct sdma_platform_data imx31_sdma_pdata __initdata = { - .fw_name = "sdma-imx31-to2.bin", - .script_addrs = &imx31_to2_sdma_script, -}; - -static const struct resource imx31_audmux_res[] __initconst = { - DEFINE_RES_MEM(MX31_AUDMUX_BASE_ADDR, SZ_16K), -}; - -static const struct resource imx31_rnga_res[] __initconst = { - DEFINE_RES_MEM(MX31_RNGA_BASE_ADDR, SZ_16K), -}; - -void __init imx31_soc_init(void) -{ - int to_version = mx31_revision() >> 4; + void __iomem *avic_base; + struct device_node *np; - imx3_init_l2x0(); + np = of_find_compatible_node(NULL, NULL, "fsl,imx31-avic"); + avic_base = of_iomap(np, 0); + BUG_ON(!avic_base); - mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR)); - mxc_device_init(); - - mxc_register_gpio("imx31-gpio", 0, MX31_GPIO1_BASE_ADDR, SZ_16K, MX31_INT_GPIO1, 0); - mxc_register_gpio("imx31-gpio", 1, MX31_GPIO2_BASE_ADDR, SZ_16K, MX31_INT_GPIO2, 0); - mxc_register_gpio("imx31-gpio", 2, MX31_GPIO3_BASE_ADDR, SZ_16K, MX31_INT_GPIO3, 0); - - pinctrl_provide_dummies(); - - if (to_version == 1) { - strncpy(imx31_sdma_pdata.fw_name, "sdma-imx31-to1.bin", - strlen(imx31_sdma_pdata.fw_name)); - imx31_sdma_pdata.script_addrs = &imx31_to1_sdma_script; - } - - imx_add_imx_sdma("imx31-sdma", MX31_SDMA_BASE_ADDR, MX31_INT_SDMA, &imx31_sdma_pdata); - - imx_set_aips(MX31_IO_ADDRESS(MX31_AIPS1_BASE_ADDR)); - imx_set_aips(MX31_IO_ADDRESS(MX31_AIPS2_BASE_ADDR)); - - platform_device_register_simple("imx31-audmux", 0, imx31_audmux_res, - ARRAY_SIZE(imx31_audmux_res)); - platform_device_register_simple("mxc_rnga", -1, imx31_rnga_res, - ARRAY_SIZE(imx31_rnga_res)); + mxc_init_irq(avic_base); } #endif /* ifdef CONFIG_SOC_IMX31 */ @@ -228,85 +149,25 @@ static void imx35_idle(void) void __init imx35_init_early(void) { + struct device_node *np; + mxc_set_cpu_type(MXC_CPU_MX35); - mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR)); arm_pm_idle = imx35_idle; arch_ioremap_caller = imx3_ioremap_caller; - mx3_ccm_base = MX35_IO_ADDRESS(MX35_CCM_BASE_ADDR); + np = of_find_compatible_node(NULL, NULL, "fsl,imx35-ccm"); + mx3_ccm_base = of_iomap(np, 0); + BUG_ON(!mx3_ccm_base); } void __init mx35_init_irq(void) { - mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR)); -} - -static struct sdma_script_start_addrs imx35_to1_sdma_script __initdata = { - .ap_2_ap_addr = 642, - .uart_2_mcu_addr = 817, - .mcu_2_app_addr = 747, - .uartsh_2_mcu_addr = 1183, - .per_2_shp_addr = 1033, - .mcu_2_shp_addr = 961, - .ata_2_mcu_addr = 1333, - .mcu_2_ata_addr = 1252, - .app_2_mcu_addr = 683, - .shp_2_per_addr = 1111, - .shp_2_mcu_addr = 892, -}; - -static struct sdma_script_start_addrs imx35_to2_sdma_script __initdata = { - .ap_2_ap_addr = 729, - .uart_2_mcu_addr = 904, - .per_2_app_addr = 1597, - .mcu_2_app_addr = 834, - .uartsh_2_mcu_addr = 1270, - .per_2_shp_addr = 1120, - .mcu_2_shp_addr = 1048, - .ata_2_mcu_addr = 1429, - .mcu_2_ata_addr = 1339, - .app_2_per_addr = 1531, - .app_2_mcu_addr = 770, - .shp_2_per_addr = 1198, - .shp_2_mcu_addr = 979, -}; - -static struct sdma_platform_data imx35_sdma_pdata __initdata = { - .fw_name = "sdma-imx35-to2.bin", - .script_addrs = &imx35_to2_sdma_script, -}; - -static const struct resource imx35_audmux_res[] __initconst = { - DEFINE_RES_MEM(MX35_AUDMUX_BASE_ADDR, SZ_16K), -}; - -void __init imx35_soc_init(void) -{ - int to_version = mx35_revision() >> 4; - - imx3_init_l2x0(); - - mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR)); - mxc_device_init(); - - mxc_register_gpio("imx35-gpio", 0, MX35_GPIO1_BASE_ADDR, SZ_16K, MX35_INT_GPIO1, 0); - mxc_register_gpio("imx35-gpio", 1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0); - mxc_register_gpio("imx35-gpio", 2, MX35_GPIO3_BASE_ADDR, SZ_16K, MX35_INT_GPIO3, 0); - - pinctrl_provide_dummies(); - if (to_version == 1) { - strncpy(imx35_sdma_pdata.fw_name, "sdma-imx35-to1.bin", - strlen(imx35_sdma_pdata.fw_name)); - imx35_sdma_pdata.script_addrs = &imx35_to1_sdma_script; - } - - imx_add_imx_sdma("imx35-sdma", MX35_SDMA_BASE_ADDR, MX35_INT_SDMA, &imx35_sdma_pdata); + void __iomem *avic_base; + struct device_node *np; - /* Setup AIPS registers */ - imx_set_aips(MX35_IO_ADDRESS(MX35_AIPS1_BASE_ADDR)); - imx_set_aips(MX35_IO_ADDRESS(MX35_AIPS2_BASE_ADDR)); + np = of_find_compatible_node(NULL, NULL, "fsl,imx35-avic"); + avic_base = of_iomap(np, 0); + BUG_ON(!avic_base); - /* i.mx35 has the i.mx31 type audmux */ - platform_device_register_simple("imx31-audmux", 0, imx35_audmux_res, - ARRAY_SIZE(imx35_audmux_res)); + mxc_init_irq(avic_base); } #endif /* ifdef CONFIG_SOC_IMX35 */ diff --git a/arch/arm/mach-imx/mx21.h b/arch/arm/mach-imx/mx21.h deleted file mode 100644 index 38be12a44bdd..000000000000 --- a/arch/arm/mach-imx/mx21.h +++ /dev/null @@ -1,176 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Juergen Beisert, kernel@pengutronix.de - * Copyright 2009 Holger Schurig, hs4233@mail.mn-solutions.de - * - * This contains i.MX21-specific hardware definitions. For those - * hardware pieces that are common between i.MX21 and i.MX27, have a - * look at mx2x.h. - */ - -#ifndef __MACH_MX21_H__ -#define __MACH_MX21_H__ - -#define MX21_AIPI_BASE_ADDR 0x10000000 -#define MX21_AIPI_SIZE SZ_1M -#define MX21_DMA_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x01000) -#define MX21_WDOG_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x02000) -#define MX21_GPT1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x03000) -#define MX21_GPT2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x04000) -#define MX21_GPT3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x05000) -#define MX21_PWM_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x06000) -#define MX21_RTC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x07000) -#define MX21_KPP_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x08000) -#define MX21_OWIRE_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x09000) -#define MX21_UART1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0a000) -#define MX21_UART2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0b000) -#define MX21_UART3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0c000) -#define MX21_UART4_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0d000) -#define MX21_CSPI1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0e000) -#define MX21_CSPI2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0f000) -#define MX21_SSI1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x10000) -#define MX21_SSI2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x11000) -#define MX21_I2C_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x12000) -#define MX21_SDHC1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x13000) -#define MX21_SDHC2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x14000) -#define MX21_GPIO_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x15000) -#define MX21_GPIO1_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x000) -#define MX21_GPIO2_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x100) -#define MX21_GPIO3_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x200) -#define MX21_GPIO4_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x300) -#define MX21_GPIO5_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x400) -#define MX21_GPIO6_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x500) -#define MX21_AUDMUX_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x16000) -#define MX21_CSPI3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x17000) -#define MX21_LCDC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x21000) -#define MX21_SLCDC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x22000) -#define MX21_USBOTG_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x24000) -#define MX21_EMMA_PP_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x26000) -#define MX21_EMMA_PRP_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x26400) -#define MX21_CCM_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x27000) -#define MX21_SYSCTRL_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x27800) -#define MX21_JAM_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x3e000) -#define MX21_MAX_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x3f000) - -#define MX21_AVIC_BASE_ADDR 0x10040000 - -#define MX21_SAHB1_BASE_ADDR 0x80000000 -#define MX21_SAHB1_SIZE SZ_1M -#define MX21_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000) - -/* Memory regions and CS */ -#define MX21_SDRAM_BASE_ADDR 0xc0000000 -#define MX21_CSD1_BASE_ADDR 0xc4000000 - -#define MX21_CS0_BASE_ADDR 0xc8000000 -#define MX21_CS1_BASE_ADDR 0xcc000000 -#define MX21_CS2_BASE_ADDR 0xd0000000 -#define MX21_CS3_BASE_ADDR 0xd1000000 -#define MX21_CS4_BASE_ADDR 0xd2000000 -#define MX21_PCMCIA_MEM_BASE_ADDR 0xd4000000 -#define MX21_CS5_BASE_ADDR 0xdd000000 - -/* NAND, SDRAM, WEIM etc controllers */ -#define MX21_X_MEMC_BASE_ADDR 0xdf000000 -#define MX21_X_MEMC_SIZE SZ_256K - -#define MX21_SDRAMC_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x0000) -#define MX21_EIM_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x1000) -#define MX21_PCMCIA_CTL_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x2000) -#define MX21_NFC_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x3000) - -#define MX21_IRAM_BASE_ADDR 0xffffe800 /* internal ram */ - -#define MX21_IO_P2V(x) IMX_IO_P2V(x) -#define MX21_IO_ADDRESS(x) IOMEM(MX21_IO_P2V(x)) - -/* fixed interrupt numbers */ -#include <asm/irq.h> -#define MX21_INT_CSPI3 (NR_IRQS_LEGACY + 6) -#define MX21_INT_GPIO (NR_IRQS_LEGACY + 8) -#define MX21_INT_FIRI (NR_IRQS_LEGACY + 9) -#define MX21_INT_SDHC2 (NR_IRQS_LEGACY + 10) -#define MX21_INT_SDHC1 (NR_IRQS_LEGACY + 11) -#define MX21_INT_I2C (NR_IRQS_LEGACY + 12) -#define MX21_INT_SSI2 (NR_IRQS_LEGACY + 13) -#define MX21_INT_SSI1 (NR_IRQS_LEGACY + 14) -#define MX21_INT_CSPI2 (NR_IRQS_LEGACY + 15) -#define MX21_INT_CSPI1 (NR_IRQS_LEGACY + 16) -#define MX21_INT_UART4 (NR_IRQS_LEGACY + 17) -#define MX21_INT_UART3 (NR_IRQS_LEGACY + 18) -#define MX21_INT_UART2 (NR_IRQS_LEGACY + 19) -#define MX21_INT_UART1 (NR_IRQS_LEGACY + 20) -#define MX21_INT_KPP (NR_IRQS_LEGACY + 21) -#define MX21_INT_RTC (NR_IRQS_LEGACY + 22) -#define MX21_INT_PWM (NR_IRQS_LEGACY + 23) -#define MX21_INT_GPT3 (NR_IRQS_LEGACY + 24) -#define MX21_INT_GPT2 (NR_IRQS_LEGACY + 25) -#define MX21_INT_GPT1 (NR_IRQS_LEGACY + 26) -#define MX21_INT_WDOG (NR_IRQS_LEGACY + 27) -#define MX21_INT_PCMCIA (NR_IRQS_LEGACY + 28) -#define MX21_INT_NFC (NR_IRQS_LEGACY + 29) -#define MX21_INT_BMI (NR_IRQS_LEGACY + 30) -#define MX21_INT_CSI (NR_IRQS_LEGACY + 31) -#define MX21_INT_DMACH0 (NR_IRQS_LEGACY + 32) -#define MX21_INT_DMACH1 (NR_IRQS_LEGACY + 33) -#define MX21_INT_DMACH2 (NR_IRQS_LEGACY + 34) -#define MX21_INT_DMACH3 (NR_IRQS_LEGACY + 35) -#define MX21_INT_DMACH4 (NR_IRQS_LEGACY + 36) -#define MX21_INT_DMACH5 (NR_IRQS_LEGACY + 37) -#define MX21_INT_DMACH6 (NR_IRQS_LEGACY + 38) -#define MX21_INT_DMACH7 (NR_IRQS_LEGACY + 39) -#define MX21_INT_DMACH8 (NR_IRQS_LEGACY + 40) -#define MX21_INT_DMACH9 (NR_IRQS_LEGACY + 41) -#define MX21_INT_DMACH10 (NR_IRQS_LEGACY + 42) -#define MX21_INT_DMACH11 (NR_IRQS_LEGACY + 43) -#define MX21_INT_DMACH12 (NR_IRQS_LEGACY + 44) -#define MX21_INT_DMACH13 (NR_IRQS_LEGACY + 45) -#define MX21_INT_DMACH14 (NR_IRQS_LEGACY + 46) -#define MX21_INT_DMACH15 (NR_IRQS_LEGACY + 47) -#define MX21_INT_EMMAENC (NR_IRQS_LEGACY + 49) -#define MX21_INT_EMMADEC (NR_IRQS_LEGACY + 50) -#define MX21_INT_EMMAPRP (NR_IRQS_LEGACY + 51) -#define MX21_INT_EMMAPP (NR_IRQS_LEGACY + 52) -#define MX21_INT_USBWKUP (NR_IRQS_LEGACY + 53) -#define MX21_INT_USBDMA (NR_IRQS_LEGACY + 54) -#define MX21_INT_USBHOST (NR_IRQS_LEGACY + 55) -#define MX21_INT_USBFUNC (NR_IRQS_LEGACY + 56) -#define MX21_INT_USBMNP (NR_IRQS_LEGACY + 57) -#define MX21_INT_USBCTRL (NR_IRQS_LEGACY + 58) -#define MX21_INT_SLCDC (NR_IRQS_LEGACY + 60) -#define MX21_INT_LCDC (NR_IRQS_LEGACY + 61) - -/* fixed DMA request numbers */ -#define MX21_DMA_REQ_CSPI3_RX 1 -#define MX21_DMA_REQ_CSPI3_TX 2 -#define MX21_DMA_REQ_EXT 3 -#define MX21_DMA_REQ_FIRI_RX 4 -#define MX21_DMA_REQ_SDHC2 6 -#define MX21_DMA_REQ_SDHC1 7 -#define MX21_DMA_REQ_SSI2_RX0 8 -#define MX21_DMA_REQ_SSI2_TX0 9 -#define MX21_DMA_REQ_SSI2_RX1 10 -#define MX21_DMA_REQ_SSI2_TX1 11 -#define MX21_DMA_REQ_SSI1_RX0 12 -#define MX21_DMA_REQ_SSI1_TX0 13 -#define MX21_DMA_REQ_SSI1_RX1 14 -#define MX21_DMA_REQ_SSI1_TX1 15 -#define MX21_DMA_REQ_CSPI2_RX 16 -#define MX21_DMA_REQ_CSPI2_TX 17 -#define MX21_DMA_REQ_CSPI1_RX 18 -#define MX21_DMA_REQ_CSPI1_TX 19 -#define MX21_DMA_REQ_UART4_RX 20 -#define MX21_DMA_REQ_UART4_TX 21 -#define MX21_DMA_REQ_UART3_RX 22 -#define MX21_DMA_REQ_UART3_TX 23 -#define MX21_DMA_REQ_UART2_RX 24 -#define MX21_DMA_REQ_UART2_TX 25 -#define MX21_DMA_REQ_UART1_RX 26 -#define MX21_DMA_REQ_UART1_TX 27 -#define MX21_DMA_REQ_BMI_TX 28 -#define MX21_DMA_REQ_BMI_RX 29 -#define MX21_DMA_REQ_CSI_STAT 30 -#define MX21_DMA_REQ_CSI_RX 31 - -#endif /* ifndef __MACH_MX21_H__ */ diff --git a/arch/arm/mach-imx/mx27.h b/arch/arm/mach-imx/mx27.h index c6f7aae02b67..241c04d706fe 100644 --- a/arch/arm/mach-imx/mx27.h +++ b/arch/arm/mach-imx/mx27.h @@ -13,209 +13,13 @@ #define MX27_AIPI_BASE_ADDR 0x10000000 #define MX27_AIPI_SIZE SZ_1M -#define MX27_DMA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x01000) -#define MX27_WDOG_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x02000) -#define MX27_GPT1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x03000) -#define MX27_GPT2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x04000) -#define MX27_GPT3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x05000) -#define MX27_PWM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x06000) -#define MX27_RTC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x07000) -#define MX27_KPP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x08000) -#define MX27_OWIRE_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x09000) -#define MX27_UART1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0a000) -#define MX27_UART2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0b000) -#define MX27_UART3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0c000) -#define MX27_UART4_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0d000) -#define MX27_CSPI1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0e000) -#define MX27_CSPI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0f000) -#define MX27_SSI1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x10000) -#define MX27_SSI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x11000) -#define MX27_I2C1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x12000) -#define MX27_SDHC1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x13000) -#define MX27_SDHC2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x14000) -#define MX27_GPIO_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x15000) -#define MX27_GPIO1_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x000) -#define MX27_GPIO2_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x100) -#define MX27_GPIO3_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x200) -#define MX27_GPIO4_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x300) -#define MX27_GPIO5_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x400) -#define MX27_GPIO6_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x500) -#define MX27_AUDMUX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x16000) -#define MX27_CSPI3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x17000) -#define MX27_MSHC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x18000) -#define MX27_GPT4_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x19000) -#define MX27_GPT5_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1a000) -#define MX27_UART5_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1b000) -#define MX27_UART6_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1c000) -#define MX27_I2C2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1d000) -#define MX27_SDHC3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1e000) -#define MX27_GPT6_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1f000) -#define MX27_LCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x21000) -#define MX27_SLCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x22000) -#define MX27_VPU_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x23000) -#define MX27_USB_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x24000) -#define MX27_USB_OTG_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0000) -#define MX27_USB_HS1_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0200) -#define MX27_USB_HS2_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0400) -#define MX27_SAHARA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x25000) -#define MX27_EMMAPP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26000) -#define MX27_EMMAPRP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26400) -#define MX27_CCM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27000) -#define MX27_SYSCTRL_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27800) -#define MX27_IIM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x28000) -#define MX27_RTIC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2a000) -#define MX27_FEC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2b000) -#define MX27_SCC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2c000) -#define MX27_ETB_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3b000) -#define MX27_ETB_RAM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3c000) -#define MX27_JAM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3e000) -#define MX27_MAX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3f000) - -#define MX27_AVIC_BASE_ADDR 0x10040000 - -/* ROM patch */ -#define MX27_ROMP_BASE_ADDR 0x10041000 #define MX27_SAHB1_BASE_ADDR 0x80000000 #define MX27_SAHB1_SIZE SZ_1M -#define MX27_CSI_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x0000) -#define MX27_ATA_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x1000) - -/* Memory regions and CS */ -#define MX27_SDRAM_BASE_ADDR 0xa0000000 -#define MX27_CSD1_BASE_ADDR 0xb0000000 -#define MX27_CS0_BASE_ADDR 0xc0000000 -#define MX27_CS1_BASE_ADDR 0xc8000000 -#define MX27_CS2_BASE_ADDR 0xd0000000 -#define MX27_CS3_BASE_ADDR 0xd2000000 -#define MX27_CS4_BASE_ADDR 0xd4000000 -#define MX27_CS5_BASE_ADDR 0xd6000000 - -/* NAND, SDRAM, WEIM, M3IF, EMI controllers */ #define MX27_X_MEMC_BASE_ADDR 0xd8000000 #define MX27_X_MEMC_SIZE SZ_1M -#define MX27_NFC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR) -#define MX27_SDRAMC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x1000) -#define MX27_WEIM_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x2000) -#define MX27_M3IF_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x3000) -#define MX27_PCMCIA_CTL_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x4000) - -#define MX27_WEIM_CSCRx_BASE_ADDR(cs) (MX27_WEIM_BASE_ADDR + (cs) * 0x10) -#define MX27_WEIM_CSCRxU(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs)) -#define MX27_WEIM_CSCRxL(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x4) -#define MX27_WEIM_CSCRxA(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x8) - -#define MX27_PCMCIA_MEM_BASE_ADDR 0xdc000000 - -/* IRAM */ -#define MX27_IRAM_BASE_ADDR 0xffff4c00 /* internal ram */ #define MX27_IO_P2V(x) IMX_IO_P2V(x) -#define MX27_IO_ADDRESS(x) IOMEM(MX27_IO_P2V(x)) - -/* fixed interrupt numbers */ -#include <asm/irq.h> -#define MX27_INT_I2C2 (NR_IRQS_LEGACY + 1) -#define MX27_INT_GPT6 (NR_IRQS_LEGACY + 2) -#define MX27_INT_GPT5 (NR_IRQS_LEGACY + 3) -#define MX27_INT_GPT4 (NR_IRQS_LEGACY + 4) -#define MX27_INT_RTIC (NR_IRQS_LEGACY + 5) -#define MX27_INT_CSPI3 (NR_IRQS_LEGACY + 6) -#define MX27_INT_MSHC (NR_IRQS_LEGACY + 7) -#define MX27_INT_GPIO (NR_IRQS_LEGACY + 8) -#define MX27_INT_SDHC3 (NR_IRQS_LEGACY + 9) -#define MX27_INT_SDHC2 (NR_IRQS_LEGACY + 10) -#define MX27_INT_SDHC1 (NR_IRQS_LEGACY + 11) -#define MX27_INT_I2C1 (NR_IRQS_LEGACY + 12) -#define MX27_INT_SSI2 (NR_IRQS_LEGACY + 13) -#define MX27_INT_SSI1 (NR_IRQS_LEGACY + 14) -#define MX27_INT_CSPI2 (NR_IRQS_LEGACY + 15) -#define MX27_INT_CSPI1 (NR_IRQS_LEGACY + 16) -#define MX27_INT_UART4 (NR_IRQS_LEGACY + 17) -#define MX27_INT_UART3 (NR_IRQS_LEGACY + 18) -#define MX27_INT_UART2 (NR_IRQS_LEGACY + 19) -#define MX27_INT_UART1 (NR_IRQS_LEGACY + 20) -#define MX27_INT_KPP (NR_IRQS_LEGACY + 21) -#define MX27_INT_RTC (NR_IRQS_LEGACY + 22) -#define MX27_INT_PWM (NR_IRQS_LEGACY + 23) -#define MX27_INT_GPT3 (NR_IRQS_LEGACY + 24) -#define MX27_INT_GPT2 (NR_IRQS_LEGACY + 25) -#define MX27_INT_GPT1 (NR_IRQS_LEGACY + 26) -#define MX27_INT_WDOG (NR_IRQS_LEGACY + 27) -#define MX27_INT_PCMCIA (NR_IRQS_LEGACY + 28) -#define MX27_INT_NFC (NR_IRQS_LEGACY + 29) -#define MX27_INT_ATA (NR_IRQS_LEGACY + 30) -#define MX27_INT_CSI (NR_IRQS_LEGACY + 31) -#define MX27_INT_DMACH0 (NR_IRQS_LEGACY + 32) -#define MX27_INT_DMACH1 (NR_IRQS_LEGACY + 33) -#define MX27_INT_DMACH2 (NR_IRQS_LEGACY + 34) -#define MX27_INT_DMACH3 (NR_IRQS_LEGACY + 35) -#define MX27_INT_DMACH4 (NR_IRQS_LEGACY + 36) -#define MX27_INT_DMACH5 (NR_IRQS_LEGACY + 37) -#define MX27_INT_DMACH6 (NR_IRQS_LEGACY + 38) -#define MX27_INT_DMACH7 (NR_IRQS_LEGACY + 39) -#define MX27_INT_DMACH8 (NR_IRQS_LEGACY + 40) -#define MX27_INT_DMACH9 (NR_IRQS_LEGACY + 41) -#define MX27_INT_DMACH10 (NR_IRQS_LEGACY + 42) -#define MX27_INT_DMACH11 (NR_IRQS_LEGACY + 43) -#define MX27_INT_DMACH12 (NR_IRQS_LEGACY + 44) -#define MX27_INT_DMACH13 (NR_IRQS_LEGACY + 45) -#define MX27_INT_DMACH14 (NR_IRQS_LEGACY + 46) -#define MX27_INT_DMACH15 (NR_IRQS_LEGACY + 47) -#define MX27_INT_UART6 (NR_IRQS_LEGACY + 48) -#define MX27_INT_UART5 (NR_IRQS_LEGACY + 49) -#define MX27_INT_FEC (NR_IRQS_LEGACY + 50) -#define MX27_INT_EMMAPRP (NR_IRQS_LEGACY + 51) -#define MX27_INT_EMMAPP (NR_IRQS_LEGACY + 52) -#define MX27_INT_VPU (NR_IRQS_LEGACY + 53) -#define MX27_INT_USB_HS1 (NR_IRQS_LEGACY + 54) -#define MX27_INT_USB_HS2 (NR_IRQS_LEGACY + 55) -#define MX27_INT_USB_OTG (NR_IRQS_LEGACY + 56) -#define MX27_INT_SCC_SMN (NR_IRQS_LEGACY + 57) -#define MX27_INT_SCC_SCM (NR_IRQS_LEGACY + 58) -#define MX27_INT_SAHARA (NR_IRQS_LEGACY + 59) -#define MX27_INT_SLCDC (NR_IRQS_LEGACY + 60) -#define MX27_INT_LCDC (NR_IRQS_LEGACY + 61) -#define MX27_INT_IIM (NR_IRQS_LEGACY + 62) -#define MX27_INT_CCM (NR_IRQS_LEGACY + 63) - -/* fixed DMA request numbers */ -#define MX27_DMA_REQ_CSPI3_RX 1 -#define MX27_DMA_REQ_CSPI3_TX 2 -#define MX27_DMA_REQ_EXT 3 -#define MX27_DMA_REQ_MSHC 4 -#define MX27_DMA_REQ_SDHC2 6 -#define MX27_DMA_REQ_SDHC1 7 -#define MX27_DMA_REQ_SSI2_RX0 8 -#define MX27_DMA_REQ_SSI2_TX0 9 -#define MX27_DMA_REQ_SSI2_RX1 10 -#define MX27_DMA_REQ_SSI2_TX1 11 -#define MX27_DMA_REQ_SSI1_RX0 12 -#define MX27_DMA_REQ_SSI1_TX0 13 -#define MX27_DMA_REQ_SSI1_RX1 14 -#define MX27_DMA_REQ_SSI1_TX1 15 -#define MX27_DMA_REQ_CSPI2_RX 16 -#define MX27_DMA_REQ_CSPI2_TX 17 -#define MX27_DMA_REQ_CSPI1_RX 18 -#define MX27_DMA_REQ_CSPI1_TX 19 -#define MX27_DMA_REQ_UART4_RX 20 -#define MX27_DMA_REQ_UART4_TX 21 -#define MX27_DMA_REQ_UART3_RX 22 -#define MX27_DMA_REQ_UART3_TX 23 -#define MX27_DMA_REQ_UART2_RX 24 -#define MX27_DMA_REQ_UART2_TX 25 -#define MX27_DMA_REQ_UART1_RX 26 -#define MX27_DMA_REQ_UART1_TX 27 -#define MX27_DMA_REQ_ATA_TX 28 -#define MX27_DMA_REQ_ATA_RCV 29 -#define MX27_DMA_REQ_CSI_STAT 30 -#define MX27_DMA_REQ_CSI_RX 31 -#define MX27_DMA_REQ_UART5_TX 32 -#define MX27_DMA_REQ_UART5_RX 33 -#define MX27_DMA_REQ_UART6_TX 34 -#define MX27_DMA_REQ_UART6_RX 35 -#define MX27_DMA_REQ_SDHC3 36 -#define MX27_DMA_REQ_NFC 37 #endif /* ifndef __MACH_MX27_H__ */ diff --git a/arch/arm/mach-imx/mx31.h b/arch/arm/mach-imx/mx31.h index d9574671ca5c..08a72e25c289 100644 --- a/arch/arm/mach-imx/mx31.h +++ b/arch/arm/mach-imx/mx31.h @@ -2,196 +2,17 @@ #ifndef __MACH_MX31_H__ #define __MACH_MX31_H__ -/* - * IRAM - */ -#define MX31_IRAM_BASE_ADDR 0x1ffc0000 /* internal ram */ -#define MX31_IRAM_SIZE SZ_16K - -#define MX31_L2CC_BASE_ADDR 0x30000000 -#define MX31_L2CC_SIZE SZ_1M - #define MX31_AIPS1_BASE_ADDR 0x43f00000 #define MX31_AIPS1_SIZE SZ_1M -#define MX31_MAX_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x04000) -#define MX31_EVTMON_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x08000) -#define MX31_CLKCTL_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x0c000) -#define MX31_ETB_SLOT4_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x10000) -#define MX31_ETB_SLOT5_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x14000) -#define MX31_ECT_CTIO_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x18000) -#define MX31_I2C1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x80000) -#define MX31_I2C3_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x84000) -#define MX31_USB_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x88000) -#define MX31_USB_OTG_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0000) -#define MX31_USB_HS1_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0200) -#define MX31_USB_HS2_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0400) -#define MX31_ATA_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x8c000) -#define MX31_UART1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x90000) -#define MX31_UART2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x94000) -#define MX31_I2C2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x98000) -#define MX31_OWIRE_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x9c000) -#define MX31_SSI1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa0000) -#define MX31_CSPI1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa4000) -#define MX31_KPP_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa8000) -#define MX31_IOMUXC_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xac000) -#define MX31_UART4_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb0000) -#define MX31_UART5_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb4000) -#define MX31_ECT_IP1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb8000) -#define MX31_ECT_IP2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xbc000) - #define MX31_SPBA0_BASE_ADDR 0x50000000 #define MX31_SPBA0_SIZE SZ_1M -#define MX31_SDHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x04000) -#define MX31_SDHC2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x08000) -#define MX31_UART3_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x0c000) -#define MX31_CSPI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x10000) -#define MX31_SSI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x14000) -#define MX31_SIM1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x18000) -#define MX31_IIM_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x1c000) -#define MX31_ATA_DMA_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x20000) -#define MX31_MSHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x24000) -#define MX31_SPBA_CTRL_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x3c000) - #define MX31_AIPS2_BASE_ADDR 0x53f00000 #define MX31_AIPS2_SIZE SZ_1M -#define MX31_CCM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x80000) -#define MX31_CSPI3_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x84000) -#define MX31_FIRI_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x8c000) -#define MX31_GPT1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x90000) -#define MX31_EPIT1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x94000) -#define MX31_EPIT2_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x98000) -#define MX31_GPIO3_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xa4000) -#define MX31_SCC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xac000) -#define MX31_SCM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xae000) -#define MX31_SMN_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xaf000) -#define MX31_RNGA_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xb0000) -#define MX31_IPU_CTRL_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc0000) -#define MX31_AUDMUX_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc4000) -#define MX31_MPEG4_ENC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc8000) -#define MX31_GPIO1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xcc000) -#define MX31_GPIO2_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd0000) -#define MX31_SDMA_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd4000) -#define MX31_RTC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd8000) -#define MX31_WDOG_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xdc000) -#define MX31_PWM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xe0000) -#define MX31_RTIC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xec000) - -#define MX31_ROMP_BASE_ADDR 0x60000000 -#define MX31_ROMP_BASE_ADDR_VIRT IOMEM(0xfc500000) -#define MX31_ROMP_SIZE SZ_1M - #define MX31_AVIC_BASE_ADDR 0x68000000 #define MX31_AVIC_SIZE SZ_1M - -#define MX31_IPU_MEM_BASE_ADDR 0x70000000 -#define MX31_CSD0_BASE_ADDR 0x80000000 -#define MX31_CSD1_BASE_ADDR 0x90000000 - -#define MX31_CS0_BASE_ADDR 0xa0000000 -#define MX31_CS1_BASE_ADDR 0xa8000000 -#define MX31_CS2_BASE_ADDR 0xb0000000 -#define MX31_CS3_BASE_ADDR 0xb2000000 - -#define MX31_CS4_BASE_ADDR 0xb4000000 -#define MX31_CS4_BASE_ADDR_VIRT IOMEM(0xf6000000) -#define MX31_CS4_SIZE SZ_32M - -#define MX31_CS5_BASE_ADDR 0xb6000000 -#define MX31_CS5_BASE_ADDR_VIRT IOMEM(0xf8000000) -#define MX31_CS5_SIZE SZ_32M - #define MX31_X_MEMC_BASE_ADDR 0xb8000000 #define MX31_X_MEMC_SIZE SZ_64K -#define MX31_NFC_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x0000) -#define MX31_ESDCTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x1000) -#define MX31_WEIM_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x2000) -#define MX31_M3IF_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x3000) -#define MX31_EMI_CTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x4000) -#define MX31_PCMCIA_CTL_BASE_ADDR MX31_EMI_CTL_BASE_ADDR - -#define MX31_WEIM_CSCRx_BASE_ADDR(cs) (MX31_WEIM_BASE_ADDR + (cs) * 0x10) -#define MX31_WEIM_CSCRxU(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs)) -#define MX31_WEIM_CSCRxL(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs) + 0x4) -#define MX31_WEIM_CSCRxA(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs) + 0x8) - -#define MX31_PCMCIA_MEM_BASE_ADDR 0xbc000000 #define MX31_IO_P2V(x) IMX_IO_P2V(x) -#define MX31_IO_ADDRESS(x) IOMEM(MX31_IO_P2V(x)) - -/* - * Interrupt numbers - */ -#include <asm/irq.h> -#define MX31_INT_I2C3 (NR_IRQS_LEGACY + 3) -#define MX31_INT_I2C2 (NR_IRQS_LEGACY + 4) -#define MX31_INT_MPEG4_ENCODER (NR_IRQS_LEGACY + 5) -#define MX31_INT_RTIC (NR_IRQS_LEGACY + 6) -#define MX31_INT_FIRI (NR_IRQS_LEGACY + 7) -#define MX31_INT_SDHC2 (NR_IRQS_LEGACY + 8) -#define MX31_INT_SDHC1 (NR_IRQS_LEGACY + 9) -#define MX31_INT_I2C1 (NR_IRQS_LEGACY + 10) -#define MX31_INT_SSI2 (NR_IRQS_LEGACY + 11) -#define MX31_INT_SSI1 (NR_IRQS_LEGACY + 12) -#define MX31_INT_CSPI2 (NR_IRQS_LEGACY + 13) -#define MX31_INT_CSPI1 (NR_IRQS_LEGACY + 14) -#define MX31_INT_ATA (NR_IRQS_LEGACY + 15) -#define MX31_INT_MBX (NR_IRQS_LEGACY + 16) -#define MX31_INT_CSPI3 (NR_IRQS_LEGACY + 17) -#define MX31_INT_UART3 (NR_IRQS_LEGACY + 18) -#define MX31_INT_IIM (NR_IRQS_LEGACY + 19) -#define MX31_INT_SIM2 (NR_IRQS_LEGACY + 20) -#define MX31_INT_SIM1 (NR_IRQS_LEGACY + 21) -#define MX31_INT_RNGA (NR_IRQS_LEGACY + 22) -#define MX31_INT_EVTMON (NR_IRQS_LEGACY + 23) -#define MX31_INT_KPP (NR_IRQS_LEGACY + 24) -#define MX31_INT_RTC (NR_IRQS_LEGACY + 25) -#define MX31_INT_PWM (NR_IRQS_LEGACY + 26) -#define MX31_INT_EPIT2 (NR_IRQS_LEGACY + 27) -#define MX31_INT_EPIT1 (NR_IRQS_LEGACY + 28) -#define MX31_INT_GPT (NR_IRQS_LEGACY + 29) -#define MX31_INT_POWER_FAIL (NR_IRQS_LEGACY + 30) -#define MX31_INT_CCM_DVFS (NR_IRQS_LEGACY + 31) -#define MX31_INT_UART2 (NR_IRQS_LEGACY + 32) -#define MX31_INT_NFC (NR_IRQS_LEGACY + 33) -#define MX31_INT_SDMA (NR_IRQS_LEGACY + 34) -#define MX31_INT_USB_HS1 (NR_IRQS_LEGACY + 35) -#define MX31_INT_USB_HS2 (NR_IRQS_LEGACY + 36) -#define MX31_INT_USB_OTG (NR_IRQS_LEGACY + 37) -#define MX31_INT_MSHC1 (NR_IRQS_LEGACY + 39) -#define MX31_INT_MSHC2 (NR_IRQS_LEGACY + 40) -#define MX31_INT_IPU_ERR (NR_IRQS_LEGACY + 41) -#define MX31_INT_IPU_SYN (NR_IRQS_LEGACY + 42) -#define MX31_INT_UART1 (NR_IRQS_LEGACY + 45) -#define MX31_INT_UART4 (NR_IRQS_LEGACY + 46) -#define MX31_INT_UART5 (NR_IRQS_LEGACY + 47) -#define MX31_INT_ECT (NR_IRQS_LEGACY + 48) -#define MX31_INT_SCC_SCM (NR_IRQS_LEGACY + 49) -#define MX31_INT_SCC_SMN (NR_IRQS_LEGACY + 50) -#define MX31_INT_GPIO2 (NR_IRQS_LEGACY + 51) -#define MX31_INT_GPIO1 (NR_IRQS_LEGACY + 52) -#define MX31_INT_CCM (NR_IRQS_LEGACY + 53) -#define MX31_INT_PCMCIA (NR_IRQS_LEGACY + 54) -#define MX31_INT_WDOG (NR_IRQS_LEGACY + 55) -#define MX31_INT_GPIO3 (NR_IRQS_LEGACY + 56) -#define MX31_INT_EXT_POWER (NR_IRQS_LEGACY + 58) -#define MX31_INT_EXT_TEMPER (NR_IRQS_LEGACY + 59) -#define MX31_INT_EXT_SENSOR60 (NR_IRQS_LEGACY + 60) -#define MX31_INT_EXT_SENSOR61 (NR_IRQS_LEGACY + 61) -#define MX31_INT_EXT_WDOG (NR_IRQS_LEGACY + 62) -#define MX31_INT_EXT_TV (NR_IRQS_LEGACY + 63) - -#define MX31_DMA_REQ_SDHC1 20 -#define MX31_DMA_REQ_SDHC2 21 -#define MX31_DMA_REQ_SSI2_RX1 22 -#define MX31_DMA_REQ_SSI2_TX1 23 -#define MX31_DMA_REQ_SSI2_RX0 24 -#define MX31_DMA_REQ_SSI2_TX0 25 -#define MX31_DMA_REQ_SSI1_RX1 26 -#define MX31_DMA_REQ_SSI1_TX1 27 -#define MX31_DMA_REQ_SSI1_RX0 28 -#define MX31_DMA_REQ_SSI1_TX0 29 - -#define MX31_PROD_SIGNATURE 0x1 /* For MX31 */ #endif /* ifndef __MACH_MX31_H__ */ diff --git a/arch/arm/mach-imx/mx31lilly-db.c b/arch/arm/mach-imx/mx31lilly-db.c deleted file mode 100644 index 00a5ee30d5dd..000000000000 --- a/arch/arm/mach-imx/mx31lilly-db.c +++ /dev/null @@ -1,182 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * LILLY-1131 development board support - * - * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de> - * - * based on code for other MX31 boards, - * - * Copyright 2005-2007 Freescale Semiconductor - * Copyright (c) 2009 Alberto Panizzo <maramaopercheseimorto@gmail.com> - * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group - */ - -#include <linux/kernel.h> -#include <linux/types.h> -#include <linux/init.h> -#include <linux/gpio.h> -#include <linux/platform_device.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/map.h> - -#include "board-mx31lilly.h" -#include "common.h" -#include "devices-imx31.h" -#include "hardware.h" -#include "iomux-mx3.h" - -/* - * This file contains board-specific initialization routines for the - * LILLY-1131 development board. If you design an own baseboard for the - * module, use this file as base for support code. - */ - -static unsigned int lilly_db_board_pins[] __initdata = { - MX31_PIN_SD1_DATA3__SD1_DATA3, - MX31_PIN_SD1_DATA2__SD1_DATA2, - MX31_PIN_SD1_DATA1__SD1_DATA1, - MX31_PIN_SD1_DATA0__SD1_DATA0, - MX31_PIN_SD1_CLK__SD1_CLK, - MX31_PIN_SD1_CMD__SD1_CMD, - MX31_PIN_LD0__LD0, - MX31_PIN_LD1__LD1, - MX31_PIN_LD2__LD2, - MX31_PIN_LD3__LD3, - MX31_PIN_LD4__LD4, - MX31_PIN_LD5__LD5, - MX31_PIN_LD6__LD6, - MX31_PIN_LD7__LD7, - MX31_PIN_LD8__LD8, - MX31_PIN_LD9__LD9, - MX31_PIN_LD10__LD10, - MX31_PIN_LD11__LD11, - MX31_PIN_LD12__LD12, - MX31_PIN_LD13__LD13, - MX31_PIN_LD14__LD14, - MX31_PIN_LD15__LD15, - MX31_PIN_LD16__LD16, - MX31_PIN_LD17__LD17, - MX31_PIN_VSYNC3__VSYNC3, - MX31_PIN_HSYNC__HSYNC, - MX31_PIN_FPSHIFT__FPSHIFT, - MX31_PIN_DRDY0__DRDY0, - MX31_PIN_CONTRAST__CONTRAST, -}; - -/* MMC support */ - -static int mxc_mmc1_get_ro(struct device *dev) -{ - return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_LCS0)); -} - -static int gpio_det, gpio_wp; - -#define MMC_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ - PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) - -static int mxc_mmc1_init(struct device *dev, - irq_handler_t detect_irq, void *data) -{ - int ret; - - gpio_det = IOMUX_TO_GPIO(MX31_PIN_GPIO1_1); - gpio_wp = IOMUX_TO_GPIO(MX31_PIN_LCS0); - - mxc_iomux_set_pad(MX31_PIN_SD1_DATA0, MMC_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_SD1_DATA1, MMC_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_SD1_DATA2, MMC_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_SD1_DATA3, MMC_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_SD1_CLK, MMC_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_SD1_CMD, MMC_PAD_CFG); - - ret = gpio_request(gpio_det, "MMC detect"); - if (ret) - return ret; - - ret = gpio_request(gpio_wp, "MMC w/p"); - if (ret) - goto exit_free_det; - - gpio_direction_input(gpio_det); - gpio_direction_input(gpio_wp); - - ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1)), - detect_irq, IRQF_TRIGGER_FALLING, - "MMC detect", data); - if (ret) - goto exit_free_wp; - - return 0; - -exit_free_wp: - gpio_free(gpio_wp); - -exit_free_det: - gpio_free(gpio_det); - - return ret; -} - -static void mxc_mmc1_exit(struct device *dev, void *data) -{ - gpio_free(gpio_det); - gpio_free(gpio_wp); - free_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1)), data); -} - -static const struct imxmmc_platform_data mmc_pdata __initconst = { - .get_ro = mxc_mmc1_get_ro, - .init = mxc_mmc1_init, - .exit = mxc_mmc1_exit, -}; - -/* Framebuffer support */ -static const struct fb_videomode fb_modedb = { - /* 640x480 TFT panel (IPS-056T) */ - .name = "CRT-VGA", - .refresh = 64, - .xres = 640, - .yres = 480, - .pixclock = 30000, - .left_margin = 200, - .right_margin = 2, - .upper_margin = 2, - .lower_margin = 2, - .hsync_len = 3, - .vsync_len = 1, - .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH, - .vmode = FB_VMODE_NONINTERLACED, - .flag = 0, -}; - -static struct mx3fb_platform_data fb_pdata __initdata = { - .name = "CRT-VGA", - .mode = &fb_modedb, - .num_modes = 1, -}; - -#define LCD_VCC_EN_GPIO (7) - -static void __init mx31lilly_init_fb(void) -{ - if (gpio_request(LCD_VCC_EN_GPIO, "LCD enable") != 0) { - printk(KERN_WARNING "unable to request LCD_VCC_EN pin.\n"); - return; - } - - imx31_add_ipu_core(); - imx31_add_mx3_sdc_fb(&fb_pdata); - gpio_direction_output(LCD_VCC_EN_GPIO, 1); -} - -void __init mx31lilly_db_init(void) -{ - mxc_iomux_setup_multiple_pins(lilly_db_board_pins, - ARRAY_SIZE(lilly_db_board_pins), - "development board pins"); - imx31_add_mxc_mmc(0, &mmc_pdata); - mx31lilly_init_fb(); -} diff --git a/arch/arm/mach-imx/mx31lite-db.c b/arch/arm/mach-imx/mx31lite-db.c deleted file mode 100644 index 13da7325c32b..000000000000 --- a/arch/arm/mach-imx/mx31lite-db.c +++ /dev/null @@ -1,154 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * LogicPD i.MX31 SOM-LV development board support - * - * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de> - * - * based on code for other MX31 boards, - * - * Copyright 2005-2007 Freescale Semiconductor - * Copyright (c) 2009 Alberto Panizzo <maramaopercheseimorto@gmail.com> - * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group - */ - -#include <linux/kernel.h> -#include <linux/types.h> -#include <linux/init.h> -#include <linux/gpio.h> -#include <linux/leds.h> -#include <linux/platform_device.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/map.h> - -#include "board-mx31lite.h" -#include "common.h" -#include "devices-imx31.h" -#include "hardware.h" -#include "iomux-mx3.h" - -/* - * This file contains board-specific initialization routines for the - * LogicPD i.MX31 SOM-LV development board, aka 'LiteKit'. - * If you design an own baseboard for the module, use this file as base - * for support code. - */ - -static unsigned int litekit_db_board_pins[] __initdata = { - /* SDHC1 */ - MX31_PIN_SD1_DATA0__SD1_DATA0, - MX31_PIN_SD1_DATA1__SD1_DATA1, - MX31_PIN_SD1_DATA2__SD1_DATA2, - MX31_PIN_SD1_DATA3__SD1_DATA3, - MX31_PIN_SD1_CLK__SD1_CLK, - MX31_PIN_SD1_CMD__SD1_CMD, -}; - -/* MMC */ - -static int gpio_det, gpio_wp; - -#define MMC_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ - PAD_CTL_ODE_CMOS) - -static int mxc_mmc1_get_ro(struct device *dev) -{ - return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_GPIO1_6)); -} - -static int mxc_mmc1_init(struct device *dev, - irq_handler_t detect_irq, void *data) -{ - int ret; - - gpio_det = IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1); - gpio_wp = IOMUX_TO_GPIO(MX31_PIN_GPIO1_6); - - mxc_iomux_set_pad(MX31_PIN_SD1_DATA0, - MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU); - mxc_iomux_set_pad(MX31_PIN_SD1_DATA1, - MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU); - mxc_iomux_set_pad(MX31_PIN_SD1_DATA2, - MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU); - mxc_iomux_set_pad(MX31_PIN_SD1_DATA3, - MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU); - mxc_iomux_set_pad(MX31_PIN_SD1_CMD, - MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU); - mxc_iomux_set_pad(MX31_PIN_SD1_CLK, MMC_PAD_CFG); - - ret = gpio_request(gpio_det, "MMC detect"); - if (ret) - return ret; - - ret = gpio_request(gpio_wp, "MMC w/p"); - if (ret) - goto exit_free_det; - - gpio_direction_input(gpio_det); - gpio_direction_input(gpio_wp); - - ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1)), - detect_irq, - IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, - "MMC detect", data); - if (ret) - goto exit_free_wp; - - return 0; - -exit_free_wp: - gpio_free(gpio_wp); - -exit_free_det: - gpio_free(gpio_det); - - return ret; -} - -static void mxc_mmc1_exit(struct device *dev, void *data) -{ - gpio_free(gpio_det); - gpio_free(gpio_wp); - free_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1)), data); -} - -static const struct imxmmc_platform_data mmc_pdata __initconst = { - .get_ro = mxc_mmc1_get_ro, - .init = mxc_mmc1_init, - .exit = mxc_mmc1_exit, -}; - -/* GPIO LEDs */ - -static const struct gpio_led litekit_leds[] __initconst = { - { - .name = "GPIO0", - .gpio = IOMUX_TO_GPIO(MX31_PIN_COMPARE), - .active_low = 1, - .default_state = LEDS_GPIO_DEFSTATE_OFF, - }, - { - .name = "GPIO1", - .gpio = IOMUX_TO_GPIO(MX31_PIN_CAPTURE), - .active_low = 1, - .default_state = LEDS_GPIO_DEFSTATE_OFF, - } -}; - -static const struct gpio_led_platform_data - litekit_led_platform_data __initconst = { - .leds = litekit_leds, - .num_leds = ARRAY_SIZE(litekit_leds), -}; - -void __init mx31lite_db_init(void) -{ - mxc_iomux_setup_multiple_pins(litekit_db_board_pins, - ARRAY_SIZE(litekit_db_board_pins), - "development board pins"); - imx31_add_mxc_mmc(0, &mmc_pdata); - gpio_led_register_device(-1, &litekit_led_platform_data); - imx31_add_imx2_wdt(); - imx31_add_mxc_rtc(); -} diff --git a/arch/arm/mach-imx/mx31moboard-devboard.c b/arch/arm/mach-imx/mx31moboard-devboard.c deleted file mode 100644 index 6a9db0663a80..000000000000 --- a/arch/arm/mach-imx/mx31moboard-devboard.c +++ /dev/null @@ -1,238 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group - */ - -#include <linux/gpio.h> -#include <linux/init.h> -#include <linux/interrupt.h> -#include <linux/delay.h> -#include <linux/platform_device.h> -#include <linux/slab.h> -#include <linux/types.h> - -#include <linux/usb/otg.h> - -#include "board-mx31moboard.h" -#include "common.h" -#include "devices-imx31.h" -#include "ehci.h" -#include "hardware.h" -#include "iomux-mx3.h" -#include "ulpi.h" - -static unsigned int devboard_pins[] = { - /* UART1 */ - MX31_PIN_CTS2__CTS2, MX31_PIN_RTS2__RTS2, - MX31_PIN_TXD2__TXD2, MX31_PIN_RXD2__RXD2, - /* SDHC2 */ - MX31_PIN_PC_PWRON__SD2_DATA3, MX31_PIN_PC_VS1__SD2_DATA2, - MX31_PIN_PC_READY__SD2_DATA1, MX31_PIN_PC_WAIT_B__SD2_DATA0, - MX31_PIN_PC_CD2_B__SD2_CLK, MX31_PIN_PC_CD1_B__SD2_CMD, - MX31_PIN_ATA_DIOR__GPIO3_28, MX31_PIN_ATA_DIOW__GPIO3_29, - /* USB H1 */ - MX31_PIN_CSPI1_MISO__USBH1_RXDP, MX31_PIN_CSPI1_MOSI__USBH1_RXDM, - MX31_PIN_CSPI1_SS0__USBH1_TXDM, MX31_PIN_CSPI1_SS1__USBH1_TXDP, - MX31_PIN_CSPI1_SS2__USBH1_RCV, MX31_PIN_CSPI1_SCLK__USBH1_OEB, - MX31_PIN_CSPI1_SPI_RDY__USBH1_FS, MX31_PIN_SFS6__USBH1_SUSPEND, - MX31_PIN_NFRE_B__GPIO1_11, MX31_PIN_NFALE__GPIO1_12, - /* SEL */ - MX31_PIN_DTR_DCE1__GPIO2_8, MX31_PIN_DSR_DCE1__GPIO2_9, - MX31_PIN_RI_DCE1__GPIO2_10, MX31_PIN_DCD_DCE1__GPIO2_11, -}; - -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -#define SDHC2_CD IOMUX_TO_GPIO(MX31_PIN_ATA_DIOR) -#define SDHC2_WP IOMUX_TO_GPIO(MX31_PIN_ATA_DIOW) - -static int devboard_sdhc2_get_ro(struct device *dev) -{ - return !gpio_get_value(SDHC2_WP); -} - -static int devboard_sdhc2_init(struct device *dev, irq_handler_t detect_irq, - void *data) -{ - int ret; - - ret = gpio_request(SDHC2_CD, "sdhc-detect"); - if (ret) - return ret; - - gpio_direction_input(SDHC2_CD); - - ret = gpio_request(SDHC2_WP, "sdhc-wp"); - if (ret) - goto err_gpio_free; - gpio_direction_input(SDHC2_WP); - - ret = request_irq(gpio_to_irq(SDHC2_CD), detect_irq, - IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, - "sdhc2-card-detect", data); - if (ret) - goto err_gpio_free_2; - - return 0; - -err_gpio_free_2: - gpio_free(SDHC2_WP); -err_gpio_free: - gpio_free(SDHC2_CD); - - return ret; -} - -static void devboard_sdhc2_exit(struct device *dev, void *data) -{ - free_irq(gpio_to_irq(SDHC2_CD), data); - gpio_free(SDHC2_WP); - gpio_free(SDHC2_CD); -} - -static const struct imxmmc_platform_data sdhc2_pdata __initconst = { - .get_ro = devboard_sdhc2_get_ro, - .init = devboard_sdhc2_init, - .exit = devboard_sdhc2_exit, -}; - -#define SEL0 IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1) -#define SEL1 IOMUX_TO_GPIO(MX31_PIN_DSR_DCE1) -#define SEL2 IOMUX_TO_GPIO(MX31_PIN_RI_DCE1) -#define SEL3 IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1) - -static void devboard_init_sel_gpios(void) -{ - if (!gpio_request(SEL0, "sel0")) { - gpio_direction_input(SEL0); - gpio_export(SEL0, true); - } - - if (!gpio_request(SEL1, "sel1")) { - gpio_direction_input(SEL1); - gpio_export(SEL1, true); - } - - if (!gpio_request(SEL2, "sel2")) { - gpio_direction_input(SEL2); - gpio_export(SEL2, true); - } - - if (!gpio_request(SEL3, "sel3")) { - gpio_direction_input(SEL3); - gpio_export(SEL3, true); - } -} -#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ - PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) - -static int devboard_usbh1_hw_init(struct platform_device *pdev) -{ - mxc_iomux_set_gpr(MUX_PGP_USB_SUSPEND, true); - - mxc_iomux_set_pad(MX31_PIN_CSPI1_MISO, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_CSPI1_MOSI, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_CSPI1_SS0, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_CSPI1_SS1, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_CSPI1_SS2, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_CSPI1_SCLK, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_CSPI1_SPI_RDY, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_SFS6, USB_PAD_CFG); - - mdelay(10); - - return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED | - MXC_EHCI_INTERFACE_SINGLE_UNI); -} - -#define USBH1_VBUSEN_B IOMUX_TO_GPIO(MX31_PIN_NFRE_B) -#define USBH1_MODE IOMUX_TO_GPIO(MX31_PIN_NFALE) - -static int devboard_isp1105_init(struct usb_phy *otg) -{ - int ret = gpio_request(USBH1_MODE, "usbh1-mode"); - if (ret) - return ret; - /* single ended */ - gpio_direction_output(USBH1_MODE, 0); - - ret = gpio_request(USBH1_VBUSEN_B, "usbh1-vbusen"); - if (ret) { - gpio_free(USBH1_MODE); - return ret; - } - gpio_direction_output(USBH1_VBUSEN_B, 1); - - return 0; -} - - -static int devboard_isp1105_set_vbus(struct usb_otg *otg, bool on) -{ - if (on) - gpio_set_value(USBH1_VBUSEN_B, 0); - else - gpio_set_value(USBH1_VBUSEN_B, 1); - - return 0; -} - -static struct mxc_usbh_platform_data usbh1_pdata __initdata = { - .init = devboard_usbh1_hw_init, - .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL, -}; - -static int __init devboard_usbh1_init(void) -{ - struct usb_phy *phy; - struct platform_device *pdev; - - phy = kzalloc(sizeof(*phy), GFP_KERNEL); - if (!phy) - return -ENOMEM; - - phy->otg = kzalloc(sizeof(struct usb_otg), GFP_KERNEL); - if (!phy->otg) { - kfree(phy); - return -ENOMEM; - } - - phy->label = "ISP1105"; - phy->init = devboard_isp1105_init; - phy->otg->set_vbus = devboard_isp1105_set_vbus; - - usbh1_pdata.otg = phy; - - pdev = imx31_add_mxc_ehci_hs(1, &usbh1_pdata); - - return PTR_ERR_OR_ZERO(pdev); -} - - -static const struct fsl_usb2_platform_data usb_pdata __initconst = { - .operating_mode = FSL_USB2_DR_DEVICE, - .phy_mode = FSL_USB2_PHY_ULPI, -}; - -/* - * system init for baseboard usage. Will be called by mx31moboard init. - */ -void __init mx31moboard_devboard_init(void) -{ - printk(KERN_INFO "Initializing mx31devboard peripherals\n"); - - mxc_iomux_setup_multiple_pins(devboard_pins, ARRAY_SIZE(devboard_pins), - "devboard"); - - imx31_add_imx_uart1(&uart_pdata); - - imx31_add_mxc_mmc(1, &sdhc2_pdata); - - devboard_init_sel_gpios(); - - imx31_add_fsl_usb2_udc(&usb_pdata); - - devboard_usbh1_init(); -} diff --git a/arch/arm/mach-imx/mx31moboard-marxbot.c b/arch/arm/mach-imx/mx31moboard-marxbot.c deleted file mode 100644 index c2690008e6fc..000000000000 --- a/arch/arm/mach-imx/mx31moboard-marxbot.c +++ /dev/null @@ -1,270 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group - */ - -#include <linux/delay.h> -#include <linux/gpio.h> -#include <linux/init.h> -#include <linux/interrupt.h> -#include <linux/i2c.h> -#include <linux/spi/spi.h> -#include <linux/slab.h> -#include <linux/platform_device.h> -#include <linux/types.h> - -#include <linux/usb/otg.h> - -#include "board-mx31moboard.h" -#include "common.h" -#include "devices-imx31.h" -#include "ehci.h" -#include "hardware.h" -#include "iomux-mx3.h" -#include "ulpi.h" - -static unsigned int marxbot_pins[] = { - /* SDHC2 */ - MX31_PIN_PC_PWRON__SD2_DATA3, MX31_PIN_PC_VS1__SD2_DATA2, - MX31_PIN_PC_READY__SD2_DATA1, MX31_PIN_PC_WAIT_B__SD2_DATA0, - MX31_PIN_PC_CD2_B__SD2_CLK, MX31_PIN_PC_CD1_B__SD2_CMD, - MX31_PIN_ATA_DIOR__GPIO3_28, MX31_PIN_ATA_DIOW__GPIO3_29, - /* dsPIC resets */ - MX31_PIN_STXD5__GPIO1_21, MX31_PIN_SRXD5__GPIO1_22, - /*battery detection */ - MX31_PIN_LCS0__GPIO3_23, - /* USB H1 */ - MX31_PIN_CSPI1_MISO__USBH1_RXDP, MX31_PIN_CSPI1_MOSI__USBH1_RXDM, - MX31_PIN_CSPI1_SS0__USBH1_TXDM, MX31_PIN_CSPI1_SS1__USBH1_TXDP, - MX31_PIN_CSPI1_SS2__USBH1_RCV, MX31_PIN_CSPI1_SCLK__USBH1_OEB, - MX31_PIN_CSPI1_SPI_RDY__USBH1_FS, MX31_PIN_SFS6__USBH1_SUSPEND, - MX31_PIN_NFRE_B__GPIO1_11, MX31_PIN_NFALE__GPIO1_12, - /* SEL */ - MX31_PIN_DTR_DCE1__GPIO2_8, MX31_PIN_DSR_DCE1__GPIO2_9, - MX31_PIN_RI_DCE1__GPIO2_10, MX31_PIN_DCD_DCE1__GPIO2_11, -}; - -#define SDHC2_CD IOMUX_TO_GPIO(MX31_PIN_ATA_DIOR) -#define SDHC2_WP IOMUX_TO_GPIO(MX31_PIN_ATA_DIOW) - -static int marxbot_sdhc2_get_ro(struct device *dev) -{ - return !gpio_get_value(SDHC2_WP); -} - -static int marxbot_sdhc2_init(struct device *dev, irq_handler_t detect_irq, - void *data) -{ - int ret; - - ret = gpio_request(SDHC2_CD, "sdhc-detect"); - if (ret) - return ret; - - gpio_direction_input(SDHC2_CD); - - ret = gpio_request(SDHC2_WP, "sdhc-wp"); - if (ret) - goto err_gpio_free; - gpio_direction_input(SDHC2_WP); - - ret = request_irq(gpio_to_irq(SDHC2_CD), detect_irq, - IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, - "sdhc2-card-detect", data); - if (ret) - goto err_gpio_free_2; - - return 0; - -err_gpio_free_2: - gpio_free(SDHC2_WP); -err_gpio_free: - gpio_free(SDHC2_CD); - - return ret; -} - -static void marxbot_sdhc2_exit(struct device *dev, void *data) -{ - free_irq(gpio_to_irq(SDHC2_CD), data); - gpio_free(SDHC2_WP); - gpio_free(SDHC2_CD); -} - -static const struct imxmmc_platform_data sdhc2_pdata __initconst = { - .get_ro = marxbot_sdhc2_get_ro, - .init = marxbot_sdhc2_init, - .exit = marxbot_sdhc2_exit, -}; - -#define TRSLAT_RST_B IOMUX_TO_GPIO(MX31_PIN_STXD5) -#define DSPICS_RST_B IOMUX_TO_GPIO(MX31_PIN_SRXD5) - -static void dspics_resets_init(void) -{ - if (!gpio_request(TRSLAT_RST_B, "translator-rst")) { - gpio_direction_output(TRSLAT_RST_B, 0); - gpio_export(TRSLAT_RST_B, false); - } - - if (!gpio_request(DSPICS_RST_B, "dspics-rst")) { - gpio_direction_output(DSPICS_RST_B, 0); - gpio_export(DSPICS_RST_B, false); - } -} - -static struct spi_board_info marxbot_spi_board_info[] __initdata = { - { - .modalias = "spidev", - .max_speed_hz = 300000, - .bus_num = 1, - .chip_select = 1, /* according spi1_cs[] ! */ - }, -}; - -#define SEL0 IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1) -#define SEL1 IOMUX_TO_GPIO(MX31_PIN_DSR_DCE1) -#define SEL2 IOMUX_TO_GPIO(MX31_PIN_RI_DCE1) -#define SEL3 IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1) - -static void marxbot_init_sel_gpios(void) -{ - if (!gpio_request(SEL0, "sel0")) { - gpio_direction_input(SEL0); - gpio_export(SEL0, true); - } - - if (!gpio_request(SEL1, "sel1")) { - gpio_direction_input(SEL1); - gpio_export(SEL1, true); - } - - if (!gpio_request(SEL2, "sel2")) { - gpio_direction_input(SEL2); - gpio_export(SEL2, true); - } - - if (!gpio_request(SEL3, "sel3")) { - gpio_direction_input(SEL3); - gpio_export(SEL3, true); - } -} - -#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ - PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) - -static int marxbot_usbh1_hw_init(struct platform_device *pdev) -{ - mxc_iomux_set_gpr(MUX_PGP_USB_SUSPEND, true); - - mxc_iomux_set_pad(MX31_PIN_CSPI1_MISO, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_CSPI1_MOSI, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_CSPI1_SS0, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_CSPI1_SS1, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_CSPI1_SS2, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_CSPI1_SCLK, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_CSPI1_SPI_RDY, USB_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_SFS6, USB_PAD_CFG); - - mdelay(10); - - return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED | - MXC_EHCI_INTERFACE_SINGLE_UNI); -} - -#define USBH1_VBUSEN_B IOMUX_TO_GPIO(MX31_PIN_NFRE_B) -#define USBH1_MODE IOMUX_TO_GPIO(MX31_PIN_NFALE) - -static int marxbot_isp1105_init(struct usb_phy *otg) -{ - int ret = gpio_request(USBH1_MODE, "usbh1-mode"); - if (ret) - return ret; - /* single ended */ - gpio_direction_output(USBH1_MODE, 0); - - ret = gpio_request(USBH1_VBUSEN_B, "usbh1-vbusen"); - if (ret) { - gpio_free(USBH1_MODE); - return ret; - } - gpio_direction_output(USBH1_VBUSEN_B, 1); - - return 0; -} - - -static int marxbot_isp1105_set_vbus(struct usb_otg *otg, bool on) -{ - if (on) - gpio_set_value(USBH1_VBUSEN_B, 0); - else - gpio_set_value(USBH1_VBUSEN_B, 1); - - return 0; -} - -static struct mxc_usbh_platform_data usbh1_pdata __initdata = { - .init = marxbot_usbh1_hw_init, - .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL, -}; - -static int __init marxbot_usbh1_init(void) -{ - struct usb_phy *phy; - struct platform_device *pdev; - - phy = kzalloc(sizeof(*phy), GFP_KERNEL); - if (!phy) - return -ENOMEM; - - phy->otg = kzalloc(sizeof(struct usb_otg), GFP_KERNEL); - if (!phy->otg) { - kfree(phy); - return -ENOMEM; - } - - phy->label = "ISP1105"; - phy->init = marxbot_isp1105_init; - phy->otg->set_vbus = marxbot_isp1105_set_vbus; - - usbh1_pdata.otg = phy; - - pdev = imx31_add_mxc_ehci_hs(1, &usbh1_pdata); - - return PTR_ERR_OR_ZERO(pdev); -} - -static const struct fsl_usb2_platform_data usb_pdata __initconst = { - .operating_mode = FSL_USB2_DR_DEVICE, - .phy_mode = FSL_USB2_PHY_ULPI, -}; - -/* - * system init for baseboard usage. Will be called by mx31moboard init. - */ -void __init mx31moboard_marxbot_init(void) -{ - printk(KERN_INFO "Initializing mx31marxbot peripherals\n"); - - mxc_iomux_setup_multiple_pins(marxbot_pins, ARRAY_SIZE(marxbot_pins), - "marxbot"); - - marxbot_init_sel_gpios(); - - dspics_resets_init(); - - imx31_add_mxc_mmc(1, &sdhc2_pdata); - - spi_register_board_info(marxbot_spi_board_info, - ARRAY_SIZE(marxbot_spi_board_info)); - - /* battery present pin */ - gpio_request(IOMUX_TO_GPIO(MX31_PIN_LCS0), "bat-present"); - gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_LCS0)); - gpio_export(IOMUX_TO_GPIO(MX31_PIN_LCS0), false); - - imx31_add_fsl_usb2_udc(&usb_pdata); - - marxbot_usbh1_init(); -} diff --git a/arch/arm/mach-imx/mx31moboard-smartbot.c b/arch/arm/mach-imx/mx31moboard-smartbot.c deleted file mode 100644 index d165bd952bad..000000000000 --- a/arch/arm/mach-imx/mx31moboard-smartbot.c +++ /dev/null @@ -1,124 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group - */ - -#include <linux/delay.h> -#include <linux/gpio.h> -#include <linux/init.h> -#include <linux/interrupt.h> -#include <linux/i2c.h> -#include <linux/platform_device.h> -#include <linux/types.h> - -#include <linux/usb/otg.h> -#include <linux/usb/ulpi.h> - -#include "board-mx31moboard.h" -#include "common.h" -#include "devices-imx31.h" -#include "ehci.h" -#include "hardware.h" -#include "iomux-mx3.h" -#include "ulpi.h" - -static unsigned int smartbot_pins[] = { - /* UART1 */ - MX31_PIN_CTS2__CTS2, MX31_PIN_RTS2__RTS2, - MX31_PIN_TXD2__TXD2, MX31_PIN_RXD2__RXD2, - /* ENABLES */ - MX31_PIN_DTR_DCE1__GPIO2_8, MX31_PIN_DSR_DCE1__GPIO2_9, - MX31_PIN_RI_DCE1__GPIO2_10, MX31_PIN_DCD_DCE1__GPIO2_11, -}; - -static const struct imxuart_platform_data uart_pdata __initconst = { - .flags = IMXUART_HAVE_RTSCTS, -}; - -static const struct fsl_usb2_platform_data usb_pdata __initconst = { - .operating_mode = FSL_USB2_DR_DEVICE, - .phy_mode = FSL_USB2_PHY_ULPI, -}; - -#if defined(CONFIG_USB_ULPI) - -static int smartbot_otg_init(struct platform_device *pdev) -{ - return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED); -} - -static struct mxc_usbh_platform_data otg_host_pdata __initdata = { - .init = smartbot_otg_init, - .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, -}; - -static int __init smartbot_otg_host_init(void) -{ - struct platform_device *pdev; - - otg_host_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS | - ULPI_OTG_DRVVBUS_EXT); - if (!otg_host_pdata.otg) - return -ENODEV; - - pdev = imx31_add_mxc_ehci_otg(&otg_host_pdata); - - return PTR_ERR_OR_ZERO(pdev); -} -#else -static inline int smartbot_otg_host_init(void) { return 0; } -#endif - -#define POWER_EN IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1) -#define DSPIC_RST_B IOMUX_TO_GPIO(MX31_PIN_DSR_DCE1) -#define TRSLAT_RST_B IOMUX_TO_GPIO(MX31_PIN_RI_DCE1) -#define TRSLAT_SRC_CHOICE IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1) - -static void smartbot_resets_init(void) -{ - if (!gpio_request(POWER_EN, "power-enable")) { - gpio_direction_output(POWER_EN, 0); - gpio_export(POWER_EN, false); - } - - if (!gpio_request(DSPIC_RST_B, "dspic-rst")) { - gpio_direction_output(DSPIC_RST_B, 0); - gpio_export(DSPIC_RST_B, false); - } - - if (!gpio_request(TRSLAT_RST_B, "translator-rst")) { - gpio_direction_output(TRSLAT_RST_B, 0); - gpio_export(TRSLAT_RST_B, false); - } - - if (!gpio_request(TRSLAT_SRC_CHOICE, "translator-src-choice")) { - gpio_direction_output(TRSLAT_SRC_CHOICE, 0); - gpio_export(TRSLAT_SRC_CHOICE, false); - } -} -/* - * system init for baseboard usage. Will be called by mx31moboard init. - */ -void __init mx31moboard_smartbot_init(int board) -{ - printk(KERN_INFO "Initializing mx31smartbot peripherals\n"); - - mxc_iomux_setup_multiple_pins(smartbot_pins, ARRAY_SIZE(smartbot_pins), - "smartbot"); - - imx31_add_imx_uart1(&uart_pdata); - - switch (board) { - case MX31SMARTBOT: - imx31_add_fsl_usb2_udc(&usb_pdata); - break; - case MX31EYEBOT: - smartbot_otg_host_init(); - break; - default: - printk(KERN_WARNING "Unknown board %d, USB OTG not initialized", - board); - } - - smartbot_resets_init(); -} diff --git a/arch/arm/mach-imx/mx35.h b/arch/arm/mach-imx/mx35.h index 760de6a0af7e..5a8a87a85c14 100644 --- a/arch/arm/mach-imx/mx35.h +++ b/arch/arm/mach-imx/mx35.h @@ -2,190 +2,17 @@ #ifndef __MACH_MX35_H__ #define __MACH_MX35_H__ -/* - * IRAM - */ -#define MX35_IRAM_BASE_ADDR 0x10000000 /* internal ram */ -#define MX35_IRAM_SIZE SZ_128K - -#define MX35_L2CC_BASE_ADDR 0x30000000 -#define MX35_L2CC_SIZE SZ_1M - #define MX35_AIPS1_BASE_ADDR 0x43f00000 #define MX35_AIPS1_SIZE SZ_1M -#define MX35_MAX_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x04000) -#define MX35_EVTMON_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x08000) -#define MX35_CLKCTL_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x0c000) -#define MX35_ETB_SLOT4_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x10000) -#define MX35_ETB_SLOT5_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x14000) -#define MX35_ECT_CTIO_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x18000) -#define MX35_I2C1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x80000) -#define MX35_I2C3_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x84000) -#define MX35_UART1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x90000) -#define MX35_UART2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x94000) -#define MX35_I2C2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x98000) -#define MX35_OWIRE_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x9c000) -#define MX35_SSI1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xa0000) -#define MX35_CSPI1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xa4000) -#define MX35_KPP_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xa8000) -#define MX35_IOMUXC_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xac000) -#define MX35_ECT_IP1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xb8000) -#define MX35_ECT_IP2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xbc000) - #define MX35_SPBA0_BASE_ADDR 0x50000000 #define MX35_SPBA0_SIZE SZ_1M -#define MX35_UART3_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x0c000) -#define MX35_CSPI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x10000) -#define MX35_SSI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x14000) -#define MX35_ATA_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x20000) -#define MX35_MSHC1_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x24000) -#define MX35_FEC_BASE_ADDR 0x50038000 -#define MX35_SPBA_CTRL_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x3c000) - #define MX35_AIPS2_BASE_ADDR 0x53f00000 #define MX35_AIPS2_SIZE SZ_1M -#define MX35_CCM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x80000) -#define MX35_GPT1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x90000) -#define MX35_EPIT1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x94000) -#define MX35_EPIT2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x98000) -#define MX35_GPIO3_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xa4000) -#define MX35_SCC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xac000) -#define MX35_RNGA_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xb0000) -#define MX35_ESDHC1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xb4000) -#define MX35_ESDHC2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xb8000) -#define MX35_ESDHC3_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xbc000) -#define MX35_IPU_CTRL_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xc0000) -#define MX35_AUDMUX_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xc4000) -#define MX35_GPIO1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xcc000) -#define MX35_GPIO2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xd0000) -#define MX35_SDMA_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xd4000) -#define MX35_RTC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xd8000) -#define MX35_WDOG_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xdc000) -#define MX35_PWM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe0000) -#define MX35_CAN1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe4000) -#define MX35_CAN2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe8000) -#define MX35_RTIC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xec000) -#define MX35_IIM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xf0000) -#define MX35_USB_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xf4000) -#define MX35_USB_OTG_BASE_ADDR (MX35_USB_BASE_ADDR + 0x0000) -/* - * The Reference Manual (IMX35RM, Rev. 2, 3/2009) claims an offset of 0x200 for - * HS. When host support was implemented only a preliminary document was - * available, which told 0x400. This works fine. - */ -#define MX35_USB_HS_BASE_ADDR (MX35_USB_BASE_ADDR + 0x0400) - -#define MX35_ROMP_BASE_ADDR 0x60000000 -#define MX35_ROMP_SIZE SZ_1M - #define MX35_AVIC_BASE_ADDR 0x68000000 #define MX35_AVIC_SIZE SZ_1M - -/* - * Memory regions and CS - */ -#define MX35_IPU_MEM_BASE_ADDR 0x70000000 -#define MX35_CSD0_BASE_ADDR 0x80000000 -#define MX35_CSD1_BASE_ADDR 0x90000000 - -#define MX35_CS0_BASE_ADDR 0xa0000000 -#define MX35_CS1_BASE_ADDR 0xa8000000 -#define MX35_CS2_BASE_ADDR 0xb0000000 -#define MX35_CS3_BASE_ADDR 0xb2000000 - -#define MX35_CS4_BASE_ADDR 0xb4000000 -#define MX35_CS4_BASE_ADDR_VIRT 0xf6000000 -#define MX35_CS4_SIZE SZ_32M - -#define MX35_CS5_BASE_ADDR 0xb6000000 -#define MX35_CS5_BASE_ADDR_VIRT 0xf8000000 -#define MX35_CS5_SIZE SZ_32M - -/* - * NAND, SDRAM, WEIM, M3IF, EMI controllers - */ #define MX35_X_MEMC_BASE_ADDR 0xb8000000 #define MX35_X_MEMC_SIZE SZ_64K -#define MX35_ESDCTL_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x1000) -#define MX35_WEIM_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x2000) -#define MX35_M3IF_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x3000) -#define MX35_EMI_CTL_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x4000) -#define MX35_PCMCIA_CTL_BASE_ADDR MX35_EMI_CTL_BASE_ADDR - -#define MX35_NFC_BASE_ADDR 0xbb000000 -#define MX35_PCMCIA_MEM_BASE_ADDR 0xbc000000 #define MX35_IO_P2V(x) IMX_IO_P2V(x) -#define MX35_IO_ADDRESS(x) IOMEM(MX35_IO_P2V(x)) - -/* - * Interrupt numbers - */ -#include <asm/irq.h> -#define MX35_INT_OWIRE (NR_IRQS_LEGACY + 2) -#define MX35_INT_I2C3 (NR_IRQS_LEGACY + 3) -#define MX35_INT_I2C2 (NR_IRQS_LEGACY + 4) -#define MX35_INT_RTIC (NR_IRQS_LEGACY + 6) -#define MX35_INT_ESDHC1 (NR_IRQS_LEGACY + 7) -#define MX35_INT_ESDHC2 (NR_IRQS_LEGACY + 8) -#define MX35_INT_ESDHC3 (NR_IRQS_LEGACY + 9) -#define MX35_INT_I2C1 (NR_IRQS_LEGACY + 10) -#define MX35_INT_SSI1 (NR_IRQS_LEGACY + 11) -#define MX35_INT_SSI2 (NR_IRQS_LEGACY + 12) -#define MX35_INT_CSPI2 (NR_IRQS_LEGACY + 13) -#define MX35_INT_CSPI1 (NR_IRQS_LEGACY + 14) -#define MX35_INT_ATA (NR_IRQS_LEGACY + 15) -#define MX35_INT_GPU2D (NR_IRQS_LEGACY + 16) -#define MX35_INT_ASRC (NR_IRQS_LEGACY + 17) -#define MX35_INT_UART3 (NR_IRQS_LEGACY + 18) -#define MX35_INT_IIM (NR_IRQS_LEGACY + 19) -#define MX35_INT_RNGA (NR_IRQS_LEGACY + 22) -#define MX35_INT_EVTMON (NR_IRQS_LEGACY + 23) -#define MX35_INT_KPP (NR_IRQS_LEGACY + 24) -#define MX35_INT_RTC (NR_IRQS_LEGACY + 25) -#define MX35_INT_PWM (NR_IRQS_LEGACY + 26) -#define MX35_INT_EPIT2 (NR_IRQS_LEGACY + 27) -#define MX35_INT_EPIT1 (NR_IRQS_LEGACY + 28) -#define MX35_INT_GPT (NR_IRQS_LEGACY + 29) -#define MX35_INT_POWER_FAIL (NR_IRQS_LEGACY + 30) -#define MX35_INT_UART2 (NR_IRQS_LEGACY + 32) -#define MX35_INT_NFC (NR_IRQS_LEGACY + 33) -#define MX35_INT_SDMA (NR_IRQS_LEGACY + 34) -#define MX35_INT_USB_HS (NR_IRQS_LEGACY + 35) -#define MX35_INT_USB_OTG (NR_IRQS_LEGACY + 37) -#define MX35_INT_MSHC1 (NR_IRQS_LEGACY + 39) -#define MX35_INT_ESAI (NR_IRQS_LEGACY + 40) -#define MX35_INT_IPU_ERR (NR_IRQS_LEGACY + 41) -#define MX35_INT_IPU_SYN (NR_IRQS_LEGACY + 42) -#define MX35_INT_CAN1 (NR_IRQS_LEGACY + 43) -#define MX35_INT_CAN2 (NR_IRQS_LEGACY + 44) -#define MX35_INT_UART1 (NR_IRQS_LEGACY + 45) -#define MX35_INT_MLB (NR_IRQS_LEGACY + 46) -#define MX35_INT_SPDIF (NR_IRQS_LEGACY + 47) -#define MX35_INT_ECT (NR_IRQS_LEGACY + 48) -#define MX35_INT_SCC_SCM (NR_IRQS_LEGACY + 49) -#define MX35_INT_SCC_SMN (NR_IRQS_LEGACY + 50) -#define MX35_INT_GPIO2 (NR_IRQS_LEGACY + 51) -#define MX35_INT_GPIO1 (NR_IRQS_LEGACY + 52) -#define MX35_INT_WDOG (NR_IRQS_LEGACY + 55) -#define MX35_INT_GPIO3 (NR_IRQS_LEGACY + 56) -#define MX35_INT_FEC (NR_IRQS_LEGACY + 57) -#define MX35_INT_EXT_POWER (NR_IRQS_LEGACY + 58) -#define MX35_INT_EXT_TEMPER (NR_IRQS_LEGACY + 59) -#define MX35_INT_EXT_SENSOR60 (NR_IRQS_LEGACY + 60) -#define MX35_INT_EXT_SENSOR61 (NR_IRQS_LEGACY + 61) -#define MX35_INT_EXT_WDOG (NR_IRQS_LEGACY + 62) -#define MX35_INT_EXT_TV (NR_IRQS_LEGACY + 63) - -#define MX35_DMA_REQ_SSI2_RX1 22 -#define MX35_DMA_REQ_SSI2_TX1 23 -#define MX35_DMA_REQ_SSI2_RX0 24 -#define MX35_DMA_REQ_SSI2_TX0 25 -#define MX35_DMA_REQ_SSI1_RX1 26 -#define MX35_DMA_REQ_SSI1_TX1 27 -#define MX35_DMA_REQ_SSI1_RX0 28 -#define MX35_DMA_REQ_SSI1_TX0 29 - -#define MX35_PROD_SIGNATURE 0x1 /* For MX31 */ #endif /* ifndef __MACH_MX35_H__ */ diff --git a/arch/arm/mach-imx/pcm037.h b/arch/arm/mach-imx/pcm037.h deleted file mode 100644 index 470d3c887e14..000000000000 --- a/arch/arm/mach-imx/pcm037.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __PCM037_H__ -#define __PCM037_H__ - -enum pcm037_board_variant { - PCM037_PCM970, - PCM037_EET, -}; - -extern enum pcm037_board_variant pcm037_variant(void); - -#ifdef CONFIG_MACH_PCM037_EET -int pcm037_eet_init_devices(void); -#else -static inline int pcm037_eet_init_devices(void) { return 0; } -#endif - -#endif diff --git a/arch/arm/mach-imx/pm-imx27.c b/arch/arm/mach-imx/pm-imx27.c index d943535566c8..020e6deb67c8 100644 --- a/arch/arm/mach-imx/pm-imx27.c +++ b/arch/arm/mach-imx/pm-imx27.c @@ -7,6 +7,7 @@ * modify it under the terms of the GNU General Public License. */ +#include <linux/of_address.h> #include <linux/kernel.h> #include <linux/suspend.h> #include <linux/io.h> @@ -15,13 +16,20 @@ static int mx27_suspend_enter(suspend_state_t state) { + void __iomem *ccm_base; + struct device_node *np; u32 cscr; + + np = of_find_compatible_node(NULL, NULL, "fsl,imx27-ccm"); + ccm_base = of_iomap(np, 0); + BUG_ON(!ccm_base); + switch (state) { case PM_SUSPEND_MEM: /* Clear MPEN and SPEN to disable MPLL/SPLL */ - cscr = imx_readl(MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR)); + cscr = imx_readl(ccm_base); cscr &= 0xFFFFFFFC; - imx_writel(cscr, MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR)); + imx_writel(cscr, ccm_base); /* Executes WFI */ cpu_do_idle(); break; diff --git a/arch/arm/mach-imx/ulpi.h b/arch/arm/mach-imx/ulpi.h deleted file mode 100644 index b367902c9c32..000000000000 --- a/arch/arm/mach-imx/ulpi.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __MACH_ULPI_H -#define __MACH_ULPI_H - -#include <linux/usb/ulpi.h> - -#ifdef CONFIG_USB_ULPI_VIEWPORT -static inline struct usb_phy *imx_otg_ulpi_create(unsigned int flags) -{ - return otg_ulpi_create(&ulpi_viewport_access_ops, flags); -} -#else -static inline struct usb_phy *imx_otg_ulpi_create(unsigned int flags) -{ - return NULL; -} -#endif - -#endif /* __MACH_ULPI_H */ - diff --git a/arch/arm/mach-mstar/Kconfig b/arch/arm/mach-mstar/Kconfig index 52744fe32368..576d1ab293c8 100644 --- a/arch/arm/mach-mstar/Kconfig +++ b/arch/arm/mach-mstar/Kconfig @@ -3,6 +3,7 @@ menuconfig ARCH_MSTARV7 depends on ARCH_MULTI_V7 select ARM_GIC select ARM_HEAVY_MB + select MST_IRQ help Support for newer MStar/Sigmastar SoC families that are based on Armv7 cores like the Cortex A7 and share the same diff --git a/arch/arm/mach-mvebu/coherency_ll.S b/arch/arm/mach-mvebu/coherency_ll.S index 2d962fe48821..a3a64bf97250 100644 --- a/arch/arm/mach-mvebu/coherency_ll.S +++ b/arch/arm/mach-mvebu/coherency_ll.S @@ -35,13 +35,8 @@ ENTRY(ll_get_coherency_base) /* * MMU is disabled, use the physical address of the coherency - * base address. However, if the coherency fabric isn't mapped - * (i.e its virtual address is zero), it means coherency is - * not enabled, so we return 0. + * base address, (or 0x0 if the coherency fabric is not mapped) */ - ldr r1, =coherency_base - cmp r1, #0 - beq 2f adr r1, 3f ldr r3, [r1] ldr r1, [r1, r3] diff --git a/arch/arm/mach-omap1/include/mach/mux.h b/arch/arm/mach-omap1/include/mach/mux.h index adfe1f6bd0c5..3f6dc55d9898 100644 --- a/arch/arm/mach-omap1/include/mach/mux.h +++ b/arch/arm/mach-omap1/include/mach/mux.h @@ -88,7 +88,7 @@ * OMAP730/850 has a slightly different config for the pin mux. * - config regs are the OMAP7XX_IO_CONF_x regs (see omap7xx.h) regs and * not the FUNC_MUX_CTRL_x regs from hardware.h - * - for pull-up/down, only has one enable bit which is is in the same register + * - for pull-up/down, only has one enable bit which is in the same register * as mux config */ #define MUX_CFG_7XX(desc, mux_reg, mode_offset, mode, \ diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index ea23205bf70f..3ee7bdff86b2 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -7,6 +7,7 @@ config ARCH_OMAP2 depends on ARCH_MULTI_V6 select ARCH_OMAP2PLUS select CPU_V6 + select PM_GENERIC_DOMAINS if PM select SOC_HAS_OMAP2_SDRC config ARCH_OMAP3 diff --git a/arch/arm/mach-omap2/am33xx.h b/arch/arm/mach-omap2/am33xx.h index 5eef093e6738..bf2b5f87e404 100644 --- a/arch/arm/mach-omap2/am33xx.h +++ b/arch/arm/mach-omap2/am33xx.h @@ -1,7 +1,7 @@ /* * This file contains the address info for various AM33XX modules. * - * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/ + * Copyright (C) 2011 Texas Instruments, Inc. - https://www.ti.com/ * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c index 334923d7652d..7290f033fd2d 100644 --- a/arch/arm/mach-omap2/board-generic.c +++ b/arch/arm/mach-omap2/board-generic.c @@ -3,7 +3,7 @@ * Copyright (C) 2005 Nokia Corporation * Author: Paul Mundt <paul.mundt@nokia.com> * - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ * * Modified from the original mach-omap/omap2/board-generic.c did by Paul * to support the OMAP2+ device tree boards with an unique board file. diff --git a/arch/arm/mach-omap2/clockdomains33xx_data.c b/arch/arm/mach-omap2/clockdomains33xx_data.c index 32c90fd9eba2..b4d5144df445 100644 --- a/arch/arm/mach-omap2/clockdomains33xx_data.c +++ b/arch/arm/mach-omap2/clockdomains33xx_data.c @@ -1,7 +1,7 @@ /* * AM33XX Clock Domain data. * - * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/ * Vaibhav Hiremath <hvaibhav@ti.com> * * This program is free software; you can redistribute it and/or diff --git a/arch/arm/mach-omap2/clockdomains81xx_data.c b/arch/arm/mach-omap2/clockdomains81xx_data.c index 65fbd136b20c..127dc7ace71f 100644 --- a/arch/arm/mach-omap2/clockdomains81xx_data.c +++ b/arch/arm/mach-omap2/clockdomains81xx_data.c @@ -1,7 +1,7 @@ /* * TI81XX Clock Domain data. * - * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/ + * Copyright (C) 2010 Texas Instruments, Inc. - https://www.ti.com/ * Copyright (C) 2013 SKTB SKiT, http://www.skitlab.ru/ * * This program is free software; you can redistribute it and/or diff --git a/arch/arm/mach-omap2/cm-regbits-33xx.h b/arch/arm/mach-omap2/cm-regbits-33xx.h index c0823fd6d5e0..e7ae2bb515e3 100644 --- a/arch/arm/mach-omap2/cm-regbits-33xx.h +++ b/arch/arm/mach-omap2/cm-regbits-33xx.h @@ -4,7 +4,7 @@ * This file is automatically generated from the AM33XX hardware databases. * Vaibhav Hiremath <hvaibhav@ti.com> * - * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/ * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/arch/arm/mach-omap2/cm-regbits-54xx.h b/arch/arm/mach-omap2/cm-regbits-54xx.h index 44663b575bf4..fc886883866f 100644 --- a/arch/arm/mach-omap2/cm-regbits-54xx.h +++ b/arch/arm/mach-omap2/cm-regbits-54xx.h @@ -2,7 +2,7 @@ /* * OMAP54xx Clock Management register bits * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com * * Paul Walmsley (paul@pwsan.com) * Rajendra Nayak (rnayak@ti.com) diff --git a/arch/arm/mach-omap2/cm-regbits-7xx.h b/arch/arm/mach-omap2/cm-regbits-7xx.h index a78ccbaab1a6..2725af4d1f87 100644 --- a/arch/arm/mach-omap2/cm-regbits-7xx.h +++ b/arch/arm/mach-omap2/cm-regbits-7xx.h @@ -2,7 +2,7 @@ /* * DRA7xx Clock Management register bits * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com * * Generated by code originally written by: * Paul Walmsley (paul@pwsan.com) diff --git a/arch/arm/mach-omap2/cm1_54xx.h b/arch/arm/mach-omap2/cm1_54xx.h index 7be363a27a40..eb86bbd93f35 100644 --- a/arch/arm/mach-omap2/cm1_54xx.h +++ b/arch/arm/mach-omap2/cm1_54xx.h @@ -2,7 +2,7 @@ /* * OMAP54xx CM1 instance offset macros * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com * * Paul Walmsley (paul@pwsan.com) * Rajendra Nayak (rnayak@ti.com) diff --git a/arch/arm/mach-omap2/cm1_7xx.h b/arch/arm/mach-omap2/cm1_7xx.h index 28660edc7f5f..aae3831f5233 100644 --- a/arch/arm/mach-omap2/cm1_7xx.h +++ b/arch/arm/mach-omap2/cm1_7xx.h @@ -2,7 +2,7 @@ /* * DRA7xx CM1 instance offset macros * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com * * Generated by code originally written by: * Paul Walmsley (paul@pwsan.com) diff --git a/arch/arm/mach-omap2/cm2_54xx.h b/arch/arm/mach-omap2/cm2_54xx.h index c5da1f5cae93..8e49765cd441 100644 --- a/arch/arm/mach-omap2/cm2_54xx.h +++ b/arch/arm/mach-omap2/cm2_54xx.h @@ -2,7 +2,7 @@ /* * OMAP54xx CM2 instance offset macros * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com * * Paul Walmsley (paul@pwsan.com) * Rajendra Nayak (rnayak@ti.com) diff --git a/arch/arm/mach-omap2/cm2_7xx.h b/arch/arm/mach-omap2/cm2_7xx.h index e16fc58ef152..f8734605b1e1 100644 --- a/arch/arm/mach-omap2/cm2_7xx.h +++ b/arch/arm/mach-omap2/cm2_7xx.h @@ -2,7 +2,7 @@ /* * DRA7xx CM2 instance offset macros * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com * * Generated by code originally written by: * Paul Walmsley (paul@pwsan.com) diff --git a/arch/arm/mach-omap2/cm33xx.c b/arch/arm/mach-omap2/cm33xx.c index 084d454f6074..ac4882ebdca3 100644 --- a/arch/arm/mach-omap2/cm33xx.c +++ b/arch/arm/mach-omap2/cm33xx.c @@ -1,7 +1,7 @@ /* * AM33XX CM functions * - * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/ * Vaibhav Hiremath <hvaibhav@ti.com> * * Reference taken from from OMAP4 cminst44xx.c diff --git a/arch/arm/mach-omap2/cm33xx.h b/arch/arm/mach-omap2/cm33xx.h index a91f7d282455..63b362bfc4d9 100644 --- a/arch/arm/mach-omap2/cm33xx.h +++ b/arch/arm/mach-omap2/cm33xx.h @@ -1,7 +1,7 @@ /* * AM33XX CM offset macros * - * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/ * Vaibhav Hiremath <hvaibhav@ti.com> * * This program is free software; you can redistribute it and/or diff --git a/arch/arm/mach-omap2/cm81xx.h b/arch/arm/mach-omap2/cm81xx.h index 5d73a1057c82..bd91223e838e 100644 --- a/arch/arm/mach-omap2/cm81xx.h +++ b/arch/arm/mach-omap2/cm81xx.h @@ -1,7 +1,7 @@ /* * Clock domain register offsets for TI81XX. * - * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/ + * Copyright (C) 2010 Texas Instruments, Inc. - https://www.ti.com/ * Copyright (C) 2013 SKTB SKiT, http://www.skitlab.ru/ * * This program is free software; you can redistribute it and/or diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c index 6f5f89711f25..a92d277f81a0 100644 --- a/arch/arm/mach-omap2/cpuidle44xx.c +++ b/arch/arm/mach-omap2/cpuidle44xx.c @@ -174,8 +174,10 @@ static int omap_enter_idle_coupled(struct cpuidle_device *dev, */ if (mpuss_can_lose_context) { error = cpu_cluster_pm_enter(); - if (error) + if (error) { + omap_set_pwrdm_state(mpu_pd, PWRDM_POWER_ON); goto cpu_cluster_pm_out; + } } } diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c index 46012ca812f4..2000fca6bd4e 100644 --- a/arch/arm/mach-omap2/display.c +++ b/arch/arm/mach-omap2/display.c @@ -1,7 +1,7 @@ /* * OMAP2plus display device setup / initialization. * - * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/ * Senthilvadivu Guruswamy * Sumit Semwal * diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c index 8cc109cc242a..dfc9b21ff19b 100644 --- a/arch/arm/mach-omap2/dma.c +++ b/arch/arm/mach-omap2/dma.c @@ -13,7 +13,7 @@ * Copyright (C) 2009 Texas Instruments * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> * - * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/ * Converted DMA library into platform driver * - G, Manjunath Kondaiah <manjugk@ti.com> */ diff --git a/arch/arm/mach-omap2/l3_2xxx.h b/arch/arm/mach-omap2/l3_2xxx.h index c2bd8d86202b..6297c62428ac 100644 --- a/arch/arm/mach-omap2/l3_2xxx.h +++ b/arch/arm/mach-omap2/l3_2xxx.h @@ -2,7 +2,7 @@ /* * arch/arm/plat-omap/include/plat/l3_2xxx.h - L3 firewall definitions * - * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/ * Sumit Semwal */ #ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_2XXX_H diff --git a/arch/arm/mach-omap2/l3_3xxx.h b/arch/arm/mach-omap2/l3_3xxx.h index 995ebccd13e0..60ea7b201fdc 100644 --- a/arch/arm/mach-omap2/l3_3xxx.h +++ b/arch/arm/mach-omap2/l3_3xxx.h @@ -2,7 +2,7 @@ /* * arch/arm/plat-omap/include/plat/l3_3xxx.h - L3 firewall definitions * - * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/ * Sumit Semwal */ #ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_3XXX_H diff --git a/arch/arm/mach-omap2/l4_2xxx.h b/arch/arm/mach-omap2/l4_2xxx.h index 556e69c2bd00..418e1072d730 100644 --- a/arch/arm/mach-omap2/l4_2xxx.h +++ b/arch/arm/mach-omap2/l4_2xxx.h @@ -2,7 +2,7 @@ /* * arch/arm/plat-omap/include/plat/l4_2xxx.h - L4 firewall definitions * - * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/ * Sumit Semwal */ #ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L4_2XXX_H diff --git a/arch/arm/mach-omap2/omap-iommu.c b/arch/arm/mach-omap2/omap-iommu.c index bfa5e1b8dba7..93c20bbd7b7e 100644 --- a/arch/arm/mach-omap2/omap-iommu.c +++ b/arch/arm/mach-omap2/omap-iommu.c @@ -2,7 +2,7 @@ /* * OMAP IOMMU quirks for various TI SoCs * - * Copyright (C) 2015-2019 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2015-2019 Texas Instruments Incorporated - https://www.ti.com/ * Suman Anna <s-anna@ti.com> */ diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h index 5f4ab24dd60d..e29841072287 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h @@ -26,7 +26,6 @@ extern struct omap_hwmod_ocp_if am33xx_mpu__prcm; extern struct omap_hwmod_ocp_if am33xx_l3_s__l3_main; extern struct omap_hwmod_ocp_if am33xx_gfx__l3_main; extern struct omap_hwmod_ocp_if am33xx_l3_main__gfx; -extern struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc; extern struct omap_hwmod_ocp_if am33xx_l3_s__gpmc; extern struct omap_hwmod_ocp_if am33xx_l4_ls__timer2; extern struct omap_hwmod_ocp_if am33xx_l3_main__ocmc; @@ -43,7 +42,6 @@ extern struct omap_hwmod am33xx_ocmcram_hwmod; extern struct omap_hwmod am33xx_smartreflex0_hwmod; extern struct omap_hwmod am33xx_smartreflex1_hwmod; extern struct omap_hwmod am33xx_gpmc_hwmod; -extern struct omap_hwmod am33xx_rtc_hwmod; extern struct omap_hwmod_class am33xx_emif_hwmod_class; extern struct omap_hwmod_class am33xx_l4_hwmod_class; diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c index b389d6589c32..ab5146bfe941 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c @@ -74,30 +74,6 @@ struct omap_hwmod_ocp_if am33xx_l3_s__l3_main = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* gfx -> l3 main */ -struct omap_hwmod_ocp_if am33xx_gfx__l3_main = { - .master = &am33xx_gfx_hwmod, - .slave = &am33xx_l3_main_hwmod, - .clk = "dpll_core_m4_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l3 main -> gfx */ -struct omap_hwmod_ocp_if am33xx_l3_main__gfx = { - .master = &am33xx_l3_main_hwmod, - .slave = &am33xx_gfx_hwmod, - .clk = "dpll_core_m4_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* l4 wkup -> rtc */ -struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc = { - .master = &am33xx_l4_wkup_hwmod, - .slave = &am33xx_rtc_hwmod, - .clk = "clkdiv32k_ick", - .user = OCP_USER_MPU, -}; - /* l3s cfg -> gpmc */ struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = { .master = &am33xx_l3_s_hwmod, diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c index 4b3cd590fb52..bcc120ed610a 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c @@ -26,7 +26,6 @@ #define CLKCTRL(oh, clkctrl) ((oh).prcm.omap4.clkctrl_offs = (clkctrl)) #define RSTCTRL(oh, rstctrl) ((oh).prcm.omap4.rstctrl_offs = (rstctrl)) #define RSTST(oh, rstst) ((oh).prcm.omap4.rstst_offs = (rstst)) -#define PRCM_FLAGS(oh, flag) ((oh).prcm.omap4.flags = (flag)) /* * 'l3' class @@ -133,30 +132,6 @@ struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = { .name = "wkup_m3", }; -/* gfx */ -/* Pseudo hwmod for reset control purpose only */ -static struct omap_hwmod_class am33xx_gfx_hwmod_class = { - .name = "gfx", -}; - -static struct omap_hwmod_rst_info am33xx_gfx_resets[] = { - { .name = "gfx", .rst_shift = 0, .st_shift = 0}, -}; - -struct omap_hwmod am33xx_gfx_hwmod = { - .name = "gfx", - .class = &am33xx_gfx_hwmod_class, - .clkdm_name = "gfx_l3_clkdm", - .main_clk = "gfx_fck_div_ck", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, - .rst_lines = am33xx_gfx_resets, - .rst_lines_cnt = ARRAY_SIZE(am33xx_gfx_resets), -}; - /* * 'prcm' class * power and reset manager (whole prcm infrastructure) @@ -274,67 +249,24 @@ struct omap_hwmod am33xx_gpmc_hwmod = { }, }; - -/* - * 'rtc' class - * rtc subsystem - */ -static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = { - .rev_offs = 0x0074, - .sysc_offs = 0x0078, - .sysc_flags = SYSC_HAS_SIDLEMODE, - .idlemodes = (SIDLE_FORCE | SIDLE_NO | - SIDLE_SMART | SIDLE_SMART_WKUP), - .sysc_fields = &omap_hwmod_sysc_type3, -}; - -static struct omap_hwmod_class am33xx_rtc_hwmod_class = { - .name = "rtc", - .sysc = &am33xx_rtc_sysc, - .unlock = &omap_hwmod_rtc_unlock, - .lock = &omap_hwmod_rtc_lock, -}; - -struct omap_hwmod am33xx_rtc_hwmod = { - .name = "rtc", - .class = &am33xx_rtc_hwmod_class, - .clkdm_name = "l4_rtc_clkdm", - .main_clk = "clk_32768_ck", - .prcm = { - .omap4 = { - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - static void omap_hwmod_am33xx_clkctrl(void) { CLKCTRL(am33xx_smartreflex0_hwmod, AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET); CLKCTRL(am33xx_smartreflex1_hwmod, AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET); - CLKCTRL(am33xx_rtc_hwmod, AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET); - PRCM_FLAGS(am33xx_rtc_hwmod, HWMOD_OMAP4_ZERO_CLKCTRL_OFFSET); CLKCTRL(am33xx_gpmc_hwmod, AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET); CLKCTRL(am33xx_l4_ls_hwmod, AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET); CLKCTRL(am33xx_l4_wkup_hwmod, AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET); CLKCTRL(am33xx_l3_main_hwmod, AM33XX_CM_PER_L3_CLKCTRL_OFFSET); - CLKCTRL(am33xx_gfx_hwmod, AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET); CLKCTRL(am33xx_mpu_hwmod , AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET); CLKCTRL(am33xx_l3_instr_hwmod , AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET); CLKCTRL(am33xx_ocmcram_hwmod , AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET); } -static void omap_hwmod_am33xx_rst(void) -{ - RSTCTRL(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTCTRL_OFFSET); - RSTST(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTST_OFFSET); -} - void omap_hwmod_am33xx_reg(void) { omap_hwmod_am33xx_clkctrl(); - omap_hwmod_am33xx_rst(); } static void omap_hwmod_am43xx_clkctrl(void) @@ -343,25 +275,16 @@ static void omap_hwmod_am43xx_clkctrl(void) AM43XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET); CLKCTRL(am33xx_smartreflex1_hwmod, AM43XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET); - CLKCTRL(am33xx_rtc_hwmod, AM43XX_CM_RTC_RTC_CLKCTRL_OFFSET); CLKCTRL(am33xx_gpmc_hwmod, AM43XX_CM_PER_GPMC_CLKCTRL_OFFSET); CLKCTRL(am33xx_l4_ls_hwmod, AM43XX_CM_PER_L4LS_CLKCTRL_OFFSET); CLKCTRL(am33xx_l4_wkup_hwmod, AM43XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET); CLKCTRL(am33xx_l3_main_hwmod, AM43XX_CM_PER_L3_CLKCTRL_OFFSET); - CLKCTRL(am33xx_gfx_hwmod, AM43XX_CM_GFX_GFX_CLKCTRL_OFFSET); CLKCTRL(am33xx_mpu_hwmod , AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET); CLKCTRL(am33xx_l3_instr_hwmod , AM43XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET); CLKCTRL(am33xx_ocmcram_hwmod , AM43XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET); } -static void omap_hwmod_am43xx_rst(void) -{ - RSTCTRL(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTCTRL_OFFSET); - RSTST(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTST_OFFSET); -} - void omap_hwmod_am43xx_reg(void) { omap_hwmod_am43xx_clkctrl(); - omap_hwmod_am43xx_rst(); } diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c index 3cf9c4c90b18..b232f6ca6fe3 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c @@ -1,7 +1,7 @@ /* * omap_hwmod_33xx_data.c: Hardware modules present on the AM33XX chips * - * Copyright (C) {2012} Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) {2012} Texas Instruments Incorporated - https://www.ti.com/ * * This file is automatically generated from the AM33XX hardware databases. * This program is free software; you can redistribute it and/or @@ -274,16 +274,13 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = { &am33xx_l3_main__l4_hs, &am33xx_l3_main__l3_s, &am33xx_l3_main__l3_instr, - &am33xx_l3_main__gfx, &am33xx_l3_s__l3_main, &am33xx_wkup_m3__l4_wkup, - &am33xx_gfx__l3_main, &am33xx_l3_main__debugss, &am33xx_l4_wkup__wkup_m3, &am33xx_l4_wkup__control, &am33xx_l4_wkup__smartreflex0, &am33xx_l4_wkup__smartreflex1, - &am33xx_l4_wkup__rtc, &am33xx_l3_s__gpmc, &am33xx_l3_main__ocmc, NULL, diff --git a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c index b88d12de68a2..b97cb745bbbc 100644 --- a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c @@ -143,11 +143,9 @@ static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = { &am43xx_l3_main__l4_hs, &am33xx_l3_main__l3_s, &am33xx_l3_main__l3_instr, - &am33xx_l3_main__gfx, &am33xx_l3_s__l3_main, &am43xx_l3_main__emif, &am43xx_wkup_m3__l4_wkup, - &am33xx_gfx__l3_main, &am43xx_l4_wkup__wkup_m3, &am43xx_l4_wkup__control, &am43xx_l4_wkup__smartreflex0, @@ -157,11 +155,6 @@ static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = { NULL, }; -static struct omap_hwmod_ocp_if *am43xx_rtc_hwmod_ocp_ifs[] __initdata = { - &am33xx_l4_wkup__rtc, - NULL, -}; - int __init am43xx_hwmod_init(void) { int ret; @@ -170,8 +163,5 @@ int __init am43xx_hwmod_init(void) omap_hwmod_init(); ret = omap_hwmod_register_links(am43xx_hwmod_ocp_ifs); - if (!ret && of_machine_is_compatible("ti,am4372")) - ret = omap_hwmod_register_links(am43xx_rtc_hwmod_ocp_ifs); - return ret; } diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 665ca74a834a..37c59115b353 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -124,21 +124,6 @@ static struct omap_hwmod_class omap44xx_l4_hwmod_class = { .name = "l4", }; -/* l4_abe */ -static struct omap_hwmod omap44xx_l4_abe_hwmod = { - .name = "l4_abe", - .class = &omap44xx_l4_hwmod_class, - .clkdm_name = "abe_clkdm", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET, - .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET, - .lostcontext_mask = OMAP4430_LOSTMEM_AESSMEM_MASK, - .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, - }, - }, -}; - /* l4_cfg */ static struct omap_hwmod omap44xx_l4_cfg_hwmod = { .name = "l4_cfg", @@ -771,22 +756,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* l3_main_1 -> l4_abe */ -static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = { - .master = &omap44xx_l3_main_1_hwmod, - .slave = &omap44xx_l4_abe_hwmod, - .clk = "l3_div_ck", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* mpu -> l4_abe */ -static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = { - .master = &omap44xx_mpu_hwmod, - .slave = &omap44xx_l4_abe_hwmod, - .clk = "ocp_abe_iclk", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* l3_main_1 -> l4_cfg */ static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = { .master = &omap44xx_l3_main_1_hwmod, @@ -988,8 +957,6 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { &omap44xx_l3_main_1__l3_main_3, &omap44xx_l3_main_2__l3_main_3, &omap44xx_l4_cfg__l3_main_3, - &omap44xx_l3_main_1__l4_abe, - &omap44xx_mpu__l4_abe, &omap44xx_l3_main_1__l4_cfg, &omap44xx_l3_main_2__l4_per, &omap44xx_l4_cfg__l4_wkup, diff --git a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c index 7c38c1ba58ac..85b9ab4756ed 100644 --- a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c @@ -2,7 +2,7 @@ /* * Hardware modules present on the OMAP54xx chips * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com * * Paul Walmsley * Benoit Cousson @@ -121,19 +121,6 @@ static struct omap_hwmod_class omap54xx_l4_hwmod_class = { .name = "l4", }; -/* l4_abe */ -static struct omap_hwmod omap54xx_l4_abe_hwmod = { - .name = "l4_abe", - .class = &omap54xx_l4_hwmod_class, - .clkdm_name = "abe_clkdm", - .prcm = { - .omap4 = { - .clkctrl_offs = OMAP54XX_CM_ABE_L4_ABE_CLKCTRL_OFFSET, - .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, - }, - }, -}; - /* l4_cfg */ static struct omap_hwmod omap54xx_l4_cfg_hwmod = { .name = "l4_cfg", @@ -395,22 +382,6 @@ static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_3 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* l3_main_1 -> l4_abe */ -static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_abe = { - .master = &omap54xx_l3_main_1_hwmod, - .slave = &omap54xx_l4_abe_hwmod, - .clk = "abe_iclk", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - -/* mpu -> l4_abe */ -static struct omap_hwmod_ocp_if omap54xx_mpu__l4_abe = { - .master = &omap54xx_mpu_hwmod, - .slave = &omap54xx_l4_abe_hwmod, - .clk = "abe_iclk", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* l3_main_1 -> l4_cfg */ static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_cfg = { .master = &omap54xx_l3_main_1_hwmod, @@ -478,8 +449,6 @@ static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = { &omap54xx_l3_main_1__l3_main_3, &omap54xx_l3_main_2__l3_main_3, &omap54xx_l4_cfg__l3_main_3, - &omap54xx_l3_main_1__l4_abe, - &omap54xx_mpu__l4_abe, &omap54xx_l3_main_1__l4_cfg, &omap54xx_l3_main_2__l4_per, &omap54xx_l3_main_1__l4_wkup, diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c index adb07848de96..05e163c8337a 100644 --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c @@ -2,7 +2,7 @@ /* * Hardware modules present on the DRA7xx chips * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com * * Paul Walmsley * Benoit Cousson @@ -419,41 +419,6 @@ static struct omap_hwmod dra7xx_qspi_hwmod = { }; /* - * 'rtcss' class - * - */ -static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc = { - .rev_offs = 0x0074, - .sysc_offs = 0x0078, - .sysc_flags = SYSC_HAS_SIDLEMODE, - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | - SIDLE_SMART_WKUP), - .sysc_fields = &omap_hwmod_sysc_type3, -}; - -static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = { - .name = "rtcss", - .sysc = &dra7xx_rtcss_sysc, - .unlock = &omap_hwmod_rtc_unlock, - .lock = &omap_hwmod_rtc_lock, -}; - -/* rtcss */ -static struct omap_hwmod dra7xx_rtcss_hwmod = { - .name = "rtcss", - .class = &dra7xx_rtcss_hwmod_class, - .clkdm_name = "rtc_clkdm", - .main_clk = "sys_32k_ck", - .prcm = { - .omap4 = { - .clkctrl_offs = DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET, - .context_offs = DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - -/* * 'sata' class * */ @@ -702,14 +667,6 @@ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; -/* l4_per3 -> rtcss */ -static struct omap_hwmod_ocp_if dra7xx_l4_per3__rtcss = { - .master = &dra7xx_l4_per3_hwmod, - .slave = &dra7xx_rtcss_hwmod, - .clk = "l4_root_clk_div", - .user = OCP_USER_MPU | OCP_USER_SDMA, -}; - /* l4_cfg -> sata */ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = { .master = &dra7xx_l4_cfg_hwmod, @@ -786,7 +743,6 @@ static struct omap_hwmod_ocp_if *dra72x_hwmod_ocp_ifs[] __initdata = { }; static struct omap_hwmod_ocp_if *rtc_hwmod_ocp_ifs[] __initdata = { - &dra7xx_l4_per3__rtcss, NULL, }; diff --git a/arch/arm/mach-omap2/omap_hwmod_81xx_data.c b/arch/arm/mach-omap2/omap_hwmod_81xx_data.c index 50fb699b163f..450ab990c66a 100644 --- a/arch/arm/mach-omap2/omap_hwmod_81xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_81xx_data.c @@ -1,7 +1,7 @@ /* * DM81xx hwmod data. * - * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/ + * Copyright (C) 2010 Texas Instruments, Inc. - https://www.ti.com/ * Copyright (C) 2013 SKTB SKiT, http://www.skitlab.ru/ * * This program is free software; you can redistribute it and/or diff --git a/arch/arm/mach-omap2/omap_opp_data.h b/arch/arm/mach-omap2/omap_opp_data.h index 336fdfcf88bb..533dd643069a 100644 --- a/arch/arm/mach-omap2/omap_opp_data.h +++ b/arch/arm/mach-omap2/omap_opp_data.h @@ -1,7 +1,7 @@ /* * OMAP SoC specific OPP Data helpers * - * Copyright (C) 2009-2010 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2009-2010 Texas Instruments Incorporated - https://www.ti.com/ * Nishanth Menon * Kevin Hilman * Copyright (C) 2010 Nokia Corporation. diff --git a/arch/arm/mach-omap2/omap_phy_internal.c b/arch/arm/mach-omap2/omap_phy_internal.c index d2925e8b2eff..6f6a6a66c981 100644 --- a/arch/arm/mach-omap2/omap_phy_internal.c +++ b/arch/arm/mach-omap2/omap_phy_internal.c @@ -3,7 +3,7 @@ * This file configures the internal USB PHY in OMAP4430. Used * with TWL6030 transceiver and MUSB on OMAP4430. * - * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com + * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com * Author: Hema HK <hemahk@ti.com> */ diff --git a/arch/arm/mach-omap2/opp3xxx_data.c b/arch/arm/mach-omap2/opp3xxx_data.c index c2d459f5b0da..b610c5fb423b 100644 --- a/arch/arm/mach-omap2/opp3xxx_data.c +++ b/arch/arm/mach-omap2/opp3xxx_data.c @@ -1,7 +1,7 @@ /* * OMAP3 OPP table definitions. * - * Copyright (C) 2009-2010 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2009-2010 Texas Instruments Incorporated - https://www.ti.com/ * Nishanth Menon * Kevin Hilman * Copyright (C) 2010-2011 Nokia Corporation. diff --git a/arch/arm/mach-omap2/opp4xxx_data.c b/arch/arm/mach-omap2/opp4xxx_data.c index 985aeab9bc2a..d937c5ef41c6 100644 --- a/arch/arm/mach-omap2/opp4xxx_data.c +++ b/arch/arm/mach-omap2/opp4xxx_data.c @@ -1,7 +1,7 @@ /* * OMAP4 OPP table definitions. * - * Copyright (C) 2010-2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2010-2012 Texas Instruments Incorporated - https://www.ti.com/ * Nishanth Menon * Kevin Hilman * Thara Gopinath diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c index fceb1e525d26..919d35d5b325 100644 --- a/arch/arm/mach-omap2/pm-debug.c +++ b/arch/arm/mach-omap2/pm-debug.c @@ -34,8 +34,6 @@ #include "prm2xxx_3xxx.h" #include "pm.h" -u32 enable_off_mode; - #ifdef CONFIG_DEBUG_FS #include <linux/debugfs.h> #include <linux/seq_file.h> diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c index 01ec1ba4878b..da829a90fe8c 100644 --- a/arch/arm/mach-omap2/pm.c +++ b/arch/arm/mach-omap2/pm.c @@ -28,6 +28,8 @@ #include "clockdomain.h" #include "pm.h" +u32 enable_off_mode; + #ifdef CONFIG_SUSPEND /* * omap_pm_suspend: points to a function that does the SoC-specific diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h index 2a883a0c1fcd..80e84ae66aee 100644 --- a/arch/arm/mach-omap2/pm.h +++ b/arch/arm/mach-omap2/pm.h @@ -49,11 +49,7 @@ static inline int omap4_opp_init(void) extern int omap3_pm_get_suspend_state(struct powerdomain *pwrdm); extern int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state); -#ifdef CONFIG_PM_DEBUG extern u32 enable_off_mode; -#else -#define enable_off_mode 0 -#endif #if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) extern void pm_dbg_update_time(struct powerdomain *pwrdm, int prev); diff --git a/arch/arm/mach-omap2/pm33xx-core.c b/arch/arm/mach-omap2/pm33xx-core.c index 58236c7dc83e..56f2c0bcae5a 100644 --- a/arch/arm/mach-omap2/pm33xx-core.c +++ b/arch/arm/mach-omap2/pm33xx-core.c @@ -2,7 +2,7 @@ /* * AM33XX Arch Power Management Routines * - * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/ * Dave Gerlach */ @@ -25,7 +25,6 @@ #include "control.h" #include "clockdomain.h" #include "iomap.h" -#include "omap_hwmod.h" #include "pm.h" #include "powerdomain.h" #include "prm33xx.h" @@ -36,7 +35,6 @@ static struct powerdomain *cefuse_pwrdm, *gfx_pwrdm, *per_pwrdm, *mpu_pwrdm; static struct clockdomain *gfx_l4ls_clkdm; static void __iomem *scu_base; -static struct omap_hwmod *rtc_oh; static int (*idle_fn)(u32 wfi_flags); @@ -267,13 +265,6 @@ static struct am33xx_pm_sram_addr *amx3_get_sram_addrs(void) return NULL; } -static void __iomem *am43xx_get_rtc_base_addr(void) -{ - rtc_oh = omap_hwmod_lookup("rtc"); - - return omap_hwmod_get_mpu_rt_va(rtc_oh); -} - static void am43xx_save_context(void) { } @@ -297,16 +288,6 @@ static void am43xx_restore_context(void) writel_relaxed(0x0, AM33XX_L4_WK_IO_ADDRESS(0x44df2e14)); } -static void am43xx_prepare_rtc_suspend(void) -{ - omap_hwmod_enable(rtc_oh); -} - -static void am43xx_prepare_rtc_resume(void) -{ - omap_hwmod_idle(rtc_oh); -} - static struct am33xx_pm_platform_data am33xx_ops = { .init = am33xx_suspend_init, .deinit = amx3_suspend_deinit, @@ -317,10 +298,7 @@ static struct am33xx_pm_platform_data am33xx_ops = { .get_sram_addrs = amx3_get_sram_addrs, .save_context = am33xx_save_context, .restore_context = am33xx_restore_context, - .prepare_rtc_suspend = am43xx_prepare_rtc_suspend, - .prepare_rtc_resume = am43xx_prepare_rtc_resume, .check_off_mode_enable = am33xx_check_off_mode_enable, - .get_rtc_base_addr = am43xx_get_rtc_base_addr, }; static struct am33xx_pm_platform_data am43xx_ops = { @@ -333,10 +311,7 @@ static struct am33xx_pm_platform_data am43xx_ops = { .get_sram_addrs = amx3_get_sram_addrs, .save_context = am43xx_save_context, .restore_context = am43xx_restore_context, - .prepare_rtc_suspend = am43xx_prepare_rtc_suspend, - .prepare_rtc_resume = am43xx_prepare_rtc_resume, .check_off_mode_enable = am43xx_check_off_mode_enable, - .get_rtc_base_addr = am43xx_get_rtc_base_addr, }; static struct am33xx_pm_platform_data *am33xx_pm_get_pdata(void) diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index f5dfddf492e2..71c1d18aafbc 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -25,6 +25,7 @@ #include <linux/clk.h> #include <linux/delay.h> #include <linux/slab.h> +#include <linux/of.h> #include <linux/omap-gpmc.h> #include <trace/events/power.h> @@ -410,7 +411,12 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) if (!pwrst) return -ENOMEM; pwrst->pwrdm = pwrdm; - pwrst->next_state = PWRDM_POWER_RET; + + if (enable_off_mode) + pwrst->next_state = PWRDM_POWER_OFF; + else + pwrst->next_state = PWRDM_POWER_RET; + list_add(&pwrst->node, &pwrst_list); if (pwrdm_has_hdwr_sar(pwrdm)) @@ -444,6 +450,22 @@ static void __init pm_errata_configure(void) } } +static void __init omap3_pm_check_pmic(void) +{ + struct device_node *np; + + np = of_find_compatible_node(NULL, NULL, "ti,twl4030-power-idle"); + if (!np) + np = of_find_compatible_node(NULL, NULL, "ti,twl4030-power-idle-osc-off"); + + if (np) { + of_node_put(np); + enable_off_mode = 1; + } else { + enable_off_mode = 0; + } +} + int __init omap3_pm_init(void) { struct power_state *pwrst, *tmp; @@ -477,6 +499,8 @@ int __init omap3_pm_init(void) goto err2; } + omap3_pm_check_pmic(); + ret = pwrdm_for_each(pwrdms_setup, NULL); if (ret) { pr_err("Failed to setup powerdomains\n"); diff --git a/arch/arm/mach-omap2/powerdomains33xx_data.c b/arch/arm/mach-omap2/powerdomains33xx_data.c index 869adb82569e..626055e59aed 100644 --- a/arch/arm/mach-omap2/powerdomains33xx_data.c +++ b/arch/arm/mach-omap2/powerdomains33xx_data.c @@ -1,7 +1,7 @@ /* * AM33XX Power domain data * - * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/ * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/arch/arm/mach-omap2/prcm43xx.h b/arch/arm/mach-omap2/prcm43xx.h index 7078a61c1d3f..899da0ae9800 100644 --- a/arch/arm/mach-omap2/prcm43xx.h +++ b/arch/arm/mach-omap2/prcm43xx.h @@ -1,7 +1,7 @@ /* * AM43x PRCM defines * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ * * This file is licensed under the terms of the GNU General Public License * version 2. This program is licensed "as is" without any warranty of any diff --git a/arch/arm/mach-omap2/prcm_mpu54xx.h b/arch/arm/mach-omap2/prcm_mpu54xx.h index 6ef38829c064..bdbfa070b08e 100644 --- a/arch/arm/mach-omap2/prcm_mpu54xx.h +++ b/arch/arm/mach-omap2/prcm_mpu54xx.h @@ -2,7 +2,7 @@ /* * OMAP54xx PRCM MPU instance offset macros * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com * * Paul Walmsley (paul@pwsan.com) * Rajendra Nayak (rnayak@ti.com) diff --git a/arch/arm/mach-omap2/prcm_mpu7xx.h b/arch/arm/mach-omap2/prcm_mpu7xx.h index 33d0013aa1d4..2e3032440ea0 100644 --- a/arch/arm/mach-omap2/prcm_mpu7xx.h +++ b/arch/arm/mach-omap2/prcm_mpu7xx.h @@ -2,7 +2,7 @@ /* * DRA7xx PRCM MPU instance offset macros * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com * * Generated by code originally written by: * Paul Walmsley (paul@pwsan.com) diff --git a/arch/arm/mach-omap2/prm-regbits-33xx.h b/arch/arm/mach-omap2/prm-regbits-33xx.h index 84feecee4fe6..7dfdff09ddeb 100644 --- a/arch/arm/mach-omap2/prm-regbits-33xx.h +++ b/arch/arm/mach-omap2/prm-regbits-33xx.h @@ -1,7 +1,7 @@ /* * AM33XX PRM_XXX register bits * - * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/ * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/arch/arm/mach-omap2/prm33xx.c b/arch/arm/mach-omap2/prm33xx.c index d5141669c28d..9144cc0479af 100644 --- a/arch/arm/mach-omap2/prm33xx.c +++ b/arch/arm/mach-omap2/prm33xx.c @@ -1,7 +1,7 @@ /* * AM33XX PRM functions * - * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/ * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/arch/arm/mach-omap2/prm33xx.h b/arch/arm/mach-omap2/prm33xx.h index 66302c6aba61..d0b7404565f1 100644 --- a/arch/arm/mach-omap2/prm33xx.h +++ b/arch/arm/mach-omap2/prm33xx.h @@ -1,7 +1,7 @@ /* * AM33XX PRM instance offset macros * - * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/ * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/arch/arm/mach-omap2/prm54xx.h b/arch/arm/mach-omap2/prm54xx.h index ee0f1cc92e3a..7329d6fcd78b 100644 --- a/arch/arm/mach-omap2/prm54xx.h +++ b/arch/arm/mach-omap2/prm54xx.h @@ -2,7 +2,7 @@ /* * OMAP54xx PRM instance offset macros * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com * * Paul Walmsley (paul@pwsan.com) * Rajendra Nayak (rnayak@ti.com) diff --git a/arch/arm/mach-omap2/prm7xx.h b/arch/arm/mach-omap2/prm7xx.h index cf99307d1b1f..e5aee0409eae 100644 --- a/arch/arm/mach-omap2/prm7xx.h +++ b/arch/arm/mach-omap2/prm7xx.h @@ -2,7 +2,7 @@ /* * DRA7xx PRM instance offset macros * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com * * Generated by code originally written by: * Paul Walmsley (paul@pwsan.com) diff --git a/arch/arm/mach-omap2/scrm54xx.h b/arch/arm/mach-omap2/scrm54xx.h index 810d2b186337..cb6f3e6a7095 100644 --- a/arch/arm/mach-omap2/scrm54xx.h +++ b/arch/arm/mach-omap2/scrm54xx.h @@ -2,7 +2,7 @@ /* * OMAP54XX SCRM registers and bitfields * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com * * Benoit Cousson (b-cousson@ti.com) * diff --git a/arch/arm/mach-omap2/sleep33xx.S b/arch/arm/mach-omap2/sleep33xx.S index dc221249bc22..ac3d0b363c51 100644 --- a/arch/arm/mach-omap2/sleep33xx.S +++ b/arch/arm/mach-omap2/sleep33xx.S @@ -2,7 +2,7 @@ /* * Low level suspend code for AM33XX SoCs * - * Copyright (C) 2012-2018 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2012-2018 Texas Instruments Incorporated - https://www.ti.com/ * Dave Gerlach, Vaibhav Bedia */ diff --git a/arch/arm/mach-omap2/sleep43xx.S b/arch/arm/mach-omap2/sleep43xx.S index 90d2907a2eb2..832c91327945 100644 --- a/arch/arm/mach-omap2/sleep43xx.S +++ b/arch/arm/mach-omap2/sleep43xx.S @@ -2,7 +2,7 @@ /* * Low level suspend code for AM43XX SoCs * - * Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2013-2018 Texas Instruments Incorporated - https://www.ti.com/ * Dave Gerlach, Vaibhav Bedia */ diff --git a/arch/arm/mach-omap2/ti81xx.h b/arch/arm/mach-omap2/ti81xx.h index a1e6caf0dba6..192b0e7d3eb4 100644 --- a/arch/arm/mach-omap2/ti81xx.h +++ b/arch/arm/mach-omap2/ti81xx.h @@ -1,7 +1,7 @@ /* * This file contains the address data for various TI81XX modules. * - * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/ + * Copyright (C) 2010 Texas Instruments, Inc. - https://www.ti.com/ * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/arch/arm/mach-omap2/voltagedomains54xx_data.c b/arch/arm/mach-omap2/voltagedomains54xx_data.c index aac274d6a93b..e60d76db0f21 100644 --- a/arch/arm/mach-omap2/voltagedomains54xx_data.c +++ b/arch/arm/mach-omap2/voltagedomains54xx_data.c @@ -4,7 +4,7 @@ * * Based on voltagedomains44xx_data.c * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com + * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com */ #include <linux/kernel.h> #include <linux/err.h> diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c index 3d2c108e911e..431709725d02 100644 --- a/arch/arm/mach-pxa/tosa.c +++ b/arch/arm/mach-pxa/tosa.c @@ -369,6 +369,15 @@ static struct pxaficp_platform_data tosa_ficp_platform_data = { /* * Tosa AC IN */ +static struct gpiod_lookup_table tosa_power_gpiod_table = { + .dev_id = "gpio-charger", + .table = { + GPIO_LOOKUP("gpio-pxa", TOSA_GPIO_AC_IN, + NULL, GPIO_ACTIVE_LOW), + { }, + }, +}; + static char *tosa_ac_supplied_to[] = { "main-battery", "backup-battery", @@ -378,8 +387,6 @@ static char *tosa_ac_supplied_to[] = { static struct gpio_charger_platform_data tosa_power_data = { .name = "charger", .type = POWER_SUPPLY_TYPE_MAINS, - .gpio = TOSA_GPIO_AC_IN, - .gpio_active_low = 1, .supplied_to = tosa_ac_supplied_to, .num_supplicants = ARRAY_SIZE(tosa_ac_supplied_to), }; @@ -951,6 +958,7 @@ static void __init tosa_init(void) clk_add_alias("CLK_CK3P6MI", tc6393xb_device.name, "GPIO11_CLK", NULL); gpiod_add_lookup_table(&tosa_udc_gpiod_table); + gpiod_add_lookup_table(&tosa_power_gpiod_table); platform_add_devices(devices, ARRAY_SIZE(devices)); } diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/mach-s3c/Kconfig index 301e572651c0..25606e668cf9 100644 --- a/arch/arm/plat-samsung/Kconfig +++ b/arch/arm/mach-s3c/Kconfig @@ -2,12 +2,16 @@ # # Copyright 2009 Simtec Electronics +source "arch/arm/mach-s3c/Kconfig.s3c24xx" +source "arch/arm/mach-s3c/Kconfig.s3c64xx" + config PLAT_SAMSUNG bool - depends on PLAT_S3C24XX || ARCH_S3C64XX || ARCH_EXYNOS || ARCH_S5PV210 + depends on PLAT_S3C24XX || ARCH_S3C64XX default y select GENERIC_IRQ_CHIP select NO_IOPORT_MAP + select SOC_SAMSUNG help Base platform code for all Samsung SoC based systems @@ -154,7 +158,7 @@ config S3C_DEV_WDT bool default y if ARCH_S3C24XX help - Complie in platform device definition for Watchdog Timer + Compile in platform device definition for Watchdog Timer config S3C_DEV_NAND bool @@ -169,7 +173,7 @@ config S3C_DEV_ONENAND config S3C_DEV_RTC bool help - Complie in platform device definition for RTC + Compile in platform device definition for RTC config SAMSUNG_DEV_ADC bool @@ -234,54 +238,6 @@ config SAMSUNG_PM_GPIO pinctrl-samsung driver. endif -comment "Power management" - -config SAMSUNG_PM_DEBUG - bool "Samsung PM Suspend debug" - depends on PM && DEBUG_KERNEL - depends on PLAT_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210 - depends on DEBUG_EXYNOS_UART || DEBUG_S3C24XX_UART || DEBUG_S3C2410_UART - help - Say Y here if you want verbose debugging from the PM Suspend and - Resume code. See <file:Documentation/arm/samsung-s3c24xx/suspend.rst> - for more information. - -config S3C_PM_DEBUG_LED_SMDK - bool "SMDK LED suspend/resume debugging" - depends on PM && (MACH_SMDK6410) - help - Say Y here to enable the use of the SMDK LEDs on the baseboard - for debugging of the state of the suspend and resume process. - - Note, this currently only works for S3C64XX based SMDK boards. - -config SAMSUNG_PM_CHECK - bool "S3C2410 PM Suspend Memory CRC" - depends on PM && (PLAT_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210) - select CRC32 - help - Enable the PM code's memory area checksum over sleep. This option - will generate CRCs of all blocks of memory, and store them before - going to sleep. The blocks are then checked on resume for any - errors. - - Note, this can take several seconds depending on memory size - and CPU speed. - - See <file:Documentation/arm/samsung-s3c24xx/suspend.rst> - -config SAMSUNG_PM_CHECK_CHUNKSIZE - int "S3C2410 PM Suspend CRC Chunksize (KiB)" - depends on PM && SAMSUNG_PM_CHECK - default 64 - help - Set the chunksize in Kilobytes of the CRC for checking memory - corruption over suspend and resume. A smaller value will mean that - the CRC data block will take more memory, but will identify any - faults with better precision. - - See <file:Documentation/arm/samsung-s3c24xx/suspend.rst> - config SAMSUNG_WAKEMASK bool depends on PM @@ -290,19 +246,5 @@ config SAMSUNG_WAKEMASK and above. This code allows a set of interrupt to wakeup-mask mappings. See <plat/wakeup-mask.h> -config SAMSUNG_WDT_RESET - bool - help - Compile support for system restart by triggering watchdog reset. - Used on SoCs that do not provide dedicated reset control. - -config DEBUG_S3C_UART - depends on PLAT_SAMSUNG - int - default "0" if DEBUG_S3C_UART0 - default "1" if DEBUG_S3C_UART1 - default "2" if DEBUG_S3C_UART2 - default "3" if DEBUG_S3C_UART3 - endmenu endif diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c/Kconfig.s3c24xx index 7673dde9671a..000e3e234f71 100644 --- a/arch/arm/mach-s3c24xx/Kconfig +++ b/arch/arm/mach-s3c/Kconfig.s3c24xx @@ -123,11 +123,6 @@ config S3C24XX_PLL This also means that the PLL tables for the selected CPU(s) will be built which may increase the size of the kernel image. -config S3C_SETUP_CAMIF - bool - help - Compile in common setup code for S3C CAMIF devices - # cpu frequency items common between s3c2410 and s3c2440/s3c2442 config S3C2410_IOTIMING @@ -137,13 +132,6 @@ config S3C2410_IOTIMING Internal node to select io timing code that is common to the s3c2410 and s3c2440/s3c2442 cpu frequency support. -config S3C2410_CPUFREQ_UTILS - bool - depends on ARM_S3C24XX_CPUFREQ - help - Internal node to select timing code that is common to the s3c2410 - and s3c2440/s3c244 cpu frequency support. - # cpu frequency support common to s3c2412, s3c2413 and s3c2442 config S3C2412_IOTIMING @@ -468,7 +456,6 @@ config MACH_MINI2440 select NEW_LEDS select S3C_DEV_NAND select S3C_DEV_USB_HOST - select S3C_SETUP_CAMIF help Say Y here to select support for the MINI2440. Is a 10cm x 10cm board available via various sources. It can come with a 3.5" or 7" touch LCD. diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c/Kconfig.s3c64xx index ac3e3563487f..f3fcb570edf5 100644 --- a/arch/arm/mach-s3c64xx/Kconfig +++ b/arch/arm/mach-s3c/Kconfig.s3c64xx @@ -13,15 +13,15 @@ menuconfig ARCH_S3C64XX select GPIO_SAMSUNG if ATAGS select GPIOLIB select HAVE_S3C2410_I2C if I2C - select HAVE_S3C2410_WATCHDOG if WATCHDOG select HAVE_TCM select PLAT_SAMSUNG select PM_GENERIC_DOMAINS if PM select S3C_DEV_NAND if ATAGS select S3C_GPIO_TRACK if ATAGS + select S3C2410_WATCHDOG select SAMSUNG_ATAGS if ATAGS select SAMSUNG_WAKEMASK if PM - select SAMSUNG_WDT_RESET + select WATCHDOG help Samsung S3C64XX series based systems @@ -165,7 +165,6 @@ config MACH_SMDK6410 bool "SMDK6410" depends on ATAGS select CPU_S3C6410 - select HAVE_S3C2410_WATCHDOG if WATCHDOG select S3C64XX_SETUP_FB_24BPP select S3C64XX_SETUP_I2C1 select S3C64XX_SETUP_IDE diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/mach-s3c/Makefile index 3db9d2c38258..54188d10ab2e 100644 --- a/arch/arm/plat-samsung/Makefile +++ b/arch/arm/mach-s3c/Makefile @@ -2,9 +2,16 @@ # # Copyright 2009 Simtec Electronics -ccflags-$(CONFIG_ARCH_S3C64XX) := -I$(srctree)/arch/arm/mach-s3c64xx/include ccflags-$(CONFIG_ARCH_MULTIPLATFORM) += -I$(srctree)/$(src)/include +ifdef CONFIG_ARCH_S3C24XX +include $(src)/Makefile.s3c24xx +endif + +ifdef CONFIG_ARCH_S3C64XX +include $(src)/Makefile.s3c64xx +endif + # Objects we always build independent of SoC choice obj-y += init.o cpu.o @@ -24,12 +31,7 @@ obj-$(CONFIG_GPIO_SAMSUNG) += gpio-samsung.o # PM support -obj-$(CONFIG_PM_SLEEP) += pm-common.o -obj-$(CONFIG_EXYNOS_CPU_SUSPEND) += pm-common.o -obj-$(CONFIG_SAMSUNG_PM) += pm.o +obj-$(CONFIG_SAMSUNG_PM) += pm.o pm-common.o obj-$(CONFIG_SAMSUNG_PM_GPIO) += pm-gpio.o -obj-$(CONFIG_SAMSUNG_PM_CHECK) += pm-check.o -obj-$(CONFIG_SAMSUNG_PM_DEBUG) += pm-debug.o obj-$(CONFIG_SAMSUNG_WAKEMASK) += wakeup-mask.o -obj-$(CONFIG_SAMSUNG_WDT_RESET) += watchdog-reset.o diff --git a/arch/arm/mach-s3c24xx/Makefile.boot b/arch/arm/mach-s3c/Makefile.boot index 7f19e226035e..7f19e226035e 100644 --- a/arch/arm/mach-s3c24xx/Makefile.boot +++ b/arch/arm/mach-s3c/Makefile.boot diff --git a/arch/arm/mach-s3c24xx/Makefile b/arch/arm/mach-s3c/Makefile.s3c24xx index 6692f2de71b2..3483ab3a2b81 100644 --- a/arch/arm/mach-s3c24xx/Makefile +++ b/arch/arm/mach-s3c/Makefile.s3c24xx @@ -7,7 +7,10 @@ # core -obj-y += common.o +obj-y += s3c24xx.o +obj-y += irq-s3c24xx.o +obj-$(CONFIG_SPI_S3C24XX_FIQ) += irq-s3c24xx-fiq.o +obj-$(CONFIG_SPI_S3C24XX_FIQ) += irq-s3c24xx-fiq-exports.o obj-$(CONFIG_CPU_S3C2410) += s3c2410.o obj-$(CONFIG_S3C2410_PLL) += pll-s3c2410.o @@ -30,12 +33,12 @@ obj-$(CONFIG_CPU_S3C2443) += s3c2443.o # PM -obj-$(CONFIG_PM) += pm.o -obj-$(CONFIG_PM_SLEEP) += irq-pm.o sleep.o +obj-$(CONFIG_PM) += pm-s3c24xx.o +obj-$(CONFIG_PM_SLEEP) += irq-pm-s3c24xx.o sleep-s3c24xx.o # common code -obj-$(CONFIG_S3C2410_CPUFREQ_UTILS) += cpufreq-utils.o +obj-$(CONFIG_ARM_S3C24XX_CPUFREQ) += cpufreq-utils-s3c24xx.o obj-$(CONFIG_S3C2410_IOTIMING) += iotiming-s3c2410.o obj-$(CONFIG_S3C2412_IOTIMING) += iotiming-s3c2412.o @@ -80,7 +83,7 @@ obj-$(CONFIG_MACH_SMDK2443) += mach-smdk2443.o # common bits of machine support -obj-$(CONFIG_S3C24XX_SMDK) += common-smdk.o +obj-$(CONFIG_S3C24XX_SMDK) += common-smdk-s3c24xx.o obj-$(CONFIG_S3C24XX_SIMTEC_AUDIO) += simtec-audio.o obj-$(CONFIG_S3C24XX_SIMTEC_NOR) += simtec-nor.o obj-$(CONFIG_S3C24XX_SIMTEC_PM) += simtec-pm.o @@ -93,8 +96,7 @@ obj-$(CONFIG_MACH_OSIRIS_DVS) += mach-osiris-dvs.o # device setup -obj-$(CONFIG_S3C2416_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o -obj-$(CONFIG_S3C2443_SETUP_SPI) += setup-spi.o -obj-$(CONFIG_ARCH_S3C24XX) += setup-i2c.o -obj-$(CONFIG_S3C24XX_SETUP_TS) += setup-ts.o -obj-$(CONFIG_S3C_SETUP_CAMIF) += setup-camif.o +obj-$(CONFIG_S3C2416_SETUP_SDHCI_GPIO) += setup-sdhci-gpio-s3c24xx.o +obj-$(CONFIG_S3C2443_SETUP_SPI) += setup-spi-s3c24xx.o +obj-$(CONFIG_ARCH_S3C24XX) += setup-i2c-s3c24xx.o +obj-$(CONFIG_S3C24XX_SETUP_TS) += setup-ts-s3c24xx.o diff --git a/arch/arm/mach-s3c64xx/Makefile b/arch/arm/mach-s3c/Makefile.s3c64xx index 8caeb4ad17e9..0c18e31936df 100644 --- a/arch/arm/mach-s3c64xx/Makefile +++ b/arch/arm/mach-s3c/Makefile.s3c64xx @@ -3,22 +3,22 @@ # Copyright 2008 Openmoko, Inc. # Copyright 2008 Simtec Electronics -ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include -I$(srctree)/arch/arm/plat-samsung/include -asflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include -I$(srctree)/arch/arm/plat-samsung/include +ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include +asflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include # PM -obj-$(CONFIG_PM) += pm.o -obj-$(CONFIG_PM_SLEEP) += sleep.o -obj-$(CONFIG_CPU_IDLE) += cpuidle.o +obj-$(CONFIG_PM) += pm-s3c64xx.o +obj-$(CONFIG_PM_SLEEP) += sleep-s3c64xx.o +obj-$(CONFIG_CPU_IDLE) += cpuidle-s3c64xx.o ifdef CONFIG_SAMSUNG_ATAGS -obj-$(CONFIG_PM_SLEEP) += irq-pm.o +obj-$(CONFIG_PM_SLEEP) += irq-pm-s3c64xx.o # Core -obj-y += common.o +obj-y += s3c64xx.o obj-$(CONFIG_CPU_S3C6400) += s3c6400.o obj-$(CONFIG_CPU_S3C6410) += s3c6410.o @@ -28,21 +28,21 @@ obj-$(CONFIG_S3C64XX_PL080) += pl080.o # Device support -obj-y += dev-uart.o -obj-y += dev-audio.o +obj-y += dev-uart-s3c64xx.o +obj-y += dev-audio-s3c64xx.o # Device setup -obj-$(CONFIG_S3C64XX_SETUP_FB_24BPP) += setup-fb-24bpp.o -obj-$(CONFIG_S3C64XX_SETUP_I2C0) += setup-i2c0.o -obj-$(CONFIG_S3C64XX_SETUP_I2C1) += setup-i2c1.o -obj-$(CONFIG_S3C64XX_SETUP_IDE) += setup-ide.o -obj-$(CONFIG_S3C64XX_SETUP_KEYPAD) += setup-keypad.o -obj-$(CONFIG_S3C64XX_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o -obj-$(CONFIG_S3C64XX_SETUP_SPI) += setup-spi.o -obj-$(CONFIG_S3C64XX_SETUP_USB_PHY) += setup-usb-phy.o +obj-$(CONFIG_S3C64XX_SETUP_FB_24BPP) += setup-fb-24bpp-s3c64xx.o +obj-$(CONFIG_S3C64XX_SETUP_I2C0) += setup-i2c0-s3c64xx.o +obj-$(CONFIG_S3C64XX_SETUP_I2C1) += setup-i2c1-s3c64xx.o +obj-$(CONFIG_S3C64XX_SETUP_IDE) += setup-ide-s3c64xx.o +obj-$(CONFIG_S3C64XX_SETUP_KEYPAD) += setup-keypad-s3c64xx.o +obj-$(CONFIG_S3C64XX_SETUP_SDHCI_GPIO) += setup-sdhci-gpio-s3c64xx.o +obj-$(CONFIG_S3C64XX_SETUP_SPI) += setup-spi-s3c64xx.o +obj-$(CONFIG_S3C64XX_SETUP_USB_PHY) += setup-usb-phy-s3c64xx.o -obj-$(CONFIG_SAMSUNG_DEV_BACKLIGHT) += dev-backlight.o +obj-$(CONFIG_SAMSUNG_DEV_BACKLIGHT) += dev-backlight-s3c64xx.o # Machine support diff --git a/arch/arm/plat-samsung/include/plat/adc-core.h b/arch/arm/mach-s3c/adc-core.h index 039f6862b6a7..039f6862b6a7 100644 --- a/arch/arm/plat-samsung/include/plat/adc-core.h +++ b/arch/arm/mach-s3c/adc-core.h diff --git a/arch/arm/plat-samsung/adc.c b/arch/arm/mach-s3c/adc.c index 55b1925f65d7..0232520d3c13 100644 --- a/arch/arm/plat-samsung/adc.c +++ b/arch/arm/mach-s3c/adc.c @@ -19,8 +19,8 @@ #include <linux/io.h> #include <linux/regulator/consumer.h> -#include <plat/regs-adc.h> -#include <plat/adc.h> +#include "regs-adc.h" +#include <linux/soc/samsung/s3c-adc.h> /* This driver is designed to control the usage of the ADC block between * the touchscreen and any other drivers that may need to use it, such as diff --git a/arch/arm/mach-s3c24xx/anubis.h b/arch/arm/mach-s3c/anubis.h index 13847292e6c7..13847292e6c7 100644 --- a/arch/arm/mach-s3c24xx/anubis.h +++ b/arch/arm/mach-s3c/anubis.h diff --git a/arch/arm/mach-s3c64xx/ata-core.h b/arch/arm/mach-s3c/ata-core-s3c64xx.h index 6d9a81f759e6..4863ad9d3a42 100644 --- a/arch/arm/mach-s3c64xx/ata-core.h +++ b/arch/arm/mach-s3c/ata-core-s3c64xx.h @@ -6,8 +6,8 @@ * Samsung CF-ATA Controller core functions */ -#ifndef __ASM_PLAT_ATA_CORE_H -#define __ASM_PLAT_ATA_CORE_H __FILE__ +#ifndef __ASM_PLAT_ATA_CORE_S3C64XX_H +#define __ASM_PLAT_ATA_CORE_S3C64XX_H __FILE__ /* These functions are only for use with the core support code, such as * the cpu specific initialisation code @@ -21,4 +21,4 @@ static inline void s3c_cfcon_setname(char *name) #endif } -#endif /* __ASM_PLAT_ATA_CORE_H */ +#endif /* __ASM_PLAT_ATA_CORE_S3C64XX_H */ diff --git a/arch/arm/mach-s3c64xx/backlight.h b/arch/arm/mach-s3c/backlight-s3c64xx.h index 028663f1cacc..2a2b35821d58 100644 --- a/arch/arm/mach-s3c64xx/backlight.h +++ b/arch/arm/mach-s3c/backlight-s3c64xx.h @@ -4,8 +4,8 @@ * http://www.samsung.com */ -#ifndef __ASM_PLAT_BACKLIGHT_H -#define __ASM_PLAT_BACKLIGHT_H __FILE__ +#ifndef __ASM_PLAT_BACKLIGHT_S3C64XX_H +#define __ASM_PLAT_BACKLIGHT_S3C64XX_H __FILE__ /* samsung_bl_gpio_info - GPIO info for PWM Backlight control * @no: GPIO number for PWM timer out @@ -19,4 +19,4 @@ struct samsung_bl_gpio_info { extern void __init samsung_bl_set(struct samsung_bl_gpio_info *gpio_info, struct platform_pwm_backlight_data *bl_data); -#endif /* __ASM_PLAT_BACKLIGHT_H */ +#endif /* __ASM_PLAT_BACKLIGHT_S3C64XX_H */ diff --git a/arch/arm/mach-s3c24xx/bast-ide.c b/arch/arm/mach-s3c/bast-ide.c index 067944398f46..da64db1811d8 100644 --- a/arch/arm/mach-s3c24xx/bast-ide.c +++ b/arch/arm/mach-s3c/bast-ide.c @@ -19,7 +19,8 @@ #include <asm/mach/map.h> #include <asm/mach/irq.h> -#include <mach/map.h> +#include "map.h" +#include <mach/irqs.h> #include "bast.h" diff --git a/arch/arm/mach-s3c24xx/bast-irq.c b/arch/arm/mach-s3c/bast-irq.c index 03728058d58d..d299f124e6dc 100644 --- a/arch/arm/mach-s3c24xx/bast-irq.c +++ b/arch/arm/mach-s3c/bast-irq.c @@ -15,8 +15,8 @@ #include <asm/mach-types.h> #include <asm/mach/irq.h> -#include <mach/hardware.h> -#include <mach/regs-irq.h> +#include "regs-irq.h" +#include <mach/irqs.h> #include "bast.h" @@ -62,7 +62,7 @@ bast_pc104_mask(struct irq_data *data) static void bast_pc104_maskack(struct irq_data *data) { - struct irq_desc *desc = irq_desc + BAST_IRQ_ISA; + struct irq_desc *desc = irq_to_desc(BAST_IRQ_ISA); bast_pc104_mask(data); desc->irq_data.chip->irq_ack(&desc->irq_data); @@ -94,8 +94,6 @@ static void bast_irq_pc104_demux(struct irq_desc *desc) if (unlikely(stat == 0)) { /* ack if we get an irq with nothing (ie, startup) */ - - desc = irq_desc + BAST_IRQ_ISA; desc->irq_data.chip->irq_ack(&desc->irq_data); } else { /* handle the IRQ */ diff --git a/arch/arm/mach-s3c24xx/bast.h b/arch/arm/mach-s3c/bast.h index a7726f93f5eb..a7726f93f5eb 100644 --- a/arch/arm/mach-s3c24xx/bast.h +++ b/arch/arm/mach-s3c/bast.h diff --git a/arch/arm/mach-s3c24xx/common-smdk.c b/arch/arm/mach-s3c/common-smdk-s3c24xx.c index 75064dfaceb1..f860d8bcba0e 100644 --- a/arch/arm/mach-s3c24xx/common-smdk.c +++ b/arch/arm/mach-s3c/common-smdk-s3c24xx.c @@ -29,19 +29,18 @@ #include <asm/mach/irq.h> #include <asm/mach-types.h> -#include <mach/hardware.h> #include <asm/irq.h> -#include <mach/regs-gpio.h> -#include <mach/gpio-samsung.h> +#include "regs-gpio.h" +#include "gpio-samsung.h" #include <linux/platform_data/leds-s3c24xx.h> #include <linux/platform_data/mtd-nand-s3c2410.h> -#include <plat/gpio-cfg.h> -#include <plat/devs.h> -#include <plat/pm.h> +#include "gpio-cfg.h" +#include "devs.h" +#include "pm.h" -#include "common-smdk.h" +#include "common-smdk-s3c24xx.h" /* LED devices */ @@ -191,7 +190,7 @@ static struct s3c2410_platform_nand smdk_nand_info = { .twrph1 = 20, .nr_sets = ARRAY_SIZE(smdk_nand_sets), .sets = smdk_nand_sets, - .ecc_mode = NAND_ECC_SOFT, + .engine_type = NAND_ECC_ENGINE_TYPE_SOFT, }; /* devices we initialise */ diff --git a/arch/arm/mach-s3c24xx/common-smdk.h b/arch/arm/mach-s3c/common-smdk-s3c24xx.h index c0352b06e435..c0352b06e435 100644 --- a/arch/arm/mach-s3c24xx/common-smdk.h +++ b/arch/arm/mach-s3c/common-smdk-s3c24xx.h diff --git a/arch/arm/plat-samsung/cpu.c b/arch/arm/mach-s3c/cpu.c index e1ba88ba31d8..6e9772555f0d 100644 --- a/arch/arm/plat-samsung/cpu.c +++ b/arch/arm/mach-s3c/cpu.c @@ -10,17 +10,10 @@ #include <linux/init.h> #include <linux/io.h> -#include <plat/map-base.h> -#include <plat/cpu.h> +#include <mach/map-base.h> +#include "cpu.h" unsigned long samsung_cpu_id; -static unsigned int samsung_cpu_rev; - -unsigned int samsung_rev(void) -{ - return samsung_cpu_rev; -} -EXPORT_SYMBOL(samsung_rev); void __init s3c64xx_init_cpu(void) { @@ -34,15 +27,5 @@ void __init s3c64xx_init_cpu(void) samsung_cpu_id = readl_relaxed(S3C_VA_SYS + 0xA1C); } - samsung_cpu_rev = 0; - - pr_info("Samsung CPU ID: 0x%08lx\n", samsung_cpu_id); -} - -void __init s5p_init_cpu(const void __iomem *cpuid_addr) -{ - samsung_cpu_id = readl_relaxed(cpuid_addr); - samsung_cpu_rev = samsung_cpu_id & 0xFF; - pr_info("Samsung CPU ID: 0x%08lx\n", samsung_cpu_id); } diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/mach-s3c/cpu.h index fadcddbea064..20ff98d05c53 100644 --- a/arch/arm/plat-samsung/include/plat/cpu.h +++ b/arch/arm/mach-s3c/cpu.h @@ -109,9 +109,6 @@ extern void s3c_init_cpu(unsigned long idcode, extern void s3c24xx_init_io(struct map_desc *mach_desc, int size); extern void s3c64xx_init_cpu(void); -extern void s5p_init_cpu(const void __iomem *cpuid_addr); - -extern unsigned int samsung_rev(void); extern void s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no); @@ -126,15 +123,6 @@ extern struct syscore_ops s3c2412_pm_syscore_ops; extern struct syscore_ops s3c2416_pm_syscore_ops; extern struct syscore_ops s3c244x_pm_syscore_ops; -/* system device subsystems */ - -extern struct bus_type s3c2410_subsys; -extern struct bus_type s3c2410a_subsys; -extern struct bus_type s3c2412_subsys; -extern struct bus_type s3c2416_subsys; -extern struct bus_type s3c2440_subsys; -extern struct bus_type s3c2442_subsys; -extern struct bus_type s3c2443_subsys; extern struct bus_type s3c6410_subsys; #endif diff --git a/arch/arm/mach-s3c24xx/cpufreq-utils.c b/arch/arm/mach-s3c/cpufreq-utils-s3c24xx.c index 1a7f38d085dd..c1784d8facdf 100644 --- a/arch/arm/mach-s3c24xx/cpufreq-utils.c +++ b/arch/arm/mach-s3c/cpufreq-utils-s3c24xx.c @@ -12,12 +12,12 @@ #include <linux/io.h> #include <linux/clk.h> -#include <mach/map.h> -#include <mach/regs-clock.h> +#include "map.h" +#include "regs-clock.h" -#include <plat/cpu-freq-core.h> +#include <linux/soc/samsung/s3c-cpufreq-core.h> -#include "regs-mem.h" +#include "regs-mem-s3c24xx.h" /** * s3c2410_cpufreq_setrefresh - set SDRAM refresh value @@ -60,3 +60,35 @@ void s3c2410_set_fvco(struct s3c_cpufreq_config *cfg) if (!IS_ERR(cfg->mpll)) clk_set_rate(cfg->mpll, cfg->pll.frequency); } + +#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442) +u32 s3c2440_read_camdivn(void) +{ + return __raw_readl(S3C2440_CAMDIVN); +} + +void s3c2440_write_camdivn(u32 camdiv) +{ + __raw_writel(camdiv, S3C2440_CAMDIVN); +} +#endif + +u32 s3c24xx_read_clkdivn(void) +{ + return __raw_readl(S3C2410_CLKDIVN); +} + +void s3c24xx_write_clkdivn(u32 clkdiv) +{ + __raw_writel(clkdiv, S3C2410_CLKDIVN); +} + +u32 s3c24xx_read_mpllcon(void) +{ + return __raw_readl(S3C2410_MPLLCON); +} + +void s3c24xx_write_locktime(u32 locktime) +{ + return __raw_writel(locktime, S3C2410_LOCKTIME); +} diff --git a/arch/arm/mach-s3c64xx/cpuidle.c b/arch/arm/mach-s3c/cpuidle-s3c64xx.c index 0bac6f6413b0..b1c5f43d4922 100644 --- a/arch/arm/mach-s3c64xx/cpuidle.c +++ b/arch/arm/mach-s3c/cpuidle-s3c64xx.c @@ -13,11 +13,11 @@ #include <asm/cpuidle.h> -#include <plat/cpu.h> -#include <mach/map.h> +#include "cpu.h" +#include "map.h" -#include "regs-sys.h" -#include "regs-syscon-power.h" +#include "regs-sys-s3c64xx.h" +#include "regs-syscon-power-s3c64xx.h" static int s3c64xx_enter_idle(struct cpuidle_device *dev, struct cpuidle_driver *drv, diff --git a/arch/arm/mach-s3c64xx/crag6410.h b/arch/arm/mach-s3c/crag6410.h index 00d9aa114aa7..f39ea2ca7a75 100644 --- a/arch/arm/mach-s3c64xx/crag6410.h +++ b/arch/arm/mach-s3c/crag6410.h @@ -8,7 +8,7 @@ #ifndef MACH_CRAG6410_H #define MACH_CRAG6410_H -#include <mach/gpio-samsung.h> +#include "gpio-samsung.h" #define GLENFARCLAS_PMIC_IRQ_BASE IRQ_BOARD_START #define BANFF_PMIC_IRQ_BASE (IRQ_BOARD_START + 64) diff --git a/arch/arm/mach-s3c64xx/dev-audio.c b/arch/arm/mach-s3c/dev-audio-s3c64xx.c index e3c49b5d1355..fc2f077afd24 100644 --- a/arch/arm/mach-s3c64xx/dev-audio.c +++ b/arch/arm/mach-s3c/dev-audio-s3c64xx.c @@ -11,13 +11,12 @@ #include <linux/export.h> #include <mach/irqs.h> -#include <mach/map.h> -#include <mach/dma.h> +#include "map.h" -#include <plat/devs.h> +#include "devs.h" #include <linux/platform_data/asoc-s3c.h> -#include <plat/gpio-cfg.h> -#include <mach/gpio-samsung.h> +#include "gpio-cfg.h" +#include "gpio-samsung.h" static int s3c64xx_i2s_cfg_gpio(struct platform_device *pdev) { diff --git a/arch/arm/mach-s3c64xx/dev-backlight.c b/arch/arm/mach-s3c/dev-backlight-s3c64xx.c index 09e6da305f60..65488b61e50c 100644 --- a/arch/arm/mach-s3c64xx/dev-backlight.c +++ b/arch/arm/mach-s3c/dev-backlight-s3c64xx.c @@ -11,10 +11,10 @@ #include <linux/io.h> #include <linux/pwm_backlight.h> -#include <plat/devs.h> -#include <plat/gpio-cfg.h> +#include "devs.h" +#include "gpio-cfg.h" -#include "backlight.h" +#include "backlight-s3c64xx.h" struct samsung_bl_drvdata { struct platform_pwm_backlight_data plat_data; diff --git a/arch/arm/mach-s3c64xx/dev-uart.c b/arch/arm/mach-s3c/dev-uart-s3c64xx.c index 5fb59ad30008..8288e8d6c092 100644 --- a/arch/arm/mach-s3c64xx/dev-uart.c +++ b/arch/arm/mach-s3c/dev-uart-s3c64xx.c @@ -15,11 +15,10 @@ #include <asm/mach/arch.h> #include <asm/mach/irq.h> -#include <mach/hardware.h> -#include <mach/map.h> +#include "map.h" #include <mach/irqs.h> -#include <plat/devs.h> +#include "devs.h" /* Serial port registrations */ diff --git a/arch/arm/plat-samsung/dev-uart.c b/arch/arm/mach-s3c/dev-uart.c index 7476a5dbae77..3d1f7f2fd7c7 100644 --- a/arch/arm/plat-samsung/dev-uart.c +++ b/arch/arm/mach-s3c/dev-uart.c @@ -10,7 +10,7 @@ #include <linux/kernel.h> #include <linux/platform_device.h> -#include <plat/devs.h> +#include "devs.h" /* uart devices */ diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/mach-s3c/devs.c index 089a17687104..06dec64848f9 100644 --- a/arch/arm/plat-samsung/devs.c +++ b/arch/arm/mach-s3c/devs.c @@ -5,6 +5,7 @@ // // Base Samsung platform device definitions +#include <linux/gpio.h> #include <linux/kernel.h> #include <linux/types.h> #include <linux/interrupt.h> @@ -37,28 +38,32 @@ #include <asm/mach/map.h> #include <asm/mach/irq.h> -#include <mach/dma.h> #include <mach/irqs.h> -#include <mach/map.h> +#include "map.h" +#include "gpio-samsung.h" +#include "gpio-cfg.h" -#include <plat/cpu.h> -#include <plat/devs.h> -#include <plat/adc.h> +#ifdef CONFIG_PLAT_S3C24XX +#include "regs-s3c2443-clock.h" +#endif /* CONFIG_PLAT_S3C24XX */ + +#include "cpu.h" +#include "devs.h" +#include <linux/soc/samsung/s3c-adc.h> #include <linux/platform_data/ata-samsung_cf.h> -#include <plat/fb.h> -#include <plat/fb-s3c2410.h> +#include "fb.h" +#include <linux/platform_data/fb-s3c2410.h> #include <linux/platform_data/hwmon-s3c.h> #include <linux/platform_data/i2c-s3c2410.h> -#include <plat/keypad.h> +#include "keypad.h" #include <linux/platform_data/mmc-s3cmci.h> #include <linux/platform_data/mtd-nand-s3c2410.h> -#include <plat/pwm-core.h> -#include <plat/sdhci.h> +#include "pwm-core.h" +#include "sdhci.h" #include <linux/platform_data/touchscreen-s3c2410.h> #include <linux/platform_data/usb-s3c2410_udc.h> #include <linux/platform_data/usb-ohci-s3c2410.h> -#include <plat/usb-phy.h> -#include <plat/regs-spi.h> +#include "usb-phy.h" #include <linux/platform_data/asoc-s3c.h> #include <linux/platform_data/spi-s3c64xx.h> @@ -833,16 +838,42 @@ struct platform_device s3c_device_rtc = { /* SDI */ #ifdef CONFIG_PLAT_S3C24XX +void s3c24xx_mci_def_set_power(unsigned char power_mode, unsigned short vdd) +{ + switch (power_mode) { + case MMC_POWER_ON: + case MMC_POWER_UP: + /* Configure GPE5...GPE10 pins in SD mode */ + s3c_gpio_cfgall_range(S3C2410_GPE(5), 6, S3C_GPIO_SFN(2), + S3C_GPIO_PULL_NONE); + break; + + case MMC_POWER_OFF: + default: + gpio_direction_output(S3C2410_GPE(5), 0); + break; + } +} + static struct resource s3c_sdi_resource[] = { [0] = DEFINE_RES_MEM(S3C24XX_PA_SDI, S3C24XX_SZ_SDI), [1] = DEFINE_RES_IRQ(IRQ_SDI), }; +static struct s3c24xx_mci_pdata s3cmci_def_pdata = { + /* This is currently here to avoid a number of if (host->pdata) + * checks. Any zero fields to ensure reasonable defaults are picked. */ + .no_wprotect = 1, + .no_detect = 1, + .set_power = s3c24xx_mci_def_set_power, +}; + struct platform_device s3c_device_sdi = { .name = "s3c2410-sdi", .id = -1, .num_resources = ARRAY_SIZE(s3c_sdi_resource), .resource = s3c_sdi_resource, + .dev.platform_data = &s3cmci_def_pdata, }; void __init s3c24xx_mci_set_platdata(struct s3c24xx_mci_pdata *pdata) @@ -1038,6 +1069,8 @@ struct platform_device s3c_device_usb_hsudc = { void __init s3c24xx_hsudc_set_platdata(struct s3c24xx_hsudc_platdata *pd) { s3c_set_platdata(pd, sizeof(*pd), &s3c_device_usb_hsudc); + pd->phy_init = s3c_hsudc_init_phy; + pd->phy_uninit = s3c_hsudc_uninit_phy; } #endif /* CONFIG_PLAT_S3C24XX */ diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/mach-s3c/devs.h index 02b0c5750572..02b0c5750572 100644 --- a/arch/arm/plat-samsung/include/plat/devs.h +++ b/arch/arm/mach-s3c/devs.h diff --git a/arch/arm/mach-s3c24xx/include/mach/dma.h b/arch/arm/mach-s3c/dma-s3c24xx.h index 25fc9c258fc1..25fc9c258fc1 100644 --- a/arch/arm/mach-s3c24xx/include/mach/dma.h +++ b/arch/arm/mach-s3c/dma-s3c24xx.h diff --git a/arch/arm/mach-s3c64xx/include/mach/dma.h b/arch/arm/mach-s3c/dma-s3c64xx.h index 40ca8de21096..40ca8de21096 100644 --- a/arch/arm/mach-s3c64xx/include/mach/dma.h +++ b/arch/arm/mach-s3c/dma-s3c64xx.h diff --git a/arch/arm/mach-s3c/dma.h b/arch/arm/mach-s3c/dma.h new file mode 100644 index 000000000000..59a4578c5f00 --- /dev/null +++ b/arch/arm/mach-s3c/dma.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifdef CONFIG_ARCH_S3C24XX +#include "dma-s3c24xx.h" +#endif + +#ifdef CONFIG_ARCH_S3C64XX +#include "dma-s3c64xx.h" +#endif diff --git a/arch/arm/mach-s3c24xx/fb-core.h b/arch/arm/mach-s3c/fb-core-s3c24xx.h index 1821e820262c..0e07f3ba4aef 100644 --- a/arch/arm/mach-s3c24xx/fb-core.h +++ b/arch/arm/mach-s3c/fb-core-s3c24xx.h @@ -5,8 +5,8 @@ * * Samsung framebuffer driver core functions */ -#ifndef __ASM_PLAT_FB_CORE_H -#define __ASM_PLAT_FB_CORE_H __FILE__ +#ifndef __ASM_PLAT_FB_CORE_S3C24XX_H +#define __ASM_PLAT_FB_CORE_S3C24XX_H __FILE__ /* * These functions are only for use with the core support code, such as @@ -21,4 +21,4 @@ static inline void s3c_fb_setname(char *name) #endif } -#endif /* __ASM_PLAT_FB_CORE_H */ +#endif /* __ASM_PLAT_FB_CORE_S3C24XX_H */ diff --git a/arch/arm/plat-samsung/include/plat/fb.h b/arch/arm/mach-s3c/fb.h index 615d381ae32e..615d381ae32e 100644 --- a/arch/arm/plat-samsung/include/plat/fb.h +++ b/arch/arm/mach-s3c/fb.h diff --git a/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h b/arch/arm/mach-s3c/gpio-cfg-helpers.h index db0c56f5ca15..db0c56f5ca15 100644 --- a/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h +++ b/arch/arm/mach-s3c/gpio-cfg-helpers.h diff --git a/arch/arm/plat-samsung/include/plat/gpio-cfg.h b/arch/arm/mach-s3c/gpio-cfg.h index 469c220e092b..469c220e092b 100644 --- a/arch/arm/plat-samsung/include/plat/gpio-cfg.h +++ b/arch/arm/mach-s3c/gpio-cfg.h diff --git a/arch/arm/plat-samsung/include/plat/gpio-core.h b/arch/arm/mach-s3c/gpio-core.h index c0bfceb88340..b361c8c0d669 100644 --- a/arch/arm/plat-samsung/include/plat/gpio-core.h +++ b/arch/arm/mach-s3c/gpio-core.h @@ -11,7 +11,7 @@ #define __PLAT_SAMSUNG_GPIO_CORE_H /* Bring in machine-local definitions, especially S3C_GPIO_END */ -#include <mach/gpio-samsung.h> +#include "gpio-samsung.h" #include <linux/gpio/driver.h> #define GPIOCON_OFF (0x00) diff --git a/arch/arm/mach-s3c24xx/include/mach/gpio-samsung.h b/arch/arm/mach-s3c/gpio-samsung-s3c24xx.h index 2ad22b2d459b..c29fdc95f883 100644 --- a/arch/arm/mach-s3c24xx/include/mach/gpio-samsung.h +++ b/arch/arm/mach-s3c/gpio-samsung-s3c24xx.h @@ -14,6 +14,8 @@ #ifndef GPIO_SAMSUNG_S3C24XX_H #define GPIO_SAMSUNG_S3C24XX_H +#include "map.h" + /* * GPIO sizes for various SoCs: * diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio-samsung.h b/arch/arm/mach-s3c/gpio-samsung-s3c64xx.h index 8ed144a0d474..8ed144a0d474 100644 --- a/arch/arm/mach-s3c64xx/include/mach/gpio-samsung.h +++ b/arch/arm/mach-s3c/gpio-samsung-s3c64xx.h diff --git a/arch/arm/plat-samsung/gpio-samsung.c b/arch/arm/mach-s3c/gpio-samsung.c index 8955fd675265..76ef415789f2 100644 --- a/arch/arm/plat-samsung/gpio-samsung.c +++ b/arch/arm/mach-s3c/gpio-samsung.c @@ -27,15 +27,15 @@ #include <asm/irq.h> #include <mach/irqs.h> -#include <mach/map.h> -#include <mach/regs-gpio.h> -#include <mach/gpio-samsung.h> - -#include <plat/cpu.h> -#include <plat/gpio-core.h> -#include <plat/gpio-cfg.h> -#include <plat/gpio-cfg-helpers.h> -#include <plat/pm.h> +#include "map.h" +#include "regs-gpio.h" +#include "gpio-samsung.h" + +#include "cpu.h" +#include "gpio-core.h" +#include "gpio-cfg.h" +#include "gpio-cfg-helpers.h" +#include "pm.h" int samsung_gpio_setpull_updown(struct samsung_gpio_chip *chip, unsigned int off, samsung_gpio_pull_t pull) diff --git a/arch/arm/mach-s3c/gpio-samsung.h b/arch/arm/mach-s3c/gpio-samsung.h new file mode 100644 index 000000000000..02f6f4a96862 --- /dev/null +++ b/arch/arm/mach-s3c/gpio-samsung.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifdef CONFIG_ARCH_S3C24XX +#include "gpio-samsung-s3c24xx.h" +#endif + +#ifdef CONFIG_ARCH_S3C64XX +#include "gpio-samsung-s3c64xx.h" +#endif diff --git a/arch/arm/mach-s3c24xx/gta02.h b/arch/arm/mach-s3c/gta02.h index d5610ba829a4..043ae382bfc5 100644 --- a/arch/arm/mach-s3c24xx/gta02.h +++ b/arch/arm/mach-s3c/gta02.h @@ -6,7 +6,7 @@ #ifndef __MACH_S3C24XX_GTA02_H #define __MACH_S3C24XX_GTA02_H __FILE__ -#include <mach/regs-gpio.h> +#include "regs-gpio.h" #define GTA02_GPIO_AUX_LED S3C2410_GPB(2) #define GTA02_GPIO_USB_PULLUP S3C2410_GPB(9) diff --git a/arch/arm/mach-s3c24xx/h1940-bluetooth.c b/arch/arm/mach-s3c/h1940-bluetooth.c index 186b5321658e..59edcf8a620d 100644 --- a/arch/arm/mach-s3c24xx/h1940-bluetooth.c +++ b/arch/arm/mach-s3c/h1940-bluetooth.c @@ -13,10 +13,9 @@ #include <linux/gpio.h> #include <linux/rfkill.h> -#include <plat/gpio-cfg.h> -#include <mach/hardware.h> -#include <mach/regs-gpio.h> -#include <mach/gpio-samsung.h> +#include "gpio-cfg.h" +#include "regs-gpio.h" +#include "gpio-samsung.h" #include "h1940.h" diff --git a/arch/arm/mach-s3c24xx/h1940.h b/arch/arm/mach-s3c/h1940.h index 5dfe9d10cd15..5dfe9d10cd15 100644 --- a/arch/arm/mach-s3c24xx/h1940.h +++ b/arch/arm/mach-s3c/h1940.h diff --git a/arch/arm/mach-s3c24xx/include/mach/hardware.h b/arch/arm/mach-s3c/hardware-s3c24xx.h index f28ac6c78d82..33b37467d05f 100644 --- a/arch/arm/mach-s3c24xx/include/mach/hardware.h +++ b/arch/arm/mach-s3c/hardware-s3c24xx.h @@ -6,16 +6,9 @@ * S3C2410 - hardware */ -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -#ifndef __ASSEMBLY__ +#ifndef __ASM_ARCH_HARDWARE_S3C24XX_H +#define __ASM_ARCH_HARDWARE_S3C24XX_H extern unsigned int s3c2410_modify_misccr(unsigned int clr, unsigned int chg); -#endif /* __ASSEMBLY__ */ - -#include <linux/sizes.h> -#include <mach/map.h> - -#endif /* __ASM_ARCH_HARDWARE_H */ +#endif /* __ASM_ARCH_HARDWARE_S3C24XX_H */ diff --git a/arch/arm/plat-samsung/include/plat/iic-core.h b/arch/arm/mach-s3c/iic-core.h index c5cfd5af3874..c5cfd5af3874 100644 --- a/arch/arm/plat-samsung/include/plat/iic-core.h +++ b/arch/arm/mach-s3c/iic-core.h diff --git a/arch/arm/mach-s3c/include/mach/io-s3c24xx.h b/arch/arm/mach-s3c/include/mach/io-s3c24xx.h new file mode 100644 index 000000000000..738b775d3336 --- /dev/null +++ b/arch/arm/mach-s3c/include/mach/io-s3c24xx.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * arch/arm/mach-s3c2410/include/mach/io.h + * from arch/arm/mach-rpc/include/mach/io.h + * + * Copyright (C) 1997 Russell King + * (C) 2003 Simtec Electronics +*/ + +#ifndef __ASM_ARM_ARCH_IO_S3C24XX_H +#define __ASM_ARM_ARCH_IO_S3C24XX_H + +#include <mach/map-base.h> + +/* + * ISA style IO, for each machine to sort out mappings for, + * if it implements it. We reserve two 16M regions for ISA, + * so the PC/104 can use separate addresses for 8-bit and + * 16-bit port I/O. + */ +#define PCIO_BASE S3C_ADDR(0x02000000) +#define IO_SPACE_LIMIT 0x00ffffff +#define S3C24XX_VA_ISA_WORD (PCIO_BASE) +#define S3C24XX_VA_ISA_BYTE (PCIO_BASE + 0x01000000) + +#ifdef CONFIG_ISA + +#define inb(p) readb(S3C24XX_VA_ISA_BYTE + (p)) +#define inw(p) readw(S3C24XX_VA_ISA_WORD + (p)) +#define inl(p) readl(S3C24XX_VA_ISA_WORD + (p)) + +#define outb(v,p) writeb((v), S3C24XX_VA_ISA_BYTE + (p)) +#define outw(v,p) writew((v), S3C24XX_VA_ISA_WORD + (p)) +#define outl(v,p) writel((v), S3C24XX_VA_ISA_WORD + (p)) + +#define insb(p,d,l) readsb(S3C24XX_VA_ISA_BYTE + (p),d,l) +#define insw(p,d,l) readsw(S3C24XX_VA_ISA_WORD + (p),d,l) +#define insl(p,d,l) readsl(S3C24XX_VA_ISA_WORD + (p),d,l) + +#define outsb(p,d,l) writesb(S3C24XX_VA_ISA_BYTE + (p),d,l) +#define outsw(p,d,l) writesw(S3C24XX_VA_ISA_WORD + (p),d,l) +#define outsl(p,d,l) writesl(S3C24XX_VA_ISA_WORD + (p),d,l) + +#else + +#define __io(x) (PCIO_BASE + (x)) + +#endif + +#endif diff --git a/arch/arm/mach-s3c/include/mach/io.h b/arch/arm/mach-s3c/include/mach/io.h new file mode 100644 index 000000000000..30a0135708dc --- /dev/null +++ b/arch/arm/mach-s3c/include/mach/io.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2020 Krzysztof Kozlowski <krzk@kernel.org> + */ + +#ifdef CONFIG_ARCH_S3C24XX +#include "io-s3c24xx.h" +#endif diff --git a/arch/arm/mach-s3c24xx/include/mach/irqs.h b/arch/arm/mach-s3c/include/mach/irqs-s3c24xx.h index aaf3bae08b52..aaf3bae08b52 100644 --- a/arch/arm/mach-s3c24xx/include/mach/irqs.h +++ b/arch/arm/mach-s3c/include/mach/irqs-s3c24xx.h diff --git a/arch/arm/mach-s3c64xx/include/mach/irqs.h b/arch/arm/mach-s3c/include/mach/irqs-s3c64xx.h index c244e480e6b3..c244e480e6b3 100644 --- a/arch/arm/mach-s3c64xx/include/mach/irqs.h +++ b/arch/arm/mach-s3c/include/mach/irqs-s3c64xx.h diff --git a/arch/arm/mach-s3c/include/mach/irqs.h b/arch/arm/mach-s3c/include/mach/irqs.h new file mode 100644 index 000000000000..0bff1c1c8eb0 --- /dev/null +++ b/arch/arm/mach-s3c/include/mach/irqs.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifdef CONFIG_ARCH_S3C24XX +#include "irqs-s3c24xx.h" +#endif + +#ifdef CONFIG_ARCH_S3C64XX +#include "irqs-s3c64xx.h" +#endif diff --git a/arch/arm/plat-samsung/include/plat/map-base.h b/arch/arm/mach-s3c/include/mach/map-base.h index 34b39ded0e2e..34b39ded0e2e 100644 --- a/arch/arm/plat-samsung/include/plat/map-base.h +++ b/arch/arm/mach-s3c/include/mach/map-base.h diff --git a/arch/arm/plat-samsung/init.c b/arch/arm/mach-s3c/init.c index e9acf02ef3c3..9d92f03e9bc1 100644 --- a/arch/arm/plat-samsung/init.c +++ b/arch/arm/mach-s3c/init.c @@ -23,8 +23,8 @@ #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <plat/cpu.h> -#include <plat/devs.h> +#include "cpu.h" +#include "devs.h" static struct cpu_table *cpu; diff --git a/arch/arm/mach-s3c24xx/iotiming-s3c2410.c b/arch/arm/mach-s3c/iotiming-s3c2410.c index 9f90aaf70bf3..28d9f473e24a 100644 --- a/arch/arm/mach-s3c24xx/iotiming-s3c2410.c +++ b/arch/arm/mach-s3c/iotiming-s3c2410.c @@ -14,12 +14,12 @@ #include <linux/io.h> #include <linux/slab.h> -#include <mach/map.h> -#include <mach/regs-clock.h> +#include "map.h" +#include "regs-clock.h" -#include <plat/cpu-freq-core.h> +#include <linux/soc/samsung/s3c-cpufreq-core.h> -#include "regs-mem.h" +#include "regs-mem-s3c24xx.h" #define print_ns(x) ((x) / 10), ((x) % 10) @@ -129,7 +129,7 @@ static unsigned int calc_0124(unsigned int cyc, unsigned long hclk_tns, return 0; } -int calc_tacp(unsigned int cyc, unsigned long hclk, unsigned long *v) +static int calc_tacp(unsigned int cyc, unsigned long hclk, unsigned long *v) { /* Currently no support for Tacp calculations. */ return 0; @@ -288,8 +288,8 @@ static unsigned int get_0124(unsigned long hclk_tns, * Given the BANKCON setting in @bt and the current frequency settings * in @cfg, update the cycle timing information. */ -void s3c2410_iotiming_getbank(struct s3c_cpufreq_config *cfg, - struct s3c2410_iobank_timing *bt) +static void s3c2410_iotiming_getbank(struct s3c_cpufreq_config *cfg, + struct s3c2410_iobank_timing *bt) { unsigned long bankcon = bt->bankcon; unsigned long hclk = cfg->freq.hclk_tns; diff --git a/arch/arm/mach-s3c24xx/iotiming-s3c2412.c b/arch/arm/mach-s3c/iotiming-s3c2412.c index 59356d10fbcf..003f89c4dc53 100644 --- a/arch/arm/mach-s3c24xx/iotiming-s3c2412.c +++ b/arch/arm/mach-s3c/iotiming-s3c2412.c @@ -23,10 +23,10 @@ #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <plat/cpu.h> -#include <plat/cpu-freq-core.h> +#include "cpu.h" +#include <linux/soc/samsung/s3c-cpufreq-core.h> -#include <mach/s3c2412.h> +#include "s3c2412.h" #define print_ns(x) ((x) / 10), ((x) % 10) diff --git a/arch/arm/mach-s3c24xx/irq-pm.c b/arch/arm/mach-s3c/irq-pm-s3c24xx.c index e0131b16a4af..4d5e28312d91 100644 --- a/arch/arm/mach-s3c24xx/irq-pm.c +++ b/arch/arm/mach-s3c/irq-pm-s3c24xx.c @@ -13,14 +13,14 @@ #include <linux/syscore_ops.h> #include <linux/io.h> -#include <plat/cpu.h> -#include <plat/pm.h> -#include <plat/map-base.h> -#include <plat/map-s3c.h> - -#include <mach/regs-irq.h> -#include <mach/regs-gpio.h> -#include <mach/pm-core.h> +#include "cpu.h" +#include "pm.h" +#include <mach/map-base.h> +#include "map-s3c.h" + +#include "regs-irq.h" +#include "regs-gpio.h" +#include "pm-core.h" #include <asm/irq.h> diff --git a/arch/arm/mach-s3c64xx/irq-pm.c b/arch/arm/mach-s3c/irq-pm-s3c64xx.c index 31b221190479..4a1e935bada1 100644 --- a/arch/arm/mach-s3c64xx/irq-pm.c +++ b/arch/arm/mach-s3c/irq-pm-s3c64xx.c @@ -20,11 +20,11 @@ #include <linux/io.h> #include <linux/of.h> -#include <mach/map.h> +#include "map.h" -#include <mach/regs-gpio.h> -#include <plat/cpu.h> -#include <plat/pm.h> +#include "regs-gpio.h" +#include "cpu.h" +#include "pm.h" /* We handled all the IRQ types in this code, to save having to make several * small files to handle each different type separately. Having the EINT_GRP diff --git a/arch/arm/mach-s3c/irq-s3c24xx-fiq-exports.c b/arch/arm/mach-s3c/irq-s3c24xx-fiq-exports.c new file mode 100644 index 000000000000..84cf86376ded --- /dev/null +++ b/arch/arm/mach-s3c/irq-s3c24xx-fiq-exports.c @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include <linux/stddef.h> +#include <linux/export.h> +#include <linux/spi/s3c24xx-fiq.h> + +EXPORT_SYMBOL(s3c24xx_spi_fiq_rx); +EXPORT_SYMBOL(s3c24xx_spi_fiq_txrx); +EXPORT_SYMBOL(s3c24xx_spi_fiq_tx); diff --git a/arch/arm/mach-s3c/irq-s3c24xx-fiq.S b/arch/arm/mach-s3c/irq-s3c24xx-fiq.S new file mode 100644 index 000000000000..b54cbd012241 --- /dev/null +++ b/arch/arm/mach-s3c/irq-s3c24xx-fiq.S @@ -0,0 +1,115 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* linux/drivers/spi/spi_s3c24xx_fiq.S + * + * Copyright 2009 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * + * S3C24XX SPI - FIQ pseudo-DMA transfer code +*/ + +#include <linux/linkage.h> +#include <asm/assembler.h> + +#include "map.h" +#include "regs-irq.h" + +#include <linux/spi/s3c24xx-fiq.h> + +#define S3C2410_SPTDAT (0x10) +#define S3C2410_SPRDAT (0x14) + + .text + + @ entry to these routines is as follows, with the register names + @ defined in fiq.h so that they can be shared with the C files which + @ setup the calling registers. + @ + @ fiq_rirq The base of the IRQ registers to find S3C2410_SRCPND + @ fiq_rtmp Temporary register to hold tx/rx data + @ fiq_rspi The base of the SPI register block + @ fiq_rtx The tx buffer pointer + @ fiq_rrx The rx buffer pointer + @ fiq_rcount The number of bytes to move + + @ each entry starts with a word entry of how long it is + @ and an offset to the irq acknowledgment word + +ENTRY(s3c24xx_spi_fiq_rx) +s3c24xx_spi_fix_rx: + .word fiq_rx_end - fiq_rx_start + .word fiq_rx_irq_ack - fiq_rx_start +fiq_rx_start: + ldr fiq_rtmp, fiq_rx_irq_ack + str fiq_rtmp, [ fiq_rirq, # S3C2410_SRCPND - S3C24XX_VA_IRQ ] + + ldrb fiq_rtmp, [ fiq_rspi, # S3C2410_SPRDAT ] + strb fiq_rtmp, [ fiq_rrx ], #1 + + mov fiq_rtmp, #0xff + strb fiq_rtmp, [ fiq_rspi, # S3C2410_SPTDAT ] + + subs fiq_rcount, fiq_rcount, #1 + subnes pc, lr, #4 @@ return, still have work to do + + @@ set IRQ controller so that next op will trigger IRQ + mov fiq_rtmp, #0 + str fiq_rtmp, [ fiq_rirq, # S3C2410_INTMOD - S3C24XX_VA_IRQ ] + subs pc, lr, #4 + +fiq_rx_irq_ack: + .word 0 +fiq_rx_end: + +ENTRY(s3c24xx_spi_fiq_txrx) +s3c24xx_spi_fiq_txrx: + .word fiq_txrx_end - fiq_txrx_start + .word fiq_txrx_irq_ack - fiq_txrx_start +fiq_txrx_start: + + ldrb fiq_rtmp, [ fiq_rspi, # S3C2410_SPRDAT ] + strb fiq_rtmp, [ fiq_rrx ], #1 + + ldr fiq_rtmp, fiq_txrx_irq_ack + str fiq_rtmp, [ fiq_rirq, # S3C2410_SRCPND - S3C24XX_VA_IRQ ] + + ldrb fiq_rtmp, [ fiq_rtx ], #1 + strb fiq_rtmp, [ fiq_rspi, # S3C2410_SPTDAT ] + + subs fiq_rcount, fiq_rcount, #1 + subnes pc, lr, #4 @@ return, still have work to do + + mov fiq_rtmp, #0 + str fiq_rtmp, [ fiq_rirq, # S3C2410_INTMOD - S3C24XX_VA_IRQ ] + subs pc, lr, #4 + +fiq_txrx_irq_ack: + .word 0 + +fiq_txrx_end: + +ENTRY(s3c24xx_spi_fiq_tx) +s3c24xx_spi_fix_tx: + .word fiq_tx_end - fiq_tx_start + .word fiq_tx_irq_ack - fiq_tx_start +fiq_tx_start: + ldrb fiq_rtmp, [ fiq_rspi, # S3C2410_SPRDAT ] + + ldr fiq_rtmp, fiq_tx_irq_ack + str fiq_rtmp, [ fiq_rirq, # S3C2410_SRCPND - S3C24XX_VA_IRQ ] + + ldrb fiq_rtmp, [ fiq_rtx ], #1 + strb fiq_rtmp, [ fiq_rspi, # S3C2410_SPTDAT ] + + subs fiq_rcount, fiq_rcount, #1 + subnes pc, lr, #4 @@ return, still have work to do + + mov fiq_rtmp, #0 + str fiq_rtmp, [ fiq_rirq, # S3C2410_INTMOD - S3C24XX_VA_IRQ ] + subs pc, lr, #4 + +fiq_tx_irq_ack: + .word 0 + +fiq_tx_end: + + .end diff --git a/arch/arm/mach-s3c/irq-s3c24xx.c b/arch/arm/mach-s3c/irq-s3c24xx.c new file mode 100644 index 000000000000..79b5f19af7a5 --- /dev/null +++ b/arch/arm/mach-s3c/irq-s3c24xx.c @@ -0,0 +1,1337 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * S3C24XX IRQ handling + * + * Copyright (c) 2003-2004 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * Copyright (c) 2012 Heiko Stuebner <heiko@sntech.de> +*/ + +#include <linux/init.h> +#include <linux/slab.h> +#include <linux/module.h> +#include <linux/io.h> +#include <linux/err.h> +#include <linux/interrupt.h> +#include <linux/ioport.h> +#include <linux/device.h> +#include <linux/irqdomain.h> +#include <linux/irqchip.h> +#include <linux/irqchip/chained_irq.h> +#include <linux/of.h> +#include <linux/of_irq.h> +#include <linux/of_address.h> + +#include <asm/exception.h> +#include <asm/mach/irq.h> + +#include <mach/irqs.h> +#include "regs-irq.h" +#include "regs-gpio.h" + +#include "cpu.h" +#include "regs-irqtype.h" +#include "pm.h" + +#define S3C_IRQTYPE_NONE 0 +#define S3C_IRQTYPE_EINT 1 +#define S3C_IRQTYPE_EDGE 2 +#define S3C_IRQTYPE_LEVEL 3 + +struct s3c_irq_data { + unsigned int type; + unsigned long offset; + unsigned long parent_irq; + + /* data gets filled during init */ + struct s3c_irq_intc *intc; + unsigned long sub_bits; + struct s3c_irq_intc *sub_intc; +}; + +/* + * Structure holding the controller data + * @reg_pending register holding pending irqs + * @reg_intpnd special register intpnd in main intc + * @reg_mask mask register + * @domain irq_domain of the controller + * @parent parent controller for ext and sub irqs + * @irqs irq-data, always s3c_irq_data[32] + */ +struct s3c_irq_intc { + void __iomem *reg_pending; + void __iomem *reg_intpnd; + void __iomem *reg_mask; + struct irq_domain *domain; + struct s3c_irq_intc *parent; + struct s3c_irq_data *irqs; +}; + +/* + * Array holding pointers to the global controller structs + * [0] ... main_intc + * [1] ... sub_intc + * [2] ... main_intc2 on s3c2416 + */ +static struct s3c_irq_intc *s3c_intc[3]; + +static void s3c_irq_mask(struct irq_data *data) +{ + struct s3c_irq_data *irq_data = irq_data_get_irq_chip_data(data); + struct s3c_irq_intc *intc = irq_data->intc; + struct s3c_irq_intc *parent_intc = intc->parent; + struct s3c_irq_data *parent_data; + unsigned long mask; + unsigned int irqno; + + mask = readl_relaxed(intc->reg_mask); + mask |= (1UL << irq_data->offset); + writel_relaxed(mask, intc->reg_mask); + + if (parent_intc) { + parent_data = &parent_intc->irqs[irq_data->parent_irq]; + + /* check to see if we need to mask the parent IRQ + * The parent_irq is always in main_intc, so the hwirq + * for find_mapping does not need an offset in any case. + */ + if ((mask & parent_data->sub_bits) == parent_data->sub_bits) { + irqno = irq_find_mapping(parent_intc->domain, + irq_data->parent_irq); + s3c_irq_mask(irq_get_irq_data(irqno)); + } + } +} + +static void s3c_irq_unmask(struct irq_data *data) +{ + struct s3c_irq_data *irq_data = irq_data_get_irq_chip_data(data); + struct s3c_irq_intc *intc = irq_data->intc; + struct s3c_irq_intc *parent_intc = intc->parent; + unsigned long mask; + unsigned int irqno; + + mask = readl_relaxed(intc->reg_mask); + mask &= ~(1UL << irq_data->offset); + writel_relaxed(mask, intc->reg_mask); + + if (parent_intc) { + irqno = irq_find_mapping(parent_intc->domain, + irq_data->parent_irq); + s3c_irq_unmask(irq_get_irq_data(irqno)); + } +} + +static inline void s3c_irq_ack(struct irq_data *data) +{ + struct s3c_irq_data *irq_data = irq_data_get_irq_chip_data(data); + struct s3c_irq_intc *intc = irq_data->intc; + unsigned long bitval = 1UL << irq_data->offset; + + writel_relaxed(bitval, intc->reg_pending); + if (intc->reg_intpnd) + writel_relaxed(bitval, intc->reg_intpnd); +} + +static int s3c_irq_type(struct irq_data *data, unsigned int type) +{ + switch (type) { + case IRQ_TYPE_NONE: + break; + case IRQ_TYPE_EDGE_RISING: + case IRQ_TYPE_EDGE_FALLING: + case IRQ_TYPE_EDGE_BOTH: + irq_set_handler(data->irq, handle_edge_irq); + break; + case IRQ_TYPE_LEVEL_LOW: + case IRQ_TYPE_LEVEL_HIGH: + irq_set_handler(data->irq, handle_level_irq); + break; + default: + pr_err("No such irq type %d\n", type); + return -EINVAL; + } + + return 0; +} + +static int s3c_irqext_type_set(void __iomem *gpcon_reg, + void __iomem *extint_reg, + unsigned long gpcon_offset, + unsigned long extint_offset, + unsigned int type) +{ + unsigned long newvalue = 0, value; + + /* Set the GPIO to external interrupt mode */ + value = readl_relaxed(gpcon_reg); + value = (value & ~(3 << gpcon_offset)) | (0x02 << gpcon_offset); + writel_relaxed(value, gpcon_reg); + + /* Set the external interrupt to pointed trigger type */ + switch (type) + { + case IRQ_TYPE_NONE: + pr_warn("No edge setting!\n"); + break; + + case IRQ_TYPE_EDGE_RISING: + newvalue = S3C2410_EXTINT_RISEEDGE; + break; + + case IRQ_TYPE_EDGE_FALLING: + newvalue = S3C2410_EXTINT_FALLEDGE; + break; + + case IRQ_TYPE_EDGE_BOTH: + newvalue = S3C2410_EXTINT_BOTHEDGE; + break; + + case IRQ_TYPE_LEVEL_LOW: + newvalue = S3C2410_EXTINT_LOWLEV; + break; + + case IRQ_TYPE_LEVEL_HIGH: + newvalue = S3C2410_EXTINT_HILEV; + break; + + default: + pr_err("No such irq type %d\n", type); + return -EINVAL; + } + + value = readl_relaxed(extint_reg); + value = (value & ~(7 << extint_offset)) | (newvalue << extint_offset); + writel_relaxed(value, extint_reg); + + return 0; +} + +static int s3c_irqext_type(struct irq_data *data, unsigned int type) +{ + void __iomem *extint_reg; + void __iomem *gpcon_reg; + unsigned long gpcon_offset, extint_offset; + + if ((data->hwirq >= 4) && (data->hwirq <= 7)) { + gpcon_reg = S3C2410_GPFCON; + extint_reg = S3C24XX_EXTINT0; + gpcon_offset = (data->hwirq) * 2; + extint_offset = (data->hwirq) * 4; + } else if ((data->hwirq >= 8) && (data->hwirq <= 15)) { + gpcon_reg = S3C2410_GPGCON; + extint_reg = S3C24XX_EXTINT1; + gpcon_offset = (data->hwirq - 8) * 2; + extint_offset = (data->hwirq - 8) * 4; + } else if ((data->hwirq >= 16) && (data->hwirq <= 23)) { + gpcon_reg = S3C2410_GPGCON; + extint_reg = S3C24XX_EXTINT2; + gpcon_offset = (data->hwirq - 8) * 2; + extint_offset = (data->hwirq - 16) * 4; + } else { + return -EINVAL; + } + + return s3c_irqext_type_set(gpcon_reg, extint_reg, gpcon_offset, + extint_offset, type); +} + +static int s3c_irqext0_type(struct irq_data *data, unsigned int type) +{ + void __iomem *extint_reg; + void __iomem *gpcon_reg; + unsigned long gpcon_offset, extint_offset; + + if (data->hwirq <= 3) { + gpcon_reg = S3C2410_GPFCON; + extint_reg = S3C24XX_EXTINT0; + gpcon_offset = (data->hwirq) * 2; + extint_offset = (data->hwirq) * 4; + } else { + return -EINVAL; + } + + return s3c_irqext_type_set(gpcon_reg, extint_reg, gpcon_offset, + extint_offset, type); +} + +static struct irq_chip s3c_irq_chip = { + .name = "s3c", + .irq_ack = s3c_irq_ack, + .irq_mask = s3c_irq_mask, + .irq_unmask = s3c_irq_unmask, + .irq_set_type = s3c_irq_type, + .irq_set_wake = s3c_irq_wake +}; + +static struct irq_chip s3c_irq_level_chip = { + .name = "s3c-level", + .irq_mask = s3c_irq_mask, + .irq_unmask = s3c_irq_unmask, + .irq_ack = s3c_irq_ack, + .irq_set_type = s3c_irq_type, +}; + +static struct irq_chip s3c_irqext_chip = { + .name = "s3c-ext", + .irq_mask = s3c_irq_mask, + .irq_unmask = s3c_irq_unmask, + .irq_ack = s3c_irq_ack, + .irq_set_type = s3c_irqext_type, + .irq_set_wake = s3c_irqext_wake +}; + +static struct irq_chip s3c_irq_eint0t4 = { + .name = "s3c-ext0", + .irq_ack = s3c_irq_ack, + .irq_mask = s3c_irq_mask, + .irq_unmask = s3c_irq_unmask, + .irq_set_wake = s3c_irq_wake, + .irq_set_type = s3c_irqext0_type, +}; + +static void s3c_irq_demux(struct irq_desc *desc) +{ + struct irq_chip *chip = irq_desc_get_chip(desc); + struct s3c_irq_data *irq_data = irq_desc_get_chip_data(desc); + struct s3c_irq_intc *intc = irq_data->intc; + struct s3c_irq_intc *sub_intc = irq_data->sub_intc; + unsigned int n, offset, irq; + unsigned long src, msk; + + /* we're using individual domains for the non-dt case + * and one big domain for the dt case where the subintc + * starts at hwirq number 32. + */ + offset = irq_domain_get_of_node(intc->domain) ? 32 : 0; + + chained_irq_enter(chip, desc); + + src = readl_relaxed(sub_intc->reg_pending); + msk = readl_relaxed(sub_intc->reg_mask); + + src &= ~msk; + src &= irq_data->sub_bits; + + while (src) { + n = __ffs(src); + src &= ~(1 << n); + irq = irq_find_mapping(sub_intc->domain, offset + n); + generic_handle_irq(irq); + } + + chained_irq_exit(chip, desc); +} + +static inline int s3c24xx_handle_intc(struct s3c_irq_intc *intc, + struct pt_regs *regs, int intc_offset) +{ + int pnd; + int offset; + + pnd = readl_relaxed(intc->reg_intpnd); + if (!pnd) + return false; + + /* non-dt machines use individual domains */ + if (!irq_domain_get_of_node(intc->domain)) + intc_offset = 0; + + /* We have a problem that the INTOFFSET register does not always + * show one interrupt. Occasionally we get two interrupts through + * the prioritiser, and this causes the INTOFFSET register to show + * what looks like the logical-or of the two interrupt numbers. + * + * Thanks to Klaus, Shannon, et al for helping to debug this problem + */ + offset = readl_relaxed(intc->reg_intpnd + 4); + + /* Find the bit manually, when the offset is wrong. + * The pending register only ever contains the one bit of the next + * interrupt to handle. + */ + if (!(pnd & (1 << offset))) + offset = __ffs(pnd); + + handle_domain_irq(intc->domain, intc_offset + offset, regs); + return true; +} + +asmlinkage void __exception_irq_entry s3c24xx_handle_irq(struct pt_regs *regs) +{ + do { + if (likely(s3c_intc[0])) + if (s3c24xx_handle_intc(s3c_intc[0], regs, 0)) + continue; + + if (s3c_intc[2]) + if (s3c24xx_handle_intc(s3c_intc[2], regs, 64)) + continue; + + break; + } while (1); +} + +#ifdef CONFIG_FIQ +/** + * s3c24xx_set_fiq - set the FIQ routing + * @irq: IRQ number to route to FIQ on processor. + * @ack_ptr: pointer to a location for storing the bit mask + * @on: Whether to route @irq to the FIQ, or to remove the FIQ routing. + * + * Change the state of the IRQ to FIQ routing depending on @irq and @on. If + * @on is true, the @irq is checked to see if it can be routed and the + * interrupt controller updated to route the IRQ. If @on is false, the FIQ + * routing is cleared, regardless of which @irq is specified. + * + * returns the mask value for the register. + */ +int s3c24xx_set_fiq(unsigned int irq, u32 *ack_ptr, bool on) +{ + u32 intmod; + unsigned offs; + + if (on) { + offs = irq - FIQ_START; + if (offs > 31) + return 0; + + intmod = 1 << offs; + } else { + intmod = 0; + } + + if (ack_ptr) + *ack_ptr = intmod; + writel_relaxed(intmod, S3C2410_INTMOD); + + return intmod; +} + +EXPORT_SYMBOL_GPL(s3c24xx_set_fiq); +#endif + +static int s3c24xx_irq_map(struct irq_domain *h, unsigned int virq, + irq_hw_number_t hw) +{ + struct s3c_irq_intc *intc = h->host_data; + struct s3c_irq_data *irq_data = &intc->irqs[hw]; + struct s3c_irq_intc *parent_intc; + struct s3c_irq_data *parent_irq_data; + unsigned int irqno; + + /* attach controller pointer to irq_data */ + irq_data->intc = intc; + irq_data->offset = hw; + + parent_intc = intc->parent; + + /* set handler and flags */ + switch (irq_data->type) { + case S3C_IRQTYPE_NONE: + return 0; + case S3C_IRQTYPE_EINT: + /* On the S3C2412, the EINT0to3 have a parent irq + * but need the s3c_irq_eint0t4 chip + */ + if (parent_intc && (!soc_is_s3c2412() || hw >= 4)) + irq_set_chip_and_handler(virq, &s3c_irqext_chip, + handle_edge_irq); + else + irq_set_chip_and_handler(virq, &s3c_irq_eint0t4, + handle_edge_irq); + break; + case S3C_IRQTYPE_EDGE: + if (parent_intc || intc->reg_pending == S3C2416_SRCPND2) + irq_set_chip_and_handler(virq, &s3c_irq_level_chip, + handle_edge_irq); + else + irq_set_chip_and_handler(virq, &s3c_irq_chip, + handle_edge_irq); + break; + case S3C_IRQTYPE_LEVEL: + if (parent_intc) + irq_set_chip_and_handler(virq, &s3c_irq_level_chip, + handle_level_irq); + else + irq_set_chip_and_handler(virq, &s3c_irq_chip, + handle_level_irq); + break; + default: + pr_err("irq-s3c24xx: unsupported irqtype %d\n", irq_data->type); + return -EINVAL; + } + + irq_set_chip_data(virq, irq_data); + + if (parent_intc && irq_data->type != S3C_IRQTYPE_NONE) { + if (irq_data->parent_irq > 31) { + pr_err("irq-s3c24xx: parent irq %lu is out of range\n", + irq_data->parent_irq); + return -EINVAL; + } + + parent_irq_data = &parent_intc->irqs[irq_data->parent_irq]; + parent_irq_data->sub_intc = intc; + parent_irq_data->sub_bits |= (1UL << hw); + + /* attach the demuxer to the parent irq */ + irqno = irq_find_mapping(parent_intc->domain, + irq_data->parent_irq); + if (!irqno) { + pr_err("irq-s3c24xx: could not find mapping for parent irq %lu\n", + irq_data->parent_irq); + return -EINVAL; + } + irq_set_chained_handler(irqno, s3c_irq_demux); + } + + return 0; +} + +static const struct irq_domain_ops s3c24xx_irq_ops = { + .map = s3c24xx_irq_map, + .xlate = irq_domain_xlate_twocell, +}; + +static void s3c24xx_clear_intc(struct s3c_irq_intc *intc) +{ + void __iomem *reg_source; + unsigned long pend; + unsigned long last; + int i; + + /* if intpnd is set, read the next pending irq from there */ + reg_source = intc->reg_intpnd ? intc->reg_intpnd : intc->reg_pending; + + last = 0; + for (i = 0; i < 4; i++) { + pend = readl_relaxed(reg_source); + + if (pend == 0 || pend == last) + break; + + writel_relaxed(pend, intc->reg_pending); + if (intc->reg_intpnd) + writel_relaxed(pend, intc->reg_intpnd); + + pr_info("irq: clearing pending status %08x\n", (int)pend); + last = pend; + } +} + +static struct s3c_irq_intc * __init s3c24xx_init_intc(struct device_node *np, + struct s3c_irq_data *irq_data, + struct s3c_irq_intc *parent, + unsigned long address) +{ + struct s3c_irq_intc *intc; + void __iomem *base = (void *)0xf6000000; /* static mapping */ + int irq_num; + int irq_start; + int ret; + + intc = kzalloc(sizeof(struct s3c_irq_intc), GFP_KERNEL); + if (!intc) + return ERR_PTR(-ENOMEM); + + intc->irqs = irq_data; + + if (parent) + intc->parent = parent; + + /* select the correct data for the controller. + * Need to hard code the irq num start and offset + * to preserve the static mapping for now + */ + switch (address) { + case 0x4a000000: + pr_debug("irq: found main intc\n"); + intc->reg_pending = base; + intc->reg_mask = base + 0x08; + intc->reg_intpnd = base + 0x10; + irq_num = 32; + irq_start = S3C2410_IRQ(0); + break; + case 0x4a000018: + pr_debug("irq: found subintc\n"); + intc->reg_pending = base + 0x18; + intc->reg_mask = base + 0x1c; + irq_num = 29; + irq_start = S3C2410_IRQSUB(0); + break; + case 0x4a000040: + pr_debug("irq: found intc2\n"); + intc->reg_pending = base + 0x40; + intc->reg_mask = base + 0x48; + intc->reg_intpnd = base + 0x50; + irq_num = 8; + irq_start = S3C2416_IRQ(0); + break; + case 0x560000a4: + pr_debug("irq: found eintc\n"); + base = (void *)0xfd000000; + + intc->reg_mask = base + 0xa4; + intc->reg_pending = base + 0xa8; + irq_num = 24; + irq_start = S3C2410_IRQ(32); + break; + default: + pr_err("irq: unsupported controller address\n"); + ret = -EINVAL; + goto err; + } + + /* now that all the data is complete, init the irq-domain */ + s3c24xx_clear_intc(intc); + intc->domain = irq_domain_add_legacy(np, irq_num, irq_start, + 0, &s3c24xx_irq_ops, + intc); + if (!intc->domain) { + pr_err("irq: could not create irq-domain\n"); + ret = -EINVAL; + goto err; + } + + set_handle_irq(s3c24xx_handle_irq); + + return intc; + +err: + kfree(intc); + return ERR_PTR(ret); +} + +static struct s3c_irq_data __maybe_unused init_eint[32] = { + { .type = S3C_IRQTYPE_NONE, }, /* reserved */ + { .type = S3C_IRQTYPE_NONE, }, /* reserved */ + { .type = S3C_IRQTYPE_NONE, }, /* reserved */ + { .type = S3C_IRQTYPE_NONE, }, /* reserved */ + { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT4 */ + { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT5 */ + { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT6 */ + { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT7 */ + { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT8 */ + { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT9 */ + { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT10 */ + { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT11 */ + { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT12 */ + { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT13 */ + { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT14 */ + { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT15 */ + { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT16 */ + { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT17 */ + { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT18 */ + { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT19 */ + { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT20 */ + { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT21 */ + { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT22 */ + { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT23 */ +}; + +#ifdef CONFIG_CPU_S3C2410 +static struct s3c_irq_data init_s3c2410base[32] = { + { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */ + { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */ + { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */ + { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */ + { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */ + { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */ + { .type = S3C_IRQTYPE_NONE, }, /* reserved */ + { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */ + { .type = S3C_IRQTYPE_EDGE, }, /* TICK */ + { .type = S3C_IRQTYPE_EDGE, }, /* WDT */ + { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */ + { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */ + { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */ + { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */ + { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */ + { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */ + { .type = S3C_IRQTYPE_EDGE, }, /* LCD */ + { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */ + { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */ + { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */ + { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */ + { .type = S3C_IRQTYPE_EDGE, }, /* SDI */ + { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */ + { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */ + { .type = S3C_IRQTYPE_NONE, }, /* reserved */ + { .type = S3C_IRQTYPE_EDGE, }, /* USBD */ + { .type = S3C_IRQTYPE_EDGE, }, /* USBH */ + { .type = S3C_IRQTYPE_EDGE, }, /* IIC */ + { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */ + { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */ + { .type = S3C_IRQTYPE_EDGE, }, /* RTC */ + { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */ +}; + +static struct s3c_irq_data init_s3c2410subint[32] = { + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */ + { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */ + { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */ +}; + +void __init s3c2410_init_irq(void) +{ +#ifdef CONFIG_FIQ + init_FIQ(FIQ_START); +#endif + + s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2410base[0], NULL, + 0x4a000000); + if (IS_ERR(s3c_intc[0])) { + pr_err("irq: could not create main interrupt controller\n"); + return; + } + + s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2410subint[0], + s3c_intc[0], 0x4a000018); + s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4); +} +#endif + +#ifdef CONFIG_CPU_S3C2412 +static struct s3c_irq_data init_s3c2412base[32] = { + { .type = S3C_IRQTYPE_LEVEL, }, /* EINT0 */ + { .type = S3C_IRQTYPE_LEVEL, }, /* EINT1 */ + { .type = S3C_IRQTYPE_LEVEL, }, /* EINT2 */ + { .type = S3C_IRQTYPE_LEVEL, }, /* EINT3 */ + { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */ + { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */ + { .type = S3C_IRQTYPE_NONE, }, /* reserved */ + { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */ + { .type = S3C_IRQTYPE_EDGE, }, /* TICK */ + { .type = S3C_IRQTYPE_EDGE, }, /* WDT */ + { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */ + { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */ + { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */ + { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */ + { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */ + { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */ + { .type = S3C_IRQTYPE_EDGE, }, /* LCD */ + { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */ + { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */ + { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */ + { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */ + { .type = S3C_IRQTYPE_LEVEL, }, /* SDI/CF */ + { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */ + { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */ + { .type = S3C_IRQTYPE_NONE, }, /* reserved */ + { .type = S3C_IRQTYPE_EDGE, }, /* USBD */ + { .type = S3C_IRQTYPE_EDGE, }, /* USBH */ + { .type = S3C_IRQTYPE_EDGE, }, /* IIC */ + { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */ + { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */ + { .type = S3C_IRQTYPE_EDGE, }, /* RTC */ + { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */ +}; + +static struct s3c_irq_data init_s3c2412eint[32] = { + { .type = S3C_IRQTYPE_EINT, .parent_irq = 0 }, /* EINT0 */ + { .type = S3C_IRQTYPE_EINT, .parent_irq = 1 }, /* EINT1 */ + { .type = S3C_IRQTYPE_EINT, .parent_irq = 2 }, /* EINT2 */ + { .type = S3C_IRQTYPE_EINT, .parent_irq = 3 }, /* EINT3 */ + { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT4 */ + { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT5 */ + { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT6 */ + { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT7 */ + { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT8 */ + { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT9 */ + { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT10 */ + { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT11 */ + { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT12 */ + { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT13 */ + { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT14 */ + { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT15 */ + { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT16 */ + { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT17 */ + { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT18 */ + { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT19 */ + { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT20 */ + { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT21 */ + { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT22 */ + { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT23 */ +}; + +static struct s3c_irq_data init_s3c2412subint[32] = { + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */ + { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */ + { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */ + { .type = S3C_IRQTYPE_NONE, }, + { .type = S3C_IRQTYPE_NONE, }, + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 21 }, /* SDI */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 21 }, /* CF */ +}; + +void __init s3c2412_init_irq(void) +{ + pr_info("S3C2412: IRQ Support\n"); + +#ifdef CONFIG_FIQ + init_FIQ(FIQ_START); +#endif + + s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2412base[0], NULL, + 0x4a000000); + if (IS_ERR(s3c_intc[0])) { + pr_err("irq: could not create main interrupt controller\n"); + return; + } + + s3c24xx_init_intc(NULL, &init_s3c2412eint[0], s3c_intc[0], 0x560000a4); + s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2412subint[0], + s3c_intc[0], 0x4a000018); +} +#endif + +#ifdef CONFIG_CPU_S3C2416 +static struct s3c_irq_data init_s3c2416base[32] = { + { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */ + { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */ + { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */ + { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */ + { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */ + { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */ + { .type = S3C_IRQTYPE_NONE, }, /* reserved */ + { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */ + { .type = S3C_IRQTYPE_EDGE, }, /* TICK */ + { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */ + { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */ + { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */ + { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */ + { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */ + { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */ + { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */ + { .type = S3C_IRQTYPE_LEVEL, }, /* LCD */ + { .type = S3C_IRQTYPE_LEVEL, }, /* DMA */ + { .type = S3C_IRQTYPE_LEVEL, }, /* UART3 */ + { .type = S3C_IRQTYPE_NONE, }, /* reserved */ + { .type = S3C_IRQTYPE_EDGE, }, /* SDI1 */ + { .type = S3C_IRQTYPE_EDGE, }, /* SDI0 */ + { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */ + { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */ + { .type = S3C_IRQTYPE_EDGE, }, /* NAND */ + { .type = S3C_IRQTYPE_EDGE, }, /* USBD */ + { .type = S3C_IRQTYPE_EDGE, }, /* USBH */ + { .type = S3C_IRQTYPE_EDGE, }, /* IIC */ + { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */ + { .type = S3C_IRQTYPE_NONE, }, + { .type = S3C_IRQTYPE_EDGE, }, /* RTC */ + { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */ +}; + +static struct s3c_irq_data init_s3c2416subint[32] = { + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */ + { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */ + { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */ + { .type = S3C_IRQTYPE_NONE }, /* reserved */ + { .type = S3C_IRQTYPE_NONE }, /* reserved */ + { .type = S3C_IRQTYPE_NONE }, /* reserved */ + { .type = S3C_IRQTYPE_NONE }, /* reserved */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD2 */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD3 */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD4 */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA0 */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA1 */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA4 */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA5 */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */ +}; + +static struct s3c_irq_data init_s3c2416_second[32] = { + { .type = S3C_IRQTYPE_EDGE }, /* 2D */ + { .type = S3C_IRQTYPE_NONE }, /* reserved */ + { .type = S3C_IRQTYPE_NONE }, /* reserved */ + { .type = S3C_IRQTYPE_NONE }, /* reserved */ + { .type = S3C_IRQTYPE_EDGE }, /* PCM0 */ + { .type = S3C_IRQTYPE_NONE }, /* reserved */ + { .type = S3C_IRQTYPE_EDGE }, /* I2S0 */ +}; + +void __init s3c2416_init_irq(void) +{ + pr_info("S3C2416: IRQ Support\n"); + +#ifdef CONFIG_FIQ + init_FIQ(FIQ_START); +#endif + + s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2416base[0], NULL, + 0x4a000000); + if (IS_ERR(s3c_intc[0])) { + pr_err("irq: could not create main interrupt controller\n"); + return; + } + + s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4); + s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2416subint[0], + s3c_intc[0], 0x4a000018); + + s3c_intc[2] = s3c24xx_init_intc(NULL, &init_s3c2416_second[0], + NULL, 0x4a000040); +} + +#endif + +#ifdef CONFIG_CPU_S3C2440 +static struct s3c_irq_data init_s3c2440base[32] = { + { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */ + { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */ + { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */ + { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */ + { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */ + { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */ + { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */ + { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */ + { .type = S3C_IRQTYPE_EDGE, }, /* TICK */ + { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */ + { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */ + { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */ + { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */ + { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */ + { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */ + { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */ + { .type = S3C_IRQTYPE_EDGE, }, /* LCD */ + { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */ + { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */ + { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */ + { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */ + { .type = S3C_IRQTYPE_EDGE, }, /* SDI */ + { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */ + { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */ + { .type = S3C_IRQTYPE_LEVEL, }, /* NFCON */ + { .type = S3C_IRQTYPE_EDGE, }, /* USBD */ + { .type = S3C_IRQTYPE_EDGE, }, /* USBH */ + { .type = S3C_IRQTYPE_EDGE, }, /* IIC */ + { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */ + { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */ + { .type = S3C_IRQTYPE_EDGE, }, /* RTC */ + { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */ +}; + +static struct s3c_irq_data init_s3c2440subint[32] = { + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */ + { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */ + { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */ +}; + +void __init s3c2440_init_irq(void) +{ + pr_info("S3C2440: IRQ Support\n"); + +#ifdef CONFIG_FIQ + init_FIQ(FIQ_START); +#endif + + s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2440base[0], NULL, + 0x4a000000); + if (IS_ERR(s3c_intc[0])) { + pr_err("irq: could not create main interrupt controller\n"); + return; + } + + s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4); + s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2440subint[0], + s3c_intc[0], 0x4a000018); +} +#endif + +#ifdef CONFIG_CPU_S3C2442 +static struct s3c_irq_data init_s3c2442base[32] = { + { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */ + { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */ + { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */ + { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */ + { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */ + { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */ + { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */ + { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */ + { .type = S3C_IRQTYPE_EDGE, }, /* TICK */ + { .type = S3C_IRQTYPE_EDGE, }, /* WDT */ + { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */ + { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */ + { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */ + { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */ + { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */ + { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */ + { .type = S3C_IRQTYPE_EDGE, }, /* LCD */ + { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */ + { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */ + { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */ + { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */ + { .type = S3C_IRQTYPE_EDGE, }, /* SDI */ + { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */ + { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */ + { .type = S3C_IRQTYPE_LEVEL, }, /* NFCON */ + { .type = S3C_IRQTYPE_EDGE, }, /* USBD */ + { .type = S3C_IRQTYPE_EDGE, }, /* USBH */ + { .type = S3C_IRQTYPE_EDGE, }, /* IIC */ + { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */ + { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */ + { .type = S3C_IRQTYPE_EDGE, }, /* RTC */ + { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */ +}; + +static struct s3c_irq_data init_s3c2442subint[32] = { + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */ + { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */ + { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */ +}; + +void __init s3c2442_init_irq(void) +{ + pr_info("S3C2442: IRQ Support\n"); + +#ifdef CONFIG_FIQ + init_FIQ(FIQ_START); +#endif + + s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2442base[0], NULL, + 0x4a000000); + if (IS_ERR(s3c_intc[0])) { + pr_err("irq: could not create main interrupt controller\n"); + return; + } + + s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4); + s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2442subint[0], + s3c_intc[0], 0x4a000018); +} +#endif + +#ifdef CONFIG_CPU_S3C2443 +static struct s3c_irq_data init_s3c2443base[32] = { + { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */ + { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */ + { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */ + { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */ + { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */ + { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */ + { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */ + { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */ + { .type = S3C_IRQTYPE_EDGE, }, /* TICK */ + { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */ + { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */ + { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */ + { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */ + { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */ + { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */ + { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */ + { .type = S3C_IRQTYPE_LEVEL, }, /* LCD */ + { .type = S3C_IRQTYPE_LEVEL, }, /* DMA */ + { .type = S3C_IRQTYPE_LEVEL, }, /* UART3 */ + { .type = S3C_IRQTYPE_EDGE, }, /* CFON */ + { .type = S3C_IRQTYPE_EDGE, }, /* SDI1 */ + { .type = S3C_IRQTYPE_EDGE, }, /* SDI0 */ + { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */ + { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */ + { .type = S3C_IRQTYPE_EDGE, }, /* NAND */ + { .type = S3C_IRQTYPE_EDGE, }, /* USBD */ + { .type = S3C_IRQTYPE_EDGE, }, /* USBH */ + { .type = S3C_IRQTYPE_EDGE, }, /* IIC */ + { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */ + { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */ + { .type = S3C_IRQTYPE_EDGE, }, /* RTC */ + { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */ +}; + + +static struct s3c_irq_data init_s3c2443subint[32] = { + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */ + { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */ + { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */ + { .type = S3C_IRQTYPE_NONE }, /* reserved */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD1 */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD2 */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD3 */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD4 */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA0 */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA1 */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA4 */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA5 */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */ + { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */ +}; + +void __init s3c2443_init_irq(void) +{ + pr_info("S3C2443: IRQ Support\n"); + +#ifdef CONFIG_FIQ + init_FIQ(FIQ_START); +#endif + + s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2443base[0], NULL, + 0x4a000000); + if (IS_ERR(s3c_intc[0])) { + pr_err("irq: could not create main interrupt controller\n"); + return; + } + + s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4); + s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2443subint[0], + s3c_intc[0], 0x4a000018); +} +#endif + +#ifdef CONFIG_OF +static int s3c24xx_irq_map_of(struct irq_domain *h, unsigned int virq, + irq_hw_number_t hw) +{ + unsigned int ctrl_num = hw / 32; + unsigned int intc_hw = hw % 32; + struct s3c_irq_intc *intc = s3c_intc[ctrl_num]; + struct s3c_irq_intc *parent_intc = intc->parent; + struct s3c_irq_data *irq_data = &intc->irqs[intc_hw]; + + /* attach controller pointer to irq_data */ + irq_data->intc = intc; + irq_data->offset = intc_hw; + + if (!parent_intc) + irq_set_chip_and_handler(virq, &s3c_irq_chip, handle_edge_irq); + else + irq_set_chip_and_handler(virq, &s3c_irq_level_chip, + handle_edge_irq); + + irq_set_chip_data(virq, irq_data); + + return 0; +} + +/* Translate our of irq notation + * format: <ctrl_num ctrl_irq parent_irq type> + */ +static int s3c24xx_irq_xlate_of(struct irq_domain *d, struct device_node *n, + const u32 *intspec, unsigned int intsize, + irq_hw_number_t *out_hwirq, unsigned int *out_type) +{ + struct s3c_irq_intc *intc; + struct s3c_irq_intc *parent_intc; + struct s3c_irq_data *irq_data; + struct s3c_irq_data *parent_irq_data; + int irqno; + + if (WARN_ON(intsize < 4)) + return -EINVAL; + + if (intspec[0] > 2 || !s3c_intc[intspec[0]]) { + pr_err("controller number %d invalid\n", intspec[0]); + return -EINVAL; + } + intc = s3c_intc[intspec[0]]; + + *out_hwirq = intspec[0] * 32 + intspec[2]; + *out_type = intspec[3] & IRQ_TYPE_SENSE_MASK; + + parent_intc = intc->parent; + if (parent_intc) { + irq_data = &intc->irqs[intspec[2]]; + irq_data->parent_irq = intspec[1]; + parent_irq_data = &parent_intc->irqs[irq_data->parent_irq]; + parent_irq_data->sub_intc = intc; + parent_irq_data->sub_bits |= (1UL << intspec[2]); + + /* parent_intc is always s3c_intc[0], so no offset */ + irqno = irq_create_mapping(parent_intc->domain, intspec[1]); + if (irqno < 0) { + pr_err("irq: could not map parent interrupt\n"); + return irqno; + } + + irq_set_chained_handler(irqno, s3c_irq_demux); + } + + return 0; +} + +static const struct irq_domain_ops s3c24xx_irq_ops_of = { + .map = s3c24xx_irq_map_of, + .xlate = s3c24xx_irq_xlate_of, +}; + +struct s3c24xx_irq_of_ctrl { + char *name; + unsigned long offset; + struct s3c_irq_intc **handle; + struct s3c_irq_intc **parent; + struct irq_domain_ops *ops; +}; + +static int __init s3c_init_intc_of(struct device_node *np, + struct device_node *interrupt_parent, + struct s3c24xx_irq_of_ctrl *s3c_ctrl, int num_ctrl) +{ + struct s3c_irq_intc *intc; + struct s3c24xx_irq_of_ctrl *ctrl; + struct irq_domain *domain; + void __iomem *reg_base; + int i; + + reg_base = of_iomap(np, 0); + if (!reg_base) { + pr_err("irq-s3c24xx: could not map irq registers\n"); + return -EINVAL; + } + + domain = irq_domain_add_linear(np, num_ctrl * 32, + &s3c24xx_irq_ops_of, NULL); + if (!domain) { + pr_err("irq: could not create irq-domain\n"); + return -EINVAL; + } + + for (i = 0; i < num_ctrl; i++) { + ctrl = &s3c_ctrl[i]; + + pr_debug("irq: found controller %s\n", ctrl->name); + + intc = kzalloc(sizeof(struct s3c_irq_intc), GFP_KERNEL); + if (!intc) + return -ENOMEM; + + intc->domain = domain; + intc->irqs = kcalloc(32, sizeof(struct s3c_irq_data), + GFP_KERNEL); + if (!intc->irqs) { + kfree(intc); + return -ENOMEM; + } + + if (ctrl->parent) { + intc->reg_pending = reg_base + ctrl->offset; + intc->reg_mask = reg_base + ctrl->offset + 0x4; + + if (*(ctrl->parent)) { + intc->parent = *(ctrl->parent); + } else { + pr_warn("irq: parent of %s missing\n", + ctrl->name); + kfree(intc->irqs); + kfree(intc); + continue; + } + } else { + intc->reg_pending = reg_base + ctrl->offset; + intc->reg_mask = reg_base + ctrl->offset + 0x08; + intc->reg_intpnd = reg_base + ctrl->offset + 0x10; + } + + s3c24xx_clear_intc(intc); + s3c_intc[i] = intc; + } + + set_handle_irq(s3c24xx_handle_irq); + + return 0; +} + +static struct s3c24xx_irq_of_ctrl s3c2410_ctrl[] = { + { + .name = "intc", + .offset = 0, + }, { + .name = "subintc", + .offset = 0x18, + .parent = &s3c_intc[0], + } +}; + +int __init s3c2410_init_intc_of(struct device_node *np, + struct device_node *interrupt_parent) +{ + return s3c_init_intc_of(np, interrupt_parent, + s3c2410_ctrl, ARRAY_SIZE(s3c2410_ctrl)); +} +IRQCHIP_DECLARE(s3c2410_irq, "samsung,s3c2410-irq", s3c2410_init_intc_of); + +static struct s3c24xx_irq_of_ctrl s3c2416_ctrl[] = { + { + .name = "intc", + .offset = 0, + }, { + .name = "subintc", + .offset = 0x18, + .parent = &s3c_intc[0], + }, { + .name = "intc2", + .offset = 0x40, + } +}; + +int __init s3c2416_init_intc_of(struct device_node *np, + struct device_node *interrupt_parent) +{ + return s3c_init_intc_of(np, interrupt_parent, + s3c2416_ctrl, ARRAY_SIZE(s3c2416_ctrl)); +} +IRQCHIP_DECLARE(s3c2416_irq, "samsung,s3c2416-irq", s3c2416_init_intc_of); +#endif diff --git a/arch/arm/mach-s3c64xx/irq-uart.h b/arch/arm/mach-s3c/irq-uart-s3c64xx.h index 78eccdce95a7..78eccdce95a7 100644 --- a/arch/arm/mach-s3c64xx/irq-uart.h +++ b/arch/arm/mach-s3c/irq-uart-s3c64xx.h diff --git a/arch/arm/plat-samsung/include/plat/keypad.h b/arch/arm/mach-s3c/keypad.h index 9754b9a29945..9754b9a29945 100644 --- a/arch/arm/plat-samsung/include/plat/keypad.h +++ b/arch/arm/mach-s3c/keypad.h diff --git a/arch/arm/mach-s3c24xx/mach-amlm5900.c b/arch/arm/mach-s3c/mach-amlm5900.c index 9a9daf526d0c..94c4512ace17 100644 --- a/arch/arm/mach-s3c24xx/mach-amlm5900.c +++ b/arch/arm/mach-s3c/mach-amlm5900.c @@ -13,6 +13,7 @@ #include <linux/list.h> #include <linux/timer.h> #include <linux/init.h> +#include <linux/gpio/machine.h> #include <linux/gpio.h> #include <linux/device.h> #include <linux/platform_device.h> @@ -26,28 +27,24 @@ #include <asm/mach/irq.h> #include <asm/mach/flash.h> -#include <mach/hardware.h> #include <asm/irq.h> #include <asm/mach-types.h> -#include <mach/fb.h> +#include <linux/platform_data/fb-s3c2410.h> -#include <mach/regs-lcd.h> -#include <mach/regs-gpio.h> -#include <mach/gpio-samsung.h> +#include "regs-gpio.h" +#include "gpio-samsung.h" #include <linux/platform_data/i2c-s3c2410.h> -#include <plat/devs.h> -#include <plat/cpu.h> -#include <plat/gpio-cfg.h> +#include "devs.h" +#include "cpu.h" +#include "gpio-cfg.h" #include <linux/mtd/mtd.h> #include <linux/mtd/partitions.h> #include <linux/mtd/map.h> #include <linux/mtd/physmap.h> -#include <plat/samsung-time.h> - -#include "common.h" +#include "s3c24xx.h" static struct resource amlm5900_nor_resource = DEFINE_RES_MEM(0x00000000, SZ_16M); @@ -124,6 +121,19 @@ static struct s3c2410_uartcfg amlm5900_uartcfgs[] = { } }; +static struct gpiod_lookup_table amlm5900_mmc_gpio_table = { + .dev_id = "s3c2410-sdi", + .table = { + /* bus pins */ + GPIO_LOOKUP_IDX("GPIOE", 5, "bus", 0, GPIO_ACTIVE_HIGH), + GPIO_LOOKUP_IDX("GPIOE", 6, "bus", 1, GPIO_ACTIVE_HIGH), + GPIO_LOOKUP_IDX("GPIOE", 7, "bus", 2, GPIO_ACTIVE_HIGH), + GPIO_LOOKUP_IDX("GPIOE", 8, "bus", 3, GPIO_ACTIVE_HIGH), + GPIO_LOOKUP_IDX("GPIOE", 9, "bus", 4, GPIO_ACTIVE_HIGH), + GPIO_LOOKUP_IDX("GPIOE", 10, "bus", 5, GPIO_ACTIVE_HIGH), + { }, + }, +}; static struct platform_device *amlm5900_devices[] __initdata = { #ifdef CONFIG_FB_S3C2410 @@ -143,13 +153,13 @@ static void __init amlm5900_map_io(void) { s3c24xx_init_io(amlm5900_iodesc, ARRAY_SIZE(amlm5900_iodesc)); s3c24xx_init_uarts(amlm5900_uartcfgs, ARRAY_SIZE(amlm5900_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); + s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4); } static void __init amlm5900_init_time(void) { s3c2410_init_clocks(12000000); - samsung_timer_init(); + s3c24xx_timer_init(); } #ifdef CONFIG_FB_S3C2410 @@ -180,13 +190,17 @@ static struct s3c2410fb_mach_info __initdata amlm5900_fb_info = { .gpccon = 0xaaaaaaaa, .gpccon_mask = 0xffffffff, + .gpccon_reg = S3C2410_GPCCON, .gpcup = 0x0000ffff, .gpcup_mask = 0xffffffff, + .gpcup_reg = S3C2410_GPCUP, .gpdcon = 0xaaaaaaaa, .gpdcon_mask = 0xffffffff, + .gpdcon_reg = S3C2410_GPDCON, .gpdup = 0x0000ffff, .gpdup_mask = 0xffffffff, + .gpdup_reg = S3C2410_GPDUP, }; #endif @@ -219,6 +233,7 @@ static void __init amlm5900_init(void) s3c24xx_fb_set_platdata(&amlm5900_fb_info); #endif s3c_i2c0_set_platdata(NULL); + gpiod_add_lookup_table(&amlm5900_mmc_gpio_table); platform_add_devices(amlm5900_devices, ARRAY_SIZE(amlm5900_devices)); } diff --git a/arch/arm/mach-s3c24xx/mach-anubis.c b/arch/arm/mach-s3c/mach-anubis.c index 072966dcad78..90e3fd98a3ac 100644 --- a/arch/arm/mach-s3c24xx/mach-anubis.c +++ b/arch/arm/mach-s3c/mach-anubis.c @@ -24,13 +24,11 @@ #include <asm/mach/map.h> #include <asm/mach/irq.h> -#include <mach/hardware.h> #include <asm/irq.h> #include <asm/mach-types.h> -#include <mach/regs-gpio.h> -#include <mach/regs-lcd.h> -#include <mach/gpio-samsung.h> +#include "regs-gpio.h" +#include "gpio-samsung.h" #include <linux/platform_data/mtd-nand-s3c2410.h> #include <linux/platform_data/i2c-s3c2410.h> @@ -41,13 +39,12 @@ #include <net/ax88796.h> -#include <plat/devs.h> -#include <plat/cpu.h> +#include "devs.h" +#include "cpu.h" #include <linux/platform_data/asoc-s3c24xx_simtec.h> -#include <plat/samsung-time.h> #include "anubis.h" -#include "common.h" +#include "s3c24xx.h" #include "simtec.h" #define COPYRIGHT ", Copyright 2005-2009 Simtec Electronics" @@ -218,7 +215,7 @@ static struct s3c2410_platform_nand __initdata anubis_nand_info = { .nr_sets = ARRAY_SIZE(anubis_nand_sets), .sets = anubis_nand_sets, .select_chip = anubis_nand_select, - .ecc_mode = NAND_ECC_SOFT, + .engine_type = NAND_ECC_ENGINE_TYPE_SOFT, }; /* IDE channels */ @@ -384,7 +381,7 @@ static void __init anubis_map_io(void) { s3c24xx_init_io(anubis_iodesc, ARRAY_SIZE(anubis_iodesc)); s3c24xx_init_uarts(anubis_uartcfgs, ARRAY_SIZE(anubis_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); + s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4); /* check for the newer revision boards with large page nand */ @@ -403,7 +400,7 @@ static void __init anubis_map_io(void) static void __init anubis_init_time(void) { s3c2440_init_clocks(12000000); - samsung_timer_init(); + s3c24xx_timer_init(); } static void __init anubis_init(void) diff --git a/arch/arm/mach-s3c64xx/mach-anw6410.c b/arch/arm/mach-s3c/mach-anw6410.c index 0d3d5befb806..825714e9ac66 100644 --- a/arch/arm/mach-s3c64xx/mach-anw6410.c +++ b/arch/arm/mach-s3c/mach-anw6410.c @@ -30,24 +30,22 @@ #include <asm/mach/map.h> #include <asm/mach/irq.h> -#include <mach/hardware.h> -#include <mach/map.h> +#include "map.h" #include <asm/irq.h> #include <asm/mach-types.h> #include <linux/platform_data/i2c-s3c2410.h> -#include <plat/fb.h> +#include "fb.h" -#include <plat/devs.h> -#include <plat/cpu.h> +#include "devs.h" +#include "cpu.h" #include <mach/irqs.h> -#include <mach/regs-gpio.h> -#include <mach/gpio-samsung.h> -#include <plat/samsung-time.h> +#include "regs-gpio.h" +#include "gpio-samsung.h" -#include "common.h" -#include "regs-modem.h" +#include "s3c64xx.h" +#include "regs-modem-s3c64xx.h" /* DM9000 */ #define ANW6410_PA_DM9000 (0x18000000) @@ -204,7 +202,7 @@ static void __init anw6410_map_io(void) s3c64xx_init_io(anw6410_iodesc, ARRAY_SIZE(anw6410_iodesc)); s3c64xx_set_xtal_freq(12000000); s3c24xx_init_uarts(anw6410_uartcfgs, ARRAY_SIZE(anw6410_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); + s3c64xx_set_timer_source(S3C64XX_PWM3, S3C64XX_PWM4); anw6410_lcd_mode_set(); } @@ -228,6 +226,5 @@ MACHINE_START(ANW6410, "A&W6410") .init_irq = s3c6410_init_irq, .map_io = anw6410_map_io, .init_machine = anw6410_machine_init, - .init_time = samsung_timer_init, - .restart = s3c64xx_restart, + .init_time = s3c64xx_timer_init, MACHINE_END diff --git a/arch/arm/mach-s3c24xx/mach-at2440evb.c b/arch/arm/mach-s3c/mach-at2440evb.c index 58c5ef3cf1d7..5fa49d4e2650 100644 --- a/arch/arm/mach-s3c24xx/mach-at2440evb.c +++ b/arch/arm/mach-s3c/mach-at2440evb.c @@ -24,14 +24,12 @@ #include <asm/mach/map.h> #include <asm/mach/irq.h> -#include <mach/hardware.h> -#include <mach/fb.h> +#include <linux/platform_data/fb-s3c2410.h> #include <asm/irq.h> #include <asm/mach-types.h> -#include <mach/regs-gpio.h> -#include <mach/regs-lcd.h> -#include <mach/gpio-samsung.h> +#include "regs-gpio.h" +#include "gpio-samsung.h" #include <linux/platform_data/mtd-nand-s3c2410.h> #include <linux/platform_data/i2c-s3c2410.h> @@ -40,12 +38,11 @@ #include <linux/mtd/nand_ecc.h> #include <linux/mtd/partitions.h> -#include <plat/devs.h> -#include <plat/cpu.h> +#include "devs.h" +#include "cpu.h" #include <linux/platform_data/mmc-s3cmci.h> -#include <plat/samsung-time.h> -#include "common.h" +#include "s3c24xx.h" static struct map_desc at2440evb_iodesc[] __initdata = { /* Nothing here */ @@ -109,7 +106,7 @@ static struct s3c2410_platform_nand __initdata at2440evb_nand_info = { .twrph1 = 40, .nr_sets = ARRAY_SIZE(at2440evb_nand_sets), .sets = at2440evb_nand_sets, - .ecc_mode = NAND_ECC_SOFT, + .engine_type = NAND_ECC_ENGINE_TYPE_SOFT, }; /* DM9000AEP 10/100 ethernet controller */ @@ -136,18 +133,26 @@ static struct platform_device at2440evb_device_eth = { }; static struct s3c24xx_mci_pdata at2440evb_mci_pdata __initdata = { - /* Intentionally left blank */ + .set_power = s3c24xx_mci_def_set_power, }; static struct gpiod_lookup_table at2440evb_mci_gpio_table = { .dev_id = "s3c2410-sdi", .table = { /* Card detect S3C2410_GPG(10) */ - GPIO_LOOKUP("GPG", 10, "cd", GPIO_ACTIVE_LOW), + GPIO_LOOKUP("GPIOG", 10, "cd", GPIO_ACTIVE_LOW), + /* bus pins */ + GPIO_LOOKUP_IDX("GPIOE", 5, "bus", 0, GPIO_ACTIVE_HIGH), + GPIO_LOOKUP_IDX("GPIOE", 6, "bus", 1, GPIO_ACTIVE_HIGH), + GPIO_LOOKUP_IDX("GPIOE", 7, "bus", 2, GPIO_ACTIVE_HIGH), + GPIO_LOOKUP_IDX("GPIOE", 8, "bus", 3, GPIO_ACTIVE_HIGH), + GPIO_LOOKUP_IDX("GPIOE", 9, "bus", 4, GPIO_ACTIVE_HIGH), + GPIO_LOOKUP_IDX("GPIOE", 10, "bus", 5, GPIO_ACTIVE_HIGH), { }, }, }; + /* 7" LCD panel */ static struct s3c2410fb_display at2440evb_lcd_cfg __initdata = { @@ -197,13 +202,13 @@ static void __init at2440evb_map_io(void) { s3c24xx_init_io(at2440evb_iodesc, ARRAY_SIZE(at2440evb_iodesc)); s3c24xx_init_uarts(at2440evb_uartcfgs, ARRAY_SIZE(at2440evb_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); + s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4); } static void __init at2440evb_init_time(void) { s3c2440_init_clocks(16934400); - samsung_timer_init(); + s3c24xx_timer_init(); } static void __init at2440evb_init(void) diff --git a/arch/arm/mach-s3c24xx/mach-bast.c b/arch/arm/mach-s3c/mach-bast.c index a7c3955ae8f6..328f5d9ae9f9 100644 --- a/arch/arm/mach-s3c24xx/mach-bast.c +++ b/arch/arm/mach-s3c/mach-bast.c @@ -40,20 +40,17 @@ #include <asm/mach/irq.h> #include <asm/mach-types.h> -#include <mach/fb.h> -#include <mach/hardware.h> -#include <mach/regs-gpio.h> -#include <mach/regs-lcd.h> -#include <mach/gpio-samsung.h> - -#include <plat/cpu.h> -#include <plat/cpu-freq.h> -#include <plat/devs.h> -#include <plat/gpio-cfg.h> -#include <plat/samsung-time.h> +#include <linux/platform_data/fb-s3c2410.h> +#include "regs-gpio.h" +#include "gpio-samsung.h" + +#include "cpu.h" +#include <linux/soc/samsung/s3c-cpu-freq.h> +#include "devs.h" +#include "gpio-cfg.h" #include "bast.h" -#include "common.h" +#include "s3c24xx.h" #include "simtec.h" #define COPYRIGHT ", Copyright 2004-2008 Simtec Electronics" @@ -294,7 +291,7 @@ static struct s3c2410_platform_nand __initdata bast_nand_info = { .nr_sets = ARRAY_SIZE(bast_nand_sets), .sets = bast_nand_sets, .select_chip = bast_nand_select, - .ecc_mode = NAND_ECC_SOFT, + .engine_type = NAND_ECC_ENGINE_TYPE_SOFT, }; /* DM9000 */ @@ -550,13 +547,13 @@ static void __init bast_map_io(void) s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc)); s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); + s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4); } static void __init bast_init_time(void) { s3c2410_init_clocks(12000000); - samsung_timer_init(); + s3c24xx_timer_init(); } static void __init bast_init(void) diff --git a/arch/arm/mach-s3c64xx/mach-crag6410-module.c b/arch/arm/mach-s3c/mach-crag6410-module.c index 34f1baa10c54..407ad493493e 100644 --- a/arch/arm/mach-s3c64xx/mach-crag6410-module.c +++ b/arch/arm/mach-s3c/mach-crag6410-module.c @@ -27,7 +27,7 @@ #include <linux/platform_data/spi-s3c64xx.h> -#include <plat/cpu.h> +#include "cpu.h" #include <mach/irqs.h> #include "crag6410.h" @@ -378,8 +378,7 @@ static const struct { .i2c_devs = wm2200_i2c, .num_i2c_devs = ARRAY_SIZE(wm2200_i2c) }, }; -static int wlf_gf_module_probe(struct i2c_client *i2c, - const struct i2c_device_id *i2c_id) +static int wlf_gf_module_probe(struct i2c_client *i2c) { int ret, i, j, id, rev; @@ -432,7 +431,7 @@ static struct i2c_driver wlf_gf_module_driver = { .driver = { .name = "wlf-gf-module" }, - .probe = wlf_gf_module_probe, + .probe_new = wlf_gf_module_probe, .id_table = wlf_gf_module_id, }; diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c/mach-crag6410.c index da9654255e3f..4a12c75d407f 100644 --- a/arch/arm/mach-s3c64xx/mach-crag6410.c +++ b/arch/arm/mach-s3c/mach-crag6410.c @@ -44,30 +44,28 @@ #include <asm/mach-types.h> #include <video/samsung_fimd.h> -#include <mach/hardware.h> -#include <mach/map.h> -#include <mach/regs-gpio.h> -#include <mach/gpio-samsung.h> +#include "map.h" +#include "regs-gpio.h" +#include "gpio-samsung.h" #include <mach/irqs.h> -#include <plat/fb.h> -#include <plat/sdhci.h> -#include <plat/gpio-cfg.h> +#include "fb.h" +#include "sdhci.h" +#include "gpio-cfg.h" #include <linux/platform_data/spi-s3c64xx.h> -#include <plat/keypad.h> -#include <plat/devs.h> -#include <plat/cpu.h> -#include <plat/adc.h> +#include "keypad.h" +#include "devs.h" +#include "cpu.h" +#include <linux/soc/samsung/s3c-adc.h> #include <linux/platform_data/i2c-s3c2410.h> -#include <plat/pm.h> -#include <plat/samsung-time.h> +#include "pm.h" -#include "common.h" +#include "s3c64xx.h" #include "crag6410.h" -#include "regs-gpio-memport.h" -#include "regs-modem.h" -#include "regs-sys.h" +#include "regs-gpio-memport-s3c64xx.h" +#include "regs-modem-s3c64xx.h" +#include "regs-sys-s3c64xx.h" /* serial port setup */ @@ -750,7 +748,7 @@ static void __init crag6410_map_io(void) s3c64xx_init_io(NULL, 0); s3c64xx_set_xtal_freq(12000000); s3c24xx_init_uarts(crag6410_uartcfgs, ARRAY_SIZE(crag6410_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); + s3c64xx_set_timer_source(S3C64XX_PWM3, S3C64XX_PWM4); /* LCD type and Bypass set by bootloader */ } @@ -877,6 +875,5 @@ MACHINE_START(WLF_CRAGG_6410, "Wolfson Cragganmore 6410") .init_irq = s3c6410_init_irq, .map_io = crag6410_map_io, .init_machine = crag6410_machine_init, - .init_time = samsung_timer_init, - .restart = s3c64xx_restart, + .init_time = s3c64xx_timer_init, MACHINE_END diff --git a/arch/arm/mach-s3c24xx/mach-gta02.c b/arch/arm/mach-s3c/mach-gta02.c index 526fd0933289..3c75c7d112ea 100644 --- a/arch/arm/mach-s3c24xx/mach-gta02.c +++ b/arch/arm/mach-s3c/mach-gta02.c @@ -57,20 +57,18 @@ #include <linux/platform_data/touchscreen-s3c2410.h> #include <linux/platform_data/usb-ohci-s3c2410.h> #include <linux/platform_data/usb-s3c2410_udc.h> +#include <linux/platform_data/fb-s3c2410.h> -#include <mach/fb.h> -#include <mach/hardware.h> -#include <mach/regs-gpio.h> -#include <mach/regs-irq.h> -#include <mach/gpio-samsung.h> +#include "regs-gpio.h" +#include "regs-irq.h" +#include "gpio-samsung.h" -#include <plat/cpu.h> -#include <plat/devs.h> -#include <plat/gpio-cfg.h> -#include <plat/pm.h> -#include <plat/samsung-time.h> +#include "cpu.h" +#include "devs.h" +#include "gpio-cfg.h" +#include "pm.h" -#include "common.h" +#include "s3c24xx.h" #include "gta02.h" static struct pcf50633 *gta02_pcf; @@ -417,7 +415,7 @@ static struct s3c2410_platform_nand __initdata gta02_nand_info = { .twrph1 = 15, .nr_sets = ARRAY_SIZE(gta02_nand_sets), .sets = gta02_nand_sets, - .ecc_mode = NAND_ECC_SOFT, + .engine_type = NAND_ECC_ENGINE_TYPE_SOFT, }; @@ -489,11 +487,25 @@ static struct platform_device gta02_audio = { .id = -1, }; +static struct gpiod_lookup_table gta02_mmc_gpio_table = { + .dev_id = "s3c2410-sdi", + .table = { + /* bus pins */ + GPIO_LOOKUP_IDX("GPIOE", 5, "bus", 0, GPIO_ACTIVE_HIGH), + GPIO_LOOKUP_IDX("GPIOE", 6, "bus", 1, GPIO_ACTIVE_HIGH), + GPIO_LOOKUP_IDX("GPIOE", 7, "bus", 2, GPIO_ACTIVE_HIGH), + GPIO_LOOKUP_IDX("GPIOE", 8, "bus", 3, GPIO_ACTIVE_HIGH), + GPIO_LOOKUP_IDX("GPIOE", 9, "bus", 4, GPIO_ACTIVE_HIGH), + GPIO_LOOKUP_IDX("GPIOE", 10, "bus", 5, GPIO_ACTIVE_HIGH), + { }, + }, +}; + static void __init gta02_map_io(void) { s3c24xx_init_io(gta02_iodesc, ARRAY_SIZE(gta02_iodesc)); s3c24xx_init_uarts(gta02_uartcfgs, ARRAY_SIZE(gta02_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); + s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4); } @@ -540,7 +552,12 @@ static void __init gta02_machine_init(void) i2c_register_board_info(0, gta02_i2c_devs, ARRAY_SIZE(gta02_i2c_devs)); + /* Configure the I2S pins (GPE0...GPE4) in correct mode */ + s3c_gpio_cfgall_range(S3C2410_GPE(0), 5, S3C_GPIO_SFN(2), + S3C_GPIO_PULL_NONE); + gpiod_add_lookup_table(>a02_audio_gpio_table); + gpiod_add_lookup_table(>a02_mmc_gpio_table); platform_add_devices(gta02_devices, ARRAY_SIZE(gta02_devices)); pm_power_off = gta02_poweroff; @@ -550,7 +567,7 @@ static void __init gta02_machine_init(void) static void __init gta02_init_time(void) { s3c2442_init_clocks(12000000); - samsung_timer_init(); + s3c24xx_timer_init(); } MACHINE_START(NEO1973_GTA02, "GTA02") diff --git a/arch/arm/mach-s3c24xx/mach-h1940.c b/arch/arm/mach-s3c/mach-h1940.c index ecb84029e15c..53d51aa83200 100644 --- a/arch/arm/mach-s3c24xx/mach-h1940.c +++ b/arch/arm/mach-s3c/mach-h1940.c @@ -47,20 +47,19 @@ #include <sound/uda1380.h> -#include <mach/fb.h> -#include <mach/hardware.h> -#include <mach/regs-clock.h> -#include <mach/regs-gpio.h> -#include <mach/regs-lcd.h> -#include <mach/gpio-samsung.h> - -#include <plat/cpu.h> -#include <plat/devs.h> -#include <plat/gpio-cfg.h> -#include <plat/pm.h> -#include <plat/samsung-time.h> - -#include "common.h" +#include <linux/platform_data/fb-s3c2410.h> +#include "map.h" +#include "hardware-s3c24xx.h" +#include "regs-clock.h" +#include "regs-gpio.h" +#include "gpio-samsung.h" + +#include "cpu.h" +#include "devs.h" +#include "gpio-cfg.h" +#include "pm.h" + +#include "s3c24xx.h" #include "h1940.h" #define H1940_LATCH ((void __force __iomem *)0xF8000000) @@ -180,9 +179,9 @@ static struct s3c2410_ts_mach_info h1940_ts_cfg __initdata = { .cfg_gpio = s3c24xx_ts_cfg_gpio, }; -/** +/* * Set lcd on or off - **/ + */ static struct s3c2410fb_display h1940_lcd __initdata = { .lcdcon5= S3C2410_LCDCON5_FRM565 | \ S3C2410_LCDCON5_INVVLINE | \ @@ -211,12 +210,16 @@ static struct s3c2410fb_mach_info h1940_fb_info __initdata = { .lpcsel = 0x02, .gpccon = 0xaa940659, .gpccon_mask = 0xffffc0f0, + .gpccon_reg = S3C2410_GPCCON, .gpcup = 0x0000ffff, .gpcup_mask = 0xffffffff, + .gpcup_reg = S3C2410_GPCUP, .gpdcon = 0xaa84aaa0, .gpdcon_mask = 0xffffffff, + .gpdcon_reg = S3C2410_GPDCON, .gpdup = 0x0000faff, .gpdup_mask = 0xffffffff, + .gpdup_reg = S3C2410_GPDUP, }; static int power_supply_init(struct device *dev) @@ -446,6 +449,8 @@ static struct platform_device h1940_device_bluetooth = { static void h1940_set_mmc_power(unsigned char power_mode, unsigned short vdd) { + s3c24xx_mci_def_set_power(power_mode, vdd); + switch (power_mode) { case MMC_POWER_OFF: gpio_set_value(H1940_LATCH_SD_POWER, 0); @@ -468,9 +473,16 @@ static struct gpiod_lookup_table h1940_mmc_gpio_table = { .dev_id = "s3c2410-sdi", .table = { /* Card detect S3C2410_GPF(5) */ - GPIO_LOOKUP("GPF", 5, "cd", GPIO_ACTIVE_LOW), + GPIO_LOOKUP("GPIOF", 5, "cd", GPIO_ACTIVE_LOW), /* Write protect S3C2410_GPH(8) */ - GPIO_LOOKUP("GPH", 8, "wp", GPIO_ACTIVE_LOW), + GPIO_LOOKUP("GPIOH", 8, "wp", GPIO_ACTIVE_LOW), + /* bus pins */ + GPIO_LOOKUP_IDX("GPIOE", 5, "bus", 0, GPIO_ACTIVE_HIGH), + GPIO_LOOKUP_IDX("GPIOE", 6, "bus", 1, GPIO_ACTIVE_HIGH), + GPIO_LOOKUP_IDX("GPIOE", 7, "bus", 2, GPIO_ACTIVE_HIGH), + GPIO_LOOKUP_IDX("GPIOE", 8, "bus", 3, GPIO_ACTIVE_HIGH), + GPIO_LOOKUP_IDX("GPIOE", 9, "bus", 4, GPIO_ACTIVE_HIGH), + GPIO_LOOKUP_IDX("GPIOE", 10, "bus", 5, GPIO_ACTIVE_HIGH), { }, }, }; @@ -674,7 +686,7 @@ static void __init h1940_map_io(void) { s3c24xx_init_io(h1940_iodesc, ARRAY_SIZE(h1940_iodesc)); s3c24xx_init_uarts(h1940_uartcfgs, ARRAY_SIZE(h1940_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); + s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4); /* setup PM */ @@ -691,7 +703,7 @@ static void __init h1940_map_io(void) static void __init h1940_init_time(void) { s3c2410_init_clocks(12000000); - samsung_timer_init(); + s3c24xx_timer_init(); } /* H1940 and RX3715 need to reserve this for suspend */ @@ -708,6 +720,9 @@ static void __init h1940_init(void) s3c24xx_fb_set_platdata(&h1940_fb_info); gpiod_add_lookup_table(&h1940_mmc_gpio_table); gpiod_add_lookup_table(&h1940_audio_gpio_table); + /* Configure the I2S pins (GPE0...GPE4) in correct mode */ + s3c_gpio_cfgall_range(S3C2410_GPE(0), 5, S3C_GPIO_SFN(2), + S3C_GPIO_PULL_NONE); s3c24xx_mci_set_platdata(&h1940_mmc_cfg); s3c24xx_udc_set_platdata(&h1940_udc_cfg); s3c24xx_ts_set_platdata(&h1940_ts_cfg); diff --git a/arch/arm/mach-s3c64xx/mach-hmt.c b/arch/arm/mach-s3c/mach-hmt.c index e7080215c624..b287e9987311 100644 --- a/arch/arm/mach-s3c64xx/mach-hmt.c +++ b/arch/arm/mach-s3c/mach-hmt.c @@ -25,23 +25,21 @@ #include <asm/mach/irq.h> #include <video/samsung_fimd.h> -#include <mach/hardware.h> -#include <mach/map.h> +#include "map.h" #include <mach/irqs.h> #include <asm/irq.h> #include <asm/mach-types.h> #include <linux/platform_data/i2c-s3c2410.h> -#include <mach/gpio-samsung.h> -#include <plat/fb.h> +#include "gpio-samsung.h" +#include "fb.h" #include <linux/platform_data/mtd-nand-s3c2410.h> -#include <plat/devs.h> -#include <plat/cpu.h> -#include <plat/samsung-time.h> +#include "devs.h" +#include "cpu.h" -#include "common.h" +#include "s3c64xx.h" #define UCON S3C2410_UCON_DEFAULT #define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE) @@ -199,7 +197,7 @@ static struct s3c2410_platform_nand hmt_nand_info = { .twrph1 = 40, .nr_sets = ARRAY_SIZE(hmt_nand_sets), .sets = hmt_nand_sets, - .ecc_mode = NAND_ECC_SOFT, + .engine_type = NAND_ECC_ENGINE_TYPE_SOFT, }; static struct gpio_led hmt_leds[] = { @@ -251,7 +249,7 @@ static void __init hmt_map_io(void) s3c64xx_init_io(hmt_iodesc, ARRAY_SIZE(hmt_iodesc)); s3c64xx_set_xtal_freq(12000000); s3c24xx_init_uarts(hmt_uartcfgs, ARRAY_SIZE(hmt_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); + s3c64xx_set_timer_source(S3C64XX_PWM3, S3C64XX_PWM4); } static void __init hmt_machine_init(void) @@ -280,6 +278,5 @@ MACHINE_START(HMT, "Airgoo-HMT") .init_irq = s3c6410_init_irq, .map_io = hmt_map_io, .init_machine = hmt_machine_init, - .init_time = samsung_timer_init, - .restart = s3c64xx_restart, + .init_time = s3c64xx_timer_init, MACHINE_END diff --git a/arch/arm/mach-s3c24xx/mach-jive.c b/arch/arm/mach-s3c/mach-jive.c index 885e8f12e4b9..2a29c3eca559 100644 --- a/arch/arm/mach-s3c24xx/mach-jive.c +++ b/arch/arm/mach-s3c/mach-jive.c @@ -31,10 +31,10 @@ #include <linux/platform_data/mtd-nand-s3c2410.h> #include <linux/platform_data/i2c-s3c2410.h> -#include <mach/regs-gpio.h> -#include <mach/regs-lcd.h> -#include <mach/fb.h> -#include <mach/gpio-samsung.h> +#include "hardware-s3c24xx.h" +#include "regs-gpio.h" +#include <linux/platform_data/fb-s3c2410.h> +#include "gpio-samsung.h" #include <asm/mach-types.h> @@ -43,14 +43,13 @@ #include <linux/mtd/nand_ecc.h> #include <linux/mtd/partitions.h> -#include <plat/gpio-cfg.h> -#include <plat/devs.h> -#include <plat/cpu.h> -#include <plat/pm.h> +#include "gpio-cfg.h" +#include "devs.h" +#include "cpu.h" +#include "pm.h" #include <linux/platform_data/usb-s3c2410_udc.h> -#include <plat/samsung-time.h> -#include "common.h" +#include "s3c24xx.h" #include "s3c2412-power.h" static struct map_desc jive_iodesc[] __initdata = { @@ -228,7 +227,7 @@ static struct s3c2410_platform_nand __initdata jive_nand_info = { .twrph1 = 40, .sets = jive_nand_sets, .nr_sets = ARRAY_SIZE(jive_nand_sets), - .ecc_mode = NAND_ECC_SOFT, + .engine_type = NAND_ECC_ENGINE_TYPE_SOFT, }; static int __init jive_mtdset(char *options) @@ -321,6 +320,7 @@ static struct s3c2410fb_mach_info jive_lcd_config = { * data. */ .gpcup = (0xf << 1) | (0x3f << 10), + .gpcup_reg = S3C2410_GPCUP, .gpccon = (S3C2410_GPC1_VCLK | S3C2410_GPC2_VLINE | S3C2410_GPC3_VFRAME | S3C2410_GPC4_VM | @@ -334,8 +334,12 @@ static struct s3c2410fb_mach_info jive_lcd_config = { S3C2410_GPCCON_MASK(12) | S3C2410_GPCCON_MASK(13) | S3C2410_GPCCON_MASK(14) | S3C2410_GPCCON_MASK(15)), + .gpccon_reg = S3C2410_GPCCON, + .gpdup = (0x3f << 2) | (0x3f << 10), + .gpdup_reg = S3C2410_GPDUP, + .gpdcon = (S3C2410_GPD2_VD10 | S3C2410_GPD3_VD11 | S3C2410_GPD4_VD12 | S3C2410_GPD5_VD13 | S3C2410_GPD6_VD14 | S3C2410_GPD7_VD15 | @@ -349,6 +353,8 @@ static struct s3c2410fb_mach_info jive_lcd_config = { S3C2410_GPDCON_MASK(10) | S3C2410_GPDCON_MASK(11)| S3C2410_GPDCON_MASK(12) | S3C2410_GPDCON_MASK(13)| S3C2410_GPDCON_MASK(14) | S3C2410_GPDCON_MASK(15)), + + .gpdcon_reg = S3C2410_GPDCON, }; /* ILI9320 support. */ @@ -523,13 +529,13 @@ static void __init jive_map_io(void) { s3c24xx_init_io(jive_iodesc, ARRAY_SIZE(jive_iodesc)); s3c24xx_init_uarts(jive_uartcfgs, ARRAY_SIZE(jive_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); + s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4); } static void __init jive_init_time(void) { s3c2412_init_clocks(12000000); - samsung_timer_init(); + s3c24xx_timer_init(); } static void jive_power_off(void) diff --git a/arch/arm/mach-s3c24xx/mach-mini2440.c b/arch/arm/mach-s3c/mach-mini2440.c index 235749448311..dc22ab839b95 100644 --- a/arch/arm/mach-s3c24xx/mach-mini2440.c +++ b/arch/arm/mach-s3c/mach-mini2440.c @@ -30,15 +30,13 @@ #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <mach/hardware.h> -#include <mach/fb.h> +#include <linux/platform_data/fb-s3c2410.h> #include <asm/mach-types.h> -#include <mach/regs-gpio.h> +#include "regs-gpio.h" #include <linux/platform_data/leds-s3c24xx.h> -#include <mach/regs-lcd.h> #include <mach/irqs.h> -#include <mach/gpio-samsung.h> +#include "gpio-samsung.h" #include <linux/platform_data/mtd-nand-s3c2410.h> #include <linux/platform_data/i2c-s3c2410.h> #include <linux/platform_data/mmc-s3cmci.h> @@ -49,14 +47,13 @@ #include <linux/mtd/nand_ecc.h> #include <linux/mtd/partitions.h> -#include <plat/gpio-cfg.h> -#include <plat/devs.h> -#include <plat/cpu.h> -#include <plat/samsung-time.h> +#include "gpio-cfg.h" +#include "devs.h" +#include "cpu.h" #include <sound/s3c24xx_uda134x.h> -#include "common.h" +#include "s3c24xx.h" #define MACH_MINI2440_DM9K_BASE (S3C2410_CS4 + 0x300) @@ -215,6 +212,9 @@ static struct s3c2410fb_mach_info mini2440_fb_info __initdata = { S3C2410_GPCCON_MASK(12) | S3C2410_GPCCON_MASK(13) | S3C2410_GPCCON_MASK(14) | S3C2410_GPCCON_MASK(15)), + .gpccon_reg = S3C2410_GPCCON, + .gpcup_reg = S3C2410_GPCUP, + .gpdup = (0x3f << 2) | (0x3f << 10), .gpdcon = (S3C2410_GPD2_VD10 | S3C2410_GPD3_VD11 | @@ -230,13 +230,16 @@ static struct s3c2410fb_mach_info mini2440_fb_info __initdata = { S3C2410_GPDCON_MASK(10) | S3C2410_GPDCON_MASK(11)| S3C2410_GPDCON_MASK(12) | S3C2410_GPDCON_MASK(13)| S3C2410_GPDCON_MASK(14) | S3C2410_GPDCON_MASK(15)), + + .gpdcon_reg = S3C2410_GPDCON, + .gpdup_reg = S3C2410_GPDUP, }; /* MMC/SD */ static struct s3c24xx_mci_pdata mini2440_mmc_cfg __initdata = { .wprotect_invert = 1, - .set_power = NULL, + .set_power = s3c24xx_mci_def_set_power, .ocr_avail = MMC_VDD_32_33|MMC_VDD_33_34, }; @@ -244,9 +247,16 @@ static struct gpiod_lookup_table mini2440_mmc_gpio_table = { .dev_id = "s3c2410-sdi", .table = { /* Card detect S3C2410_GPG(8) */ - GPIO_LOOKUP("GPG", 8, "cd", GPIO_ACTIVE_LOW), + GPIO_LOOKUP("GPIOG", 8, "cd", GPIO_ACTIVE_LOW), /* Write protect S3C2410_GPH(8) */ - GPIO_LOOKUP("GPH", 8, "wp", GPIO_ACTIVE_HIGH), + GPIO_LOOKUP("GPIOH", 8, "wp", GPIO_ACTIVE_HIGH), + /* bus pins */ + GPIO_LOOKUP_IDX("GPIOE", 5, "bus", 0, GPIO_ACTIVE_HIGH), + GPIO_LOOKUP_IDX("GPIOE", 6, "bus", 1, GPIO_ACTIVE_HIGH), + GPIO_LOOKUP_IDX("GPIOE", 7, "bus", 2, GPIO_ACTIVE_HIGH), + GPIO_LOOKUP_IDX("GPIOE", 8, "bus", 3, GPIO_ACTIVE_HIGH), + GPIO_LOOKUP_IDX("GPIOE", 9, "bus", 4, GPIO_ACTIVE_HIGH), + GPIO_LOOKUP_IDX("GPIOE", 10, "bus", 5, GPIO_ACTIVE_HIGH), { }, }, }; @@ -296,7 +306,7 @@ static struct s3c2410_platform_nand mini2440_nand_info __initdata = { .nr_sets = ARRAY_SIZE(mini2440_nand_sets), .sets = mini2440_nand_sets, .ignore_unset_ecc = 1, - .ecc_mode = NAND_ECC_HW, + .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST, }; /* DM9000AEP 10/100 ethernet controller */ @@ -587,13 +597,13 @@ static void __init mini2440_map_io(void) { s3c24xx_init_io(mini2440_iodesc, ARRAY_SIZE(mini2440_iodesc)); s3c24xx_init_uarts(mini2440_uartcfgs, ARRAY_SIZE(mini2440_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); + s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4); } static void __init mini2440_init_time(void) { s3c2440_init_clocks(12000000); - samsung_timer_init(); + s3c24xx_timer_init(); } /* @@ -716,6 +726,11 @@ static void __init mini2440_init(void) s3c_gpio_setpull(mini2440_buttons[i].gpio, S3C_GPIO_PULL_UP); s3c_gpio_cfgpin(mini2440_buttons[i].gpio, S3C2410_GPIO_INPUT); } + + /* Configure the I2S pins (GPE0...GPE4) in correct mode */ + s3c_gpio_cfgall_range(S3C2410_GPE(0), 5, S3C_GPIO_SFN(2), + S3C_GPIO_PULL_NONE); + if (features.lcd_index != -1) { int li; diff --git a/arch/arm/mach-s3c64xx/mach-mini6410.c b/arch/arm/mach-s3c/mach-mini6410.c index 0dd36ae49e6a..741fa1f09694 100644 --- a/arch/arm/mach-s3c64xx/mach-mini6410.c +++ b/arch/arm/mach-s3c/mach-mini6410.c @@ -23,27 +23,26 @@ #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <mach/map.h> -#include <mach/regs-gpio.h> -#include <mach/gpio-samsung.h> - -#include <plat/adc.h> -#include <plat/cpu.h> -#include <plat/devs.h> -#include <plat/fb.h> +#include "map.h" +#include "regs-gpio.h" +#include "gpio-samsung.h" + +#include <linux/soc/samsung/s3c-adc.h> +#include "cpu.h" +#include "devs.h" +#include "fb.h" #include <linux/platform_data/mtd-nand-s3c2410.h> #include <linux/platform_data/mmc-sdhci-s3c.h> -#include <plat/sdhci.h> +#include "sdhci.h" #include <linux/platform_data/touchscreen-s3c2410.h> #include <mach/irqs.h> #include <video/platform_lcd.h> #include <video/samsung_fimd.h> -#include <plat/samsung-time.h> -#include "common.h" -#include "regs-modem.h" -#include "regs-srom.h" +#include "s3c64xx.h" +#include "regs-modem-s3c64xx.h" +#include "regs-srom-s3c64xx.h" #define UCON S3C2410_UCON_DEFAULT #define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB) @@ -136,7 +135,7 @@ static struct s3c2410_platform_nand mini6410_nand_info = { .twrph1 = 40, .nr_sets = ARRAY_SIZE(mini6410_nand_sets), .sets = mini6410_nand_sets, - .ecc_mode = NAND_ECC_SOFT, + .engine_type = NAND_ECC_ENGINE_TYPE_SOFT, }; static struct s3c_fb_pd_win mini6410_lcd_type0_fb_win = { @@ -238,7 +237,7 @@ static void __init mini6410_map_io(void) s3c64xx_init_io(NULL, 0); s3c64xx_set_xtal_freq(12000000); s3c24xx_init_uarts(mini6410_uartcfgs, ARRAY_SIZE(mini6410_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); + s3c64xx_set_timer_source(S3C64XX_PWM3, S3C64XX_PWM4); /* set the LCD type */ tmp = __raw_readl(S3C64XX_SPCON); @@ -362,6 +361,5 @@ MACHINE_START(MINI6410, "MINI6410") .init_irq = s3c6410_init_irq, .map_io = mini6410_map_io, .init_machine = mini6410_machine_init, - .init_time = samsung_timer_init, - .restart = s3c64xx_restart, + .init_time = s3c64xx_timer_init, MACHINE_END diff --git a/arch/arm/mach-s3c24xx/mach-n30.c b/arch/arm/mach-s3c/mach-n30.c index 998ccff3c174..e40c1fcf418c 100644 --- a/arch/arm/mach-s3c24xx/mach-n30.c +++ b/arch/arm/mach-s3c/mach-n30.c @@ -27,15 +27,15 @@ #include <linux/io.h> #include <linux/mmc/host.h> -#include <mach/hardware.h> +#include "hardware-s3c24xx.h" #include <asm/irq.h> #include <asm/mach-types.h> -#include <mach/fb.h> +#include <linux/platform_data/fb-s3c2410.h> #include <linux/platform_data/leds-s3c24xx.h> -#include <mach/regs-gpio.h> -#include <mach/regs-lcd.h> -#include <mach/gpio-samsung.h> +#include "regs-gpio.h" +#include "gpio-samsung.h" +#include "gpio-cfg.h" #include <asm/mach/arch.h> #include <asm/mach/irq.h> @@ -43,14 +43,12 @@ #include <linux/platform_data/i2c-s3c2410.h> -#include <plat/cpu.h> -#include <plat/devs.h> -#include <plat/gpio-cfg.h> +#include "cpu.h" +#include "devs.h" #include <linux/platform_data/mmc-s3cmci.h> #include <linux/platform_data/usb-s3c2410_udc.h> -#include <plat/samsung-time.h> -#include "common.h" +#include "s3c24xx.h" static struct map_desc n30_iodesc[] __initdata = { /* nothing here yet */ @@ -368,6 +366,8 @@ static struct s3c2410fb_mach_info n30_fb_info __initdata = { static void n30_sdi_set_power(unsigned char power_mode, unsigned short vdd) { + s3c24xx_mci_def_set_power(power_mode, vdd); + switch (power_mode) { case MMC_POWER_ON: case MMC_POWER_UP: @@ -389,10 +389,17 @@ static struct gpiod_lookup_table n30_mci_gpio_table = { .dev_id = "s3c2410-sdi", .table = { /* Card detect S3C2410_GPF(1) */ - GPIO_LOOKUP("GPF", 1, "cd", GPIO_ACTIVE_LOW), + GPIO_LOOKUP("GPIOF", 1, "cd", GPIO_ACTIVE_LOW), /* Write protect S3C2410_GPG(10) */ - GPIO_LOOKUP("GPG", 10, "wp", GPIO_ACTIVE_LOW), + GPIO_LOOKUP("GPIOG", 10, "wp", GPIO_ACTIVE_LOW), { }, + /* bus pins */ + GPIO_LOOKUP_IDX("GPIOE", 5, "bus", 0, GPIO_ACTIVE_HIGH), + GPIO_LOOKUP_IDX("GPIOE", 6, "bus", 1, GPIO_ACTIVE_HIGH), + GPIO_LOOKUP_IDX("GPIOE", 7, "bus", 2, GPIO_ACTIVE_HIGH), + GPIO_LOOKUP_IDX("GPIOE", 8, "bus", 3, GPIO_ACTIVE_HIGH), + GPIO_LOOKUP_IDX("GPIOE", 9, "bus", 4, GPIO_ACTIVE_HIGH), + GPIO_LOOKUP_IDX("GPIOE", 10, "bus", 5, GPIO_ACTIVE_HIGH), }, }; @@ -572,13 +579,13 @@ static void __init n30_map_io(void) s3c24xx_init_io(n30_iodesc, ARRAY_SIZE(n30_iodesc)); n30_hwinit(); s3c24xx_init_uarts(n30_uartcfgs, ARRAY_SIZE(n30_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); + s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4); } static void __init n30_init_time(void) { s3c2410_init_clocks(12000000); - samsung_timer_init(); + s3c24xx_timer_init(); } /* GPB3 is the line that controls the pull-up for the USB D+ line */ @@ -600,6 +607,10 @@ static void __init n30_init(void) S3C2410_MISCCR_USBSUSPND0 | S3C2410_MISCCR_USBSUSPND1, 0x0); + /* Configure the I2S pins (GPE0...GPE4) in correct mode */ + s3c_gpio_cfgall_range(S3C2410_GPE(0), 5, S3C_GPIO_SFN(2), + S3C_GPIO_PULL_NONE); + if (machine_is_n30()) { /* Turn off suspend on both USB ports, and switch the * selectable USB port to USB device mode. */ diff --git a/arch/arm/mach-s3c64xx/mach-ncp.c b/arch/arm/mach-s3c/mach-ncp.c index 13fea5c86ca3..1a45bed56622 100644 --- a/arch/arm/mach-s3c64xx/mach-ncp.c +++ b/arch/arm/mach-s3c/mach-ncp.c @@ -25,20 +25,18 @@ #include <asm/mach/irq.h> #include <mach/irqs.h> -#include <mach/hardware.h> -#include <mach/map.h> +#include "map.h" #include <asm/irq.h> #include <asm/mach-types.h> #include <linux/platform_data/i2c-s3c2410.h> -#include <plat/fb.h> +#include "fb.h" -#include <plat/devs.h> -#include <plat/cpu.h> -#include <plat/samsung-time.h> +#include "devs.h" +#include "cpu.h" -#include "common.h" +#include "s3c64xx.h" #define UCON S3C2410_UCON_DEFAULT #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE @@ -81,7 +79,7 @@ static void __init ncp_map_io(void) s3c64xx_init_io(ncp_iodesc, ARRAY_SIZE(ncp_iodesc)); s3c64xx_set_xtal_freq(12000000); s3c24xx_init_uarts(ncp_uartcfgs, ARRAY_SIZE(ncp_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); + s3c64xx_set_timer_source(S3C64XX_PWM3, S3C64XX_PWM4); } static void __init ncp_machine_init(void) @@ -98,6 +96,5 @@ MACHINE_START(NCP, "NCP") .init_irq = s3c6410_init_irq, .map_io = ncp_map_io, .init_machine = ncp_machine_init, - .init_time = samsung_timer_init, - .restart = s3c64xx_restart, + .init_time = s3c64xx_timer_init, MACHINE_END diff --git a/arch/arm/mach-s3c24xx/mach-nexcoder.c b/arch/arm/mach-s3c/mach-nexcoder.c index c2f34758ccb6..2a454c919658 100644 --- a/arch/arm/mach-s3c24xx/mach-nexcoder.c +++ b/arch/arm/mach-s3c/mach-nexcoder.c @@ -28,21 +28,19 @@ #include <asm/mach/irq.h> #include <asm/setup.h> -#include <mach/hardware.h> #include <asm/irq.h> #include <asm/mach-types.h> //#include <asm/debug-ll.h> -#include <mach/regs-gpio.h> -#include <mach/gpio-samsung.h> +#include "regs-gpio.h" +#include "gpio-samsung.h" #include <linux/platform_data/i2c-s3c2410.h> -#include <plat/gpio-cfg.h> -#include <plat/devs.h> -#include <plat/cpu.h> -#include <plat/samsung-time.h> +#include "gpio-cfg.h" +#include "devs.h" +#include "cpu.h" -#include "common.h" +#include "s3c24xx.h" static struct map_desc nexcoder_iodesc[] __initdata = { /* nothing here yet */ @@ -131,7 +129,7 @@ static void __init nexcoder_map_io(void) { s3c24xx_init_io(nexcoder_iodesc, ARRAY_SIZE(nexcoder_iodesc)); s3c24xx_init_uarts(nexcoder_uartcfgs, ARRAY_SIZE(nexcoder_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); + s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4); nexcoder_sensorboard_init(); } @@ -139,12 +137,17 @@ static void __init nexcoder_map_io(void) static void __init nexcoder_init_time(void) { s3c2440_init_clocks(12000000); - samsung_timer_init(); + s3c24xx_timer_init(); } static void __init nexcoder_init(void) { s3c_i2c0_set_platdata(NULL); + + /* Configure the I2S pins (GPE0...GPE4) in correct mode */ + s3c_gpio_cfgall_range(S3C2410_GPE(0), 5, S3C_GPIO_SFN(2), + S3C_GPIO_PULL_NONE); + platform_add_devices(nexcoder_devices, ARRAY_SIZE(nexcoder_devices)); }; diff --git a/arch/arm/mach-s3c24xx/mach-osiris-dvs.c b/arch/arm/mach-s3c/mach-osiris-dvs.c index 5d819b6ea428..2e283aedab65 100644 --- a/arch/arm/mach-s3c24xx/mach-osiris-dvs.c +++ b/arch/arm/mach-s3c/mach-osiris-dvs.c @@ -14,8 +14,8 @@ #include <linux/mfd/tps65010.h> -#include <plat/cpu-freq.h> -#include <mach/gpio-samsung.h> +#include <linux/soc/samsung/s3c-cpu-freq.h> +#include "gpio-samsung.h" #define OSIRIS_GPIO_DVS S3C2410_GPB(5) diff --git a/arch/arm/mach-s3c24xx/mach-osiris.c b/arch/arm/mach-s3c/mach-osiris.c index ee3630cb236a..81744ca67d1d 100644 --- a/arch/arm/mach-s3c24xx/mach-osiris.c +++ b/arch/arm/mach-s3c/mach-osiris.c @@ -36,20 +36,17 @@ #include <linux/mtd/nand_ecc.h> #include <linux/mtd/partitions.h> -#include <plat/cpu.h> -#include <plat/cpu-freq.h> -#include <plat/devs.h> -#include <plat/gpio-cfg.h> -#include <plat/samsung-time.h> - -#include <mach/hardware.h> -#include <mach/regs-gpio.h> -#include <mach/regs-lcd.h> -#include <mach/gpio-samsung.h> - -#include "common.h" +#include "cpu.h" +#include <linux/soc/samsung/s3c-cpu-freq.h> +#include "devs.h" +#include "gpio-cfg.h" + +#include "regs-gpio.h" +#include "gpio-samsung.h" + +#include "s3c24xx.h" #include "osiris.h" -#include "regs-mem.h" +#include "regs-mem-s3c24xx.h" /* onboard perihperal map */ @@ -234,7 +231,7 @@ static struct s3c2410_platform_nand __initdata osiris_nand_info = { .nr_sets = ARRAY_SIZE(osiris_nand_sets), .sets = osiris_nand_sets, .select_chip = osiris_nand_select, - .ecc_mode = NAND_ECC_SOFT, + .engine_type = NAND_ECC_ENGINE_TYPE_SOFT, }; /* PCMCIA control and configuration */ @@ -359,7 +356,7 @@ static void __init osiris_map_io(void) s3c24xx_init_io(osiris_iodesc, ARRAY_SIZE(osiris_iodesc)); s3c24xx_init_uarts(osiris_uartcfgs, ARRAY_SIZE(osiris_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); + s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4); /* check for the newer revision boards with large page nand */ @@ -384,7 +381,7 @@ static void __init osiris_map_io(void) static void __init osiris_init_time(void) { s3c2440_init_clocks(12000000); - samsung_timer_init(); + s3c24xx_timer_init(); } static void __init osiris_init(void) diff --git a/arch/arm/mach-s3c24xx/mach-otom.c b/arch/arm/mach-s3c/mach-otom.c index 4e24d89e870b..460ee97766cd 100644 --- a/arch/arm/mach-s3c24xx/mach-otom.c +++ b/arch/arm/mach-s3c/mach-otom.c @@ -22,14 +22,13 @@ #include <asm/mach/map.h> #include <asm/mach/irq.h> -#include <mach/hardware.h> -#include <mach/regs-gpio.h> +#include "gpio-samsung.h" +#include "gpio-cfg.h" -#include <plat/cpu.h> -#include <plat/devs.h> -#include <plat/samsung-time.h> +#include "cpu.h" +#include "devs.h" -#include "common.h" +#include "s3c24xx.h" #include "otom.h" static struct map_desc otom11_iodesc[] __initdata = { @@ -95,18 +94,22 @@ static void __init otom11_map_io(void) { s3c24xx_init_io(otom11_iodesc, ARRAY_SIZE(otom11_iodesc)); s3c24xx_init_uarts(otom11_uartcfgs, ARRAY_SIZE(otom11_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); + s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4); } static void __init otom11_init_time(void) { s3c2410_init_clocks(12000000); - samsung_timer_init(); + s3c24xx_timer_init(); } static void __init otom11_init(void) { s3c_i2c0_set_platdata(NULL); + + /* Configure the I2S pins (GPE0...GPE4) in correct mode */ + s3c_gpio_cfgall_range(S3C2410_GPE(0), 5, S3C_GPIO_SFN(2), + S3C_GPIO_PULL_NONE); platform_add_devices(otom11_devices, ARRAY_SIZE(otom11_devices)); } diff --git a/arch/arm/mach-s3c24xx/mach-qt2410.c b/arch/arm/mach-s3c/mach-qt2410.c index ff9e3197309b..151e8e373d40 100644 --- a/arch/arm/mach-s3c24xx/mach-qt2410.c +++ b/arch/arm/mach-s3c/mach-qt2410.c @@ -28,26 +28,23 @@ #include <asm/mach/map.h> #include <asm/mach/irq.h> -#include <mach/hardware.h> #include <asm/irq.h> #include <asm/mach-types.h> #include <linux/platform_data/leds-s3c24xx.h> -#include <mach/regs-lcd.h> -#include <mach/fb.h> +#include <linux/platform_data/fb-s3c2410.h> #include <linux/platform_data/mtd-nand-s3c2410.h> #include <linux/platform_data/usb-s3c2410_udc.h> #include <linux/platform_data/i2c-s3c2410.h> -#include <mach/gpio-samsung.h> +#include "gpio-samsung.h" -#include <plat/gpio-cfg.h> -#include <plat/devs.h> -#include <plat/cpu.h> -#include <plat/pm.h> -#include <plat/samsung-time.h> +#include "gpio-cfg.h" +#include "devs.h" +#include "cpu.h" +#include "pm.h" -#include "common.h" -#include "common-smdk.h" +#include "s3c24xx.h" +#include "common-smdk-s3c24xx.h" static struct map_desc qt2410_iodesc[] __initdata = { { 0xe0000000, __phys_to_pfn(S3C2410_CS3+0x01000000), SZ_1M, MT_DEVICE } @@ -225,6 +222,20 @@ static struct gpiod_lookup_table qt2410_spi_gpiod_table = { }, }; +static struct gpiod_lookup_table qt2410_mmc_gpiod_table = { + .dev_id = "s3c2410-sdi", + .table = { + /* bus pins */ + GPIO_LOOKUP_IDX("GPIOE", 5, "bus", 0, GPIO_ACTIVE_HIGH), + GPIO_LOOKUP_IDX("GPIOE", 6, "bus", 1, GPIO_ACTIVE_HIGH), + GPIO_LOOKUP_IDX("GPIOE", 7, "bus", 2, GPIO_ACTIVE_HIGH), + GPIO_LOOKUP_IDX("GPIOE", 8, "bus", 3, GPIO_ACTIVE_HIGH), + GPIO_LOOKUP_IDX("GPIOE", 9, "bus", 4, GPIO_ACTIVE_HIGH), + GPIO_LOOKUP_IDX("GPIOE", 10, "bus", 5, GPIO_ACTIVE_HIGH), + { }, + }, +}; + /* Board devices */ static struct platform_device *qt2410_devices[] __initdata = { @@ -287,7 +298,7 @@ static struct s3c2410_platform_nand __initdata qt2410_nand_info = { .twrph1 = 20, .nr_sets = ARRAY_SIZE(qt2410_nand_sets), .sets = qt2410_nand_sets, - .ecc_mode = NAND_ECC_SOFT, + .engine_type = NAND_ECC_ENGINE_TYPE_SOFT, }; /* UDC */ @@ -309,13 +320,13 @@ static void __init qt2410_map_io(void) { s3c24xx_init_io(qt2410_iodesc, ARRAY_SIZE(qt2410_iodesc)); s3c24xx_init_uarts(smdk2410_uartcfgs, ARRAY_SIZE(smdk2410_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); + s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4); } static void __init qt2410_init_time(void) { s3c2410_init_clocks(12000000); - samsung_timer_init(); + s3c24xx_timer_init(); } static void __init qt2410_machine_init(void) @@ -343,9 +354,13 @@ static void __init qt2410_machine_init(void) s3c24xx_udc_set_platdata(&qt2410_udc_cfg); s3c_i2c0_set_platdata(NULL); + /* Configure the I2S pins (GPE0...GPE4) in correct mode */ + s3c_gpio_cfgall_range(S3C2410_GPE(0), 5, S3C_GPIO_SFN(2), + S3C_GPIO_PULL_NONE); gpiod_add_lookup_table(&qt2410_spi_gpiod_table); s3c_gpio_setpull(S3C2410_GPB(0), S3C_GPIO_PULL_NONE); gpiod_add_lookup_table(&qt2410_led_gpio_table); + gpiod_add_lookup_table(&qt2410_mmc_gpiod_table); platform_add_devices(qt2410_devices, ARRAY_SIZE(qt2410_devices)); s3c_pm_init(); } diff --git a/arch/arm/mach-s3c64xx/mach-real6410.c b/arch/arm/mach-s3c/mach-real6410.c index 0ff88b6859c4..9d218a53d631 100644 --- a/arch/arm/mach-s3c64xx/mach-real6410.c +++ b/arch/arm/mach-s3c/mach-real6410.c @@ -24,25 +24,24 @@ #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <mach/map.h> -#include <mach/regs-gpio.h> -#include <mach/gpio-samsung.h> +#include "map.h" +#include "regs-gpio.h" +#include "gpio-samsung.h" #include <mach/irqs.h> -#include <plat/adc.h> -#include <plat/cpu.h> -#include <plat/devs.h> -#include <plat/fb.h> +#include <linux/soc/samsung/s3c-adc.h> +#include "cpu.h" +#include "devs.h" +#include "fb.h" #include <linux/platform_data/mtd-nand-s3c2410.h> #include <linux/platform_data/touchscreen-s3c2410.h> #include <video/platform_lcd.h> #include <video/samsung_fimd.h> -#include <plat/samsung-time.h> -#include "common.h" -#include "regs-modem.h" -#include "regs-srom.h" +#include "s3c64xx.h" +#include "regs-modem-s3c64xx.h" +#include "regs-srom-s3c64xx.h" #define UCON S3C2410_UCON_DEFAULT #define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB) @@ -188,7 +187,7 @@ static struct s3c2410_platform_nand real6410_nand_info = { .twrph1 = 40, .nr_sets = ARRAY_SIZE(real6410_nand_sets), .sets = real6410_nand_sets, - .ecc_mode = NAND_ECC_SOFT, + .engine_type = NAND_ECC_ENGINE_TYPE_SOFT, }; static struct platform_device *real6410_devices[] __initdata = { @@ -208,7 +207,7 @@ static void __init real6410_map_io(void) s3c64xx_init_io(NULL, 0); s3c24xx_init_clocks(12000000); s3c24xx_init_uarts(real6410_uartcfgs, ARRAY_SIZE(real6410_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); + s3c64xx_set_timer_source(S3C64XX_PWM3, S3C64XX_PWM4); /* set the LCD type */ tmp = __raw_readl(S3C64XX_SPCON); @@ -330,6 +329,5 @@ MACHINE_START(REAL6410, "REAL6410") .init_irq = s3c6410_init_irq, .map_io = real6410_map_io, .init_machine = real6410_machine_init, - .init_time = samsung_timer_init, - .restart = s3c64xx_restart, + .init_time = s3c64xx_timer_init, MACHINE_END diff --git a/arch/arm/mach-s3c24xx/mach-rx1950.c b/arch/arm/mach-s3c/mach-rx1950.c index e9806bf654b4..b9758f0a9a14 100644 --- a/arch/arm/mach-s3c24xx/mach-rx1950.c +++ b/arch/arm/mach-s3c/mach-rx1950.c @@ -42,21 +42,20 @@ #include <linux/platform_data/mtd-nand-s3c2410.h> #include <linux/platform_data/touchscreen-s3c2410.h> #include <linux/platform_data/usb-s3c2410_udc.h> +#include <linux/platform_data/fb-s3c2410.h> #include <sound/uda1380.h> -#include <mach/fb.h> -#include <mach/regs-gpio.h> -#include <mach/regs-lcd.h> -#include <mach/gpio-samsung.h> +#include "hardware-s3c24xx.h" +#include "regs-gpio.h" +#include "gpio-samsung.h" -#include <plat/cpu.h> -#include <plat/devs.h> -#include <plat/pm.h> -#include <plat/samsung-time.h> -#include <plat/gpio-cfg.h> +#include "cpu.h" +#include "devs.h" +#include "pm.h" +#include "gpio-cfg.h" -#include "common.h" +#include "s3c24xx.h" #include "h1940.h" #define LCD_PWM_PERIOD 192960 @@ -361,14 +360,17 @@ static struct s3c2410fb_mach_info rx1950_lcd_cfg = { .lpcsel = 0x02, .gpccon = 0xaa9556a9, .gpccon_mask = 0xffc003fc, + .gpccon_reg = S3C2410_GPCCON, .gpcup = 0x0000ffff, .gpcup_mask = 0xffffffff, + .gpcup_reg = S3C2410_GPCUP, .gpdcon = 0xaa90aaa1, .gpdcon_mask = 0xffc0fff0, + .gpdcon_reg = S3C2410_GPDCON, .gpdup = 0x0000fcfd, .gpdup_mask = 0xffffffff, - + .gpdup_reg = S3C2410_GPDUP, }; static struct pwm_lookup rx1950_pwm_lookup[] = { @@ -549,6 +551,8 @@ static struct platform_device rx1950_backlight = { static void rx1950_set_mmc_power(unsigned char power_mode, unsigned short vdd) { + s3c24xx_mci_def_set_power(power_mode, vdd); + switch (power_mode) { case MMC_POWER_OFF: gpio_direction_output(S3C2410_GPJ(1), 0); @@ -571,9 +575,16 @@ static struct gpiod_lookup_table rx1950_mmc_gpio_table = { .dev_id = "s3c2410-sdi", .table = { /* Card detect S3C2410_GPF(5) */ - GPIO_LOOKUP("GPF", 5, "cd", GPIO_ACTIVE_LOW), + GPIO_LOOKUP("GPIOF", 5, "cd", GPIO_ACTIVE_LOW), /* Write protect S3C2410_GPH(8) */ - GPIO_LOOKUP("GPH", 8, "wp", GPIO_ACTIVE_LOW), + GPIO_LOOKUP("GPIOH", 8, "wp", GPIO_ACTIVE_LOW), + /* bus pins */ + GPIO_LOOKUP_IDX("GPIOE", 5, "bus", 0, GPIO_ACTIVE_HIGH), + GPIO_LOOKUP_IDX("GPIOE", 6, "bus", 1, GPIO_ACTIVE_HIGH), + GPIO_LOOKUP_IDX("GPIOE", 7, "bus", 2, GPIO_ACTIVE_HIGH), + GPIO_LOOKUP_IDX("GPIOE", 8, "bus", 3, GPIO_ACTIVE_HIGH), + GPIO_LOOKUP_IDX("GPIOE", 9, "bus", 4, GPIO_ACTIVE_HIGH), + GPIO_LOOKUP_IDX("GPIOE", 10, "bus", 5, GPIO_ACTIVE_HIGH), { }, }, }; @@ -620,7 +631,7 @@ static struct s3c2410_platform_nand rx1950_nand_info = { .twrph1 = 15, .nr_sets = ARRAY_SIZE(rx1950_nand_sets), .sets = rx1950_nand_sets, - .ecc_mode = NAND_ECC_SOFT, + .engine_type = NAND_ECC_ENGINE_TYPE_SOFT, }; static struct s3c2410_udc_mach_info rx1950_udc_cfg __initdata = { @@ -767,7 +778,7 @@ static void __init rx1950_map_io(void) { s3c24xx_init_io(rx1950_iodesc, ARRAY_SIZE(rx1950_iodesc)); s3c24xx_init_uarts(rx1950_uartcfgs, ARRAY_SIZE(rx1950_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); + s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4); /* setup PM */ @@ -781,7 +792,7 @@ static void __init rx1950_map_io(void) static void __init rx1950_init_time(void) { s3c2442_init_clocks(16934000); - samsung_timer_init(); + s3c24xx_timer_init(); } static void __init rx1950_init_machine(void) @@ -829,6 +840,9 @@ static void __init rx1950_init_machine(void) pwm_add_table(rx1950_pwm_lookup, ARRAY_SIZE(rx1950_pwm_lookup)); gpiod_add_lookup_table(&rx1950_audio_gpio_table); + /* Configure the I2S pins (GPE0...GPE4) in correct mode */ + s3c_gpio_cfgall_range(S3C2410_GPE(0), 5, S3C_GPIO_SFN(2), + S3C_GPIO_PULL_NONE); platform_add_devices(rx1950_devices, ARRAY_SIZE(rx1950_devices)); i2c_register_board_info(0, rx1950_i2c_devices, diff --git a/arch/arm/mach-s3c24xx/mach-rx3715.c b/arch/arm/mach-s3c/mach-rx3715.c index 995f1ff34a1b..a03662a47b38 100644 --- a/arch/arm/mach-s3c24xx/mach-rx3715.c +++ b/arch/arm/mach-s3c/mach-rx3715.c @@ -30,22 +30,20 @@ #include <asm/mach/map.h> #include <linux/platform_data/mtd-nand-s3c2410.h> +#include <linux/platform_data/fb-s3c2410.h> #include <asm/irq.h> #include <asm/mach-types.h> -#include <mach/fb.h> -#include <mach/hardware.h> -#include <mach/regs-gpio.h> -#include <mach/regs-lcd.h> -#include <mach/gpio-samsung.h> +#include "regs-gpio.h" +#include "gpio-samsung.h" +#include "gpio-cfg.h" -#include <plat/cpu.h> -#include <plat/devs.h> -#include <plat/pm.h> -#include <plat/samsung-time.h> +#include "cpu.h" +#include "devs.h" +#include "pm.h" -#include "common.h" +#include "s3c24xx.h" #include "h1940.h" static struct map_desc rx3715_iodesc[] __initdata = { @@ -125,13 +123,17 @@ static struct s3c2410fb_mach_info rx3715_fb_info __initdata = { .gpccon = 0xaa955699, .gpccon_mask = 0xffc003cc, + .gpccon_reg = S3C2410_GPCCON, .gpcup = 0x0000ffff, .gpcup_mask = 0xffffffff, + .gpcup_reg = S3C2410_GPCUP, .gpdcon = 0xaa95aaa1, .gpdcon_mask = 0xffc0fff0, + .gpdcon_reg = S3C2410_GPDCON, .gpdup = 0x0000faff, .gpdup_mask = 0xffffffff, + .gpdup_reg = S3C2410_GPDUP, }; static struct mtd_partition __initdata rx3715_nand_part[] = { @@ -158,7 +160,7 @@ static struct s3c2410_platform_nand __initdata rx3715_nand_info = { .twrph1 = 15, .nr_sets = ARRAY_SIZE(rx3715_nand_sets), .sets = rx3715_nand_sets, - .ecc_mode = NAND_ECC_SOFT, + .engine_type = NAND_ECC_ENGINE_TYPE_SOFT, }; static struct platform_device *rx3715_devices[] __initdata = { @@ -174,13 +176,13 @@ static void __init rx3715_map_io(void) { s3c24xx_init_io(rx3715_iodesc, ARRAY_SIZE(rx3715_iodesc)); s3c24xx_init_uarts(rx3715_uartcfgs, ARRAY_SIZE(rx3715_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); + s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4); } static void __init rx3715_init_time(void) { s3c2440_init_clocks(16934000); - samsung_timer_init(); + s3c24xx_timer_init(); } /* H1940 and RX3715 need to reserve this for suspend */ @@ -199,6 +201,9 @@ static void __init rx3715_init_machine(void) s3c_nand_set_platdata(&rx3715_nand_info); s3c24xx_fb_set_platdata(&rx3715_fb_info); + /* Configure the I2S pins (GPE0...GPE4) in correct mode */ + s3c_gpio_cfgall_range(S3C2410_GPE(0), 5, S3C_GPIO_SFN(2), + S3C_GPIO_PULL_NONE); platform_add_devices(rx3715_devices, ARRAY_SIZE(rx3715_devices)); } diff --git a/arch/arm/mach-s3c24xx/mach-s3c2416-dt.c b/arch/arm/mach-s3c/mach-s3c2416-dt.c index aa7102713b37..418544d3015d 100644 --- a/arch/arm/mach-s3c24xx/mach-s3c2416-dt.c +++ b/arch/arm/mach-s3c/mach-s3c2416-dt.c @@ -16,12 +16,12 @@ #include <linux/serial_s3c.h> #include <asm/mach/arch.h> -#include <mach/map.h> +#include "map.h" -#include <plat/cpu.h> -#include <plat/pm.h> +#include "cpu.h" +#include "pm.h" -#include "common.h" +#include "s3c24xx.h" static void __init s3c2416_dt_map_io(void) { diff --git a/arch/arm/mach-s3c64xx/mach-s3c64xx-dt.c b/arch/arm/mach-s3c/mach-s3c64xx-dt.c index 1724f5ea5c46..00169c103862 100644 --- a/arch/arm/mach-s3c64xx/mach-s3c64xx-dt.c +++ b/arch/arm/mach-s3c/mach-s3c64xx-dt.c @@ -8,11 +8,10 @@ #include <asm/mach/map.h> #include <asm/system_misc.h> -#include <plat/cpu.h> -#include <mach/map.h> +#include "cpu.h" +#include "map.h" -#include "common.h" -#include "watchdog-reset.h" +#include "s3c64xx.h" /* * IO mapping for shared system controller IP. @@ -39,20 +38,6 @@ static void __init s3c64xx_dt_map_io(void) panic("SoC is not S3C64xx!"); } -static void __init s3c64xx_dt_init_machine(void) -{ - samsung_wdt_reset_of_init(); -} - -static void s3c64xx_dt_restart(enum reboot_mode mode, const char *cmd) -{ - if (mode != REBOOT_SOFT) - samsung_wdt_reset(); - - /* if all else fails, or mode was for soft, jump to 0 */ - soft_restart(0); -} - static const char *const s3c64xx_dt_compat[] __initconst = { "samsung,s3c6400", "samsung,s3c6410", @@ -63,6 +48,4 @@ DT_MACHINE_START(S3C6400_DT, "Samsung S3C64xx (Flattened Device Tree)") /* Maintainer: Tomasz Figa <tomasz.figa@gmail.com> */ .dt_compat = s3c64xx_dt_compat, .map_io = s3c64xx_dt_map_io, - .init_machine = s3c64xx_dt_init_machine, - .restart = s3c64xx_dt_restart, MACHINE_END diff --git a/arch/arm/mach-s3c64xx/mach-smartq.c b/arch/arm/mach-s3c/mach-smartq.c index 5025db607c0f..5b6e7c2a85ef 100644 --- a/arch/arm/mach-s3c64xx/mach-smartq.c +++ b/arch/arm/mach-s3c/mach-smartq.c @@ -18,25 +18,24 @@ #include <asm/mach-types.h> #include <asm/mach/map.h> -#include <mach/map.h> -#include <mach/regs-gpio.h> -#include <mach/gpio-samsung.h> +#include "map.h" +#include "regs-gpio.h" +#include "gpio-samsung.h" -#include <plat/cpu.h> -#include <plat/devs.h> +#include "cpu.h" +#include "devs.h" #include <linux/platform_data/i2c-s3c2410.h> -#include <plat/gpio-cfg.h> +#include "gpio-cfg.h" #include <linux/platform_data/hwmon-s3c.h> #include <linux/platform_data/usb-ohci-s3c2410.h> -#include <plat/sdhci.h> +#include "sdhci.h" #include <linux/platform_data/touchscreen-s3c2410.h> #include <video/platform_lcd.h> -#include <plat/samsung-time.h> -#include "common.h" +#include "s3c64xx.h" #include "mach-smartq.h" -#include "regs-modem.h" +#include "regs-modem-s3c64xx.h" #define UCON S3C2410_UCON_DEFAULT #define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE) @@ -384,7 +383,7 @@ void __init smartq_map_io(void) s3c64xx_set_xtal_freq(12000000); s3c64xx_set_xusbxti_freq(12000000); s3c24xx_init_uarts(smartq_uartcfgs, ARRAY_SIZE(smartq_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); + s3c64xx_set_timer_source(S3C64XX_PWM3, S3C64XX_PWM4); smartq_lcd_mode_set(); } diff --git a/arch/arm/mach-s3c64xx/mach-smartq.h b/arch/arm/mach-s3c/mach-smartq.h index f98132f4f430..f98132f4f430 100644 --- a/arch/arm/mach-s3c64xx/mach-smartq.h +++ b/arch/arm/mach-s3c/mach-smartq.h diff --git a/arch/arm/mach-s3c64xx/mach-smartq5.c b/arch/arm/mach-s3c/mach-smartq5.c index 44e9edb144fa..8c940227e810 100644 --- a/arch/arm/mach-s3c64xx/mach-smartq5.c +++ b/arch/arm/mach-s3c/mach-smartq5.c @@ -15,17 +15,16 @@ #include <video/samsung_fimd.h> #include <mach/irqs.h> -#include <mach/map.h> -#include <mach/regs-gpio.h> -#include <mach/gpio-samsung.h> +#include "map.h" +#include "regs-gpio.h" +#include "gpio-samsung.h" -#include <plat/cpu.h> -#include <plat/devs.h> -#include <plat/fb.h> -#include <plat/gpio-cfg.h> -#include <plat/samsung-time.h> +#include "cpu.h" +#include "devs.h" +#include "fb.h" +#include "gpio-cfg.h" -#include "common.h" +#include "s3c64xx.h" #include "mach-smartq.h" static struct gpio_led smartq5_leds[] = { @@ -151,6 +150,5 @@ MACHINE_START(SMARTQ5, "SmartQ 5") .init_irq = s3c6410_init_irq, .map_io = smartq_map_io, .init_machine = smartq5_machine_init, - .init_time = samsung_timer_init, - .restart = s3c64xx_restart, + .init_time = s3c64xx_timer_init, MACHINE_END diff --git a/arch/arm/mach-s3c64xx/mach-smartq7.c b/arch/arm/mach-s3c/mach-smartq7.c index 815ee7d0b5e3..ab243969d6d0 100644 --- a/arch/arm/mach-s3c64xx/mach-smartq7.c +++ b/arch/arm/mach-s3c/mach-smartq7.c @@ -15,17 +15,16 @@ #include <video/samsung_fimd.h> #include <mach/irqs.h> -#include <mach/map.h> -#include <mach/regs-gpio.h> -#include <mach/gpio-samsung.h> +#include "map.h" +#include "regs-gpio.h" +#include "gpio-samsung.h" -#include <plat/cpu.h> -#include <plat/devs.h> -#include <plat/fb.h> -#include <plat/gpio-cfg.h> -#include <plat/samsung-time.h> +#include "cpu.h" +#include "devs.h" +#include "fb.h" +#include "gpio-cfg.h" -#include "common.h" +#include "s3c64xx.h" #include "mach-smartq.h" static struct gpio_led smartq7_leds[] = { @@ -167,6 +166,5 @@ MACHINE_START(SMARTQ7, "SmartQ 7") .init_irq = s3c6410_init_irq, .map_io = smartq_map_io, .init_machine = smartq7_machine_init, - .init_time = samsung_timer_init, - .restart = s3c64xx_restart, + .init_time = s3c64xx_timer_init, MACHINE_END diff --git a/arch/arm/mach-s3c24xx/mach-smdk2410.c b/arch/arm/mach-s3c/mach-smdk2410.c index 18dfef52c8bf..ca83d5a7d101 100644 --- a/arch/arm/mach-s3c24xx/mach-smdk2410.c +++ b/arch/arm/mach-s3c/mach-smdk2410.c @@ -19,23 +19,23 @@ #include <linux/serial_s3c.h> #include <linux/platform_device.h> #include <linux/io.h> +#include "gpio-samsung.h" +#include "gpio-cfg.h" #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <asm/mach/irq.h> -#include <mach/hardware.h> #include <asm/irq.h> #include <asm/mach-types.h> #include <linux/platform_data/i2c-s3c2410.h> -#include <plat/devs.h> -#include <plat/cpu.h> -#include <plat/samsung-time.h> +#include "devs.h" +#include "cpu.h" -#include "common.h" -#include "common-smdk.h" +#include "s3c24xx.h" +#include "common-smdk-s3c24xx.h" static struct map_desc smdk2410_iodesc[] __initdata = { /* nothing here yet */ @@ -81,19 +81,22 @@ static void __init smdk2410_map_io(void) { s3c24xx_init_io(smdk2410_iodesc, ARRAY_SIZE(smdk2410_iodesc)); s3c24xx_init_uarts(smdk2410_uartcfgs, ARRAY_SIZE(smdk2410_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); + s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4); } static void __init smdk2410_init_time(void) { s3c2410_init_clocks(12000000); - samsung_timer_init(); + s3c24xx_timer_init(); } static void __init smdk2410_init(void) { s3c_i2c0_set_platdata(NULL); platform_add_devices(smdk2410_devices, ARRAY_SIZE(smdk2410_devices)); + /* Configure the I2S pins (GPE0...GPE4) in correct mode */ + s3c_gpio_cfgall_range(S3C2410_GPE(0), 5, S3C_GPIO_SFN(2), + S3C_GPIO_PULL_NONE); smdk_machine_init(); } diff --git a/arch/arm/mach-s3c24xx/mach-smdk2413.c b/arch/arm/mach-s3c/mach-smdk2413.c index ca80167f268d..c43095b321d7 100644 --- a/arch/arm/mach-s3c24xx/mach-smdk2413.c +++ b/arch/arm/mach-s3c/mach-smdk2413.c @@ -23,27 +23,26 @@ #include <asm/mach/map.h> #include <asm/mach/irq.h> -#include <mach/hardware.h> #include <asm/hardware/iomd.h> #include <asm/setup.h> #include <asm/irq.h> #include <asm/mach-types.h> //#include <asm/debug-ll.h> -#include <mach/regs-gpio.h> -#include <mach/regs-lcd.h> +#include "hardware-s3c24xx.h" +#include "regs-gpio.h" #include <linux/platform_data/usb-s3c2410_udc.h> #include <linux/platform_data/i2c-s3c2410.h> -#include <mach/gpio-samsung.h> -#include <mach/fb.h> +#include <linux/platform_data/fb-s3c2410.h> +#include "gpio-samsung.h" +#include "gpio-cfg.h" -#include <plat/devs.h> -#include <plat/cpu.h> -#include <plat/samsung-time.h> +#include "devs.h" +#include "cpu.h" -#include "common.h" -#include "common-smdk.h" +#include "s3c24xx.h" +#include "common-smdk-s3c24xx.h" static struct map_desc smdk2413_iodesc[] __initdata = { }; @@ -99,13 +98,13 @@ static void __init smdk2413_map_io(void) { s3c24xx_init_io(smdk2413_iodesc, ARRAY_SIZE(smdk2413_iodesc)); s3c24xx_init_uarts(smdk2413_uartcfgs, ARRAY_SIZE(smdk2413_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); + s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4); } static void __init smdk2413_init_time(void) { s3c2412_init_clocks(12000000); - samsung_timer_init(); + s3c24xx_timer_init(); } static void __init smdk2413_machine_init(void) @@ -119,6 +118,9 @@ static void __init smdk2413_machine_init(void) s3c24xx_udc_set_platdata(&smdk2413_udc_cfg); s3c_i2c0_set_platdata(NULL); + /* Configure the I2S pins (GPE0...GPE4) in correct mode */ + s3c_gpio_cfgall_range(S3C2410_GPE(0), 5, S3C_GPIO_SFN(2), + S3C_GPIO_PULL_NONE); platform_add_devices(smdk2413_devices, ARRAY_SIZE(smdk2413_devices)); smdk_machine_init(); @@ -132,7 +134,7 @@ MACHINE_START(S3C2413, "S3C2413") .init_irq = s3c2412_init_irq, .map_io = smdk2413_map_io, .init_machine = smdk2413_machine_init, - .init_time = samsung_timer_init, + .init_time = s3c24xx_timer_init, MACHINE_END MACHINE_START(SMDK2412, "SMDK2412") @@ -143,7 +145,7 @@ MACHINE_START(SMDK2412, "SMDK2412") .init_irq = s3c2412_init_irq, .map_io = smdk2413_map_io, .init_machine = smdk2413_machine_init, - .init_time = samsung_timer_init, + .init_time = s3c24xx_timer_init, MACHINE_END MACHINE_START(SMDK2413, "SMDK2413") diff --git a/arch/arm/mach-s3c24xx/mach-smdk2416.c b/arch/arm/mach-s3c/mach-smdk2416.c index 61c3e45898d3..4d883a792cc6 100644 --- a/arch/arm/mach-s3c24xx/mach-smdk2416.c +++ b/arch/arm/mach-s3c/mach-smdk2416.c @@ -25,31 +25,29 @@ #include <asm/mach/irq.h> #include <video/samsung_fimd.h> -#include <mach/hardware.h> #include <asm/irq.h> #include <asm/mach-types.h> -#include <mach/regs-gpio.h> -#include <mach/regs-lcd.h> -#include <mach/regs-s3c2443-clock.h> -#include <mach/gpio-samsung.h> +#include "hardware-s3c24xx.h" +#include "regs-gpio.h" +#include "regs-s3c2443-clock.h" +#include "gpio-samsung.h" #include <linux/platform_data/leds-s3c24xx.h> #include <linux/platform_data/i2c-s3c2410.h> -#include <plat/gpio-cfg.h> -#include <plat/devs.h> -#include <plat/cpu.h> +#include "gpio-cfg.h" +#include "devs.h" +#include "cpu.h" #include <linux/platform_data/mtd-nand-s3c2410.h> -#include <plat/sdhci.h> +#include "sdhci.h" #include <linux/platform_data/usb-s3c2410_udc.h> #include <linux/platform_data/s3c-hsudc.h> -#include <plat/samsung-time.h> -#include <plat/fb.h> +#include "fb.h" -#include "common.h" -#include "common-smdk.h" +#include "s3c24xx.h" +#include "common-smdk-s3c24xx.h" static struct map_desc smdk2416_iodesc[] __initdata = { /* ISA IO Space map (memory space selected by A24) */ @@ -215,14 +213,14 @@ static struct platform_device *smdk2416_devices[] __initdata = { static void __init smdk2416_init_time(void) { s3c2416_init_clocks(12000000); - samsung_timer_init(); + s3c24xx_timer_init(); } static void __init smdk2416_map_io(void) { s3c24xx_init_io(smdk2416_iodesc, ARRAY_SIZE(smdk2416_iodesc)); s3c24xx_init_uarts(smdk2416_uartcfgs, ARRAY_SIZE(smdk2416_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); + s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4); } static void __init smdk2416_machine_init(void) diff --git a/arch/arm/mach-s3c24xx/mach-smdk2440.c b/arch/arm/mach-s3c/mach-smdk2440.c index 7bafcd8ea104..7f6fe0db04f3 100644 --- a/arch/arm/mach-s3c24xx/mach-smdk2440.c +++ b/arch/arm/mach-s3c/mach-smdk2440.c @@ -23,22 +23,21 @@ #include <asm/mach/map.h> #include <asm/mach/irq.h> -#include <mach/hardware.h> #include <asm/irq.h> #include <asm/mach-types.h> -#include <mach/regs-gpio.h> -#include <mach/regs-lcd.h> +#include "regs-gpio.h" +#include "gpio-samsung.h" +#include "gpio-cfg.h" -#include <mach/fb.h> +#include <linux/platform_data/fb-s3c2410.h> #include <linux/platform_data/i2c-s3c2410.h> -#include <plat/devs.h> -#include <plat/cpu.h> -#include <plat/samsung-time.h> +#include "devs.h" +#include "cpu.h" -#include "common.h" -#include "common-smdk.h" +#include "s3c24xx.h" +#include "common-smdk-s3c24xx.h" static struct map_desc smdk2440_iodesc[] __initdata = { /* ISA IO Space map (memory space selected by A24) */ @@ -137,6 +136,11 @@ static struct s3c2410fb_mach_info smdk2440_fb_info __initdata = { .gpdcon_mask = 0xffffffff, .gpdup = 0x0000faff, .gpdup_mask = 0xffffffff, + + .gpccon_reg = S3C2410_GPCCON, + .gpcup_reg = S3C2410_GPCUP, + .gpdcon_reg = S3C2410_GPDCON, + .gpdup_reg = S3C2410_GPDUP, #endif .lpcsel = ((0xCE6) & ~7) | 1<<4, @@ -154,20 +158,22 @@ static void __init smdk2440_map_io(void) { s3c24xx_init_io(smdk2440_iodesc, ARRAY_SIZE(smdk2440_iodesc)); s3c24xx_init_uarts(smdk2440_uartcfgs, ARRAY_SIZE(smdk2440_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); + s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4); } static void __init smdk2440_init_time(void) { s3c2440_init_clocks(16934400); - samsung_timer_init(); + s3c24xx_timer_init(); } static void __init smdk2440_machine_init(void) { s3c24xx_fb_set_platdata(&smdk2440_fb_info); s3c_i2c0_set_platdata(NULL); - + /* Configure the I2S pins (GPE0...GPE4) in correct mode */ + s3c_gpio_cfgall_range(S3C2410_GPE(0), 5, S3C_GPIO_SFN(2), + S3C_GPIO_PULL_NONE); platform_add_devices(smdk2440_devices, ARRAY_SIZE(smdk2440_devices)); smdk_machine_init(); } diff --git a/arch/arm/mach-s3c24xx/mach-smdk2443.c b/arch/arm/mach-s3c/mach-smdk2443.c index 2358ed5ed7be..fc54c91ade56 100644 --- a/arch/arm/mach-s3c24xx/mach-smdk2443.c +++ b/arch/arm/mach-s3c/mach-smdk2443.c @@ -22,22 +22,19 @@ #include <asm/mach/map.h> #include <asm/mach/irq.h> -#include <mach/hardware.h> #include <asm/irq.h> #include <asm/mach-types.h> -#include <mach/regs-gpio.h> -#include <mach/regs-lcd.h> +#include "regs-gpio.h" -#include <mach/fb.h> +#include <linux/platform_data/fb-s3c2410.h> #include <linux/platform_data/i2c-s3c2410.h> -#include <plat/devs.h> -#include <plat/cpu.h> -#include <plat/samsung-time.h> +#include "devs.h" +#include "cpu.h" -#include "common.h" -#include "common-smdk.h" +#include "s3c24xx.h" +#include "common-smdk-s3c24xx.h" static struct map_desc smdk2443_iodesc[] __initdata = { /* ISA IO Space map (memory space selected by A24) */ @@ -112,13 +109,13 @@ static void __init smdk2443_map_io(void) { s3c24xx_init_io(smdk2443_iodesc, ARRAY_SIZE(smdk2443_iodesc)); s3c24xx_init_uarts(smdk2443_uartcfgs, ARRAY_SIZE(smdk2443_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); + s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4); } static void __init smdk2443_init_time(void) { s3c2443_init_clocks(12000000); - samsung_timer_init(); + s3c24xx_timer_init(); } static void __init smdk2443_machine_init(void) diff --git a/arch/arm/mach-s3c64xx/mach-smdk6400.c b/arch/arm/mach-s3c/mach-smdk6400.c index cbd16843c7d1..827221398d6c 100644 --- a/arch/arm/mach-s3c64xx/mach-smdk6400.c +++ b/arch/arm/mach-s3c/mach-smdk6400.c @@ -23,16 +23,14 @@ #include <asm/mach/irq.h> #include <mach/irqs.h> -#include <mach/hardware.h> -#include <mach/map.h> +#include "map.h" -#include <plat/devs.h> -#include <plat/cpu.h> +#include "devs.h" +#include "cpu.h" #include <linux/platform_data/i2c-s3c2410.h> -#include <mach/gpio-samsung.h> -#include <plat/samsung-time.h> +#include "gpio-samsung.h" -#include "common.h" +#include "s3c64xx.h" #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB @@ -62,7 +60,7 @@ static void __init smdk6400_map_io(void) s3c64xx_init_io(smdk6400_iodesc, ARRAY_SIZE(smdk6400_iodesc)); s3c64xx_set_xtal_freq(12000000); s3c24xx_init_uarts(smdk6400_uartcfgs, ARRAY_SIZE(smdk6400_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); + s3c64xx_set_timer_source(S3C64XX_PWM3, S3C64XX_PWM4); } static struct platform_device *smdk6400_devices[] __initdata = { @@ -88,6 +86,5 @@ MACHINE_START(SMDK6400, "SMDK6400") .init_irq = s3c6400_init_irq, .map_io = smdk6400_map_io, .init_machine = smdk6400_machine_init, - .init_time = samsung_timer_init, - .restart = s3c64xx_restart, + .init_time = s3c64xx_timer_init, MACHINE_END diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c/mach-smdk6410.c index 56f406c0c3dd..ae18c1375c9c 100644 --- a/arch/arm/mach-s3c64xx/mach-smdk6410.c +++ b/arch/arm/mach-s3c/mach-smdk6410.c @@ -45,32 +45,30 @@ #include <asm/mach/map.h> #include <asm/mach/irq.h> -#include <mach/hardware.h> #include <mach/irqs.h> -#include <mach/map.h> +#include "map.h" #include <asm/irq.h> #include <asm/mach-types.h> -#include <mach/regs-gpio.h> -#include <mach/gpio-samsung.h> +#include "regs-gpio.h" +#include "gpio-samsung.h" #include <linux/platform_data/ata-samsung_cf.h> #include <linux/platform_data/i2c-s3c2410.h> -#include <plat/fb.h> -#include <plat/gpio-cfg.h> +#include "fb.h" +#include "gpio-cfg.h" -#include <plat/devs.h> -#include <plat/cpu.h> -#include <plat/adc.h> +#include "devs.h" +#include "cpu.h" +#include <linux/soc/samsung/s3c-adc.h> #include <linux/platform_data/touchscreen-s3c2410.h> -#include <plat/keypad.h> -#include <plat/samsung-time.h> +#include "keypad.h" -#include "backlight.h" -#include "common.h" -#include "regs-modem.h" -#include "regs-srom.h" -#include "regs-sys.h" +#include "backlight-s3c64xx.h" +#include "s3c64xx.h" +#include "regs-modem-s3c64xx.h" +#include "regs-srom-s3c64xx.h" +#include "regs-sys-s3c64xx.h" #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB @@ -635,7 +633,7 @@ static void __init smdk6410_map_io(void) s3c64xx_init_io(smdk6410_iodesc, ARRAY_SIZE(smdk6410_iodesc)); s3c64xx_set_xtal_freq(12000000); s3c24xx_init_uarts(smdk6410_uartcfgs, ARRAY_SIZE(smdk6410_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); + s3c64xx_set_timer_source(S3C64XX_PWM3, S3C64XX_PWM4); /* set the LCD type */ @@ -704,6 +702,5 @@ MACHINE_START(SMDK6410, "SMDK6410") .init_irq = s3c6410_init_irq, .map_io = smdk6410_map_io, .init_machine = smdk6410_machine_init, - .init_time = samsung_timer_init, - .restart = s3c64xx_restart, + .init_time = s3c64xx_timer_init, MACHINE_END diff --git a/arch/arm/mach-s3c24xx/mach-tct_hammer.c b/arch/arm/mach-s3c/mach-tct_hammer.c index 8d8ddd6ea305..2a61df316e8c 100644 --- a/arch/arm/mach-s3c24xx/mach-tct_hammer.c +++ b/arch/arm/mach-s3c/mach-tct_hammer.c @@ -7,6 +7,7 @@ // derived from linux/arch/arm/mach-s3c2410/mach-bast.c, written by // Ben Dooks <ben@simtec.co.uk> +#include <linux/gpio/machine.h> #include <linux/kernel.h> #include <linux/types.h> #include <linux/interrupt.h> @@ -24,21 +25,19 @@ #include <asm/mach/irq.h> #include <asm/mach/flash.h> -#include <mach/hardware.h> #include <asm/irq.h> #include <asm/mach-types.h> #include <linux/platform_data/i2c-s3c2410.h> -#include <plat/devs.h> -#include <plat/cpu.h> +#include "devs.h" +#include "cpu.h" #include <linux/mtd/mtd.h> #include <linux/mtd/partitions.h> #include <linux/mtd/map.h> #include <linux/mtd/physmap.h> -#include <plat/samsung-time.h> -#include "common.h" +#include "s3c24xx.h" static struct resource tct_hammer_nor_resource = DEFINE_RES_MEM(0x00000000, SZ_16M); @@ -103,6 +102,19 @@ static struct s3c2410_uartcfg tct_hammer_uartcfgs[] = { } }; +static struct gpiod_lookup_table tct_hammer_mmc_gpio_table = { + .dev_id = "s3c2410-sdi", + .table = { + /* bus pins */ + GPIO_LOOKUP_IDX("GPIOE", 5, "bus", 0, GPIO_ACTIVE_HIGH), + GPIO_LOOKUP_IDX("GPIOE", 6, "bus", 1, GPIO_ACTIVE_HIGH), + GPIO_LOOKUP_IDX("GPIOE", 7, "bus", 2, GPIO_ACTIVE_HIGH), + GPIO_LOOKUP_IDX("GPIOE", 8, "bus", 3, GPIO_ACTIVE_HIGH), + GPIO_LOOKUP_IDX("GPIOE", 9, "bus", 4, GPIO_ACTIVE_HIGH), + GPIO_LOOKUP_IDX("GPIOE", 10, "bus", 5, GPIO_ACTIVE_HIGH), + { }, + }, +}; static struct platform_device *tct_hammer_devices[] __initdata = { &s3c_device_adc, @@ -119,18 +131,19 @@ static void __init tct_hammer_map_io(void) { s3c24xx_init_io(tct_hammer_iodesc, ARRAY_SIZE(tct_hammer_iodesc)); s3c24xx_init_uarts(tct_hammer_uartcfgs, ARRAY_SIZE(tct_hammer_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); + s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4); } static void __init tct_hammer_init_time(void) { s3c2410_init_clocks(12000000); - samsung_timer_init(); + s3c24xx_timer_init(); } static void __init tct_hammer_init(void) { s3c_i2c0_set_platdata(NULL); + gpiod_add_lookup_table(&tct_hammer_mmc_gpio_table); platform_add_devices(tct_hammer_devices, ARRAY_SIZE(tct_hammer_devices)); } diff --git a/arch/arm/mach-s3c24xx/mach-vr1000.c b/arch/arm/mach-s3c/mach-vr1000.c index 6a3fb2becc7c..5c3d07cf2e79 100644 --- a/arch/arm/mach-s3c24xx/mach-vr1000.c +++ b/arch/arm/mach-s3c/mach-vr1000.c @@ -35,17 +35,15 @@ #include <linux/platform_data/i2c-s3c2410.h> #include <linux/platform_data/asoc-s3c24xx_simtec.h> -#include <mach/hardware.h> -#include <mach/regs-gpio.h> -#include <mach/gpio-samsung.h> +#include "regs-gpio.h" +#include "gpio-samsung.h" +#include "gpio-cfg.h" -#include <plat/cpu.h> -#include <plat/devs.h> -#include <plat/gpio-cfg.h> -#include <plat/samsung-time.h> +#include "cpu.h" +#include "devs.h" #include "bast.h" -#include "common.h" +#include "s3c24xx.h" #include "simtec.h" #include "vr1000.h" @@ -328,13 +326,13 @@ static void __init vr1000_map_io(void) s3c24xx_init_io(vr1000_iodesc, ARRAY_SIZE(vr1000_iodesc)); s3c24xx_init_uarts(vr1000_uartcfgs, ARRAY_SIZE(vr1000_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); + s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4); } static void __init vr1000_init_time(void) { s3c2410_init_clocks(12000000); - samsung_timer_init(); + s3c24xx_timer_init(); } static void __init vr1000_init(void) diff --git a/arch/arm/mach-s3c24xx/mach-vstms.c b/arch/arm/mach-s3c/mach-vstms.c index d76b28b65e65..05f19f5ffabb 100644 --- a/arch/arm/mach-s3c24xx/mach-vstms.c +++ b/arch/arm/mach-s3c/mach-vstms.c @@ -24,24 +24,23 @@ #include <asm/mach/map.h> #include <asm/mach/irq.h> -#include <mach/hardware.h> #include <asm/setup.h> #include <asm/irq.h> #include <asm/mach-types.h> -#include <mach/regs-gpio.h> -#include <mach/regs-lcd.h> +#include "regs-gpio.h" +#include "gpio-samsung.h" +#include "gpio-cfg.h" -#include <mach/fb.h> +#include <linux/platform_data/fb-s3c2410.h> #include <linux/platform_data/i2c-s3c2410.h> #include <linux/platform_data/mtd-nand-s3c2410.h> -#include <plat/devs.h> -#include <plat/cpu.h> -#include <plat/samsung-time.h> +#include "devs.h" +#include "cpu.h" -#include "common.h" +#include "s3c24xx.h" static struct map_desc vstms_iodesc[] __initdata = { }; @@ -112,7 +111,7 @@ static struct s3c2410_platform_nand __initdata vstms_nand_info = { .twrph1 = 20, .nr_sets = ARRAY_SIZE(vstms_nand_sets), .sets = vstms_nand_sets, - .ecc_mode = NAND_ECC_SOFT, + .engine_type = NAND_ECC_ENGINE_TYPE_SOFT, }; static struct platform_device *vstms_devices[] __initdata = { @@ -136,20 +135,22 @@ static void __init vstms_map_io(void) { s3c24xx_init_io(vstms_iodesc, ARRAY_SIZE(vstms_iodesc)); s3c24xx_init_uarts(vstms_uartcfgs, ARRAY_SIZE(vstms_uartcfgs)); - samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); + s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4); } static void __init vstms_init_time(void) { s3c2412_init_clocks(12000000); - samsung_timer_init(); + s3c24xx_timer_init(); } static void __init vstms_init(void) { s3c_i2c0_set_platdata(NULL); s3c_nand_set_platdata(&vstms_nand_info); - + /* Configure the I2S pins (GPE0...GPE4) in correct mode */ + s3c_gpio_cfgall_range(S3C2410_GPE(0), 5, S3C_GPIO_SFN(2), + S3C_GPIO_PULL_NONE); platform_add_devices(vstms_devices, ARRAY_SIZE(vstms_devices)); } diff --git a/arch/arm/plat-samsung/include/plat/map-s3c.h b/arch/arm/mach-s3c/map-s3c.h index 4244acbf4b65..a18fdd3d6ae2 100644 --- a/arch/arm/plat-samsung/include/plat/map-s3c.h +++ b/arch/arm/mach-s3c/map-s3c.h @@ -9,6 +9,8 @@ #ifndef __ASM_PLAT_MAP_S3C_H #define __ASM_PLAT_MAP_S3C_H __FILE__ +#include "map.h" + #define S3C24XX_VA_IRQ S3C_VA_IRQ #define S3C24XX_VA_MEMCTRL S3C_VA_MEM #define S3C24XX_VA_UART S3C_VA_UART @@ -45,16 +47,8 @@ #define S3C_VA_USB_HSPHY S3C64XX_VA_USB_HSPHY -/* - * ISA style IO, for each machine to sort out mappings for, - * if it implements it. We reserve two 16M regions for ISA. - */ - #define S3C2410_ADDR(x) S3C_ADDR(x) -#define S3C24XX_VA_ISA_WORD S3C2410_ADDR(0x02000000) -#define S3C24XX_VA_ISA_BYTE S3C2410_ADDR(0x03000000) - /* deal with the registers that move under the 2412/2413 */ #if defined(CONFIG_CPU_S3C2412) @@ -71,6 +65,6 @@ extern void __iomem *s3c24xx_va_gpio2; #define S3C24XX_VA_GPIO2 S3C24XX_VA_GPIO #endif -#include <plat/map-s5p.h> +#include "map-s5p.h" #endif /* __ASM_PLAT_MAP_S3C_H */ diff --git a/arch/arm/mach-s3c24xx/include/mach/map.h b/arch/arm/mach-s3c/map-s3c24xx.h index bca93112f57d..b5dba78a9dd7 100644 --- a/arch/arm/mach-s3c24xx/include/mach/map.h +++ b/arch/arm/mach-s3c/map-s3c24xx.h @@ -9,8 +9,8 @@ #ifndef __ASM_ARCH_MAP_H #define __ASM_ARCH_MAP_H -#include <plat/map-base.h> -#include <plat/map-s3c.h> +#include <mach/map-base.h> +#include "map-s3c.h" /* * interrupt controller is the first thing we put in, to make @@ -86,6 +86,8 @@ #define S3C2410_PA_SPI (0x59000000) #define S3C2443_PA_SPI0 (0x52000000) #define S3C2443_PA_SPI1 S3C2410_PA_SPI +#define S3C2410_SPI1 (0x20) +#define S3C2412_SPI1 (0x100) /* SDI */ #define S3C2410_PA_SDI (0x5A000000) diff --git a/arch/arm/mach-s3c64xx/include/mach/map.h b/arch/arm/mach-s3c/map-s3c64xx.h index 9372a535b7ba..d7740d2a77c4 100644 --- a/arch/arm/mach-s3c64xx/include/mach/map.h +++ b/arch/arm/mach-s3c/map-s3c64xx.h @@ -11,8 +11,8 @@ #ifndef __ASM_ARCH_MAP_H #define __ASM_ARCH_MAP_H __FILE__ -#include <plat/map-base.h> -#include <plat/map-s3c.h> +#include <mach/map-base.h> +#include "map-s3c.h" /* * Post-mux Chip Select Regions Xm0CSn_ diff --git a/arch/arm/plat-samsung/include/plat/map-s5p.h b/arch/arm/mach-s3c/map-s5p.h index d69a0ca09fb5..cd237924e34d 100644 --- a/arch/arm/plat-samsung/include/plat/map-s5p.h +++ b/arch/arm/mach-s3c/map-s5p.h @@ -9,14 +9,12 @@ #ifndef __ASM_PLAT_MAP_S5P_H #define __ASM_PLAT_MAP_S5P_H __FILE__ -#define S5P_VA_CHIPID S3C_ADDR(0x02000000) - #define VA_VIC(x) (S3C_VA_IRQ + ((x) * 0x10000)) #define VA_VIC0 VA_VIC(0) #define VA_VIC1 VA_VIC(1) #define VA_VIC2 VA_VIC(2) #define VA_VIC3 VA_VIC(3) -#include <plat/map-s3c.h> +#include "map-s3c.h" #endif /* __ASM_PLAT_MAP_S5P_H */ diff --git a/arch/arm/mach-s3c/map.h b/arch/arm/mach-s3c/map.h new file mode 100644 index 000000000000..7cfb517d4886 --- /dev/null +++ b/arch/arm/mach-s3c/map.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifdef CONFIG_ARCH_S3C24XX +#include "map-s3c24xx.h" +#endif + +#ifdef CONFIG_ARCH_S3C64XX +#include "map-s3c64xx.h" +#endif diff --git a/arch/arm/mach-s3c24xx/nand-core.h b/arch/arm/mach-s3c/nand-core-s3c24xx.h index 8de633d416ae..a14316729c48 100644 --- a/arch/arm/mach-s3c24xx/nand-core.h +++ b/arch/arm/mach-s3c/nand-core-s3c24xx.h @@ -6,8 +6,8 @@ * S3C - Nand Controller core functions */ -#ifndef __ASM_ARCH_NAND_CORE_H -#define __ASM_ARCH_NAND_CORE_H __FILE__ +#ifndef __ASM_ARCH_NAND_CORE_S3C24XX_H +#define __ASM_ARCH_NAND_CORE_S3C24XX_H __FILE__ /* These functions are only for use with the core support code, such as * the cpu specific initialisation code @@ -21,4 +21,4 @@ static inline void s3c_nand_setname(char *name) #endif } -#endif /* __ASM_ARCH_NAND_CORE_H */ +#endif /* __ASM_ARCH_NAND_CORE_S3C24XX_H */ diff --git a/arch/arm/mach-s3c64xx/onenand-core.h b/arch/arm/mach-s3c/onenand-core-s3c64xx.h index 0cf6b5e76b24..e2dfdd1fec93 100644 --- a/arch/arm/mach-s3c64xx/onenand-core.h +++ b/arch/arm/mach-s3c/onenand-core-s3c64xx.h @@ -7,8 +7,8 @@ * Samsung OneNAD Controller core functions */ -#ifndef __ASM_ARCH_ONENAND_CORE_H -#define __ASM_ARCH_ONENAND_CORE_H __FILE__ +#ifndef __ASM_ARCH_ONENAND_CORE_S3C64XX_H +#define __ASM_ARCH_ONENAND_CORE_S3C64XX_H __FILE__ /* These functions are only for use with the core support code, such as * the cpu specific initialisation code @@ -29,4 +29,4 @@ static inline void s3c64xx_onenand1_setname(char *name) #endif } -#endif /* __ASM_ARCH_ONENAND_CORE_H */ +#endif /* __ASM_ARCH_ONENAND_CORE_S3C64XX_H */ diff --git a/arch/arm/mach-s3c24xx/osiris.h b/arch/arm/mach-s3c/osiris.h index b6c9c5ed2ba7..b6c9c5ed2ba7 100644 --- a/arch/arm/mach-s3c24xx/osiris.h +++ b/arch/arm/mach-s3c/osiris.h diff --git a/arch/arm/mach-s3c24xx/otom.h b/arch/arm/mach-s3c/otom.h index c800f67d03d4..c800f67d03d4 100644 --- a/arch/arm/mach-s3c24xx/otom.h +++ b/arch/arm/mach-s3c/otom.h diff --git a/arch/arm/mach-s3c64xx/pl080.c b/arch/arm/mach-s3c/pl080.c index 152edbeea0c7..4730f080c736 100644 --- a/arch/arm/mach-s3c64xx/pl080.c +++ b/arch/arm/mach-s3c/pl080.c @@ -10,11 +10,11 @@ #include <linux/amba/pl08x.h> #include <linux/of.h> -#include <plat/cpu.h> +#include "cpu.h" #include <mach/irqs.h> -#include <mach/map.h> +#include "map.h" -#include "regs-sys.h" +#include "regs-sys-s3c64xx.h" static int pl08x_get_xfer_signal(const struct pl08x_channel_data *cd) { diff --git a/arch/arm/plat-samsung/platformdata.c b/arch/arm/mach-s3c/platformdata.c index cbc3b4b45c74..e643c81aef45 100644 --- a/arch/arm/plat-samsung/platformdata.c +++ b/arch/arm/mach-s3c/platformdata.c @@ -9,8 +9,8 @@ #include <linux/string.h> #include <linux/platform_device.h> -#include <plat/devs.h> -#include <plat/sdhci.h> +#include "devs.h" +#include "sdhci.h" void __init *s3c_set_platdata(void *pd, size_t pdsize, struct platform_device *pdev) diff --git a/arch/arm/mach-s3c24xx/pll-s3c2410.c b/arch/arm/mach-s3c/pll-s3c2410.c index 0561f79ddce8..3fbc99eaa4a2 100644 --- a/arch/arm/mach-s3c24xx/pll-s3c2410.c +++ b/arch/arm/mach-s3c/pll-s3c2410.c @@ -15,8 +15,8 @@ #include <linux/clk.h> #include <linux/err.h> -#include <plat/cpu.h> -#include <plat/cpu-freq-core.h> +#include <linux/soc/samsung/s3c-cpufreq-core.h> +#include <linux/soc/samsung/s3c-pm.h> /* This array should be sorted in ascending order of the frequencies */ static struct cpufreq_frequency_table pll_vals_12MHz[] = { diff --git a/arch/arm/mach-s3c24xx/pll-s3c2440-12000000.c b/arch/arm/mach-s3c/pll-s3c2440-12000000.c index 2ec3a2f9a6a5..fdb8e8c2fe3b 100644 --- a/arch/arm/mach-s3c24xx/pll-s3c2440-12000000.c +++ b/arch/arm/mach-s3c/pll-s3c2440-12000000.c @@ -13,8 +13,8 @@ #include <linux/clk.h> #include <linux/err.h> -#include <plat/cpu.h> -#include <plat/cpu-freq-core.h> +#include <linux/soc/samsung/s3c-cpufreq-core.h> +#include <linux/soc/samsung/s3c-pm.h> /* This array should be sorted in ascending order of the frequencies */ static struct cpufreq_frequency_table s3c2440_plls_12[] = { diff --git a/arch/arm/mach-s3c24xx/pll-s3c2440-16934400.c b/arch/arm/mach-s3c/pll-s3c2440-16934400.c index 4b3d9e36c6bb..438b6fc099a4 100644 --- a/arch/arm/mach-s3c24xx/pll-s3c2440-16934400.c +++ b/arch/arm/mach-s3c/pll-s3c2440-16934400.c @@ -13,8 +13,8 @@ #include <linux/clk.h> #include <linux/err.h> -#include <plat/cpu.h> -#include <plat/cpu-freq-core.h> +#include <linux/soc/samsung/s3c-cpufreq-core.h> +#include <linux/soc/samsung/s3c-pm.h> /* This array should be sorted in ascending order of the frequencies */ static struct cpufreq_frequency_table s3c2440_plls_169344[] = { diff --git a/arch/arm/plat-samsung/pm-common.c b/arch/arm/mach-s3c/pm-common.c index 59a10c6dcba1..618bd4499cae 100644 --- a/arch/arm/plat-samsung/pm-common.c +++ b/arch/arm/mach-s3c/pm-common.c @@ -12,7 +12,7 @@ #include <linux/io.h> #include <linux/kernel.h> -#include <plat/pm-common.h> +#include "pm-common.h" /* helper functions to save and restore register state */ @@ -55,6 +55,8 @@ void s3c_pm_do_restore(const struct sleep_save *ptr, int count) /** * s3c_pm_do_restore_core() - early restore register values from save list. + * @ptr: Pointer to an array of registers. + * @count: Size of the ptr array. * * This is similar to s3c_pm_do_restore() except we try and minimise the * side effects of the function in case registers that hardware might need diff --git a/arch/arm/mach-s3c/pm-common.h b/arch/arm/mach-s3c/pm-common.h new file mode 100644 index 000000000000..18b9607e1e39 --- /dev/null +++ b/arch/arm/mach-s3c/pm-common.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2013 Samsung Electronics Co., Ltd. + * Tomasz Figa <t.figa@samsung.com> + * Copyright (c) 2004 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Written by Ben Dooks, <ben@simtec.co.uk> + */ + +#ifndef __PLAT_SAMSUNG_PM_COMMON_H +#define __PLAT_SAMSUNG_PM_COMMON_H __FILE__ + +#include <linux/irq.h> +#include <linux/soc/samsung/s3c-pm.h> + +/* sleep save info */ + +/** + * struct sleep_save - save information for shared peripherals. + * @reg: Pointer to the register to save. + * @val: Holder for the value saved from reg. + * + * This describes a list of registers which is used by the pm core and + * other subsystem to save and restore register values over suspend. + */ +struct sleep_save { + void __iomem *reg; + unsigned long val; +}; + +#define SAVE_ITEM(x) \ + { .reg = (x) } + +/* helper functions to save/restore lists of registers. */ + +extern void s3c_pm_do_save(struct sleep_save *ptr, int count); +extern void s3c_pm_do_restore(const struct sleep_save *ptr, int count); +extern void s3c_pm_do_restore_core(const struct sleep_save *ptr, int count); + +#endif diff --git a/arch/arm/mach-s3c24xx/include/mach/pm-core.h b/arch/arm/mach-s3c/pm-core-s3c24xx.h index 5e4ce89d0158..bcb7978a4e85 100644 --- a/arch/arm/mach-s3c24xx/include/mach/pm-core.h +++ b/arch/arm/mach-s3c/pm-core-s3c24xx.h @@ -11,10 +11,12 @@ #include <linux/io.h> #include "regs-clock.h" -#include "regs-irq.h" +#include "regs-irq-s3c24xx.h" +#include <mach/irqs.h> static inline void s3c_pm_debug_init_uart(void) { +#ifdef CONFIG_SAMSUNG_PM_DEBUG unsigned long tmp = __raw_readl(S3C2410_CLKCON); /* re-start uart clocks */ @@ -24,6 +26,7 @@ static inline void s3c_pm_debug_init_uart(void) __raw_writel(tmp, S3C2410_CLKCON); udelay(10); +#endif } static inline void s3c_pm_arch_prepare_irqs(void) @@ -75,11 +78,6 @@ static inline void s3c_pm_arch_show_resume_irqs(void) s3c_irqwake_eintmask); } -static inline void s3c_pm_arch_update_uart(void __iomem *regs, - struct pm_uart_save *save) -{ -} - static inline void s3c_pm_restored_gpios(void) { } static inline void samsung_pm_saved_gpios(void) { } diff --git a/arch/arm/mach-s3c64xx/include/mach/pm-core.h b/arch/arm/mach-s3c/pm-core-s3c64xx.h index bbf79ed28583..06f564e5cf63 100644 --- a/arch/arm/mach-s3c64xx/include/mach/pm-core.h +++ b/arch/arm/mach-s3c/pm-core-s3c64xx.h @@ -14,12 +14,13 @@ #include <linux/serial_s3c.h> #include <linux/delay.h> -#include <mach/regs-gpio.h> -#include <mach/regs-clock.h> -#include <mach/map.h> +#include "regs-gpio.h" +#include "regs-clock.h" +#include "map.h" static inline void s3c_pm_debug_init_uart(void) { +#ifdef CONFIG_SAMSUNG_PM_DEBUG u32 tmp = __raw_readl(S3C_PCLK_GATE); /* As a note, since the S3C64XX UARTs generally have multiple @@ -35,6 +36,7 @@ static inline void s3c_pm_debug_init_uart(void) __raw_writel(tmp, S3C_PCLK_GATE); udelay(10); +#endif } static inline void s3c_pm_arch_prepare_irqs(void) @@ -63,48 +65,6 @@ static inline void s3c_pm_arch_show_resume_irqs(void) #define s3c_irqwake_intallow 0 #endif -static inline void s3c_pm_arch_update_uart(void __iomem *regs, - struct pm_uart_save *save) -{ - u32 ucon = __raw_readl(regs + S3C2410_UCON); - u32 ucon_clk = ucon & S3C6400_UCON_CLKMASK; - u32 save_clk = save->ucon & S3C6400_UCON_CLKMASK; - u32 new_ucon; - u32 delta; - - /* S3C64XX UART blocks only support level interrupts, so ensure that - * when we restore unused UART blocks we force the level interrupt - * settigs. */ - save->ucon |= S3C2410_UCON_TXILEVEL | S3C2410_UCON_RXILEVEL; - - /* We have a constraint on changing the clock type of the UART - * between UCLKx and PCLK, so ensure that when we restore UCON - * that the CLK field is correctly modified if the bootloader - * has changed anything. - */ - if (ucon_clk != save_clk) { - new_ucon = save->ucon; - delta = ucon_clk ^ save_clk; - - /* change from UCLKx => wrong PCLK, - * either UCLK can be tested for by a bit-test - * with UCLK0 */ - if (ucon_clk & S3C6400_UCON_UCLK0 && - !(save_clk & S3C6400_UCON_UCLK0) && - delta & S3C6400_UCON_PCLK2) { - new_ucon &= ~S3C6400_UCON_UCLK0; - } else if (delta == S3C6400_UCON_PCLK2) { - /* as an precaution, don't change from - * PCLK2 => PCLK or vice-versa */ - new_ucon ^= S3C6400_UCON_PCLK2; - } - - S3C_PMDBG("ucon change %04x => %04x (save=%04x)\n", - ucon, new_ucon, save->ucon); - save->ucon = new_ucon; - } -} - static inline void s3c_pm_restored_gpios(void) { /* ensure sleep mode has been cleared from the system */ diff --git a/arch/arm/mach-s3c/pm-core.h b/arch/arm/mach-s3c/pm-core.h new file mode 100644 index 000000000000..b0e1d277f599 --- /dev/null +++ b/arch/arm/mach-s3c/pm-core.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifdef CONFIG_ARCH_S3C24XX +#include "pm-core-s3c24xx.h" +#endif + +#ifdef CONFIG_ARCH_S3C64XX +#include "pm-core-s3c64xx.h" +#endif diff --git a/arch/arm/plat-samsung/pm-gpio.c b/arch/arm/mach-s3c/pm-gpio.c index cb2e3bc79336..cfdbc2337998 100644 --- a/arch/arm/plat-samsung/pm-gpio.c +++ b/arch/arm/mach-s3c/pm-gpio.c @@ -13,10 +13,10 @@ #include <linux/io.h> #include <linux/gpio.h> -#include <mach/gpio-samsung.h> +#include "gpio-samsung.h" -#include <plat/gpio-core.h> -#include <plat/pm.h> +#include "gpio-core.h" +#include "pm.h" /* PM GPIO helpers */ diff --git a/arch/arm/mach-s3c24xx/pm-h1940.S b/arch/arm/mach-s3c/pm-h1940.S index a7bbe336ac6b..3bf6685123cb 100644 --- a/arch/arm/mach-s3c24xx/pm-h1940.S +++ b/arch/arm/mach-s3c/pm-h1940.S @@ -7,10 +7,9 @@ #include <linux/linkage.h> #include <asm/assembler.h> -#include <mach/hardware.h> -#include <mach/map.h> +#include "map.h" -#include <mach/regs-gpio.h> +#include "regs-gpio.h" .text .global h1940_pm_return diff --git a/arch/arm/mach-s3c24xx/pm-s3c2410.c b/arch/arm/mach-s3c/pm-s3c2410.c index 2d8ea701380a..a66419883735 100644 --- a/arch/arm/mach-s3c24xx/pm-s3c2410.c +++ b/arch/arm/mach-s3c/pm-s3c2410.c @@ -16,13 +16,12 @@ #include <asm/mach-types.h> -#include <mach/hardware.h> -#include <mach/regs-gpio.h> -#include <mach/gpio-samsung.h> +#include "regs-gpio.h" +#include "gpio-samsung.h" -#include <plat/gpio-cfg.h> -#include <plat/cpu.h> -#include <plat/pm.h> +#include "gpio-cfg.h" +#include "cpu.h" +#include "pm.h" #include "h1940.h" diff --git a/arch/arm/mach-s3c24xx/pm-s3c2412.c b/arch/arm/mach-s3c/pm-s3c2412.c index 2dfdaab0aa1f..6a9604477c9e 100644 --- a/arch/arm/mach-s3c24xx/pm-s3c2412.c +++ b/arch/arm/mach-s3c/pm-s3c2412.c @@ -19,14 +19,14 @@ #include <asm/cacheflush.h> #include <asm/irq.h> -#include <mach/hardware.h> -#include <mach/regs-gpio.h> +#include <mach/irqs.h> +#include "regs-gpio.h" -#include <plat/cpu.h> -#include <plat/pm.h> -#include <plat/wakeup-mask.h> +#include "cpu.h" +#include "pm.h" +#include "wakeup-mask.h" -#include "regs-dsc.h" +#include "regs-dsc-s3c24xx.h" #include "s3c2412-power.h" extern void s3c2412_sleep_enter(void); diff --git a/arch/arm/mach-s3c24xx/pm-s3c2416.c b/arch/arm/mach-s3c/pm-s3c2416.c index 9a2f05e279d4..f69ad84cf4ff 100644 --- a/arch/arm/mach-s3c24xx/pm-s3c2416.c +++ b/arch/arm/mach-s3c/pm-s3c2416.c @@ -11,10 +11,10 @@ #include <asm/cacheflush.h> -#include <mach/regs-s3c2443-clock.h> +#include "regs-s3c2443-clock.h" -#include <plat/cpu.h> -#include <plat/pm.h> +#include "cpu.h" +#include "pm.h" #include "s3c2412-power.h" diff --git a/arch/arm/mach-s3c24xx/pm.c b/arch/arm/mach-s3c/pm-s3c24xx.c index c64988c609ad..3a8f5c38882e 100644 --- a/arch/arm/mach-s3c24xx/pm.c +++ b/arch/arm/mach-s3c/pm-s3c24xx.c @@ -21,17 +21,17 @@ #include <linux/serial_s3c.h> #include <linux/io.h> -#include <mach/regs-clock.h> -#include <mach/regs-gpio.h> -#include <mach/regs-irq.h> -#include <mach/gpio-samsung.h> +#include "regs-clock.h" +#include "regs-gpio.h" +#include "regs-irq.h" +#include "gpio-samsung.h" #include <asm/mach/time.h> -#include <plat/gpio-cfg.h> -#include <plat/pm.h> +#include "gpio-cfg.h" +#include "pm.h" -#include "regs-mem.h" +#include "regs-mem-s3c24xx.h" #define PFX "s3c24xx-pm: " diff --git a/arch/arm/mach-s3c64xx/pm.c b/arch/arm/mach-s3c/pm-s3c64xx.c index fd6dbb263ed5..4f1778123dee 100644 --- a/arch/arm/mach-s3c64xx/pm.c +++ b/arch/arm/mach-s3c/pm-s3c64xx.c @@ -14,22 +14,22 @@ #include <linux/gpio.h> #include <linux/pm_domain.h> -#include <mach/map.h> +#include "map.h" #include <mach/irqs.h> -#include <plat/cpu.h> -#include <plat/devs.h> -#include <plat/pm.h> -#include <plat/wakeup-mask.h> +#include "cpu.h" +#include "devs.h" +#include "pm.h" +#include "wakeup-mask.h" -#include <mach/regs-gpio.h> -#include <mach/regs-clock.h> -#include <mach/gpio-samsung.h> +#include "regs-gpio.h" +#include "regs-clock.h" +#include "gpio-samsung.h" -#include "regs-gpio-memport.h" -#include "regs-modem.h" -#include "regs-sys.h" -#include "regs-syscon-power.h" +#include "regs-gpio-memport-s3c64xx.h" +#include "regs-modem-s3c64xx.h" +#include "regs-sys-s3c64xx.h" +#include "regs-syscon-power-s3c64xx.h" struct s3c64xx_pm_domain { char *const name; @@ -305,6 +305,56 @@ static void s3c64xx_pm_prepare(void) __raw_writel(__raw_readl(S3C64XX_WAKEUP_STAT), S3C64XX_WAKEUP_STAT); } +#ifdef CONFIG_SAMSUNG_PM_DEBUG +void s3c_pm_arch_update_uart(void __iomem *regs, struct pm_uart_save *save) +{ + u32 ucon; + u32 ucon_clk + u32 save_clk; + u32 new_ucon; + u32 delta; + + if (!soc_is_s3c64xx()) + return; + + ucon = __raw_readl(regs + S3C2410_UCON); + ucon_clk = ucon & S3C6400_UCON_CLKMASK; + sav_clk = save->ucon & S3C6400_UCON_CLKMASK; + + /* S3C64XX UART blocks only support level interrupts, so ensure that + * when we restore unused UART blocks we force the level interrupt + * settigs. */ + save->ucon |= S3C2410_UCON_TXILEVEL | S3C2410_UCON_RXILEVEL; + + /* We have a constraint on changing the clock type of the UART + * between UCLKx and PCLK, so ensure that when we restore UCON + * that the CLK field is correctly modified if the bootloader + * has changed anything. + */ + if (ucon_clk != save_clk) { + new_ucon = save->ucon; + delta = ucon_clk ^ save_clk; + + /* change from UCLKx => wrong PCLK, + * either UCLK can be tested for by a bit-test + * with UCLK0 */ + if (ucon_clk & S3C6400_UCON_UCLK0 && + !(save_clk & S3C6400_UCON_UCLK0) && + delta & S3C6400_UCON_PCLK2) { + new_ucon &= ~S3C6400_UCON_UCLK0; + } else if (delta == S3C6400_UCON_PCLK2) { + /* as an precaution, don't change from + * PCLK2 => PCLK or vice-versa */ + new_ucon ^= S3C6400_UCON_PCLK2; + } + + S3C_PMDBG("ucon change %04x => %04x (save=%04x)\n", + ucon, new_ucon, save->ucon); + save->ucon = new_ucon; + } +} +#endif + int __init s3c64xx_pm_init(void) { int i; diff --git a/arch/arm/plat-samsung/pm.c b/arch/arm/mach-s3c/pm.c index d6bfd66592b0..c563bb9d92be 100644 --- a/arch/arm/plat-samsung/pm.c +++ b/arch/arm/mach-s3c/pm.c @@ -18,15 +18,16 @@ #include <asm/cacheflush.h> #include <asm/suspend.h> -#include <mach/map.h> -#include <mach/regs-clock.h> -#include <mach/regs-irq.h> +#include "map.h" +#include "regs-clock.h" +#include "regs-irq.h" #include <mach/irqs.h> #include <asm/irq.h> -#include <plat/pm.h> -#include <mach/pm-core.h> +#include "cpu.h" +#include "pm.h" +#include "pm-core.h" /* for external use */ @@ -70,8 +71,7 @@ static int s3c_pm_enter(suspend_state_t state) { int ret; /* ensure the debug is initialised (if enabled) */ - - s3c_pm_debug_init(); + s3c_pm_debug_init_uart(); S3C_PMDBG("%s(%d)\n", __func__, state); @@ -100,7 +100,7 @@ static int s3c_pm_enter(suspend_state_t state) samsung_pm_saved_gpios(); } - s3c_pm_save_uarts(); + s3c_pm_save_uarts(soc_is_s3c2410()); s3c_pm_save_core(); /* set the irq configuration for wake */ @@ -137,14 +137,14 @@ static int s3c_pm_enter(suspend_state_t state) /* restore the system state */ s3c_pm_restore_core(); - s3c_pm_restore_uarts(); + s3c_pm_restore_uarts(soc_is_s3c2410()); if (!of_have_populated_dt()) { samsung_pm_restore_gpios(); s3c_pm_restored_gpios(); } - s3c_pm_debug_init(); + s3c_pm_debug_init_uart(); /* check what irq (if any) restored the system */ diff --git a/arch/arm/plat-samsung/include/plat/pm.h b/arch/arm/mach-s3c/pm.h index 2746137f9794..eed61e585457 100644 --- a/arch/arm/plat-samsung/include/plat/pm.h +++ b/arch/arm/mach-s3c/pm.h @@ -11,7 +11,7 @@ * management */ -#include <plat/pm-common.h> +#include "pm-common.h" struct device; diff --git a/arch/arm/plat-samsung/include/plat/pwm-core.h b/arch/arm/mach-s3c/pwm-core.h index 05e3448642a1..05e3448642a1 100644 --- a/arch/arm/plat-samsung/include/plat/pwm-core.h +++ b/arch/arm/mach-s3c/pwm-core.h diff --git a/arch/arm/plat-samsung/include/plat/regs-adc.h b/arch/arm/mach-s3c/regs-adc.h index 58953c7381dd..58953c7381dd 100644 --- a/arch/arm/plat-samsung/include/plat/regs-adc.h +++ b/arch/arm/mach-s3c/regs-adc.h diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-clock.h b/arch/arm/mach-s3c/regs-clock-s3c24xx.h index 7ca3dd4f13c0..933ddb5eedec 100644 --- a/arch/arm/mach-s3c24xx/include/mach/regs-clock.h +++ b/arch/arm/mach-s3c/regs-clock-s3c24xx.h @@ -9,6 +9,8 @@ #ifndef __ASM_ARM_REGS_CLOCK #define __ASM_ARM_REGS_CLOCK +#include "map.h" + #define S3C2410_CLKREG(x) ((x) + S3C24XX_VA_CLKPWR) #define S3C2410_PLLVAL(_m,_p,_s) ((_m) << 12 | ((_p) << 4) | ((_s))) diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-clock.h b/arch/arm/mach-s3c/regs-clock-s3c64xx.h index 35a68767b318..35a68767b318 100644 --- a/arch/arm/mach-s3c64xx/include/mach/regs-clock.h +++ b/arch/arm/mach-s3c/regs-clock-s3c64xx.h diff --git a/arch/arm/mach-s3c/regs-clock.h b/arch/arm/mach-s3c/regs-clock.h new file mode 100644 index 000000000000..7df31f203d28 --- /dev/null +++ b/arch/arm/mach-s3c/regs-clock.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifdef CONFIG_ARCH_S3C24XX +#include "regs-clock-s3c24xx.h" +#endif + +#ifdef CONFIG_ARCH_S3C64XX +#include "regs-clock-s3c64xx.h" +#endif diff --git a/arch/arm/mach-s3c24xx/regs-dsc.h b/arch/arm/mach-s3c/regs-dsc-s3c24xx.h index b500636276f2..8b8b572aef04 100644 --- a/arch/arm/mach-s3c24xx/regs-dsc.h +++ b/arch/arm/mach-s3c/regs-dsc-s3c24xx.h @@ -7,8 +7,8 @@ */ -#ifndef __ASM_ARCH_REGS_DSC_H -#define __ASM_ARCH_REGS_DSC_H __FILE__ +#ifndef __ASM_ARCH_REGS_DSC_S3C24XX_H +#define __ASM_ARCH_REGS_DSC_S3C24XX_H __FILE__ /* S3C2412 */ #define S3C2412_DSC0 S3C2410_GPIOREG(0xdc) @@ -18,5 +18,5 @@ #define S3C2440_DSC0 S3C2410_GPIOREG(0xc4) #define S3C2440_DSC1 S3C2410_GPIOREG(0xc8) -#endif /* __ASM_ARCH_REGS_DSC_H */ +#endif /* __ASM_ARCH_REGS_DSC_S3C24XX_H */ diff --git a/arch/arm/mach-s3c64xx/regs-gpio-memport.h b/arch/arm/mach-s3c/regs-gpio-memport-s3c64xx.h index 589afe1132d6..589afe1132d6 100644 --- a/arch/arm/mach-s3c64xx/regs-gpio-memport.h +++ b/arch/arm/mach-s3c/regs-gpio-memport-s3c64xx.h diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-gpio.h b/arch/arm/mach-s3c/regs-gpio-s3c24xx.h index 594e967c0673..9a7e262268a7 100644 --- a/arch/arm/mach-s3c24xx/include/mach/regs-gpio.h +++ b/arch/arm/mach-s3c/regs-gpio-s3c24xx.h @@ -10,6 +10,8 @@ #ifndef __ASM_ARCH_REGS_GPIO_H #define __ASM_ARCH_REGS_GPIO_H +#include "map-s3c.h" + #define S3C24XX_MISCCR S3C24XX_GPIOREG2(0x80) /* general configuration options */ diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-gpio.h b/arch/arm/mach-s3c/regs-gpio-s3c64xx.h index 592a2be3d2aa..592a2be3d2aa 100644 --- a/arch/arm/mach-s3c64xx/include/mach/regs-gpio.h +++ b/arch/arm/mach-s3c/regs-gpio-s3c64xx.h diff --git a/arch/arm/mach-s3c/regs-gpio.h b/arch/arm/mach-s3c/regs-gpio.h new file mode 100644 index 000000000000..0d41cb76d440 --- /dev/null +++ b/arch/arm/mach-s3c/regs-gpio.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifdef CONFIG_ARCH_S3C24XX +#include "regs-gpio-s3c24xx.h" +#endif + +#ifdef CONFIG_ARCH_S3C64XX +#include "regs-gpio-s3c64xx.h" +#endif diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-irq.h b/arch/arm/mach-s3c/regs-irq-s3c24xx.h index 8d8e669e3903..c0b97b203415 100644 --- a/arch/arm/mach-s3c24xx/include/mach/regs-irq.h +++ b/arch/arm/mach-s3c/regs-irq-s3c24xx.h @@ -8,6 +8,8 @@ #ifndef ___ASM_ARCH_REGS_IRQ_H #define ___ASM_ARCH_REGS_IRQ_H +#include "map-s3c.h" + /* interrupt controller */ #define S3C2410_IRQREG(x) ((x) + S3C24XX_VA_IRQ) diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-irq.h b/arch/arm/mach-s3c/regs-irq-s3c64xx.h index b18c7bcb61c5..b18c7bcb61c5 100644 --- a/arch/arm/mach-s3c64xx/include/mach/regs-irq.h +++ b/arch/arm/mach-s3c/regs-irq-s3c64xx.h diff --git a/arch/arm/mach-s3c/regs-irq.h b/arch/arm/mach-s3c/regs-irq.h new file mode 100644 index 000000000000..57f0dda8dbf5 --- /dev/null +++ b/arch/arm/mach-s3c/regs-irq.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifdef CONFIG_ARCH_S3C24XX +#include "regs-irq-s3c24xx.h" +#endif + +#ifdef CONFIG_ARCH_S3C64XX +#include "regs-irq-s3c64xx.h" +#endif diff --git a/arch/arm/plat-samsung/include/plat/regs-irqtype.h b/arch/arm/mach-s3c/regs-irqtype.h index ec5c4c5fdd8f..ec5c4c5fdd8f 100644 --- a/arch/arm/plat-samsung/include/plat/regs-irqtype.h +++ b/arch/arm/mach-s3c/regs-irqtype.h diff --git a/arch/arm/mach-s3c24xx/regs-mem.h b/arch/arm/mach-s3c/regs-mem-s3c24xx.h index 2f3bc48b5890..8fed34a1672a 100644 --- a/arch/arm/mach-s3c24xx/regs-mem.h +++ b/arch/arm/mach-s3c/regs-mem-s3c24xx.h @@ -9,6 +9,8 @@ #ifndef __ARCH_ARM_MACH_S3C24XX_REGS_MEM_H #define __ARCH_ARM_MACH_S3C24XX_REGS_MEM_H __FILE__ +#include "map-s3c.h" + #define S3C2410_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x)) #define S3C2410_BWSCON S3C2410_MEMREG(0x00) diff --git a/arch/arm/mach-s3c64xx/regs-modem.h b/arch/arm/mach-s3c/regs-modem-s3c64xx.h index 136ad44291bf..136ad44291bf 100644 --- a/arch/arm/mach-s3c64xx/regs-modem.h +++ b/arch/arm/mach-s3c/regs-modem-s3c64xx.h diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-s3c2443-clock.h b/arch/arm/mach-s3c/regs-s3c2443-clock.h index 6bf924612b06..b3b670d463db 100644 --- a/arch/arm/mach-s3c24xx/include/mach/regs-s3c2443-clock.h +++ b/arch/arm/mach-s3c/regs-s3c2443-clock.h @@ -10,6 +10,9 @@ #ifndef __ASM_ARM_REGS_S3C2443_CLOCK #define __ASM_ARM_REGS_S3C2443_CLOCK +#include <linux/delay.h> +#include "map-s3c.h" + #define S3C2443_CLKREG(x) ((x) + S3C24XX_VA_CLKPWR) #define S3C2443_PLLCON_MDIVSHIFT 16 @@ -184,5 +187,52 @@ s3c2443_get_epll(unsigned int pllval, unsigned int baseclk) return (unsigned int)fvco; } +static inline void s3c_hsudc_init_phy(void) +{ + u32 cfg; + + cfg = readl(S3C2443_PWRCFG) | S3C2443_PWRCFG_USBPHY; + writel(cfg, S3C2443_PWRCFG); + + cfg = readl(S3C2443_URSTCON); + cfg |= (S3C2443_URSTCON_FUNCRST | S3C2443_URSTCON_PHYRST); + writel(cfg, S3C2443_URSTCON); + mdelay(1); + + cfg = readl(S3C2443_URSTCON); + cfg &= ~(S3C2443_URSTCON_FUNCRST | S3C2443_URSTCON_PHYRST); + writel(cfg, S3C2443_URSTCON); + + cfg = readl(S3C2443_PHYCTRL); + cfg &= ~(S3C2443_PHYCTRL_CLKSEL | S3C2443_PHYCTRL_DSPORT); + cfg |= (S3C2443_PHYCTRL_EXTCLK | S3C2443_PHYCTRL_PLLSEL); + writel(cfg, S3C2443_PHYCTRL); + + cfg = readl(S3C2443_PHYPWR); + cfg &= ~(S3C2443_PHYPWR_FSUSPEND | S3C2443_PHYPWR_PLL_PWRDN | + S3C2443_PHYPWR_XO_ON | S3C2443_PHYPWR_PLL_REFCLK | + S3C2443_PHYPWR_ANALOG_PD); + cfg |= S3C2443_PHYPWR_COMMON_ON; + writel(cfg, S3C2443_PHYPWR); + + cfg = readl(S3C2443_UCLKCON); + cfg |= (S3C2443_UCLKCON_DETECT_VBUS | S3C2443_UCLKCON_FUNC_CLKEN | + S3C2443_UCLKCON_TCLKEN); + writel(cfg, S3C2443_UCLKCON); +} + +static inline void s3c_hsudc_uninit_phy(void) +{ + u32 cfg; + + cfg = readl(S3C2443_PWRCFG) & ~S3C2443_PWRCFG_USBPHY; + writel(cfg, S3C2443_PWRCFG); + + writel(S3C2443_PHYPWR_FSUSPEND, S3C2443_PHYPWR); + + cfg = readl(S3C2443_UCLKCON) & ~S3C2443_UCLKCON_FUNC_CLKEN; + writel(cfg, S3C2443_UCLKCON); +} + #endif /* __ASM_ARM_REGS_S3C2443_CLOCK */ diff --git a/arch/arm/mach-s3c64xx/regs-srom.h b/arch/arm/mach-s3c/regs-srom-s3c64xx.h index 2b37988bdf94..2b37988bdf94 100644 --- a/arch/arm/mach-s3c64xx/regs-srom.h +++ b/arch/arm/mach-s3c/regs-srom-s3c64xx.h diff --git a/arch/arm/mach-s3c64xx/regs-sys.h b/arch/arm/mach-s3c/regs-sys-s3c64xx.h index 3687325e2bb4..3687325e2bb4 100644 --- a/arch/arm/mach-s3c64xx/regs-sys.h +++ b/arch/arm/mach-s3c/regs-sys-s3c64xx.h diff --git a/arch/arm/mach-s3c64xx/regs-syscon-power.h b/arch/arm/mach-s3c/regs-syscon-power-s3c64xx.h index a35811cc656e..a35811cc656e 100644 --- a/arch/arm/mach-s3c64xx/regs-syscon-power.h +++ b/arch/arm/mach-s3c/regs-syscon-power-s3c64xx.h diff --git a/arch/arm/mach-s3c64xx/regs-usb-hsotg-phy.h b/arch/arm/mach-s3c/regs-usb-hsotg-phy-s3c64xx.h index deb1dd2d9c83..deb1dd2d9c83 100644 --- a/arch/arm/mach-s3c64xx/regs-usb-hsotg-phy.h +++ b/arch/arm/mach-s3c/regs-usb-hsotg-phy-s3c64xx.h diff --git a/arch/arm/mach-s3c24xx/include/mach/rtc-core.h b/arch/arm/mach-s3c/rtc-core-s3c24xx.h index 88510333b96b..e7258b2423fc 100644 --- a/arch/arm/mach-s3c24xx/include/mach/rtc-core.h +++ b/arch/arm/mach-s3c/rtc-core-s3c24xx.h @@ -5,8 +5,8 @@ * Samsung RTC Controller core functions */ -#ifndef __RTC_CORE_H -#define __RTC_CORE_H __FILE__ +#ifndef __RTC_CORE_S3C24XX_H +#define __RTC_CORE_S3C24XX_H __FILE__ /* These functions are only for use with the core support code, such as * the cpu specific initialisation code @@ -20,4 +20,4 @@ static inline void s3c_rtc_setname(char *name) s3c_device_rtc.name = name; } -#endif /* __RTC_CORE_H */ +#endif /* __RTC_CORE_S3C24XX_H */ diff --git a/arch/arm/mach-s3c24xx/s3c2410.c b/arch/arm/mach-s3c/s3c2410.c index 21fd5404bc98..4d39d9939c2f 100644 --- a/arch/arm/mach-s3c24xx/s3c2410.c +++ b/arch/arm/mach-s3c/s3c2410.c @@ -25,28 +25,27 @@ #include <asm/mach/map.h> #include <asm/mach/irq.h> -#include <mach/hardware.h> -#include <mach/gpio-samsung.h> +#include "map.h" +#include "gpio-samsung.h" #include <asm/irq.h> #include <asm/system_misc.h> -#include <plat/cpu-freq.h> -#include <mach/regs-clock.h> +#include "regs-clock.h" -#include <plat/cpu.h> -#include <plat/devs.h> -#include <plat/pm.h> +#include "cpu.h" +#include "devs.h" +#include "pm.h" -#include <plat/gpio-core.h> -#include <plat/gpio-cfg.h> -#include <plat/gpio-cfg-helpers.h> +#include "gpio-core.h" +#include "gpio-cfg.h" +#include "gpio-cfg-helpers.h" -#include "common.h" +#include "s3c24xx.h" /* Initial IO mappings */ -static struct map_desc s3c2410_iodesc[] __initdata = { +static struct map_desc s3c2410_iodesc[] __initdata __maybe_unused = { IODESC_ENT(CLKPWR), IODESC_ENT(TIMER), IODESC_ENT(WATCHDOG), diff --git a/arch/arm/mach-s3c24xx/s3c2412-power.h b/arch/arm/mach-s3c/s3c2412-power.h index 0031cfaa1d76..0031cfaa1d76 100644 --- a/arch/arm/mach-s3c24xx/s3c2412-power.h +++ b/arch/arm/mach-s3c/s3c2412-power.h diff --git a/arch/arm/mach-s3c24xx/s3c2412.c b/arch/arm/mach-s3c/s3c2412.c index 8fe4d4670dcb..0b1ca78c9d2a 100644 --- a/arch/arm/mach-s3c24xx/s3c2412.c +++ b/arch/arm/mach-s3c/s3c2412.c @@ -29,19 +29,17 @@ #include <asm/irq.h> #include <asm/system_misc.h> -#include <mach/hardware.h> -#include <mach/regs-clock.h> -#include <mach/regs-gpio.h> - -#include <plat/cpu.h> -#include <plat/cpu-freq.h> -#include <plat/devs.h> -#include <plat/pm.h> -#include <plat/regs-spi.h> - -#include "common.h" -#include "nand-core.h" -#include "regs-dsc.h" +#include "map.h" +#include "regs-clock.h" +#include "regs-gpio.h" + +#include "cpu.h" +#include "devs.h" +#include "pm.h" + +#include "s3c24xx.h" +#include "nand-core-s3c24xx.h" +#include "regs-dsc-s3c24xx.h" #include "s3c2412-power.h" #ifndef CONFIG_CPU_S3C2412_ONLY @@ -57,7 +55,7 @@ static inline void s3c2412_init_gpio2(void) /* Initial IO mappings */ -static struct map_desc s3c2412_iodesc[] __initdata = { +static struct map_desc s3c2412_iodesc[] __initdata __maybe_unused = { IODESC_ENT(CLKPWR), IODESC_ENT(TIMER), IODESC_ENT(WATCHDOG), diff --git a/arch/arm/mach-s3c24xx/include/mach/s3c2412.h b/arch/arm/mach-s3c/s3c2412.h index 4ff83f956cfb..ed09a0e13bd8 100644 --- a/arch/arm/mach-s3c24xx/include/mach/s3c2412.h +++ b/arch/arm/mach-s3c/s3c2412.h @@ -8,6 +8,8 @@ #ifndef __ARCH_ARM_MACH_S3C24XX_S3C2412_H #define __ARCH_ARM_MACH_S3C24XX_S3C2412_H __FILE__ +#include "map-s3c.h" + #define S3C2412_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x)) #define S3C2412_EBIREG(x) (S3C2412_VA_EBI + (x)) diff --git a/arch/arm/mach-s3c24xx/s3c2416.c b/arch/arm/mach-s3c/s3c2416.c index 9514196cad8c..126e6ed29713 100644 --- a/arch/arm/mach-s3c24xx/s3c2416.c +++ b/arch/arm/mach-s3c/s3c2416.c @@ -26,32 +26,32 @@ #include <asm/mach/map.h> #include <asm/mach/irq.h> -#include <mach/hardware.h> -#include <mach/gpio-samsung.h> +#include "map.h" +#include "gpio-samsung.h" #include <asm/proc-fns.h> #include <asm/irq.h> #include <asm/system_misc.h> -#include <mach/regs-s3c2443-clock.h> -#include <mach/rtc-core.h> +#include "regs-s3c2443-clock.h" +#include "rtc-core-s3c24xx.h" -#include <plat/gpio-core.h> -#include <plat/gpio-cfg.h> -#include <plat/gpio-cfg-helpers.h> -#include <plat/devs.h> -#include <plat/cpu.h> -#include <plat/sdhci.h> -#include <plat/pm.h> +#include "gpio-core.h" +#include "gpio-cfg.h" +#include "gpio-cfg-helpers.h" +#include "devs.h" +#include "cpu.h" +#include "sdhci.h" +#include "pm.h" -#include <plat/iic-core.h> -#include <plat/adc-core.h> +#include "iic-core.h" +#include "adc-core.h" -#include "common.h" -#include "fb-core.h" -#include "nand-core.h" -#include "spi-core.h" +#include "s3c24xx.h" +#include "fb-core-s3c24xx.h" +#include "nand-core-s3c24xx.h" +#include "spi-core-s3c24xx.h" -static struct map_desc s3c2416_iodesc[] __initdata = { +static struct map_desc s3c2416_iodesc[] __initdata __maybe_unused = { IODESC_ENT(WATCHDOG), IODESC_ENT(CLKPWR), IODESC_ENT(TIMER), diff --git a/arch/arm/mach-s3c24xx/s3c2440.c b/arch/arm/mach-s3c/s3c2440.c index 451d9851b0a7..c6cdee4987e8 100644 --- a/arch/arm/mach-s3c24xx/s3c2440.c +++ b/arch/arm/mach-s3c/s3c2440.c @@ -23,19 +23,18 @@ #include <asm/mach/map.h> #include <asm/mach/irq.h> -#include <mach/hardware.h> -#include <mach/gpio-samsung.h> #include <asm/irq.h> -#include <plat/devs.h> -#include <plat/cpu.h> -#include <plat/pm.h> +#include "devs.h" +#include "cpu.h" +#include "pm.h" -#include <plat/gpio-core.h> -#include <plat/gpio-cfg.h> -#include <plat/gpio-cfg-helpers.h> +#include "gpio-core.h" +#include "gpio-cfg.h" +#include "gpio-cfg-helpers.h" +#include "gpio-samsung.h" -#include "common.h" +#include "s3c24xx.h" static struct device s3c2440_dev = { .bus = &s3c2440_subsys, diff --git a/arch/arm/mach-s3c24xx/s3c2442.c b/arch/arm/mach-s3c/s3c2442.c index 432d68325c9d..0c0e30b6688f 100644 --- a/arch/arm/mach-s3c24xx/s3c2442.c +++ b/arch/arm/mach-s3c/s3c2442.c @@ -21,21 +21,20 @@ #include <linux/clk.h> #include <linux/io.h> -#include <mach/hardware.h> -#include <mach/gpio-samsung.h> #include <linux/atomic.h> #include <asm/irq.h> -#include <mach/regs-clock.h> +#include "regs-clock.h" -#include <plat/cpu.h> -#include <plat/pm.h> +#include "cpu.h" +#include "pm.h" -#include <plat/gpio-core.h> -#include <plat/gpio-cfg.h> -#include <plat/gpio-cfg-helpers.h> +#include "gpio-core.h" +#include "gpio-cfg.h" +#include "gpio-cfg-helpers.h" +#include "gpio-samsung.h" -#include "common.h" +#include "s3c24xx.h" static struct device s3c2442_dev = { .bus = &s3c2442_subsys, diff --git a/arch/arm/mach-s3c24xx/s3c2443.c b/arch/arm/mach-s3c/s3c2443.c index 4cbeb74cf3d6..08f910144246 100644 --- a/arch/arm/mach-s3c24xx/s3c2443.c +++ b/arch/arm/mach-s3c/s3c2443.c @@ -23,26 +23,28 @@ #include <asm/mach/map.h> #include <asm/mach/irq.h> -#include <mach/hardware.h> -#include <mach/gpio-samsung.h> +#include "map.h" +#include "gpio-samsung.h" +#include <mach/irqs.h> #include <asm/irq.h> #include <asm/system_misc.h> -#include <mach/regs-s3c2443-clock.h> -#include <mach/rtc-core.h> +#include "regs-s3c2443-clock.h" +#include "rtc-core-s3c24xx.h" -#include <plat/gpio-core.h> -#include <plat/gpio-cfg.h> -#include <plat/gpio-cfg-helpers.h> -#include <plat/devs.h> -#include <plat/cpu.h> -#include <plat/adc-core.h> +#include "gpio-core.h" +#include "gpio-cfg.h" +#include "gpio-cfg-helpers.h" +#include "devs.h" +#include "cpu.h" +#include "adc-core.h" -#include "fb-core.h" -#include "nand-core.h" -#include "spi-core.h" +#include "s3c24xx.h" +#include "fb-core-s3c24xx.h" +#include "nand-core-s3c24xx.h" +#include "spi-core-s3c24xx.h" -static struct map_desc s3c2443_iodesc[] __initdata = { +static struct map_desc s3c2443_iodesc[] __initdata __maybe_unused = { IODESC_ENT(WATCHDOG), IODESC_ENT(CLKPWR), IODESC_ENT(TIMER), diff --git a/arch/arm/mach-s3c24xx/s3c244x.c b/arch/arm/mach-s3c/s3c244x.c index a75f588b9d45..95df3491e650 100644 --- a/arch/arm/mach-s3c24xx/s3c244x.c +++ b/arch/arm/mach-s3c/s3c244x.c @@ -25,23 +25,21 @@ #include <asm/mach/map.h> #include <asm/mach/irq.h> -#include <mach/hardware.h> +#include "map.h" #include <asm/irq.h> -#include <plat/cpu-freq.h> +#include "regs-clock.h" +#include "regs-gpio.h" -#include <mach/regs-clock.h> -#include <mach/regs-gpio.h> +#include "devs.h" +#include "cpu.h" +#include "pm.h" -#include <plat/devs.h> -#include <plat/cpu.h> -#include <plat/pm.h> +#include "s3c24xx.h" +#include "nand-core-s3c24xx.h" +#include "regs-dsc-s3c24xx.h" -#include "common.h" -#include "nand-core.h" -#include "regs-dsc.h" - -static struct map_desc s3c244x_iodesc[] __initdata = { +static struct map_desc s3c244x_iodesc[] __initdata __maybe_unused = { IODESC_ENT(CLKPWR), IODESC_ENT(TIMER), IODESC_ENT(WATCHDOG), diff --git a/arch/arm/mach-s3c24xx/common.c b/arch/arm/mach-s3c/s3c24xx.c index 3dc029c2d2cb..ccfed48c98aa 100644 --- a/arch/arm/mach-s3c24xx/common.c +++ b/arch/arm/mach-s3c/s3c24xx.c @@ -17,11 +17,14 @@ #include <linux/platform_device.h> #include <linux/delay.h> #include <linux/io.h> +#include <linux/platform_data/clk-s3c2410.h> #include <linux/platform_data/dma-s3c24xx.h> #include <linux/dmaengine.h> +#include <linux/clk/samsung.h> -#include <mach/hardware.h> -#include <mach/regs-clock.h> +#include "hardware-s3c24xx.h" +#include "map.h" +#include "regs-clock.h" #include <asm/irq.h> #include <asm/cacheflush.h> #include <asm/system_info.h> @@ -30,15 +33,14 @@ #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <mach/regs-gpio.h> -#include <mach/dma.h> +#include "regs-gpio.h" +#include "dma-s3c24xx.h" -#include <plat/cpu.h> -#include <plat/devs.h> -#include <plat/cpu-freq.h> -#include <plat/pwm-core.h> +#include "cpu.h" +#include "devs.h" +#include "pwm-core.h" -#include "common.h" +#include "s3c24xx.h" /* table of supported CPUs */ @@ -137,7 +139,7 @@ static struct cpu_table cpu_ids[] __initdata = { /* minimal IO mapping */ -static struct map_desc s3c_iodesc[] __initdata = { +static struct map_desc s3c_iodesc[] __initdata __maybe_unused = { IODESC_ENT(GPIO), IODESC_ENT(IRQ), IODESC_ENT(MEMCTRL), @@ -220,13 +222,13 @@ void __init s3c24xx_init_io(struct map_desc *mach_desc, int size) samsung_pwm_set_platdata(&s3c24xx_pwm_variant); } -void __init samsung_set_timer_source(unsigned int event, unsigned int source) +void __init s3c24xx_set_timer_source(unsigned int event, unsigned int source) { s3c24xx_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1; s3c24xx_pwm_variant.output_mask &= ~(BIT(event) | BIT(source)); } -void __init samsung_timer_init(void) +void __init s3c24xx_timer_init(void) { unsigned int timer_irqs[SAMSUNG_PWM_NUM] = { IRQ_TIMER0, IRQ_TIMER1, IRQ_TIMER2, IRQ_TIMER3, IRQ_TIMER4, @@ -662,10 +664,17 @@ static struct resource s3c2410_dclk_resource[] = { [0] = DEFINE_RES_MEM(0x56000084, 0x4), }; +static struct s3c2410_clk_platform_data s3c_clk_platform_data = { + .modify_misccr = s3c2410_modify_misccr, +}; + struct platform_device s3c2410_device_dclk = { .name = "s3c2410-dclk", .id = 0, .num_resources = ARRAY_SIZE(s3c2410_dclk_resource), .resource = s3c2410_dclk_resource, + .dev = { + .platform_data = &s3c_clk_platform_data, + }, }; #endif diff --git a/arch/arm/mach-s3c24xx/common.h b/arch/arm/mach-s3c/s3c24xx.h index d087b20e8857..5848bef5bb49 100644 --- a/arch/arm/mach-s3c24xx/common.h +++ b/arch/arm/mach-s3c/s3c24xx.h @@ -10,6 +10,7 @@ #define __ARCH_ARM_MACH_S3C24XX_COMMON_H __FILE__ #include <linux/reboot.h> +#include <mach/irqs.h> struct s3c2410_uartcfg; @@ -108,19 +109,16 @@ extern struct platform_device s3c2443_device_dma; extern struct platform_device s3c2410_device_dclk; -#ifdef CONFIG_S3C2410_COMMON_CLK -void __init s3c2410_common_clk_init(struct device_node *np, unsigned long xti_f, - int current_soc, - void __iomem *reg_base); -#endif -#ifdef CONFIG_S3C2412_COMMON_CLK -void __init s3c2412_common_clk_init(struct device_node *np, unsigned long xti_f, - unsigned long ext_f, void __iomem *reg_base); -#endif -#ifdef CONFIG_S3C2443_COMMON_CLK -void __init s3c2443_common_clk_init(struct device_node *np, unsigned long xti_f, - int current_soc, - void __iomem *reg_base); -#endif +enum s3c24xx_timer_mode { + S3C24XX_PWM0, + S3C24XX_PWM1, + S3C24XX_PWM2, + S3C24XX_PWM3, + S3C24XX_PWM4, +}; + +extern void __init s3c24xx_set_timer_source(enum s3c24xx_timer_mode event, + enum s3c24xx_timer_mode source); +extern void __init s3c24xx_timer_init(void); #endif /* __ARCH_ARM_MACH_S3C24XX_COMMON_H */ diff --git a/arch/arm/mach-s3c64xx/s3c6400.c b/arch/arm/mach-s3c/s3c6400.c index 545eea716db8..802f4fb7462d 100644 --- a/arch/arm/mach-s3c64xx/s3c6400.c +++ b/arch/arm/mach-s3c/s3c6400.c @@ -26,19 +26,17 @@ #include <asm/mach/map.h> #include <asm/mach/irq.h> -#include <mach/hardware.h> #include <asm/irq.h> -#include <plat/cpu-freq.h> -#include <mach/regs-clock.h> +#include "regs-clock.h" -#include <plat/cpu.h> -#include <plat/devs.h> -#include <plat/sdhci.h> -#include <plat/iic-core.h> +#include "cpu.h" +#include "devs.h" +#include "sdhci.h" +#include "iic-core.h" -#include "common.h" -#include "onenand-core.h" +#include "s3c64xx.h" +#include "onenand-core-s3c64xx.h" void __init s3c6400_map_io(void) { diff --git a/arch/arm/mach-s3c64xx/s3c6410.c b/arch/arm/mach-s3c/s3c6410.c index 47e04e019624..dae17d5fd092 100644 --- a/arch/arm/mach-s3c64xx/s3c6410.c +++ b/arch/arm/mach-s3c/s3c6410.c @@ -27,21 +27,20 @@ #include <asm/mach/map.h> #include <asm/mach/irq.h> -#include <mach/hardware.h> #include <asm/irq.h> -#include <plat/cpu-freq.h> -#include <mach/regs-clock.h> +#include <linux/soc/samsung/s3c-pm.h> +#include "regs-clock.h" -#include <plat/cpu.h> -#include <plat/devs.h> -#include <plat/sdhci.h> -#include <plat/adc-core.h> -#include <plat/iic-core.h> +#include "cpu.h" +#include "devs.h" +#include "sdhci.h" +#include "adc-core.h" +#include "iic-core.h" -#include "ata-core.h" -#include "common.h" -#include "onenand-core.h" +#include "ata-core-s3c64xx.h" +#include "s3c64xx.h" +#include "onenand-core-s3c64xx.h" void __init s3c6410_map_io(void) { diff --git a/arch/arm/mach-s3c64xx/common.c b/arch/arm/mach-s3c/s3c64xx.c index 13e91074308a..4dfb648142f2 100644 --- a/arch/arm/mach-s3c64xx/common.c +++ b/arch/arm/mach-s3c/s3c64xx.c @@ -24,6 +24,7 @@ #include <linux/platform_device.h> #include <linux/reboot.h> #include <linux/io.h> +#include <linux/clk/samsung.h> #include <linux/dma-mapping.h> #include <linux/irq.h> #include <linux/gpio.h> @@ -34,22 +35,19 @@ #include <asm/mach/map.h> #include <asm/system_misc.h> -#include <mach/map.h> +#include "map.h" #include <mach/irqs.h> -#include <mach/hardware.h> -#include <mach/regs-gpio.h> -#include <mach/gpio-samsung.h> - -#include <plat/cpu.h> -#include <plat/devs.h> -#include <plat/pm.h> -#include <plat/gpio-cfg.h> -#include <plat/pwm-core.h> -#include <plat/regs-irqtype.h> - -#include "common.h" -#include "irq-uart.h" -#include "watchdog-reset.h" +#include "regs-gpio.h" +#include "gpio-samsung.h" + +#include "cpu.h" +#include "devs.h" +#include "pm.h" +#include "gpio-cfg.h" +#include "pwm-core.h" +#include "regs-irqtype.h" +#include "s3c64xx.h" +#include "irq-uart-s3c64xx.h" /* External clock frequency */ static unsigned long xtal_f __ro_after_init = 12000000; @@ -97,7 +95,12 @@ static struct cpu_table cpu_ids[] __initdata = { /* minimal IO mapping */ -/* see notes on uart map in arch/arm/mach-s3c64xx/include/mach/debug-macro.S */ +/* + * note, for the boot process to work we have to keep the UART + * virtual address aligned to an 1MiB boundary for the L1 + * mapping the head code makes. We keep the UART virtual address + * aligned and add in the offset when we load the value here. + */ #define UART_OFFS (S3C_PA_UART & 0xfffff) static struct map_desc s3c_iodesc[] __initdata = { @@ -170,13 +173,13 @@ static struct samsung_pwm_variant s3c64xx_pwm_variant = { .tclk_mask = (1 << 7) | (1 << 6) | (1 << 5), }; -void __init samsung_set_timer_source(unsigned int event, unsigned int source) +void __init s3c64xx_set_timer_source(unsigned int event, unsigned int source) { s3c64xx_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1; s3c64xx_pwm_variant.output_mask &= ~(BIT(event) | BIT(source)); } -void __init samsung_timer_init(void) +void __init s3c64xx_timer_init(void) { unsigned int timer_irqs[SAMSUNG_PWM_NUM] = { IRQ_TIMER0_VIC, IRQ_TIMER1_VIC, IRQ_TIMER2_VIC, @@ -228,13 +231,7 @@ core_initcall(s3c64xx_dev_init); void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid) { - /* - * FIXME: there is no better place to put this at the moment - * (s3c64xx_clk_init needs ioremap and must happen before init_time - * samsung_wdt_reset_init needs clocks) - */ s3c64xx_clk_init(NULL, xtal_f, xusbxti_f, soc_is_s3c6400(), S3C_VA_SYS); - samsung_wdt_reset_init(S3C_VA_WATCHDOG); printk(KERN_DEBUG "%s: initialising interrupts\n", __func__); @@ -428,12 +425,3 @@ static int __init s3c64xx_init_irq_eint(void) return 0; } arch_initcall(s3c64xx_init_irq_eint); - -void s3c64xx_restart(enum reboot_mode mode, const char *cmd) -{ - if (mode != REBOOT_SOFT) - samsung_wdt_reset(); - - /* if all else fails, or mode was for soft, jump to 0 */ - soft_restart(0); -} diff --git a/arch/arm/mach-s3c64xx/common.h b/arch/arm/mach-s3c/s3c64xx.h index 03670887a764..92258e4f60f6 100644 --- a/arch/arm/mach-s3c64xx/common.h +++ b/arch/arm/mach-s3c/s3c64xx.h @@ -19,11 +19,7 @@ void s3c64xx_init_irq(u32 vic0, u32 vic1); void s3c64xx_init_io(struct map_desc *mach_desc, int size); -void s3c64xx_restart(enum reboot_mode mode, const char *cmd); - struct device_node; -void s3c64xx_clk_init(struct device_node *np, unsigned long xtal_f, - unsigned long xusbxti_f, bool is_s3c6400, void __iomem *reg_base); void s3c64xx_set_xtal_freq(unsigned long freq); void s3c64xx_set_xusbxti_freq(unsigned long freq); @@ -54,4 +50,17 @@ extern struct pl08x_platform_data s3c64xx_dma0_plat_data; extern struct pl08x_platform_data s3c64xx_dma1_plat_data; #endif +/* Samsung HR-Timer Clock mode */ +enum s3c64xx_timer_mode { + S3C64XX_PWM0, + S3C64XX_PWM1, + S3C64XX_PWM2, + S3C64XX_PWM3, + S3C64XX_PWM4, +}; + +extern void __init s3c64xx_set_timer_source(enum s3c64xx_timer_mode event, + enum s3c64xx_timer_mode source); +extern void __init s3c64xx_timer_init(void); + #endif /* __ARCH_ARM_MACH_S3C64XX_COMMON_H */ diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/mach-s3c/sdhci.h index 5731e42ea208..9f9d419e58d7 100644 --- a/arch/arm/plat-samsung/include/plat/sdhci.h +++ b/arch/arm/mach-s3c/sdhci.h @@ -15,7 +15,7 @@ #define __PLAT_S3C_SDHCI_H __FILE__ #include <linux/platform_data/mmc-sdhci-s3c.h> -#include <plat/devs.h> +#include "devs.h" /* s3c_sdhci_set_platdata() - common helper for setting SDHCI platform data * @pd: The default platform data for this device. diff --git a/arch/arm/mach-s3c64xx/setup-fb-24bpp.c b/arch/arm/mach-s3c/setup-fb-24bpp-s3c64xx.c index 2c7178b26ebb..cfa34b55ca21 100644 --- a/arch/arm/mach-s3c64xx/setup-fb-24bpp.c +++ b/arch/arm/mach-s3c/setup-fb-24bpp-s3c64xx.c @@ -12,9 +12,9 @@ #include <linux/fb.h> #include <linux/gpio.h> -#include <plat/fb.h> -#include <plat/gpio-cfg.h> -#include <mach/gpio-samsung.h> +#include "fb.h" +#include "gpio-cfg.h" +#include "gpio-samsung.h" void s3c64xx_fb_gpio_setup_24bpp(void) { diff --git a/arch/arm/mach-s3c24xx/setup-i2c.c b/arch/arm/mach-s3c/setup-i2c-s3c24xx.c index 1a01d44b5910..0d88366b234c 100644 --- a/arch/arm/mach-s3c24xx/setup-i2c.c +++ b/arch/arm/mach-s3c/setup-i2c-s3c24xx.c @@ -10,11 +10,11 @@ struct platform_device; -#include <plat/gpio-cfg.h> #include <linux/platform_data/i2c-s3c2410.h> -#include <mach/hardware.h> -#include <mach/regs-gpio.h> -#include <mach/gpio-samsung.h> + +#include "gpio-cfg.h" +#include "regs-gpio.h" +#include "gpio-samsung.h" void s3c_i2c0_cfg_gpio(struct platform_device *dev) { diff --git a/arch/arm/mach-s3c64xx/setup-i2c0.c b/arch/arm/mach-s3c/setup-i2c0-s3c64xx.c index 552eb50da38c..a6ef8d2bc995 100644 --- a/arch/arm/mach-s3c64xx/setup-i2c0.c +++ b/arch/arm/mach-s3c/setup-i2c0-s3c64xx.c @@ -14,8 +14,8 @@ struct platform_device; /* don't need the contents */ #include <linux/platform_data/i2c-s3c2410.h> -#include <plat/gpio-cfg.h> -#include <mach/gpio-samsung.h> +#include "gpio-cfg.h" +#include "gpio-samsung.h" void s3c_i2c0_cfg_gpio(struct platform_device *dev) { diff --git a/arch/arm/mach-s3c64xx/setup-i2c1.c b/arch/arm/mach-s3c/setup-i2c1-s3c64xx.c index d231f0fc508d..0fe37363d26e 100644 --- a/arch/arm/mach-s3c64xx/setup-i2c1.c +++ b/arch/arm/mach-s3c/setup-i2c1-s3c64xx.c @@ -14,8 +14,8 @@ struct platform_device; /* don't need the contents */ #include <linux/platform_data/i2c-s3c2410.h> -#include <plat/gpio-cfg.h> -#include <mach/gpio-samsung.h> +#include "gpio-cfg.h" +#include "gpio-samsung.h" void s3c_i2c1_cfg_gpio(struct platform_device *dev) { diff --git a/arch/arm/mach-s3c64xx/setup-ide.c b/arch/arm/mach-s3c/setup-ide-s3c64xx.c index 810139a807ce..f11f2b02e49f 100644 --- a/arch/arm/mach-s3c64xx/setup-ide.c +++ b/arch/arm/mach-s3c/setup-ide-s3c64xx.c @@ -9,12 +9,13 @@ #include <linux/gpio.h> #include <linux/io.h> -#include <mach/map.h> -#include <mach/regs-clock.h> -#include <plat/gpio-cfg.h> -#include <mach/gpio-samsung.h> #include <linux/platform_data/ata-samsung_cf.h> +#include "map.h" +#include "regs-clock.h" +#include "gpio-cfg.h" +#include "gpio-samsung.h" + void s3c64xx_ide_setup_gpio(void) { u32 reg; diff --git a/arch/arm/mach-s3c64xx/setup-keypad.c b/arch/arm/mach-s3c/setup-keypad-s3c64xx.c index 351961025273..8463ad37c6ab 100644 --- a/arch/arm/mach-s3c64xx/setup-keypad.c +++ b/arch/arm/mach-s3c/setup-keypad-s3c64xx.c @@ -6,9 +6,9 @@ // GPIO configuration for S3C64XX KeyPad device #include <linux/gpio.h> -#include <plat/gpio-cfg.h> -#include <plat/keypad.h> -#include <mach/gpio-samsung.h> +#include "gpio-cfg.h" +#include "keypad.h" +#include "gpio-samsung.h" void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols) { diff --git a/arch/arm/mach-s3c24xx/setup-sdhci-gpio.c b/arch/arm/mach-s3c/setup-sdhci-gpio-s3c24xx.c index 218346a36d1e..02131b3a731d 100644 --- a/arch/arm/mach-s3c24xx/setup-sdhci-gpio.c +++ b/arch/arm/mach-s3c/setup-sdhci-gpio-s3c24xx.c @@ -14,9 +14,10 @@ #include <linux/io.h> #include <linux/gpio.h> -#include <mach/regs-gpio.h> -#include <mach/gpio-samsung.h> -#include <plat/gpio-cfg.h> +#include "regs-gpio.h" +#include "gpio-samsung.h" +#include "gpio-cfg.h" +#include "sdhci.h" void s3c2416_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width) { diff --git a/arch/arm/mach-s3c64xx/setup-sdhci-gpio.c b/arch/arm/mach-s3c/setup-sdhci-gpio-s3c64xx.c index 138455af4937..646ff949acd5 100644 --- a/arch/arm/mach-s3c64xx/setup-sdhci-gpio.c +++ b/arch/arm/mach-s3c/setup-sdhci-gpio-s3c64xx.c @@ -13,9 +13,9 @@ #include <linux/io.h> #include <linux/gpio.h> -#include <plat/gpio-cfg.h> -#include <plat/sdhci.h> -#include <mach/gpio-samsung.h> +#include "gpio-cfg.h" +#include "sdhci.h" +#include "gpio-samsung.h" void s3c64xx_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width) { diff --git a/arch/arm/mach-s3c24xx/setup-spi.c b/arch/arm/mach-s3c/setup-spi-s3c24xx.c index 6c2b96a82da5..93fa1bbc9d5c 100644 --- a/arch/arm/mach-s3c24xx/setup-spi.c +++ b/arch/arm/mach-s3c/setup-spi-s3c24xx.c @@ -8,10 +8,10 @@ #include <linux/gpio.h> #include <linux/platform_device.h> -#include <plat/gpio-cfg.h> +#include "gpio-cfg.h" -#include <mach/hardware.h> -#include <mach/regs-gpio.h> +#include "hardware-s3c24xx.h" +#include "regs-gpio.h" #ifdef CONFIG_S3C64XX_DEV_SPI0 int s3c64xx_spi0_cfg_gpio(void) diff --git a/arch/arm/mach-s3c64xx/setup-spi.c b/arch/arm/mach-s3c/setup-spi-s3c64xx.c index 39dfae1f46e7..efcf78d41585 100644 --- a/arch/arm/mach-s3c64xx/setup-spi.c +++ b/arch/arm/mach-s3c/setup-spi-s3c64xx.c @@ -4,8 +4,9 @@ // http://www.samsung.com/ #include <linux/gpio.h> -#include <plat/gpio-cfg.h> -#include <mach/gpio-samsung.h> +#include <linux/platform_data/spi-s3c64xx.h> +#include "gpio-cfg.h" +#include "gpio-samsung.h" #ifdef CONFIG_S3C64XX_DEV_SPI0 int s3c64xx_spi0_cfg_gpio(void) diff --git a/arch/arm/mach-s3c24xx/setup-ts.c b/arch/arm/mach-s3c/setup-ts-s3c24xx.c index 53a14d4f4852..57363eaeb7e8 100644 --- a/arch/arm/mach-s3c24xx/setup-ts.c +++ b/arch/arm/mach-s3c/setup-ts-s3c24xx.c @@ -10,12 +10,14 @@ struct platform_device; /* don't need the contents */ -#include <plat/gpio-cfg.h> -#include <mach/hardware.h> -#include <mach/gpio-samsung.h> +#include <linux/platform_data/touchscreen-s3c2410.h> + +#include "gpio-cfg.h" +#include "gpio-samsung.h" /** * s3c24xx_ts_cfg_gpio - configure gpio for s3c2410 systems + * @dev: Device to configure GPIO for (ignored) * * Configure the GPIO for the S3C2410 system, where we have external FETs * connected to the device (later systems such as the S3C2440 integrate diff --git a/arch/arm/mach-s3c64xx/setup-usb-phy.c b/arch/arm/mach-s3c/setup-usb-phy-s3c64xx.c index d6b0e3b268af..500d105afd6b 100644 --- a/arch/arm/mach-s3c64xx/setup-usb-phy.c +++ b/arch/arm/mach-s3c/setup-usb-phy-s3c64xx.c @@ -8,12 +8,12 @@ #include <linux/err.h> #include <linux/io.h> #include <linux/platform_device.h> -#include <mach/map.h> -#include <plat/cpu.h> -#include <plat/usb-phy.h> +#include "map.h" +#include "cpu.h" +#include "usb-phy.h" -#include "regs-sys.h" -#include "regs-usb-hsotg-phy.h" +#include "regs-sys-s3c64xx.h" +#include "regs-usb-hsotg-phy-s3c64xx.h" enum samsung_usb_phy_type { USB_PHY_TYPE_DEVICE, @@ -31,7 +31,7 @@ static int s3c_usb_otgphy_init(struct platform_device *pdev) phyclk = readl(S3C_PHYCLK) & ~S3C_PHYCLK_CLKSEL_MASK; xusbxti = clk_get(&pdev->dev, "xusbxti"); - if (xusbxti && !IS_ERR(xusbxti)) { + if (!IS_ERR(xusbxti)) { switch (clk_get_rate(xusbxti)) { case 12 * MHZ: phyclk |= S3C_PHYCLK_CLKSEL_12M; diff --git a/arch/arm/mach-s3c24xx/simtec-audio.c b/arch/arm/mach-s3c/simtec-audio.c index 12e17f82dae3..487485bcc2ab 100644 --- a/arch/arm/mach-s3c24xx/simtec-audio.c +++ b/arch/arm/mach-s3c/simtec-audio.c @@ -12,11 +12,12 @@ #include <linux/device.h> #include <linux/io.h> -#include <mach/hardware.h> -#include <mach/regs-gpio.h> +#include "regs-gpio.h" +#include "gpio-samsung.h" +#include "gpio-cfg.h" #include <linux/platform_data/asoc-s3c24xx_simtec.h> -#include <plat/devs.h> +#include "devs.h" #include "bast.h" #include "simtec.h" @@ -65,6 +66,10 @@ int __init simtec_audio_add(const char *name, bool has_lr_routing, if (has_lr_routing) simtec_audio_platdata.startup = simtec_audio_startup_lrroute; + /* Configure the I2S pins (GPE0...GPE4) in correct mode */ + s3c_gpio_cfgall_range(S3C2410_GPE(0), 5, S3C_GPIO_SFN(2), + S3C_GPIO_PULL_NONE); + platform_device_register(&s3c_device_iis); platform_device_register(&simtec_audio_dev); return 0; diff --git a/arch/arm/mach-s3c24xx/simtec-nor.c b/arch/arm/mach-s3c/simtec-nor.c index 26b18497e959..a6fba056a747 100644 --- a/arch/arm/mach-s3c24xx/simtec-nor.c +++ b/arch/arm/mach-s3c/simtec-nor.c @@ -21,7 +21,7 @@ #include <asm/mach/map.h> #include <asm/mach/irq.h> -#include <mach/map.h> +#include "map.h" #include "bast.h" #include "simtec.h" diff --git a/arch/arm/mach-s3c24xx/simtec-pm.c b/arch/arm/mach-s3c/simtec-pm.c index c19074d81389..490256a766e2 100644 --- a/arch/arm/mach-s3c24xx/simtec-pm.c +++ b/arch/arm/mach-s3c/simtec-pm.c @@ -19,16 +19,14 @@ #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <mach/hardware.h> - -#include <mach/map.h> -#include <mach/regs-gpio.h> +#include "map.h" +#include "regs-gpio.h" #include <asm/mach-types.h> -#include <plat/pm.h> +#include "pm.h" -#include "regs-mem.h" +#include "regs-mem-s3c24xx.h" #define COPYRIGHT ", Copyright 2005 Simtec Electronics" diff --git a/arch/arm/mach-s3c24xx/simtec-usb.c b/arch/arm/mach-s3c/simtec-usb.c index dc1016ffed94..18fe0642743a 100644 --- a/arch/arm/mach-s3c24xx/simtec-usb.c +++ b/arch/arm/mach-s3c/simtec-usb.c @@ -23,12 +23,12 @@ #include <asm/mach/map.h> #include <asm/mach/irq.h> -#include <mach/hardware.h> -#include <mach/gpio-samsung.h> +#include "gpio-samsung.h" +#include <mach/irqs.h> #include <asm/irq.h> #include <linux/platform_data/usb-ohci-s3c2410.h> -#include <plat/devs.h> +#include "devs.h" #include "bast.h" #include "simtec.h" diff --git a/arch/arm/mach-s3c24xx/simtec.h b/arch/arm/mach-s3c/simtec.h index d96bd60872b8..d96bd60872b8 100644 --- a/arch/arm/mach-s3c24xx/simtec.h +++ b/arch/arm/mach-s3c/simtec.h diff --git a/arch/arm/mach-s3c24xx/sleep-s3c2410.S b/arch/arm/mach-s3c/sleep-s3c2410.S index 659f9eff9de2..04aded98782b 100644 --- a/arch/arm/mach-s3c24xx/sleep-s3c2410.S +++ b/arch/arm/mach-s3c/sleep-s3c2410.S @@ -13,13 +13,12 @@ #include <linux/linkage.h> #include <linux/serial_s3c.h> #include <asm/assembler.h> -#include <mach/hardware.h> -#include <mach/map.h> +#include "map.h" -#include <mach/regs-gpio.h> -#include <mach/regs-clock.h> +#include "regs-gpio.h" +#include "regs-clock.h" -#include "regs-mem.h" +#include "regs-mem-s3c24xx.h" /* s3c2410_cpu_suspend * diff --git a/arch/arm/mach-s3c24xx/sleep-s3c2412.S b/arch/arm/mach-s3c/sleep-s3c2412.S index c373f1ca862b..b4b61737fbb2 100644 --- a/arch/arm/mach-s3c24xx/sleep-s3c2412.S +++ b/arch/arm/mach-s3c/sleep-s3c2412.S @@ -8,10 +8,9 @@ #include <linux/linkage.h> #include <asm/assembler.h> -#include <mach/hardware.h> -#include <mach/map.h> +#include "map.h" -#include <mach/regs-irq.h> +#include "regs-irq.h" .text diff --git a/arch/arm/mach-s3c24xx/sleep.S b/arch/arm/mach-s3c/sleep-s3c24xx.S index f0f11ad60c52..4b2af91f3dce 100644 --- a/arch/arm/mach-s3c24xx/sleep.S +++ b/arch/arm/mach-s3c/sleep-s3c24xx.S @@ -13,11 +13,10 @@ #include <linux/linkage.h> #include <linux/serial_s3c.h> #include <asm/assembler.h> -#include <mach/hardware.h> -#include <mach/map.h> +#include "map.h" -#include <mach/regs-gpio.h> -#include <mach/regs-clock.h> +#include "regs-gpio.h" +#include "regs-clock.h" /* * S3C24XX_DEBUG_RESUME is dangerous if your bootloader does not diff --git a/arch/arm/mach-s3c64xx/sleep.S b/arch/arm/mach-s3c/sleep-s3c64xx.S index 39e16a07a5e4..739e53fbce09 100644 --- a/arch/arm/mach-s3c64xx/sleep.S +++ b/arch/arm/mach-s3c/sleep-s3c64xx.S @@ -11,12 +11,12 @@ #include <linux/linkage.h> #include <asm/assembler.h> -#include <mach/map.h> +#include "map.h" #undef S3C64XX_VA_GPIO #define S3C64XX_VA_GPIO (0x0) -#include <mach/regs-gpio.h> +#include "regs-gpio.h" #define LL_UART (S3C_PA_UART + (0x400 * CONFIG_S3C_LOWLEVEL_UART_PORT)) diff --git a/arch/arm/mach-s3c24xx/spi-core.h b/arch/arm/mach-s3c/spi-core-s3c24xx.h index 1048fac629a2..057667469cc3 100644 --- a/arch/arm/mach-s3c24xx/spi-core.h +++ b/arch/arm/mach-s3c/spi-core-s3c24xx.h @@ -3,8 +3,8 @@ * Copyright (C) 2012 Heiko Stuebner <heiko@sntech.de> */ -#ifndef __PLAT_S3C_SPI_CORE_H -#define __PLAT_S3C_SPI_CORE_H +#ifndef __PLAT_S3C_SPI_CORE_S3C24XX_H +#define __PLAT_S3C_SPI_CORE_S3C24XX_H /* These functions are only for use with the core support code, such as * the cpu specific initialisation code @@ -24,4 +24,4 @@ static inline void s3c24xx_spi_setname(char *name) #endif } -#endif /* __PLAT_S3C_SPI_CORE_H */ +#endif /* __PLAT_S3C_SPI_CORE_S3C24XX_H */ diff --git a/arch/arm/plat-samsung/include/plat/usb-phy.h b/arch/arm/mach-s3c/usb-phy.h index 759d66a0773a..759d66a0773a 100644 --- a/arch/arm/plat-samsung/include/plat/usb-phy.h +++ b/arch/arm/mach-s3c/usb-phy.h diff --git a/arch/arm/mach-s3c24xx/vr1000.h b/arch/arm/mach-s3c/vr1000.h index 3cfa296bec2a..3cfa296bec2a 100644 --- a/arch/arm/mach-s3c24xx/vr1000.h +++ b/arch/arm/mach-s3c/vr1000.h diff --git a/arch/arm/plat-samsung/wakeup-mask.c b/arch/arm/mach-s3c/wakeup-mask.c index 24f96fb80738..b490e7527c66 100644 --- a/arch/arm/plat-samsung/wakeup-mask.c +++ b/arch/arm/mach-s3c/wakeup-mask.c @@ -11,8 +11,8 @@ #include <linux/irq.h> #include <linux/io.h> -#include <plat/wakeup-mask.h> -#include <plat/pm.h> +#include "wakeup-mask.h" +#include "pm.h" void samsung_sync_wakemask(void __iomem *reg, const struct samsung_wakeup_mask *mask, int nr_mask) diff --git a/arch/arm/plat-samsung/include/plat/wakeup-mask.h b/arch/arm/mach-s3c/wakeup-mask.h index 630909e6630b..630909e6630b 100644 --- a/arch/arm/plat-samsung/include/plat/wakeup-mask.h +++ b/arch/arm/mach-s3c/wakeup-mask.h diff --git a/arch/arm/mach-s3c24xx/include/mach/fb.h b/arch/arm/mach-s3c24xx/include/mach/fb.h deleted file mode 100644 index 4e539cb8b884..000000000000 --- a/arch/arm/mach-s3c24xx/include/mach/fb.h +++ /dev/null @@ -1,2 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#include <plat/fb-s3c2410.h> diff --git a/arch/arm/mach-s3c24xx/include/mach/io.h b/arch/arm/mach-s3c24xx/include/mach/io.h deleted file mode 100644 index f960e6d10114..000000000000 --- a/arch/arm/mach-s3c24xx/include/mach/io.h +++ /dev/null @@ -1,212 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * arch/arm/mach-s3c2410/include/mach/io.h - * from arch/arm/mach-rpc/include/mach/io.h - * - * Copyright (C) 1997 Russell King - * (C) 2003 Simtec Electronics -*/ - -#ifndef __ASM_ARM_ARCH_IO_H -#define __ASM_ARM_ARCH_IO_H - -#include <mach/hardware.h> - -#define IO_SPACE_LIMIT 0xffffffff - -/* - * We use two different types of addressing - PC style addresses, and ARM - * addresses. PC style accesses the PC hardware with the normal PC IO - * addresses, eg 0x3f8 for serial#1. ARM addresses are above A28 - * and are translated to the start of IO. Note that all addresses are - * not shifted left! - */ - -#define __PORT_PCIO(x) ((x) < (1<<28)) - -#define PCIO_BASE (S3C24XX_VA_ISA_WORD) -#define PCIO_BASE_b (S3C24XX_VA_ISA_BYTE) -#define PCIO_BASE_w (S3C24XX_VA_ISA_WORD) -#define PCIO_BASE_l (S3C24XX_VA_ISA_WORD) -/* - * Dynamic IO functions - let the compiler - * optimize the expressions - */ - -#define DECLARE_DYN_OUT(sz,fnsuffix,instr) \ -static inline void __out##fnsuffix (unsigned int val, unsigned int port) \ -{ \ - unsigned long temp; \ - __asm__ __volatile__( \ - "cmp %2, #(1<<28)\n\t" \ - "mov %0, %2\n\t" \ - "addcc %0, %0, %3\n\t" \ - "str" instr " %1, [%0, #0 ] @ out" #fnsuffix \ - : "=&r" (temp) \ - : "r" (val), "r" (port), "Ir" (PCIO_BASE_##fnsuffix) \ - : "cc"); \ -} - - -#define DECLARE_DYN_IN(sz,fnsuffix,instr) \ -static inline unsigned sz __in##fnsuffix (unsigned int port) \ -{ \ - unsigned long temp, value; \ - __asm__ __volatile__( \ - "cmp %2, #(1<<28)\n\t" \ - "mov %0, %2\n\t" \ - "addcc %0, %0, %3\n\t" \ - "ldr" instr " %1, [%0, #0 ] @ in" #fnsuffix \ - : "=&r" (temp), "=r" (value) \ - : "r" (port), "Ir" (PCIO_BASE_##fnsuffix) \ - : "cc"); \ - return (unsigned sz)value; \ -} - -static inline void __iomem *__ioaddr (unsigned long port) -{ - return __PORT_PCIO(port) ? (PCIO_BASE + port) : (void __iomem *)port; -} - -#define DECLARE_IO(sz,fnsuffix,instr) \ - DECLARE_DYN_IN(sz,fnsuffix,instr) \ - DECLARE_DYN_OUT(sz,fnsuffix,instr) - -DECLARE_IO(char,b,"b") -DECLARE_IO(short,w,"h") -DECLARE_IO(int,l,"") - -#undef DECLARE_IO -#undef DECLARE_DYN_IN - -/* - * Constant address IO functions - * - * These have to be macros for the 'J' constraint to work - - * +/-4096 immediate operand. - */ -#define __outbc(value,port) \ -({ \ - if (__PORT_PCIO((port))) \ - __asm__ __volatile__( \ - "strb %0, [%1, %2] @ outbc" \ - : : "r" (value), "r" (PCIO_BASE), "Jr" ((port))); \ - else \ - __asm__ __volatile__( \ - "strb %0, [%1, #0] @ outbc" \ - : : "r" (value), "r" ((port))); \ -}) - -#define __inbc(port) \ -({ \ - unsigned char result; \ - if (__PORT_PCIO((port))) \ - __asm__ __volatile__( \ - "ldrb %0, [%1, %2] @ inbc" \ - : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port))); \ - else \ - __asm__ __volatile__( \ - "ldrb %0, [%1, #0] @ inbc" \ - : "=r" (result) : "r" ((port))); \ - result; \ -}) - -#define __outwc(value,port) \ -({ \ - unsigned long v = value; \ - if (__PORT_PCIO((port))) { \ - if ((port) < 256 && (port) > -256) \ - __asm__ __volatile__( \ - "strh %0, [%1, %2] @ outwc" \ - : : "r" (v), "r" (PCIO_BASE), "Jr" ((port))); \ - else if ((port) > 0) \ - __asm__ __volatile__( \ - "strh %0, [%1, %2] @ outwc" \ - : : "r" (v), \ - "r" (PCIO_BASE + ((port) & ~0xff)), \ - "Jr" (((port) & 0xff))); \ - else \ - __asm__ __volatile__( \ - "strh %0, [%1, #0] @ outwc" \ - : : "r" (v), \ - "r" (PCIO_BASE + (port))); \ - } else \ - __asm__ __volatile__( \ - "strh %0, [%1, #0] @ outwc" \ - : : "r" (v), "r" ((port))); \ -}) - -#define __inwc(port) \ -({ \ - unsigned short result; \ - if (__PORT_PCIO((port))) { \ - if ((port) < 256 && (port) > -256 ) \ - __asm__ __volatile__( \ - "ldrh %0, [%1, %2] @ inwc" \ - : "=r" (result) \ - : "r" (PCIO_BASE), \ - "Jr" ((port))); \ - else if ((port) > 0) \ - __asm__ __volatile__( \ - "ldrh %0, [%1, %2] @ inwc" \ - : "=r" (result) \ - : "r" (PCIO_BASE + ((port) & ~0xff)), \ - "Jr" (((port) & 0xff))); \ - else \ - __asm__ __volatile__( \ - "ldrh %0, [%1, #0] @ inwc" \ - : "=r" (result) \ - : "r" (PCIO_BASE + ((port)))); \ - } else \ - __asm__ __volatile__( \ - "ldrh %0, [%1, #0] @ inwc" \ - : "=r" (result) : "r" ((port))); \ - result; \ -}) - -#define __outlc(value,port) \ -({ \ - unsigned long v = value; \ - if (__PORT_PCIO((port))) \ - __asm__ __volatile__( \ - "str %0, [%1, %2] @ outlc" \ - : : "r" (v), "r" (PCIO_BASE), "Jr" ((port))); \ - else \ - __asm__ __volatile__( \ - "str %0, [%1, #0] @ outlc" \ - : : "r" (v), "r" ((port))); \ -}) - -#define __inlc(port) \ -({ \ - unsigned long result; \ - if (__PORT_PCIO((port))) \ - __asm__ __volatile__( \ - "ldr %0, [%1, %2] @ inlc" \ - : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port))); \ - else \ - __asm__ __volatile__( \ - "ldr %0, [%1, #0] @ inlc" \ - : "=r" (result) : "r" ((port))); \ - result; \ -}) - -#define __ioaddrc(port) ((__PORT_PCIO(port) ? PCIO_BASE + (port) : (void __iomem *)0 + (port))) - -#define inb(p) (__builtin_constant_p((p)) ? __inbc(p) : __inb(p)) -#define inw(p) (__builtin_constant_p((p)) ? __inwc(p) : __inw(p)) -#define inl(p) (__builtin_constant_p((p)) ? __inlc(p) : __inl(p)) -#define outb(v,p) (__builtin_constant_p((p)) ? __outbc(v,p) : __outb(v,p)) -#define outw(v,p) (__builtin_constant_p((p)) ? __outwc(v,p) : __outw(v,p)) -#define outl(v,p) (__builtin_constant_p((p)) ? __outlc(v,p) : __outl(v,p)) -#define __ioaddr(p) (__builtin_constant_p((p)) ? __ioaddr(p) : __ioaddrc(p)) - -#define insb(p,d,l) __raw_readsb(__ioaddr(p),d,l) -#define insw(p,d,l) __raw_readsw(__ioaddr(p),d,l) -#define insl(p,d,l) __raw_readsl(__ioaddr(p),d,l) - -#define outsb(p,d,l) __raw_writesb(__ioaddr(p),d,l) -#define outsw(p,d,l) __raw_writesw(__ioaddr(p),d,l) -#define outsl(p,d,l) __raw_writesl(__ioaddr(p),d,l) - -#endif diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-lcd.h b/arch/arm/mach-s3c24xx/include/mach/regs-lcd.h deleted file mode 100644 index 4c3434f261bb..000000000000 --- a/arch/arm/mach-s3c24xx/include/mach/regs-lcd.h +++ /dev/null @@ -1,157 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk> - * http://www.simtec.co.uk/products/SWLINUX/ - */ - -#ifndef ___ASM_ARCH_REGS_LCD_H -#define ___ASM_ARCH_REGS_LCD_H - -#define S3C2410_LCDREG(x) (x) - -/* LCD control registers */ -#define S3C2410_LCDCON1 S3C2410_LCDREG(0x00) -#define S3C2410_LCDCON2 S3C2410_LCDREG(0x04) -#define S3C2410_LCDCON3 S3C2410_LCDREG(0x08) -#define S3C2410_LCDCON4 S3C2410_LCDREG(0x0C) -#define S3C2410_LCDCON5 S3C2410_LCDREG(0x10) - -#define S3C2410_LCDCON1_CLKVAL(x) ((x) << 8) -#define S3C2410_LCDCON1_MMODE (1<<7) -#define S3C2410_LCDCON1_DSCAN4 (0<<5) -#define S3C2410_LCDCON1_STN4 (1<<5) -#define S3C2410_LCDCON1_STN8 (2<<5) -#define S3C2410_LCDCON1_TFT (3<<5) - -#define S3C2410_LCDCON1_STN1BPP (0<<1) -#define S3C2410_LCDCON1_STN2GREY (1<<1) -#define S3C2410_LCDCON1_STN4GREY (2<<1) -#define S3C2410_LCDCON1_STN8BPP (3<<1) -#define S3C2410_LCDCON1_STN12BPP (4<<1) - -#define S3C2410_LCDCON1_TFT1BPP (8<<1) -#define S3C2410_LCDCON1_TFT2BPP (9<<1) -#define S3C2410_LCDCON1_TFT4BPP (10<<1) -#define S3C2410_LCDCON1_TFT8BPP (11<<1) -#define S3C2410_LCDCON1_TFT16BPP (12<<1) -#define S3C2410_LCDCON1_TFT24BPP (13<<1) - -#define S3C2410_LCDCON1_ENVID (1) - -#define S3C2410_LCDCON1_MODEMASK 0x1E - -#define S3C2410_LCDCON2_VBPD(x) ((x) << 24) -#define S3C2410_LCDCON2_LINEVAL(x) ((x) << 14) -#define S3C2410_LCDCON2_VFPD(x) ((x) << 6) -#define S3C2410_LCDCON2_VSPW(x) ((x) << 0) - -#define S3C2410_LCDCON2_GET_VBPD(x) ( ((x) >> 24) & 0xFF) -#define S3C2410_LCDCON2_GET_VFPD(x) ( ((x) >> 6) & 0xFF) -#define S3C2410_LCDCON2_GET_VSPW(x) ( ((x) >> 0) & 0x3F) - -#define S3C2410_LCDCON3_HBPD(x) ((x) << 19) -#define S3C2410_LCDCON3_WDLY(x) ((x) << 19) -#define S3C2410_LCDCON3_HOZVAL(x) ((x) << 8) -#define S3C2410_LCDCON3_HFPD(x) ((x) << 0) -#define S3C2410_LCDCON3_LINEBLANK(x)((x) << 0) - -#define S3C2410_LCDCON3_GET_HBPD(x) ( ((x) >> 19) & 0x7F) -#define S3C2410_LCDCON3_GET_HFPD(x) ( ((x) >> 0) & 0xFF) - -/* LDCCON4 changes for STN mode on the S3C2412 */ - -#define S3C2410_LCDCON4_MVAL(x) ((x) << 8) -#define S3C2410_LCDCON4_HSPW(x) ((x) << 0) -#define S3C2410_LCDCON4_WLH(x) ((x) << 0) - -#define S3C2410_LCDCON4_GET_HSPW(x) ( ((x) >> 0) & 0xFF) - -#define S3C2410_LCDCON5_BPP24BL (1<<12) -#define S3C2410_LCDCON5_FRM565 (1<<11) -#define S3C2410_LCDCON5_INVVCLK (1<<10) -#define S3C2410_LCDCON5_INVVLINE (1<<9) -#define S3C2410_LCDCON5_INVVFRAME (1<<8) -#define S3C2410_LCDCON5_INVVD (1<<7) -#define S3C2410_LCDCON5_INVVDEN (1<<6) -#define S3C2410_LCDCON5_INVPWREN (1<<5) -#define S3C2410_LCDCON5_INVLEND (1<<4) -#define S3C2410_LCDCON5_PWREN (1<<3) -#define S3C2410_LCDCON5_ENLEND (1<<2) -#define S3C2410_LCDCON5_BSWP (1<<1) -#define S3C2410_LCDCON5_HWSWP (1<<0) - -/* framebuffer start addressed */ -#define S3C2410_LCDSADDR1 S3C2410_LCDREG(0x14) -#define S3C2410_LCDSADDR2 S3C2410_LCDREG(0x18) -#define S3C2410_LCDSADDR3 S3C2410_LCDREG(0x1C) - -#define S3C2410_LCDBANK(x) ((x) << 21) -#define S3C2410_LCDBASEU(x) (x) - -#define S3C2410_OFFSIZE(x) ((x) << 11) -#define S3C2410_PAGEWIDTH(x) (x) - -/* colour lookup and miscellaneous controls */ - -#define S3C2410_REDLUT S3C2410_LCDREG(0x20) -#define S3C2410_GREENLUT S3C2410_LCDREG(0x24) -#define S3C2410_BLUELUT S3C2410_LCDREG(0x28) - -#define S3C2410_DITHMODE S3C2410_LCDREG(0x4C) -#define S3C2410_TPAL S3C2410_LCDREG(0x50) - -#define S3C2410_TPAL_EN (1<<24) - -/* interrupt info */ -#define S3C2410_LCDINTPND S3C2410_LCDREG(0x54) -#define S3C2410_LCDSRCPND S3C2410_LCDREG(0x58) -#define S3C2410_LCDINTMSK S3C2410_LCDREG(0x5C) -#define S3C2410_LCDINT_FIWSEL (1<<2) -#define S3C2410_LCDINT_FRSYNC (1<<1) -#define S3C2410_LCDINT_FICNT (1<<0) - -/* s3c2442 extra stn registers */ - -#define S3C2442_REDLUT S3C2410_LCDREG(0x20) -#define S3C2442_GREENLUT S3C2410_LCDREG(0x24) -#define S3C2442_BLUELUT S3C2410_LCDREG(0x28) -#define S3C2442_DITHMODE S3C2410_LCDREG(0x20) - -#define S3C2410_LPCSEL S3C2410_LCDREG(0x60) - -#define S3C2410_TFTPAL(x) S3C2410_LCDREG((0x400 + (x)*4)) - -/* S3C2412 registers */ - -#define S3C2412_TPAL S3C2410_LCDREG(0x20) - -#define S3C2412_LCDINTPND S3C2410_LCDREG(0x24) -#define S3C2412_LCDSRCPND S3C2410_LCDREG(0x28) -#define S3C2412_LCDINTMSK S3C2410_LCDREG(0x2C) - -#define S3C2412_TCONSEL S3C2410_LCDREG(0x30) - -#define S3C2412_LCDCON6 S3C2410_LCDREG(0x34) -#define S3C2412_LCDCON7 S3C2410_LCDREG(0x38) -#define S3C2412_LCDCON8 S3C2410_LCDREG(0x3C) -#define S3C2412_LCDCON9 S3C2410_LCDREG(0x40) - -#define S3C2412_REDLUT(x) S3C2410_LCDREG(0x44 + ((x)*4)) -#define S3C2412_GREENLUT(x) S3C2410_LCDREG(0x60 + ((x)*4)) -#define S3C2412_BLUELUT(x) S3C2410_LCDREG(0x98 + ((x)*4)) - -#define S3C2412_FRCPAT(x) S3C2410_LCDREG(0xB4 + ((x)*4)) - -/* general registers */ - -/* base of the LCD registers, where INTPND, INTSRC and then INTMSK - * are available. */ - -#define S3C2410_LCDINTBASE S3C2410_LCDREG(0x54) -#define S3C2412_LCDINTBASE S3C2410_LCDREG(0x24) - -#define S3C24XX_LCDINTPND (0x00) -#define S3C24XX_LCDSRCPND (0x04) -#define S3C24XX_LCDINTMSK (0x08) - -#endif /* ___ASM_ARCH_REGS_LCD_H */ diff --git a/arch/arm/mach-s3c24xx/setup-camif.c b/arch/arm/mach-s3c24xx/setup-camif.c deleted file mode 100644 index 2b262fae3f61..000000000000 --- a/arch/arm/mach-s3c24xx/setup-camif.c +++ /dev/null @@ -1,67 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright (C) 2012 Sylwester Nawrocki <sylvester.nawrocki@gmail.com> -// -// Helper functions for S3C24XX/S3C64XX SoC series CAMIF driver - -#include <linux/gpio.h> -#include <plat/gpio-cfg.h> -#include <mach/gpio-samsung.h> - -/* Number of camera port pins, without FIELD */ -#define S3C_CAMIF_NUM_GPIOS 13 - -/* Default camera port configuration helpers. */ - -static void camif_get_gpios(int *gpio_start, int *gpio_reset) -{ -#ifdef CONFIG_ARCH_S3C24XX - *gpio_start = S3C2410_GPJ(0); - *gpio_reset = S3C2410_GPJ(12); -#else - /* s3c64xx */ - *gpio_start = S3C64XX_GPF(0); - *gpio_reset = S3C64XX_GPF(3); -#endif -} - -int s3c_camif_gpio_get(void) -{ - int gpio_start, gpio_reset; - int ret, i; - - camif_get_gpios(&gpio_start, &gpio_reset); - - for (i = 0; i < S3C_CAMIF_NUM_GPIOS; i++) { - int gpio = gpio_start + i; - - if (gpio == gpio_reset) - continue; - - ret = gpio_request(gpio, "camif"); - if (!ret) - ret = s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); - if (ret) { - pr_err("failed to configure GPIO %d\n", gpio); - for (--i; i >= 0; i--) - gpio_free(gpio--); - return ret; - } - s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); - } - - return 0; -} - -void s3c_camif_gpio_put(void) -{ - int i, gpio_start, gpio_reset; - - camif_get_gpios(&gpio_start, &gpio_reset); - - for (i = 0; i < S3C_CAMIF_NUM_GPIOS; i++) { - int gpio = gpio_start + i; - if (gpio != gpio_reset) - gpio_free(gpio); - } -} diff --git a/arch/arm/mach-s3c64xx/include/mach/hardware.h b/arch/arm/mach-s3c64xx/include/mach/hardware.h deleted file mode 100644 index c4ed359474de..000000000000 --- a/arch/arm/mach-s3c64xx/include/mach/hardware.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* linux/arch/arm/mach-s3c6400/include/mach/hardware.h - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * S3C6400 - Hardware support - */ - -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H __FILE__ - -/* currently nothing here, placeholder */ - -#endif /* __ASM_ARCH_IRQ_H */ diff --git a/arch/arm/mach-s3c64xx/watchdog-reset.h b/arch/arm/mach-s3c64xx/watchdog-reset.h deleted file mode 100644 index 1042d6c463dc..000000000000 --- a/arch/arm/mach-s3c64xx/watchdog-reset.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * - * S3C2410 - System define for arch_reset() function - */ - -#ifndef __PLAT_SAMSUNG_WATCHDOG_RESET_H -#define __PLAT_SAMSUNG_WATCHDOG_RESET_H - -extern void samsung_wdt_reset(void); -extern void samsung_wdt_reset_of_init(void); -extern void samsung_wdt_reset_init(void __iomem *base); - -#endif /* __PLAT_SAMSUNG_WATCHDOG_RESET_H */ diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig index 03984a791879..95d4e8284866 100644 --- a/arch/arm/mach-s5pv210/Kconfig +++ b/arch/arm/mach-s5pv210/Kconfig @@ -14,10 +14,10 @@ config ARCH_S5PV210 select COMMON_CLK_SAMSUNG select GPIOLIB select HAVE_S3C2410_I2C if I2C - select HAVE_S3C2410_WATCHDOG if WATCHDOG select HAVE_S3C_RTC if RTC_CLASS select PINCTRL select PINCTRL_EXYNOS + select SOC_SAMSUNG help Samsung S5PV210/S5PC110 series based systems diff --git a/arch/arm/mach-s5pv210/Makefile b/arch/arm/mach-s5pv210/Makefile index e7b551e18e5c..aa0a1f091daf 100644 --- a/arch/arm/mach-s5pv210/Makefile +++ b/arch/arm/mach-s5pv210/Makefile @@ -3,12 +3,5 @@ # Copyright (c) 2010 Samsung Electronics Co., Ltd. # http://www.samsung.com/ -ccflags-$(CONFIG_ARCH_MULTIPLATFORM) += -I$(srctree)/arch/arm/plat-samsung/include - -# Core - obj-$(CONFIG_PM_SLEEP) += pm.o sleep.o - -# machine support - obj-y += s5pv210.o diff --git a/arch/arm/mach-s5pv210/pm.c b/arch/arm/mach-s5pv210/pm.c index b336df0c57f3..d59c094cdea8 100644 --- a/arch/arm/mach-s5pv210/pm.c +++ b/arch/arm/mach-s5pv210/pm.c @@ -13,15 +13,56 @@ #include <linux/suspend.h> #include <linux/syscore_ops.h> #include <linux/io.h> +#include <linux/soc/samsung/s3c-pm.h> #include <asm/cacheflush.h> #include <asm/suspend.h> -#include <plat/pm-common.h> - #include "common.h" #include "regs-clock.h" +/* helper functions to save and restore register state */ +struct sleep_save { + void __iomem *reg; + unsigned long val; +}; + +#define SAVE_ITEM(x) \ + { .reg = (x) } + +/** + * s3c_pm_do_save() - save a set of registers for restoration on resume. + * @ptr: Pointer to an array of registers. + * @count: Size of the ptr array. + * + * Run through the list of registers given, saving their contents in the + * array for later restoration when we wakeup. + */ +static void s3c_pm_do_save(struct sleep_save *ptr, int count) +{ + for (; count > 0; count--, ptr++) { + ptr->val = readl_relaxed(ptr->reg); + S3C_PMDBG("saved %p value %08lx\n", ptr->reg, ptr->val); + } +} + +/** + * s3c_pm_do_restore() - restore register values from the save list. + * @ptr: Pointer to an array of registers. + * @count: Size of the ptr array. + * + * Restore the register values saved from s3c_pm_do_save(). + * + * WARNING: Do not put any debug in here that may effect memory or use + * peripherals, as things may be changing! +*/ + +static void s3c_pm_do_restore_core(const struct sleep_save *ptr, int count) +{ + for (; count > 0; count--, ptr++) + writel_relaxed(ptr->val, ptr->reg); +} + static struct sleep_save s5pv210_core_save[] = { /* Clock ETC */ SAVE_ITEM(S5P_MDNIE_SEL), @@ -99,8 +140,6 @@ static int s5pv210_suspend_enter(suspend_state_t state) u32 eint_wakeup_mask = s5pv210_read_eint_wakeup_mask(); int ret; - s3c_pm_debug_init(); - S3C_PMDBG("%s: suspending the system...\n", __func__); S3C_PMDBG("%s: wakeup masks: %08x,%08x\n", __func__, @@ -113,7 +152,7 @@ static int s5pv210_suspend_enter(suspend_state_t state) return -EINVAL; } - s3c_pm_save_uarts(); + s3c_pm_save_uarts(false); s5pv210_pm_prepare(); flush_cache_all(); s3c_pm_check_store(); @@ -122,7 +161,7 @@ static int s5pv210_suspend_enter(suspend_state_t state) if (ret) return ret; - s3c_pm_restore_uarts(); + s3c_pm_restore_uarts(false); S3C_PMDBG("%s: wakeup stat: %08x\n", __func__, __raw_readl(S5P_WAKEUP_STAT)); diff --git a/arch/arm/mach-s5pv210/regs-clock.h b/arch/arm/mach-s5pv210/regs-clock.h index 2a35c831a9b0..9cad2306e470 100644 --- a/arch/arm/mach-s5pv210/regs-clock.h +++ b/arch/arm/mach-s5pv210/regs-clock.h @@ -9,7 +9,9 @@ #ifndef __ASM_ARCH_REGS_CLOCK_H #define __ASM_ARCH_REGS_CLOCK_H __FILE__ -#include <plat/map-base.h> +#define S3C_ADDR_BASE 0xF6000000 +#define S3C_ADDR(x) ((void __iomem __force *)S3C_ADDR_BASE + (x)) +#define S3C_VA_SYS S3C_ADDR(0x00100000) #define S5P_CLKREG(x) (S3C_VA_SYS + (x)) diff --git a/arch/arm/mach-s5pv210/s5pv210.c b/arch/arm/mach-s5pv210/s5pv210.c index 868f9c20419d..a21ed3bb992a 100644 --- a/arch/arm/mach-s5pv210/s5pv210.c +++ b/arch/arm/mach-s5pv210/s5pv210.c @@ -13,8 +13,6 @@ #include <asm/mach/map.h> #include <asm/system_misc.h> -#include <plat/map-base.h> - #include "common.h" #include "regs-clock.h" diff --git a/arch/arm/mach-sa1100/collie.c b/arch/arm/mach-sa1100/collie.c index 3cc2b71e16f0..bd3a52fd09ce 100644 --- a/arch/arm/mach-sa1100/collie.c +++ b/arch/arm/mach-sa1100/collie.c @@ -30,6 +30,7 @@ #include <linux/gpio_keys.h> #include <linux/input.h> #include <linux/gpio.h> +#include <linux/gpio/machine.h> #include <linux/power/gpio-charger.h> #include <video/sa1100fb.h> @@ -131,16 +132,23 @@ static struct irda_platform_data collie_ir_data = { /* * Collie AC IN */ +static struct gpiod_lookup_table collie_power_gpiod_table = { + .dev_id = "gpio-charger", + .table = { + GPIO_LOOKUP("gpio", COLLIE_GPIO_AC_IN, + NULL, GPIO_ACTIVE_HIGH), + { }, + }, +}; + static char *collie_ac_supplied_to[] = { "main-battery", "backup-battery", }; - static struct gpio_charger_platform_data collie_power_data = { .name = "charger", .type = POWER_SUPPLY_TYPE_MAINS, - .gpio = COLLIE_GPIO_AC_IN, .supplied_to = collie_ac_supplied_to, .num_supplicants = ARRAY_SIZE(collie_ac_supplied_to), }; @@ -386,6 +394,8 @@ static void __init collie_init(void) platform_scoop_config = &collie_pcmcia_config; + gpiod_add_lookup_table(&collie_power_gpiod_table); + ret = platform_add_devices(devices, ARRAY_SIZE(devices)); if (ret) { printk(KERN_WARNING "collie: Unable to register LoCoMo device\n"); diff --git a/arch/arm/mach-shmobile/rcar-gen2.h b/arch/arm/mach-shmobile/rcar-gen2.h index 4777fff2de41..af9dbd6aa49e 100644 --- a/arch/arm/mach-shmobile/rcar-gen2.h +++ b/arch/arm/mach-shmobile/rcar-gen2.h @@ -2,8 +2,6 @@ #ifndef __ASM_RCAR_GEN2_H__ #define __ASM_RCAR_GEN2_H__ -void rcar_gen2_timer_init(void); -void rcar_gen2_reserve(void); void rcar_gen2_pm_init(void); #endif /* __ASM_RCAR_GEN2_H__ */ diff --git a/arch/arm/mach-shmobile/setup-rcar-gen2.c b/arch/arm/mach-shmobile/setup-rcar-gen2.c index e00f5b3b9293..d42d93443f2f 100644 --- a/arch/arm/mach-shmobile/setup-rcar-gen2.c +++ b/arch/arm/mach-shmobile/setup-rcar-gen2.c @@ -59,7 +59,7 @@ static unsigned int __init get_extal_freq(void) #define CNTCR 0 #define CNTFID0 0x20 -void __init rcar_gen2_timer_init(void) +static void __init rcar_gen2_timer_init(void) { bool need_update = true; void __iomem *base; @@ -174,7 +174,7 @@ static int __init rcar_gen2_scan_mem(unsigned long node, const char *uname, return 0; } -void __init rcar_gen2_reserve(void) +static void __init rcar_gen2_reserve(void) { struct memory_reserve_config mrc; diff --git a/arch/arm/mach-stm32/Makefile.boot b/arch/arm/mach-stm32/Makefile.boot index cec195d4fcba..5dde7328a7a9 100644 --- a/arch/arm/mach-stm32/Makefile.boot +++ b/arch/arm/mach-stm32/Makefile.boot @@ -1,4 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only # Empty file waiting for deletion once Makefile.boot isn't needed any more. # Patch waits for application at -# http://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=7889/1 . +# https://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=7889/1 . diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index 12c26eb88afb..43d91bfd2360 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -1249,20 +1249,28 @@ static void __init l2c310_of_parse(const struct device_node *np, ret = of_property_read_u32(np, "prefetch-data", &val); if (ret == 0) { - if (val) + if (val) { prefetch |= L310_PREFETCH_CTRL_DATA_PREFETCH; - else + *aux_val |= L310_PREFETCH_CTRL_DATA_PREFETCH; + } else { prefetch &= ~L310_PREFETCH_CTRL_DATA_PREFETCH; + *aux_val &= ~L310_PREFETCH_CTRL_DATA_PREFETCH; + } + *aux_mask &= ~L310_PREFETCH_CTRL_DATA_PREFETCH; } else if (ret != -EINVAL) { pr_err("L2C-310 OF prefetch-data property value is missing\n"); } ret = of_property_read_u32(np, "prefetch-instr", &val); if (ret == 0) { - if (val) + if (val) { prefetch |= L310_PREFETCH_CTRL_INSTR_PREFETCH; - else + *aux_val |= L310_PREFETCH_CTRL_INSTR_PREFETCH; + } else { prefetch &= ~L310_PREFETCH_CTRL_INSTR_PREFETCH; + *aux_val &= ~L310_PREFETCH_CTRL_INSTR_PREFETCH; + } + *aux_mask &= ~L310_PREFETCH_CTRL_INSTR_PREFETCH; } else if (ret != -EINVAL) { pr_err("L2C-310 OF prefetch-instr property value is missing\n"); } diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c index d57112a276f5..c23dbf8bebee 100644 --- a/arch/arm/mm/init.c +++ b/arch/arm/mm/init.c @@ -354,8 +354,8 @@ static void __init free_highpages(void) /* set highmem page free */ for_each_free_mem_range(i, NUMA_NO_NODE, MEMBLOCK_NONE, &range_start, &range_end, NULL) { - unsigned long start = PHYS_PFN(range_start); - unsigned long end = PHYS_PFN(range_end); + unsigned long start = PFN_UP(range_start); + unsigned long end = PFN_DOWN(range_end); /* Ignore complete lowmem entries */ if (end <= max_low) diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c index 698cc740c6b8..ab69250a86bc 100644 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c @@ -17,7 +17,6 @@ #include <asm/cp15.h> #include <asm/cputype.h> -#include <asm/sections.h> #include <asm/cachetype.h> #include <asm/fixmap.h> #include <asm/sections.h> diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig index 93fd7fc537cf..272670ef1e92 100644 --- a/arch/arm/plat-omap/Kconfig +++ b/arch/arm/plat-omap/Kconfig @@ -23,7 +23,7 @@ config OMAP_DEBUG_LEDS config POWER_AVS_OMAP bool "AVS(Adaptive Voltage Scaling) support for OMAP IP versions 1&2" - depends on POWER_AVS && (ARCH_OMAP3 || ARCH_OMAP4) && PM + depends on (ARCH_OMAP3 || ARCH_OMAP4) && PM select POWER_SUPPLY help Say Y to enable AVS(Adaptive Voltage Scaling) diff --git a/arch/arm/plat-samsung/include/plat/adc.h b/arch/arm/plat-samsung/include/plat/adc.h deleted file mode 100644 index 74d1a46408c1..000000000000 --- a/arch/arm/plat-samsung/include/plat/adc.h +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2008 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks <ben@simtec.co.uk> - * - * S3C ADC driver information - */ - -#ifndef __ASM_PLAT_ADC_H -#define __ASM_PLAT_ADC_H __FILE__ - -struct s3c_adc_client; -struct platform_device; - -extern int s3c_adc_start(struct s3c_adc_client *client, - unsigned int channel, unsigned int nr_samples); - -extern int s3c_adc_read(struct s3c_adc_client *client, unsigned int ch); - -extern struct s3c_adc_client * - s3c_adc_register(struct platform_device *pdev, - void (*select)(struct s3c_adc_client *client, - unsigned selected), - void (*conv)(struct s3c_adc_client *client, - unsigned d0, unsigned d1, - unsigned *samples_left), - unsigned int is_ts); - -extern void s3c_adc_release(struct s3c_adc_client *client); - -#endif /* __ASM_PLAT_ADC_H */ diff --git a/arch/arm/plat-samsung/include/plat/cpu-freq-core.h b/arch/arm/plat-samsung/include/plat/cpu-freq-core.h deleted file mode 100644 index 2c7cf2665634..000000000000 --- a/arch/arm/plat-samsung/include/plat/cpu-freq-core.h +++ /dev/null @@ -1,287 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2006-2009 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks <ben@simtec.co.uk> - * - * S3C CPU frequency scaling support - core support - */ - -#include <plat/cpu-freq.h> - -struct seq_file; - -#define MAX_BANKS (8) -#define S3C2412_MAX_IO (8) - -/** - * struct s3c2410_iobank_timing - IO bank timings for S3C2410 style timings - * @bankcon: The cached version of settings in this structure. - * @tacp: - * @tacs: Time from address valid to nCS asserted. - * @tcos: Time from nCS asserted to nOE or nWE asserted. - * @tacc: Time that nOE or nWE is asserted. - * @tcoh: Time nCS is held after nOE or nWE are released. - * @tcah: Time address is held for after - * @nwait_en: Whether nWAIT is enabled for this bank. - * - * This structure represents the IO timings for a S3C2410 style IO bank - * used by the CPU frequency support if it needs to change the settings - * of the IO. - */ -struct s3c2410_iobank_timing { - unsigned long bankcon; - unsigned int tacp; - unsigned int tacs; - unsigned int tcos; - unsigned int tacc; - unsigned int tcoh; /* nCS hold after nOE/nWE */ - unsigned int tcah; /* Address hold after nCS */ - unsigned char nwait_en; /* nWait enabled for bank. */ -}; - -/** - * struct s3c2412_iobank_timing - io timings for PL092 (S3C2412) style IO - * @idcy: The idle cycle time between transactions. - * @wstrd: nCS release to end of read cycle. - * @wstwr: nCS release to end of write cycle. - * @wstoen: nCS assertion to nOE assertion time. - * @wstwen: nCS assertion to nWE assertion time. - * @wstbrd: Burst ready delay. - * @smbidcyr: Register cache for smbidcyr value. - * @smbwstrd: Register cache for smbwstrd value. - * @smbwstwr: Register cache for smbwstwr value. - * @smbwstoen: Register cache for smbwstoen value. - * @smbwstwen: Register cache for smbwstwen value. - * @smbwstbrd: Register cache for smbwstbrd value. - * - * Timing information for a IO bank on an S3C2412 or similar system which - * uses a PL093 block. - */ -struct s3c2412_iobank_timing { - unsigned int idcy; - unsigned int wstrd; - unsigned int wstwr; - unsigned int wstoen; - unsigned int wstwen; - unsigned int wstbrd; - - /* register cache */ - unsigned char smbidcyr; - unsigned char smbwstrd; - unsigned char smbwstwr; - unsigned char smbwstoen; - unsigned char smbwstwen; - unsigned char smbwstbrd; -}; - -union s3c_iobank { - struct s3c2410_iobank_timing *io_2410; - struct s3c2412_iobank_timing *io_2412; -}; - -/** - * struct s3c_iotimings - Chip IO timings holder - * @bank: The timings for each IO bank. - */ -struct s3c_iotimings { - union s3c_iobank bank[MAX_BANKS]; -}; - -/** - * struct s3c_plltab - PLL table information. - * @vals: List of PLL values. - * @size: Size of the PLL table @vals. - */ -struct s3c_plltab { - struct s3c_pllval *vals; - int size; -}; - -/** - * struct s3c_cpufreq_config - current cpu frequency configuration - * @freq: The current settings for the core clocks. - * @max: Maxium settings, derived from core, board and user settings. - * @pll: The PLL table entry for the current PLL settings. - * @divs: The divisor settings for the core clocks. - * @info: The current core driver information. - * @board: The information for the board we are running on. - * @lock_pll: Set if the PLL settings cannot be changed. - * - * This is for the core drivers that need to know information about - * the current settings and values. It should not be needed by any - * device drivers. -*/ -struct s3c_cpufreq_config { - struct s3c_freq freq; - struct s3c_freq max; - struct clk *mpll; - struct cpufreq_frequency_table pll; - struct s3c_clkdivs divs; - struct s3c_cpufreq_info *info; /* for core, not drivers */ - struct s3c_cpufreq_board *board; - - unsigned int lock_pll:1; -}; - -/** - * struct s3c_cpufreq_info - Information for the CPU frequency driver. - * @name: The name of this implementation. - * @max: The maximum frequencies for the system. - * @latency: Transition latency to give to cpufreq. - * @locktime_m: The lock-time in uS for the MPLL. - * @locktime_u: The lock-time in uS for the UPLL. - * @locttime_bits: The number of bits each LOCKTIME field. - * @need_pll: Set if this driver needs to change the PLL values to achieve - * any frequency changes. This is really only need by devices like the - * S3C2410 where there is no or limited divider between the PLL and the - * ARMCLK. - * @get_iotiming: Get the current IO timing data, mainly for use at start. - * @set_iotiming: Update the IO timings from the cached copies calculated - * from the @calc_iotiming entry when changing the frequency. - * @calc_iotiming: Calculate and update the cached copies of the IO timings - * from the newly calculated frequencies. - * @calc_freqtable: Calculate (fill in) the given frequency table from the - * current frequency configuration. If the table passed in is NULL, - * then the return is the number of elements to be filled for allocation - * of the table. - * @set_refresh: Set the memory refresh configuration. - * @set_fvco: Set the PLL frequencies. - * @set_divs: Update the clock divisors. - * @calc_divs: Calculate the clock divisors. - */ -struct s3c_cpufreq_info { - const char *name; - struct s3c_freq max; - - unsigned int latency; - - unsigned int locktime_m; - unsigned int locktime_u; - unsigned char locktime_bits; - - unsigned int need_pll:1; - - /* driver routines */ - - int (*get_iotiming)(struct s3c_cpufreq_config *cfg, - struct s3c_iotimings *timings); - - void (*set_iotiming)(struct s3c_cpufreq_config *cfg, - struct s3c_iotimings *timings); - - int (*calc_iotiming)(struct s3c_cpufreq_config *cfg, - struct s3c_iotimings *timings); - - int (*calc_freqtable)(struct s3c_cpufreq_config *cfg, - struct cpufreq_frequency_table *t, - size_t table_size); - - void (*debug_io_show)(struct seq_file *seq, - struct s3c_cpufreq_config *cfg, - union s3c_iobank *iob); - - void (*set_refresh)(struct s3c_cpufreq_config *cfg); - void (*set_fvco)(struct s3c_cpufreq_config *cfg); - void (*set_divs)(struct s3c_cpufreq_config *cfg); - int (*calc_divs)(struct s3c_cpufreq_config *cfg); -}; - -extern int s3c_cpufreq_register(struct s3c_cpufreq_info *info); - -extern int s3c_plltab_register(struct cpufreq_frequency_table *plls, - unsigned int plls_no); - -/* exports and utilities for debugfs */ -extern struct s3c_cpufreq_config *s3c_cpufreq_getconfig(void); -extern struct s3c_iotimings *s3c_cpufreq_getiotimings(void); - -#ifdef CONFIG_ARM_S3C24XX_CPUFREQ_DEBUGFS -#define s3c_cpufreq_debugfs_call(x) x -#else -#define s3c_cpufreq_debugfs_call(x) NULL -#endif - -/* Useful utility functions. */ - -extern struct clk *s3c_cpufreq_clk_get(struct device *, const char *); - -/* S3C2410 and compatible exported functions */ - -extern void s3c2410_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg); -extern void s3c2410_set_fvco(struct s3c_cpufreq_config *cfg); - -#ifdef CONFIG_S3C2410_IOTIMING -extern void s3c2410_iotiming_debugfs(struct seq_file *seq, - struct s3c_cpufreq_config *cfg, - union s3c_iobank *iob); - -extern int s3c2410_iotiming_calc(struct s3c_cpufreq_config *cfg, - struct s3c_iotimings *iot); - -extern int s3c2410_iotiming_get(struct s3c_cpufreq_config *cfg, - struct s3c_iotimings *timings); - -extern void s3c2410_iotiming_set(struct s3c_cpufreq_config *cfg, - struct s3c_iotimings *iot); -#else -#define s3c2410_iotiming_debugfs NULL -#define s3c2410_iotiming_calc NULL -#define s3c2410_iotiming_get NULL -#define s3c2410_iotiming_set NULL -#endif /* CONFIG_S3C2410_IOTIMING */ - -/* S3C2412 compatible routines */ - -#ifdef CONFIG_S3C2412_IOTIMING -extern void s3c2412_iotiming_debugfs(struct seq_file *seq, - struct s3c_cpufreq_config *cfg, - union s3c_iobank *iob); - -extern int s3c2412_iotiming_get(struct s3c_cpufreq_config *cfg, - struct s3c_iotimings *timings); - -extern int s3c2412_iotiming_calc(struct s3c_cpufreq_config *cfg, - struct s3c_iotimings *iot); - -extern void s3c2412_iotiming_set(struct s3c_cpufreq_config *cfg, - struct s3c_iotimings *iot); -#else -#define s3c2412_iotiming_debugfs NULL -#define s3c2412_iotiming_calc NULL -#define s3c2412_iotiming_get NULL -#define s3c2412_iotiming_set NULL -#endif /* CONFIG_S3C2412_IOTIMING */ - -#ifdef CONFIG_ARM_S3C24XX_CPUFREQ_DEBUG -#define s3c_freq_dbg(x...) printk(KERN_INFO x) -#else -#define s3c_freq_dbg(x...) do { if (0) printk(x); } while (0) -#endif /* CONFIG_ARM_S3C24XX_CPUFREQ_DEBUG */ - -#ifdef CONFIG_ARM_S3C24XX_CPUFREQ_IODEBUG -#define s3c_freq_iodbg(x...) printk(KERN_INFO x) -#else -#define s3c_freq_iodbg(x...) do { if (0) printk(x); } while (0) -#endif /* CONFIG_ARM_S3C24XX_CPUFREQ_IODEBUG */ - -static inline int s3c_cpufreq_addfreq(struct cpufreq_frequency_table *table, - int index, size_t table_size, - unsigned int freq) -{ - if (index < 0) - return index; - - if (table) { - if (index >= table_size) - return -ENOMEM; - - s3c_freq_dbg("%s: { %d = %u kHz }\n", - __func__, index, freq); - - table[index].driver_data = index; - table[index].frequency = freq; - } - - return index + 1; -} diff --git a/arch/arm/plat-samsung/include/plat/cpu-freq.h b/arch/arm/plat-samsung/include/plat/cpu-freq.h deleted file mode 100644 index 558892bcf9b6..000000000000 --- a/arch/arm/plat-samsung/include/plat/cpu-freq.h +++ /dev/null @@ -1,141 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2006-2007 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks <ben@simtec.co.uk> - * - * S3C CPU frequency scaling support - driver and board - */ - -#include <linux/cpufreq.h> - -struct s3c_cpufreq_info; -struct s3c_cpufreq_board; -struct s3c_iotimings; - -/** - * struct s3c_freq - frequency information (mainly for core drivers) - * @fclk: The FCLK frequency in Hz. - * @armclk: The ARMCLK frequency in Hz. - * @hclk_tns: HCLK cycle time in 10ths of nano-seconds. - * @hclk: The HCLK frequency in Hz. - * @pclk: The PCLK frequency in Hz. - * - * This contains the frequency information about the current configuration - * mainly for the core drivers to ensure we do not end up passing about - * a large number of parameters. - * - * The @hclk_tns field is a useful cache for the parts of the drivers that - * need to calculate IO timings and suchlike. - */ -struct s3c_freq { - unsigned long fclk; - unsigned long armclk; - unsigned long hclk_tns; /* in 10ths of ns */ - unsigned long hclk; - unsigned long pclk; -}; - -/** - * struct s3c_cpufreq_freqs - s3c cpufreq notification information. - * @freqs: The cpufreq setting information. - * @old: The old clock settings. - * @new: The new clock settings. - * @pll_changing: Set if the PLL is changing. - * - * Wrapper 'struct cpufreq_freqs' so that any drivers receiving the - * notification can use this information that is not provided by just - * having the core frequency alone. - * - * The pll_changing flag is used to indicate if the PLL itself is - * being set during this change. This is important as the clocks - * will temporarily be set to the XTAL clock during this time, so - * drivers may want to close down their output during this time. - * - * Note, this is not being used by any current drivers and therefore - * may be removed in the future. - */ -struct s3c_cpufreq_freqs { - struct cpufreq_freqs freqs; - struct s3c_freq old; - struct s3c_freq new; - - unsigned int pll_changing:1; -}; - -#define to_s3c_cpufreq(_cf) container_of(_cf, struct s3c_cpufreq_freqs, freqs) - -/** - * struct s3c_clkdivs - clock divisor information - * @p_divisor: Divisor from FCLK to PCLK. - * @h_divisor: Divisor from FCLK to HCLK. - * @arm_divisor: Divisor from FCLK to ARMCLK (not all CPUs). - * @dvs: Non-zero if using DVS mode for ARMCLK. - * - * Divisor settings for the core clocks. - */ -struct s3c_clkdivs { - int p_divisor; - int h_divisor; - int arm_divisor; - unsigned char dvs; -}; - -#define PLLVAL(_m, _p, _s) (((_m) << 12) | ((_p) << 4) | (_s)) - -/** - * struct s3c_pllval - PLL value entry. - * @freq: The frequency for this entry in Hz. - * @pll_reg: The PLL register setting for this PLL value. - */ -struct s3c_pllval { - unsigned long freq; - unsigned long pll_reg; -}; - -/** - * struct s3c_cpufreq_board - per-board cpu frequency informatin - * @refresh: The SDRAM refresh period in nanoseconds. - * @auto_io: Set if the IO timing settings should be generated from the - * initialisation time hardware registers. - * @need_io: Set if the board has external IO on any of the chipselect - * lines that will require the hardware timing registers to be - * updated on a clock change. - * @max: The maxium frequency limits for the system. Any field that - * is left at zero will use the CPU's settings. - * - * This contains the board specific settings that affect how the CPU - * drivers chose settings. These include the memory refresh and IO - * timing information. - * - * Registration depends on the driver being used, the ARMCLK only - * implementation does not currently need this but the older style - * driver requires this to be available. - */ -struct s3c_cpufreq_board { - unsigned int refresh; - unsigned int auto_io:1; /* automatically init io timings. */ - unsigned int need_io:1; /* set if needs io timing support. */ - - /* any non-zero field in here is taken as an upper limit. */ - struct s3c_freq max; /* frequency limits */ -}; - -/* Things depending on frequency scaling. */ -#ifdef CONFIG_ARM_S3C_CPUFREQ -#define __init_or_cpufreq -#else -#define __init_or_cpufreq __init -#endif - -/* Board functions */ - -#ifdef CONFIG_ARM_S3C_CPUFREQ -extern int s3c_cpufreq_setboard(struct s3c_cpufreq_board *board); -#else - -static inline int s3c_cpufreq_setboard(struct s3c_cpufreq_board *board) -{ - return 0; -} -#endif /* CONFIG_ARM_S3C_CPUFREQ */ diff --git a/arch/arm/plat-samsung/include/plat/fb-s3c2410.h b/arch/arm/plat-samsung/include/plat/fb-s3c2410.h deleted file mode 100644 index 614240d768b4..000000000000 --- a/arch/arm/plat-samsung/include/plat/fb-s3c2410.h +++ /dev/null @@ -1,68 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2004 Arnaud Patard <arnaud.patard@rtp-net.org> - * - * Inspired by pxafb.h -*/ - -#ifndef __ASM_PLAT_FB_S3C2410_H -#define __ASM_PLAT_FB_S3C2410_H __FILE__ - -struct s3c2410fb_hw { - unsigned long lcdcon1; - unsigned long lcdcon2; - unsigned long lcdcon3; - unsigned long lcdcon4; - unsigned long lcdcon5; -}; - -/* LCD description */ -struct s3c2410fb_display { - /* LCD type */ - unsigned type; - - /* Screen size */ - unsigned short width; - unsigned short height; - - /* Screen info */ - unsigned short xres; - unsigned short yres; - unsigned short bpp; - - unsigned pixclock; /* pixclock in picoseconds */ - unsigned short left_margin; /* value in pixels (TFT) or HCLKs (STN) */ - unsigned short right_margin; /* value in pixels (TFT) or HCLKs (STN) */ - unsigned short hsync_len; /* value in pixels (TFT) or HCLKs (STN) */ - unsigned short upper_margin; /* value in lines (TFT) or 0 (STN) */ - unsigned short lower_margin; /* value in lines (TFT) or 0 (STN) */ - unsigned short vsync_len; /* value in lines (TFT) or 0 (STN) */ - - /* lcd configuration registers */ - unsigned long lcdcon5; -}; - -struct s3c2410fb_mach_info { - - struct s3c2410fb_display *displays; /* attached displays info */ - unsigned num_displays; /* number of defined displays */ - unsigned default_display; - - /* GPIOs */ - - unsigned long gpcup; - unsigned long gpcup_mask; - unsigned long gpccon; - unsigned long gpccon_mask; - unsigned long gpdup; - unsigned long gpdup_mask; - unsigned long gpdcon; - unsigned long gpdcon_mask; - - /* lpc3600 control register */ - unsigned long lpcsel; -}; - -extern void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *); - -#endif /* __ASM_PLAT_FB_S3C2410_H */ diff --git a/arch/arm/plat-samsung/include/plat/pm-common.h b/arch/arm/plat-samsung/include/plat/pm-common.h deleted file mode 100644 index 1268bae04234..000000000000 --- a/arch/arm/plat-samsung/include/plat/pm-common.h +++ /dev/null @@ -1,107 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2013 Samsung Electronics Co., Ltd. - * Tomasz Figa <t.figa@samsung.com> - * Copyright (c) 2004 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Written by Ben Dooks, <ben@simtec.co.uk> - */ - -#ifndef __PLAT_SAMSUNG_PM_COMMON_H -#define __PLAT_SAMSUNG_PM_COMMON_H __FILE__ - -#include <linux/irq.h> - -/* sleep save info */ - -/** - * struct sleep_save - save information for shared peripherals. - * @reg: Pointer to the register to save. - * @val: Holder for the value saved from reg. - * - * This describes a list of registers which is used by the pm core and - * other subsystem to save and restore register values over suspend. - */ -struct sleep_save { - void __iomem *reg; - unsigned long val; -}; - -#define SAVE_ITEM(x) \ - { .reg = (x) } - -/* helper functions to save/restore lists of registers. */ - -extern void s3c_pm_do_save(struct sleep_save *ptr, int count); -extern void s3c_pm_do_restore(const struct sleep_save *ptr, int count); -extern void s3c_pm_do_restore_core(const struct sleep_save *ptr, int count); - -/* PM debug functions */ - -/** - * struct pm_uart_save - save block for core UART - * @ulcon: Save value for S3C2410_ULCON - * @ucon: Save value for S3C2410_UCON - * @ufcon: Save value for S3C2410_UFCON - * @umcon: Save value for S3C2410_UMCON - * @ubrdiv: Save value for S3C2410_UBRDIV - * - * Save block for UART registers to be held over sleep and restored if they - * are needed (say by debug). -*/ -struct pm_uart_save { - u32 ulcon; - u32 ucon; - u32 ufcon; - u32 umcon; - u32 ubrdiv; - u32 udivslot; -}; - -#ifdef CONFIG_SAMSUNG_PM_DEBUG -/** - * s3c_pm_dbg() - low level debug function for use in suspend/resume. - * @msg: The message to print. - * - * This function is used mainly to debug the resume process before the system - * can rely on printk/console output. It uses the low-level debugging output - * routine printascii() to do its work. - */ -extern void s3c_pm_dbg(const char *msg, ...); - -/** - * s3c_pm_debug_init() - suspend/resume low level debug initialization. - * @base: Virtual base of UART to use for suspend/resume debugging. - * - * This function needs to be called before S3C_PMDBG() can be used, to set up - * UART port base address and configuration. - */ -extern void s3c_pm_debug_init(void); - -#define S3C_PMDBG(fmt...) s3c_pm_dbg(fmt) - -extern void s3c_pm_save_uarts(void); -extern void s3c_pm_restore_uarts(void); -#else -#define S3C_PMDBG(fmt...) pr_debug(fmt) -#define s3c_pm_debug_init() do { } while (0) - -static inline void s3c_pm_save_uarts(void) { } -static inline void s3c_pm_restore_uarts(void) { } -#endif - -/* suspend memory checking */ - -#ifdef CONFIG_SAMSUNG_PM_CHECK -extern void s3c_pm_check_prepare(void); -extern void s3c_pm_check_restore(void); -extern void s3c_pm_check_cleanup(void); -extern void s3c_pm_check_store(void); -#else -#define s3c_pm_check_prepare() do { } while (0) -#define s3c_pm_check_restore() do { } while (0) -#define s3c_pm_check_cleanup() do { } while (0) -#define s3c_pm_check_store() do { } while (0) -#endif - -#endif diff --git a/arch/arm/plat-samsung/include/plat/regs-spi.h b/arch/arm/plat-samsung/include/plat/regs-spi.h deleted file mode 100644 index 607844311566..000000000000 --- a/arch/arm/plat-samsung/include/plat/regs-spi.h +++ /dev/null @@ -1,44 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2004 Fetron GmbH - * - * S3C2410 SPI register definition - */ - -#ifndef __ASM_ARCH_REGS_SPI_H -#define __ASM_ARCH_REGS_SPI_H - -#define S3C2410_SPI1 (0x20) -#define S3C2412_SPI1 (0x100) - -#define S3C2410_SPCON (0x00) - -#define S3C2410_SPCON_SMOD_DMA (2 << 5) /* DMA mode */ -#define S3C2410_SPCON_SMOD_INT (1 << 5) /* interrupt mode */ -#define S3C2410_SPCON_SMOD_POLL (0 << 5) /* polling mode */ -#define S3C2410_SPCON_ENSCK (1 << 4) /* Enable SCK */ -#define S3C2410_SPCON_MSTR (1 << 3) /* Master:1, Slave:0 select */ -#define S3C2410_SPCON_CPOL_HIGH (1 << 2) /* Clock polarity select */ -#define S3C2410_SPCON_CPOL_LOW (0 << 2) /* Clock polarity select */ - -#define S3C2410_SPCON_CPHA_FMTB (1 << 1) /* Clock Phase Select */ -#define S3C2410_SPCON_CPHA_FMTA (0 << 1) /* Clock Phase Select */ - -#define S3C2410_SPSTA (0x04) - -#define S3C2410_SPSTA_DCOL (1 << 2) /* Data Collision Error */ -#define S3C2410_SPSTA_MULD (1 << 1) /* Multi Master Error */ -#define S3C2410_SPSTA_READY (1 << 0) /* Data Tx/Rx ready */ -#define S3C2412_SPSTA_READY_ORG (1 << 3) - -#define S3C2410_SPPIN (0x08) - -#define S3C2410_SPPIN_ENMUL (1 << 2) /* Multi Master Error detect */ -#define S3C2410_SPPIN_RESERVED (1 << 1) -#define S3C2410_SPPIN_KEEP (1 << 0) /* Master Out keep */ - -#define S3C2410_SPPRE (0x0C) -#define S3C2410_SPTDAT (0x10) -#define S3C2410_SPRDAT (0x14) - -#endif /* __ASM_ARCH_REGS_SPI_H */ diff --git a/arch/arm/plat-samsung/include/plat/regs-udc.h b/arch/arm/plat-samsung/include/plat/regs-udc.h deleted file mode 100644 index d8d2eeaca088..000000000000 --- a/arch/arm/plat-samsung/include/plat/regs-udc.h +++ /dev/null @@ -1,146 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2004 Herbert Poetzl <herbert@13thfloor.at> - */ - -#ifndef __ASM_ARCH_REGS_UDC_H -#define __ASM_ARCH_REGS_UDC_H - -#define S3C2410_USBDREG(x) (x) - -#define S3C2410_UDC_FUNC_ADDR_REG S3C2410_USBDREG(0x0140) -#define S3C2410_UDC_PWR_REG S3C2410_USBDREG(0x0144) -#define S3C2410_UDC_EP_INT_REG S3C2410_USBDREG(0x0148) - -#define S3C2410_UDC_USB_INT_REG S3C2410_USBDREG(0x0158) -#define S3C2410_UDC_EP_INT_EN_REG S3C2410_USBDREG(0x015c) - -#define S3C2410_UDC_USB_INT_EN_REG S3C2410_USBDREG(0x016c) - -#define S3C2410_UDC_FRAME_NUM1_REG S3C2410_USBDREG(0x0170) -#define S3C2410_UDC_FRAME_NUM2_REG S3C2410_USBDREG(0x0174) - -#define S3C2410_UDC_EP0_FIFO_REG S3C2410_USBDREG(0x01c0) -#define S3C2410_UDC_EP1_FIFO_REG S3C2410_USBDREG(0x01c4) -#define S3C2410_UDC_EP2_FIFO_REG S3C2410_USBDREG(0x01c8) -#define S3C2410_UDC_EP3_FIFO_REG S3C2410_USBDREG(0x01cc) -#define S3C2410_UDC_EP4_FIFO_REG S3C2410_USBDREG(0x01d0) - -#define S3C2410_UDC_EP1_DMA_CON S3C2410_USBDREG(0x0200) -#define S3C2410_UDC_EP1_DMA_UNIT S3C2410_USBDREG(0x0204) -#define S3C2410_UDC_EP1_DMA_FIFO S3C2410_USBDREG(0x0208) -#define S3C2410_UDC_EP1_DMA_TTC_L S3C2410_USBDREG(0x020c) -#define S3C2410_UDC_EP1_DMA_TTC_M S3C2410_USBDREG(0x0210) -#define S3C2410_UDC_EP1_DMA_TTC_H S3C2410_USBDREG(0x0214) - -#define S3C2410_UDC_EP2_DMA_CON S3C2410_USBDREG(0x0218) -#define S3C2410_UDC_EP2_DMA_UNIT S3C2410_USBDREG(0x021c) -#define S3C2410_UDC_EP2_DMA_FIFO S3C2410_USBDREG(0x0220) -#define S3C2410_UDC_EP2_DMA_TTC_L S3C2410_USBDREG(0x0224) -#define S3C2410_UDC_EP2_DMA_TTC_M S3C2410_USBDREG(0x0228) -#define S3C2410_UDC_EP2_DMA_TTC_H S3C2410_USBDREG(0x022c) - -#define S3C2410_UDC_EP3_DMA_CON S3C2410_USBDREG(0x0240) -#define S3C2410_UDC_EP3_DMA_UNIT S3C2410_USBDREG(0x0244) -#define S3C2410_UDC_EP3_DMA_FIFO S3C2410_USBDREG(0x0248) -#define S3C2410_UDC_EP3_DMA_TTC_L S3C2410_USBDREG(0x024c) -#define S3C2410_UDC_EP3_DMA_TTC_M S3C2410_USBDREG(0x0250) -#define S3C2410_UDC_EP3_DMA_TTC_H S3C2410_USBDREG(0x0254) - -#define S3C2410_UDC_EP4_DMA_CON S3C2410_USBDREG(0x0258) -#define S3C2410_UDC_EP4_DMA_UNIT S3C2410_USBDREG(0x025c) -#define S3C2410_UDC_EP4_DMA_FIFO S3C2410_USBDREG(0x0260) -#define S3C2410_UDC_EP4_DMA_TTC_L S3C2410_USBDREG(0x0264) -#define S3C2410_UDC_EP4_DMA_TTC_M S3C2410_USBDREG(0x0268) -#define S3C2410_UDC_EP4_DMA_TTC_H S3C2410_USBDREG(0x026c) - -#define S3C2410_UDC_INDEX_REG S3C2410_USBDREG(0x0178) - -/* indexed registers */ - -#define S3C2410_UDC_MAXP_REG S3C2410_USBDREG(0x0180) - -#define S3C2410_UDC_EP0_CSR_REG S3C2410_USBDREG(0x0184) - -#define S3C2410_UDC_IN_CSR1_REG S3C2410_USBDREG(0x0184) -#define S3C2410_UDC_IN_CSR2_REG S3C2410_USBDREG(0x0188) - -#define S3C2410_UDC_OUT_CSR1_REG S3C2410_USBDREG(0x0190) -#define S3C2410_UDC_OUT_CSR2_REG S3C2410_USBDREG(0x0194) -#define S3C2410_UDC_OUT_FIFO_CNT1_REG S3C2410_USBDREG(0x0198) -#define S3C2410_UDC_OUT_FIFO_CNT2_REG S3C2410_USBDREG(0x019c) - -#define S3C2410_UDC_FUNCADDR_UPDATE (1 << 7) - -#define S3C2410_UDC_PWR_ISOUP (1 << 7) /* R/W */ -#define S3C2410_UDC_PWR_RESET (1 << 3) /* R */ -#define S3C2410_UDC_PWR_RESUME (1 << 2) /* R/W */ -#define S3C2410_UDC_PWR_SUSPEND (1 << 1) /* R */ -#define S3C2410_UDC_PWR_ENSUSPEND (1 << 0) /* R/W */ - -#define S3C2410_UDC_PWR_DEFAULT (0x00) - -#define S3C2410_UDC_INT_EP4 (1 << 4) /* R/W (clear only) */ -#define S3C2410_UDC_INT_EP3 (1 << 3) /* R/W (clear only) */ -#define S3C2410_UDC_INT_EP2 (1 << 2) /* R/W (clear only) */ -#define S3C2410_UDC_INT_EP1 (1 << 1) /* R/W (clear only) */ -#define S3C2410_UDC_INT_EP0 (1 << 0) /* R/W (clear only) */ - -#define S3C2410_UDC_USBINT_RESET (1 << 2) /* R/W (clear only) */ -#define S3C2410_UDC_USBINT_RESUME (1 << 1) /* R/W (clear only) */ -#define S3C2410_UDC_USBINT_SUSPEND (1 << 0) /* R/W (clear only) */ - -#define S3C2410_UDC_INTE_EP4 (1 << 4) /* R/W */ -#define S3C2410_UDC_INTE_EP3 (1 << 3) /* R/W */ -#define S3C2410_UDC_INTE_EP2 (1 << 2) /* R/W */ -#define S3C2410_UDC_INTE_EP1 (1 << 1) /* R/W */ -#define S3C2410_UDC_INTE_EP0 (1 << 0) /* R/W */ - -#define S3C2410_UDC_USBINTE_RESET (1 << 2) /* R/W */ -#define S3C2410_UDC_USBINTE_SUSPEND (1 << 0) /* R/W */ - -#define S3C2410_UDC_INDEX_EP0 (0x00) -#define S3C2410_UDC_INDEX_EP1 (0x01) -#define S3C2410_UDC_INDEX_EP2 (0x02) -#define S3C2410_UDC_INDEX_EP3 (0x03) -#define S3C2410_UDC_INDEX_EP4 (0x04) - -#define S3C2410_UDC_ICSR1_CLRDT (1 << 6) /* R/W */ -#define S3C2410_UDC_ICSR1_SENTSTL (1 << 5) /* R/W (clear only) */ -#define S3C2410_UDC_ICSR1_SENDSTL (1 << 4) /* R/W */ -#define S3C2410_UDC_ICSR1_FFLUSH (1 << 3) /* W (set only) */ -#define S3C2410_UDC_ICSR1_UNDRUN (1 << 2) /* R/W (clear only) */ -#define S3C2410_UDC_ICSR1_PKTRDY (1 << 0) /* R/W (set only) */ - -#define S3C2410_UDC_ICSR2_AUTOSET (1 << 7) /* R/W */ -#define S3C2410_UDC_ICSR2_ISO (1 << 6) /* R/W */ -#define S3C2410_UDC_ICSR2_MODEIN (1 << 5) /* R/W */ -#define S3C2410_UDC_ICSR2_DMAIEN (1 << 4) /* R/W */ - -#define S3C2410_UDC_OCSR1_CLRDT (1 << 7) /* R/W */ -#define S3C2410_UDC_OCSR1_SENTSTL (1 << 6) /* R/W (clear only) */ -#define S3C2410_UDC_OCSR1_SENDSTL (1 << 5) /* R/W */ -#define S3C2410_UDC_OCSR1_FFLUSH (1 << 4) /* R/W */ -#define S3C2410_UDC_OCSR1_DERROR (1 << 3) /* R */ -#define S3C2410_UDC_OCSR1_OVRRUN (1 << 2) /* R/W (clear only) */ -#define S3C2410_UDC_OCSR1_PKTRDY (1 << 0) /* R/W (clear only) */ - -#define S3C2410_UDC_OCSR2_AUTOCLR (1 << 7) /* R/W */ -#define S3C2410_UDC_OCSR2_ISO (1 << 6) /* R/W */ -#define S3C2410_UDC_OCSR2_DMAIEN (1 << 5) /* R/W */ - -#define S3C2410_UDC_EP0_CSR_OPKRDY (1 << 0) -#define S3C2410_UDC_EP0_CSR_IPKRDY (1 << 1) -#define S3C2410_UDC_EP0_CSR_SENTSTL (1 << 2) -#define S3C2410_UDC_EP0_CSR_DE (1 << 3) -#define S3C2410_UDC_EP0_CSR_SE (1 << 4) -#define S3C2410_UDC_EP0_CSR_SENDSTL (1 << 5) -#define S3C2410_UDC_EP0_CSR_SOPKTRDY (1 << 6) -#define S3C2410_UDC_EP0_CSR_SSE (1 << 7) - -#define S3C2410_UDC_MAXP_8 (1 << 0) -#define S3C2410_UDC_MAXP_16 (1 << 1) -#define S3C2410_UDC_MAXP_32 (1 << 2) -#define S3C2410_UDC_MAXP_64 (1 << 3) - -#endif diff --git a/arch/arm/plat-samsung/include/plat/samsung-time.h b/arch/arm/plat-samsung/include/plat/samsung-time.h deleted file mode 100644 index 32ab0860f631..000000000000 --- a/arch/arm/plat-samsung/include/plat/samsung-time.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright 2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com/ - * - * Header file for samsung s3c and s5p time support - */ - -#ifndef __ASM_PLAT_SAMSUNG_TIME_H -#define __ASM_PLAT_SAMSUNG_TIME_H __FILE__ - -/* Samsung HR-Timer Clock mode */ -enum samsung_timer_mode { - SAMSUNG_PWM0, - SAMSUNG_PWM1, - SAMSUNG_PWM2, - SAMSUNG_PWM3, - SAMSUNG_PWM4, -}; - -extern void __init samsung_set_timer_source(enum samsung_timer_mode event, - enum samsung_timer_mode source); - -extern void __init samsung_timer_init(void); - -#endif /* __ASM_PLAT_SAMSUNG_TIME_H */ diff --git a/arch/arm/plat-samsung/pm-check.c b/arch/arm/plat-samsung/pm-check.c deleted file mode 100644 index cd2c02c68bc3..000000000000 --- a/arch/arm/plat-samsung/pm-check.c +++ /dev/null @@ -1,233 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// originally in linux/arch/arm/plat-s3c24xx/pm.c -// -// Copyright (c) 2004-2008 Simtec Electronics -// http://armlinux.simtec.co.uk -// Ben Dooks <ben@simtec.co.uk> -// -// S3C Power Mangament - suspend/resume memory corruption check. - -#include <linux/kernel.h> -#include <linux/suspend.h> -#include <linux/init.h> -#include <linux/crc32.h> -#include <linux/ioport.h> -#include <linux/slab.h> - -#include <plat/pm-common.h> - -#if CONFIG_SAMSUNG_PM_CHECK_CHUNKSIZE < 1 -#error CONFIG_SAMSUNG_PM_CHECK_CHUNKSIZE must be a positive non-zero value -#endif - -/* suspend checking code... - * - * this next area does a set of crc checks over all the installed - * memory, so the system can verify if the resume was ok. - * - * CONFIG_SAMSUNG_PM_CHECK_CHUNKSIZE defines the block-size for the CRC, - * increasing it will mean that the area corrupted will be less easy to spot, - * and reducing the size will cause the CRC save area to grow -*/ - -#define CHECK_CHUNKSIZE (CONFIG_SAMSUNG_PM_CHECK_CHUNKSIZE * 1024) - -static u32 crc_size; /* size needed for the crc block */ -static u32 *crcs; /* allocated over suspend/resume */ - -typedef u32 *(run_fn_t)(struct resource *ptr, u32 *arg); - -/* s3c_pm_run_res - * - * go through the given resource list, and look for system ram -*/ - -static void s3c_pm_run_res(struct resource *ptr, run_fn_t fn, u32 *arg) -{ - while (ptr != NULL) { - if (ptr->child != NULL) - s3c_pm_run_res(ptr->child, fn, arg); - - if ((ptr->flags & IORESOURCE_SYSTEM_RAM) - == IORESOURCE_SYSTEM_RAM) { - S3C_PMDBG("Found system RAM at %08lx..%08lx\n", - (unsigned long)ptr->start, - (unsigned long)ptr->end); - arg = (fn)(ptr, arg); - } - - ptr = ptr->sibling; - } -} - -static void s3c_pm_run_sysram(run_fn_t fn, u32 *arg) -{ - s3c_pm_run_res(&iomem_resource, fn, arg); -} - -static u32 *s3c_pm_countram(struct resource *res, u32 *val) -{ - u32 size = (u32)resource_size(res); - - size += CHECK_CHUNKSIZE-1; - size /= CHECK_CHUNKSIZE; - - S3C_PMDBG("Area %08lx..%08lx, %d blocks\n", - (unsigned long)res->start, (unsigned long)res->end, size); - - *val += size * sizeof(u32); - return val; -} - -/* s3c_pm_prepare_check - * - * prepare the necessary information for creating the CRCs. This - * must be done before the final save, as it will require memory - * allocating, and thus touching bits of the kernel we do not - * know about. -*/ - -void s3c_pm_check_prepare(void) -{ - crc_size = 0; - - s3c_pm_run_sysram(s3c_pm_countram, &crc_size); - - S3C_PMDBG("s3c_pm_prepare_check: %u checks needed\n", crc_size); - - crcs = kmalloc(crc_size+4, GFP_KERNEL); - if (crcs == NULL) - printk(KERN_ERR "Cannot allocated CRC save area\n"); -} - -static u32 *s3c_pm_makecheck(struct resource *res, u32 *val) -{ - unsigned long addr, left; - - for (addr = res->start; addr < res->end; - addr += CHECK_CHUNKSIZE) { - left = res->end - addr; - - if (left > CHECK_CHUNKSIZE) - left = CHECK_CHUNKSIZE; - - *val = crc32_le(~0, phys_to_virt(addr), left); - val++; - } - - return val; -} - -/* s3c_pm_check_store - * - * compute the CRC values for the memory blocks before the final - * sleep. -*/ - -void s3c_pm_check_store(void) -{ - if (crcs != NULL) - s3c_pm_run_sysram(s3c_pm_makecheck, crcs); -} - -/* in_region - * - * return TRUE if the area defined by ptr..ptr+size contains the - * what..what+whatsz -*/ - -static inline int in_region(void *ptr, int size, void *what, size_t whatsz) -{ - if ((what+whatsz) < ptr) - return 0; - - if (what > (ptr+size)) - return 0; - - return 1; -} - -/** - * s3c_pm_runcheck() - helper to check a resource on restore. - * @res: The resource to check - * @vak: Pointer to list of CRC32 values to check. - * - * Called from the s3c_pm_check_restore() via s3c_pm_run_sysram(), this - * function runs the given memory resource checking it against the stored - * CRC to ensure that memory is restored. The function tries to skip as - * many of the areas used during the suspend process. - */ -static u32 *s3c_pm_runcheck(struct resource *res, u32 *val) -{ - unsigned long addr; - unsigned long left; - void *stkpage; - void *ptr; - u32 calc; - - stkpage = (void *)((u32)&calc & ~PAGE_MASK); - - for (addr = res->start; addr < res->end; - addr += CHECK_CHUNKSIZE) { - left = res->end - addr; - - if (left > CHECK_CHUNKSIZE) - left = CHECK_CHUNKSIZE; - - ptr = phys_to_virt(addr); - - if (in_region(ptr, left, stkpage, 4096)) { - S3C_PMDBG("skipping %08lx, has stack in\n", addr); - goto skip_check; - } - - if (in_region(ptr, left, crcs, crc_size)) { - S3C_PMDBG("skipping %08lx, has crc block in\n", addr); - goto skip_check; - } - - /* calculate and check the checksum */ - - calc = crc32_le(~0, ptr, left); - if (calc != *val) { - printk(KERN_ERR "Restore CRC error at " - "%08lx (%08x vs %08x)\n", addr, calc, *val); - - S3C_PMDBG("Restore CRC error at %08lx (%08x vs %08x)\n", - addr, calc, *val); - } - - skip_check: - val++; - } - - return val; -} - -/** - * s3c_pm_check_restore() - memory check called on resume - * - * check the CRCs after the restore event and free the memory used - * to hold them -*/ -void s3c_pm_check_restore(void) -{ - if (crcs != NULL) - s3c_pm_run_sysram(s3c_pm_runcheck, crcs); -} - -/** - * s3c_pm_check_cleanup() - free memory resources - * - * Free the resources that where allocated by the suspend - * memory check code. We do this separately from the - * s3c_pm_check_restore() function as we cannot call any - * functions that might sleep during that resume. - */ -void s3c_pm_check_cleanup(void) -{ - kfree(crcs); - crcs = NULL; -} - diff --git a/arch/arm/plat-samsung/pm-debug.c b/arch/arm/plat-samsung/pm-debug.c deleted file mode 100644 index b76b1e9ba4ae..000000000000 --- a/arch/arm/plat-samsung/pm-debug.c +++ /dev/null @@ -1,95 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright (C) 2013 Samsung Electronics Co., Ltd. -// Tomasz Figa <t.figa@samsung.com> -// Copyright (C) 2008 Openmoko, Inc. -// Copyright (C) 2004-2008 Simtec Electronics -// Ben Dooks <ben@simtec.co.uk> -// http://armlinux.simtec.co.uk/ -// -// Samsung common power management (suspend to RAM) debug support - -#include <linux/serial_core.h> -#include <linux/serial_s3c.h> -#include <linux/io.h> - -#include <asm/mach/map.h> - -#include <plat/cpu.h> -#include <plat/pm-common.h> - -#ifdef CONFIG_SAMSUNG_ATAGS -#include <plat/pm.h> -#include <mach/pm-core.h> -#else -static inline void s3c_pm_debug_init_uart(void) {} -static inline void s3c_pm_arch_update_uart(void __iomem *regs, - struct pm_uart_save *save) {} -#endif - -static struct pm_uart_save uart_save; - -extern void printascii(const char *); - -void s3c_pm_dbg(const char *fmt, ...) -{ - va_list va; - char buff[256]; - - va_start(va, fmt); - vsnprintf(buff, sizeof(buff), fmt, va); - va_end(va); - - printascii(buff); -} - -void s3c_pm_debug_init(void) -{ - /* restart uart clocks so we can use them to output */ - s3c_pm_debug_init_uart(); -} - -static inline void __iomem *s3c_pm_uart_base(void) -{ - unsigned long paddr; - unsigned long vaddr; - - debug_ll_addr(&paddr, &vaddr); - - return (void __iomem *)vaddr; -} - -void s3c_pm_save_uarts(void) -{ - void __iomem *regs = s3c_pm_uart_base(); - struct pm_uart_save *save = &uart_save; - - save->ulcon = __raw_readl(regs + S3C2410_ULCON); - save->ucon = __raw_readl(regs + S3C2410_UCON); - save->ufcon = __raw_readl(regs + S3C2410_UFCON); - save->umcon = __raw_readl(regs + S3C2410_UMCON); - save->ubrdiv = __raw_readl(regs + S3C2410_UBRDIV); - - if (!soc_is_s3c2410()) - save->udivslot = __raw_readl(regs + S3C2443_DIVSLOT); - - S3C_PMDBG("UART[%p]: ULCON=%04x, UCON=%04x, UFCON=%04x, UBRDIV=%04x\n", - regs, save->ulcon, save->ucon, save->ufcon, save->ubrdiv); -} - -void s3c_pm_restore_uarts(void) -{ - void __iomem *regs = s3c_pm_uart_base(); - struct pm_uart_save *save = &uart_save; - - s3c_pm_arch_update_uart(regs, save); - - __raw_writel(save->ulcon, regs + S3C2410_ULCON); - __raw_writel(save->ucon, regs + S3C2410_UCON); - __raw_writel(save->ufcon, regs + S3C2410_UFCON); - __raw_writel(save->umcon, regs + S3C2410_UMCON); - __raw_writel(save->ubrdiv, regs + S3C2410_UBRDIV); - - if (!soc_is_s3c2410()) - __raw_writel(save->udivslot, regs + S3C2443_DIVSLOT); -} diff --git a/arch/arm/plat-samsung/watchdog-reset.c b/arch/arm/plat-samsung/watchdog-reset.c deleted file mode 100644 index 71d85ff323f7..000000000000 --- a/arch/arm/plat-samsung/watchdog-reset.c +++ /dev/null @@ -1,93 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright (c) 2008 Simtec Electronics -// Ben Dooks <ben@simtec.co.uk> -// -// Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com> -// -// Watchdog reset support for Samsung SoCs. - -#include <linux/clk.h> -#include <linux/err.h> -#include <linux/io.h> -#include <linux/delay.h> -#include <linux/of.h> -#include <linux/of_address.h> - -#define S3C2410_WTCON 0x00 -#define S3C2410_WTDAT 0x04 -#define S3C2410_WTCNT 0x08 - -#define S3C2410_WTCON_ENABLE (1 << 5) -#define S3C2410_WTCON_DIV16 (0 << 3) -#define S3C2410_WTCON_RSTEN (1 << 0) -#define S3C2410_WTCON_PRESCALE(x) ((x) << 8) - -static void __iomem *wdt_base; -static struct clk *wdt_clock; - -void samsung_wdt_reset(void) -{ - if (!wdt_base) { - pr_err("%s: wdt reset not initialized\n", __func__); - /* delay to allow the serial port to show the message */ - mdelay(50); - return; - } - - if (!IS_ERR(wdt_clock)) - clk_prepare_enable(wdt_clock); - - /* disable watchdog, to be safe */ - __raw_writel(0, wdt_base + S3C2410_WTCON); - - /* put initial values into count and data */ - __raw_writel(0x80, wdt_base + S3C2410_WTCNT); - __raw_writel(0x80, wdt_base + S3C2410_WTDAT); - - /* set the watchdog to go and reset... */ - __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV16 | - S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x20), - wdt_base + S3C2410_WTCON); - - /* wait for reset to assert... */ - mdelay(500); - - pr_err("Watchdog reset failed to assert reset\n"); - - /* delay to allow the serial port to show the message */ - mdelay(50); -} - -#ifdef CONFIG_OF -static const struct of_device_id s3c2410_wdt_match[] = { - { .compatible = "samsung,s3c2410-wdt" }, - { .compatible = "samsung,s3c6410-wdt" }, - {}, -}; - -void __init samsung_wdt_reset_of_init(void) -{ - struct device_node *np; - - np = of_find_matching_node(NULL, s3c2410_wdt_match); - if (!np) { - pr_err("%s: failed to find watchdog node\n", __func__); - return; - } - - wdt_base = of_iomap(np, 0); - if (!wdt_base) { - pr_err("%s: failed to map watchdog registers\n", __func__); - return; - } - - wdt_clock = of_clk_get(np, 0); -} -#endif - -void __init samsung_wdt_reset_init(void __iomem *base) -{ - wdt_base = base; - wdt_clock = clk_get(NULL, "watchdog"); -} diff --git a/arch/arm/probes/kprobes/opt-arm.c b/arch/arm/probes/kprobes/opt-arm.c index 7a449df0b359..c78180172120 100644 --- a/arch/arm/probes/kprobes/opt-arm.c +++ b/arch/arm/probes/kprobes/opt-arm.c @@ -85,21 +85,21 @@ asm ( "optprobe_template_end:\n"); #define TMPL_VAL_IDX \ - ((unsigned long *)&optprobe_template_val - (unsigned long *)&optprobe_template_entry) + ((unsigned long *)optprobe_template_val - (unsigned long *)optprobe_template_entry) #define TMPL_CALL_IDX \ - ((unsigned long *)&optprobe_template_call - (unsigned long *)&optprobe_template_entry) + ((unsigned long *)optprobe_template_call - (unsigned long *)optprobe_template_entry) #define TMPL_END_IDX \ - ((unsigned long *)&optprobe_template_end - (unsigned long *)&optprobe_template_entry) + ((unsigned long *)optprobe_template_end - (unsigned long *)optprobe_template_entry) #define TMPL_ADD_SP \ - ((unsigned long *)&optprobe_template_add_sp - (unsigned long *)&optprobe_template_entry) + ((unsigned long *)optprobe_template_add_sp - (unsigned long *)optprobe_template_entry) #define TMPL_SUB_SP \ - ((unsigned long *)&optprobe_template_sub_sp - (unsigned long *)&optprobe_template_entry) + ((unsigned long *)optprobe_template_sub_sp - (unsigned long *)optprobe_template_entry) #define TMPL_RESTORE_BEGIN \ - ((unsigned long *)&optprobe_template_restore_begin - (unsigned long *)&optprobe_template_entry) + ((unsigned long *)optprobe_template_restore_begin - (unsigned long *)optprobe_template_entry) #define TMPL_RESTORE_ORIGN_INSN \ - ((unsigned long *)&optprobe_template_restore_orig_insn - (unsigned long *)&optprobe_template_entry) + ((unsigned long *)optprobe_template_restore_orig_insn - (unsigned long *)optprobe_template_entry) #define TMPL_RESTORE_END \ - ((unsigned long *)&optprobe_template_restore_end - (unsigned long *)&optprobe_template_entry) + ((unsigned long *)optprobe_template_restore_end - (unsigned long *)optprobe_template_entry) /* * ARM can always optimize an instruction when using ARM ISA, except @@ -234,7 +234,7 @@ int arch_prepare_optimized_kprobe(struct optimized_kprobe *op, struct kprobe *or } /* Copy arch-dep-instance from template. */ - memcpy(code, (unsigned long *)&optprobe_template_entry, + memcpy(code, (unsigned long *)optprobe_template_entry, TMPL_END_IDX * sizeof(kprobe_opcode_t)); /* Adjust buffer according to instruction. */ diff --git a/arch/arm/tools/syscall.tbl b/arch/arm/tools/syscall.tbl index 171077cbf419..d056a548358e 100644 --- a/arch/arm/tools/syscall.tbl +++ b/arch/arm/tools/syscall.tbl @@ -453,3 +453,4 @@ 437 common openat2 sys_openat2 438 common pidfd_getfd sys_pidfd_getfd 439 common faccessat2 sys_faccessat2 +440 common process_madvise sys_process_madvise diff --git a/arch/arm/vdso/Makefile b/arch/arm/vdso/Makefile index a54f70731d9f..150ce6e6a5d3 100644 --- a/arch/arm/vdso/Makefile +++ b/arch/arm/vdso/Makefile @@ -19,7 +19,7 @@ ccflags-y += -DDISABLE_BRANCH_PROFILING -DBUILD_VDSO32 ldflags-$(CONFIG_CPU_ENDIAN_BE8) := --be8 ldflags-y := -Bsymbolic --no-undefined -soname=linux-vdso.so.1 \ -z max-page-size=4096 -nostdlib -shared $(ldflags-y) \ - --hash-style=sysv --build-id \ + --hash-style=sysv --build-id=sha1 \ -T obj-$(CONFIG_VDSO) += vdso.o |