summaryrefslogtreecommitdiff
path: root/arch/arm64
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm64')
-rw-r--r--arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts14
-rw-r--r--arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi20
-rw-r--r--arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts20
-rw-r--r--arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts189
-rw-r--r--arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts24
-rw-r--r--arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts22
-rw-r--r--arch/arm64/boot/dts/marvell/cn9130-crb.dtsi42
7 files changed, 167 insertions, 164 deletions
diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts
index 870bb380a40a..f9abef8dcc94 100644
--- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts
+++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts
@@ -126,32 +126,32 @@
reset-gpios = <&gpiosb 23 GPIO_ACTIVE_LOW>;
- ethernet-ports {
- switch0port1: ethernet-port@1 {
+ ports {
+ switch0port1: port@1 {
reg = <1>;
label = "lan0";
phy-handle = <&switch0phy0>;
};
- switch0port2: ethernet-port@2 {
+ switch0port2: port@2 {
reg = <2>;
label = "lan1";
phy-handle = <&switch0phy1>;
};
- switch0port3: ethernet-port@3 {
+ switch0port3: port@3 {
reg = <3>;
label = "lan2";
phy-handle = <&switch0phy2>;
};
- switch0port4: ethernet-port@4 {
+ switch0port4: port@4 {
reg = <4>;
label = "lan3";
phy-handle = <&switch0phy3>;
};
- switch0port5: ethernet-port@5 {
+ switch0port5: port@5 {
reg = <5>;
label = "wan";
phy-handle = <&extphy>;
@@ -160,7 +160,7 @@
};
mdio {
- switch0phy3: ethernet-phy@14 {
+ switch0phy3: switch0phy3@14 {
reg = <0x14>;
};
};
diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi
index fed2dcecb323..49cbdb55b4b3 100644
--- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi
@@ -145,17 +145,19 @@
};
&mdio {
- switch0: ethernet-switch@1 {
+ switch0: switch0@1 {
compatible = "marvell,mv88e6085";
+ #address-cells = <1>;
+ #size-cells = <0>;
reg = <1>;
dsa,member = <0 0>;
- ethernet-ports {
+ ports {
#address-cells = <1>;
#size-cells = <0>;
- switch0port0: ethernet-port@0 {
+ switch0port0: port@0 {
reg = <0>;
label = "cpu";
ethernet = <&eth0>;
@@ -166,19 +168,19 @@
};
};
- switch0port1: ethernet-port@1 {
+ switch0port1: port@1 {
reg = <1>;
label = "wan";
phy-handle = <&switch0phy0>;
};
- switch0port2: ethernet-port@2 {
+ switch0port2: port@2 {
reg = <2>;
label = "lan0";
phy-handle = <&switch0phy1>;
};
- switch0port3: ethernet-port@3 {
+ switch0port3: port@3 {
reg = <3>;
label = "lan1";
phy-handle = <&switch0phy2>;
@@ -190,13 +192,13 @@
#address-cells = <1>;
#size-cells = <0>;
- switch0phy0: ethernet-phy@11 {
+ switch0phy0: switch0phy0@11 {
reg = <0x11>;
};
- switch0phy1: ethernet-phy@12 {
+ switch0phy1: switch0phy1@12 {
reg = <0x12>;
};
- switch0phy2: ethernet-phy@13 {
+ switch0phy2: switch0phy2@13 {
reg = <0x13>;
};
};
diff --git a/arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts b/arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts
index 63fbc8352161..b1b45b4fa9d4 100644
--- a/arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts
+++ b/arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts
@@ -152,29 +152,31 @@
};
&mdio {
- switch0: ethernet-switch@1 {
+ switch0: switch0@1 {
compatible = "marvell,mv88e6085";
+ #address-cells = <1>;
+ #size-cells = <0>;
reg = <1>;
dsa,member = <0 0>;
- ports: ethernet-ports {
+ ports: ports {
#address-cells = <1>;
#size-cells = <0>;
- ethernet-port@0 {
+ port@0 {
reg = <0>;
label = "cpu";
ethernet = <&eth0>;
};
- ethernet-port@1 {
+ port@1 {
reg = <1>;
label = "wan";
phy-handle = <&switch0phy0>;
};
- ethernet-port@2 {
+ port@2 {
reg = <2>;
label = "lan0";
phy-handle = <&switch0phy1>;
@@ -183,7 +185,7 @@
nvmem-cell-names = "mac-address";
};
- ethernet-port@3 {
+ port@3 {
reg = <3>;
label = "lan1";
phy-handle = <&switch0phy2>;
@@ -197,13 +199,13 @@
#address-cells = <1>;
#size-cells = <0>;
- switch0phy0: ethernet-phy@11 {
+ switch0phy0: switch0phy0@11 {
reg = <0x11>;
};
- switch0phy1: ethernet-phy@12 {
+ switch0phy1: switch0phy1@12 {
reg = <0x12>;
};
- switch0phy2: ethernet-phy@13 {
+ switch0phy2: switch0phy2@13 {
reg = <0x13>;
};
};
diff --git a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts
index cdf1b8bdb230..9eab2bb22134 100644
--- a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts
+++ b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts
@@ -304,12 +304,7 @@
reg = <1>;
};
- /*
- * NOTE: switch nodes are enabled by U-Boot if modules are present
- * DO NOT change this node name (switch0@10) even if it is not following
- * conventions! Deployed U-Boot binaries are explicitly looking for
- * this node in order to augment the device tree!
- */
+ /* switch nodes are enabled by U-Boot if modules are present */
switch0@10 {
compatible = "marvell,mv88e6190";
reg = <0x10>;
@@ -322,92 +317,92 @@
#address-cells = <1>;
#size-cells = <0>;
- switch0phy1: ethernet-phy@1 {
+ switch0phy1: switch0phy1@1 {
reg = <0x1>;
};
- switch0phy2: ethernet-phy@2 {
+ switch0phy2: switch0phy2@2 {
reg = <0x2>;
};
- switch0phy3: ethernet-phy@3 {
+ switch0phy3: switch0phy3@3 {
reg = <0x3>;
};
- switch0phy4: ethernet-phy@4 {
+ switch0phy4: switch0phy4@4 {
reg = <0x4>;
};
- switch0phy5: ethernet-phy@5 {
+ switch0phy5: switch0phy5@5 {
reg = <0x5>;
};
- switch0phy6: ethernet-phy@6 {
+ switch0phy6: switch0phy6@6 {
reg = <0x6>;
};
- switch0phy7: ethernet-phy@7 {
+ switch0phy7: switch0phy7@7 {
reg = <0x7>;
};
- switch0phy8: ethernet-phy@8 {
+ switch0phy8: switch0phy8@8 {
reg = <0x8>;
};
};
- ethernet-ports {
+ ports {
#address-cells = <1>;
#size-cells = <0>;
- ethernet-port@1 {
+ port@1 {
reg = <0x1>;
label = "lan1";
phy-handle = <&switch0phy1>;
};
- ethernet-port@2 {
+ port@2 {
reg = <0x2>;
label = "lan2";
phy-handle = <&switch0phy2>;
};
- ethernet-port@3 {
+ port@3 {
reg = <0x3>;
label = "lan3";
phy-handle = <&switch0phy3>;
};
- ethernet-port@4 {
+ port@4 {
reg = <0x4>;
label = "lan4";
phy-handle = <&switch0phy4>;
};
- ethernet-port@5 {
+ port@5 {
reg = <0x5>;
label = "lan5";
phy-handle = <&switch0phy5>;
};
- ethernet-port@6 {
+ port@6 {
reg = <0x6>;
label = "lan6";
phy-handle = <&switch0phy6>;
};
- ethernet-port@7 {
+ port@7 {
reg = <0x7>;
label = "lan7";
phy-handle = <&switch0phy7>;
};
- ethernet-port@8 {
+ port@8 {
reg = <0x8>;
label = "lan8";
phy-handle = <&switch0phy8>;
};
- ethernet-port@9 {
+ port@9 {
reg = <0x9>;
label = "cpu";
ethernet = <&eth1>;
@@ -415,7 +410,7 @@
managed = "in-band-status";
};
- switch0port10: ethernet-port@a {
+ switch0port10: port@a {
reg = <0xa>;
label = "dsa";
phy-mode = "2500base-x";
@@ -435,7 +430,7 @@
};
};
- ethernet-switch@2 {
+ switch0@2 {
compatible = "marvell,mv88e6085";
reg = <0x2>;
dsa,member = <0 0>;
@@ -447,52 +442,52 @@
#address-cells = <1>;
#size-cells = <0>;
- switch0phy1_topaz: ethernet-phy@11 {
+ switch0phy1_topaz: switch0phy1@11 {
reg = <0x11>;
};
- switch0phy2_topaz: ethernet-phy@12 {
+ switch0phy2_topaz: switch0phy2@12 {
reg = <0x12>;
};
- switch0phy3_topaz: ethernet-phy@13 {
+ switch0phy3_topaz: switch0phy3@13 {
reg = <0x13>;
};
- switch0phy4_topaz: ethernet-phy@14 {
+ switch0phy4_topaz: switch0phy4@14 {
reg = <0x14>;
};
};
- ethernet-ports {
+ ports {
#address-cells = <1>;
#size-cells = <0>;
- ethernet-port@1 {
+ port@1 {
reg = <0x1>;
label = "lan1";
phy-handle = <&switch0phy1_topaz>;
};
- ethernet-port@2 {
+ port@2 {
reg = <0x2>;
label = "lan2";
phy-handle = <&switch0phy2_topaz>;
};
- ethernet-port@3 {
+ port@3 {
reg = <0x3>;
label = "lan3";
phy-handle = <&switch0phy3_topaz>;
};
- ethernet-port@4 {
+ port@4 {
reg = <0x4>;
label = "lan4";
phy-handle = <&switch0phy4_topaz>;
};
- ethernet-port@5 {
+ port@5 {
reg = <0x5>;
label = "cpu";
phy-mode = "2500base-x";
@@ -502,7 +497,7 @@
};
};
- ethernet-switch@11 {
+ switch1@11 {
compatible = "marvell,mv88e6190";
reg = <0x11>;
dsa,member = <0 1>;
@@ -514,92 +509,92 @@
#address-cells = <1>;
#size-cells = <0>;
- switch1phy1: ethernet-phy@1 {
+ switch1phy1: switch1phy1@1 {
reg = <0x1>;
};
- switch1phy2: ethernet-phy@2 {
+ switch1phy2: switch1phy2@2 {
reg = <0x2>;
};
- switch1phy3: ethernet-phy@3 {
+ switch1phy3: switch1phy3@3 {
reg = <0x3>;
};
- switch1phy4: ethernet-phy@4 {
+ switch1phy4: switch1phy4@4 {
reg = <0x4>;
};
- switch1phy5: ethernet-phy@5 {
+ switch1phy5: switch1phy5@5 {
reg = <0x5>;
};
- switch1phy6: ethernet-phy@6 {
+ switch1phy6: switch1phy6@6 {
reg = <0x6>;
};
- switch1phy7: ethernet-phy@7 {
+ switch1phy7: switch1phy7@7 {
reg = <0x7>;
};
- switch1phy8: ethernet-phy@8 {
+ switch1phy8: switch1phy8@8 {
reg = <0x8>;
};
};
- ethernet-ports {
+ ports {
#address-cells = <1>;
#size-cells = <0>;
- ethernet-port@1 {
+ port@1 {
reg = <0x1>;
label = "lan9";
phy-handle = <&switch1phy1>;
};
- ethernet-port@2 {
+ port@2 {
reg = <0x2>;
label = "lan10";
phy-handle = <&switch1phy2>;
};
- ethernet-port@3 {
+ port@3 {
reg = <0x3>;
label = "lan11";
phy-handle = <&switch1phy3>;
};
- ethernet-port@4 {
+ port@4 {
reg = <0x4>;
label = "lan12";
phy-handle = <&switch1phy4>;
};
- ethernet-port@5 {
+ port@5 {
reg = <0x5>;
label = "lan13";
phy-handle = <&switch1phy5>;
};
- ethernet-port@6 {
+ port@6 {
reg = <0x6>;
label = "lan14";
phy-handle = <&switch1phy6>;
};
- ethernet-port@7 {
+ port@7 {
reg = <0x7>;
label = "lan15";
phy-handle = <&switch1phy7>;
};
- ethernet-port@8 {
+ port@8 {
reg = <0x8>;
label = "lan16";
phy-handle = <&switch1phy8>;
};
- switch1port9: ethernet-port@9 {
+ switch1port9: port@9 {
reg = <0x9>;
label = "dsa";
phy-mode = "2500base-x";
@@ -607,7 +602,7 @@
link = <&switch0port10>;
};
- switch1port10: ethernet-port@a {
+ switch1port10: port@a {
reg = <0xa>;
label = "dsa";
phy-mode = "2500base-x";
@@ -627,7 +622,7 @@
};
};
- ethernet-switch@2 {
+ switch1@2 {
compatible = "marvell,mv88e6085";
reg = <0x2>;
dsa,member = <0 1>;
@@ -639,52 +634,52 @@
#address-cells = <1>;
#size-cells = <0>;
- switch1phy1_topaz: ethernet-phy@11 {
+ switch1phy1_topaz: switch1phy1@11 {
reg = <0x11>;
};
- switch1phy2_topaz: ethernet-phy@12 {
+ switch1phy2_topaz: switch1phy2@12 {
reg = <0x12>;
};
- switch1phy3_topaz: ethernet-phy@13 {
+ switch1phy3_topaz: switch1phy3@13 {
reg = <0x13>;
};
- switch1phy4_topaz: ethernet-phy@14 {
+ switch1phy4_topaz: switch1phy4@14 {
reg = <0x14>;
};
};
- ethernet-ports {
+ ports {
#address-cells = <1>;
#size-cells = <0>;
- ethernet-port@1 {
+ port@1 {
reg = <0x1>;
label = "lan9";
phy-handle = <&switch1phy1_topaz>;
};
- ethernet-port@2 {
+ port@2 {
reg = <0x2>;
label = "lan10";
phy-handle = <&switch1phy2_topaz>;
};
- ethernet-port@3 {
+ port@3 {
reg = <0x3>;
label = "lan11";
phy-handle = <&switch1phy3_topaz>;
};
- ethernet-port@4 {
+ port@4 {
reg = <0x4>;
label = "lan12";
phy-handle = <&switch1phy4_topaz>;
};
- ethernet-port@5 {
+ port@5 {
reg = <0x5>;
label = "dsa";
phy-mode = "2500base-x";
@@ -694,7 +689,7 @@
};
};
- ethernet-switch@12 {
+ switch2@12 {
compatible = "marvell,mv88e6190";
reg = <0x12>;
dsa,member = <0 2>;
@@ -706,92 +701,92 @@
#address-cells = <1>;
#size-cells = <0>;
- switch2phy1: ethernet-phy@1 {
+ switch2phy1: switch2phy1@1 {
reg = <0x1>;
};
- switch2phy2: ethernet-phy@2 {
+ switch2phy2: switch2phy2@2 {
reg = <0x2>;
};
- switch2phy3: ethernet-phy@3 {
+ switch2phy3: switch2phy3@3 {
reg = <0x3>;
};
- switch2phy4: ethernet-phy@4 {
+ switch2phy4: switch2phy4@4 {
reg = <0x4>;
};
- switch2phy5: ethernet-phy@5 {
+ switch2phy5: switch2phy5@5 {
reg = <0x5>;
};
- switch2phy6: ethernet-phy@6 {
+ switch2phy6: switch2phy6@6 {
reg = <0x6>;
};
- switch2phy7: ethernet-phy@7 {
+ switch2phy7: switch2phy7@7 {
reg = <0x7>;
};
- switch2phy8: ethernet-phy@8 {
+ switch2phy8: switch2phy8@8 {
reg = <0x8>;
};
};
- ethernet-ports {
+ ports {
#address-cells = <1>;
#size-cells = <0>;
- ethernet-port@1 {
+ port@1 {
reg = <0x1>;
label = "lan17";
phy-handle = <&switch2phy1>;
};
- ethernet-port@2 {
+ port@2 {
reg = <0x2>;
label = "lan18";
phy-handle = <&switch2phy2>;
};
- ethernet-port@3 {
+ port@3 {
reg = <0x3>;
label = "lan19";
phy-handle = <&switch2phy3>;
};
- ethernet-port@4 {
+ port@4 {
reg = <0x4>;
label = "lan20";
phy-handle = <&switch2phy4>;
};
- ethernet-port@5 {
+ port@5 {
reg = <0x5>;
label = "lan21";
phy-handle = <&switch2phy5>;
};
- ethernet-port@6 {
+ port@6 {
reg = <0x6>;
label = "lan22";
phy-handle = <&switch2phy6>;
};
- ethernet-port@7 {
+ port@7 {
reg = <0x7>;
label = "lan23";
phy-handle = <&switch2phy7>;
};
- ethernet-port@8 {
+ port@8 {
reg = <0x8>;
label = "lan24";
phy-handle = <&switch2phy8>;
};
- switch2port9: ethernet-port@9 {
+ switch2port9: port@9 {
reg = <0x9>;
label = "dsa";
phy-mode = "2500base-x";
@@ -810,7 +805,7 @@
};
};
- ethernet-switch@2 {
+ switch2@2 {
compatible = "marvell,mv88e6085";
reg = <0x2>;
dsa,member = <0 2>;
@@ -822,52 +817,52 @@
#address-cells = <1>;
#size-cells = <0>;
- switch2phy1_topaz: ethernet-phy@11 {
+ switch2phy1_topaz: switch2phy1@11 {
reg = <0x11>;
};
- switch2phy2_topaz: ethernet-phy@12 {
+ switch2phy2_topaz: switch2phy2@12 {
reg = <0x12>;
};
- switch2phy3_topaz: ethernet-phy@13 {
+ switch2phy3_topaz: switch2phy3@13 {
reg = <0x13>;
};
- switch2phy4_topaz: ethernet-phy@14 {
+ switch2phy4_topaz: switch2phy4@14 {
reg = <0x14>;
};
};
- ethernet-ports {
+ ports {
#address-cells = <1>;
#size-cells = <0>;
- ethernet-port@1 {
+ port@1 {
reg = <0x1>;
label = "lan17";
phy-handle = <&switch2phy1_topaz>;
};
- ethernet-port@2 {
+ port@2 {
reg = <0x2>;
label = "lan18";
phy-handle = <&switch2phy2_topaz>;
};
- ethernet-port@3 {
+ port@3 {
reg = <0x3>;
label = "lan19";
phy-handle = <&switch2phy3_topaz>;
};
- ethernet-port@4 {
+ port@4 {
reg = <0x4>;
label = "lan20";
phy-handle = <&switch2phy4_topaz>;
};
- ethernet-port@5 {
+ port@5 {
reg = <0x5>;
label = "dsa";
phy-mode = "2500base-x";
diff --git a/arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts b/arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts
index 40b7ee7ead72..48202810bf78 100644
--- a/arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts
+++ b/arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts
@@ -301,8 +301,10 @@
};
/* 88E6141 Topaz switch */
- switch: ethernet-switch@3 {
+ switch: switch@3 {
compatible = "marvell,mv88e6085";
+ #address-cells = <1>;
+ #size-cells = <0>;
reg = <3>;
pinctrl-names = "default";
@@ -312,35 +314,35 @@
interrupt-parent = <&cp0_gpio1>;
interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
- ethernet-ports {
+ ports {
#address-cells = <1>;
#size-cells = <0>;
- swport1: ethernet-port@1 {
+ swport1: port@1 {
reg = <1>;
label = "lan0";
phy-handle = <&swphy1>;
};
- swport2: ethernet-port@2 {
+ swport2: port@2 {
reg = <2>;
label = "lan1";
phy-handle = <&swphy2>;
};
- swport3: ethernet-port@3 {
+ swport3: port@3 {
reg = <3>;
label = "lan2";
phy-handle = <&swphy3>;
};
- swport4: ethernet-port@4 {
+ swport4: port@4 {
reg = <4>;
label = "lan3";
phy-handle = <&swphy4>;
};
- ethernet-port@5 {
+ port@5 {
reg = <5>;
label = "cpu";
ethernet = <&cp0_eth1>;
@@ -353,19 +355,19 @@
#address-cells = <1>;
#size-cells = <0>;
- swphy1: ethernet-phy@17 {
+ swphy1: swphy1@17 {
reg = <17>;
};
- swphy2: ethernet-phy@18 {
+ swphy2: swphy2@18 {
reg = <18>;
};
- swphy3: ethernet-phy@19 {
+ swphy3: swphy3@19 {
reg = <19>;
};
- swphy4: ethernet-phy@20 {
+ swphy4: swphy4@20 {
reg = <20>;
};
};
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
index 67892f0d2863..4125202028c8 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
+++ b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
@@ -497,42 +497,42 @@
reset-deassert-us = <10000>;
};
- switch0: ethernet-switch@4 {
+ switch0: switch0@4 {
compatible = "marvell,mv88e6085";
reg = <4>;
pinctrl-names = "default";
pinctrl-0 = <&cp1_switch_reset_pins>;
reset-gpios = <&cp1_gpio1 24 GPIO_ACTIVE_LOW>;
- ethernet-ports {
+ ports {
#address-cells = <1>;
#size-cells = <0>;
- ethernet-port@1 {
+ port@1 {
reg = <1>;
label = "lan2";
phy-handle = <&switch0phy0>;
};
- ethernet-port@2 {
+ port@2 {
reg = <2>;
label = "lan1";
phy-handle = <&switch0phy1>;
};
- ethernet-port@3 {
+ port@3 {
reg = <3>;
label = "lan4";
phy-handle = <&switch0phy2>;
};
- ethernet-port@4 {
+ port@4 {
reg = <4>;
label = "lan3";
phy-handle = <&switch0phy3>;
};
- ethernet-port@5 {
+ port@5 {
reg = <5>;
label = "cpu";
ethernet = <&cp1_eth2>;
@@ -545,19 +545,19 @@
#address-cells = <1>;
#size-cells = <0>;
- switch0phy0: ethernet-phy@11 {
+ switch0phy0: switch0phy0@11 {
reg = <0x11>;
};
- switch0phy1: ethernet-phy@12 {
+ switch0phy1: switch0phy1@12 {
reg = <0x12>;
};
- switch0phy2: ethernet-phy@13 {
+ switch0phy2: switch0phy2@13 {
reg = <0x13>;
};
- switch0phy3: ethernet-phy@14 {
+ switch0phy3: switch0phy3@14 {
reg = <0x14>;
};
};
diff --git a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi
index 7538ed56053b..32cfb3e2efc3 100644
--- a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi
+++ b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi
@@ -207,9 +207,11 @@
reg = <0>;
};
- switch6: ethernet-switch@6 {
+ switch6: switch0@6 {
/* Actual device is MV88E6393X */
compatible = "marvell,mv88e6190";
+ #address-cells = <1>;
+ #size-cells = <0>;
reg = <6>;
interrupt-parent = <&cp0_gpio1>;
interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
@@ -218,59 +220,59 @@
dsa,member = <0 0>;
- ethernet-ports {
+ ports {
#address-cells = <1>;
#size-cells = <0>;
- ethernet-port@1 {
+ port@1 {
reg = <1>;
label = "p1";
phy-handle = <&switch0phy1>;
};
- ethernet-port@2 {
+ port@2 {
reg = <2>;
label = "p2";
phy-handle = <&switch0phy2>;
};
- ethernet-port@3 {
+ port@3 {
reg = <3>;
label = "p3";
phy-handle = <&switch0phy3>;
};
- ethernet-port@4 {
+ port@4 {
reg = <4>;
label = "p4";
phy-handle = <&switch0phy4>;
};
- ethernet-port@5 {
+ port@5 {
reg = <5>;
label = "p5";
phy-handle = <&switch0phy5>;
};
- ethernet-port@6 {
+ port@6 {
reg = <6>;
label = "p6";
phy-handle = <&switch0phy6>;
};
- ethernet-port@7 {
+ port@7 {
reg = <7>;
label = "p7";
phy-handle = <&switch0phy7>;
};
- ethernet-port@8 {
+ port@8 {
reg = <8>;
label = "p8";
phy-handle = <&switch0phy8>;
};
- ethernet-port@9 {
+ port@9 {
reg = <9>;
label = "p9";
phy-mode = "10gbase-r";
@@ -278,7 +280,7 @@
managed = "in-band-status";
};
- ethernet-port@a {
+ port@a {
reg = <10>;
ethernet = <&cp0_eth0>;
phy-mode = "10gbase-r";
@@ -291,35 +293,35 @@
#address-cells = <1>;
#size-cells = <0>;
- switch0phy1: ethernet-phy@1 {
+ switch0phy1: switch0phy1@1 {
reg = <0x1>;
};
- switch0phy2: ethernet-phy@2 {
+ switch0phy2: switch0phy2@2 {
reg = <0x2>;
};
- switch0phy3: ethernet-phy@3 {
+ switch0phy3: switch0phy3@3 {
reg = <0x3>;
};
- switch0phy4: ethernet-phy@4 {
+ switch0phy4: switch0phy4@4 {
reg = <0x4>;
};
- switch0phy5: ethernet-phy@5 {
+ switch0phy5: switch0phy5@5 {
reg = <0x5>;
};
- switch0phy6: ethernet-phy@6 {
+ switch0phy6: switch0phy6@6 {
reg = <0x6>;
};
- switch0phy7: ethernet-phy@7 {
+ switch0phy7: switch0phy7@7 {
reg = <0x7>;
};
- switch0phy8: ethernet-phy@8 {
+ switch0phy8: switch0phy8@8 {
reg = <0x8>;
};
};
generated by cgit v1.2.3 (git 2.39.0) at 2024-12-02 09:33:05 +0300