diff options
Diffstat (limited to 'arch/arm64/boot/dts/qcom')
165 files changed, 26102 insertions, 4585 deletions
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 3e79496292e7..31aa54f0428c 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -7,8 +7,10 @@ dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c1.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c2.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8916-acer-a1-724.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-alcatel-idol347.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-asus-z00l.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8916-gplus-fl8005a.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-huawei-g7.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-longcheer-l8150.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-longcheer-l8910.dtb @@ -18,9 +20,19 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-a5u-eur.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-e5.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-e7.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-grandmax.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-gt510.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-gt58.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-j5.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-j5x.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-serranove.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8916-thwc-uf896.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8916-thwc-ufi001c.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-wingtech-wt88047.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8953-motorola-potter.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8953-xiaomi-daisy.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8953-xiaomi-mido.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8953-xiaomi-tissot.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8953-xiaomi-vince.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8956-sony-xperia-loire-kugo.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8956-sony-xperia-loire-suzu.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8992-lg-bullhead-rev-10.dtb @@ -56,8 +68,10 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8998-sony-xperia-yoshino-poplar.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-xiaomi-sagit.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb +dtb-$(CONFIG_ARCH_QCOM) += qdu1000-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5.dtb dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5-vision-mezzanine.dtb +dtb-$(CONFIG_ARCH_QCOM) += qru1000-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += sa8155p-adp.dtb dtb-$(CONFIG_ARCH_QCOM) += sa8295p-adp.dtb dtb-$(CONFIG_ARCH_QCOM) += sa8540p-ride.dtb @@ -113,6 +127,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-wormdingler-rev1-boe-rt5682s.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-crd.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-crd-pro.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-evoker.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-evoker-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-herobrine-r1.dtb @@ -121,17 +136,21 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-villager-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-villager-r1-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-zombie.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-zombie-lte.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-zombie-nvme.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-zombie-nvme-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp2.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-crd-r3.dtb dtb-$(CONFIG_ARCH_QCOM) += sc8280xp-crd.dtb dtb-$(CONFIG_ARCH_QCOM) += sc8280xp-lenovo-thinkpad-x13s.dtb dtb-$(CONFIG_ARCH_QCOM) += sda660-inforce-ifc6560.dtb +dtb-$(CONFIG_ARCH_QCOM) += sdm450-motorola-ali.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-ganges-kirin.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-discovery.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-pioneer.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-voyager.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm632-fairphone-fp3.dtb +dtb-$(CONFIG_ARCH_QCOM) += sdm632-motorola-ocean.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm636-sony-xperia-ganges-mermaid.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm660-xiaomi-lavender.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm670-google-sargo.dtb @@ -156,6 +175,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-shift-axolotl.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm850-samsung-w737.dtb dtb-$(CONFIG_ARCH_QCOM) += sm4250-oneplus-billie2.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm6115p-lenovo-j606f.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6125-sony-xperia-seine-pdx201.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6350-sony-xperia-lena-pdx213.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6375-sony-xperia-murray-pdx225.dtb @@ -169,6 +189,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8250-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8250-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8250-sony-xperia-edo-pdx203.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8250-sony-xperia-edo-pdx206.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm8250-xiaomi-elish.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8350-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8350-microsoft-surface-duo2.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8350-mtp.dtb @@ -178,3 +199,4 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8450-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8450-qrd.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8450-sony-xperia-nagara-pdx223.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8450-sony-xperia-nagara-pdx224.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm8550-mtp.dtb diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts index ef5b39ba1238..c52d79a55d80 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts @@ -169,10 +169,6 @@ }; }; -&blsp_dma { - status = "okay"; -}; - &blsp_i2c2 { /* On Low speed expansion */ status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index 5d453f11acd9..bbd94025ff5d 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -87,6 +87,12 @@ }; }; + firmware { + scm { + compatible = "qcom,scm-ipq6018", "qcom,scm"; + }; + }; + cpu_opp_table: opp-table-cpu { compatible = "operating-points-v2"; opp-shared; @@ -96,26 +102,31 @@ opp-microvolt = <725000>; clock-latency-ns = <200000>; }; + opp-1056000000 { opp-hz = /bits/ 64 <1056000000>; opp-microvolt = <787500>; clock-latency-ns = <200000>; }; + opp-1320000000 { opp-hz = /bits/ 64 <1320000000>; opp-microvolt = <862500>; clock-latency-ns = <200000>; }; + opp-1440000000 { opp-hz = /bits/ 64 <1440000000>; opp-microvolt = <925000>; clock-latency-ns = <200000>; }; + opp-1608000000 { opp-hz = /bits/ 64 <1608000000>; opp-microvolt = <987500>; clock-latency-ns = <200000>; }; + opp-1800000000 { opp-hz = /bits/ 64 <1800000000>; opp-microvolt = <1062500>; @@ -123,16 +134,9 @@ }; }; - firmware { - scm { - compatible = "qcom,scm-ipq6018", "qcom,scm"; - }; - }; - pmuv8: pmu { compatible = "arm,cortex-a53-pmu"; - interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | - IRQ_TYPE_LEVEL_HIGH)>; + interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; psci: psci { @@ -146,7 +150,7 @@ ranges; rpm_msg_ram: memory@60000 { - reg = <0x0 0x60000 0x0 0x6000>; + reg = <0x0 0x00060000 0x0 0x6000>; no-map; }; @@ -166,6 +170,28 @@ }; }; + rpm-glink { + compatible = "qcom,glink-rpm"; + interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + mboxes = <&apcs_glb 0>; + + rpm_requests: rpm-requests { + compatible = "qcom,rpm-ipq6018"; + qcom,glink-channels = "rpm_requests"; + + regulators { + compatible = "qcom,rpm-mp5496-regulators"; + + ipq6018_s2: s2 { + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1062500>; + regulator-always-on; + }; + }; + }; + }; + smem { compatible = "qcom,smem"; memory-region = <&smem_region>; @@ -179,9 +205,105 @@ dma-ranges; compatible = "simple-bus"; + qusb_phy_1: qusb@59000 { + compatible = "qcom,ipq6018-qusb2-phy"; + reg = <0x0 0x00059000 0x0 0x180>; + #phy-cells = <0>; + + clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, + <&xo>; + clock-names = "cfg_ahb", "ref"; + + resets = <&gcc GCC_QUSB2_1_PHY_BCR>; + status = "disabled"; + }; + + ssphy_0: ssphy@78000 { + compatible = "qcom,ipq6018-qmp-usb3-phy"; + reg = <0x0 0x00078000 0x0 0x1c4>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&gcc GCC_USB0_AUX_CLK>, + <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, <&xo>; + clock-names = "aux", "cfg_ahb", "ref"; + + resets = <&gcc GCC_USB0_PHY_BCR>, + <&gcc GCC_USB3PHY_0_PHY_BCR>; + reset-names = "phy","common"; + status = "disabled"; + + usb0_ssphy: phy@78200 { + reg = <0x0 0x00078200 0x0 0x130>, /* Tx */ + <0x0 0x00078400 0x0 0x200>, /* Rx */ + <0x0 0x00078800 0x0 0x1f8>, /* PCS */ + <0x0 0x00078600 0x0 0x044>; /* PCS misc */ + #phy-cells = <0>; + #clock-cells = <0>; + clocks = <&gcc GCC_USB0_PIPE_CLK>; + clock-names = "pipe0"; + clock-output-names = "gcc_usb0_pipe_clk_src"; + }; + }; + + qusb_phy_0: qusb@79000 { + compatible = "qcom,ipq6018-qusb2-phy"; + reg = <0x0 0x00079000 0x0 0x180>; + #phy-cells = <0>; + + clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, + <&xo>; + clock-names = "cfg_ahb", "ref"; + + resets = <&gcc GCC_QUSB2_0_PHY_BCR>; + status = "disabled"; + }; + + pcie_phy: phy@84000 { + compatible = "qcom,ipq6018-qmp-pcie-phy"; + reg = <0x0 0x00084000 0x0 0x1bc>; /* Serdes PLL */ + status = "disabled"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&gcc GCC_PCIE0_AUX_CLK>, + <&gcc GCC_PCIE0_AHB_CLK>; + clock-names = "aux", "cfg_ahb"; + + resets = <&gcc GCC_PCIE0_PHY_BCR>, + <&gcc GCC_PCIE0PHY_PHY_BCR>; + reset-names = "phy", + "common"; + + pcie_phy0: phy@84200 { + reg = <0x0 0x00084200 0x0 0x16c>, /* Serdes Tx */ + <0x0 0x00084400 0x0 0x200>, /* Serdes Rx */ + <0x0 0x00084800 0x0 0x1f0>, /* PCS: Lane0, COM, PCIE */ + <0x0 0x00084c00 0x0 0xf4>; /* pcs_misc */ + #phy-cells = <0>; + + clocks = <&gcc GCC_PCIE0_PIPE_CLK>; + clock-names = "pipe0"; + clock-output-names = "gcc_pcie0_pipe_clk_src"; + #clock-cells = <0>; + }; + }; + + mdio: mdio@90000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "qcom,ipq6018-mdio", "qcom,ipq4019-mdio"; + reg = <0x0 0x00090000 0x0 0x64>; + clocks = <&gcc GCC_MDIO_AHB_CLK>; + clock-names = "gcc_mdio_ahb_clk"; + status = "disabled"; + }; + prng: qrng@e1000 { compatible = "qcom,prng-ee"; - reg = <0x0 0xe3000 0x0 0x1000>; + reg = <0x0 0x000e3000 0x0 0x1000>; clocks = <&gcc GCC_PRNG_AHB_CLK>; clock-names = "core"; }; @@ -201,8 +323,8 @@ compatible = "qcom,crypto-v5.1"; reg = <0x0 0x0073a000 0x0 0x6000>; clocks = <&gcc GCC_CRYPTO_AHB_CLK>, - <&gcc GCC_CRYPTO_AXI_CLK>, - <&gcc GCC_CRYPTO_CLK>; + <&gcc GCC_CRYPTO_AXI_CLK>, + <&gcc GCC_CRYPTO_CLK>; clock-names = "iface", "bus", "core"; dmas = <&cryptobam 2>, <&cryptobam 3>; dma-names = "rx", "tx"; @@ -257,6 +379,41 @@ reg = <0x0 0x01937000 0x0 0x21000>; }; + usb2: usb@70f8800 { + compatible = "qcom,ipq6018-dwc3", "qcom,dwc3"; + reg = <0x0 0x070f8800 0x0 0x400>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clocks = <&gcc GCC_USB1_MASTER_CLK>, + <&gcc GCC_USB1_SLEEP_CLK>, + <&gcc GCC_USB1_MOCK_UTMI_CLK>; + clock-names = "core", + "sleep", + "mock_utmi"; + + assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>, + <&gcc GCC_USB1_MOCK_UTMI_CLK>; + assigned-clock-rates = <133330000>, + <24000000>; + resets = <&gcc GCC_USB1_BCR>; + status = "disabled"; + + dwc_1: usb@7000000 { + compatible = "snps,dwc3"; + reg = <0x0 0x07000000 0x0 0xcd00>; + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; + phys = <&qusb_phy_1>; + phy-names = "usb2-phy"; + tx-fifo-resize; + snps,is-utmi-l1-suspend; + snps,hird-threshold = /bits/ 8 <0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + dr_mode = "host"; + }; + }; + blsp_dma: dma-controller@7884000 { compatible = "qcom,bam-v1.7.0"; reg = <0x0 0x07884000 0x0 0x2b000>; @@ -272,7 +429,7 @@ reg = <0x0 0x078b1000 0x0 0x200>; interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; + <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; status = "disabled"; }; @@ -285,7 +442,7 @@ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; spi-max-frequency = <50000000>; clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; + <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; dmas = <&blsp_dma 12>, <&blsp_dma 13>; dma-names = "tx", "rx"; @@ -300,7 +457,7 @@ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; spi-max-frequency = <50000000>; clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; + <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; dmas = <&blsp_dma 14>, <&blsp_dma 15>; dma-names = "tx", "rx"; @@ -358,24 +515,67 @@ clock-names = "core", "aon"; dmas = <&qpic_bam 0>, - <&qpic_bam 1>, - <&qpic_bam 2>; + <&qpic_bam 1>, + <&qpic_bam 2>; dma-names = "tx", "rx", "cmd"; pinctrl-0 = <&qpic_pins>; pinctrl-names = "default"; status = "disabled"; }; + usb3: usb@8af8800 { + compatible = "qcom,ipq6018-dwc3", "qcom,dwc3"; + reg = <0x0 0x08af8800 0x0 0x400>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, + <&gcc GCC_USB0_MASTER_CLK>, + <&gcc GCC_USB0_SLEEP_CLK>, + <&gcc GCC_USB0_MOCK_UTMI_CLK>; + clock-names = "cfg_noc", + "core", + "sleep", + "mock_utmi"; + + assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, + <&gcc GCC_USB0_MASTER_CLK>, + <&gcc GCC_USB0_MOCK_UTMI_CLK>; + assigned-clock-rates = <133330000>, + <133330000>, + <20000000>; + + resets = <&gcc GCC_USB0_BCR>; + status = "disabled"; + + dwc_0: usb@8a00000 { + compatible = "snps,dwc3"; + reg = <0x0 0x08a00000 0x0 0xcd00>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; + phys = <&qusb_phy_0>, <&usb0_ssphy>; + phy-names = "usb2-phy", "usb3-phy"; + clocks = <&xo>; + clock-names = "ref"; + tx-fifo-resize; + snps,is-utmi-l1-suspend; + snps,hird-threshold = /bits/ 8 <0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + dr_mode = "host"; + }; + }; + intc: interrupt-controller@b000000 { compatible = "qcom,msm-qgic2"; #address-cells = <2>; #size-cells = <2>; interrupt-controller; #interrupt-cells = <0x3>; - reg = <0x0 0x0b000000 0x0 0x1000>, /*GICD*/ - <0x0 0x0b002000 0x0 0x1000>, /*GICC*/ - <0x0 0x0b001000 0x0 0x1000>, /*GICH*/ - <0x0 0x0b004000 0x0 0x1000>; /*GICV*/ + reg = <0x0 0x0b000000 0x0 0x1000>, /*GICD*/ + <0x0 0x0b002000 0x0 0x1000>, /*GICC*/ + <0x0 0x0b001000 0x0 0x1000>, /*GICH*/ + <0x0 0x0b004000 0x0 0x1000>; /*GICV*/ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; ranges = <0 0 0 0xb00a000 0 0xffd>; @@ -386,107 +586,6 @@ }; }; - pcie_phy: phy@84000 { - compatible = "qcom,ipq6018-qmp-pcie-phy"; - reg = <0x0 0x84000 0x0 0x1bc>; /* Serdes PLL */ - status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - clocks = <&gcc GCC_PCIE0_AUX_CLK>, - <&gcc GCC_PCIE0_AHB_CLK>; - clock-names = "aux", "cfg_ahb"; - - resets = <&gcc GCC_PCIE0_PHY_BCR>, - <&gcc GCC_PCIE0PHY_PHY_BCR>; - reset-names = "phy", - "common"; - - pcie_phy0: phy@84200 { - reg = <0x0 0x84200 0x0 0x16c>, /* Serdes Tx */ - <0x0 0x84400 0x0 0x200>, /* Serdes Rx */ - <0x0 0x84800 0x0 0x1f0>, /* PCS: Lane0, COM, PCIE */ - <0x0 0x84c00 0x0 0xf4>; /* pcs_misc */ - #phy-cells = <0>; - - clocks = <&gcc GCC_PCIE0_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "gcc_pcie0_pipe_clk_src"; - #clock-cells = <0>; - }; - }; - - pcie0: pci@20000000 { - compatible = "qcom,pcie-ipq6018"; - reg = <0x0 0x20000000 0x0 0xf1d>, - <0x0 0x20000f20 0x0 0xa8>, - <0x0 0x20001000 0x0 0x1000>, - <0x0 0x80000 0x0 0x4000>, - <0x0 0x20100000 0x0 0x1000>; - reg-names = "dbi", "elbi", "atu", "parf", "config"; - - device_type = "pci"; - linux,pci-domain = <0>; - bus-range = <0x00 0xff>; - num-lanes = <1>; - max-link-speed = <3>; - #address-cells = <3>; - #size-cells = <2>; - - phys = <&pcie_phy0>; - phy-names = "pciephy"; - - ranges = <0x81000000 0 0x20200000 0 0x20200000 - 0 0x10000>, /* downstream I/O */ - <0x82000000 0 0x20220000 0 0x20220000 - 0 0xfde0000>; /* non-prefetchable memory */ - - interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "msi"; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 75 - IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 78 - IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 79 - IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 83 - IRQ_TYPE_LEVEL_HIGH>; /* int_d */ - - clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, - <&gcc GCC_PCIE0_AXI_M_CLK>, - <&gcc GCC_PCIE0_AXI_S_CLK>, - <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>, - <&gcc PCIE0_RCHNG_CLK>; - clock-names = "iface", - "axi_m", - "axi_s", - "axi_bridge", - "rchng"; - - resets = <&gcc GCC_PCIE0_PIPE_ARES>, - <&gcc GCC_PCIE0_SLEEP_ARES>, - <&gcc GCC_PCIE0_CORE_STICKY_ARES>, - <&gcc GCC_PCIE0_AXI_MASTER_ARES>, - <&gcc GCC_PCIE0_AXI_SLAVE_ARES>, - <&gcc GCC_PCIE0_AHB_ARES>, - <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>, - <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>; - reset-names = "pipe", - "sleep", - "sticky", - "axi_m", - "axi_s", - "ahb", - "axi_m_sticky", - "axi_s_sticky"; - - status = "disabled"; - }; - watchdog@b017000 { compatible = "qcom,kpss-wdt"; interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; @@ -619,147 +718,68 @@ }; }; - mdio: mdio@90000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "qcom,ipq6018-mdio", "qcom,ipq4019-mdio"; - reg = <0x0 0x90000 0x0 0x64>; - clocks = <&gcc GCC_MDIO_AHB_CLK>; - clock-names = "gcc_mdio_ahb_clk"; - status = "disabled"; - }; - - qusb_phy_1: qusb@59000 { - compatible = "qcom,ipq6018-qusb2-phy"; - reg = <0x0 0x059000 0x0 0x180>; - #phy-cells = <0>; - - clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, - <&xo>; - clock-names = "cfg_ahb", "ref"; - - resets = <&gcc GCC_QUSB2_1_PHY_BCR>; - status = "disabled"; - }; - - usb2: usb@70f8800 { - compatible = "qcom,ipq6018-dwc3", "qcom,dwc3"; - reg = <0x0 0x070F8800 0x0 0x400>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - clocks = <&gcc GCC_USB1_MASTER_CLK>, - <&gcc GCC_USB1_SLEEP_CLK>, - <&gcc GCC_USB1_MOCK_UTMI_CLK>; - clock-names = "core", - "sleep", - "mock_utmi"; - - assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>, - <&gcc GCC_USB1_MOCK_UTMI_CLK>; - assigned-clock-rates = <133330000>, - <24000000>; - resets = <&gcc GCC_USB1_BCR>; - status = "disabled"; - - dwc_1: usb@7000000 { - compatible = "snps,dwc3"; - reg = <0x0 0x7000000 0x0 0xcd00>; - interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; - phys = <&qusb_phy_1>; - phy-names = "usb2-phy"; - tx-fifo-resize; - snps,is-utmi-l1-suspend; - snps,hird-threshold = /bits/ 8 <0x0>; - snps,dis_u2_susphy_quirk; - snps,dis_u3_susphy_quirk; - dr_mode = "host"; - }; - }; + pcie0: pci@20000000 { + compatible = "qcom,pcie-ipq6018"; + reg = <0x0 0x20000000 0x0 0xf1d>, + <0x0 0x20000f20 0x0 0xa8>, + <0x0 0x20001000 0x0 0x1000>, + <0x0 0x80000 0x0 0x4000>, + <0x0 0x20100000 0x0 0x1000>; + reg-names = "dbi", "elbi", "atu", "parf", "config"; - ssphy_0: ssphy@78000 { - compatible = "qcom,ipq6018-qmp-usb3-phy"; - reg = <0x0 0x78000 0x0 0x1C4>; - #address-cells = <2>; + device_type = "pci"; + linux,pci-domain = <0>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + max-link-speed = <3>; + #address-cells = <3>; #size-cells = <2>; - ranges; - - clocks = <&gcc GCC_USB0_AUX_CLK>, - <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, <&xo>; - clock-names = "aux", "cfg_ahb", "ref"; - - resets = <&gcc GCC_USB0_PHY_BCR>, - <&gcc GCC_USB3PHY_0_PHY_BCR>; - reset-names = "phy","common"; - status = "disabled"; - usb0_ssphy: phy@78200 { - reg = <0x0 0x00078200 0x0 0x130>, /* Tx */ - <0x0 0x00078400 0x0 0x200>, /* Rx */ - <0x0 0x00078800 0x0 0x1F8>, /* PCS */ - <0x0 0x00078600 0x0 0x044>; /* PCS misc */ - #phy-cells = <0>; - #clock-cells = <0>; - clocks = <&gcc GCC_USB0_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "gcc_usb0_pipe_clk_src"; - }; - }; - - qusb_phy_0: qusb@79000 { - compatible = "qcom,ipq6018-qusb2-phy"; - reg = <0x0 0x079000 0x0 0x180>; - #phy-cells = <0>; + phys = <&pcie_phy0>; + phy-names = "pciephy"; - clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, - <&xo>; - clock-names = "cfg_ahb", "ref"; + ranges = <0x81000000 0 0x20200000 0 0x20200000 0 0x10000>, + <0x82000000 0 0x20220000 0 0x20220000 0 0xfde0000>; - resets = <&gcc GCC_QUSB2_0_PHY_BCR>; - status = "disabled"; - }; + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi"; - usb3: usb@8af8800 { - compatible = "qcom,ipq6018-dwc3", "qcom,dwc3"; - reg = <0x0 0x8AF8800 0x0 0x400>; - #address-cells = <2>; - #size-cells = <2>; - ranges; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 78 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 79 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 83 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ - clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, - <&gcc GCC_USB0_MASTER_CLK>, - <&gcc GCC_USB0_SLEEP_CLK>, - <&gcc GCC_USB0_MOCK_UTMI_CLK>; - clock-names = "cfg_noc", - "core", - "sleep", - "mock_utmi"; + clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, + <&gcc GCC_PCIE0_AXI_M_CLK>, + <&gcc GCC_PCIE0_AXI_S_CLK>, + <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>, + <&gcc PCIE0_RCHNG_CLK>; + clock-names = "iface", + "axi_m", + "axi_s", + "axi_bridge", + "rchng"; - assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, - <&gcc GCC_USB0_MASTER_CLK>, - <&gcc GCC_USB0_MOCK_UTMI_CLK>; - assigned-clock-rates = <133330000>, - <133330000>, - <20000000>; + resets = <&gcc GCC_PCIE0_PIPE_ARES>, + <&gcc GCC_PCIE0_SLEEP_ARES>, + <&gcc GCC_PCIE0_CORE_STICKY_ARES>, + <&gcc GCC_PCIE0_AXI_MASTER_ARES>, + <&gcc GCC_PCIE0_AXI_SLAVE_ARES>, + <&gcc GCC_PCIE0_AHB_ARES>, + <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>, + <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>; + reset-names = "pipe", + "sleep", + "sticky", + "axi_m", + "axi_s", + "ahb", + "axi_m_sticky", + "axi_s_sticky"; - resets = <&gcc GCC_USB0_BCR>; status = "disabled"; - - dwc_0: usb@8a00000 { - compatible = "snps,dwc3"; - reg = <0x0 0x8A00000 0x0 0xcd00>; - interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; - phys = <&qusb_phy_0>, <&usb0_ssphy>; - phy-names = "usb2-phy", "usb3-phy"; - clocks = <&xo>; - clock-names = "ref"; - tx-fifo-resize; - snps,is-utmi-l1-suspend; - snps,hird-threshold = /bits/ 8 <0x0>; - snps,dis_u2_susphy_quirk; - snps,dis_u3_susphy_quirk; - dr_mode = "host"; - }; }; }; @@ -794,26 +814,4 @@ #interrupt-cells = <2>; }; }; - - rpm-glink { - compatible = "qcom,glink-rpm"; - interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; - qcom,rpm-msg-ram = <&rpm_msg_ram>; - mboxes = <&apcs_glb 0>; - - rpm_requests: glink-channel { - compatible = "qcom,rpm-ipq6018"; - qcom,glink-channels = "rpm_requests"; - - regulators { - compatible = "qcom,rpm-mp5496-regulators"; - - ipq6018_s2: s2 { - regulator-min-microvolt = <725000>; - regulator-max-microvolt = <1062500>; - regulator-always-on; - }; - }; - }; - }; }; diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 4e51d8e3df04..62d05d740646 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -137,7 +137,7 @@ #clock-cells = <0>; clocks = <&gcc GCC_USB1_PIPE_CLK>; clock-names = "pipe0"; - clock-output-names = "gcc_usb1_pipe_clk_src"; + clock-output-names = "usb3phy_1_cc_pipe_clk"; }; }; @@ -180,7 +180,7 @@ #clock-cells = <0>; clocks = <&gcc GCC_USB0_PIPE_CLK>; clock-names = "pipe0"; - clock-output-names = "gcc_usb0_pipe_clk_src"; + clock-output-names = "usb3phy_0_cc_pipe_clk"; }; }; @@ -197,9 +197,9 @@ status = "disabled"; }; - pcie_qmp0: phy@86000 { - compatible = "qcom,ipq8074-qmp-pcie-phy"; - reg = <0x00086000 0x1c4>; + pcie_qmp0: phy@84000 { + compatible = "qcom,ipq8074-qmp-gen3-pcie-phy"; + reg = <0x00084000 0x1bc>; #address-cells = <1>; #size-cells = <1>; ranges; @@ -213,15 +213,16 @@ "common"; status = "disabled"; - pcie_phy0: phy@86200 { - reg = <0x86200 0x16c>, - <0x86400 0x200>, - <0x86800 0x4f4>; + pcie_phy0: phy@84200 { + reg = <0x84200 0x16c>, + <0x84400 0x200>, + <0x84800 0x1f0>, + <0x84c00 0xf4>; #phy-cells = <0>; #clock-cells = <0>; clocks = <&gcc GCC_PCIE0_PIPE_CLK>; clock-names = "pipe0"; - clock-output-names = "pcie_0_pipe_clk"; + clock-output-names = "pcie20_phy0_pipe_clk"; }; }; @@ -242,19 +243,19 @@ status = "disabled"; pcie_phy1: phy@8e200 { - reg = <0x8e200 0x16c>, + reg = <0x8e200 0x130>, <0x8e400 0x200>, - <0x8e800 0x4f4>; + <0x8e800 0x1f8>; #phy-cells = <0>; #clock-cells = <0>; clocks = <&gcc GCC_PCIE1_PIPE_CLK>; clock-names = "pipe0"; - clock-output-names = "pcie_1_pipe_clk"; + clock-output-names = "pcie20_phy1_pipe_clk"; }; }; mdio: mdio@90000 { - compatible = "qcom,ipq4019-mdio"; + compatible = "qcom,ipq8074-mdio", "qcom,ipq4019-mdio"; reg = <0x00090000 0x64>; #address-cells = <1>; #size-cells = <0>; @@ -265,6 +266,13 @@ status = "disabled"; }; + qfprom: efuse@a4000 { + compatible = "qcom,ipq8074-qfprom", "qcom,qfprom"; + reg = <0x000a4000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + }; + prng: rng@e3000 { compatible = "qcom,prng-ee"; reg = <0x000e3000 0x1000>; @@ -765,6 +773,7 @@ linux,pci-domain = <1>; bus-range = <0x00 0xff>; num-lanes = <1>; + max-link-speed = <2>; #address-cells = <3>; #size-cells = <2>; @@ -772,9 +781,9 @@ phy-names = "pciephy"; ranges = <0x81000000 0 0x10200000 0x10200000 - 0 0x100000 /* downstream I/O */ - 0x82000000 0 0x10300000 0x10300000 - 0 0xd00000>; /* non-prefetchable memory */ + 0 0x10000>, /* downstream I/O */ + <0x82000000 0 0x10220000 0x10220000 + 0 0xfde0000>; /* non-prefetchable memory */ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "msi"; @@ -817,16 +826,18 @@ }; pcie0: pci@20000000 { - compatible = "qcom,pcie-ipq8074"; + compatible = "qcom,pcie-ipq8074-gen3"; reg = <0x20000000 0xf1d>, <0x20000f20 0xa8>, - <0x00080000 0x2000>, + <0x20001000 0x1000>, + <0x00080000 0x4000>, <0x20100000 0x1000>; - reg-names = "dbi", "elbi", "parf", "config"; + reg-names = "dbi", "elbi", "atu", "parf", "config"; device_type = "pci"; linux,pci-domain = <0>; bus-range = <0x00 0xff>; num-lanes = <1>; + max-link-speed = <3>; #address-cells = <3>; #size-cells = <2>; @@ -834,9 +845,9 @@ phy-names = "pciephy"; ranges = <0x81000000 0 0x20200000 0x20200000 - 0 0x100000 /* downstream I/O */ - 0x82000000 0 0x20300000 0x20300000 - 0 0xd00000>; /* non-prefetchable memory */ + 0 0x10000>, /* downstream I/O */ + <0x82000000 0 0x20220000 0x20220000 + 0 0xfde0000>; /* non-prefetchable memory */ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "msi"; @@ -854,28 +865,30 @@ clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, <&gcc GCC_PCIE0_AXI_M_CLK>, <&gcc GCC_PCIE0_AXI_S_CLK>, - <&gcc GCC_PCIE0_AHB_CLK>, - <&gcc GCC_PCIE0_AUX_CLK>; - + <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>, + <&gcc GCC_PCIE0_RCHNG_CLK>; clock-names = "iface", "axi_m", "axi_s", - "ahb", - "aux"; + "axi_bridge", + "rchng"; + resets = <&gcc GCC_PCIE0_PIPE_ARES>, <&gcc GCC_PCIE0_SLEEP_ARES>, <&gcc GCC_PCIE0_CORE_STICKY_ARES>, <&gcc GCC_PCIE0_AXI_MASTER_ARES>, <&gcc GCC_PCIE0_AXI_SLAVE_ARES>, <&gcc GCC_PCIE0_AHB_ARES>, - <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>; + <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>, + <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>; reset-names = "pipe", "sleep", "sticky", "axi_m", "axi_s", "ahb", - "axi_m_sticky"; + "axi_m_sticky", + "axi_s_sticky"; status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts b/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts new file mode 100644 index 000000000000..ed3fa7b3575b --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts @@ -0,0 +1,295 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include "msm8916-pm8916.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/* + * NOTE: The original firmware from Acer can only boot 32-bit kernels. + * To boot this device tree using arm64 it is necessary to flash 64-bit + * TZ/HYP firmware (e.g. taken from the DragonBoard 410c). + * See https://wiki.postmarketos.org/wiki/Acer_Iconia_Talk_S_(acer-a1-724) + * for suggested installation instructions. + */ + +/ { + model = "Acer Iconia Talk S A1-724"; + compatible = "acer,a1-724", "qcom,msm8916"; + chassis-type = "tablet"; + + aliases { + serial0 = &blsp1_uart2; + }; + + chosen { + stdout-path = "serial0"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_default>; + + label = "GPIO Buttons"; + + button-volume-up { + label = "Volume Up"; + gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + }; + }; + + usb_id: usb-id { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&msmgpio 110 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_id_default>; + }; +}; + +&blsp_i2c2 { + status = "okay"; + + accelerometer@10 { + compatible = "bosch,bmc150_accel"; + reg = <0x10>; + interrupt-parent = <&msmgpio>; + interrupts = <115 IRQ_TYPE_EDGE_RISING>; + + vdd-supply = <&pm8916_l17>; + vddio-supply = <&pm8916_l6>; + + pinctrl-names = "default"; + pinctrl-0 = <&accel_int_default>; + + mount-matrix = "0", "-1", "0", + "-1", "0", "0", + "0", "0", "1"; + }; + + magnetometer@12 { + compatible = "bosch,bmc150_magn"; + reg = <0x12>; + + vdd-supply = <&pm8916_l17>; + vddio-supply = <&pm8916_l6>; + }; +}; + +&blsp_i2c5 { + status = "okay"; + + touchscreen@38 { + /* Actually ft5446 */ + compatible = "edt,edt-ft5406"; + reg = <0x38>; + + interrupt-parent = <&msmgpio>; + interrupts = <13 IRQ_TYPE_LEVEL_LOW>; + + reset-gpios = <&msmgpio 12 GPIO_ACTIVE_LOW>; + + vcc-supply = <&pm8916_l16>; + iovcc-supply = <&pm8916_l6>; + + touchscreen-size-x = <720>; + touchscreen-size-y = <1280>; + + pinctrl-names = "default"; + pinctrl-0 = <&touchscreen_default>; + }; +}; + +&blsp1_uart2 { + status = "okay"; +}; + +&pm8916_resin { + linux,code = <KEY_VOLUMEDOWN>; + status = "okay"; +}; + +&pm8916_vib { + status = "okay"; +}; + +&pronto { + status = "okay"; +}; + +&sdhc_1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; + pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; + + status = "okay"; +}; + +&sdhc_2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; + + cd-gpios = <&msmgpio 38 GPIO_ACTIVE_HIGH>; + + status = "okay"; +}; + +&usb { + extcon = <&usb_id>, <&usb_id>; + status = "okay"; +}; + +&usb_hs_phy { + extcon = <&usb_id>; +}; + +&smd_rpm_regulators { + vdd_l1_l2_l3-supply = <&pm8916_s3>; + vdd_l4_l5_l6-supply = <&pm8916_s4>; + vdd_l7-supply = <&pm8916_s4>; + + s3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1300000>; + }; + + s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2100000>; + }; + + l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + l4 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l8 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2900000>; + }; + + l9 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + l10 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2800000>; + }; + + l11 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + regulator-system-load = <200000>; + regulator-allow-set-load; + }; + + l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + l13 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + }; + + l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + l16 { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + }; + + l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + l18 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; +}; + +&msmgpio { + accel_int_default: accel-int-default-state { + pins = "gpio115"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + + gpio_keys_default: gpio-keys-default-state { + pins = "gpio107"; + function = "gpio"; + + drive-strength = <2>; + bias-pull-up; + }; + + touchscreen_default: touchscreen-default-state { + reset-pins { + pins = "gpio12"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + touchscreen-pins { + pins = "gpio13"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + usb_id_default: usb-id-default-state { + pins = "gpio110"; + function = "gpio"; + + drive-strength = <8>; + bias-pull-up; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts b/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts new file mode 100644 index 000000000000..a0e520edde02 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts @@ -0,0 +1,299 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include "msm8916-pm8916.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> + +/ { + model = "GPLUS FL8005A"; + compatible = "gplus,fl8005a", "qcom,msm8916"; + chassis-type = "tablet"; + + aliases { + serial0 = &blsp1_uart2; + }; + + chosen { + stdout-path = "serial0"; + }; + + flash-led-controller { + /* Actually qcom,leds-gpio-flash */ + compatible = "sgmicro,sgm3140"; + enable-gpios = <&msmgpio 31 GPIO_ACTIVE_HIGH>; + flash-gpios = <&msmgpio 32 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&camera_flash_default>; + pinctrl-names = "default"; + + flash_led: led { + function = LED_FUNCTION_FLASH; + color = <LED_COLOR_ID_WHITE>; + flash-max-timeout-us = <250000>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&gpio_keys_default>; + pinctrl-names = "default"; + + button-volume-up { + label = "Volume Up"; + gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + pinctrl-0 = <&gpio_leds_default>; + pinctrl-names = "default"; + + led-red { + function = LED_FUNCTION_CHARGING; + color = <LED_COLOR_ID_RED>; + gpios = <&msmgpio 117 GPIO_ACTIVE_HIGH>; + retain-state-suspended; + }; + + led-green { + function = LED_FUNCTION_CHARGING; + color = <LED_COLOR_ID_GREEN>; + gpios = <&msmgpio 118 GPIO_ACTIVE_HIGH>; + retain-state-suspended; + }; + }; + + usb_id: usb-id { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&msmgpio 110 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&usb_id_default>; + pinctrl-names = "default"; + }; +}; + +&blsp_i2c5 { + status = "okay"; + + touchscreen@38 { + /* Actually ft5402 */ + compatible = "edt,edt-ft5406"; + reg = <0x38>; + + interrupt-parent = <&msmgpio>; + interrupts = <13 IRQ_TYPE_EDGE_FALLING>; + + reset-gpios = <&msmgpio 12 GPIO_ACTIVE_LOW>; + + vcc-supply = <&pm8916_l17>; + iovcc-supply = <&pm8916_l6>; + + touchscreen-size-x = <800>; + touchscreen-size-y = <500>; + touchscreen-inverted-x; + touchscreen-swapped-x-y; + + pinctrl-0 = <&touchscreen_default>; + pinctrl-names = "default"; + }; +}; + +&blsp1_uart2 { + status = "okay"; +}; + +&pm8916_resin { + linux,code = <KEY_VOLUMEDOWN>; + status = "okay"; +}; + +&pm8916_vib { + status = "okay"; +}; + +&pronto { + status = "okay"; +}; + +&sdhc_1 { + pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; + pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; + pinctrl-names = "default", "sleep"; + + status = "okay"; +}; + +&sdhc_2 { + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; + pinctrl-names = "default", "sleep"; + + cd-gpios = <&msmgpio 38 GPIO_ACTIVE_LOW>; + + status = "okay"; +}; + +&usb { + extcon = <&usb_id>, <&usb_id>; + status = "okay"; +}; + +&usb_hs_phy { + extcon = <&usb_id>; +}; + +&smd_rpm_regulators { + vdd_l1_l2_l3-supply = <&pm8916_s3>; + vdd_l4_l5_l6-supply = <&pm8916_s4>; + vdd_l7-supply = <&pm8916_s4>; + + s3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1300000>; + }; + + s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2100000>; + }; + + l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + l4 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l8 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2900000>; + }; + + l9 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + l10 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2800000>; + }; + + l11 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + regulator-system-load = <200000>; + regulator-allow-set-load; + }; + + l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + l13 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + }; + + l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + l16 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + l18 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; +}; + +&msmgpio { + camera_flash_default: camera-flash-default-state { + pins = "gpio31", "gpio32"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + gpio_keys_default: gpio-keys-default-state { + pins = "gpio107"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + gpio_leds_default: gpio-led-default-state { + pins = "gpio117", "gpio118"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + touchscreen_default: touchscreen-default-state { + reset-pins { + pins = "gpio12"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + touchscreen-pins { + pins = "gpio13"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + usb_id_default: usb-id-default-state { + pins = "gpio110"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi index d600916a0e55..a2ed7bdbf528 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi @@ -434,7 +434,7 @@ bias-pull-down; }; - motor_en_default: motor-en-default-stae { + motor_en_default: motor-en-default-state { pins = "gpio76"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-grandmax.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-grandmax.dts index a3d572d851ef..4cbd68b89448 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-grandmax.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-grandmax.dts @@ -29,8 +29,12 @@ gpio-leds { compatible = "gpio-leds"; - keyled { + led-keyled { + function = LED_FUNCTION_KBD_BACKLIGHT; + color = <LED_COLOR_ID_WHITE>; + gpios = <&msmgpio 60 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; pinctrl-0 = <&gpio_leds_default>; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi new file mode 100644 index 000000000000..d920b7247d82 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi @@ -0,0 +1,296 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include "msm8916-pm8916.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + aliases { + serial0 = &blsp1_uart2; + }; + + chosen { + stdout-path = "serial0"; + }; + + reserved-memory { + /* Additional memory used by Samsung firmware modifications */ + tz-apps@85500000 { + reg = <0x0 0x85500000 0x0 0xb00000>; + no-map; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&gpio_keys_default>; + pinctrl-names = "default"; + + label = "GPIO Buttons"; + + volume-up-button { + label = "Volume Up"; + gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + }; + + home-button { + label = "Home"; + gpios = <&msmgpio 109 GPIO_ACTIVE_LOW>; + linux,code = <KEY_HOMEPAGE>; + }; + }; + + gpio-hall-sensor { + compatible = "gpio-keys"; + + pinctrl-0 = <&gpio_hall_sensor_default>; + pinctrl-names = "default"; + + label = "GPIO Hall Effect Sensor"; + + hall-sensor-switch { + label = "Hall Effect Sensor"; + gpios = <&msmgpio 52 GPIO_ACTIVE_LOW>; + linux,input-type = <EV_SW>; + linux,code = <SW_LID>; + linux,can-disable; + }; + }; +}; + +&blsp_i2c4 { + status = "okay"; + + fuelgauge@36 { + compatible = "maxim,max77849-battery"; + reg = <0x36>; + + maxim,rsns-microohm = <10000>; + maxim,over-heat-temp = <600>; + maxim,over-volt = <4400>; + + interrupt-parent = <&msmgpio>; + interrupts = <121 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-0 = <&fuelgauge_int_default>; + pinctrl-names = "default"; + }; +}; + +&blsp_i2c2 { + status = "okay"; + + light-sensor@10 { + compatible = "capella,cm3323"; + reg = <0x10>; + }; + + accelerometer@1d { + compatible = "st,lis2hh12"; + reg = <0x1d>; + + vdd-supply = <&pm8916_l17>; + vddio-supply = <&pm8916_l5>; + + interrupt-parent = <&msmgpio>; + interrupts = <115 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "INT1"; + + st,drdy-int-pin = <1>; + mount-matrix = "0", "1", "0", + "-1", "0", "0", + "0", "0", "1"; + + pinctrl-0 = <&accel_int_default>; + pinctrl-names = "default"; + }; +}; + +&blsp1_uart2 { + status = "okay"; +}; + +&pm8916_resin { + linux,code = <KEY_VOLUMEDOWN>; + status = "okay"; +}; + +/* FIXME: Replace with MAX77849 MUIC when driver is available */ +&pm8916_usbin { + status = "okay"; +}; + +&pronto { + status = "okay"; + + iris { + compatible = "qcom,wcn3660b"; + }; +}; + +&sdhc_1 { + pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; + pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; + pinctrl-names = "default", "sleep"; + + status = "okay"; +}; + +&sdhc_2 { + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + pinctrl-names = "default", "sleep"; + + cd-gpios = <&msmgpio 38 GPIO_ACTIVE_LOW>; + + status = "okay"; +}; + +&usb { + dr_mode = "peripheral"; + extcon = <&pm8916_usbin>; + + status = "okay"; +}; + +&usb_hs_phy { + extcon = <&pm8916_usbin>; +}; + +&smd_rpm_regulators { + vdd_l1_l2_l3-supply = <&pm8916_s3>; + vdd_l4_l5_l6-supply = <&pm8916_s4>; + vdd_l7-supply = <&pm8916_s4>; + + s3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1300000>; + }; + + s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2100000>; + }; + + l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + l4 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l8 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2900000>; + }; + + l9 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + l10 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2800000>; + }; + + l11 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + regulator-system-load = <200000>; + regulator-allow-set-load; + }; + + l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + l13 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + }; + + l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + l16 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + l18 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; +}; + +&msmgpio { + accel_int_default: accel-int-default-state { + pins = "gpio115"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + fuelgauge_int_default: fuelgauge-int-default-state { + pins = "gpio121"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + gpio_keys_default: gpio-keys-default-state { + pins = "gpio107", "gpio109"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + gpio_hall_sensor_default: gpio-hall-sensor-default-state { + pins = "gpio52"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-gt510.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-gt510.dts new file mode 100644 index 000000000000..607a5dc8a534 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-gt510.dts @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include "msm8916-samsung-gt5-common.dtsi" + +/ { + model = "Samsung Galaxy Tab A 9.7 (2015)"; + compatible = "samsung,gt510", "qcom,msm8916"; + chassis-type = "tablet"; + + clk_pwm: pwm { + compatible = "clk-pwm"; + #pwm-cells = <2>; + + clocks = <&gcc GCC_GP2_CLK>; + + pinctrl-0 = <&motor_pwm_default>; + pinctrl-names = "default"; + }; + + reg_motor_vdd: regulator-motor-vdd { + compatible = "regulator-fixed"; + regulator-name = "motor_vdd"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + gpio = <&msmgpio 76 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&motor_en_default>; + pinctrl-names = "default"; + }; + + reg_tsp_1p8v: regulator-tsp-1p8v { + compatible = "regulator-fixed"; + regulator-name = "tsp_1p8v"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&msmgpio 73 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&tsp_en_default>; + pinctrl-names = "default"; + }; + + reg_tsp_3p3v: regulator-tsp-3p3v { + compatible = "regulator-fixed"; + regulator-name = "tsp_3p3v"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&msmgpio 73 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vibrator { + compatible = "pwm-vibrator"; + + pwms = <&clk_pwm 0 100000>; + pwm-names = "enable"; + + vcc-supply = <®_motor_vdd>; + }; +}; + +&blsp_i2c5 { + status = "okay"; + + touchscreen@4a { + compatible = "atmel,maxtouch"; + reg = <0x4a>; + interrupt-parent = <&msmgpio>; + interrupts = <13 IRQ_TYPE_LEVEL_LOW>; + + vdd-supply = <®_tsp_1p8v>; + vdda-supply = <®_tsp_3p3v>; + + reset-gpios = <&msmgpio 114 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&tsp_int_rst_default>; + pinctrl-names = "default"; + }; +}; + +&msmgpio { + motor_en_default: motor-en-default-state { + pins = "gpio76"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + motor_pwm_default: motor-pwm-default-state { + pins = "gpio50"; + function = "gcc_gp2_clk_a"; + }; + + tsp_en_default: tsp-en-default-state { + pins = "gpio73"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + tsp_int_rst_default: tsp-int-rst-default-state { + pins = "gpio13", "gpio114"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-gt58.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-gt58.dts new file mode 100644 index 000000000000..5d6f8383306b --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-gt58.dts @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include "msm8916-samsung-gt5-common.dtsi" + +/ { + model = "Samsung Galaxy Tab A 8.0 (2015)"; + compatible = "samsung,gt58", "qcom,msm8916"; + chassis-type = "tablet"; + + reg_vdd_tsp: regulator-vdd-tsp { + compatible = "regulator-fixed"; + regulator-name = "vdd_tsp"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&msmgpio 73 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <®_tsp_en_default>; + pinctrl-names = "default"; + }; + + vibrator { + compatible = "gpio-vibrator"; + enable-gpios = <&msmgpio 76 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&vibrator_en_default>; + pinctrl-names = "default"; + }; +}; + +&blsp_i2c5 { + status = "okay"; + + touchscreen@20 { + compatible = "zinitix,bt532"; + reg = <0x20>; + interrupt-parent = <&msmgpio>; + interrupts = <13 IRQ_TYPE_EDGE_FALLING>; + + touchscreen-size-x = <768>; + touchscreen-size-y = <1024>; + + vcca-supply = <®_vdd_tsp>; + vdd-supply = <&pm8916_l6>; + + pinctrl-0 = <&tsp_int_default>; + pinctrl-names = "default"; + }; +}; + +&msmgpio { + reg_tsp_en_default: reg-tsp-en-default-state { + pins = "gpio73"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + tsp_int_default: tsp-int-default-state { + pins = "gpio13"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + vibrator_en_default: vibrator-en-default-state { + pins = "gpio76"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi new file mode 100644 index 000000000000..f3b81b6f0a2f --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi @@ -0,0 +1,262 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include "msm8916-pm8916.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + aliases { + serial0 = &blsp1_uart2; + }; + + chosen { + stdout-path = "serial0"; + }; + + reserved-memory { + /* Additional memory used by Samsung firmware modifications */ + tz-apps@85500000 { + reg = <0x0 0x85500000 0x0 0xb00000>; + no-map; + }; + }; + + gpio_hall_sensor: gpio-hall-sensor { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_hall_sensor_default>; + + label = "GPIO Hall Effect Sensor"; + + event-hall-sensor { + label = "Hall Effect Sensor"; + gpios = <&msmgpio 52 GPIO_ACTIVE_LOW>; + linux,input-type = <EV_SW>; + linux,code = <SW_LID>; + linux,can-disable; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_default>; + + label = "GPIO Buttons"; + + button-volume-up { + label = "Volume Up"; + gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + }; + + button-home { + label = "Home Key"; + gpios = <&msmgpio 109 GPIO_ACTIVE_LOW>; + linux,code = <KEY_HOMEPAGE>; + }; + }; + + i2c_muic: i2c-muic { + compatible = "i2c-gpio"; + sda-gpios = <&msmgpio 105 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&msmgpio 106 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + + pinctrl-names = "default"; + pinctrl-0 = <&muic_i2c_default>; + + #address-cells = <1>; + #size-cells = <0>; + + muic: extcon@25 { + compatible = "siliconmitus,sm5703-muic"; + reg = <0x25>; + + interrupt-parent = <&msmgpio>; + interrupts = <12 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-names = "default"; + pinctrl-0 = <&muic_int_default>; + }; + }; +}; + +&blsp1_uart2 { + status = "okay"; +}; + +&pm8916_resin { + status = "okay"; + linux,code = <KEY_VOLUMEDOWN>; +}; + +&pronto { + status = "okay"; +}; + +&sdhc_1 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; + pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; +}; + +&sdhc_2 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + + cd-gpios = <&msmgpio 38 GPIO_ACTIVE_LOW>; +}; + +&usb { + extcon = <&muic>, <&muic>; + status = "okay"; +}; + +&usb_hs_phy { + extcon = <&muic>; +}; + +&smd_rpm_regulators { + vdd_l1_l2_l3-supply = <&pm8916_s3>; + vdd_l4_l5_l6-supply = <&pm8916_s4>; + vdd_l7-supply = <&pm8916_s4>; + + s3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1300000>; + }; + + s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2100000>; + }; + + l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + l4 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l8 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2900000>; + }; + + l9 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + l10 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2800000>; + }; + + l11 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + regulator-allow-set-load; + regulator-system-load = <200000>; + }; + + l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + l13 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + }; + + l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + l16 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + l17 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + l18 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; +}; + +&msmgpio { + gpio_hall_sensor_default: gpio-hall-sensor-default-state { + pins = "gpio52"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + + gpio_keys_default: gpio-keys-default-state { + pins = "gpio107", "gpio109"; + function = "gpio"; + + drive-strength = <2>; + bias-pull-up; + }; + + muic_i2c_default: muic-i2c-default-state { + pins = "gpio105", "gpio106"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + + muic_int_default: muic-int-default-state { + pins = "gpio12"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-j5.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-j5.dts index 7ac49a021563..0a32d33e9778 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-j5.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-j5.dts @@ -2,208 +2,14 @@ /dts-v1/; -#include "msm8916-pm8916.dtsi" -#include <dt-bindings/gpio/gpio.h> +#include "msm8916-samsung-j5-common.dtsi" / { model = "Samsung Galaxy J5 (2015)"; compatible = "samsung,j5", "qcom,msm8916"; chassis-type = "handset"; - - aliases { - serial0 = &blsp1_uart2; - }; - - chosen { - stdout-path = "serial0"; - }; - - reserved-memory { - /* Additional memory used by Samsung firmware modifications */ - tz-apps@85500000 { - reg = <0x0 0x85500000 0x0 0xb00000>; - no-map; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys_default>; - - label = "GPIO Buttons"; - - button-volume-up { - label = "Volume Up"; - gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>; - linux,code = <KEY_VOLUMEUP>; - }; - - button-home { - label = "Home Key"; - gpios = <&msmgpio 109 GPIO_ACTIVE_LOW>; - linux,code = <KEY_HOMEPAGE>; - }; - }; -}; - -&blsp1_uart2 { - status = "okay"; -}; - -&pm8916_resin { - status = "okay"; - linux,code = <KEY_VOLUMEDOWN>; -}; - -/* FIXME: Replace with SM5703 MUIC when driver is available */ -&pm8916_usbin { - status = "okay"; -}; - -&pronto { - status = "okay"; -}; - -&sdhc_1 { - status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; - pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; -}; - -&sdhc_2 { - status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; - pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; - - cd-gpios = <&msmgpio 38 GPIO_ACTIVE_LOW>; -}; - -&usb { - status = "okay"; - dr_mode = "peripheral"; - extcon = <&pm8916_usbin>; }; &usb_hs_phy { - extcon = <&pm8916_usbin>; qcom,init-seq = /bits/ 8 <0x1 0x19 0x2 0x0b>; }; - -&smd_rpm_regulators { - vdd_l1_l2_l3-supply = <&pm8916_s3>; - vdd_l4_l5_l6-supply = <&pm8916_s4>; - vdd_l7-supply = <&pm8916_s4>; - - s3 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1300000>; - }; - - s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2100000>; - }; - - l1 { - regulator-min-microvolt = <1225000>; - regulator-max-microvolt = <1225000>; - }; - - l2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - l4 { - regulator-min-microvolt = <2050000>; - regulator-max-microvolt = <2050000>; - }; - - l5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l7 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - l8 { - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2900000>; - }; - - l9 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - l10 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2800000>; - }; - - l11 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - regulator-allow-set-load; - regulator-system-load = <200000>; - }; - - l12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - }; - - l13 { - regulator-min-microvolt = <3075000>; - regulator-max-microvolt = <3075000>; - }; - - l14 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l15 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l16 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - l17 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - l18 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - }; -}; - -&msmgpio { - gpio_keys_default: gpio-keys-default-state { - pins = "gpio107", "gpio109"; - function = "gpio"; - - drive-strength = <2>; - bias-pull-up; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-j5x.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-j5x.dts new file mode 100644 index 000000000000..7e1326cc13c5 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-j5x.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include "msm8916-samsung-j5-common.dtsi" + +/ { + model = "Samsung Galaxy J5 (2016)"; + compatible = "samsung,j5x", "qcom,msm8916"; + chassis-type = "handset"; +}; + +&muic { + interrupts = <121 IRQ_TYPE_EDGE_FALLING>; +}; + +&muic_int_default { + pins = "gpio121"; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8916-thwc-uf896.dts b/arch/arm64/boot/dts/qcom/msm8916-thwc-uf896.dts new file mode 100644 index 000000000000..c492db856190 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8916-thwc-uf896.dts @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include "msm8916-ufi.dtsi" + +/ { + model = "uf896 4G Modem Stick"; + compatible = "thwc,uf896", "qcom,msm8916"; +}; + +&button_restart { + gpios = <&msmgpio 35 GPIO_ACTIVE_LOW>; +}; + +&led_r { + gpios = <&msmgpio 82 GPIO_ACTIVE_HIGH>; +}; + +&led_g { + gpios = <&msmgpio 83 GPIO_ACTIVE_HIGH>; +}; + +&led_b { + gpios = <&msmgpio 81 GPIO_ACTIVE_HIGH>; +}; + +&button_default { + pins = "gpio35"; + bias-pull-up; +}; + +&gpio_leds_default { + pins = "gpio81", "gpio82", "gpio83"; +}; + +&sim_ctrl_default { + pins = "gpio1", "gpio2"; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8916-thwc-ufi001c.dts b/arch/arm64/boot/dts/qcom/msm8916-thwc-ufi001c.dts new file mode 100644 index 000000000000..700cf81cbf8c --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8916-thwc-ufi001c.dts @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include "msm8916-ufi.dtsi" + +/ { + model = "ufi-001c/ufi-001b 4G Modem Stick"; + compatible = "thwc,ufi001c", "qcom,msm8916"; +}; + +&button_restart { + gpios = <&msmgpio 37 GPIO_ACTIVE_HIGH>; +}; + +&led_r { + gpios = <&msmgpio 22 GPIO_ACTIVE_HIGH>; +}; + +&led_g { + gpios = <&msmgpio 21 GPIO_ACTIVE_HIGH>; +}; + +&led_b { + gpios = <&msmgpio 20 GPIO_ACTIVE_HIGH>; +}; + +&button_default { + pins = "gpio37"; + bias-pull-down; +}; + +&gpio_leds_default { + pins = "gpio20", "gpio21", "gpio22"; +}; + +&sim_ctrl_default { + pins = "gpio1", "gpio2"; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi b/arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi new file mode 100644 index 000000000000..790a9696da9d --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi @@ -0,0 +1,250 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include "msm8916-pm8916.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> + +/ { + chassis-type = "embedded"; + + aliases { + serial0 = &blsp1_uart2; + }; + + chosen { + stdout-path = "serial0"; + }; + + reserved-memory { + mpss_mem: mpss@86800000 { + reg = <0x0 0x86800000 0x0 0x5500000>; + no-map; + }; + + gps_mem: gps@8bd00000 { + reg = <0x0 0x8bd00000 0x0 0x200000>; + no-map; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&button_default>; + pinctrl-names = "default"; + + label = "GPIO Buttons"; + + /* GPIO is board-specific */ + button_restart: button-restart { + label = "Restart"; + linux,code = <KEY_RESTART>; + }; + }; + + leds { + compatible = "gpio-leds"; + + pinctrl-0 = <&gpio_leds_default>; + pinctrl-names = "default"; + + /* + * GPIOs are board-specific. + * Functions and default-states defined here are fallbacks. + * Feel free to override them if your board is different. + */ + led_r: led-r { + color = <LED_COLOR_ID_RED>; + default-state = "on"; + function = LED_FUNCTION_POWER; + }; + + led_g: led-g { + color = <LED_COLOR_ID_GREEN>; + default-state = "off"; + function = LED_FUNCTION_WLAN; + }; + + led_b: led-b { + color = <LED_COLOR_ID_BLUE>; + default-state = "off"; + function = LED_FUNCTION_WAN; + }; + }; +}; + +&bam_dmux { + status = "okay"; +}; + +&bam_dmux_dma { + status = "okay"; +}; + +&blsp1_uart2 { + status = "okay"; +}; + +/* Remove &dsi_phy0 from clocks to make sure that gcc probes with display disabled */ +&gcc { + clocks = <&xo_board>, <&sleep_clk>, <0>, <0>, <0>, <0>, <0>; +}; + +&mpss { + pinctrl-0 = <&sim_ctrl_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pm8916_usbin { + status = "okay"; +}; + +&pronto { + status = "okay"; +}; + +&sdhc_1 { + pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; + pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; + pinctrl-names = "default", "sleep"; + + status = "okay"; +}; + +&usb { + extcon = <&pm8916_usbin>; + dr_mode = "peripheral"; + + status = "okay"; +}; + +&usb_hs_phy { + extcon = <&pm8916_usbin>; +}; + +&smd_rpm_regulators { + vdd_l1_l2_l3-supply = <&pm8916_s3>; + vdd_l4_l5_l6-supply = <&pm8916_s4>; + vdd_l7-supply = <&pm8916_s4>; + + s3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1300000>; + }; + + s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2100000>; + }; + + l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + l4 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l8 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2900000>; + }; + + l9 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + l10 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2800000>; + }; + + l11 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + regulator-system-load = <200000>; + regulator-allow-set-load; + }; + + l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + l13 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + }; + + l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + l16 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + l18 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; +}; + +&msmgpio { + /* pins are board-specific */ + button_default: button-default-state { + function = "gpio"; + drive-strength = <2>; + }; + + gpio_leds_default: gpio-leds-default-state { + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + sim_ctrl_default: sim-ctrl-default-state { + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 2ca8e977fc2a..0733c2f4f379 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -442,11 +442,70 @@ reg = <0x0005c000 0x1000>; #address-cells = <1>; #size-cells = <1>; - tsens_caldata: caldata@d0 { - reg = <0xd0 0x8>; + + tsens_base1: base1@d0 { + reg = <0xd0 0x1>; + bits = <0 7>; + }; + + tsens_s0_p1: s0-p1@d0 { + reg = <0xd0 0x2>; + bits = <7 5>; + }; + + tsens_s0_p2: s0-p2@d1 { + reg = <0xd1 0x2>; + bits = <4 5>; }; - tsens_calsel: calsel@ec { - reg = <0xec 0x4>; + + tsens_s1_p1: s1-p1@d2 { + reg = <0xd2 0x1>; + bits = <1 5>; + }; + tsens_s1_p2: s1-p2@d2 { + reg = <0xd2 0x2>; + bits = <6 5>; + }; + tsens_s2_p1: s2-p1@d3 { + reg = <0xd3 0x1>; + bits = <3 5>; + }; + + tsens_s2_p2: s2-p2@d4 { + reg = <0xd4 0x1>; + bits = <0 5>; + }; + + // no tsens with hw_id 3 + + tsens_s4_p1: s4-p1@d4 { + reg = <0xd4 0x2>; + bits = <5 5>; + }; + + tsens_s4_p2: s4-p2@d5 { + reg = <0xd5 0x1>; + bits = <2 5>; + }; + + tsens_s5_p1: s5-p1@d5 { + reg = <0xd5 0x2>; + bits = <7 5>; + }; + + tsens_s5_p2: s5-p2@d6 { + reg = <0xd6 0x2>; + bits = <4 5>; + }; + + tsens_base2: base2@d7 { + reg = <0xd7 0x1>; + bits = <1 7>; + }; + + tsens_mode: mode@ec { + reg = <0xef 0x1>; + bits = <5 3>; }; }; @@ -473,8 +532,22 @@ compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1"; reg = <0x004a9000 0x1000>, /* TM */ <0x004a8000 0x1000>; /* SROT */ - nvmem-cells = <&tsens_caldata>, <&tsens_calsel>; - nvmem-cell-names = "calib", "calib_sel"; + + // no hw_id 3 + nvmem-cells = <&tsens_mode>, + <&tsens_base1>, <&tsens_base2>, + <&tsens_s0_p1>, <&tsens_s0_p2>, + <&tsens_s1_p1>, <&tsens_s1_p2>, + <&tsens_s2_p1>, <&tsens_s2_p2>, + <&tsens_s4_p1>, <&tsens_s4_p2>, + <&tsens_s5_p1>, <&tsens_s5_p2>; + nvmem-cell-names = "mode", + "base1", "base2", + "s0_p1", "s0_p2", + "s1_p1", "s1_p2", + "s2_p1", "s2_p2", + "s4_p1", "s4_p2", + "s5_p1", "s5_p2"; #qcom,sensors = <5>; interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "uplow"; @@ -963,7 +1036,7 @@ reg = <0x01937000 0x30000>; }; - mdss: mdss@1a00000 { + mdss: display-subsystem@1a00000 { status = "disabled"; compatible = "qcom,mdss"; reg = <0x01a00000 0x1000>, @@ -988,8 +1061,8 @@ #size-cells = <1>; ranges; - mdp: mdp@1a01000 { - compatible = "qcom,mdp5"; + mdp: display-controller@1a01000 { + compatible = "qcom,msm8916-mdp5", "qcom,mdp5"; reg = <0x01a01000 0x89000>; reg-names = "mdp_phys"; @@ -1021,7 +1094,8 @@ }; dsi0: dsi@1a98000 { - compatible = "qcom,mdss-dsi-ctrl"; + compatible = "qcom,msm8916-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; reg = <0x01a98000 0x25c>; reg-names = "dsi_ctrl"; @@ -1167,7 +1241,7 @@ }; cci: cci@1b0c000 { - compatible = "qcom,msm8916-cci"; + compatible = "qcom,msm8916-cci", "qcom,msm8226-cci"; #address-cells = <1>; #size-cells = <0>; reg = <0x01b0c000 0x1000>; @@ -1521,7 +1595,6 @@ clock-names = "bam_clk"; #dma-cells = <1>; qcom,ee = <0>; - status = "disabled"; }; blsp1_uart1: serial@78af000 { @@ -1559,6 +1632,8 @@ clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; + dmas = <&blsp_dma 4>, <&blsp_dma 5>; + dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c1_default>; pinctrl-1 = <&i2c1_sleep>; @@ -1591,6 +1666,8 @@ clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; + dmas = <&blsp_dma 6>, <&blsp_dma 7>; + dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c2_default>; pinctrl-1 = <&i2c2_sleep>; @@ -1623,6 +1700,8 @@ clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; + dmas = <&blsp_dma 8>, <&blsp_dma 9>; + dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c3_default>; pinctrl-1 = <&i2c3_sleep>; @@ -1655,6 +1734,8 @@ clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; + dmas = <&blsp_dma 10>, <&blsp_dma 11>; + dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c4_default>; pinctrl-1 = <&i2c4_sleep>; @@ -1687,6 +1768,8 @@ clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; + dmas = <&blsp_dma 12>, <&blsp_dma 13>; + dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c5_default>; pinctrl-1 = <&i2c5_sleep>; @@ -1719,6 +1802,8 @@ clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; + dmas = <&blsp_dma 14>, <&blsp_dma 15>; + dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c6_default>; pinctrl-1 = <&i2c6_sleep>; @@ -1998,7 +2083,7 @@ hysteresis = <2000>; type = "passive"; }; - cpu0_1_crit: cpu_crit { + cpu0_1_crit: cpu-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -2028,7 +2113,7 @@ hysteresis = <2000>; type = "passive"; }; - cpu2_3_crit: cpu_crit { + cpu2_3_crit: cpu-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -2058,7 +2143,7 @@ hysteresis = <2000>; type = "passive"; }; - gpu_crit: gpu_crit { + gpu_crit: gpu-crit { temperature = <95000>; hysteresis = <2000>; type = "critical"; diff --git a/arch/arm64/boot/dts/qcom/msm8953-motorola-potter.dts b/arch/arm64/boot/dts/qcom/msm8953-motorola-potter.dts new file mode 100644 index 000000000000..711d84dad9d7 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8953-motorola-potter.dts @@ -0,0 +1,305 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Sireesh Kodali + */ +/dts-v1/; + +#include "msm8953.dtsi" +#include "pm8953.dtsi" +#include "pmi8950.dtsi" + +/delete-node/ &cont_splash_mem; +/delete-node/ &qseecom_mem; + +/ { + model = "Motorola G5 Plus"; + compatible = "motorola,potter", "qcom,msm8953"; + chassis-type = "handset"; + qcom,msm-id = <293 0>; + qcom,board-id = <0x46 0x83a0>; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + framebuffer@90001000 { + compatible = "simple-framebuffer"; + reg = <0 0x90001000 0 (2220 * 1920 * 3)>; + + width = <1080>; + height = <1920>; + stride = <(1080 * 3)>; + format = "r8g8b8"; + + power-domains = <&gcc MDSS_GDSC>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>, + <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_BYTE0_CLK>, + <&gcc GCC_MDSS_PCLK0_CLK>, + <&gcc GCC_MDSS_ESC0_CLK>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_key_default>; + + key-volume-up { + label = "Volume Up"; + gpios = <&tlmm 85 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + }; + }; + + reserved-memory { + qseecom_mem: qseecom@84300000 { + reg = <0x0 0x84300000 0x0 0x2000000>; + no-map; + }; + + cont_splash_mem: cont-splash@90001000 { + reg = <0x0 0x90001000 0x0 (1080 * 1920 * 3)>; + no-map; + }; + + reserved@aefd2000 { + reg = <0x0 0xaefd2000 0x0 0x2e000>; + no-map; + }; + + reserved@eefe4000 { + reg = <0x0 0xeefe4000 0x0 0x1c000>; + no-map; + }; + + ramoops@ef000000 { + compatible = "ramoops"; + reg = <0x0 0xef000000 0x0 0x80000>; + console-size = <0x40000>; + ftrace-size = <0>; + record-size = <0x3f800>; + pmsg-size = <0x800>; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-always-on; + regulator-boot-on; + }; +}; + +&hsusb_phy { + vdd-supply = <&pm8953_l3>; + vdda-pll-supply = <&pm8953_l7>; + vdda-phy-dpdm-supply = <&pm8953_l13>; + + status = "okay"; +}; + +&i2c_3 { + status = "okay"; + + touchscreen@20 { + reg = <0x20>; + compatible = "syna,rmi4-i2c"; + + interrupt-parent = <&tlmm>; + interrupts = <65 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-names = "default"; + pinctrl-0 = <&ts_reset>; + + vdd-supply = <&pm8953_l22>; + vio-supply = <&pm8953_l6>; + + syna,reset-delay-ms = <200>; + syna,startup-delay-ms = <500>; + }; +}; + +&pm8953_resin { + linux,code = <KEY_VOLUMEDOWN>; + status = "okay"; +}; + +&pmi8950_wled { + qcom,current-limit-microamp = <25000>; + qcom,num-strings = <3>; + qcom,external-pfet; + qcom,cabc; + + status = "okay"; +}; + +&rpm_requests { + regulators { + compatible = "qcom,rpm-pm8953-regulators"; + vdd_s1-supply = <&vph_pwr>; + vdd_s2-supply = <&vph_pwr>; + vdd_s3-supply = <&vph_pwr>; + vdd_s4-supply = <&vph_pwr>; + vdd_s5-supply = <&vph_pwr>; + vdd_s6-supply = <&vph_pwr>; + vdd_s7-supply = <&vph_pwr>; + vdd_l1-supply = <&pm8953_s3>; + vdd_l2_l3-supply = <&pm8953_s3>; + vdd_l4_l5_l6_l7_l16_l19-supply = <&pm8953_s4>; + vdd_l8_l11_l12_l13_l14_l15-supply = <&vph_pwr>; + vdd_l9_l10_l17_l18_l22-supply = <&vph_pwr>; + + pm8953_s1: s1 { + regulator-min-microvolt = <863000>; + regulator-max-microvolt = <1152000>; + }; + + pm8953_s3: s3 { + regulator-min-microvolt = <1224000>; + regulator-max-microvolt = <1224000>; + }; + + pm8953_s4: s4 { + regulator-min-microvolt = <1896000>; + regulator-max-microvolt = <2048000>; + }; + + pm8953_l1: l1 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1100000>; + }; + + pm8953_l2: l2 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + pm8953_l3: l3 { + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <925000>; + regulator-allow-set-load; + }; + + pm8953_l5: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8953_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + pm8953_l7: l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1900000>; + }; + + pm8953_l8: l8 { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + }; + + pm8953_l9: l9 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + }; + + pm8953_l10: l10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8953_l11: l11 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3000000>; + }; + + pm8953_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + }; + + pm8953_l13: l13 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3125000>; + }; + + pm8953_l15: l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8953_l16: l16 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8953_l17: l17 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3000000>; + }; + + pm8953_l19: l19 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1350000>; + }; + + pm8953_l22: l22 { + regulator-always-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2850000>; + }; + + pm8953_l23: l23 { + regulator-min-microvolt = <975000>; + regulator-max-microvolt = <1225000>; + }; + }; +}; + +&sdhc_1 { + vmmc-supply = <&pm8953_l8>; + vqmmc-supply = <&pm8953_l5>; + + status = "okay"; +}; + +&sdhc_2 { + vmmc-supply = <&pm8953_l11>; + vqmmc-supply = <&pm8953_l12>; + + cd-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_off>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <1 2>, <96 4>, <111 1>, <126 1>; + + ts_reset: ts-reset-state { + pins = "gpio64"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; +}; + +&usb3 { + status = "okay"; +}; + +&usb3_dwc3 { + dr_mode = "peripheral"; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8953-xiaomi-daisy.dts b/arch/arm64/boot/dts/qcom/msm8953-xiaomi-daisy.dts new file mode 100644 index 000000000000..1d672e608653 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8953-xiaomi-daisy.dts @@ -0,0 +1,325 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Alejandro Tafalla + */ +/dts-v1/; + +#include "msm8953.dtsi" +#include "pm8953.dtsi" +#include "pmi8950.dtsi" + +/delete-node/ &adsp_fw_mem; +/delete-node/ &qseecom_mem; +/delete-node/ &wcnss_fw_mem; + +/ { + model = "Xiaomi Mi A2 Lite"; + compatible = "xiaomi,daisy", "qcom,msm8953"; + chassis-type = "handset"; + qcom,msm-id = <293 0>; + qcom,board-id= <0x1000b 0x9>; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + framebuffer@90001000 { + compatible = "simple-framebuffer"; + reg = <0 0x90001000 0 (1920 * 2280 * 3)>; + + width = <1080>; + height = <2280>; + stride = <(1080 * 3)>; + format = "r8g8b8"; + + power-domains = <&gcc MDSS_GDSC>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>, + <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_BYTE0_CLK>, + <&gcc GCC_MDSS_PCLK0_CLK>, + <&gcc GCC_MDSS_ESC0_CLK>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_key_default>; + + key-volume-up { + label = "Volume Up"; + gpios = <&tlmm 85 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + }; + }; + + reserved-memory { + qseecom_mem: qseecom@84a00000 { + reg = <0x0 0x84a00000 0x0 0x1900000>; + no-map; + }; + + adsp_fw_mem: adsp@8d600000 { + reg = <0x0 0x8d600000 0x0 0x1200000>; + no-map; + }; + + wcnss_fw_mem: wcnss@8e800000 { + reg = <0x0 0x8e800000 0x0 0x700000>; + no-map; + }; + }; + + /* + * We bitbang on &i2c_4 because BLSP is protected by TZ as sensors are + * normally proxied via ADSP firmware. GPIOs aren't protected. + */ + i2c-sensors { + compatible = "i2c-gpio"; + sda-gpios = <&tlmm 14 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&tlmm 15 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; /* ~100 kHz */ + #address-cells = <1>; + #size-cells = <0>; + + imu@6a { + compatible = "st,lsm6dsl"; + reg = <0x6a>; + vdd-supply = <&pm8953_l10>; + vddio-supply = <&pm8953_l6>; + mount-matrix = "-1", "0", "0", + "0", "-1", "0", + "0", "0", "1"; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-always-on; + regulator-boot-on; + }; +}; + +&hsusb_phy { + vdd-supply = <&pm8953_l3>; + vdda-pll-supply = <&pm8953_l7>; + vdda-phy-dpdm-supply = <&pm8953_l13>; + + status = "okay"; +}; + +&i2c_2 { + status = "okay"; + + speaker_codec: audio-codec@3a { + compatible = "maxim,max98927"; + reg = <0x3a>; + + reset-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>; + + vmon-slot-no = <1>; + imon-slot-no = <1>; + interleave_mode = <0>; + + #sound-dai-cells = <0>; + }; +}; + +&i2c_3 { + status = "okay"; + + touchscreen@38 { + compatible = "edt,edt-ft5406"; + reg = <0x38>; + + interrupt-parent = <&tlmm>; + interrupts = <65 IRQ_TYPE_EDGE_FALLING>; + + reset-gpios = <&tlmm 64 GPIO_ACTIVE_LOW>; + + vcc-supply = <&pm8953_l10>; + + touchscreen-size-x = <1080>; + touchscreen-size-y = <2280>; + }; +}; + +&pm8953_resin { + linux,code = <KEY_VOLUMEDOWN>; + status = "okay"; +}; + +&pmi8950_wled { + qcom,current-limit-microamp = <20000>; + qcom,num-strings = <2>; + + status = "okay"; +}; + +&rpm_requests { + regulators { + compatible = "qcom,rpm-pm8953-regulators"; + + vdd_s1-supply = <&vph_pwr>; + vdd_s2-supply = <&vph_pwr>; + vdd_s3-supply = <&vph_pwr>; + vdd_s4-supply = <&vph_pwr>; + vdd_s5-supply = <&vph_pwr>; + vdd_s6-supply = <&vph_pwr>; + vdd_s7-supply = <&vph_pwr>; + vdd_l1-supply = <&pm8953_s3>; + vdd_l2_l3-supply = <&pm8953_s3>; + vdd_l4_l5_l6_l7_l16_l19-supply = <&pm8953_s4>; + vdd_l8_l11_l12_l13_l14_l15-supply = <&vph_pwr>; + vdd_l9_l10_l17_l18_l22-supply = <&vph_pwr>; + + pm8953_s1: s1 { + regulator-min-microvolt = <863000>; + regulator-max-microvolt = <1152000>; + }; + + pm8953_s3: s3 { + regulator-min-microvolt = <1224000>; + regulator-max-microvolt = <1224000>; + }; + + pm8953_s4: s4 { + regulator-min-microvolt = <1896000>; + regulator-max-microvolt = <2048000>; + }; + + pm8953_l1: l1 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1100000>; + }; + + pm8953_l2: l2 { + regulator-min-microvolt = <975000>; + regulator-max-microvolt = <1225000>; + }; + + pm8953_l3: l3 { + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <925000>; + regulator-allow-set-load; + }; + + pm8953_l5: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8953_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + pm8953_l7: l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1900000>; + }; + + pm8953_l8: l8 { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + }; + + pm8953_l9: l9 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + }; + + pm8953_l10: l10 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + pm8953_l11: l11 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + }; + + pm8953_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8953_l13: l13 { + regulator-min-microvolt = <3125000>; + regulator-max-microvolt = <3125000>; + }; + + pm8953_l16: l16 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8953_l17: l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pm8953_l19: l19 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1350000>; + }; + + pm8953_l22: l22 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + pm8953_l23: l23 { + regulator-min-microvolt = <975000>; + regulator-max-microvolt = <1225000>; + }; + }; +}; + +&sdhc_1 { + vmmc-supply = <&pm8953_l8>; + vqmmc-supply = <&pm8953_l5>; + + status = "okay"; +}; + +&sdhc_2 { + vmmc-supply = <&pm8953_l11>; + vqmmc-supply = <&pm8953_l12>; + + cd-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <0 4>, <16 4>, <135 4>; +}; + +&uart_0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart_console_active>; + + status = "okay"; +}; + +&usb3 { + status = "okay"; +}; + +&usb3_dwc3 { + dr_mode = "peripheral"; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8953-xiaomi-mido.dts b/arch/arm64/boot/dts/qcom/msm8953-xiaomi-mido.dts new file mode 100644 index 000000000000..ed95d09cedb1 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8953-xiaomi-mido.dts @@ -0,0 +1,329 @@ +// SPDX-License-Identifier: BSD-3-Clause +/dts-v1/; + +#include "msm8953.dtsi" +#include "pm8953.dtsi" +#include "pmi8950.dtsi" +#include <dt-bindings/leds/common.h> + +/delete-node/ &cont_splash_mem; +/delete-node/ &qseecom_mem; + +/ { + model = "Xiaomi Redmi Note 4X"; + compatible = "xiaomi,mido", "qcom,msm8953"; + chassis-type = "handset"; + qcom,msm-id = <293 0>; + qcom,board-id = <11 0>; + + aliases { + mmc0 = &sdhc_1; + mmc1 = &sdhc_2; + }; + + speaker_amp: audio-amplifier { + compatible = "awinic,aw8738"; + mode-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + awinic,mode = <5>; + sound-name-prefix = "Speaker Amp"; + }; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + framebuffer@90001000 { + compatible = "simple-framebuffer"; + reg = <0 0x90001000 0 (1920 * 1080 * 3)>; + + width = <1080>; + height = <1920>; + stride = <(1080 * 3)>; + format = "r8g8b8"; + + power-domains = <&gcc MDSS_GDSC>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>, + <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_BYTE0_CLK>, + <&gcc GCC_MDSS_PCLK0_CLK>, + <&gcc GCC_MDSS_ESC0_CLK>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_key_default>; + + key-volume-up { + label = "Volume Up"; + gpios = <&tlmm 85 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + }; + }; + + reserved-memory { + qseecom_mem: qseecom@84a00000 { + reg = <0x0 0x84a00000 0x0 0x1900000>; + no-map; + }; + + cont_splash_mem: cont-splash@90001000 { + reg = <0x0 0x90001000 0x0 (1080 * 1920 * 3)>; + no-map; + }; + + ramoops@9ff00000 { + compatible = "ramoops"; + reg = <0x0 0x9ff00000 0x0 0x00100000>; + console-size = <0x100000>; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&hsusb_phy { + vdd-supply = <&pm8953_l3>; + vdda-pll-supply = <&pm8953_l7>; + vdda-phy-dpdm-supply = <&pm8953_l13>; + + status = "okay"; +}; + +&i2c_2 { + status = "okay"; + + led-controller@45 { + compatible = "awinic,aw2013"; + reg = <0x45>; + + vcc-supply = <&pm8953_l10>; + + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = <LED_COLOR_ID_RED>; + function = LED_FUNCTION_INDICATOR; + led-max-microamp = <5000>; + }; + + led@1 { + reg = <1>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_INDICATOR; + led-max-microamp = <5000>; + }; + + led@2 { + reg = <2>; + color = <LED_COLOR_ID_BLUE>; + function = LED_FUNCTION_INDICATOR; + led-max-microamp = <5000>; + }; + }; +}; + +&i2c_3 { + status = "okay"; + + touchscreen@38 { + compatible = "edt,edt-ft5406"; + reg = <0x38>; + + interrupt-parent = <&tlmm>; + interrupts = <65 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_active>; + + reset-gpios = <&tlmm 64 GPIO_ACTIVE_LOW>; + + vcc-supply = <&pm8953_l10>; + + touchscreen-size-x = <1080>; + touchscreen-size-y = <1920>; + }; +}; + +&pm8953_resin { + linux,code = <KEY_VOLUMEDOWN>; + status = "okay"; +}; + +&rpm_requests { + regulators { + compatible = "qcom,rpm-pm8953-regulators"; + + vdd_s1-supply = <&vph_pwr>; + vdd_s2-supply = <&vph_pwr>; + vdd_s3-supply = <&vph_pwr>; + vdd_s4-supply = <&vph_pwr>; + vdd_s5-supply = <&vph_pwr>; + vdd_s6-supply = <&vph_pwr>; + vdd_s7-supply = <&vph_pwr>; + vdd_l1-supply = <&pm8953_s3>; + vdd_l2_l3-supply = <&pm8953_s3>; + vdd_l4_l5_l6_l7_l16_l19-supply = <&pm8953_s4>; + vdd_l8_l11_l12_l13_l14_l15-supply = <&vph_pwr>; + vdd_l9_l10_l17_l18_l22-supply = <&vph_pwr>; + vdd_l23-supply = <&pm8953_s3>; + + pm8953_s1: s1 { + regulator-min-microvolt = <863000>; + regulator-max-microvolt = <1152000>; + }; + + pm8953_s3: s3 { + regulator-min-microvolt = <1224000>; + regulator-max-microvolt = <1224000>; + }; + + pm8953_s4: s4 { + regulator-min-microvolt = <1896000>; + regulator-max-microvolt = <2048000>; + }; + + pm8953_l1: l1 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1100000>; + }; + + pm8953_l2: l2 { + regulator-min-microvolt = <975000>; + regulator-max-microvolt = <1225000>; + }; + + pm8953_l3: l3 { + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <925000>; + regulator-allow-set-load; + }; + + pm8953_l5: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8953_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + pm8953_l7: l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1900000>; + }; + + pm8953_l8: l8 { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + }; + + pm8953_l9: l9 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + }; + + pm8953_l10: l10 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + pm8953_l11: l11 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + }; + + pm8953_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8953_l13: l13 { + regulator-min-microvolt = <3125000>; + regulator-max-microvolt = <3125000>; + }; + + pm8953_l16: l16 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8953_l17: l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pm8953_l19: l19 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1350000>; + }; + + pm8953_l22: l22 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + pm8953_l23: l23 { + regulator-min-microvolt = <975000>; + regulator-max-microvolt = <1225000>; + }; + }; +}; + +&sdhc_1 { + vmmc-supply = <&pm8953_l8>; + vqmmc-supply = <&pm8953_l5>; + + status = "okay"; +}; + +&sdhc_2 { + vmmc-supply = <&pm8953_l11>; + vqmmc-supply = <&pm8953_l12>; + + cd-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <0 4>, <135 4>; + + ts_int_active: ts-int-active-state { + pins = "gpio65"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; +}; + +&usb3 { + status = "okay"; +}; + +&usb3_dwc3 { + dr_mode = "peripheral"; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8953-xiaomi-tissot.dts b/arch/arm64/boot/dts/qcom/msm8953-xiaomi-tissot.dts new file mode 100644 index 000000000000..831d3a42b583 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8953-xiaomi-tissot.dts @@ -0,0 +1,325 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Danila Tikhonov <JIaxyga@protonmail.com> + * Copyright (c) 2022, Anton Bambura <jenneron@protonmail.com> + */ +/dts-v1/; + +#include "msm8953.dtsi" +#include "pm8953.dtsi" +#include "pmi8950.dtsi" +#include <dt-bindings/leds/common.h> + +/delete-node/ &adsp_fw_mem; +/delete-node/ &qseecom_mem; +/delete-node/ &wcnss_fw_mem; + +/ { + model = "Xiaomi Mi A1"; + compatible = "xiaomi,tissot", "qcom,msm8953"; + chassis-type = "handset"; + qcom,msm-id = <293 0>; + qcom,board-id = <0x1000b 0x00>; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_key_default>, <&gpio_hall_sensor_default>; + + event-hall-sensor { + label = "Hall Effect Sensor"; + gpios = <&tlmm 44 GPIO_ACTIVE_LOW>; + linux,input-type = <EV_SW>; + linux,code = <SW_LID>; + linux,can-disable; + }; + + key-volume-up { + label = "Volume Up"; + gpios = <&tlmm 85 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + }; + }; + + reserved-memory { + qseecom_mem: qseecom@84a00000 { + reg = <0x0 0x84a00000 0x0 0x1900000>; + no-map; + }; + + adsp_fw_mem: adsp@8d600000 { + reg = <0x0 0x8d600000 0x0 0x1200000>; + no-map; + }; + + wcnss_fw_mem: wcnss@8e800000 { + reg = <0x0 0x8e800000 0x0 0x700000>; + no-map; + }; + + ramoops@9ff00000 { + compatible = "ramoops"; + reg = <0x0 0x9ff00000 0x0 0x00100000>; + record-size = <0x1000>; + console-size = <0x80000>; + ftrace-size = <0x1000>; + pmsg-size = <0x8000>; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-always-on; + regulator-boot-on; + }; +}; + +&hsusb_phy { + vdd-supply = <&pm8953_l3>; + vdda-pll-supply = <&pm8953_l7>; + vdda-phy-dpdm-supply = <&pm8953_l13>; + + status = "okay"; +}; + +&i2c_2 { + status = "okay"; + + max98927_codec: audio-codec@3a { + compatible = "maxim,max98927"; + reg = <0x3a>; + + reset-gpios = <&tlmm 86 GPIO_ACTIVE_LOW>; + + vmon-slot-no = <1>; + imon-slot-no = <1>; + + #sound-dai-cells = <1>; + }; + + led-controller@45 { + compatible = "awinic,aw2013"; + reg = <0x45>; + + vcc-supply = <&pm8953_l10>; + + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + led-max-microamp = <5000>; + function = LED_FUNCTION_INDICATOR; + color = <LED_COLOR_ID_WHITE>; + }; + }; +}; + +&i2c_3 { + status = "okay"; + + touchscreen@38 { + compatible = "edt,edt-ft5406"; + reg = <0x38>; + + interrupt-parent = <&tlmm>; + interrupts = <65 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_default>; + + reset-gpios = <&tlmm 64 GPIO_ACTIVE_LOW>; + + vcc-supply = <&pm8953_l10>; + + touchscreen-size-x = <1080>; + touchscreen-size-y = <1920>; + }; +}; + +&pm8953_resin { + linux,code = <KEY_VOLUMEDOWN>; + status = "okay"; +}; + +&pmi8950_wled { + qcom,num-strings = <2>; + qcom,external-pfet; + qcom,cabc; + + status = "okay"; +}; + +&rpm_requests { + regulators { + compatible = "qcom,rpm-pm8953-regulators"; + + vdd_s1-supply = <&vph_pwr>; + vdd_s2-supply = <&vph_pwr>; + vdd_s3-supply = <&vph_pwr>; + vdd_s4-supply = <&vph_pwr>; + vdd_s5-supply = <&vph_pwr>; + vdd_s6-supply = <&vph_pwr>; + vdd_s7-supply = <&vph_pwr>; + vdd_l1-supply = <&pm8953_s3>; + vdd_l2_l3-supply = <&pm8953_s3>; + vdd_l4_l5_l6_l7_l16_l19-supply = <&pm8953_s4>; + vdd_l8_l11_l12_l13_l14_l15-supply = <&vph_pwr>; + vdd_l9_l10_l17_l18_l22-supply = <&vph_pwr>; + + pm8953_s1: s1 { + regulator-min-microvolt = <870000>; + regulator-max-microvolt = <1156000>; + }; + + pm8953_s3: s3 { + regulator-min-microvolt = <1224000>; + regulator-max-microvolt = <1224000>; + }; + + pm8953_s4: s4 { + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <2050000>; + }; + + pm8953_l1: l1 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + pm8953_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1225000>; + }; + + pm8953_l3: l3 { + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <925000>; + }; + + pm8953_l5: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8953_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8953_l7: l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1900000>; + }; + + pm8953_l8: l8 { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + }; + + pm8953_l9: l9 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + pm8953_l10:l10 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pm8953_l11: l11 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + }; + + pm8953_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8953_l13: l13 { + regulator-min-microvolt = <3125000>; + regulator-max-microvolt = <3125000>; + }; + + pm8953_l16: l16 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8953_l17: l17 { + regulator-min-microvolt = <2750000>; + regulator-max-microvolt = <2850000>; + }; + + pm8953_l19: l19 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1350000>; + }; + + pm8953_l22: l22 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + pm8953_l23: l23 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1225000>; + }; + }; +}; + +&sdhc_1 { + vmmc-supply = <&pm8953_l8>; + vqmmc-supply = <&pm8953_l5>; + + status = "okay"; +}; + +&sdhc_2 { + vmmc-supply = <&pm8953_l11>; + vqmmc-supply = <&pm8953_l12>; + + cd-gpios = <&tlmm 133 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <0 4>, <16 4>, <135 4>; + + gpio_hall_sensor_default: gpio-hall-sensor-state { + pins = "gpio44"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + ts_int_default: ts-int-default-state { + pins = "gpio65"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; +}; + +&uart_0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart_console_active>; + + status = "okay"; +}; + +&usb3 { + status = "okay"; +}; + +&usb3_dwc3 { + dr_mode = "peripheral"; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8953-xiaomi-vince.dts b/arch/arm64/boot/dts/qcom/msm8953-xiaomi-vince.dts new file mode 100644 index 000000000000..b5be55034fd3 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8953-xiaomi-vince.dts @@ -0,0 +1,361 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Eugene Lepshy <fekz115@gmail.com> + * Copyright (c) 2022, Gianluca Boiano <morf3089@gmail.com> + */ +/dts-v1/; + +#include "msm8953.dtsi" +#include "pm8953.dtsi" +#include "pmi8950.dtsi" +#include <dt-bindings/leds/common.h> + +/delete-node/ &adsp_fw_mem; +/delete-node/ &cont_splash_mem; +/delete-node/ &qseecom_mem; +/delete-node/ &wcnss_fw_mem; + +/ { + model = "Xiaomi Redmi 5 Plus"; + compatible = "xiaomi,vince", "qcom,msm8953"; + chassis-type = "handset"; + qcom,msm-id = <293 0>; + qcom,board-id= <0x1000b 0x08>; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_key_default>; + + key-volume-up { + label = "volume_up"; + linux,code = <KEY_VOLUMEUP>; + gpios = <&tlmm 85 GPIO_ACTIVE_LOW>; + }; + }; + + reserved-memory { + qseecom_mem: qseecom@84a00000 { + reg = <0x0 0x84a00000 0x0 0x1900000>; + no-map; + }; + + cont_splash_mem: cont-splash@90001000 { + reg = <0x0 0x90001000 0x0 (1080 * 2160 * 3)>; + no-map; + }; + + adsp_fw_mem: adsp@8d600000 { + reg = <0x0 0x8d600000 0x0 0x1200000>; + no-map; + }; + + wcnss_fw_mem: wcnss@8e800000 { + reg = <0x0 0x8e800000 0x0 0x700000>; + no-map; + }; + + ramoops@9ff00000 { + compatible = "ramoops"; + reg = <0x0 0x9ff00000 0x0 0x100000>; + record-size = <0x1000>; + console-size = <0x80000>; + ftrace-size = <0x1000>; + pmsg-size = <0x8000>; + }; + }; + + /* + * We bitbang on &i2c_4 because BLSP is protected by TZ as sensors are + * normally proxied via ADSP firmware. GPIOs aren't protected. + */ + i2c-sensors { + compatible = "i2c-gpio"; + sda-gpios = <&tlmm 14 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&tlmm 15 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; /* ~100 kHz */ + #address-cells = <1>; + #size-cells = <0>; + + imu@6a { + compatible = "st,lsm6dsl"; + reg = <0x6a>; + vdd-supply = <&pm8953_l10>; + vddio-supply = <&pm8953_l6>; + mount-matrix = "1", "0", "0", + "0", "-1", "0", + "0", "0", "1"; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-always-on; + regulator-boot-on; + }; +}; + +&hsusb_phy { + vdd-supply = <&pm8953_l3>; + vdda-pll-supply = <&pm8953_l7>; + vdda-phy-dpdm-supply = <&pm8953_l13>; + + status = "okay"; +}; + +&i2c_2 { + status = "okay"; + + led-controller@45 { + compatible = "awinic,aw2013"; + reg = <0x45>; + + vcc-supply = <&pm8953_l10>; + + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + led-max-microamp = <5000>; + function = LED_FUNCTION_INDICATOR; + color = <LED_COLOR_ID_WHITE>; + }; + }; +}; + +&i2c_3 { + status = "okay"; + + touchscreen@20 { + reg = <0x20>; + compatible = "syna,rmi4-i2c"; + interrupts-parent = <&tlmm>; + interrupts-extended = <&tlmm 65 IRQ_TYPE_EDGE_FALLING>; + + #address-cells = <1>; + #size-cells = <0>; + + vdd-supply = <&pm8953_l10>; + vio-supply = <&pm8953_l6>; + + pinctrl-names = "init", "suspend"; + pinctrl-0 = <&ts_reset_active &ts_int_active>; + pinctrl-1 = <&ts_reset_suspend &ts_int_suspend>; + syna,reset-delay-ms = <200>; + syna,startup-delay-ms = <500>; + + rmi4-f01@1 { + reg = <0x01>; + syna,nosleep-mode = <1>; + }; + + rmi4-f12@12 { + reg = <0x12>; + syna,rezero-wait-ms = <20>; + syna,sensor-type = <1>; + touchscreen-x-mm = <68>; + touchscreen-y-mm = <122>; + }; + }; +}; + +&pm8953_resin { + linux,code = <KEY_VOLUMEDOWN>; + status = "okay"; +}; + +&pmi8950_wled { + qcom,current-limit-microamp = <20000>; + qcom,ovp-millivolt = <29600>; + qcom,num-strings = <2>; + qcom,external-pfet; + qcom,cabc; + + status = "okay"; +}; + +&rpm_requests { + regulators { + compatible = "qcom,rpm-pm8953-regulators"; + vdd_s1-supply = <&vph_pwr>; + vdd_s2-supply = <&vph_pwr>; + vdd_s3-supply = <&vph_pwr>; + vdd_s4-supply = <&vph_pwr>; + vdd_s5-supply = <&vph_pwr>; + vdd_s6-supply = <&vph_pwr>; + vdd_s7-supply = <&vph_pwr>; + vdd_l1-supply = <&pm8953_s3>; + vdd_l2_l3-supply = <&pm8953_s3>; + vdd_l4_l5_l6_l7_l16_l19-supply = <&pm8953_s4>; + vdd_l8_l11_l12_l13_l14_l15-supply = <&vph_pwr>; + vdd_l9_l10_l17_l18_l22-supply = <&vph_pwr>; + + pm8953_s1: s1 { + regulator-min-microvolt = <870000>; + regulator-max-microvolt = <1156000>; + }; + + pm8953_s3: s3 { + regulator-min-microvolt = <984000>; + regulator-max-microvolt = <1224000>; + }; + + pm8953_s4: s4 { + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <2050000>; + }; + + pm8953_l1: l1 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1100000>; + }; + + pm8953_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1225000>; + }; + + pm8953_l3: l3 { + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <925000>; + }; + + pm8953_l5: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8953_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8953_l7: l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1900000>; + }; + + pm8953_l8: l8 { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + }; + + pm8953_l9: l9 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + }; + + pm8953_l10: l10 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pm8953_l11: l11 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + }; + + pm8953_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8953_l13: l13 { + regulator-min-microvolt = <3125000>; + regulator-max-microvolt = <3125000>; + }; + + pm8953_l16: l16 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8953_l17: l17 { + regulator-min-microvolt = <2750000>; + regulator-max-microvolt = <2850000>; + }; + + pm8953_l19: l19 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1380000>; + }; + + pm8953_l22: l22 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + pm8953_l23: l23 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1225000>; + }; + }; +}; + +&sdhc_1 { + vmmc-supply = <&pm8953_l8>; + vqmmc-supply = <&pm8953_l5>; + + status = "okay"; +}; + +&sdhc_2 { + vmmc-supply = <&pm8953_l11>; + vqmmc-supply = <&pm8953_l12>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <0 4>, <16 4>, <135 4>; + + ts_reset_active: ts-reset-active-state { + pins = "gpio64"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; + + ts_reset_suspend: ts-reset-suspend-state { + pins = "gpio64"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + ts_int_active: ts-int-active-state { + pins = "gpio65"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; + + ts_int_suspend: ts-int-suspend-state { + pins = "gpio65"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; +}; + +&uart_0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart_console_active>; + + status = "okay"; +}; + +&usb3 { + status = "okay"; +}; + +&usb3_dwc3 { + dr_mode = "peripheral"; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi index 32349174c4bd..610f3e3fc0c2 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -42,13 +42,6 @@ capacity-dmips-mhz = <1024>; next-level-cache = <&L2_0>; #cooling-cells = <2>; - - l1-icache { - compatible = "cache"; - }; - l1-dcache { - compatible = "cache"; - }; }; CPU1: cpu@1 { @@ -59,13 +52,6 @@ capacity-dmips-mhz = <1024>; next-level-cache = <&L2_0>; #cooling-cells = <2>; - - l1-icache { - compatible = "cache"; - }; - l1-dcache { - compatible = "cache"; - }; }; CPU2: cpu@2 { @@ -76,13 +62,6 @@ capacity-dmips-mhz = <1024>; next-level-cache = <&L2_0>; #cooling-cells = <2>; - - l1-icache { - compatible = "cache"; - }; - l1-dcache { - compatible = "cache"; - }; }; CPU3: cpu@3 { @@ -93,13 +72,6 @@ capacity-dmips-mhz = <1024>; next-level-cache = <&L2_0>; #cooling-cells = <2>; - - l1-icache { - compatible = "cache"; - }; - l1-dcache { - compatible = "cache"; - }; }; CPU4: cpu@100 { @@ -110,13 +82,6 @@ capacity-dmips-mhz = <1024>; next-level-cache = <&L2_1>; #cooling-cells = <2>; - - l1-icache { - compatible = "cache"; - }; - l1-dcache { - compatible = "cache"; - }; }; CPU5: cpu@101 { @@ -127,13 +92,6 @@ capacity-dmips-mhz = <1024>; next-level-cache = <&L2_1>; #cooling-cells = <2>; - - l1-icache { - compatible = "cache"; - }; - l1-dcache { - compatible = "cache"; - }; }; CPU6: cpu@102 { @@ -144,13 +102,6 @@ capacity-dmips-mhz = <1024>; next-level-cache = <&L2_1>; #cooling-cells = <2>; - - l1-icache { - compatible = "cache"; - }; - l1-dcache { - compatible = "cache"; - }; }; CPU7: cpu@103 { @@ -161,13 +112,6 @@ capacity-dmips-mhz = <1024>; next-level-cache = <&L2_1>; #cooling-cells = <2>; - - l1-icache { - compatible = "cache"; - }; - l1-dcache { - compatible = "cache"; - }; }; cpu-map { @@ -202,12 +146,12 @@ }; }; - L2_0: l2-cache_0 { + L2_0: l2-cache-0 { compatible = "cache"; cache-level = <2>; }; - L2_1: l2-cache_1 { + L2_1: l2-cache-1 { compatible = "cache"; cache-level = <2>; }; @@ -245,18 +189,18 @@ #size-cells = <2>; ranges; - zap_shader_region: memory@81800000 { + zap_shader_region: zap@81800000 { compatible = "shared-dma-pool"; reg = <0x0 0x81800000 0x0 0x2000>; no-map; }; - memory@85b00000 { + qseecom_mem: qseecom@85b00000 { reg = <0x0 0x85b00000 0x0 0x800000>; no-map; }; - smem_mem: memory@86300000 { + smem_mem: smem@86300000 { compatible = "qcom,smem"; reg = <0x0 0x86300000 0x0 0x100000>; qcom,rpm-msg-ram = <&rpm_msg_ram>; @@ -264,47 +208,47 @@ no-map; }; - memory@86400000 { + reserved@86400000 { reg = <0x0 0x86400000 0x0 0x400000>; no-map; }; - mpss_mem: memory@86c00000 { + mpss_mem: mpss@86c00000 { reg = <0x0 0x86c00000 0x0 0x6a00000>; no-map; }; - adsp_fw_mem: memory@8d600000 { + adsp_fw_mem: adsp@8d600000 { reg = <0x0 0x8d600000 0x0 0x1100000>; no-map; }; - wcnss_fw_mem: memory@8e700000 { + wcnss_fw_mem: wcnss@8e700000 { reg = <0x0 0x8e700000 0x0 0x700000>; no-map; }; - memory@90000000 { + dfps_data_mem: dfps-data@90000000 { reg = <0 0x90000000 0 0x1000>; no-map; }; - memory@90001000 { + cont_splash_mem: cont-splash@90001000 { reg = <0x0 0x90001000 0x0 0x13ff000>; no-map; }; - venus_mem: memory@91400000 { + venus_mem: venus@91400000 { reg = <0x0 0x91400000 0x0 0x700000>; no-map; }; - mba_mem: memory@92000000 { + mba_mem: mba@92000000 { reg = <0x0 0x92000000 0x0 0x100000>; no-map; }; - memory@f2d00000 { + rmtfs@f2d00000 { compatible = "qcom,rmtfs-mem"; reg = <0x0 0xf2d00000 0x0 0x180000>; no-map; @@ -455,7 +399,7 @@ reg = <0x1000000 0x300000>; interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; - gpio-ranges = <&tlmm 0 0 155>; + gpio-ranges = <&tlmm 0 0 142>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; @@ -726,7 +670,7 @@ reg = <0x193f044 0x4>; }; - mdss: mdss@1a00000 { + mdss: display-subsystem@1a00000 { compatible = "qcom,mdss"; reg = <0x1a00000 0x1000>, @@ -755,7 +699,7 @@ status = "disabled"; - mdp: mdp@1a01000 { + mdp: display-controller@1a01000 { compatible = "qcom,msm8953-mdp5", "qcom,mdp5"; reg = <0x1a01000 0x89000>; reg-names = "mdp_phys"; @@ -797,7 +741,7 @@ }; dsi0: dsi@1a94000 { - compatible = "qcom,mdss-dsi-ctrl"; + compatible = "qcom,msm8953-dsi-ctrl", "qcom,mdss-dsi-ctrl"; reg = <0x1a94000 0x400>; reg-names = "dsi_ctrl"; @@ -867,7 +811,7 @@ }; dsi1: dsi@1a96000 { - compatible = "qcom,mdss-dsi-ctrl"; + compatible = "qcom,msm8953-dsi-ctrl", "qcom,mdss-dsi-ctrl"; reg = <0x1a96000 0x400>; reg-names = "dsi_ctrl"; diff --git a/arch/arm64/boot/dts/qcom/msm8956.dtsi b/arch/arm64/boot/dts/qcom/msm8956.dtsi index e432512d8716..668e05185c21 100644 --- a/arch/arm64/boot/dts/qcom/msm8956.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8956.dtsi @@ -12,6 +12,10 @@ interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; }; +&tsens { + compatible = "qcom,msm8956-tsens", "qcom,tsens-v1"; +}; + /* * You might be wondering.. why is it so empty out there? * Well, the SoCs are almost identical. diff --git a/arch/arm64/boot/dts/qcom/msm8976.dtsi b/arch/arm64/boot/dts/qcom/msm8976.dtsi index 05dcb30b0779..2d360d05aa5e 100644 --- a/arch/arm64/boot/dts/qcom/msm8976.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8976.dtsi @@ -481,8 +481,129 @@ #address-cells = <1>; #size-cells = <1>; - tsens_caldata: caldata@218 { - reg = <0x218 0x18>; + tsens_base1: base1@218 { + reg = <0x218 1>; + bits = <0 8>; + }; + + tsens_s0_p1: s0-p1@219 { + reg = <0x219 0x1>; + bits = <0 6>; + }; + + tsens_s0_p2: s0-p2@219 { + reg = <0x219 0x2>; + bits = <6 6>; + }; + + tsens_s1_p1: s1-p1@21a { + reg = <0x21a 0x2>; + bits = <4 6>; + }; + + tsens_s1_p2: s1-p2@21b { + reg = <0x21b 0x1>; + bits = <2 6>; + }; + + tsens_s2_p1: s2-p1@21c { + reg = <0x21c 0x1>; + bits = <0 6>; + }; + + tsens_s2_p2: s2-p2@21c { + reg = <0x21c 0x2>; + bits = <6 6>; + }; + + tsens_s3_p1: s3-p1@21d { + reg = <0x21d 0x2>; + bits = <4 6>; + }; + + tsens_s3_p2: s3-p2@21e { + reg = <0x21e 0x1>; + bits = <2 6>; + }; + + tsens_base2: base2@220 { + reg = <0x220 1>; + bits = <0 8>; + }; + + tsens_s4_p1: s4-p1@221 { + reg = <0x221 0x1>; + bits = <0 6>; + }; + + tsens_s4_p2: s4-p2@221 { + reg = <0x221 0x2>; + bits = <6 6>; + }; + + tsens_s5_p1: s5-p1@222 { + reg = <0x222 0x2>; + bits = <4 6>; + }; + + tsens_s5_p2: s5-p2@223 { + reg = <0x224 0x1>; + bits = <2 6>; + }; + + tsens_s6_p1: s6-p1@224 { + reg = <0x224 0x1>; + bits = <0 6>; + }; + + tsens_s6_p2: s6-p2@224 { + reg = <0x224 0x2>; + bits = <6 6>; + }; + + tsens_s7_p1: s7-p1@225 { + reg = <0x225 0x2>; + bits = <4 6>; + }; + + tsens_s7_p2: s7-p2@226 { + reg = <0x226 0x2>; + bits = <2 6>; + }; + + tsens_mode: mode@228 { + reg = <0x228 1>; + bits = <0 3>; + }; + + tsens_s8_p1: s8-p1@228 { + reg = <0x228 0x2>; + bits = <3 6>; + }; + + tsens_s8_p2: s8-p2@229 { + reg = <0x229 0x1>; + bits = <1 6>; + }; + + tsens_s9_p1: s9-p1@229 { + reg = <0x229 0x2>; + bits = <7 6>; + }; + + tsens_s9_p2: s9-p2@22a { + reg = <0x22a 0x2>; + bits = <5 6>; + }; + + tsens_s10_p1: s10-p1@22b { + reg = <0x22b 0x2>; + bits = <3 6>; + }; + + tsens_s10_p2: s10-p2@22c { + reg = <0x22c 0x1>; + bits = <1 6>; }; }; @@ -492,8 +613,32 @@ <0x004a8000 0x1000>; /* SROT */ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "uplow"; - nvmem-cells = <&tsens_caldata>; - nvmem-cell-names = "calib"; + nvmem-cells = <&tsens_mode>, + <&tsens_base1>, <&tsens_base2>, + <&tsens_s0_p1>, <&tsens_s0_p2>, + <&tsens_s1_p1>, <&tsens_s1_p2>, + <&tsens_s2_p1>, <&tsens_s2_p2>, + <&tsens_s3_p1>, <&tsens_s3_p2>, + <&tsens_s4_p1>, <&tsens_s4_p2>, + <&tsens_s5_p1>, <&tsens_s5_p2>, + <&tsens_s6_p1>, <&tsens_s6_p2>, + <&tsens_s7_p1>, <&tsens_s7_p2>, + <&tsens_s8_p1>, <&tsens_s8_p2>, + <&tsens_s9_p1>, <&tsens_s9_p2>, + <&tsens_s10_p1>, <&tsens_s10_p2>; + nvmem-cell-names = "mode", + "base1", "base2", + "s0_p1", "s0_p2", + "s1_p1", "s1_p2", + "s2_p1", "s2_p2", + "s3_p1", "s3_p2", + "s4_p1", "s4_p2", + "s5_p1", "s5_p2", + "s6_p1", "s6_p2", + "s7_p1", "s7_p2", + "s8_p1", "s8_p2", + "s9_p1", "s9_p2", + "s10_p1", "s10_p2"; #qcom,sensors = <11>; #thermal-sensor-cells = <1>; }; diff --git a/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi b/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi index 87c90e93667f..cd77dcb55872 100644 --- a/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi @@ -2,7 +2,8 @@ /* * Copyright (c) 2015, LGE Inc. All rights reserved. * Copyright (c) 2016, The Linux Foundation. All rights reserved. - * Copyright (c) 2021, Petr Vorel <petr.vorel@gmail.com> + * Copyright (c) 2021-2022, Petr Vorel <petr.vorel@gmail.com> + * Copyright (c) 2022, Dominik Kobinski <dominikkobinski314@gmail.com> */ /dts-v1/; @@ -14,6 +15,9 @@ /* cont_splash_mem has different memory mapping */ /delete-node/ &cont_splash_mem; +/* disabled on downstream, conflicts with cont_splash_mem */ +/delete-node/ &dfps_data_mem; + / { model = "LG Nexus 5X"; compatible = "lg,bullhead", "qcom,msm8992"; @@ -48,7 +52,17 @@ }; cont_splash_mem: memory@3400000 { - reg = <0 0x03400000 0 0x1200000>; + reg = <0 0x03400000 0 0xc00000>; + no-map; + }; + + reserved@5000000 { + reg = <0x0 0x05000000 0x0 0x1a00000>; + no-map; + }; + + reserved@6c00000 { + reg = <0x0 0x06c00000 0x0 0x400000>; no-map; }; }; @@ -80,8 +94,8 @@ /* S1, S2, S6 and S12 are managed by RPMPD */ pm8994_s1: s1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; + regulator-min-microvolt = <1025000>; + regulator-max-microvolt = <1025000>; }; pm8994_s2: s2 { @@ -237,11 +251,8 @@ }; pm8994_l26: l26 { - /* - * TODO: value from downstream - * regulator-min-microvolt = <987500>; - * fails to apply - */ + regulator-min-microvolt = <987500>; + regulator-max-microvolt = <987500>; }; pm8994_l27: l27 { @@ -255,19 +266,13 @@ }; pm8994_l29: l29 { - /* - * TODO: Unsupported voltage range. - * regulator-min-microvolt = <2800000>; - * regulator-max-microvolt = <2800000>; - */ + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; }; pm8994_l30: l30 { - /* - * TODO: get this verified - * regulator-min-microvolt = <1800000>; - * regulator-max-microvolt = <1800000>; - */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; }; pm8994_l31: l31 { @@ -276,11 +281,8 @@ }; pm8994_l32: l32 { - /* - * TODO: get this verified - * regulator-min-microvolt = <1800000>; - * regulator-max-microvolt = <1800000>; - */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts b/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts index b242c272d2af..fcca1ba94da6 100644 --- a/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts +++ b/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts @@ -11,6 +11,12 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/gpio-keys.h> +/delete-node/ &adsp_mem; +/delete-node/ &audio_mem; +/delete-node/ &mpss_mem; +/delete-node/ &peripheral_region; +/delete-node/ &rmtfs_mem; + / { model = "Xiaomi Mi 4C"; compatible = "xiaomi,libra", "qcom,msm8992"; @@ -70,25 +76,67 @@ #size-cells = <2>; ranges; - /* This is for getting crash logs using Android downstream kernels */ - ramoops@dfc00000 { - compatible = "ramoops"; - reg = <0x0 0xdfc00000 0x0 0x40000>; - console-size = <0x10000>; - record-size = <0x10000>; - ftrace-size = <0x10000>; - pmsg-size = <0x20000>; + memory_hole: hole@6400000 { + reg = <0 0x06400000 0 0x600000>; + no-map; + }; + + memory_hole2: hole2@6c00000 { + reg = <0 0x06c00000 0 0x2400000>; + no-map; + }; + + mpss_mem: mpss@9000000 { + reg = <0 0x09000000 0 0x5a00000>; + no-map; + }; + + tzapp: tzapp@ea00000 { + reg = <0 0x0ea00000 0 0x1900000>; + no-map; + }; + + mdm_rfsa_mem: mdm-rfsa@ca0b0000 { + reg = <0 0xca0b0000 0 0x10000>; + no-map; + }; + + rmtfs_mem: rmtfs@ca100000 { + compatible = "qcom,rmtfs-mem"; + reg = <0 0xca100000 0 0x180000>; + no-map; + + qcom,client-id = <1>; }; - modem_region: modem_region@9000000 { - reg = <0x0 0x9000000 0x0 0x5a00000>; + audio_mem: audio@cb400000 { + reg = <0 0xcb000000 0 0x400000>; + no-mem; + }; + + qseecom_mem: qseecom@cb400000 { + reg = <0 0xcb400000 0 0x1c00000>; + no-mem; + }; + + adsp_rfsa_mem: adsp-rfsa@cd000000 { + reg = <0 0xcd000000 0 0x10000>; no-map; }; - tzapp: modem_region@ea00000 { - reg = <0x0 0xea00000 0x0 0x1900000>; + sensor_rfsa_mem: sensor-rfsa@cd010000 { + reg = <0 0xcd010000 0 0x10000>; no-map; }; + + ramoops@dfc00000 { + compatible = "ramoops"; + reg = <0 0xdfc00000 0 0x40000>; + console-size = <0x10000>; + record-size = <0x10000>; + ftrace-size = <0x10000>; + pmsg-size = <0x20000>; + }; }; }; @@ -130,11 +178,6 @@ status = "okay"; }; -&peripheral_region { - reg = <0x0 0x7400000 0x0 0x1c00000>; - no-map; -}; - &pm8994_spmi_regulators { VDD_APC0: s8 { regulator-min-microvolt = <680000>; diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qcom/msm8992.dtsi index 10adb4986ef1..02fc3795dbfd 100644 --- a/arch/arm64/boot/dts/qcom/msm8992.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8992.dtsi @@ -37,10 +37,6 @@ compatible = "qcom,rpmcc-msm8992", "qcom,rpmcc"; }; -&tcsr_mutex { - compatible = "qcom,sfpb-mutex"; -}; - &timer { interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, diff --git a/arch/arm64/boot/dts/qcom/msm8994-huawei-angler-rev-101.dts b/arch/arm64/boot/dts/qcom/msm8994-huawei-angler-rev-101.dts index 85abff0e9b3f..7b0f62144c3e 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-huawei-angler-rev-101.dts +++ b/arch/arm64/boot/dts/qcom/msm8994-huawei-angler-rev-101.dts @@ -9,9 +9,6 @@ #include "msm8994.dtsi" -/* Angler's firmware does not report where the memory is allocated */ -/delete-node/ &cont_splash_mem; - / { model = "Huawei Nexus 6P"; compatible = "huawei,angler", "qcom,msm8994"; @@ -28,6 +25,22 @@ chosen { stdout-path = "serial0:115200n8"; }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + tzapp_mem: tzapp@4800000 { + reg = <0 0x04800000 0 0x1900000>; + no-map; + }; + + removed_region: reserved@6300000 { + reg = <0 0x06300000 0 0xD00000>; + no-map; + }; + }; }; &blsp1_uart2 { diff --git a/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi b/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi index 9b67f0d3820c..4520a7e86d5b 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi @@ -127,98 +127,98 @@ */ uefi_mem: memory@200000 { - reg = <0 0x200000 0 0x100000>; + reg = <0 0x00200000 0 0x100000>; no-map; }; mppark_mem: memory@300000 { - reg = <0 0x300000 0 0x80000>; + reg = <0 0x00300000 0 0x80000>; no-map; }; fbpt_mem: memory@380000 { - reg = <0 0x380000 0 0x1000>; + reg = <0 0x00380000 0 0x1000>; no-map; }; dbg2_mem: memory@381000 { - reg = <0 0x381000 0 0x4000>; + reg = <0 0x00381000 0 0x4000>; no-map; }; capsule_mem: memory@385000 { - reg = <0 0x385000 0 0x1000>; + reg = <0 0x00385000 0 0x1000>; no-map; }; tpmctrl_mem: memory@386000 { - reg = <0 0x386000 0 0x3000>; + reg = <0 0x00386000 0 0x3000>; no-map; }; uefiinfo_mem: memory@389000 { - reg = <0 0x389000 0 0x1000>; + reg = <0 0x00389000 0 0x1000>; no-map; }; reset_mem: memory@389000 { - reg = <0 0x389000 0 0x1000>; + reg = <0 0x00389000 0 0x1000>; no-map; }; resuncached_mem: memory@38e000 { - reg = <0 0x38e000 0 0x72000>; + reg = <0 0x0038e000 0 0x72000>; no-map; }; disp_mem: memory@400000 { - reg = <0 0x400000 0 0x800000>; + reg = <0 0x00400000 0 0x800000>; no-map; }; uefistack_mem: memory@c00000 { - reg = <0 0xc00000 0 0x40000>; + reg = <0 0x00c00000 0 0x40000>; no-map; }; cpuvect_mem: memory@c40000 { - reg = <0 0xc40000 0 0x10000>; + reg = <0 0x00c40000 0 0x10000>; no-map; }; rescached_mem: memory@400000 { - reg = <0 0xc50000 0 0xb0000>; + reg = <0 0x00c50000 0 0xb0000>; no-map; }; tzapps_mem: memory@6500000 { - reg = <0 0x6500000 0 0x500000>; + reg = <0 0x06500000 0 0x500000>; no-map; }; smem_mem: memory@6a00000 { - reg = <0 0x6a00000 0 0x200000>; + reg = <0 0x06a00000 0 0x200000>; no-map; }; hyp_mem: memory@6c00000 { - reg = <0 0x6c00000 0 0x100000>; + reg = <0 0x06c00000 0 0x100000>; no-map; }; tz_mem: memory@6d00000 { - reg = <0 0x6d00000 0 0x160000>; + reg = <0 0x06d00000 0 0x160000>; no-map; }; rfsa_adsp_mem: memory@6e60000 { - reg = <0 0x6e60000 0 0x10000>; + reg = <0 0x06e60000 0 0x10000>; no-map; }; rfsa_mpss_mem: memory@6e70000 { compatible = "qcom,rmtfs-mem"; - reg = <0 0x6e70000 0 0x10000>; + reg = <0 0x06e70000 0 0x10000>; no-map; qcom,client-id = <1>; @@ -229,7 +229,7 @@ * MPSS_EFS / SBL */ mba_mem: memory@6e80000 { - reg = <0 0x6e80000 0 0x180000>; + reg = <0 0x06e80000 0 0x180000>; no-map; }; @@ -239,33 +239,33 @@ */ mpss_mem: memory@7000000 { - reg = <0 0x7000000 0 0x5a00000>; + reg = <0 0x07000000 0 0x5a00000>; no-map; }; adsp_mem: memory@ca00000 { - reg = <0 0xca00000 0 0x1800000>; + reg = <0 0x0ca00000 0 0x1800000>; no-map; }; venus_mem: memory@e200000 { - reg = <0 0xe200000 0 0x500000>; + reg = <0 0x0e200000 0 0x500000>; no-map; }; pil_metadata_mem: memory@e700000 { - reg = <0 0xe700000 0 0x4000>; + reg = <0 0x0e700000 0 0x4000>; no-map; }; memory@e704000 { - reg = <0 0xe704000 0 0x7fc000>; + reg = <0 0x0e704000 0 0x7fc000>; no-map; }; /* Peripheral Image loader region end */ cnss_mem: memory@ef00000 { - reg = <0 0xef00000 0 0x300000>; + reg = <0 0x0ef00000 0 0x300000>; no-map; }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi index f3d153c34918..3ceb86b06209 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi @@ -163,7 +163,7 @@ * mainline Linux. */ &cont_splash_mem { - reg = <0 0x3401000 0 0x2200000>; + reg = <0 0x03401000 0 0x2200000>; }; &pmi8994_spmi_regulators { diff --git a/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi index 20f5c103c63b..2994337c6046 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi @@ -179,7 +179,6 @@ }; &dsi0_phy { - vdda-supply = <&vreg_l2a_1p25>; vcca-supply = <&vreg_l28a_0p925>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi index dec361b93cce..7f4d493a55ff 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi @@ -24,11 +24,7 @@ qcom,board-id = <8 0>; chosen { - /* - * Due to an unknown-for-a-few-years regression, - * SDHCI only works on MSM8996 in PIO (lame) mode. - */ - bootargs = "sdhci.debug_quirks=0x40 sdhci.debug_quirks2=0x4 maxcpus=2"; + bootargs = "maxcpus=2"; }; reserved-memory { @@ -104,8 +100,8 @@ }; &blsp1_i2c3 { - status = "okay"; clock-frequency = <355000>; + status = "okay"; tof_sensor: vl53l0x@29 { compatible = "st,vl53l0x"; @@ -118,15 +114,15 @@ }; &blsp2_i2c5 { - status = "okay"; clock-frequency = <355000>; + status = "okay"; /* FUSB301 USB-C controller */ }; &blsp2_i2c6 { - status = "okay"; clock-frequency = <355000>; + status = "okay"; synaptics@2c { compatible = "syna,rmi4-i2c"; @@ -183,11 +179,10 @@ }; &hsusb_phy1 { - status = "okay"; - vdd-supply = <&pm8994_l28>; vdda-pll-supply = <&pm8994_l12>; vdda-phy-dpdm-supply = <&pm8994_l24>; + status = "okay"; }; &mmcc { @@ -195,18 +190,17 @@ }; &pcie0 { - status = "okay"; perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>; vddpe-3v3-supply = <&wlan_en>; vdda-supply = <&pm8994_l28>; + status = "okay"; }; &pcie_phy { - status = "okay"; - vdda-phy-supply = <&pm8994_l28>; vdda-pll-supply = <&pm8994_l12>; + status = "okay"; }; &pm8994_gpios { @@ -478,8 +472,8 @@ }; &pm8994_resin { - status = "okay"; linux,code = <KEY_VOLUMEUP>; + status = "okay"; }; &pmi8994_gpios { @@ -623,9 +617,9 @@ }; &pmi8994_wled { - status = "okay"; default-brightness = <512>; qcom,num-strings = <3>; + status = "okay"; }; &rpm_requests { @@ -825,21 +819,18 @@ }; &sdhc1 { - /* eMMC doesn't seem to cooperate even in PIO mode.. */ - status = "disabled"; - vmmc-supply = <&pm8994_l20>; vqmmc-supply = <&pm8994_s4>; mmc-hs400-1_8v; mmc-hs200-1_8v; + status = "okay"; }; &sdhc2 { - status = "okay"; - cd-gpios = <&tlmm 40 GPIO_ACTIVE_HIGH>; vmmc-supply = <&pm8994_l21>; vqmmc-supply = <&pm8994_l13>; + status = "okay"; }; &tlmm { @@ -943,18 +934,15 @@ }; }; -/* - * For reasons that are currently unknown (but probably related to fusb301), USB takes about - * 6 minutes to wake up (nothing interesting in kernel logs), but then it works as it should. - */ &usb3 { - status = "okay"; qcom,select-utmi-as-pipe-clk; + status = "okay"; }; &usb3_dwc3 { extcon = <&usb3_id>; dr_mode = "peripheral"; + maximum-speed = "high-speed"; phys = <&hsusb_phy1>; phy-names = "usb2-phy"; snps,hird-threshold = /bits/ 8 <0>; diff --git a/arch/arm64/boot/dts/qcom/msm8996-v3.0.dtsi b/arch/arm64/boot/dts/qcom/msm8996-v3.0.dtsi index 5728583af41e..929bdcd45d02 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-v3.0.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-v3.0.dtsi @@ -19,7 +19,7 @@ * features get enabled upstream. */ -gpu_opp_table_3_0: gpu-opp-table-30 { +gpu_opp_table_3_0: opp-table-gpu30 { compatible = "operating-points-v2"; opp-624000000 { diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi index 5b47b8de69da..2acfed28e3cb 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi @@ -229,7 +229,7 @@ status = "okay"; label = "QCA_UART"; - bluetooth: qca6174a { + bluetooth: bluetooth { compatible = "qcom,qca6174-bt"; enable-gpios = <&pm8994_gpios 19 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts index d8734913482f..100123d51494 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts @@ -54,7 +54,7 @@ reg = <0x30>; #address-cells = <1>; #size-cells = <0>; - enable-gpio = <&pm8994_gpios 7 1>; + enable-gpios = <&pm8994_gpios 7 1>; clock-mode = /bits/8 <2>; label = "button-backlight"; @@ -62,14 +62,14 @@ reg = <0>; chan-name = "button-backlight"; led-cur = /bits/ 8 <0x32>; - max-cur = /bits/ 8 <0xC8>; + max-cur = /bits/ 8 <0xc8>; }; led@1 { reg = <0>; chan-name = "button-backlight1"; led-cur = /bits/ 8 <0x32>; - max-cur = /bits/ 8 <0xC8>; + max-cur = /bits/ 8 <0xc8>; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index d31464204f69..905678e7175d 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -462,6 +462,12 @@ reg = <0x0 0x91500000 0x0 0x200000>; no-map; }; + + mdata_mem: mpss-metadata { + alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>; + size = <0x0 0x4000>; + no-map; + }; }; rpm-glink { @@ -477,7 +483,7 @@ compatible = "qcom,rpm-msm8996"; qcom,glink-channels = "rpm_requests"; - rpmcc: qcom,rpmcc { + rpmcc: clock-controller { compatible = "qcom,rpmcc-msm8996", "qcom,rpmcc"; #clock-cells = <1>; clocks = <&xo_board>; @@ -713,14 +719,16 @@ #power-domain-cells = <1>; reg = <0x00300000 0x90000>; - clocks = <&rpmcc RPM_SMD_BB_CLK1>, + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&rpmcc RPM_SMD_LN_BB_CLK>, <&sleep_clk>, <&pciephy_0>, <&pciephy_1>, <&pciephy_2>, <&ssusb_phy_0>, - <0>, <0>, <0>; + <&ufsphy_lane 0>, + <&ufsphy_lane 1>, + <&ufsphy_lane 2>; clock-names = "cxo", "cxo2", "sleep_clk", @@ -830,9 +838,11 @@ compatible = "qcom,msm8996-a2noc"; reg = <0x00583000 0x7000>; #interconnect-cells = <1>; - clock-names = "bus", "bus_a"; + clock-names = "bus", "bus_a", "aggre2_ufs_axi", "ufs_axi"; clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>, - <&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>; + <&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>, + <&gcc GCC_AGGRE2_UFS_AXI_CLK>, + <&gcc GCC_UFS_AXI_CLK>; }; mnoc: interconnect@5a4000 { @@ -904,7 +914,7 @@ <825000000>; }; - mdss: mdss@900000 { + mdss: display-subsystem@900000 { compatible = "qcom,mdss"; reg = <0x00900000 0x1000>, @@ -930,8 +940,8 @@ status = "disabled"; - mdp: mdp@901000 { - compatible = "qcom,mdp5"; + mdp: display-controller@901000 { + compatible = "qcom,msm8996-mdp5", "qcom,mdp5"; reg = <0x00901000 0x90000>; reg-names = "mdp_phys"; @@ -989,7 +999,8 @@ }; dsi0: dsi@994000 { - compatible = "qcom,mdss-dsi-ctrl"; + compatible = "qcom,msm8996-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; reg = <0x00994000 0x400>; reg-names = "dsi_ctrl"; @@ -1050,13 +1061,14 @@ #clock-cells = <1>; #phy-cells = <0>; - clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_BB_CLK1>; + clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; clock-names = "iface", "ref"; status = "disabled"; }; dsi1: dsi@996000 { - compatible = "qcom,mdss-dsi-ctrl"; + compatible = "qcom,msm8996-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; reg = <0x00996000 0x400>; reg-names = "dsi_ctrl"; @@ -1117,7 +1129,7 @@ #clock-cells = <1>; #phy-cells = <0>; - clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_BB_CLK1>; + clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; clock-names = "iface", "ref"; status = "disabled"; }; @@ -1246,23 +1258,23 @@ }; opp-510000000 { opp-hz = /bits/ 64 <510000000>; - opp-supported-hw = <0xFF>; + opp-supported-hw = <0xff>; }; opp-401800000 { opp-hz = /bits/ 64 <401800000>; - opp-supported-hw = <0xFF>; + opp-supported-hw = <0xff>; }; opp-315000000 { opp-hz = /bits/ 64 <315000000>; - opp-supported-hw = <0xFF>; + opp-supported-hw = <0xff>; }; opp-214000000 { opp-hz = /bits/ 64 <214000000>; - opp-supported-hw = <0xFF>; + opp-supported-hw = <0xff>; }; opp-133000000 { opp-hz = /bits/ 64 <133000000>; - opp-supported-hw = <0xFF>; + opp-supported-hw = <0xff>; }; }; @@ -1814,7 +1826,7 @@ #interrupt-cells = <4>; }; - agnoc@0 { + bus@0 { power-domains = <&gcc AGGRE0_NOC_GDSC>; compatible = "simple-pm-bus"; #address-cells = <1>; @@ -2025,6 +2037,10 @@ <0 0>, <0 0>; + interconnects = <&a2noc MASTER_UFS &bimc SLAVE_EBI_CH0>, + <&bimc MASTER_AMPSS_M0 &cnoc SLAVE_UFS_CFG>; + interconnect-names = "ufs-ddr", "cpu-ufs"; + lanes-per-direction = <1>; #reset-cells = <1>; status = "disabled"; @@ -2048,6 +2064,7 @@ reg = <0x627400 0x12c>, <0x627600 0x200>, <0x627c00 0x1b4>; + #clock-cells = <1>; #phy-cells = <0>; }; }; @@ -2458,6 +2475,10 @@ memory-region = <&mpss_mem>; }; + metadata { + memory-region = <&mdata_mem>; + }; + smd-edge { interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; @@ -2940,8 +2961,8 @@ compatible = "qcom,msm8996-apcc"; reg = <0x06400000 0x90000>; - clock-names = "xo"; - clocks = <&rpmcc RPM_SMD_BB_CLK1>; + clock-names = "xo", "sys_apcs_aux"; + clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>, <&apcs_glb>; #clock-cells = <1>; }; @@ -3060,7 +3081,7 @@ clock-names = "iface", "core", "xo"; clocks = <&gcc GCC_SDCC1_AHB_CLK>, <&gcc GCC_SDCC1_APPS_CLK>, - <&rpmcc RPM_SMD_BB_CLK1>; + <&rpmcc RPM_SMD_XO_CLK_SRC>; resets = <&gcc GCC_SDCC1_BCR>; pinctrl-names = "default", "sleep"; @@ -3084,7 +3105,7 @@ clock-names = "iface", "core", "xo"; clocks = <&gcc GCC_SDCC2_AHB_CLK>, <&gcc GCC_SDCC2_APPS_CLK>, - <&rpmcc RPM_SMD_BB_CLK1>; + <&rpmcc RPM_SMD_XO_CLK_SRC>; resets = <&gcc GCC_SDCC2_BCR>; pinctrl-names = "default", "sleep"; @@ -3288,7 +3309,7 @@ status = "disabled"; }; - blsp2_spi6: spi@75ba000{ + blsp2_spi6: spi@75ba000 { compatible = "qcom,spi-qup-v2.2.1"; reg = <0x075ba000 0x600>; interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; @@ -3356,7 +3377,7 @@ slim_msm: slim-ngd@91c0000 { compatible = "qcom,slim-ngd-v1.5.0"; - reg = <0x091c0000 0x2C000>; + reg = <0x091c0000 0x2c000>; interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>; dmas = <&slimbam 3>, <&slimbam 4>; dma-names = "rx", "tx"; @@ -3406,7 +3427,7 @@ interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; - clocks = <&rpmcc RPM_SMD_BB_CLK1>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; clock-names = "xo"; memory-region = <&adsp_mem>; @@ -3426,8 +3447,7 @@ mboxes = <&apcs_glb 8>; qcom,smd-edge = <1>; qcom,remote-pid = <2>; - #address-cells = <1>; - #size-cells = <0>; + apr { power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>; compatible = "qcom,apr-v2"; @@ -3485,6 +3505,7 @@ reg = <0x09820000 0x1000>; #mbox-cells = <1>; + #clock-cells = <0>; }; timer@9840000 { @@ -3551,6 +3572,13 @@ reg = <0x09a10000 0x1000>; }; + cbf: clock-controller@9a11000 { + compatible = "qcom,msm8996-cbf"; + reg = <0x09a11000 0x10000>; + clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>, <&apcs_glb>; + #clock-cells = <0>; + }; + intc: interrupt-controller@9bc0000 { compatible = "qcom,msm8996-gic-v3", "arm,gic-v3"; #interrupt-cells = <3>; @@ -3580,7 +3608,7 @@ type = "passive"; }; - cpu0_crit: cpu_crit { + cpu0_crit: cpu-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -3601,7 +3629,7 @@ type = "passive"; }; - cpu1_crit: cpu_crit { + cpu1_crit: cpu-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -3622,7 +3650,7 @@ type = "passive"; }; - cpu2_crit: cpu_crit { + cpu2_crit: cpu-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -3643,7 +3671,7 @@ type = "passive"; }; - cpu3_crit: cpu_crit { + cpu3_crit: cpu-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; diff --git a/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts b/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts index 310f7a2df1e8..5aad9f05780a 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts @@ -113,7 +113,7 @@ <&cam_snapshot_pin_a>; button-vol-up { label = "Volume Up"; - gpios = <&pm8998_gpio 6 GPIO_ACTIVE_LOW>; + gpios = <&pm8998_gpios 6 GPIO_ACTIVE_LOW>; linux,input-type = <EV_KEY>; linux,code = <KEY_VOLUMEUP>; gpio-key,wakeup; @@ -122,7 +122,7 @@ button-camera-snapshot { label = "Camera Snapshot"; - gpios = <&pm8998_gpio 7 GPIO_ACTIVE_LOW>; + gpios = <&pm8998_gpios 7 GPIO_ACTIVE_LOW>; linux,input-type = <EV_KEY>; linux,code = <KEY_CAMERA>; debounce-interval = <15>; @@ -130,7 +130,7 @@ button-camera-focus { label = "Camera Focus"; - gpios = <&pm8998_gpio 8 GPIO_ACTIVE_LOW>; + gpios = <&pm8998_gpios 8 GPIO_ACTIVE_LOW>; linux,input-type = <EV_KEY>; linux,code = <KEY_CAMERA_FOCUS>; debounce-interval = <15>; @@ -249,7 +249,7 @@ reg = <0x14>; interrupt-parent = <&tlmm>; interrupts = <125 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>; + reset-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>; AVDD28-supply = <&vreg_l28_3p0>; VDDIO-supply = <&ts_vio_vreg>; pinctrl-names = "active"; @@ -338,7 +338,7 @@ }; }; -&pm8998_gpio { +&pm8998_gpios { vol_up_pin_a: vol-up-active-state { pins = "gpio6"; function = "normal"; @@ -364,14 +364,9 @@ }; }; -&pm8998_pon { - resin { - compatible = "qcom,pm8941-resin"; - interrupts = <GIC_SPI 0x8 1 IRQ_TYPE_EDGE_BOTH>; - bias-pull-up; - debounce = <15625>; - linux,code = <KEY_VOLUMEDOWN>; - }; +&pm8998_resin { + linux,code = <KEY_VOLUMEDOWN>; + status = "okay"; }; &qusb2phy { diff --git a/arch/arm64/boot/dts/qcom/msm8998-oneplus-cheeseburger.dts b/arch/arm64/boot/dts/qcom/msm8998-oneplus-cheeseburger.dts index 9fb1fb9b8529..d36b36af49d0 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-oneplus-cheeseburger.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-oneplus-cheeseburger.dts @@ -23,7 +23,7 @@ pinctrl-0 = <&button_backlight_default>; led-keypad-backlight { - gpios = <&pmi8998_gpio 5 GPIO_ACTIVE_HIGH>; + gpios = <&pmi8998_gpios 5 GPIO_ACTIVE_HIGH>; color = <LED_COLOR_ID_WHITE>; function = LED_FUNCTION_KBD_BACKLIGHT; default-state = "off"; @@ -31,7 +31,7 @@ }; }; -&pmi8998_gpio { +&pmi8998_gpios { button_backlight_default: button-backlight-state { pins = "gpio5"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi index 7d4a67d07501..ce03c7c239e5 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi @@ -92,7 +92,7 @@ button-vol-down { label = "Volume down"; - gpios = <&pm8998_gpio 5 GPIO_ACTIVE_LOW>; + gpios = <&pm8998_gpios 5 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEDOWN>; debounce-interval = <15>; wakeup-source; @@ -100,7 +100,7 @@ button-vol-up { label = "Volume up"; - gpios = <&pm8998_gpio 6 GPIO_ACTIVE_LOW>; + gpios = <&pm8998_gpios 6 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEUP>; debounce-interval = <15>; wakeup-source; @@ -269,7 +269,7 @@ }; }; -&pm8998_gpio { +&pm8998_gpios { vol_keys_default: vol-keys-state { pins = "gpio5", "gpio6"; function = "normal"; diff --git a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-maple.dts b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-maple.dts index 20fe0394a3c1..1868ad649415 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-maple.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-maple.dts @@ -20,7 +20,7 @@ regulator-max-microvolt = <1350000>; startup-delay-us = <0>; enable-active-high; - gpio = <&pmi8998_gpio 10 GPIO_ACTIVE_HIGH>; + gpio = <&pmi8998_gpios 10 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&disp_dvdd_en>; }; @@ -37,7 +37,7 @@ qcom,soft-start-us = <200>; }; -&pmi8998_gpio { +&pmi8998_gpios { disp_dvdd_en: disp-dvdd-en-active-state { pins = "gpio10"; function = "normal"; diff --git a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi index 5da87baa2b23..820414758888 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi @@ -25,7 +25,7 @@ pinctrl-names = "default"; clocks = <&rpmcc RPM_SMD_DIV_CLK1>; #clock-cells = <0>; - enable-gpios = <&pm8998_gpio 13 GPIO_ACTIVE_HIGH>; + enable-gpios = <&pm8998_gpios 13 GPIO_ACTIVE_HIGH>; }; }; @@ -65,7 +65,7 @@ regulator-name = "cam_vio_vreg"; startup-delay-us = <0>; enable-active-high; - gpio = <&pmi8998_gpio 1 GPIO_ACTIVE_HIGH>; + gpio = <&pmi8998_gpios 1 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&cam_vio_default>; vin-supply = <&vreg_lvs1a_1p8>; @@ -103,7 +103,7 @@ <&cam_snapshot_pin_a>; button-vol-down { label = "Volume Down"; - gpios = <&pm8998_gpio 5 GPIO_ACTIVE_LOW>; + gpios = <&pm8998_gpios 5 GPIO_ACTIVE_LOW>; linux,input-type = <EV_KEY>; linux,code = <KEY_VOLUMEDOWN>; gpio-key,wakeup; @@ -112,7 +112,7 @@ button-camera-snapshot { label = "Camera Snapshot"; - gpios = <&pm8998_gpio 7 GPIO_ACTIVE_LOW>; + gpios = <&pm8998_gpios 7 GPIO_ACTIVE_LOW>; linux,input-type = <EV_KEY>; linux,code = <KEY_CAMERA>; debounce-interval = <15>; @@ -120,7 +120,7 @@ button-camera-focus { label = "Camera Focus"; - gpios = <&pm8998_gpio 8 GPIO_ACTIVE_LOW>; + gpios = <&pm8998_gpios 8 GPIO_ACTIVE_LOW>; linux,input-type = <EV_KEY>; linux,code = <KEY_CAMERA_FOCUS>; debounce-interval = <15>; @@ -187,7 +187,7 @@ vibrator { compatible = "gpio-vibrator"; - enable-gpios = <&pmi8998_gpio 5 GPIO_ACTIVE_HIGH>; + enable-gpios = <&pmi8998_gpios 5 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&vib_default>; }; @@ -303,7 +303,7 @@ }; }; -&pm8998_gpio { +&pm8998_gpios { vol_down_pin_a: vol-down-active-state { pins = "gpio5"; function = PMIC_GPIO_FUNC_NORMAL; @@ -335,7 +335,7 @@ }; }; -&pmi8998_gpio { +&pmi8998_gpios { cam_vio_default: cam-vio-active-state { pins = "gpio1"; function = PMIC_GPIO_FUNC_NORMAL; @@ -357,14 +357,9 @@ }; }; -&pm8998_pon { - resin { - compatible = "qcom,pm8941-resin"; - interrupts = <GIC_SPI 0x8 1 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; - linux,code = <KEY_VOLUMEUP>; - }; +&pm8998_resin { + linux,code = <KEY_VOLUMEUP>; + status = "okay"; }; &qusb2phy { diff --git a/arch/arm64/boot/dts/qcom/msm8998-xiaomi-sagit.dts b/arch/arm64/boot/dts/qcom/msm8998-xiaomi-sagit.dts index b1aac7311ef9..7956b151c7a4 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-xiaomi-sagit.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-xiaomi-sagit.dts @@ -133,7 +133,7 @@ key-vol-up { label = "Volume up"; - gpios = <&pm8998_gpio 6 GPIO_ACTIVE_LOW>; + gpios = <&pm8998_gpios 6 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEUP>; debounce-interval = <15>; wakeup-source; @@ -278,7 +278,7 @@ }; }; -&pm8998_gpio { +&pm8998_gpios { vol_up_key_default: vol-up-key-default-state { pins = "gpio6"; function = "normal"; diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 539382dab0ad..8bc1c59127e5 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -108,6 +108,12 @@ reg = <0x0 0x95700000 0x0 0x100000>; no-map; }; + + mdata_mem: mpss-metadata { + alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>; + size = <0x0 0x4000>; + no-map; + }; }; clocks { @@ -465,7 +471,7 @@ type = "passive"; }; - cpu0_crit: cpu_crit { + cpu0_crit: cpu-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -486,7 +492,7 @@ type = "passive"; }; - cpu1_crit: cpu_crit { + cpu1_crit: cpu-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -507,7 +513,7 @@ type = "passive"; }; - cpu2_crit: cpu_crit { + cpu2_crit: cpu-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -528,7 +534,7 @@ type = "passive"; }; - cpu3_crit: cpu_crit { + cpu3_crit: cpu-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -549,7 +555,7 @@ type = "passive"; }; - cpu4_crit: cpu_crit { + cpu4_crit: cpu-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -570,7 +576,7 @@ type = "passive"; }; - cpu5_crit: cpu_crit { + cpu5_crit: cpu-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -591,7 +597,7 @@ type = "passive"; }; - cpu6_crit: cpu_crit { + cpu6_crit: cpu-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -612,7 +618,7 @@ type = "passive"; }; - cpu7_crit: cpu_crit { + cpu7_crit: cpu-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -808,7 +814,7 @@ reg = <0x00100000 0xb0000>; clock-names = "xo", "sleep_clk"; - clocks = <&xo>, <&sleep_clk>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; /* * The hypervisor typically configures the memory region where these clocks @@ -1357,6 +1363,10 @@ memory-region = <&mpss_mem>; }; + metadata { + memory-region = <&mdata_mem>; + }; + glink-edge { interrupts = <GIC_SPI 452 IRQ_TYPE_EDGE_RISING>; label = "modem"; @@ -1394,43 +1404,43 @@ opp-710000097 { opp-hz = /bits/ 64 <710000097>; opp-level = <RPM_SMD_LEVEL_TURBO>; - opp-supported-hw = <0xFF>; + opp-supported-hw = <0xff>; }; opp-670000048 { opp-hz = /bits/ 64 <670000048>; opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; - opp-supported-hw = <0xFF>; + opp-supported-hw = <0xff>; }; opp-596000097 { opp-hz = /bits/ 64 <596000097>; opp-level = <RPM_SMD_LEVEL_NOM>; - opp-supported-hw = <0xFF>; + opp-supported-hw = <0xff>; }; opp-515000097 { opp-hz = /bits/ 64 <515000097>; opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; - opp-supported-hw = <0xFF>; + opp-supported-hw = <0xff>; }; opp-414000000 { opp-hz = /bits/ 64 <414000000>; opp-level = <RPM_SMD_LEVEL_SVS>; - opp-supported-hw = <0xFF>; + opp-supported-hw = <0xff>; }; opp-342000000 { opp-hz = /bits/ 64 <342000000>; opp-level = <RPM_SMD_LEVEL_LOW_SVS>; - opp-supported-hw = <0xFF>; + opp-supported-hw = <0xff>; }; opp-257000000 { opp-hz = /bits/ 64 <257000000>; opp-level = <RPM_SMD_LEVEL_MIN_SVS>; - opp-supported-hw = <0xFF>; + opp-supported-hw = <0xff>; }; }; }; @@ -2088,7 +2098,7 @@ clock-names = "iface", "core", "xo"; clocks = <&gcc GCC_SDCC2_AHB_CLK>, <&gcc GCC_SDCC2_APPS_CLK>, - <&xo>; + <&rpmcc RPM_SMD_XO_CLK_SRC>; bus-width = <4>; status = "disabled"; }; @@ -2398,8 +2408,7 @@ "dsi1byte", "hdmipll", "dplink", - "dpvco", - "core_bi_pll_test_se"; + "dpvco"; clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GCC_MMSS_GPLL0_CLK>, <0>, @@ -2408,7 +2417,6 @@ <0>, <0>, <0>, - <0>, <0>; }; diff --git a/arch/arm64/boot/dts/qcom/pm6125.dtsi b/arch/arm64/boot/dts/qcom/pm6125.dtsi index 1c8ccda26ffb..59092a551a16 100644 --- a/arch/arm64/boot/dts/qcom/pm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/pm6125.dtsi @@ -136,11 +136,11 @@ status = "disabled"; }; - pm6125_gpio: gpio@c000 { + pm6125_gpios: gpio@c000 { compatible = "qcom,pm6125-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; - gpio-ranges = <&pm6125_gpio 0 0 9>; + gpio-ranges = <&pm6125_gpios 0 0 9>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; diff --git a/arch/arm64/boot/dts/qcom/pm6150.dtsi b/arch/arm64/boot/dts/qcom/pm6150.dtsi index 3d91fb405ca2..2e6afa296141 100644 --- a/arch/arm64/boot/dts/qcom/pm6150.dtsi +++ b/arch/arm64/boot/dts/qcom/pm6150.dtsi @@ -88,11 +88,11 @@ status = "disabled"; }; - pm6150_gpio: gpio@c000 { + pm6150_gpios: gpio@c000 { compatible = "qcom,pm6150-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; - gpio-ranges = <&pm6150_gpio 0 0 10>; + gpio-ranges = <&pm6150_gpios 0 0 10>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; diff --git a/arch/arm64/boot/dts/qcom/pm6150l.dtsi b/arch/arm64/boot/dts/qcom/pm6150l.dtsi index 90aac61ad264..6f7aa67501e2 100644 --- a/arch/arm64/boot/dts/qcom/pm6150l.dtsi +++ b/arch/arm64/boot/dts/qcom/pm6150l.dtsi @@ -95,11 +95,11 @@ status = "disabled"; }; - pm6150l_gpio: gpio@c000 { + pm6150l_gpios: gpio@c000 { compatible = "qcom,pm6150l-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; - gpio-ranges = <&pm6150l_gpio 0 0 12>; + gpio-ranges = <&pm6150l_gpios 0 0 12>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; @@ -112,6 +112,12 @@ #address-cells = <1>; #size-cells = <0>; + pm6150l_flash: led-controller@d300 { + compatible = "qcom,pm6150l-flash-led", "qcom,spmi-flash-led"; + reg = <0xd300>; + status = "disabled"; + }; + pm6150l_wled: leds@d800 { compatible = "qcom,pm6150l-wled"; reg = <0xd800>, <0xd900>; diff --git a/arch/arm64/boot/dts/qcom/pm7250b.dtsi b/arch/arm64/boot/dts/qcom/pm7250b.dtsi index 61f7a6345150..d709d955a2f5 100644 --- a/arch/arm64/boot/dts/qcom/pm7250b.dtsi +++ b/arch/arm64/boot/dts/qcom/pm7250b.dtsi @@ -110,6 +110,14 @@ label = "chg_mid"; }; + adc-chan@4b { + reg = <ADC5_BAT_ID_100K_PU>; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,ratiometric; + label = "bat_id"; + }; + adc-chan@83 { reg = <ADC5_VPH_PWR>; qcom,pre-scaling = <1 3>; diff --git a/arch/arm64/boot/dts/qcom/pm8005.dtsi b/arch/arm64/boot/dts/qcom/pm8005.dtsi index 8d4b081b4e9d..0f0ab2da8305 100644 --- a/arch/arm64/boot/dts/qcom/pm8005.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8005.dtsi @@ -11,11 +11,11 @@ #address-cells = <1>; #size-cells = <0>; - pm8005_gpio: gpio@c000 { + pm8005_gpios: gpio@c000 { compatible = "qcom,pm8005-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; - gpio-ranges = <&pm8005_gpio 0 0 4>; + gpio-ranges = <&pm8005_gpios 0 0 4>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; diff --git a/arch/arm64/boot/dts/qcom/pm8010.dtsi b/arch/arm64/boot/dts/qcom/pm8010.dtsi new file mode 100644 index 000000000000..0ea641e12209 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pm8010.dtsi @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Linaro Limited + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/spmi/spmi.h> + +/ { + thermal-zones { + pm8010-m-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + + thermal-sensors = <&pm8010_m_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + }; + + pm8010-n-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + + thermal-sensors = <&pm8010_n_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + }; + }; +}; + + +&spmi_bus { + pm8010_m: pmic@c { + compatible = "qcom,pm8010", "qcom,spmi-pmic"; + reg = <0xc SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8010_m_temp_alarm: temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0xc 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + }; + + pm8010_n: pmic@d { + compatible = "qcom,pm8010", "qcom,spmi-pmic"; + reg = <0xd SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8010_n_temp_alarm: temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0xd 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/pm8150.dtsi b/arch/arm64/boot/dts/qcom/pm8150.dtsi index 574fa95a2871..db90c55fa2cf 100644 --- a/arch/arm64/boot/dts/qcom/pm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8150.dtsi @@ -121,7 +121,7 @@ rtc@6000 { compatible = "qcom,pm8941-rtc"; - reg = <0x6000>; + reg = <0x6000>, <0x6100>; reg-names = "rtc", "alarm"; interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; }; diff --git a/arch/arm64/boot/dts/qcom/pm8550.dtsi b/arch/arm64/boot/dts/qcom/pm8550.dtsi new file mode 100644 index 000000000000..46396ec1a330 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pm8550.dtsi @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Linaro Limited + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/spmi/spmi.h> + +/ { + thermal-zones { + pm8550-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + + thermal-sensors = <&pm8550_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + }; + }; +}; + + +&spmi_bus { + pm8550: pmic@1 { + compatible = "qcom,pm8550", "qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8550_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pm8550_gpios: gpio@8800 { + compatible = "qcom,pm8550-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pm8550_gpios 0 0 12>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/pm8550b.dtsi b/arch/arm64/boot/dts/qcom/pm8550b.dtsi new file mode 100644 index 000000000000..16bcfb64d735 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pm8550b.dtsi @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Linaro Limited + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/spmi/spmi.h> + +/ { + thermal-zones { + pm8550b-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + + thermal-sensors = <&pm8550b_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + }; + }; +}; + + +&spmi_bus { + pm8550b: pmic@7 { + compatible = "qcom,pm8550", "qcom,spmi-pmic"; + reg = <0x7 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8550b_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x7 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pm8550b_gpios: gpio@8800 { + compatible = "qcom,pm8550b-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pm8550b_gpios 0 0 12>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/pm8550ve.dtsi b/arch/arm64/boot/dts/qcom/pm8550ve.dtsi new file mode 100644 index 000000000000..c47646a467be --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pm8550ve.dtsi @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Linaro Limited + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/spmi/spmi.h> + +/ { + thermal-zones { + pm8550ve-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + + thermal-sensors = <&pm8550ve_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + }; + }; +}; + + +&spmi_bus { + pm8550ve: pmic@5 { + compatible = "qcom,pm8550", "qcom,spmi-pmic"; + reg = <0x5 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8550ve_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x5 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pm8550ve_gpios: gpio@8800 { + compatible = "qcom,pm8550ve-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pm8550ve_gpios 0 0 8>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/pm8550vs.dtsi b/arch/arm64/boot/dts/qcom/pm8550vs.dtsi new file mode 100644 index 000000000000..97b1c18aa7d8 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pm8550vs.dtsi @@ -0,0 +1,194 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Linaro Limited + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/spmi/spmi.h> + +/ { + thermal-zones { + pm8550vs-c-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + + thermal-sensors = <&pm8550vs_c_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + }; + + pm8550vs-d-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + + thermal-sensors = <&pm8550vs_d_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + }; + + pm8550vs-e-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + + thermal-sensors = <&pm8550vs_e_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + }; + + pm8550vs-g-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + + thermal-sensors = <&pm8550vs_g_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + }; + }; +}; + + +&spmi_bus { + pm8550vs_c: pmic@2 { + compatible = "qcom,pm8550", "qcom,spmi-pmic"; + reg = <0x2 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8550vs_c_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pm8550vs_c_gpios: gpio@8800 { + compatible = "qcom,pm8550vs-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pm8550vs_c_gpios 0 0 6>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pm8550vs_d: pmic@3 { + compatible = "qcom,pm8550", "qcom,spmi-pmic"; + reg = <0x3 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8550vs_d_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x3 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pm8550vs_d_gpios: gpio@8800 { + compatible = "qcom,pm8550vs-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pm8550vs_d_gpios 0 0 6>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pm8550vs_e: pmic@4 { + compatible = "qcom,pm8550", "qcom,spmi-pmic"; + reg = <0x4 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8550vs_e_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pm8550vs_e_gpios: gpio@8800 { + compatible = "qcom,pm8550vs-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pm8550vs_e_gpios 0 0 6>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pm8550vs_g: pmic@6 { + compatible = "qcom,pm8550", "qcom,spmi-pmic"; + reg = <0x6 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8550vs_g_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x6 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pm8550vs_g_gpios: gpio@8800 { + compatible = "qcom,pm8550vs-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pm8550vs_g_gpios 0 0 6>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/pm8916.dtsi b/arch/arm64/boot/dts/qcom/pm8916.dtsi index 08f9ca006e72..e2a6b66d8847 100644 --- a/arch/arm64/boot/dts/qcom/pm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8916.dtsi @@ -93,7 +93,8 @@ rtc@6000 { compatible = "qcom,pm8941-rtc"; - reg = <0x6000>; + reg = <0x6000>, <0x6100>; + reg-names = "rtc", "alarm"; interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; }; diff --git a/arch/arm64/boot/dts/qcom/pm8950.dtsi b/arch/arm64/boot/dts/qcom/pm8950.dtsi index 07c3896bd36f..5ec38b7e335a 100644 --- a/arch/arm64/boot/dts/qcom/pm8950.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8950.dtsi @@ -126,7 +126,7 @@ rtc@6000 { compatible = "qcom,pm8941-rtc"; - reg = <0x6000>; + reg = <0x6000>, <0x6100>; reg-names = "rtc", "alarm"; interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; }; @@ -141,11 +141,11 @@ #interrupt-cells = <2>; }; - pm8950_gpio: gpio@c000 { + pm8950_gpios: gpio@c000 { compatible = "qcom,pm8950-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; - gpio-ranges = <&pm8950_gpio 0 0 8>; + gpio-ranges = <&pm8950_gpios 0 0 8>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; diff --git a/arch/arm64/boot/dts/qcom/pm8998.dtsi b/arch/arm64/boot/dts/qcom/pm8998.dtsi index 6a5854333b2b..adbba9f4089a 100644 --- a/arch/arm64/boot/dts/qcom/pm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8998.dtsi @@ -109,11 +109,11 @@ interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; }; - pm8998_gpio: gpio@c000 { + pm8998_gpios: gpio@c000 { compatible = "qcom,pm8998-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; - gpio-ranges = <&pm8998_gpio 0 0 26>; + gpio-ranges = <&pm8998_gpios 0 0 26>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; diff --git a/arch/arm64/boot/dts/qcom/pmi8950.dtsi b/arch/arm64/boot/dts/qcom/pmi8950.dtsi index 32d27e2187e3..4891be3cd68a 100644 --- a/arch/arm64/boot/dts/qcom/pmi8950.dtsi +++ b/arch/arm64/boot/dts/qcom/pmi8950.dtsi @@ -47,7 +47,7 @@ adc-chan@a { reg = <VADC_REF_1250MV>; qcom,pre-scaling = <1 1>; - label = "ref_1250v"; + label = "ref_1250mv"; }; adc-chan@d { @@ -67,11 +67,11 @@ #interrupt-cells = <2>; }; - pmi8950_gpio: gpio@c000 { + pmi8950_gpios: gpio@c000 { compatible = "qcom,pmi8950-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; - gpio-ranges = <&pmi8950_gpio 0 0 2>; + gpio-ranges = <&pmi8950_gpios 0 0 2>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; diff --git a/arch/arm64/boot/dts/qcom/pmi8998.dtsi b/arch/arm64/boot/dts/qcom/pmi8998.dtsi index cd1caeae8281..ffe587f281d8 100644 --- a/arch/arm64/boot/dts/qcom/pmi8998.dtsi +++ b/arch/arm64/boot/dts/qcom/pmi8998.dtsi @@ -9,11 +9,11 @@ #address-cells = <1>; #size-cells = <0>; - pmi8998_gpio: gpio@c000 { + pmi8998_gpios: gpio@c000 { compatible = "qcom,pmi8998-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; - gpio-ranges = <&pmi8998_gpio 0 0 14>; + gpio-ranges = <&pmi8998_gpios 0 0 14>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; diff --git a/arch/arm64/boot/dts/qcom/pmk8350.dtsi b/arch/arm64/boot/dts/qcom/pmk8350.dtsi index 32f5e6af8c11..f26fb7d32faf 100644 --- a/arch/arm64/boot/dts/qcom/pmk8350.dtsi +++ b/arch/arm64/boot/dts/qcom/pmk8350.dtsi @@ -21,7 +21,7 @@ #size-cells = <0>; pmk8350_pon: pon@1300 { - compatible = "qcom,pm8998-pon"; + compatible = "qcom,pmk8350-pon"; reg = <0x1300>, <0x800>; reg-names = "hlos", "pbs"; diff --git a/arch/arm64/boot/dts/qcom/pmk8550.dtsi b/arch/arm64/boot/dts/qcom/pmk8550.dtsi new file mode 100644 index 000000000000..201efeda7d2d --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pmk8550.dtsi @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Linaro Limited + */ + +#include <dt-bindings/input/input.h> +#include <dt-bindings/input/linux-event-codes.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/spmi/spmi.h> + +&spmi_bus { + pmk8550: pmic@0 { + compatible = "qcom,pm8550", "qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmk8550_pon: pon@1300 { + compatible = "qcom,pmk8350-pon"; + reg = <0x1300>, <0x800>; + reg-names = "hlos", "pbs"; + + pon_pwrkey: pwrkey { + compatible = "qcom,pmk8350-pwrkey"; + interrupts = <0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH>; + linux,code = <KEY_POWER>; + status = "disabled"; + }; + + pon_resin: resin { + compatible = "qcom,pmk8350-resin"; + interrupts = <0x0 0x13 0x6 IRQ_TYPE_EDGE_BOTH>; + status = "disabled"; + }; + }; + + pmk8550_rtc: rtc@6100 { + compatible = "qcom,pmk8350-rtc"; + reg = <0x6100>, <0x6200>; + reg-names = "rtc", "alarm"; + interrupts = <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; + }; + + pmk8550_gpios: gpio@8800 { + compatible = "qcom,pmk8550-gpio", "qcom,spmi-gpio"; + reg = <0xb800>; + gpio-controller; + gpio-ranges = <&pmk8550_gpios 0 0 6>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi b/arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi index 20c5d60c8c2c..ee1e428d3a6e 100644 --- a/arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi +++ b/arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi @@ -108,7 +108,7 @@ pmm8155au_1_rtc: rtc@6000 { compatible = "qcom,pm8941-rtc"; - reg = <0x6000>; + reg = <0x6000>, <0x6100>; reg-names = "rtc", "alarm"; interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; diff --git a/arch/arm64/boot/dts/qcom/pmp8074.dtsi b/arch/arm64/boot/dts/qcom/pmp8074.dtsi index ceb2e6358b3d..580684411d74 100644 --- a/arch/arm64/boot/dts/qcom/pmp8074.dtsi +++ b/arch/arm64/boot/dts/qcom/pmp8074.dtsi @@ -74,7 +74,7 @@ pmp8074_rtc: rtc@6000 { compatible = "qcom,pm8941-rtc"; - reg = <0x6000>; + reg = <0x6000>, <0x6100>; reg-names = "rtc", "alarm"; interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; allow-set-time; diff --git a/arch/arm64/boot/dts/qcom/pmr735d.dtsi b/arch/arm64/boot/dts/qcom/pmr735d.dtsi new file mode 100644 index 000000000000..41fb664a10b3 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pmr735d.dtsi @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Linaro Limited + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/spmi/spmi.h> + +/ { + thermal-zones { + pmr735d-k-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + + thermal-sensors = <&pmr735d_k_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + }; + + pmr735d-l-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + + thermal-sensors = <&pmr735d_l_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + }; + }; +}; + + +&spmi_bus { + pmr735d_k: pmic@a { + compatible = "qcom,pmr735d", "qcom,spmi-pmic"; + reg = <0xa SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmr735d_k_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0xa 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmr735d_k_gpios: gpio@8800 { + compatible = "qcom,pmr735d-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmr735d_k_gpios 0 0 2>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pmr735d_l: pmic@b { + compatible = "qcom,pmr735d", "qcom,spmi-pmic"; + reg = <0xb SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmr735d_l_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0xb 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmr735d_l_gpios: gpio@8800 { + compatible = "qcom,pmr735d-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmr735d_l_gpios 0 0 2>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/pms405.dtsi b/arch/arm64/boot/dts/qcom/pms405.dtsi index ffe9e33808d0..22edb47c6a84 100644 --- a/arch/arm64/boot/dts/qcom/pms405.dtsi +++ b/arch/arm64/boot/dts/qcom/pms405.dtsi @@ -125,7 +125,7 @@ rtc@6000 { compatible = "qcom,pm8941-rtc"; - reg = <0x6000>; + reg = <0x6000>, <0x6100>; reg-names = "rtc", "alarm"; interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; }; diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index a5324eecb50a..bc2ed73afb74 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -223,13 +223,15 @@ qcom,rpm-msg-ram = <&rpm_msg_ram>; mboxes = <&apcs_glb 0>; - rpm_requests: glink-channel { + rpm_requests: rpm-requests { compatible = "qcom,rpm-qcs404"; qcom,glink-channels = "rpm_requests"; rpmcc: clock-controller { compatible = "qcom,rpmcc-qcs404", "qcom,rpmcc"; #clock-cells = <1>; + clocks = <&xo_board>; + clock-names = "xo"; }; rpmpd: power-controller { @@ -366,13 +368,126 @@ reg = <0x000a4000 0x1000>; #address-cells = <1>; #size-cells = <1>; - tsens_caldata: caldata@d0 { - reg = <0x1f8 0x14>; - }; cpr_efuse_speedbin: speedbin@13c { reg = <0x13c 0x4>; bits = <2 3>; }; + + tsens_s0_p1: s0-p1@1f8 { + reg = <0x1f8 0x1>; + bits = <0 6>; + }; + + tsens_s0_p2: s0-p2@1f8 { + reg = <0x1f8 0x2>; + bits = <6 6>; + }; + + tsens_s1_p1: s1-p1@1f9 { + reg = <0x1f9 0x2>; + bits = <4 6>; + }; + + tsens_s1_p2: s1-p2@1fa { + reg = <0x1fa 0x1>; + bits = <2 6>; + }; + + tsens_s2_p1: s2-p1@1fb { + reg = <0x1fb 0x1>; + bits = <0 6>; + }; + + tsens_s2_p2: s2-p2@1fb { + reg = <0x1fb 0x2>; + bits = <6 6>; + }; + + tsens_s3_p1: s3-p1@1fc { + reg = <0x1fc 0x2>; + bits = <4 6>; + }; + + tsens_s3_p2: s3-p2@1fd { + reg = <0x1fd 0x1>; + bits = <2 6>; + }; + + tsens_s4_p1: s4-p1@1fe { + reg = <0x1fe 0x1>; + bits = <0 6>; + }; + + tsens_s4_p2: s4-p2@1fe { + reg = <0x1fe 0x2>; + bits = <6 6>; + }; + + tsens_s5_p1: s5-p1@200 { + reg = <0x200 0x1>; + bits = <0 6>; + }; + + tsens_s5_p2: s5-p2@200 { + reg = <0x200 0x2>; + bits = <6 6>; + }; + + tsens_s6_p1: s6-p1@201 { + reg = <0x201 0x2>; + bits = <4 6>; + }; + + tsens_s6_p2: s6-p2@202 { + reg = <0x202 0x1>; + bits = <2 6>; + }; + + tsens_s7_p1: s7-p1@203 { + reg = <0x203 0x1>; + bits = <0 6>; + }; + + tsens_s7_p2: s7-p2@203 { + reg = <0x203 0x2>; + bits = <6 6>; + }; + + tsens_s8_p1: s8-p1@204 { + reg = <0x204 0x2>; + bits = <4 6>; + }; + + tsens_s8_p2: s8-p2@205 { + reg = <0x205 0x1>; + bits = <2 6>; + }; + + tsens_s9_p1: s9-p1@206 { + reg = <0x206 0x1>; + bits = <0 6>; + }; + + tsens_s9_p2: s9-p2@206 { + reg = <0x206 0x2>; + bits = <6 6>; + }; + + tsens_mode: mode@208 { + reg = <0x208 1>; + bits = <0 3>; + }; + + tsens_base1: base1@208 { + reg = <0x208 2>; + bits = <3 8>; + }; + + tsens_base2: base2@208 { + reg = <0x209 2>; + bits = <3 8>; + }; + cpr_efuse_quot_offset1: qoffset1@231 { reg = <0x231 0x4>; bits = <4 7>; @@ -447,8 +562,30 @@ compatible = "qcom,qcs404-tsens", "qcom,tsens-v1"; reg = <0x004a9000 0x1000>, /* TM */ <0x004a8000 0x1000>; /* SROT */ - nvmem-cells = <&tsens_caldata>; - nvmem-cell-names = "calib"; + nvmem-cells = <&tsens_mode>, + <&tsens_base1>, <&tsens_base2>, + <&tsens_s0_p1>, <&tsens_s0_p2>, + <&tsens_s1_p1>, <&tsens_s1_p2>, + <&tsens_s2_p1>, <&tsens_s2_p2>, + <&tsens_s3_p1>, <&tsens_s3_p2>, + <&tsens_s4_p1>, <&tsens_s4_p2>, + <&tsens_s5_p1>, <&tsens_s5_p2>, + <&tsens_s6_p1>, <&tsens_s6_p2>, + <&tsens_s7_p1>, <&tsens_s7_p2>, + <&tsens_s8_p1>, <&tsens_s8_p2>, + <&tsens_s9_p1>, <&tsens_s9_p2>; + nvmem-cell-names = "mode", + "base1", "base2", + "s0_p1", "s0_p2", + "s1_p1", "s1_p2", + "s2_p1", "s2_p2", + "s3_p1", "s3_p2", + "s4_p1", "s4_p2", + "s5_p1", "s5_p2", + "s6_p1", "s6_p2", + "s7_p1", "s7_p2", + "s8_p1", "s8_p2", + "s9_p1", "s9_p2"; #qcom,sensors = <10>; interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "uplow"; @@ -485,27 +622,31 @@ interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; - clocks = <&xo_board>, - <&gcc GCC_CDSP_CFG_AHB_CLK>, - <&gcc GCC_CDSP_TBU_CLK>, - <&gcc GCC_BIMC_CDSP_CLK>, - <&turingcc TURING_WRAPPER_AON_CLK>, - <&turingcc TURING_Q6SS_AHBS_AON_CLK>, - <&turingcc TURING_Q6SS_AHBM_AON_CLK>, - <&turingcc TURING_Q6SS_Q6_AXIM_CLK>; - clock-names = "xo", - "sway", - "tbu", - "bimc", - "ahb_aon", - "q6ss_slave", - "q6ss_master", - "q6_axim"; - - resets = <&gcc GCC_CDSP_RESTART>; - reset-names = "restart"; - - qcom,halt-regs = <&tcsr 0x19004>; + clocks = <&xo_board>; + clock-names = "xo"; + + /* + * If the node was using the PIL binding, then include properties: + * clocks = <&xo_board>, + * <&gcc GCC_CDSP_CFG_AHB_CLK>, + * <&gcc GCC_CDSP_TBU_CLK>, + * <&gcc GCC_BIMC_CDSP_CLK>, + * <&turingcc TURING_WRAPPER_AON_CLK>, + * <&turingcc TURING_Q6SS_AHBS_AON_CLK>, + * <&turingcc TURING_Q6SS_AHBM_AON_CLK>, + * <&turingcc TURING_Q6SS_Q6_AXIM_CLK>; + * clock-names = "xo", + * "sway", + * "tbu", + * "bimc", + * "ahb_aon", + * "q6ss_slave", + * "q6ss_master", + * "q6_axim"; + * resets = <&gcc GCC_CDSP_RESTART>; + * reset-names = "restart"; + * qcom,halt-regs = <&tcsr 0x19004>; + */ memory-region = <&cdsp_fw_mem>; @@ -729,6 +870,14 @@ reg = <0x01800000 0x80000>; #clock-cells = <1>; #reset-cells = <1>; + #power-domain-cells = <1>; + + clocks = <&xo_board>, + <&sleep_clk>, + <&pcie_phy>, + <0>, + <0>, + <0>; assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>; assigned-clock-rates = <19200000>; @@ -806,10 +955,11 @@ clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>, - <&gcc 21>; + <&gcc GCC_PCIE_0_PIPE_ARES>; reset-names = "phy", "pipe"; clock-output-names = "pcie_0_pipe_clk"; + #clock-cells = <0>; #phy-cells = <0>; status = "disabled"; @@ -1336,12 +1486,12 @@ <&gcc GCC_PCIE_0_SLV_AXI_CLK>; clock-names = "iface", "aux", "master_bus", "slave_bus"; - resets = <&gcc 18>, - <&gcc 17>, - <&gcc 15>, - <&gcc 19>, + resets = <&gcc GCC_PCIE_0_AXI_MASTER_ARES>, + <&gcc GCC_PCIE_0_AXI_SLAVE_ARES>, + <&gcc GCC_PCIE_0_AXI_MASTER_STICKY_ARES>, + <&gcc GCC_PCIE_0_CORE_STICKY_ARES>, <&gcc GCC_PCIE_0_BCR>, - <&gcc 16>; + <&gcc GCC_PCIE_0_AHB_ARES>; reset-names = "axi_m", "axi_s", "axi_m_sticky", @@ -1502,7 +1652,7 @@ hysteresis = <2000>; type = "passive"; }; - cluster_crit: cluster_crit { + cluster_crit: cluster-crit { temperature = <120000>; hysteresis = <2000>; type = "critical"; @@ -1536,7 +1686,7 @@ hysteresis = <2000>; type = "passive"; }; - cpu0_crit: cpu_crit { + cpu0_crit: cpu-crit { temperature = <120000>; hysteresis = <2000>; type = "critical"; @@ -1570,7 +1720,7 @@ hysteresis = <2000>; type = "passive"; }; - cpu1_crit: cpu_crit { + cpu1_crit: cpu-crit { temperature = <120000>; hysteresis = <2000>; type = "critical"; @@ -1604,7 +1754,7 @@ hysteresis = <2000>; type = "passive"; }; - cpu2_crit: cpu_crit { + cpu2_crit: cpu-crit { temperature = <120000>; hysteresis = <2000>; type = "critical"; @@ -1638,7 +1788,7 @@ hysteresis = <2000>; type = "passive"; }; - cpu3_crit: cpu_crit { + cpu3_crit: cpu-crit { temperature = <120000>; hysteresis = <2000>; type = "critical"; diff --git a/arch/arm64/boot/dts/qcom/qdu1000-idp.dts b/arch/arm64/boot/dts/qcom/qdu1000-idp.dts new file mode 100644 index 000000000000..9e9fd4b8023e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qdu1000-idp.dts @@ -0,0 +1,453 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> +#include "qdu1000.dtsi" +#include "pm8150.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. QDU1000 IDP"; + compatible = "qcom,qdu1000-idp", "qcom,qdu1000"; + chassis-type = "embedded"; + + aliases { + serial0 = &uart7; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + clocks { + xo_board: xo-board-clk { + compatible = "fixed-clock"; + clock-frequency = <19200000>; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32000>; + #clock-cells = <0>; + }; + }; + + ppvar_sys: ppvar-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "ppvar_sys"; + regulator-min-microvolt = <4200000>; + regulator-max-microvolt = <4200000>; + + regulator-always-on; + regulator-boot-on; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + + vin-supply = <&ppvar_sys>; + }; +}; + +&apps_rsc { + regulators { + compatible = "qcom,pm8150-rpmh-regulators"; + qcom,pmic-id = "a"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + + vdd-l1-l8-l11-supply = <&vreg_s6a_0p9>; + vdd-l2-l10-supply = <&vph_pwr>; + vdd-l3-l4-l5-l18-supply = <&vreg_s5a_2p0>; + vdd-l6-l9-supply = <&vreg_s6a_0p9>; + vdd-l7-l12-l14-l15-supply = <&vreg_s4a_1p8>; + vdd-l13-l16-l17-supply = <&vph_pwr>; + + vreg_s2a_0p5: smps2 { + regulator-name = "vreg_s2a_0p5"; + regulator-min-microvolt = <320000>; + regulator-max-microvolt = <570000>; + }; + + vreg_s3a_1p05: smps3 { + regulator-name = "vreg_s3a_1p05"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1170000>; + }; + + vreg_s4a_1p8: smps4 { + regulator-name = "vreg_s4a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vreg_s5a_2p0: smps5 { + regulator-name = "vreg_s5a_2p0"; + regulator-min-microvolt = <1904000>; + regulator-max-microvolt = <2000000>; + }; + + vreg_s6a_0p9: smps6 { + regulator-name = "vreg_s6a_0p9"; + regulator-min-microvolt = <920000>; + regulator-max-microvolt = <1128000>; + }; + + vreg_s7a_1p2: smps7 { + regulator-name = "vreg_s7a_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vreg_s8a_1p3: smps8 { + regulator-name = "vreg_s8a_1p3"; + regulator-min-microvolt = <1352000>; + regulator-max-microvolt = <1352000>; + }; + + vreg_l1a_0p91: ldo1 { + regulator-name = "vreg_l1a_0p91"; + regulator-min-microvolt = <312000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l2a_2p3: ldo2 { + regulator-name = "vreg_l2a_2p3"; + regulator-min-microvolt = <2970000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l3a_1p2: ldo3 { + regulator-name = "vreg_l3a_1p2"; + regulator-min-microvolt = <920000>; + regulator-max-microvolt = <1260000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l5a_0p8: ldo5 { + regulator-name = "vreg_l5a_0p8"; + regulator-min-microvolt = <312000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l6a_0p91: ldo6 { + regulator-name = "vreg_l6a_0p91"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <950000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l7a_1p8: ldo7 { + regulator-name = "vreg_l7a_1p8"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + + }; + + vreg_l8a_0p91: ldo8 { + regulator-name = "vreg_l8a_0p91"; + regulator-min-microvolt = <888000>; + regulator-max-microvolt = <925000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l9a_0p91: ldo9 { + regulator-name = "vreg_l9a_0p91"; + regulator-min-microvolt = <312000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l10a_2p95: ldo10 { + regulator-name = "vreg_l10a_2p95"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l11a_0p91: ldo11 { + regulator-name = "vreg_l11a_0p91"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l12a_1p8: ldo12 { + regulator-name = "vreg_l12a_1p8"; + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <1504000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l14a_1p8: ldo14 { + regulator-name = "vreg_l14a_1p8"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1950000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l15a_1p8: ldo15 { + regulator-name = "vreg_l15a_1p8"; + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l16a_1p8: ldo16 { + regulator-name = "vreg_l16a_1p8"; + regulator-min-microvolt = <1710000>; + regulator-max-microvolt = <1890000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l17a_3p3: ldo17 { + regulator-name = "vreg_l17a_3p3"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l18a_1p2: ldo18 { + regulator-name = "vreg_l18a_1p2"; + regulator-min-microvolt = <312000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + }; +}; + +&qup_i2c1_data_clk { + drive-strength = <2>; + bias-pull-up; +}; + +&qup_i2c2_data_clk { + drive-strength = <2>; + bias-pull-up; +}; + +&qup_i2c3_data_clk { + drive-strength = <2>; + bias-pull-up; +}; + +&qup_i2c4_data_clk { + drive-strength = <2>; + bias-pull-up; +}; + +&qup_i2c5_data_clk { + drive-strength = <2>; + bias-pull-up; +}; + +&qup_i2c6_data_clk { + drive-strength = <2>; + bias-pull-up; +}; + +&qup_i2c9_data_clk { + drive-strength = <2>; + bias-pull-up; +}; + +&qup_i2c10_data_clk { + drive-strength = <2>; + bias-pull-up; +}; + +&qup_i2c11_data_clk { + drive-strength = <2>; + bias-pull-up; +}; + +&qup_i2c12_data_clk { + drive-strength = <2>; + bias-pull-up; +}; + +&qup_i2c13_data_clk { + drive-strength = <2>; + bias-pull-up; +}; + +&qup_i2c14_data_clk { + drive-strength = <2>; + bias-pull-up; +}; + +&qup_i2c15_data_clk { + drive-strength = <2>; + bias-pull-up; +}; + +&qup_spi1_cs { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi1_data_clk { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi2_cs { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi2_data_clk { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi3_cs { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi3_data_clk { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi4_cs { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi4_data_clk { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi5_cs { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi5_data_clk { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi6_cs { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi6_data_clk { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi9_cs { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi9_data_clk { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi10_cs { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi10_data_clk { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi11_cs { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi11_data_clk { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi12_cs { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi12_data_clk { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi13_cs { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi13_data_clk { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi14_cs { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi14_data_clk { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi15_cs { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi15_data_clk { + drive-strength = <6>; + bias-disable; +}; + +&qup_uart7_rx { + drive-strength = <2>; + bias-disable; +}; + +&qup_uart7_tx { + drive-strength = <2>; + bias-disable; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&uart7 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi new file mode 100644 index 000000000000..f234159d2060 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi @@ -0,0 +1,1333 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include <dt-bindings/clock/qcom,qdu1000-gcc.h> +#include <dt-bindings/clock/qcom,rpmh.h> +#include <dt-bindings/dma/qcom-gpi.h> +#include <dt-bindings/interconnect/qcom,qdu1000-rpmh.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/power/qcom-rpmpd.h> +#include <dt-bindings/soc/qcom,rpmh-rsc.h> + +/ { + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + chosen: chosen { }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x0>; + enable-method = "psci"; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; + qcom,freq-domains = <&cpufreq_hw 0>; + next-level-cache = <&L2_0>; + L2_0: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + L3_0: l3-cache { + compatible = "cache"; + }; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x100>; + enable-method = "psci"; + power-domains = <&CPU_PD1>; + power-domain-names = "psci"; + qcom,freq-domains = <&cpufreq_hw 0>; + next-level-cache = <&L2_100>; + L2_100: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x200>; + enable-method = "psci"; + power-domains = <&CPU_PD2>; + power-domain-names = "psci"; + qcom,freq-domains = <&cpufreq_hw 0>; + next-level-cache = <&L2_200>; + L2_200: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x300>; + enable-method = "psci"; + power-domains = <&CPU_PD3>; + power-domain-names = "psci"; + qcom,freq-domains = <&cpufreq_hw 0>; + next-level-cache = <&L2_300>; + L2_300: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + }; + }; + }; + + idle-states { + entry-method = "psci"; + + CPU_OFF: cpu-sleep-0 { + compatible = "arm,idle-state"; + entry-latency-us = <274>; + exit-latency-us = <480>; + min-residency-us = <3934>; + arm,psci-suspend-param = <0x40000004>; + local-timer-stop; + }; + }; + + domain-idle-states { + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "domain-idle-state"; + entry-latency-us = <584>; + exit-latency-us = <2332>; + min-residency-us = <6118>; + arm,psci-suspend-param = <0x41000044>; + }; + + CLUSTER_SLEEP_1: cluster-sleep-1 { + compatible = "domain-idle-state"; + entry-latency-us = <2893>; + exit-latency-us = <4023>; + min-residency-us = <9987>; + arm,psci-suspend-param = <0x41003344>; + }; + }; + + firmware { + scm { + compatible = "qcom,scm-qdu1000", "qcom,scm"; + }; + }; + + mc_virt: interconnect-0 { + compatible = "qcom,qdu1000-mc-virt"; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + clk_virt: interconnect-1 { + compatible = "qcom,qdu1000-clk-virt"; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0x0 0x80000000 0x0 0x0>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + + CPU_PD0: power-domain-cpu0 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&CPU_OFF>; + }; + + CPU_PD1: power-domain-cpu1 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&CPU_OFF>; + }; + + CPU_PD2: power-domain-cpu2 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&CPU_OFF>; + }; + + CPU_PD3: power-domain-cpu3 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&CPU_OFF>; + }; + + CLUSTER_PD: power-domain-cluster { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_1>; + }; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_mem: hyp@80000000 { + reg = <0x0 0x80000000 0x0 0x600000>; + no-map; + }; + + xbl_dt_log_mem: xbl-dt-log@80600000 { + reg = <0x0 0x80600000 0x0 0x40000>; + no-map; + }; + + xbl_ramdump_mem: xbl-ramdump@80640000 { + reg = <0x0 0x80640000 0x0 0x1c0000>; + no-map; + }; + + aop_image_mem: aop-image@80800000 { + reg = <0x0 0x80800000 0x0 0x60000>; + no-map; + }; + + aop_cmd_db_mem: aop-cmd-db@80860000 { + compatible = "qcom,cmd-db"; + reg = <0x0 0x80860000 0x0 0x20000>; + no-map; + }; + + aop_config_mem: aop-config@80880000 { + reg = <0x0 0x80880000 0x0 0x20000>; + no-map; + }; + + tme_crash_dump_mem: tme-crash-dump@808a0000 { + reg = <0x0 0x808a0000 0x0 0x40000>; + no-map; + }; + + tme_log_mem: tme-log@808e0000 { + reg = <0x0 0x808e0000 0x0 0x4000>; + no-map; + }; + + uefi_log_mem: uefi-log@808e4000 { + reg = <0x0 0x808e4000 0x0 0x10000>; + no-map; + }; + + smem_mem: smem@80900000 { + compatible = "qcom,smem"; + reg = <0x0 0x80900000 0x0 0x200000>; + no-map; + hwlocks = <&tcsr_mutex 3>; + }; + + cpucp_fw_mem: cpucp-fw@80b00000 { + reg = <0x0 0x80b00000 0x0 0x100000>; + no-map; + }; + + xbl_sc_mem: memory@80c00000 { + reg = <0x0 0x80c00000 0x0 0x40000>; + no-map; + }; + + tz_stat_mem: tz-stat@81d00000 { + reg = <0x0 0x81d00000 0x0 0x100000>; + no-map; + }; + + tags_mem: tags@81e00000 { + reg = <0x0 0x81e00000 0x0 0x500000>; + no-map; + }; + + qtee_mem: qtee@82300000 { + reg = <0x0 0x82300000 0x0 0x500000>; + no-map; + }; + + ta_mem: ta@82800000 { + reg = <0x0 0x82800000 0x0 0xa00000>; + no-map; + }; + + fs1_mem: fs1@83200000 { + reg = <0x0 0x83200000 0x0 0x400000>; + no-map; + }; + + fs2_mem: fs2@83600000 { + reg = <0x0 0x83600000 0x0 0x400000>; + no-map; + }; + + fs3_mem: fs3@83a00000 { + reg = <0x0 0x83a00000 0x0 0x400000>; + no-map; + }; + + /* Linux kernel image is loaded at 0x83e00000 */ + + ipa_fw_mem: ipa-fw@8be00000 { + reg = <0x0 0x8be00000 0x0 0x10000>; + no-map; + }; + + ipa_gsi_mem: ipa-gsi@8be10000 { + reg = <0x0 0x8be10000 0x0 0x14000>; + no-map; + }; + + mpss_mem: mpss@8c000000 { + reg = <0x0 0x8c000000 0x0 0x12c00000>; + no-map; + }; + + q6_mpss_dtb_mem: q6-mpss-dtb@9ec00000 { + reg = <0x0 0x9ec00000 0x0 0x80000>; + no-map; + }; + + tenx_mem: tenx@a0000000 { + reg = <0x0 0xa0000000 0x0 0x19600000>; + no-map; + }; + + oem_tenx_mem: oem-tenx@b9600000 { + reg = <0x0 0xb9600000 0x0 0x6a00000>; + no-map; + }; + + tenx_q6_buffer_mem: tenx-q6-buffer@c0000000 { + reg = <0x0 0xc0000000 0x0 0x3200000>; + no-map; + }; + + ipa_buffer_mem: ipa-buffer@c3200000 { + reg = <0x0 0xc3200000 0x0 0x12c00000>; + no-map; + }; + }; + + soc: soc@0 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0 0 0 0x10 0>; + dma-ranges = <0 0 0 0 0x10 0>; + + gcc: clock-controller@80000 { + compatible = "qcom,qdu1000-gcc"; + reg = <0x0 0x80000 0x0 0x1f4200>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, + <0>, + <0>, + <0>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + gpi_dma0: dma-controller@900000 { + compatible = "qcom,qdu1000-gpi-dma", "qcom,sm6350-gpi-dma"; + reg = <0x0 0x900000 0x0 0x60000>; + interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; + dma-channels = <12>; + dma-channel-mask = <0x3f>; + iommus = <&apps_smmu 0xf6 0x0>; + #dma-cells = <3>; + }; + + qupv3_id_0: geniqup@9c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x9c0000 0x0 0x2000>; + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + clock-names = "m-ahb", "s-ahb"; + iommus = <&apps_smmu 0xe3 0x0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 + &clk_virt SLAVE_QUP_CORE_0 0>; + interconnect-names = "qup-core"; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + uart0: serial@980000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x980000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_uart0_default>; + pinctrl-names = "default"; + interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@984000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x984000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&qup_i2c1_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@984000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x984000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; + pinctrl-names = "default"; + status = "disabled"; + }; + + i2c2: i2c@988000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x988000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&qup_i2c2_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@988000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x988000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; + pinctrl-names = "default"; + status = "disabled"; + }; + + i2c3: i2c@98c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x98c000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&qup_i2c3_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi3: spi@98c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x98c000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; + pinctrl-names = "default"; + status = "disabled"; + }; + + i2c4: i2c@990000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x990000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&qup_i2c4_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi4: spi@990000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x990000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; + pinctrl-names = "default"; + status = "disabled"; + }; + + i2c5: i2c@994000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x994000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&qup_i2c5_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi5: spi@994000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x994000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; + pinctrl-names = "default"; + status = "disabled"; + }; + + i2c6: i2c@998000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x998000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&qup_i2c6_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi6: spi@998000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x998000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; + pinctrl-names = "default"; + status = "disabled"; + }; + + uart7: serial@99c000 { + compatible = "qcom,geni-debug-uart"; + reg = <0x0 0x99c000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; + pinctrl-names = "default"; + interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + gpi_dma1: dma-controller@a00000 { + compatible = "qcom,qdu1000-gpi-dma", "qcom,sm6350-gpi-dma"; + reg = <0x0 0xa00000 0x0 0x60000>; + interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; + dma-channels = <12>; + dma-channel-mask = <0x3f>; + iommus = <&apps_smmu 0x116 0x0>; + #dma-cells = <3>; + }; + + qupv3_id_1: geniqup@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0xac0000 0x0 0x2000>; + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + clock-names = "m-ahb", "s-ahb"; + iommus = <&apps_smmu 0x103 0x0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + uart8: serial@a80000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0xa80000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_uart8_default>; + pinctrl-names = "default"; + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c9: i2c@a84000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0xa84000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&qup_i2c9_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi9: spi@a84000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0xa84000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; + pinctrl-names = "default"; + status = "disabled"; + }; + + i2c10: i2c@a88000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0xa88000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&qup_i2c10_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi10: spi@a88000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0xa88000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; + pinctrl-names = "default"; + status = "disabled"; + }; + + i2c11: i2c@a8c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0xa8c000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&qup_i2c11_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi11: spi@a8c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0xa8c000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; + pinctrl-names = "default"; + status = "disabled"; + }; + + i2c12: i2c@a90000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0xa90000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&qup_i2c12_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi12: spi@a90000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0xa90000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; + pinctrl-names = "default"; + status = "disabled"; + }; + + i2c13: i2c@a94000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0xa94000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&qup_i2c13_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart13: serial@a94000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0xa94000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_uart13_default>; + pinctrl-names = "default"; + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi13: spi@a94000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0xa94000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; + pinctrl-names = "default"; + status = "disabled"; + }; + + i2c14: i2c@a98000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0xa98000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&qup_i2c14_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi14: spi@a98000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0xa98000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; + pinctrl-names = "default"; + status = "disabled"; + }; + + i2c15: i2c@a9c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0xa9c000 0x0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&qup_i2c15_data_clk>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi15: spi@a9c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0xa9c000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + system_noc: interconnect@1640000 { + compatible = "qcom,qdu1000-system-noc"; + reg = <0x0 0x1640000 0x0 0x45080>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x0 0x1f40000 0x0 0x20000>; + #hwlock-cells = <1>; + }; + + pdc: interrupt-controller@b220000 { + compatible = "qcom,qdu1000-pdc", "qcom,pdc"; + reg = <0x0 0xb220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>; + qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>, + <94 609 31>, <125 63 1>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + + spmi_bus: spmi@c400000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x0 0xc400000 0x0 0x3000>, + <0x0 0xc500000 0x0 0x400000>, + <0x0 0xc440000 0x0 0x80000>, + <0x0 0xc4c0000 0x0 0x10000>, + <0x0 0xc42d000 0x0 0x4000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "periph_irq"; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + }; + + tlmm: pinctrl@f000000 { + compatible = "qcom,qdu1000-tlmm"; + reg = <0x0 0xf000000 0x0 0x1000000>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 151>; + wakeup-parent = <&pdc>; + + qup_uart0_default: qup-uart0-default-state { + pins = "gpio6", "gpio7", "gpio8", "gpio9"; + function = "qup00"; + }; + + qup_i2c1_data_clk: qup-i2c1-data-clk-state { + pins = "gpio10", "gpio11"; + function = "qup01"; + }; + + qup_spi1_data_clk: qup-spi1-data-clk-state { + pins = "gpio10", "gpio11", "gpio12"; + function = "qup01"; + }; + + qup_spi1_cs: qup-spi1-cs-state { + pins = "gpio13"; + function = "gpio"; + }; + + qup_i2c2_data_clk: qup-i2c2-data-clk-state { + pins = "gpio12", "gpio13"; + function = "qup02"; + }; + + qup_spi2_data_clk: qup-spi2-data-clk-state { + pins = "gpio12", "gpio13", "gpio10"; + function = "qup02"; + }; + + qup_spi2_cs: qup-spi2-cs-state { + pins = "gpio11"; + function = "gpio"; + }; + + qup_i2c3_data_clk: qup-i2c3-data-clk-state { + pins = "gpio14", "gpio15"; + function = "qup03"; + }; + + qup_spi3_data_clk: qup-spi3-data-clk-state { + pins = "gpio14", "gpio15", "gpio16"; + function = "qup03"; + }; + + qup_spi3_cs: qup-spi3-cs-state { + pins = "gpio17"; + function = "gpio"; + }; + + qup_i2c4_data_clk: qup-i2c4-data-clk-state { + pins = "gpio16", "gpio17"; + function = "qup04"; + }; + + qup_spi4_data_clk: qup-spi4-data-clk-state { + pins = "gpio16", "gpio17", "gpio14"; + function = "qup04"; + }; + + qup_spi4_cs: qup-spi4-cs-state { + pins = "gpio15"; + function = "gpio"; + }; + + qup_i2c5_data_clk: qup-i2c5-data-clk-state { + pins = "gpio130", "gpio131"; + function = "qup05"; + }; + + qup_spi5_data_clk: qup-spi5-data-clk-state { + pins = "gpio130", "gpio131", "gpio132"; + function = "qup05"; + }; + + qup_spi5_cs: qup-spi5-cs-state { + pins = "gpio133"; + function = "gpio"; + }; + + qup_i2c6_data_clk: qup-i2c6-data-clk-state { + pins = "gpio132", "gpio133"; + function = "qup06"; + }; + + qup_spi6_data_clk: qup-spi6-data-clk-state { + pins = "gpio132", "gpio133", "gpio130"; + function = "qup06"; + }; + + qup_spi6_cs: qup-spi6-cs-state { + pins = "gpio131"; + function = "gpio"; + }; + + qup_uart7_rx: qup-uart7-rx-state { + pins = "gpio135"; + function = "qup07"; + }; + + qup_uart7_tx: qup-uart7-tx-state { + pins = "gpio134"; + function = "qup07"; + }; + + qup_uart8_default: qup-uart8-default-state { + pins = "gpio18", "gpio19", "gpio20", "gpio21"; + function = "qup10"; + }; + + qup_i2c9_data_clk: qup-i2c9-data-clk-state { + pins = "gpio22", "gpio23"; + function = "qup11"; + }; + + qup_spi9_data_clk: qup-spi9-data-clk-state { + pins = "gpio22", "gpio23", "gpio24"; + function = "qup11"; + }; + + qup_spi9_cs: qup-spi9-cs-state { + pins = "gpio25"; + function = "gpio"; + }; + + qup_i2c10_data_clk: qup-i2c10-data-clk-state { + pins = "gpio24", "gpio25"; + function = "qup12"; + }; + + qup_spi10_data_clk: qup-spi10-data-clk-state { + pins = "gpio24", "gpio25", "gpio22"; + function = "qup12"; + }; + + qup_spi10_cs: qup-spi10-cs-state { + pins = "gpio23"; + function = "gpio"; + }; + + qup_i2c11_data_clk: qup-i2c11-data-clk-state { + pins = "gpio26", "gpio27"; + function = "qup13"; + }; + + qup_spi11_data_clk: qup-spi11-data-clk-state { + pins = "gpio26", "gpio27", "gpio28"; + function = "qup13"; + }; + + qup_spi11_cs: qup-spi11-cs-state { + pins = "gpio29"; + function = "gpio"; + }; + + qup_i2c12_data_clk: qup-i2c12-data-clk-state { + pins = "gpio28", "gpio29"; + function = "qup14"; + }; + + qup_spi12_data_clk: qup-spi12-data-clk-state { + pins = "gpio28", "gpio29", "gpio26"; + function = "qup14"; + }; + + qup_spi12_cs: qup-spi12-cs-state { + pins = "gpio27"; + function = "gpio"; + }; + + qup_i2c13_data_clk: qup-i2c13-data-clk-state { + pins = "gpio30", "gpio31"; + function = "qup15"; + }; + + qup_spi13_data_clk: qup-spi13-data-clk-state { + pins = "gpio30", "gpio31", "gpio32"; + function = "qup15"; + }; + + qup_spi13_cs: qup-spi13-cs-state { + pins = "gpio33"; + function = "gpio"; + }; + + qup_uart13_default: qup-uart13-default-state { + pins = "gpio30", "gpio31", "gpio32", "gpio33"; + function = "qup15"; + }; + + qup_i2c14_data_clk: qup-i2c14-data-clk-state { + pins = "gpio34", "gpio35"; + function = "qup16"; + }; + + qup_spi14_data_clk: qup-spi14-data-clk-state { + pins = "gpio34", "gpio35", "gpio36"; + function = "qup16"; + }; + + qup_spi14_cs: qup-spi14-cs-state { + pins = "gpio37", "gpio38"; + function = "gpio"; + }; + + qup_i2c15_data_clk: qup-i2c15-data-clk-state { + pins = "gpio40", "gpio41"; + function = "qup17"; + }; + + qup_spi15_data_clk: qup-spi15-data-clk-state { + pins = "gpio40", "gpio41", "gpio30"; + function = "qup17"; + }; + + qup_spi15_cs: qup-spi15-cs-state { + pins = "gpio31"; + function = "gpio"; + }; + }; + + apps_smmu: iommu@15000000 { + compatible = "qcom,qdu1000-smmu-500", "arm,mmu-500"; + reg = <0x0 0x15000000 0x0 0x100000>; + #iommu-cells = <2>; + #global-interrupts = <2>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; + }; + + intc: interrupt-controller@17200000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x17200000 0x0 0x10000>, /* GICD */ + <0x0 0x17260000 0x0 0x80000>; /* GICR * 4 */ + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; + #interrupt-cells = <3>; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + }; + + timer@17420000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x17420000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x20000000>; + + frame@17421000 { + reg = <0x17421000 0x1000>, + <0x17422000 0x1000>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + frame-number = <0>; + }; + + frame@17423000 { + reg = <0x17423000 0x1000>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + frame-number = <1>; + status = "disabled"; + }; + + frame@17425000 { + reg = <0x17425000 0x1000>, + <0x17426000 0x1000>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + frame-number = <2>; + status = "disabled"; + }; + + frame@17427000 { + reg = <0x17427000 0x1000>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + frame-number = <3>; + status = "disabled"; + }; + + frame@17429000 { + reg = <0x17429000 0x1000>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + frame-number = <4>; + status = "disabled"; + }; + + frame@1742b000 { + reg = <0x1742b000 0x1000>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + frame-number = <5>; + status = "disabled"; + }; + + frame@1742d000 { + reg = <0x1742d000 0x1000>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + frame-number = <6>; + status = "disabled"; + }; + }; + + apps_rsc: rsc@17a00000 { + compatible = "qcom,rpmh-rsc"; + reg = <0x0 0x17a00000 0x0 0x10000>, + <0x0 0x17a10000 0x0 0x10000>, + <0x0 0x17a20000 0x0 0x10000>; + reg-names = "drv-0", "drv-1", "drv-2"; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <2>; + qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, + <WAKE_TCS 3>, <CONTROL_TCS 0>; + label = "apps_rsc"; + + apps_bcm_voter: bcm-voter { + compatible = "qcom,bcm-voter"; + }; + + rpmhcc: clock-controller { + compatible = "qcom,qdu1000-rpmh-clk"; + clocks = <&xo_board>; + clock-names = "xo"; + #clock-cells = <1>; + }; + + rpmhpd: power-controller { + compatible = "qcom,qdu1000-rpmhpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmhpd_opp_table>; + + rpmhpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmhpd_opp_ret: opp1 { + opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; + }; + + rpmhpd_opp_min_svs: opp2 { + opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; + }; + + rpmhpd_opp_low_svs: opp3 { + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; + }; + + rpmhpd_opp_svs: opp4 { + opp-level = <RPMH_REGULATOR_LEVEL_SVS>; + }; + + rpmhpd_opp_svs_l1: opp5 { + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; + }; + + rpmhpd_opp_nom: opp6 { + opp-level = <RPMH_REGULATOR_LEVEL_NOM>; + }; + + rpmhpd_opp_nom_l1: opp7 { + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; + }; + + rpmhpd_opp_nom_l2: opp8 { + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; + }; + + rpmhpd_opp_turbo: opp9 { + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; + }; + + rpmhpd_opp_turbo_l1: opp10 { + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; + }; + }; + }; + }; + + cpufreq_hw: cpufreq@17d90000 { + compatible = "qcom,qdu1000-cpufreq-epss", "qcom,cpufreq-epss"; + reg = <0x0 0x17d90000 0x0 0x1000>, <0x0 0x17d91000 0x0 0x1000>; + reg-names = "freq-domain0", "freq-domain1"; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + #freq-domain-cells = <1>; + }; + + gem_noc: interconnect@19100000 { + compatible = "qcom,qdu1000-gem-noc"; + reg = <0x0 0x19100000 0x0 0xB8080>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index 8c64cb060e21..aa0a7bd7307c 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -238,7 +238,7 @@ }; &apps_rsc { - pm8009-rpmh-regulators { + regulators-0 { compatible = "qcom,pm8009-1-rpmh-regulators"; qcom,pmic-id = "f"; @@ -284,7 +284,7 @@ }; }; - pm8150-rpmh-regulators { + regulators-1 { compatible = "qcom,pm8150-rpmh-regulators"; qcom,pmic-id = "a"; @@ -417,7 +417,7 @@ }; }; - pm8150l-rpmh-regulators { + regulators-2 { compatible = "qcom,pm8150l-rpmh-regulators"; qcom,pmic-id = "c"; @@ -1007,6 +1007,8 @@ }; &swr0 { + status = "okay"; + left_spkr: speaker@0,3 { compatible = "sdw10217211000"; reg = <0 3>; @@ -1322,6 +1324,10 @@ status = "okay"; }; +&wsamacro { + status = "okay"; +}; + /* PINCTRL - additions to nodes defined in sm8250.dtsi */ &qup_spi0_cs_gpio { drive-strength = <6>; diff --git a/arch/arm64/boot/dts/qcom/qru1000-idp.dts b/arch/arm64/boot/dts/qcom/qru1000-idp.dts new file mode 100644 index 000000000000..2cc893ae4d10 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qru1000-idp.dts @@ -0,0 +1,453 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> +#include "qru1000.dtsi" +#include "pm8150.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. QRU1000 IDP"; + compatible = "qcom,qru1000-idp", "qcom,qru1000"; + chassis-type = "embedded"; + + aliases { + serial0 = &uart7; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + clocks { + xo_board: xo-board-clk { + compatible = "fixed-clock"; + clock-frequency = <19200000>; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32000>; + #clock-cells = <0>; + }; + }; + + ppvar_sys: ppvar-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "ppvar_sys"; + regulator-min-microvolt = <4200000>; + regulator-max-microvolt = <4200000>; + + regulator-always-on; + regulator-boot-on; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + + vin-supply = <&ppvar_sys>; + }; +}; + +&apps_rsc { + regulators { + compatible = "qcom,pm8150-rpmh-regulators"; + qcom,pmic-id = "a"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + + vdd-l1-l8-l11-supply = <&vreg_s6a_0p9>; + vdd-l2-l10-supply = <&vph_pwr>; + vdd-l3-l4-l5-l18-supply = <&vreg_s5a_2p0>; + vdd-l6-l9-supply = <&vreg_s6a_0p9>; + vdd-l7-l12-l14-l15-supply = <&vreg_s4a_1p8>; + vdd-l13-l16-l17-supply = <&vph_pwr>; + + vreg_s2a_0p5: smps2 { + regulator-name = "vreg_s2a_0p5"; + regulator-min-microvolt = <320000>; + regulator-max-microvolt = <570000>; + }; + + vreg_s3a_1p05: smps3 { + regulator-name = "vreg_s3a_1p05"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1170000>; + }; + + vreg_s4a_1p8: smps4 { + regulator-name = "vreg_s4a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vreg_s5a_2p0: smps5 { + regulator-name = "vreg_s5a_2p0"; + regulator-min-microvolt = <1904000>; + regulator-max-microvolt = <2000000>; + }; + + vreg_s6a_0p9: smps6 { + regulator-name = "vreg_s6a_0p9"; + regulator-min-microvolt = <920000>; + regulator-max-microvolt = <1128000>; + }; + + vreg_s7a_1p2: smps7 { + regulator-name = "vreg_s7a_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vreg_s8a_1p3: smps8 { + regulator-name = "vreg_s8a_1p3"; + regulator-min-microvolt = <1352000>; + regulator-max-microvolt = <1352000>; + }; + + vreg_l1a_0p91: ldo1 { + regulator-name = "vreg_l1a_0p91"; + regulator-min-microvolt = <312000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l2a_2p3: ldo2 { + regulator-name = "vreg_l2a_2p3"; + regulator-min-microvolt = <2970000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l3a_1p2: ldo3 { + regulator-name = "vreg_l3a_1p2"; + regulator-min-microvolt = <920000>; + regulator-max-microvolt = <1260000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l5a_0p8: ldo5 { + regulator-name = "vreg_l5a_0p8"; + regulator-min-microvolt = <312000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l6a_0p91: ldo6 { + regulator-name = "vreg_l6a_0p91"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <950000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l7a_1p8: ldo7 { + regulator-name = "vreg_l7a_1p8"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + + }; + + vreg_l8a_0p91: ldo8 { + regulator-name = "vreg_l8a_0p91"; + regulator-min-microvolt = <888000>; + regulator-max-microvolt = <925000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l9a_0p91: ldo9 { + regulator-name = "vreg_l9a_0p91"; + regulator-min-microvolt = <312000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l10a_2p95: ldo10 { + regulator-name = "vreg_l10a_2p95"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l11a_0p91: ldo11 { + regulator-name = "vreg_l11a_0p91"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l12a_1p8: ldo12 { + regulator-name = "vreg_l12a_1p8"; + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <1504000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l14a_1p8: ldo14 { + regulator-name = "vreg_l14a_1p8"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1950000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l15a_1p8: ldo15 { + regulator-name = "vreg_l15a_1p8"; + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l16a_1p8: ldo16 { + regulator-name = "vreg_l16a_1p8"; + regulator-min-microvolt = <1710000>; + regulator-max-microvolt = <1890000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l17a_3p3: ldo17 { + regulator-name = "vreg_l17a_3p3"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + + vreg_l18a_1p2: ldo18 { + regulator-name = "vreg_l18a_1p2"; + regulator-min-microvolt = <312000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>; + }; + }; +}; + +&qup_i2c1_data_clk { + drive-strength = <2>; + bias-pull-up; +}; + +&qup_i2c2_data_clk { + drive-strength = <2>; + bias-pull-up; +}; + +&qup_i2c3_data_clk { + drive-strength = <2>; + bias-pull-up; +}; + +&qup_i2c4_data_clk { + drive-strength = <2>; + bias-pull-up; +}; + +&qup_i2c5_data_clk { + drive-strength = <2>; + bias-pull-up; +}; + +&qup_i2c6_data_clk { + drive-strength = <2>; + bias-pull-up; +}; + +&qup_i2c9_data_clk { + drive-strength = <2>; + bias-pull-up; +}; + +&qup_i2c10_data_clk { + drive-strength = <2>; + bias-pull-up; +}; + +&qup_i2c11_data_clk { + drive-strength = <2>; + bias-pull-up; +}; + +&qup_i2c12_data_clk { + drive-strength = <2>; + bias-pull-up; +}; + +&qup_i2c13_data_clk { + drive-strength = <2>; + bias-pull-up; +}; + +&qup_i2c14_data_clk { + drive-strength = <2>; + bias-pull-up; +}; + +&qup_i2c15_data_clk { + drive-strength = <2>; + bias-pull-up; +}; + +&qup_spi1_cs { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi1_data_clk { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi2_cs { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi2_data_clk { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi3_cs { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi3_data_clk { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi4_cs { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi4_data_clk { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi5_cs { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi5_data_clk { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi6_cs { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi6_data_clk { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi9_cs { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi9_data_clk { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi10_cs { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi10_data_clk { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi11_cs { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi11_data_clk { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi12_cs { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi12_data_clk { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi13_cs { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi13_data_clk { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi14_cs { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi14_data_clk { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi15_cs { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi15_data_clk { + drive-strength = <6>; + bias-disable; +}; + +&qup_uart7_rx { + drive-strength = <2>; + bias-disable; +}; + +&qup_uart7_tx { + drive-strength = <2>; + bias-disable; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&uart7 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/qru1000.dtsi b/arch/arm64/boot/dts/qcom/qru1000.dtsi new file mode 100644 index 000000000000..eac5dc54a8ab --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qru1000.dtsi @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "qdu1000.dtsi" +/delete-node/ &tenx_mem; +/delete-node/ &oem_tenx_mem; +/delete-node/ &tenx_q6_buffer_mem; + +&reserved_memory { + oem_tenx_mem: oem-tenx@a0000000 { + reg = <0x0 0xa0000000 0x0 0x6400000>; + no-map; + }; + + mpss_diag_buffer_mem: mpss-diag-buffer@aea00000 { + reg = <0x0 0xaea00000 0x0 0x6400000>; + no-map; + }; + + tenx_q6_buffer_mem: tenx-q6-buffer@b4e00000 { + reg = <0x0 0xb4e00000 0x0 0x3200000>; + no-map; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts index f41dcc379dce..459384ec8f23 100644 --- a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts +++ b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts @@ -23,7 +23,7 @@ stdout-path = "serial0:115200n8"; }; - vreg_3p3: vreg_3p3_regulator { + vreg_3p3: vreg-3p3-regulator { compatible = "regulator-fixed"; regulator-name = "vreg_3p3"; regulator-min-microvolt = <3300000>; @@ -72,7 +72,7 @@ }; &apps_rsc { - pmm8155au-1-rpmh-regulators { + regulators-0 { compatible = "qcom,pmm8155au-rpmh-regulators"; qcom,pmic-id = "a"; @@ -201,7 +201,7 @@ }; }; - pmm8155au-2-rpmh-regulators { + regulators-1 { compatible = "qcom,pmm8155au-rpmh-regulators"; qcom,pmic-id = "c"; diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts index 84cb6f3eeb56..fd253942e5e5 100644 --- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts +++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts @@ -11,22 +11,107 @@ #include <dt-bindings/spmi/spmi.h> #include "sa8540p.dtsi" +#include "sa8540p-pmics.dtsi" / { model = "Qualcomm SA8295P ADP"; compatible = "qcom,sa8295p-adp", "qcom,sa8540p"; aliases { - serial0 = &qup2_uart17; + serial0 = &uart17; }; chosen { stdout-path = "serial0:115200n8"; }; + + dp2-connector { + compatible = "dp-connector"; + label = "DP2"; + type = "mini"; + + hpd-gpios = <&tlmm 20 GPIO_ACTIVE_HIGH>; + + port { + dp2_connector_in: endpoint { + remote-endpoint = <&mdss1_dp0_phy_out>; + }; + }; + }; + + dp3-connector { + compatible = "dp-connector"; + label = "DP3"; + type = "mini"; + + hpd-gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>; + + port { + dp3_connector_in: endpoint { + remote-endpoint = <&mdss1_dp1_phy_out>; + }; + }; + }; + + edp0-connector { + compatible = "dp-connector"; + label = "EDP0"; + type = "mini"; + + hpd-gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>; + + port { + edp0_connector_in: endpoint { + remote-endpoint = <&mdss0_dp2_phy_out>; + }; + }; + }; + + edp1-connector { + compatible = "dp-connector"; + label = "EDP1"; + type = "mini"; + + hpd-gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>; + + port { + edp1_connector_in: endpoint { + remote-endpoint = <&mdss0_dp3_phy_out>; + }; + }; + }; + + edp2-connector { + compatible = "dp-connector"; + label = "EDP2"; + type = "mini"; + + hpd-gpios = <&tlmm 7 GPIO_ACTIVE_HIGH>; + + port { + edp2_connector_in: endpoint { + remote-endpoint = <&mdss1_dp2_phy_out>; + }; + }; + }; + + edp3-connector { + compatible = "dp-connector"; + label = "EDP3"; + type = "mini"; + + hpd-gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>; + + port { + edp3_connector_in: endpoint { + remote-endpoint = <&mdss1_dp3_phy_out>; + }; + }; + }; }; &apps_rsc { - pmm8540-a-regulators { + regulators-0 { compatible = "qcom,pm8150-rpmh-regulators"; qcom,pmic-id = "a"; @@ -66,7 +151,7 @@ }; }; - pmm8540-c-regulators { + regulators-1 { compatible = "qcom,pm8150-rpmh-regulators"; qcom,pmic-id = "c"; @@ -139,7 +224,7 @@ }; }; - pmm8540-g-regulators { + regulators-2 { compatible = "qcom,pm8150-rpmh-regulators"; qcom,pmic-id = "g"; @@ -159,13 +244,168 @@ vreg_l8g: ldo8 { regulator-name = "vreg_l8g"; - regulator-min-microvolt = <880000>; - regulator-max-microvolt = <880000>; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; + + vreg_l11g: ldo11 { + regulator-name = "vreg_l11g"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; +}; + +&dispcc0 { + status = "okay"; +}; + +&dispcc1 { + status = "okay"; +}; + +&mdss0 { + status = "okay"; +}; + +&mdss0_dp2 { + data-lanes = <0 1 2 3>; + + status = "okay"; + + ports { + port@1 { + reg = <1>; + mdss0_dp2_phy_out: endpoint { + remote-endpoint = <&edp0_connector_in>; + }; + }; }; }; +&mdss0_dp2_phy { + vdda-phy-supply = <&vreg_l8g>; + vdda-pll-supply = <&vreg_l3g>; + + status = "okay"; +}; + +&mdss0_dp3 { + data-lanes = <0 1 2 3>; + + status = "okay"; + + ports { + port@1 { + reg = <1>; + mdss0_dp3_phy_out: endpoint { + remote-endpoint = <&edp1_connector_in>; + }; + }; + }; +}; + +&mdss0_dp3_phy { + vdda-phy-supply = <&vreg_l8g>; + vdda-pll-supply = <&vreg_l3g>; + + status = "okay"; +}; + +&mdss1 { + status = "okay"; +}; + +&mdss1_dp0 { + data-lanes = <0 1 2 3>; + + status = "okay"; + + ports { + port@1 { + reg = <1>; + mdss1_dp0_phy_out: endpoint { + remote-endpoint = <&dp2_connector_in>; + }; + }; + }; +}; + +&mdss1_dp0_phy { + vdda-phy-supply = <&vreg_l11g>; + vdda-pll-supply = <&vreg_l3g>; + + status = "okay"; +}; + +&mdss1_dp1 { + data-lanes = <0 1 2 3>; + + status = "okay"; + + ports { + port@1 { + reg = <1>; + mdss1_dp1_phy_out: endpoint { + remote-endpoint = <&dp3_connector_in>; + }; + }; + }; +}; + +&mdss1_dp1_phy { + vdda-phy-supply = <&vreg_l11g>; + vdda-pll-supply = <&vreg_l3g>; + + status = "okay"; +}; + +&mdss1_dp2 { + data-lanes = <0 1 2 3>; + + status = "okay"; + + ports { + port@1 { + reg = <1>; + mdss1_dp2_phy_out: endpoint { + remote-endpoint = <&edp2_connector_in>; + }; + }; + }; +}; + +&mdss1_dp2_phy { + vdda-phy-supply = <&vreg_l11g>; + vdda-pll-supply = <&vreg_l3g>; + + status = "okay"; +}; + +&mdss1_dp3 { + data-lanes = <0 1 2 3>; + + status = "okay"; + + ports { + port@1 { + reg = <1>; + mdss1_dp3_phy_out: endpoint { + remote-endpoint = <&edp3_connector_in>; + }; + }; + }; +}; + +&mdss1_dp3_phy { + vdda-phy-supply = <&vreg_l11g>; + vdda-pll-supply = <&vreg_l3g>; + + status = "okay"; +}; + &pcie2a { perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; @@ -240,11 +480,6 @@ status = "okay"; }; -&qup2_uart17 { - compatible = "qcom,geni-debug-uart"; - status = "okay"; -}; - &remoteproc_adsp { firmware-name = "qcom/sa8540p/adsp.mbn"; status = "okay"; @@ -260,82 +495,9 @@ status = "okay"; }; -&spmi_bus { - pm8450a: pmic@0 { - compatible = "qcom,pm8150", "qcom,spmi-pmic"; - reg = <0x0 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - rtc@6000 { - compatible = "qcom,pm8941-rtc"; - reg = <0x6000>; - reg-names = "rtc", "alarm"; - interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; - wakeup-source; - }; - - pm8450a_gpios: gpio@c000 { - compatible = "qcom,pm8150-gpio", "qcom,spmi-gpio"; - reg = <0xc000>; - gpio-controller; - gpio-ranges = <&pm8450a_gpios 0 0 10>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - pm8450c: pmic@4 { - compatible = "qcom,pm8150", "qcom,spmi-pmic"; - reg = <0x4 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - pm8450c_gpios: gpio@c000 { - compatible = "qcom,pm8150-gpio", "qcom,spmi-gpio"; - reg = <0xc000>; - gpio-controller; - gpio-ranges = <&pm8450c_gpios 0 0 10>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - pm8450e: pmic@8 { - compatible = "qcom,pm8150", "qcom,spmi-pmic"; - reg = <0x8 SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - pm8450e_gpios: gpio@c000 { - compatible = "qcom,pm8150-gpio", "qcom,spmi-gpio"; - reg = <0xc000>; - gpio-controller; - gpio-ranges = <&pm8450e_gpios 0 0 10>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - pm8450g: pmic@c { - compatible = "qcom,pm8150", "qcom,spmi-pmic"; - reg = <0xc SPMI_USID>; - #address-cells = <1>; - #size-cells = <0>; - - pm8450g_gpios: gpio@c000 { - compatible = "qcom,pm8150-gpio", "qcom,spmi-gpio"; - reg = <0xc000>; - gpio-controller; - gpio-ranges = <&pm8450g_gpios 0 0 10>; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; +&uart17 { + compatible = "qcom,geni-debug-uart"; + status = "okay"; }; &ufs_mem_hc { diff --git a/arch/arm64/boot/dts/qcom/pm8450a.dtsi b/arch/arm64/boot/dts/qcom/sa8540p-pmics.dtsi index 34fc72896761..1221be89b3de 100644 --- a/arch/arm64/boot/dts/qcom/pm8450a.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8540p-pmics.dtsi @@ -4,71 +4,80 @@ * Copyright (c) 2022, Linaro Limited */ +#include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/spmi/spmi.h> &spmi_bus { - pm8450a: pmic@0 { + pmm8540a: pmic@0 { compatible = "qcom,pm8150", "qcom,spmi-pmic"; reg = <0x0 SPMI_USID>; #address-cells = <1>; #size-cells = <0>; - pm8450a_gpios: gpio@c000 { + rtc@6000 { + compatible = "qcom,pm8941-rtc"; + reg = <0x6000>, <0x6100>; + reg-names = "rtc", "alarm"; + interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; + wakeup-source; + }; + + pmm8540a_gpios: gpio@c000 { compatible = "qcom,pm8150-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; - gpio-ranges = <&pm8450a_gpios 0 0 10>; + gpio-ranges = <&pmm8540a_gpios 0 0 10>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; }; - pm8450c: pmic@4 { + pmm8540c: pmic@4 { compatible = "qcom,pm8150", "qcom,spmi-pmic"; reg = <0x4 SPMI_USID>; #address-cells = <1>; #size-cells = <0>; - pm8450c_gpios: gpio@c000 { + pmm8540c_gpios: gpio@c000 { compatible = "qcom,pm8150-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; - gpio-ranges = <&pm8450c_gpios 0 0 10>; + gpio-ranges = <&pmm8540c_gpios 0 0 10>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; }; - pm8450e: pmic@8 { + pmm8540e: pmic@8 { compatible = "qcom,pm8150", "qcom,spmi-pmic"; reg = <0x8 SPMI_USID>; #address-cells = <1>; #size-cells = <0>; - pm8450e_gpios: gpio@c000 { + pmm8540e_gpios: gpio@c000 { compatible = "qcom,pm8150-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; - gpio-ranges = <&pm8450e_gpios 0 0 10>; + gpio-ranges = <&pmm8540e_gpios 0 0 10>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; }; - pm8450g: pmic@c { + pmm8540g: pmic@c { compatible = "qcom,pm8150", "qcom,spmi-pmic"; reg = <0xc SPMI_USID>; #address-cells = <1>; #size-cells = <0>; - pm8450g_gpios: gpio@c000 { + pmm8540g_gpios: gpio@c000 { compatible = "qcom,pm8150-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; - gpio-ranges = <&pm8450g_gpios 0 0 10>; + gpio-ranges = <&pmm8540g_gpios 0 0 10>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; diff --git a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts index 6c547f1b13dc..3ccb5ffdb3ca 100644 --- a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts @@ -10,14 +10,19 @@ #include <dt-bindings/regulator/qcom,rpmh-regulator.h> #include "sa8540p.dtsi" -#include "pm8450a.dtsi" +#include "sa8540p-pmics.dtsi" / { model = "Qualcomm SA8540P Ride"; compatible = "qcom,sa8540p-ride", "qcom,sa8540p"; aliases { - serial0 = &qup2_uart17; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c12 = &i2c12; + i2c15 = &i2c15; + i2c18 = &i2c18; + serial0 = &uart17; }; chosen { @@ -146,6 +151,62 @@ }; }; +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_default>; + + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_default>; + + status = "okay"; +}; + +&i2c12 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c12_default>; + + status = "okay"; +}; + +&i2c15 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c15_default>; + + status = "okay"; +}; + +&i2c18 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c18_default>; + + status = "okay"; +}; + +&pcie2a { + ranges = <0x01000000 0x0 0x3c200000 0x0 0x3c200000 0x0 0x100000>, + <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>, + <0x03000000 0x5 0x00000000 0x5 0x00000000 0x1 0x00000000>; + + perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 145 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie2a_default>; + + status = "okay"; +}; + +&pcie2a_phy { + vdda-phy-supply = <&vreg_l11a>; + vdda-pll-supply = <&vreg_l3a>; + + status = "okay"; +}; + &pcie3a { ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x20000000>, @@ -167,12 +228,15 @@ status = "okay"; }; -&qup2 { +&qup0 { status = "okay"; }; -&qup2_uart17 { - compatible = "qcom,geni-debug-uart"; +&qup1 { + status = "okay"; +}; + +&qup2 { status = "okay"; }; @@ -186,29 +250,9 @@ status = "okay"; }; -&tlmm { - pcie3a_default: pcie3a-default-state { - perst-pins { - pins = "gpio151"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - - clkreq-pins { - pins = "gpio150"; - function = "pcie3a_clkreq"; - drive-strength = <2>; - bias-pull-up; - }; - - wake-pins { - pins = "gpio56"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; +&uart17 { + compatible = "qcom,geni-debug-uart"; + status = "okay"; }; &ufs_mem_hc { @@ -268,3 +312,93 @@ &xo_board_clk { clock-frequency = <38400000>; }; + +/* PINCTRL */ + +&tlmm { + i2c0_default: i2c0-default-state { + /* To USB7002T-I/KDXVA0 USB hub (SIP1 only) */ + pins = "gpio135", "gpio136"; + function = "qup0"; + drive-strength = <2>; + bias-pull-up; + }; + + i2c1_default: i2c1-default-state { + /* To PM40028B-F3EI PCIe switch */ + pins = "gpio158", "gpio159"; + function = "qup1"; + drive-strength = <2>; + bias-pull-up; + }; + + i2c12_default: i2c12-default-state { + /* To Maxim max20411 */ + pins = "gpio0", "gpio1"; + function = "qup12"; + drive-strength = <2>; + bias-pull-up; + }; + + i2c15_default: i2c15-default-state { + /* To display connector (SIP1 only) */ + pins = "gpio36", "gpio37"; + function = "qup15"; + drive-strength = <2>; + bias-pull-up; + }; + + i2c18_default: i2c18-default-state { + /* To ASM330LHH IMU (SIP1 only) */ + pins = "gpio66", "gpio67"; + function = "qup18"; + drive-strength = <2>; + bias-pull-up; + }; + + pcie2a_default: pcie2a-default-state { + perst-pins { + pins = "gpio143"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + clkreq-pins { + pins = "gpio142"; + function = "pcie2a_clkreq"; + drive-strength = <2>; + bias-pull-up; + }; + + wake-pins { + pins = "gpio145"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie3a_default: pcie3a-default-state { + perst-pins { + pins = "gpio151"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + clkreq-pins { + pins = "gpio150"; + function = "pcie3a_clkreq"; + drive-strength = <2>; + bias-pull-up; + }; + + wake-pins { + pins = "gpio56"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sa8540p.dtsi b/arch/arm64/boot/dts/qcom/sa8540p.dtsi index a88452c20d05..4a990fda8fc3 100644 --- a/arch/arm64/boot/dts/qcom/sa8540p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8540p.dtsi @@ -10,7 +10,7 @@ /delete-node/ &cpu4_opp_table; / { - cpu0_opp_table: cpu0-opp-table { + cpu0_opp_table: opp-table-cpu0 { compatible = "operating-points-v2"; opp-shared; @@ -92,7 +92,7 @@ }; }; - cpu4_opp_table: cpu4-opp-table { + cpu4_opp_table: opp-table-cpu4 { compatible = "operating-points-v2"; opp-shared; diff --git a/arch/arm64/boot/dts/qcom/sc7180-idp.dts b/arch/arm64/boot/dts/qcom/sc7180-idp.dts index 70fd9ff8dfa2..c3bdd3295c02 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-idp.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-idp.dts @@ -80,11 +80,17 @@ reg = <0x0 0x94400000 0x0 0x200000>; no-map; }; + + mdata_mem: mpss-metadata { + alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>; + size = <0x0 0x4000>; + no-map; + }; }; }; &apps_rsc { - pm6150-rpmh-regulators { + regulators-0 { compatible = "qcom,pm6150-rpmh-regulators"; qcom,pmic-id = "a"; @@ -206,7 +212,7 @@ }; }; - pm6150l-rpmh-regulators { + regulators-1 { compatible = "qcom,pm6150l-rpmh-regulators"; qcom,pmic-id = "c"; @@ -304,7 +310,7 @@ pinctrl-names = "default"; pinctrl-0 = <&disp_pins>; - reset-gpios = <&pm6150l_gpio 3 GPIO_ACTIVE_HIGH>; + reset-gpios = <&pm6150l_gpios 3 GPIO_ACTIVE_HIGH>; ports { #address-cells = <1>; @@ -370,8 +376,26 @@ &remoteproc_mpss { status = "okay"; compatible = "qcom,sc7180-mss-pil"; + reg = <0 0x04080000 0 0x4040>, <0 0x04180000 0 0x48>; + reg-names = "qdsp6", "rmb"; + + clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, + <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>, + <&gcc GCC_MSS_NAV_AXI_CLK>, + <&gcc GCC_MSS_SNOC_AXI_CLK>, + <&gcc GCC_MSS_MFAB_AXIS_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "bus", "nav", "snoc_axi", "mnoc_axi", "xo"; + iommus = <&apps_smmu 0x461 0x0>, <&apps_smmu 0x444 0x3>; - memory-region = <&mba_mem &mpss_mem>; + memory-region = <&mba_mem>, <&mpss_mem>, <&mdata_mem>; + + resets = <&aoss_reset AOSS_CC_MSS_RESTART>, + <&pdc_reset PDC_MODEM_SYNC_RESET>; + reset-names = "mss_restart", "pdc_reset"; + + qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>; + qcom,spare-regs = <&tcsr_regs_2 0xb3e4>; }; &sdhc_1 { @@ -406,7 +430,7 @@ pinctrl-names = "default", "sleep"; pinctrl-1 = <&qup_uart3_sleep>; - bluetooth: wcn3990-bt { + bluetooth: bluetooth { compatible = "qcom,wcn3990-bt"; vddio-supply = <&vreg_l10a_1p8>; vddxo-supply = <&vreg_l1c_1p8>; @@ -467,7 +491,7 @@ /* PINCTRL - additions to nodes defined in sc7180.dtsi */ -&pm6150l_gpio { +&pm6150l_gpios { disp_pins: disp-state { pinconf { pins = "gpio3"; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi index d3cf64c16dcd..b3ba23a88a0b 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi @@ -85,6 +85,24 @@ }; }; +/* + * ADDITIONS TO FIXED REGULATORS DEFINED IN PARENT DEVICE TREE FILES + * + * Sort order matches the order in the parent files (parents before children). + */ + +&pp3300_dx_edp { + /* + * The atna33xc20 really likes to be power cycled to keep it from + * getting in a bad state. This is the reason that the touchscreen + * rail and eDP rails are separate from each other on homestar (but + * not other trogdor devices) Make sure it starts "off" at bootup. + */ + /delete-property/ regulator-boot-on; +}; + +/* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */ + ap_ts_pen_1v8: &i2c4 { status = "okay"; clock-frequency = <400000>; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lte-sku.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lte-sku.dtsi index fd4b71203754..bffcbd141bd7 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lte-sku.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lte-sku.dtsi @@ -19,12 +19,11 @@ }; &ipa { - status = "okay"; - /* * Trogdor doesn't have QHEE (Qualcomm's EL2 blob), so the * modem needs to cover certain init steps (GSI init), and * the AP needs to wait for it. */ - modem-init; + qcom,gsi-loader = "modem"; + status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-parade-ps8640.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-parade-ps8640.dtsi index ebd6765e2afa..5aa7949b5328 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-parade-ps8640.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-parade-ps8640.dtsi @@ -26,6 +26,26 @@ }; }; +/* + * ADDITIONS TO FIXED REGULATORS DEFINED IN PARENT DEVICE TREE FILES + * + * Sort order matches the order in the parent files (parents before children). + */ + +&pp3300_dx_edp { + off-on-delay-us = <500000>; + + /* + * It's nicer to start with this regulator enabled. The + * bootloader may have left it on and it's nice not to cause an + * extra power cycle of the touchscreen and eDP panel at bootup. + * This should help speed bootup because we have off-on-delay-us. + */ + regulator-boot-on; +}; + +/* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */ + &dsi0_out { remote-endpoint = <&ps8640_in>; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel360.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel360.dtsi index 5702325d0c7b..bc4f3b6c6634 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel360.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel360.dtsi @@ -14,6 +14,25 @@ realtek,dmic-clk-rate-hz = <2048000>; }; +ap_ts_pen_1v8: &i2c4 { + clock-frequency = <400000>; + status = "okay"; + + ap_ts: touchscreen@10 { + compatible = "elan,ekth3915", "elan,ekth3500"; + reg = <0x10>; + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_l>, <&ts_reset_l>; + + interrupt-parent = <&tlmm>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + + vcc33-supply = <&pp3300_ts>; + vccio-supply = <&pp1800_l10a>; + reset-gpios = <&tlmm 8 GPIO_ACTIVE_LOW>; + }; +}; + &keyboard_controller { function-row-physmap = < MATRIX_KEY(0x00, 0x02, 0) /* T1 */ @@ -48,3 +67,7 @@ compatible = "google,sc7180-trogdor"; model = "sc7180-rt5682s-max98357a-1mic"; }; + +&wifi { + qcom,ath10k-calibration-variant = "GO_PAZQUEL360"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-ti-sn65dsi86.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-ti-sn65dsi86.dtsi index 65333709e529..e52b8776755d 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-ti-sn65dsi86.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-ti-sn65dsi86.dtsi @@ -7,6 +7,26 @@ #include <dt-bindings/gpio/gpio.h> +/* + * ADDITIONS TO FIXED REGULATORS DEFINED IN PARENT DEVICE TREE FILES + * + * Sort order matches the order in the parent files (parents before children). + */ + +&pp3300_dx_edp { + off-on-delay-us = <500000>; + + /* + * It's nicer to start with this regulator enabled. The + * bootloader may have left it on and it's nice not to cause an + * extra power cycle of the touchscreen and eDP panel at bootup. + * This should help speed bootup because we have off-on-delay-us. + */ + regulator-boot-on; +}; + +/* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */ + &dsi0_out { remote-endpoint = <&sn65dsi86_in>; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index f1defb94d670..423630c4d02c 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -81,6 +81,12 @@ reg = <0x0 0x94400000 0x0 0x200000>; no-map; }; + + mdata_mem: mpss-metadata { + alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>; + size = <0x0 0x4000>; + no-map; + }; }; aliases { @@ -432,7 +438,7 @@ }; &apps_rsc { - pm6150-rpmh-regulators { + regulators-0 { compatible = "qcom,pm6150-rpmh-regulators"; qcom,pmic-id = "a"; @@ -545,7 +551,7 @@ }; }; - pm6150l-rpmh-regulators { + regulators-1 { compatible = "qcom,pm6150l-rpmh-regulators"; qcom,pmic-id = "c"; @@ -788,18 +794,18 @@ hp_i2c: &i2c9 { #address-cells = <1>; #size-cells = <0>; - mi2s@0 { + dai-link@0 { reg = <MI2S_PRIMARY>; qcom,playback-sd-lines = <1>; qcom,capture-sd-lines = <0>; }; - secondary_mi2s: mi2s@1 { + secondary_mi2s: dai-link@1 { reg = <MI2S_SECONDARY>; qcom,playback-sd-lines = <0>; }; - hdmi@5 { + dai-link@5 { reg = <LPASS_DP_RX>; }; }; @@ -816,7 +822,11 @@ hp_i2c: &i2c9 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&dp_hot_plug_det>; +}; + +&mdss_dp_out { data-lanes = <0 1>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000>; }; &pm6150_adc { @@ -853,12 +863,30 @@ hp_i2c: &i2c9 { &remoteproc_mpss { status = "okay"; compatible = "qcom,sc7180-mss-pil"; + reg = <0 0x04080000 0 0x4040>, <0 0x04180000 0 0x48>; + reg-names = "qdsp6", "rmb"; + + clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, + <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>, + <&gcc GCC_MSS_NAV_AXI_CLK>, + <&gcc GCC_MSS_SNOC_AXI_CLK>, + <&gcc GCC_MSS_MFAB_AXIS_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "bus", "nav", "snoc_axi", "mnoc_axi", "xo"; + iommus = <&apps_smmu 0x461 0x0>, <&apps_smmu 0x444 0x3>; - memory-region = <&mba_mem &mpss_mem>; + memory-region = <&mba_mem>, <&mpss_mem>, <&mdata_mem>; /* This gets overridden for SKUs with LTE support. */ firmware-name = "qcom/sc7180-trogdor/modem-nolte/mba.mbn", "qcom/sc7180-trogdor/modem-nolte/qdsp6sw.mbn"; + + resets = <&aoss_reset AOSS_CC_MSS_RESTART>, + <&pdc_reset PDC_MODEM_SYNC_RESET>; + reset-names = "mss_restart", "pdc_reset"; + + qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>; + qcom,spare-regs = <&tcsr_regs_2 0xb3e4>; }; &sdhc_1 { @@ -1141,11 +1169,11 @@ ap_spi_fp: &spi10 { /* PINCTRL - board-specific pinctrl */ -&pm6150_gpio { +&pm6150_gpios { status = "disabled"; /* No GPIOs are connected */ }; -&pm6150l_gpio { +&pm6150l_gpios { gpio-line-names = "AP_SUSPEND", "", "", @@ -1376,7 +1404,15 @@ ap_spi_fp: &spi10 { pins = "gpio8"; function = "gpio"; bias-disable; - drive-strength = <2>; + + /* + * The reset GPIO to the touchscreen takes almost 2ms to drop + * at the default drive strength. When we bump it up to 8mA it + * falls in under 500us. We want this to be fast since the Elan + * datasheet (and any drivers written based on it) talk about using + * a 500 us reset pulse. + */ + drive-strength = <8>; }; sdc1_on: sdc1-on-state { diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index f71cf21a8dd8..ebfa21e9ed8a 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -27,8 +27,6 @@ #address-cells = <2>; #size-cells = <2>; - chosen { }; - aliases { mmc1 = &sdhc_1; mmc2 = &sdhc_2; @@ -54,6 +52,8 @@ spi11 = &spi11; }; + chosen { }; + clocks { xo_board: xo-board { compatible = "fixed-clock"; @@ -68,62 +68,6 @@ }; }; - reserved_memory: reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - hyp_mem: memory@80000000 { - reg = <0x0 0x80000000 0x0 0x600000>; - no-map; - }; - - xbl_mem: memory@80600000 { - reg = <0x0 0x80600000 0x0 0x200000>; - no-map; - }; - - aop_mem: memory@80800000 { - reg = <0x0 0x80800000 0x0 0x20000>; - no-map; - }; - - aop_cmd_db_mem: memory@80820000 { - reg = <0x0 0x80820000 0x0 0x20000>; - compatible = "qcom,cmd-db"; - no-map; - }; - - sec_apps_mem: memory@808ff000 { - reg = <0x0 0x808ff000 0x0 0x1000>; - no-map; - }; - - smem_mem: memory@80900000 { - reg = <0x0 0x80900000 0x0 0x200000>; - no-map; - }; - - tz_mem: memory@80b00000 { - reg = <0x0 0x80b00000 0x0 0x3900000>; - no-map; - }; - - ipa_fw_mem: memory@8b700000 { - reg = <0 0x8b700000 0 0x10000>; - no-map; - }; - - rmtfs_mem: memory@94600000 { - compatible = "qcom,rmtfs-mem"; - reg = <0x0 0x94600000 0x0 0x200000>; - no-map; - - qcom,client-id = <1>; - qcom,vmid = <15>; - }; - }; - cpus { #address-cells = <2>; #size-cells = <0>; @@ -146,9 +90,11 @@ qcom,freq-domain = <&cpufreq_hw 0>; L2_0: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; L3_0: l3-cache { compatible = "cache"; + cache-level = <3>; }; }; }; @@ -171,6 +117,7 @@ qcom,freq-domain = <&cpufreq_hw 0>; L2_100: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -193,6 +140,7 @@ qcom,freq-domain = <&cpufreq_hw 0>; L2_200: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -215,6 +163,7 @@ qcom,freq-domain = <&cpufreq_hw 0>; L2_300: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -237,6 +186,7 @@ qcom,freq-domain = <&cpufreq_hw 0>; L2_400: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -259,6 +209,7 @@ qcom,freq-domain = <&cpufreq_hw 0>; L2_500: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -281,6 +232,7 @@ qcom,freq-domain = <&cpufreq_hw 1>; L2_600: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -303,6 +255,7 @@ qcom,freq-domain = <&cpufreq_hw 1>; L2_700: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -398,6 +351,18 @@ }; }; + firmware { + scm { + compatible = "qcom,scm-sc7180", "qcom,scm"; + }; + }; + + memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0 0x80000000 0 0>; + }; + cpu0_opp_table: opp-table-cpu0 { compatible = "operating-points-v2"; opp-shared; @@ -538,10 +503,42 @@ }; }; - memory@80000000 { - device_type = "memory"; - /* We expect the bootloader to fill in the size */ - reg = <0 0x80000000 0 0>; + qspi_opp_table: opp-table-qspi { + compatible = "operating-points-v2"; + + opp-75000000 { + opp-hz = /bits/ 64 <75000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-150000000 { + opp-hz = /bits/ 64 <150000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + + qup_opp_table: opp-table-qup { + compatible = "operating-points-v2"; + + opp-75000000 { + opp-hz = /bits/ 64 <75000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-128000000 { + opp-hz = /bits/ 64 <128000000>; + required-opps = <&rpmhpd_opp_nom>; + }; }; pmu { @@ -549,9 +546,64 @@ interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; }; - firmware { - scm { - compatible = "qcom,scm-sc7180", "qcom,scm"; + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_mem: memory@80000000 { + reg = <0x0 0x80000000 0x0 0x600000>; + no-map; + }; + + xbl_mem: memory@80600000 { + reg = <0x0 0x80600000 0x0 0x200000>; + no-map; + }; + + aop_mem: memory@80800000 { + reg = <0x0 0x80800000 0x0 0x20000>; + no-map; + }; + + aop_cmd_db_mem: memory@80820000 { + reg = <0x0 0x80820000 0x0 0x20000>; + compatible = "qcom,cmd-db"; + no-map; + }; + + sec_apps_mem: memory@808ff000 { + reg = <0x0 0x808ff000 0x0 0x1000>; + no-map; + }; + + smem_mem: memory@80900000 { + reg = <0x0 0x80900000 0x0 0x200000>; + no-map; + }; + + tz_mem: memory@80b00000 { + reg = <0x0 0x80b00000 0x0 0x3900000>; + no-map; + }; + + ipa_fw_mem: memory@8b700000 { + reg = <0 0x8b700000 0 0x10000>; + no-map; + }; + + rmtfs_mem: memory@94600000 { + compatible = "qcom,rmtfs-mem"; + reg = <0x0 0x94600000 0x0 0x200000>; + no-map; + + qcom,client-id = <1>; + qcom,vmid = <15>; }; }; @@ -640,11 +692,6 @@ }; }; - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - soc: soc@0 { #address-cells = <2>; #size-cells = <2>; @@ -690,8 +737,8 @@ sdhc_1: mmc@7c4000 { compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; - reg = <0 0x7c4000 0 0x1000>, - <0 0x07c5000 0 0x1000>; + reg = <0 0x007c4000 0 0x1000>, + <0 0x007c5000 0 0x1000>; reg-names = "hc", "cqhci"; iommus = <&apps_smmu 0x60 0x0>; @@ -739,25 +786,6 @@ }; }; - qup_opp_table: opp-table-qup { - compatible = "operating-points-v2"; - - opp-75000000 { - opp-hz = /bits/ 64 <75000000>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - required-opps = <&rpmhpd_opp_svs>; - }; - - opp-128000000 { - opp-hz = /bits/ 64 <128000000>; - required-opps = <&rpmhpd_opp_nom>; - }; - }; - qupv3_id_0: geniqup@8c0000 { compatible = "qcom,geni-se-qup"; reg = <0 0x008c0000 0 0x6000>; @@ -1421,9 +1449,9 @@ iommus = <&apps_smmu 0x440 0x0>, <&apps_smmu 0x442 0x0>; - reg = <0 0x1e40000 0 0x7000>, - <0 0x1e47000 0 0x2000>, - <0 0x1e04000 0 0x2c000>; + reg = <0 0x01e40000 0 0x7000>, + <0 0x01e47000 0 0x2000>, + <0 0x01e04000 0 0x2c000>; reg-names = "ipa-reg", "ipa-shared", "gsi"; @@ -1929,8 +1957,7 @@ remoteproc_mpss: remoteproc@4080000 { compatible = "qcom,sc7180-mpss-pas"; - reg = <0 0x04080000 0 0x4040>, <0 0x04180000 0 0x48>; - reg-names = "qdsp6", "rmb"; + reg = <0 0x04080000 0 0x4040>; interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, @@ -1941,14 +1968,8 @@ interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack", "shutdown-ack"; - clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, - <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>, - <&gcc GCC_MSS_NAV_AXI_CLK>, - <&gcc GCC_MSS_SNOC_AXI_CLK>, - <&gcc GCC_MSS_MFAB_AXIS_CLK>, - <&rpmhcc RPMH_CXO_CLK>; - clock-names = "iface", "bus", "nav", "snoc_axi", - "mnoc_axi", "xo"; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; power-domains = <&rpmhpd SC7180_CX>, <&rpmhpd SC7180_MX>, @@ -1962,13 +1983,6 @@ qcom,smem-states = <&modem_smp2p_out 0>; qcom,smem-state-names = "stop"; - resets = <&aoss_reset AOSS_CC_MSS_RESTART>, - <&pdc_reset PDC_MODEM_SYNC_RESET>; - reset-names = "mss_restart", "pdc_reset"; - - qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>; - qcom,spare-regs = <&tcsr_regs_2 0xb3e4>; - status = "disabled"; glink-edge { @@ -2123,6 +2137,12 @@ #power-domain-cells = <1>; }; + dma@10a2000 { + compatible = "qcom,sc7180-dcc", "qcom,dcc"; + reg = <0x0 0x010a2000 0x0 0x1000>, + <0x0 0x010ae000 0x0 0x2000>; + }; + stm@6002000 { compatible = "arm,coresight-stm", "arm,primecell"; reg = <0 0x06002000 0 0x1000>, @@ -2655,25 +2675,6 @@ }; }; - qspi_opp_table: opp-table-qspi { - compatible = "operating-points-v2"; - - opp-75000000 { - opp-hz = /bits/ 64 <75000000>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - - opp-150000000 { - opp-hz = /bits/ 64 <150000000>; - required-opps = <&rpmhpd_opp_svs>; - }; - - opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - required-opps = <&rpmhpd_opp_nom>; - }; - }; - qspi: spi@88dc000 { compatible = "qcom,sc7180-qspi", "qcom,qspi-v1"; reg = <0 0x088dc000 0 0x600>; @@ -2921,7 +2922,7 @@ #power-domain-cells = <1>; }; - mdss: mdss@ae00000 { + mdss: display-subsystem@ae00000 { compatible = "qcom,sc7180-mdss"; reg = <0 0x0ae00000 0 0x1000>; reg-names = "mdss"; @@ -3022,7 +3023,8 @@ }; dsi0: dsi@ae94000 { - compatible = "qcom,mdss-dsi-ctrl"; + compatible = "qcom,sc7180-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; reg = <0 0x0ae94000 0 0x400>; reg-names = "dsi_ctrl"; @@ -3116,11 +3118,11 @@ compatible = "qcom,sc7180-dp"; status = "disabled"; - reg = <0 0xae90000 0 0x200>, - <0 0xae90200 0 0x200>, - <0 0xae90400 0 0xc00>, - <0 0xae91000 0 0x400>, - <0 0xae91400 0 0x400>; + reg = <0 0x0ae90000 0 0x200>, + <0 0x0ae90200 0 0x200>, + <0 0x0ae90400 0 0xc00>, + <0 0x0ae91000 0 0x400>, + <0 0x0ae91400 0 0x400>; interrupt-parent = <&mdss>; interrupts = <12>; @@ -3155,7 +3157,7 @@ port@1 { reg = <1>; - dp_out: endpoint { }; + mdss_dp_out: endpoint { }; }; }; @@ -3248,7 +3250,7 @@ #reset-cells = <1>; }; - aoss_qmp: power-controller@c300000 { + aoss_qmp: power-management@c300000 { compatible = "qcom,sc7180-aoss-qmp", "qcom,aoss-qmp"; reg = <0 0x0c300000 0 0x400>; interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; @@ -3274,8 +3276,8 @@ interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; qcom,ee = <0>; qcom,channel = <0>; - #address-cells = <1>; - #size-cells = <1>; + #address-cells = <2>; + #size-cells = <0>; interrupt-controller; #interrupt-cells = <4>; cell-index = <0>; @@ -3417,7 +3419,7 @@ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; }; - timer@17c20000{ + timer@17c20000 { #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0 0x20000000>; @@ -3625,6 +3627,7 @@ <&apps_smmu 0x1032 0>; power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>; + required-opps = <&rpmhpd_opp_nom>; status = "disabled"; @@ -3655,6 +3658,8 @@ clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, <&rpmhcc RPMH_CXO_CLK>; clock-names = "iface", "bi_tcxo"; + power-domains = <&rpmhpd SC7180_CX>; + #clock-cells = <1>; #power-domain-cells = <1>; }; @@ -3681,7 +3686,7 @@ type = "passive"; }; - cpu0_crit: cpu_crit { + cpu0_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -3730,7 +3735,7 @@ type = "passive"; }; - cpu1_crit: cpu_crit { + cpu1_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -3779,7 +3784,7 @@ type = "passive"; }; - cpu2_crit: cpu_crit { + cpu2_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -3828,7 +3833,7 @@ type = "passive"; }; - cpu3_crit: cpu_crit { + cpu3_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -3877,7 +3882,7 @@ type = "passive"; }; - cpu4_crit: cpu_crit { + cpu4_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -3926,7 +3931,7 @@ type = "passive"; }; - cpu5_crit: cpu_crit { + cpu5_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -3975,7 +3980,7 @@ type = "passive"; }; - cpu6_crit: cpu_crit { + cpu6_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -4016,7 +4021,7 @@ type = "passive"; }; - cpu7_crit: cpu_crit { + cpu7_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -4057,7 +4062,7 @@ type = "passive"; }; - cpu8_crit: cpu_crit { + cpu8_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -4098,7 +4103,7 @@ type = "passive"; }; - cpu9_crit: cpu_crit { + cpu9_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -4132,7 +4137,7 @@ type = "hot"; }; - aoss0_crit: aoss0_crit { + aoss0_crit: aoss0-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -4152,7 +4157,7 @@ hysteresis = <2000>; type = "hot"; }; - cpuss0_crit: cluster0_crit { + cpuss0_crit: cluster0-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -4172,7 +4177,7 @@ hysteresis = <2000>; type = "hot"; }; - cpuss1_crit: cluster0_crit { + cpuss1_crit: cluster0-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -4193,7 +4198,7 @@ type = "passive"; }; - gpuss0_crit: gpuss0_crit { + gpuss0_crit: gpuss0-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -4221,7 +4226,7 @@ type = "passive"; }; - gpuss1_crit: gpuss1_crit { + gpuss1_crit: gpuss1-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -4249,7 +4254,7 @@ type = "hot"; }; - aoss1_crit: aoss1_crit { + aoss1_crit: aoss1-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -4270,7 +4275,7 @@ type = "hot"; }; - cwlan_crit: cwlan_crit { + cwlan_crit: cwlan-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -4291,7 +4296,7 @@ type = "hot"; }; - audio_crit: audio_crit { + audio_crit: audio-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -4312,7 +4317,7 @@ type = "hot"; }; - ddr_crit: ddr_crit { + ddr_crit: ddr-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -4333,7 +4338,7 @@ type = "hot"; }; - q6_hvx_crit: q6_hvx_crit { + q6_hvx_crit: q6-hvx-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -4354,7 +4359,7 @@ type = "hot"; }; - camera_crit: camera_crit { + camera_crit: camera-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -4375,7 +4380,7 @@ type = "hot"; }; - mdm_crit: mdm_crit { + mdm_crit: mdm-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -4396,7 +4401,7 @@ type = "hot"; }; - mdm_dsp_crit: mdm_dsp_crit { + mdm_dsp_crit: mdm-dsp-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -4417,7 +4422,7 @@ type = "hot"; }; - npu_crit: npu_crit { + npu_crit: npu-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; @@ -4438,7 +4443,7 @@ type = "hot"; }; - video_crit: video_crit { + video_crit: video-crit { temperature = <110000>; hysteresis = <2000>; type = "critical"; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682.dtsi index af685bc35e10..69e7aa7b2f6c 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682.dtsi @@ -33,10 +33,23 @@ }; dai-link@1 { - link-name = "ALC5682"; + link-name = "DisplayPort"; reg = <1>; cpu { + sound-dai = <&lpass_cpu LPASS_DP_RX>; + }; + + codec { + sound-dai = <&mdss_dp>; + }; + }; + + dai-link@2 { + link-name = "ALC5682"; + reg = <2>; + + cpu { sound-dai = <&lpass_cpu MI2S_PRIMARY>; }; @@ -92,6 +105,10 @@ hp_i2c: &i2c2 { reg = <MI2S_SECONDARY>; qcom,playback-sd-lines = <0>; }; + + dai-link@5 { + reg = <LPASS_DP_RX>; + }; }; /* PINCTRL - ADDITIONS TO NODES IN PARENT DEVICE TREE FILES */ diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-wcd9385.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-wcd9385.dtsi index ae2552094cda..020ef666e35f 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-wcd9385.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-wcd9385.dtsi @@ -32,12 +32,8 @@ "TX SWR_DMIC6", "DMIC7_OUTPUT", "TX SWR_DMIC7", "DMIC8_OUTPUT"; - qcom,msm-mbhc-hphl-swh = <1>; - qcom,msm-mbhc-gnd-swh = <1>; - #address-cells = <1>; #size-cells = <0>; - #sound-dai-cells = <0>; dai-link@0 { link-name = "MAX98360A"; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd-pro.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd-pro.dts new file mode 100644 index 000000000000..4ee5f0b0a5de --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd-pro.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * sc7280 CRD 3+ Pro board device tree source + * + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "sc7280-herobrine-crd.dts" +#include "sc7280-herobrine-pro-sku.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. sc7280 CRD Pro platform (rev5+)"; + compatible = "google,zoglin-sku1536", "google,hoglin-sku1536", "qcom,sc7280"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker.dtsi index 3d639c70a06e..0add7a2a099c 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-evoker.dtsi @@ -55,6 +55,7 @@ ts_i2c: &i2c13 { reset-gpios = <&tlmm 54 GPIO_ACTIVE_LOW>; vdd-supply = <&ts_avdd>; + mainboard-vddio-supply = <&ts_avccio>; }; }; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-lte-sku.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-lte-sku.dtsi index ad66e5e9db4e..95505549adcc 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-lte-sku.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-lte-sku.dtsi @@ -17,16 +17,44 @@ reg = <0x0 0x9c700000 0x0 0x200000>; no-map; }; + + mdata_mem: mpss-metadata { + alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>; + size = <0x0 0x4000>; + no-map; + }; }; }; +&ipa { + qcom,gsi-loader = "modem"; + status = "okay"; +}; + &remoteproc_mpss { compatible = "qcom,sc7280-mss-pil"; + + clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, + <&gcc GCC_MSS_OFFLINE_AXI_CLK>, + <&gcc GCC_MSS_SNOC_AXI_CLK>, + <&rpmhcc RPMH_PKA_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "offline", "snoc_axi", "pka", "xo"; + iommus = <&apps_smmu 0x124 0x0>, <&apps_smmu 0x488 0x7>; interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; - memory-region = <&mba_mem>, <&mpss_mem>; + memory-region = <&mba_mem>, <&mpss_mem>, <&mdata_mem>; firmware-name = "qcom/sc7280-herobrine/modem/mba.mbn", "qcom/sc7280-herobrine/modem/qdsp6sw.mbn"; + + resets = <&aoss_reset AOSS_CC_MSS_RESTART>, + <&pdc_reset PDC_MODEM_SYNC_RESET>; + reset-names = "mss_restart", "pdc_reset"; + + qcom,halt-regs = <&tcsr_1 0x3000 0x5000 0x8000 0x13000>; + qcom,ext-regs = <&tcsr_2 0x10000 0x10004 &tcsr_1 0x6004 0x6008>; + qcom,qaccept-regs = <&tcsr_1 0x3030 0x3040 0x3020>; + status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-nvme-sku.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-nvme-sku.dtsi new file mode 100644 index 000000000000..1aed02297f44 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-nvme-sku.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Herobrine dts fragment for NVMe SKUs + * + * Copyright 2022 Google LLC. + */ + +&pcie1 { + status = "okay"; +}; + +&pcie1_phy { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-pro-sku.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-pro-sku.dtsi new file mode 100644 index 000000000000..fb4bbe8aeda0 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-pro-sku.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Google Herobrine dts fragment for PRO SKUs + * + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/delete-node/ &vreg_s9c_0p676; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager.dtsi index 17553e0fd6fd..818d4046d2c7 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager.dtsi @@ -55,6 +55,7 @@ ts_i2c: &i2c13 { reset-gpios = <&tlmm 54 GPIO_ACTIVE_LOW>; vcc33-supply = <&ts_avdd>; + vccio-supply = <&ts_avccio>; }; }; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-zombie-nvme-lte.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-zombie-nvme-lte.dts new file mode 100644 index 000000000000..e1fcacdccd51 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-zombie-nvme-lte.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Zombie board device tree source + * + * Copyright 2022 Google LLC. + */ + +/dts-v1/; + +#include "sc7280-herobrine-zombie.dtsi" +#include "sc7280-herobrine-lte-sku.dtsi" +#include "sc7280-herobrine-nvme-sku.dtsi" + +/ { + model = "Google Zombie with LTE and NVMe"; + compatible = "google,zombie-sku514", "qcom,sc7280"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-zombie-nvme.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-zombie-nvme.dts new file mode 100644 index 000000000000..e3d52c560363 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-zombie-nvme.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Zombie board device tree source + * + * Copyright 2022 Google LLC. + */ + +/dts-v1/; + +#include "sc7280-herobrine-zombie.dtsi" +#include "sc7280-herobrine-wifi-sku.dtsi" +#include "sc7280-herobrine-nvme-sku.dtsi" + +/ { + model = "Google Zombie with NVMe"; + compatible = "google,zombie-sku2","google,zombie-sku3","google,zombie-sku515", "qcom,sc7280"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-zombie.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-zombie.dtsi index 7fc0b6bfc0d6..a4fde22e3355 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-zombie.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-zombie.dtsi @@ -60,19 +60,9 @@ ap_tp_i2c: &i2c0 { status = "okay"; }; -/* For nvme */ -&pcie1 { - status = "okay"; -}; - -/* For nvme */ -&pcie1_phy { - status = "okay"; -}; - -&pm8350c_pwm_backlight{ - /* Set the PWM period to 200 microseconds (5kHz duty cycle) */ - pwms = <&pm8350c_pwm 3 200000>; +&pm8350c_pwm_backlight { + /* Set the PWM period to 320 microseconds (3.125kHz frequency) */ + pwms = <&pm8350c_pwm 3 320000>; }; &pwmleds { diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi index 27f479ff9d80..b6137816f2f3 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi @@ -108,6 +108,24 @@ pinctrl-names = "default"; pinctrl-0 = <&en_pp3300_dx_edp>; + regulator-enable-ramp-delay = <3000>; + + /* + * eDP panel specs nearly always have a spec that says you + * shouldn't turn them off an on again without waiting 500ms. + * Add this as a board constraint since this rail is shared + * between the panel and touchscreen. + */ + off-on-delay-us = <500000>; + + /* + * Stat the regulator on. This has the advantage of starting + * the slow process of powering the panel on as soon as we + * probe the regulator. It also avoids tripping the + * off-on-delay immediately on every bootup. + */ + regulator-boot-on; + vin-supply = <&pp3300_z1>; }; @@ -442,7 +460,11 @@ ap_i2c_tpm: &i2c14 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&dp_hot_plug_det>; +}; + +&mdss_dp_out { data-lanes = <0 1>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; &mdss_mdp { diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index f7efb9966afd..8b5293e7fd2a 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -19,6 +19,7 @@ aliases { bluetooth0 = &bluetooth; serial1 = &uart7; + wifi0 = &wifi; }; max98360a: audio-codec-0 { @@ -112,12 +113,8 @@ "TX SWR_DMIC6", "DMIC7_OUTPUT", "TX SWR_DMIC7", "DMIC8_OUTPUT"; - qcom,msm-mbhc-hphl-swh = <1>; - qcom,msm-mbhc-gnd-swh = <1>; - #address-cells = <1>; #size-cells = <0>; - #sound-dai-cells = <0>; dai-link@0 { link-name = "MAX98360A"; @@ -376,11 +373,6 @@ status = "okay"; }; -&ipa { - status = "okay"; - modem-init; -}; - &lpass_cpu { status = "okay"; @@ -736,6 +728,7 @@ &tlmm { amp_en: amp-en-state { pins = "gpio63"; + function = "gpio"; bias-pull-down; drive-strength = <2>; }; diff --git a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi index df49564ae6dc..88204f794ccb 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi @@ -230,9 +230,15 @@ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; + /* + * The initial design of this regulator was to use it as 3.3V, + * but due to later changes in design it was changed to 1.8V. + * The original name is kept due to same schematic. + */ + ts_avccio: vreg_l3c_3p0: ldo3 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3540000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; @@ -336,11 +342,6 @@ /* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */ -&ipa { - status = "okay"; - modem-init; -}; - &lpass_va_macro { vdd-micb-supply = <&vreg_bob>; }; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 0adf13399e64..bdcb74925313 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -166,7 +166,7 @@ CPU0: cpu@0 { device_type = "cpu"; - compatible = "arm,kryo"; + compatible = "qcom,kryo"; reg = <0x0 0x0>; enable-method = "psci"; cpu-idle-states = <&LITTLE_CPU_SLEEP_0 @@ -180,16 +180,18 @@ #cooling-cells = <2>; L2_0: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; L3_0: l3-cache { compatible = "cache"; + cache-level = <3>; }; }; }; CPU1: cpu@100 { device_type = "cpu"; - compatible = "arm,kryo"; + compatible = "qcom,kryo"; reg = <0x0 0x100>; enable-method = "psci"; cpu-idle-states = <&LITTLE_CPU_SLEEP_0 @@ -203,13 +205,14 @@ #cooling-cells = <2>; L2_100: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; CPU2: cpu@200 { device_type = "cpu"; - compatible = "arm,kryo"; + compatible = "qcom,kryo"; reg = <0x0 0x200>; enable-method = "psci"; cpu-idle-states = <&LITTLE_CPU_SLEEP_0 @@ -223,13 +226,14 @@ #cooling-cells = <2>; L2_200: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; CPU3: cpu@300 { device_type = "cpu"; - compatible = "arm,kryo"; + compatible = "qcom,kryo"; reg = <0x0 0x300>; enable-method = "psci"; cpu-idle-states = <&LITTLE_CPU_SLEEP_0 @@ -243,13 +247,14 @@ #cooling-cells = <2>; L2_300: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; CPU4: cpu@400 { device_type = "cpu"; - compatible = "arm,kryo"; + compatible = "qcom,kryo"; reg = <0x0 0x400>; enable-method = "psci"; cpu-idle-states = <&BIG_CPU_SLEEP_0 @@ -263,13 +268,14 @@ #cooling-cells = <2>; L2_400: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; CPU5: cpu@500 { device_type = "cpu"; - compatible = "arm,kryo"; + compatible = "qcom,kryo"; reg = <0x0 0x500>; enable-method = "psci"; cpu-idle-states = <&BIG_CPU_SLEEP_0 @@ -283,13 +289,14 @@ #cooling-cells = <2>; L2_500: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; CPU6: cpu@600 { device_type = "cpu"; - compatible = "arm,kryo"; + compatible = "qcom,kryo"; reg = <0x0 0x600>; enable-method = "psci"; cpu-idle-states = <&BIG_CPU_SLEEP_0 @@ -303,13 +310,14 @@ #cooling-cells = <2>; L2_600: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; CPU7: cpu@700 { device_type = "cpu"; - compatible = "arm,kryo"; + compatible = "qcom,kryo"; reg = <0x0 0x700>; enable-method = "psci"; cpu-idle-states = <&BIG_CPU_SLEEP_0 @@ -323,6 +331,7 @@ #cooling-cells = <2>; L2_700: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -2171,9 +2180,9 @@ iommus = <&apps_smmu 0x480 0x0>, <&apps_smmu 0x482 0x0>; - reg = <0 0x1e40000 0 0x8000>, - <0 0x1e50000 0 0x4ad0>, - <0 0x1e04000 0 0x23000>; + reg = <0 0x01e40000 0 0x8000>, + <0 0x01e50000 0 0x4ad0>, + <0 0x01e04000 0 0x23000>; reg-names = "ipa-reg", "ipa-shared", "gsi"; @@ -2455,7 +2464,7 @@ lpass_hm: clock-controller@3c00000 { compatible = "qcom,sc7280-lpasshm"; - reg = <0 0x3c00000 0 0x28>; + reg = <0 0x03c00000 0 0x28>; clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "bi_tcxo"; #clock-cells = <1>; @@ -2661,6 +2670,12 @@ #power-domain-cells = <1>; }; + dma@117f000 { + compatible = "qcom,sc7280-dcc", "qcom,dcc"; + reg = <0x0 0x0117f000 0x0 0x1000>, + <0x0 0x01112000 0x0 0x6000>; + }; + adreno_smmu: iommu@3da0000 { compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", "arm,mmu-500"; reg = <0 0x03da0000 0 0x20000>; @@ -2711,12 +2726,8 @@ interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack", "shutdown-ack"; - clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, - <&gcc GCC_MSS_OFFLINE_AXI_CLK>, - <&gcc GCC_MSS_SNOC_AXI_CLK>, - <&rpmhcc RPMH_PKA_CLK>, - <&rpmhcc RPMH_CXO_CLK>; - clock-names = "iface", "offline", "snoc_axi", "pka", "xo"; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; power-domains = <&rpmhpd SC7280_CX>, <&rpmhpd SC7280_MSS>; @@ -2729,14 +2740,6 @@ qcom,smem-states = <&modem_smp2p_out 0>; qcom,smem-state-names = "stop"; - resets = <&aoss_reset AOSS_CC_MSS_RESTART>, - <&pdc_reset PDC_MODEM_SYNC_RESET>; - reset-names = "mss_restart", "pdc_reset"; - - qcom,halt-regs = <&tcsr_1 0x3000 0x5000 0x8000 0x13000>; - qcom,ext-regs = <&tcsr_2 0x10000 0x10004 &tcsr_1 0x6004 0x6008>; - qcom,qaccept-regs = <&tcsr_1 0x3030 0x3040 0x3020>; - status = "disabled"; glink-edge { @@ -3489,7 +3492,7 @@ pmu@9091000 { compatible = "qcom,sc7280-llcc-bwmon"; - reg = <0 0x9091000 0 0x1000>; + reg = <0 0x09091000 0 0x1000>; interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; @@ -3571,7 +3574,7 @@ }; gem_noc: interconnect@9100000 { - reg = <0 0x9100000 0 0xe2200>; + reg = <0 0x09100000 0 0xe2200>; compatible = "qcom,sc7280-gem-noc"; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; @@ -3586,8 +3589,8 @@ eud: eud@88e0000 { compatible = "qcom,sc7280-eud","qcom,eud"; - reg = <0 0x88e0000 0 0x2000>, - <0 0x88e2000 0 0x1000>; + reg = <0 0x088e0000 0 0x2000>, + <0 0x088e2000 0 0x1000>; interrupts-extended = <&pdc 11 IRQ_TYPE_LEVEL_HIGH>; ports { port@0 { @@ -3750,7 +3753,7 @@ videocc: clock-controller@aaf0000 { compatible = "qcom,sc7280-videocc"; - reg = <0 0xaaf0000 0 0x10000>; + reg = <0 0x0aaf0000 0 0x10000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>; clock-names = "bi_tcxo", "bi_tcxo_ao"; @@ -3773,7 +3776,7 @@ dispcc: clock-controller@af00000 { compatible = "qcom,sc7280-dispcc"; - reg = <0 0xaf00000 0 0x20000>; + reg = <0 0x0af00000 0 0x20000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_DISP_GPLL0_CLK_SRC>, <&mdss_dsi_phy 0>, @@ -3906,7 +3909,8 @@ }; mdss_dsi: dsi@ae94000 { - compatible = "qcom,mdss-dsi-ctrl"; + compatible = "qcom,sc7280-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; reg = <0 0x0ae94000 0 0x400>; reg-names = "dsi_ctrl"; @@ -4001,10 +4005,10 @@ pinctrl-names = "default"; pinctrl-0 = <&edp_hot_plug_det>; - reg = <0 0xaea0000 0 0x200>, - <0 0xaea0200 0 0x200>, - <0 0xaea0400 0 0xc00>, - <0 0xaea1000 0 0x400>; + reg = <0 0x0aea0000 0 0x200>, + <0 0x0aea0200 0 0x200>, + <0 0x0aea0400 0 0xc00>, + <0 0x0aea1000 0 0x400>; interrupt-parent = <&mdss>; interrupts = <14>; @@ -4076,10 +4080,10 @@ mdss_edp_phy: phy@aec2a00 { compatible = "qcom,sc7280-edp-phy"; - reg = <0 0xaec2a00 0 0x19c>, - <0 0xaec2200 0 0xa0>, - <0 0xaec2600 0 0xa0>, - <0 0xaec2000 0 0x1c0>; + reg = <0 0x0aec2a00 0 0x19c>, + <0 0x0aec2200 0 0xa0>, + <0 0x0aec2600 0 0xa0>, + <0 0x0aec2000 0 0x1c0>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_EDP_CLKREF_EN>; @@ -4095,11 +4099,11 @@ mdss_dp: displayport-controller@ae90000 { compatible = "qcom,sc7280-dp"; - reg = <0 0xae90000 0 0x200>, - <0 0xae90200 0 0x200>, - <0 0xae90400 0 0xc00>, - <0 0xae91000 0 0x400>, - <0 0xae91400 0 0x400>; + reg = <0 0x0ae90000 0 0x200>, + <0 0x0ae90200 0 0x200>, + <0 0x0ae90400 0 0xc00>, + <0 0x0ae91000 0 0x400>, + <0 0x0ae91400 0 0x400>; interrupt-parent = <&mdss>; interrupts = <12>; @@ -4140,7 +4144,7 @@ port@1 { reg = <1>; - dp_out: endpoint { }; + mdss_dp_out: endpoint { }; }; }; @@ -4217,7 +4221,7 @@ #reset-cells = <1>; }; - aoss_qmp: power-controller@c300000 { + aoss_qmp: power-management@c300000 { compatible = "qcom,sc7280-aoss-qmp", "qcom,aoss-qmp"; reg = <0 0x0c300000 0 0x400>; interrupts-extended = <&ipcc IPCC_CLIENT_AOP @@ -4246,8 +4250,8 @@ interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; qcom,ee = <0>; qcom,channel = <0>; - #address-cells = <1>; - #size-cells = <1>; + #address-cells = <2>; + #size-cells = <0>; interrupt-controller; #interrupt-cells = <4>; }; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts index 551768f97729..98a0f1f9f01e 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts @@ -17,10 +17,12 @@ compatible = "qcom,sc8280xp-crd", "qcom,sc8280xp"; aliases { - serial0 = &qup2_uart17; + i2c4 = &i2c4; + i2c21 = &i2c21; + serial0 = &uart17; }; - backlight { + backlight: backlight { compatible = "pwm-backlight"; pwms = <&pmc8280c_lpg 3 1000000>; enable-gpios = <&pmc8280_1_gpios 8 GPIO_ACTIVE_HIGH>; @@ -34,6 +36,100 @@ stdout-path = "serial0:115200n8"; }; + pmic-glink { + compatible = "qcom,sc8280xp-pmic-glink", "qcom,pmic-glink"; + + #address-cells = <1>; + #size-cells = <0>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_con0_hs: endpoint { + remote-endpoint = <&usb_0_role_switch>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_con0_ss: endpoint { + remote-endpoint = <&mdss0_dp0_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_con0_sbu: endpoint { + remote-endpoint = <&usb0_sbu_mux>; + }; + }; + }; + }; + + connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + + pmic_glink_con1_hs: endpoint { + remote-endpoint = <&usb_1_role_switch>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_con1_ss: endpoint { + remote-endpoint = <&mdss0_dp1_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_con1_sbu: endpoint { + remote-endpoint = <&usb1_sbu_mux>; + }; + }; + }; + }; + }; + + vreg_edp_3p3: regulator-edp-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_EDP_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 25 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&edp_reg_en>; + + regulator-boot-on; + }; + vreg_edp_bl: regulator-edp-bl { compatible = "regulator-fixed"; @@ -112,10 +208,59 @@ regulator-boot-on; }; + + reserved-memory { + linux,cma { + compatible = "shared-dma-pool"; + size = <0x0 0x8000000>; + reusable; + linux,cma-default; + }; + }; + + usb0-sbu-mux { + compatible = "pericom,pi3usb102", "gpio-sbu-mux"; + + enable-gpios = <&tlmm 101 GPIO_ACTIVE_LOW>; + select-gpios = <&tlmm 164 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&usb0_sbu_default>; + + mode-switch; + orientation-switch; + svid = /bits/ 16 <0xff01>; + + port { + usb0_sbu_mux: endpoint { + remote-endpoint = <&pmic_glink_con0_sbu>; + }; + }; + }; + + usb1-sbu-mux { + compatible = "pericom,pi3usb102", "gpio-sbu-mux"; + + enable-gpios = <&tlmm 48 GPIO_ACTIVE_LOW>; + select-gpios = <&tlmm 47 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&usb1_sbu_default>; + + mode-switch; + orientation-switch; + svid = /bits/ 16 <0xff01>; + + port { + usb1_sbu_mux: endpoint { + remote-endpoint = <&pmic_glink_con1_sbu>; + }; + }; + }; }; &apps_rsc { - pmc8280-1-rpmh-regulators { + regulators-0 { compatible = "qcom,pm8350-rpmh-regulators"; qcom,pmic-id = "b"; @@ -134,7 +279,6 @@ regulator-max-microvolt = <1200000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; regulator-boot-on; - regulator-always-on; }; vreg_l4b: ldo4 { @@ -153,7 +297,7 @@ }; }; - pmc8280c-rpmh-regulators { + regulators-1 { compatible = "qcom,pm8350c-rpmh-regulators"; qcom,pmic-id = "c"; @@ -182,7 +326,7 @@ }; }; - pmc8280-2-rpmh-regulators { + regulators-2 { compatible = "qcom,pm8350-rpmh-regulators"; qcom,pmic-id = "d"; @@ -228,80 +372,79 @@ }; }; -&pcie2a { - perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; - - vddpe-3v3-supply = <&vreg_nvme>; - - pinctrl-names = "default"; - pinctrl-0 = <&pcie2a_default>; - +&dispcc0 { status = "okay"; }; -&pcie2a_phy { - vdda-phy-supply = <&vreg_l6d>; - vdda-pll-supply = <&vreg_l4d>; - +&mdss0 { status = "okay"; }; -&pcie3a { - perst-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; - - vddpe-3v3-supply = <&vreg_wwan>; - - pinctrl-names = "default"; - pinctrl-0 = <&pcie3a_default>; - +&mdss0_dp0 { status = "okay"; }; -&pcie3a_phy { - vdda-phy-supply = <&vreg_l6d>; - vdda-pll-supply = <&vreg_l4d>; +&mdss0_dp0_out { + data-lanes = <0 1>; + remote-endpoint = <&pmic_glink_con0_ss>; +}; +&mdss0_dp1 { status = "okay"; }; -&pcie4 { - perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>; +&mdss0_dp1_out { + data-lanes = <0 1>; + remote-endpoint = <&pmic_glink_con1_ss>; +}; - vddpe-3v3-supply = <&vreg_wlan>; +&mdss0_dp3 { + compatible = "qcom,sc8280xp-edp"; + /delete-property/ #sound-dai-cells; - pinctrl-names = "default"; - pinctrl-0 = <&pcie4_default>; + data-lanes = <0 1 2 3>; status = "okay"; -}; -&pcie4_phy { - vdda-phy-supply = <&vreg_l6d>; - vdda-pll-supply = <&vreg_l4d>; + aux-bus { + panel { + compatible = "edp-panel"; + power-supply = <&vreg_edp_3p3>; - status = "okay"; -}; + backlight = <&backlight>; -&pmc8280c_lpg { - status = "okay"; -}; + ports { + port { + edp_panel_in: endpoint { + remote-endpoint = <&mdss0_dp3_out>; + }; + }; + }; + }; + }; -&pmk8280_pon_pwrkey { - status = "okay"; + ports { + port@1 { + reg = <1>; + mdss0_dp3_out: endpoint { + remote-endpoint = <&edp_panel_in>; + }; + }; + }; }; -&qup0 { +&mdss0_dp3_phy { + vdda-phy-supply = <&vreg_l6b>; + vdda-pll-supply = <&vreg_l3b>; + status = "okay"; }; -&qup0_i2c4 { +&i2c4 { clock-frequency = <400000>; pinctrl-names = "default"; - pinctrl-0 = <&qup0_i2c4_default>; + pinctrl-0 = <&i2c4_default>; status = "okay"; @@ -318,19 +461,11 @@ }; }; -&qup1 { - status = "okay"; -}; - -&qup2 { - status = "okay"; -}; - -&qup2_i2c5 { +&i2c21 { clock-frequency = <400000>; pinctrl-names = "default"; - pinctrl-0 = <&qup2_i2c5_default>; + pinctrl-0 = <&i2c21_default>; status = "okay"; @@ -363,12 +498,83 @@ }; }; -&qup2_uart17 { - compatible = "qcom,geni-debug-uart"; +&pcie2a { + perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; + + vddpe-3v3-supply = <&vreg_nvme>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie2a_default>; status = "okay"; }; +&pcie2a_phy { + vdda-phy-supply = <&vreg_l6d>; + vdda-pll-supply = <&vreg_l4d>; + + status = "okay"; +}; + +&pcie3a { + perst-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; + + vddpe-3v3-supply = <&vreg_wwan>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie3a_default>; + + status = "okay"; +}; + +&pcie3a_phy { + vdda-phy-supply = <&vreg_l6d>; + vdda-pll-supply = <&vreg_l4d>; + + status = "okay"; +}; + +&pcie4 { + perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>; + + vddpe-3v3-supply = <&vreg_wlan>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie4_default>; + + status = "okay"; +}; + +&pcie4_phy { + vdda-phy-supply = <&vreg_l6d>; + vdda-pll-supply = <&vreg_l4d>; + + status = "okay"; +}; + +&pmc8280c_lpg { + status = "okay"; +}; + +&pmk8280_pon_pwrkey { + status = "okay"; +}; + +&qup0 { + status = "okay"; +}; + +&qup1 { + status = "okay"; +}; + +&qup2 { + status = "okay"; +}; + &remoteproc_adsp { firmware-name = "qcom/sc8280xp/qcadsp8280.mbn"; @@ -381,6 +587,12 @@ status = "okay"; }; +&uart17 { + compatible = "qcom,geni-debug-uart"; + + status = "okay"; +}; + &ufs_mem_hc { reset-gpios = <&tlmm 228 GPIO_ACTIVE_LOW>; @@ -404,7 +616,6 @@ }; &usb_0_dwc3 { - /* TODO: Define USB-C connector properly */ dr_mode = "host"; }; @@ -423,12 +634,15 @@ status = "okay"; }; +&usb_0_role_switch { + remote-endpoint = <&pmic_glink_con0_hs>; +}; + &usb_1 { status = "okay"; }; &usb_1_dwc3 { - /* TODO: Define USB-C connector properly */ dr_mode = "host"; }; @@ -447,6 +661,10 @@ status = "okay"; }; +&usb_1_role_switch { + remote-endpoint = <&pmic_glink_con1_hs>; +}; + &xo_board_clk { clock-frequency = <38400000>; }; @@ -494,6 +712,27 @@ &tlmm { gpio-reserved-ranges = <74 6>, <83 4>, <125 2>, <128 2>, <154 7>; + edp_reg_en: edp-reg-en-state { + pins = "gpio25"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + i2c4_default: i2c4-default-state { + pins = "gpio171", "gpio172"; + function = "qup4"; + drive-strength = <16>; + bias-disable; + }; + + i2c21_default: i2c21-default-state { + pins = "gpio81", "gpio82"; + function = "qup21"; + drive-strength = <16>; + bias-disable; + }; + kybd_default: kybd-default-state { disable-pins { pins = "gpio102"; @@ -590,22 +829,6 @@ }; }; - qup0_i2c4_default: qup0-i2c4-default-state { - pins = "gpio171", "gpio172"; - function = "qup4"; - - bias-disable; - drive-strength = <16>; - }; - - qup2_i2c5_default: qup2-i2c5-default-state { - pins = "gpio81", "gpio82"; - function = "qup21"; - - bias-disable; - drive-strength = <16>; - }; - tpad_default: tpad-default-state { int-n-pins { pins = "gpio182"; @@ -628,4 +851,54 @@ drive-strength = <16>; }; }; + + usb0_sbu_default: usb0-sbu-state { + oe-n-pins { + pins = "gpio101"; + function = "gpio"; + bias-disable; + drive-strengh = <16>; + output-high; + }; + + sel-pins { + pins = "gpio164"; + function = "gpio"; + bias-disable; + drive-strength = <16>; + }; + + mode-pins { + pins = "gpio167"; + function = "gpio"; + bias-disable; + drive-strength = <16>; + output-high; + }; + }; + + usb1_sbu_default: usb1-sbu-state { + oe-n-pins { + pins = "gpio48"; + function = "gpio"; + bias-disable; + drive-strengh = <16>; + output-high; + }; + + sel-pins { + pins = "gpio47"; + function = "gpio"; + bias-disable; + drive-strength = <16>; + }; + + mode-pins { + pins = "gpio50"; + function = "gpio"; + bias-disable; + drive-strength = <16>; + output-high; + }; + }; }; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index 568c6be1ceaa..98e71b933437 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -21,7 +21,38 @@ model = "Lenovo ThinkPad X13s"; compatible = "lenovo,thinkpad-x13s", "qcom,sc8280xp"; - backlight { + aliases { + i2c4 = &i2c4; + i2c21 = &i2c21; + }; + + wcd938x: audio-codec { + compatible = "qcom,wcd9380-codec"; + + pinctrl-names = "default"; + pinctrl-0 = <&wcd_default>; + + reset-gpios = <&tlmm 106 GPIO_ACTIVE_LOW>; + + vdd-buck-supply = <&vreg_s10b>; + vdd-rxtx-supply = <&vreg_s10b>; + vdd-io-supply = <&vreg_s10b>; + vdd-mic-bias-supply = <&vreg_bob>; + + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; + qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt = <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt = <50000>; + qcom,rx-device = <&wcd_rx>; + qcom,tx-device = <&wcd_tx>; + + #sound-dai-cells = <1>; + }; + + backlight: backlight { compatible = "pwm-backlight"; pwms = <&pmc8280c_lpg 3 1000000>; enable-gpios = <&pmc8280_1_gpios 8 GPIO_ACTIVE_HIGH>; @@ -31,65 +62,113 @@ pinctrl-0 = <&edp_bl_en>, <&edp_bl_pwm>; }; - thermal-zones { - skin-temp-thermal { - polling-delay-passive = <250>; - polling-delay = <0>; - thermal-sensors = <&pmk8280_adc_tm 5>; + gpio-keys { + compatible = "gpio-keys"; - trips { - skin_temp_alert0: trip-point0 { - temperature = <55000>; - hysteresis = <1000>; - type = "passive"; + pinctrl-names = "default"; + pinctrl-0 = <&hall_int_n_default>; + + switch-lid { + gpios = <&tlmm 107 GPIO_ACTIVE_LOW>; + linux,input-type = <EV_SW>; + linux,code = <SW_LID>; + wakeup-source; + wakeup-event-action = <EV_ACT_DEASSERTED>; + }; + }; + + pmic-glink { + compatible = "qcom,sc8280xp-pmic-glink", "qcom,pmic-glink"; + + #address-cells = <1>; + #size-cells = <0>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_con0_hs: endpoint { + remote-endpoint = <&usb_0_role_switch>; + }; }; - skin_temp_alert1: trip-point1 { - temperature = <58000>; - hysteresis = <1000>; - type = "passive"; + port@1 { + reg = <1>; + + pmic_glink_con0_ss: endpoint { + remote-endpoint = <&mdss0_dp0_out>; + }; }; - skin-temp-crit { - temperature = <73000>; - hysteresis = <1000>; - type = "critical"; + port@2 { + reg = <2>; + + pmic_glink_con0_sbu: endpoint { + remote-endpoint = <&usb0_sbu_mux>; + }; }; }; + }; - cooling-maps { - map0 { - trip = <&skin_temp_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + + pmic_glink_con1_hs: endpoint { + remote-endpoint = <&usb_1_role_switch>; + }; }; - map1 { - trip = <&skin_temp_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + port@1 { + reg = <1>; + + pmic_glink_con1_ss: endpoint { + remote-endpoint = <&mdss0_dp1_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_con1_sbu: endpoint { + remote-endpoint = <&usb1_sbu_mux>; + }; }; }; }; }; - gpio-keys { - compatible = "gpio-keys"; + vreg_edp_3p3: regulator-edp-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VCC3LCD"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 25 GPIO_ACTIVE_HIGH>; + enable-active-high; pinctrl-names = "default"; - pinctrl-0 = <&hall_int_n_default>; + pinctrl-0 = <&edp_reg_en>; - switch-lid { - gpios = <&tlmm 107 GPIO_ACTIVE_LOW>; - linux,input-type = <EV_SW>; - linux,code = <SW_LID>; - wakeup-source; - wakeup-event-action = <EV_ACT_DEASSERTED>; - }; + regulator-boot-on; }; vreg_edp_bl: regulator-edp-bl { @@ -141,6 +220,16 @@ regulator-boot-on; }; + vreg_vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + + regulator-name = "VPH_VCC3R9"; + regulator-min-microvolt = <3900000>; + regulator-max-microvolt = <3900000>; + + regulator-always-on; + }; + vreg_wlan: regulator-wlan { compatible = "regulator-fixed"; @@ -172,15 +261,117 @@ regulator-boot-on; }; + + reserved-memory { + linux,cma { + compatible = "shared-dma-pool"; + size = <0x0 0x8000000>; + reusable; + linux,cma-default; + }; + }; + + thermal-zones { + skin-temp-thermal { + polling-delay-passive = <250>; + polling-delay = <0>; + thermal-sensors = <&pmk8280_adc_tm 5>; + + trips { + skin_temp_alert0: trip-point0 { + temperature = <55000>; + hysteresis = <1000>; + type = "passive"; + }; + + skin_temp_alert1: trip-point1 { + temperature = <58000>; + hysteresis = <1000>; + type = "passive"; + }; + + skin-temp-crit { + temperature = <73000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&skin_temp_alert0>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + + map1 { + trip = <&skin_temp_alert1>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + + usb0-sbu-mux { + compatible = "pericom,pi3usb102", "gpio-sbu-mux"; + + enable-gpios = <&tlmm 101 GPIO_ACTIVE_LOW>; + select-gpios = <&tlmm 164 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&usb0_sbu_default>; + + mode-switch; + orientation-switch; + svid = /bits/ 16 <0xff01>; + + port { + usb0_sbu_mux: endpoint { + remote-endpoint = <&pmic_glink_con0_sbu>; + }; + }; + }; + + usb1-sbu-mux { + compatible = "pericom,pi3usb102", "gpio-sbu-mux"; + + enable-gpios = <&tlmm 48 GPIO_ACTIVE_LOW>; + select-gpios = <&tlmm 47 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&usb1_sbu_default>; + + mode-switch; + orientation-switch; + svid = /bits/ 16 <0xff01>; + + port { + usb1_sbu_mux: endpoint { + remote-endpoint = <&pmic_glink_con1_sbu>; + }; + }; + }; }; &apps_rsc { - pmc8280-1-rpmh-regulators { + regulators-0 { compatible = "qcom,pm8350-rpmh-regulators"; qcom,pmic-id = "b"; vdd-l3-l5-supply = <&vreg_s11b>; + vreg_s10b: smps10 { + regulator-name = "vreg_s10b"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + vreg_s11b: smps11 { regulator-name = "vreg_s11b"; regulator-min-microvolt = <1272000>; @@ -188,6 +379,13 @@ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; + vreg_s12b: smps12 { + regulator-name = "vreg_s12b"; + regulator-min-microvolt = <984000>; + regulator-max-microvolt = <984000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + vreg_l3b: ldo3 { regulator-name = "vreg_l3b"; regulator-min-microvolt = <1200000>; @@ -209,13 +407,13 @@ regulator-max-microvolt = <880000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; regulator-boot-on; - regulator-always-on; /* FIXME: VDD_A_EDP_0_0P9 */ }; }; - pmc8280c-rpmh-regulators { + regulators-1 { compatible = "qcom,pm8350c-rpmh-regulators"; qcom,pmic-id = "c"; + vdd-bob-supply = <&vreg_vph_pwr>; vreg_l1c: ldo1 { regulator-name = "vreg_l1c"; @@ -237,9 +435,16 @@ regulator-max-microvolt = <3072000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; }; + + vreg_bob: bob { + regulator-name = "vreg_bob"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + }; }; - pmc8280-2-rpmh-regulators { + regulators-2 { compatible = "qcom,pm8350-rpmh-regulators"; qcom,pmic-id = "d"; @@ -282,6 +487,148 @@ }; }; +&dispcc0 { + status = "okay"; +}; + +&mdss0 { + status = "okay"; +}; + +&mdss0_dp0 { + status = "okay"; +}; + +&mdss0_dp0_out { + data-lanes = <0 1>; + remote-endpoint = <&pmic_glink_con0_ss>; +}; + +&mdss0_dp1 { + status = "okay"; +}; + +&mdss0_dp1_out { + data-lanes = <0 1>; + remote-endpoint = <&pmic_glink_con1_ss>; +}; + +&mdss0_dp3 { + compatible = "qcom,sc8280xp-edp"; + + data-lanes = <0 1 2 3>; + + status = "okay"; + + aux-bus { + panel { + compatible = "edp-panel"; + + backlight = <&backlight>; + power-supply = <&vreg_edp_3p3>; + + ports { + port { + edp_panel_in: endpoint { + remote-endpoint = <&mdss0_dp3_out>; + }; + }; + }; + }; + }; + + ports { + port@1 { + reg = <1>; + mdss0_dp3_out: endpoint { + remote-endpoint = <&edp_panel_in>; + }; + }; + }; +}; + +&mdss0_dp3_phy { + vdda-phy-supply = <&vreg_l6b>; + vdda-pll-supply = <&vreg_l3b>; + + status = "okay"; +}; + +&i2c4 { + clock-frequency = <400000>; + + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_default>; + + status = "okay"; + + /* FIXME: verify */ + touchscreen@10 { + compatible = "hid-over-i2c"; + reg = <0x10>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 175 IRQ_TYPE_LEVEL_LOW>; + vdd-supply = <&vreg_misc_3p3>; + + pinctrl-names = "default"; + pinctrl-0 = <&ts0_default>; + }; +}; + +&i2c21 { + clock-frequency = <400000>; + + pinctrl-names = "default"; + pinctrl-0 = <&i2c21_default>; + + status = "okay"; + + touchpad@15 { + compatible = "hid-over-i2c"; + reg = <0x15>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 182 IRQ_TYPE_LEVEL_LOW>; + vdd-supply = <&vreg_misc_3p3>; + + pinctrl-names = "default"; + pinctrl-0 = <&tpad_default>; + + wakeup-source; + + status = "disabled"; + }; + + touchpad@2c { + compatible = "hid-over-i2c"; + reg = <0x2c>; + + hid-descr-addr = <0x20>; + interrupts-extended = <&tlmm 182 IRQ_TYPE_LEVEL_LOW>; + vdd-supply = <&vreg_misc_3p3>; + + pinctrl-names = "default"; + pinctrl-0 = <&tpad_default>; + + wakeup-source; + }; + + keyboard@68 { + compatible = "hid-over-i2c"; + reg = <0x68>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 104 IRQ_TYPE_LEVEL_LOW>; + vdd-supply = <&vreg_misc_3p3>; + + pinctrl-names = "default"; + pinctrl-0 = <&kybd_default>; + + wakeup-source; + }; +}; + &pcie2a { perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; @@ -501,98 +848,157 @@ status = "okay"; }; -&qup0_i2c4 { - clock-frequency = <400000>; - - pinctrl-names = "default"; - pinctrl-0 = <&qup0_i2c4_default>; - +&qup1 { status = "okay"; +}; - /* FIXME: verify */ - touchscreen@10 { - compatible = "hid-over-i2c"; - reg = <0x10>; +&qup2 { + status = "okay"; +}; - hid-descr-addr = <0x1>; - interrupts-extended = <&tlmm 175 IRQ_TYPE_LEVEL_LOW>; - vdd-supply = <&vreg_misc_3p3>; +&remoteproc_adsp { + firmware-name = "qcom/sc8280xp/LENOVO/21BX/qcadsp8280.mbn"; - pinctrl-names = "default"; - pinctrl-0 = <&ts0_default>; - }; + status = "okay"; }; -&qup1 { +&remoteproc_nsp0 { + firmware-name = "qcom/sc8280xp/LENOVO/21BX/qccdsp8280.mbn"; + status = "okay"; }; -&qup2 { +&rxmacro { status = "okay"; }; -&qup2_i2c5 { - clock-frequency = <400000>; +&sound { + compatible = "qcom,sc8280xp-sndcard"; + model = "SC8280XP-LENOVO-X13S"; + audio-routing = + "SpkrLeft IN", "WSA_SPK1 OUT", + "SpkrRight IN", "WSA_SPK2 OUT", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC2", "MIC BIAS2", + "VA DMIC0", "MIC BIAS1", + "VA DMIC1", "MIC BIAS1", + "VA DMIC2", "MIC BIAS3", + "TX DMIC0", "MIC BIAS1", + "TX DMIC1", "MIC BIAS2", + "TX DMIC2", "MIC BIAS3", + "TX SWR_ADC1", "ADC2_OUTPUT"; + + wcd-playback-dai-link { + link-name = "WCD Playback"; + cpu { + sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>; + }; - pinctrl-names = "default"; - pinctrl-0 = <&qup2_i2c5_default>; + codec { + sound-dai = <&wcd938x 0>, <&swr1 0>, <&rxmacro 0>; + }; - status = "okay"; + platform { + sound-dai = <&q6apm>; + }; + }; - touchpad@15 { - compatible = "hid-over-i2c"; - reg = <0x15>; + wcd-capture-dai-link { + link-name = "WCD Capture"; + cpu { + sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; - hid-descr-addr = <0x1>; - interrupts-extended = <&tlmm 182 IRQ_TYPE_LEVEL_LOW>; - vdd-supply = <&vreg_misc_3p3>; + codec { + sound-dai = <&wcd938x 1>, <&swr2 0>, <&txmacro 0>; + }; - pinctrl-names = "default"; - pinctrl-0 = <&tpad_default>; + platform { + sound-dai = <&q6apm>; + }; + }; - wakeup-source; + wsa-dai-link { + link-name = "WSA Playback"; + cpu { + sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; - status = "disabled"; - }; + codec { + sound-dai = <&left_spkr>, <&right_spkr>, <&swr0 0>, <&wsamacro 0>; + }; - touchpad@2c { - compatible = "hid-over-i2c"; - reg = <0x2c>; + platform { + sound-dai = <&q6apm>; + }; + }; - hid-descr-addr = <0x20>; - interrupts-extended = <&tlmm 182 IRQ_TYPE_LEVEL_LOW>; - vdd-supply = <&vreg_misc_3p3>; + va-dai-link { + link-name = "VA Capture"; + cpu { + sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; - pinctrl-names = "default"; - pinctrl-0 = <&tpad_default>; + platform { + sound-dai = <&q6apm>; + }; - wakeup-source; + codec { + sound-dai = <&vamacro 0>; + }; }; +}; - keyboard@68 { - compatible = "hid-over-i2c"; - reg = <0x68>; - - hid-descr-addr = <0x1>; - interrupts-extended = <&tlmm 104 IRQ_TYPE_LEVEL_LOW>; - vdd-supply = <&vreg_misc_3p3>; +&swr0 { + status = "okay"; + left_spkr: wsa8830-left@0,1 { + compatible = "sdw10217020200"; + reg = <0 1>; pinctrl-names = "default"; - pinctrl-0 = <&kybd_default>; + pinctrl-0 = <&spkr_1_sd_n_default>; + powerdown-gpios = <&tlmm 178 GPIO_ACTIVE_LOW>; + #thermal-sensor-cells = <0>; + sound-name-prefix = "SpkrLeft"; + #sound-dai-cells = <0>; + vdd-supply = <&vreg_s10b>; + }; - wakeup-source; + right_spkr: wsa8830-right@0,2 { + compatible = "sdw10217020200"; + reg = <0 2>; + pinctrl-names = "default"; + pinctrl-0 = <&spkr_2_sd_n_default>; + powerdown-gpios = <&tlmm 179 GPIO_ACTIVE_LOW>; + #thermal-sensor-cells = <0>; + sound-name-prefix = "SpkrRight"; + #sound-dai-cells = <0>; + vdd-supply = <&vreg_s10b>; }; }; -&remoteproc_adsp { - firmware-name = "qcom/sc8280xp/LENOVO/21BX/qcadsp8280.mbn"; - +&swr1 { status = "okay"; + + wcd_rx: wcd9380-rx@0,4 { + compatible = "sdw20217010d00"; + reg = <0 4>; + qcom,rx-port-mapping = <1 2 3 4 5>; + }; }; -&remoteproc_nsp0 { - firmware-name = "qcom/sc8280xp/LENOVO/21BX/qccdsp8280.mbn"; +&swr2 { + status = "okay"; + + wcd_tx: wcd9380-tx@0,3 { + compatible = "sdw20217010d00"; + reg = <0 3>; + qcom,tx-port-mapping = <1 1 2 3>; + }; +}; +&txmacro { status = "okay"; }; @@ -601,7 +1007,6 @@ }; &usb_0_dwc3 { - /* TODO: Define USB-C connector properly */ dr_mode = "host"; }; @@ -620,12 +1025,15 @@ status = "okay"; }; +&usb_0_role_switch { + remote-endpoint = <&pmic_glink_con0_hs>; +}; + &usb_1 { status = "okay"; }; &usb_1_dwc3 { - /* TODO: Define USB-C connector properly */ dr_mode = "host"; }; @@ -644,12 +1052,35 @@ status = "okay"; }; +&usb_1_role_switch { + remote-endpoint = <&pmic_glink_con1_hs>; +}; + +&vamacro { + pinctrl-0 = <&dmic01_default>, <&dmic02_default>; + pinctrl-names = "default"; + + vdd-micb-supply = <&vreg_s10b>; + + qcom,dmic-sample-rate = <600000>; + + status = "okay"; +}; + +&wsamacro { + status = "okay"; +}; + &xo_board_clk { clock-frequency = <38400000>; }; /* PINCTRL */ +&lpass_tlmm { + status = "okay"; +}; + &pmc8280_1_gpios { edp_bl_en: edp-bl-en-state { pins = "gpio8"; @@ -691,6 +1122,13 @@ &tlmm { gpio-reserved-ranges = <70 2>, <74 6>, <83 4>, <125 2>, <128 2>, <154 7>; + edp_reg_en: edp-reg-en-state { + pins = "gpio25"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + hall_int_n_default: hall-int-n-state { pins = "gpio107"; function = "gpio"; @@ -698,6 +1136,20 @@ bias-disable; }; + i2c4_default: i2c4-default-state { + pins = "gpio171", "gpio172"; + function = "qup4"; + drive-strength = <16>; + bias-disable; + }; + + i2c21_default: i2c21-default-state { + pins = "gpio81", "gpio82"; + function = "qup21"; + drive-strength = <16>; + bias-disable; + }; + kybd_default: kybd-default-state { disable-pins { pins = "gpio102"; @@ -794,18 +1246,24 @@ }; }; - qup0_i2c4_default: qup0-i2c4-default-state { - pins = "gpio171", "gpio172"; - function = "qup4"; - bias-disable; - drive-strength = <16>; + spkr_1_sd_n_default: spkr-1-sd-n-default-state { + perst-n-pins { + pins = "gpio178"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-high; + }; }; - qup2_i2c5_default: qup2-i2c5-default-state { - pins = "gpio81", "gpio82"; - function = "qup21"; - bias-disable; - drive-strength = <16>; + spkr_2_sd_n_default: spkr-2-sd-n-default-state { + perst-n-pins { + pins = "gpio179"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-high; + }; }; tpad_default: tpad-default-state { @@ -830,4 +1288,46 @@ drive-strength = <16>; }; }; + + usb0_sbu_default: usb0-sbu-state { + oe-n-pins { + pins = "gpio101"; + function = "gpio"; + bias-disable; + drive-strengh = <16>; + output-high; + }; + + sel-pins { + pins = "gpio164"; + function = "gpio"; + bias-disable; + drive-strength = <16>; + }; + }; + + usb1_sbu_default: usb1-sbu-state { + oe-n-pins { + pins = "gpio48"; + function = "gpio"; + bias-disable; + drive-strengh = <16>; + output-high; + }; + + sel-pins { + pins = "gpio47"; + function = "gpio"; + bias-disable; + drive-strength = <16>; + }; + }; + + wcd_default: wcd-default-state { + reset-pins { + pins = "gpio106"; + function = "gpio"; + bias-disable; + }; + }; }; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi index f2c0b71b5d8e..df7d28f7ae60 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi @@ -64,14 +64,14 @@ pmk8280_pon_pwrkey: pwrkey { compatible = "qcom,pmk8350-pwrkey"; - interrupts = <0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH>; + interrupts-extended = <&spmi_bus 0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH>; linux,code = <KEY_POWER>; status = "disabled"; }; pmk8280_pon_resin: resin { compatible = "qcom,pmk8350-resin"; - interrupts = <0x0 0x13 0x6 IRQ_TYPE_EDGE_BOTH>; + interrupts-extended = <&spmi_bus 0x0 0x13 0x6 IRQ_TYPE_EDGE_BOTH>; status = "disabled"; }; }; @@ -79,7 +79,7 @@ pmk8280_vadc: adc@3100 { compatible = "qcom,spmi-adc7"; reg = <0x3100>; - interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + interrupts-extended = <&spmi_bus 0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; #address-cells = <1>; #size-cells = <0>; #io-channel-cells = <1>; @@ -89,7 +89,7 @@ pmk8280_adc_tm: adc-tm@3400 { compatible = "qcom,spmi-adc-tm5-gen2"; reg = <0x3400>; - interrupts = <0x0 0x34 0x0 IRQ_TYPE_EDGE_RISING>; + interrupts-extended = <&spmi_bus 0x0 0x34 0x0 IRQ_TYPE_EDGE_RISING>; #address-cells = <1>; #size-cells = <0>; #thermal-sensor-cells = <1>; @@ -106,7 +106,7 @@ pm8280_1_temp_alarm: temp-alarm@a00 { compatible = "qcom,spmi-temp-alarm"; reg = <0xa00>; - interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + interrupts-extended = <&spmi_bus 0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; #thermal-sensor-cells = <0>; }; @@ -158,7 +158,7 @@ pm8280_2_temp_alarm: temp-alarm@a00 { compatible = "qcom,spmi-temp-alarm"; reg = <0xa00>; - interrupts = <0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + interrupts-extended = <&spmi_bus 0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; #thermal-sensor-cells = <0>; }; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 109c9d2b684d..0d02599d8867 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -4,14 +4,18 @@ * Copyright (c) 2022, Linaro Limited */ +#include <dt-bindings/clock/qcom,dispcc-sc8280xp.h> #include <dt-bindings/clock/qcom,gcc-sc8280xp.h> #include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/interconnect/qcom,osm-l3.h> #include <dt-bindings/interconnect/qcom,sc8280xp.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/mailbox/qcom-ipcc.h> +#include <dt-bindings/phy/phy-qcom-qmp.h> #include <dt-bindings/power/qcom-rpmpd.h> +#include <dt-bindings/soc/qcom,gpr.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> +#include <dt-bindings/sound/qcom,q6afe.h> #include <dt-bindings/thermal/thermal.h> / { @@ -33,186 +37,6 @@ }; }; - cpu0_opp_table: cpu0-opp-table { - compatible = "operating-points-v2"; - opp-shared; - - opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - opp-peak-kBps = <(300000 * 32)>; - }; - opp-403200000 { - opp-hz = /bits/ 64 <403200000>; - opp-peak-kBps = <(384000 * 32)>; - }; - opp-499200000 { - opp-hz = /bits/ 64 <499200000>; - opp-peak-kBps = <(480000 * 32)>; - }; - opp-595200000 { - opp-hz = /bits/ 64 <595200000>; - opp-peak-kBps = <(576000 * 32)>; - }; - opp-691200000 { - opp-hz = /bits/ 64 <691200000>; - opp-peak-kBps = <(672000 * 32)>; - }; - opp-806400000 { - opp-hz = /bits/ 64 <806400000>; - opp-peak-kBps = <(768000 * 32)>; - }; - opp-902400000 { - opp-hz = /bits/ 64 <902400000>; - opp-peak-kBps = <(864000 * 32)>; - }; - opp-1017600000 { - opp-hz = /bits/ 64 <1017600000>; - opp-peak-kBps = <(960000 * 32)>; - }; - opp-1113600000 { - opp-hz = /bits/ 64 <1113600000>; - opp-peak-kBps = <(1075200 * 32)>; - }; - opp-1209600000 { - opp-hz = /bits/ 64 <1209600000>; - opp-peak-kBps = <(1171200 * 32)>; - }; - opp-1324800000 { - opp-hz = /bits/ 64 <1324800000>; - opp-peak-kBps = <(1267200 * 32)>; - }; - opp-1440000000 { - opp-hz = /bits/ 64 <1440000000>; - opp-peak-kBps = <(1363200 * 32)>; - }; - opp-1555200000 { - opp-hz = /bits/ 64 <1555200000>; - opp-peak-kBps = <(1536000 * 32)>; - }; - opp-1670400000 { - opp-hz = /bits/ 64 <1670400000>; - opp-peak-kBps = <(1612800 * 32)>; - }; - opp-1785600000 { - opp-hz = /bits/ 64 <1785600000>; - opp-peak-kBps = <(1689600 * 32)>; - }; - opp-1881600000 { - opp-hz = /bits/ 64 <1881600000>; - opp-peak-kBps = <(1689600 * 32)>; - }; - opp-1996800000 { - opp-hz = /bits/ 64 <1996800000>; - opp-peak-kBps = <(1689600 * 32)>; - }; - opp-2112000000 { - opp-hz = /bits/ 64 <2112000000>; - opp-peak-kBps = <(1689600 * 32)>; - }; - opp-2227200000 { - opp-hz = /bits/ 64 <2227200000>; - opp-peak-kBps = <(1689600 * 32)>; - }; - opp-2342400000 { - opp-hz = /bits/ 64 <2342400000>; - opp-peak-kBps = <(1689600 * 32)>; - }; - opp-2438400000 { - opp-hz = /bits/ 64 <2438400000>; - opp-peak-kBps = <(1689600 * 32)>; - }; - }; - - cpu4_opp_table: cpu4-opp-table { - compatible = "operating-points-v2"; - opp-shared; - - opp-825600000 { - opp-hz = /bits/ 64 <825600000>; - opp-peak-kBps = <(768000 * 32)>; - }; - opp-940800000 { - opp-hz = /bits/ 64 <940800000>; - opp-peak-kBps = <(864000 * 32)>; - }; - opp-1056000000 { - opp-hz = /bits/ 64 <1056000000>; - opp-peak-kBps = <(960000 * 32)>; - }; - opp-1171200000 { - opp-hz = /bits/ 64 <1171200000>; - opp-peak-kBps = <(1171200 * 32)>; - }; - opp-1286400000 { - opp-hz = /bits/ 64 <1286400000>; - opp-peak-kBps = <(1267200 * 32)>; - }; - opp-1401600000 { - opp-hz = /bits/ 64 <1401600000>; - opp-peak-kBps = <(1363200 * 32)>; - }; - opp-1516800000 { - opp-hz = /bits/ 64 <1516800000>; - opp-peak-kBps = <(1459200 * 32)>; - }; - opp-1632000000 { - opp-hz = /bits/ 64 <1632000000>; - opp-peak-kBps = <(1612800 * 32)>; - }; - opp-1747200000 { - opp-hz = /bits/ 64 <1747200000>; - opp-peak-kBps = <(1689600 * 32)>; - }; - opp-1862400000 { - opp-hz = /bits/ 64 <1862400000>; - opp-peak-kBps = <(1689600 * 32)>; - }; - opp-1977600000 { - opp-hz = /bits/ 64 <1977600000>; - opp-peak-kBps = <(1689600 * 32)>; - }; - opp-2073600000 { - opp-hz = /bits/ 64 <2073600000>; - opp-peak-kBps = <(1689600 * 32)>; - }; - opp-2169600000 { - opp-hz = /bits/ 64 <2169600000>; - opp-peak-kBps = <(1689600 * 32)>; - }; - opp-2284800000 { - opp-hz = /bits/ 64 <2284800000>; - opp-peak-kBps = <(1689600 * 32)>; - }; - opp-2400000000 { - opp-hz = /bits/ 64 <2400000000>; - opp-peak-kBps = <(1689600 * 32)>; - }; - opp-2496000000 { - opp-hz = /bits/ 64 <2496000000>; - opp-peak-kBps = <(1689600 * 32)>; - }; - opp-2592000000 { - opp-hz = /bits/ 64 <2592000000>; - opp-peak-kBps = <(1689600 * 32)>; - }; - opp-2688000000 { - opp-hz = /bits/ 64 <2688000000>; - opp-peak-kBps = <(1689600 * 32)>; - }; - opp-2803200000 { - opp-hz = /bits/ 64 <2803200000>; - opp-peak-kBps = <(1689600 * 32)>; - }; - opp-2899200000 { - opp-hz = /bits/ 64 <2899200000>; - opp-peak-kBps = <(1689600 * 32)>; - }; - opp-2995200000 { - opp-hz = /bits/ 64 <2995200000>; - opp-peak-kBps = <(1689600 * 32)>; - }; - }; - cpus { #address-cells = <2>; #size-cells = <0>; @@ -232,9 +56,11 @@ #cooling-cells = <2>; L2_0: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; L3_0: l3-cache { compatible = "cache"; + cache-level = <3>; }; }; }; @@ -254,6 +80,7 @@ #cooling-cells = <2>; L2_100: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -273,6 +100,7 @@ #cooling-cells = <2>; L2_200: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -292,6 +120,7 @@ #cooling-cells = <2>; L2_300: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -311,6 +140,7 @@ #cooling-cells = <2>; L2_400: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -330,6 +160,7 @@ #cooling-cells = <2>; L2_500: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -349,6 +180,7 @@ #cooling-cells = <2>; L2_600: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -368,6 +200,7 @@ #cooling-cells = <2>; L2_700: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -528,6 +361,200 @@ reg = <0x0 0x80000000 0x0 0x0>; }; + cpu0_opp_table: opp-table-cpu0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-peak-kBps = <(300000 * 32)>; + }; + opp-403200000 { + opp-hz = /bits/ 64 <403200000>; + opp-peak-kBps = <(384000 * 32)>; + }; + opp-499200000 { + opp-hz = /bits/ 64 <499200000>; + opp-peak-kBps = <(480000 * 32)>; + }; + opp-595200000 { + opp-hz = /bits/ 64 <595200000>; + opp-peak-kBps = <(576000 * 32)>; + }; + opp-691200000 { + opp-hz = /bits/ 64 <691200000>; + opp-peak-kBps = <(672000 * 32)>; + }; + opp-806400000 { + opp-hz = /bits/ 64 <806400000>; + opp-peak-kBps = <(768000 * 32)>; + }; + opp-902400000 { + opp-hz = /bits/ 64 <902400000>; + opp-peak-kBps = <(864000 * 32)>; + }; + opp-1017600000 { + opp-hz = /bits/ 64 <1017600000>; + opp-peak-kBps = <(960000 * 32)>; + }; + opp-1113600000 { + opp-hz = /bits/ 64 <1113600000>; + opp-peak-kBps = <(1075200 * 32)>; + }; + opp-1209600000 { + opp-hz = /bits/ 64 <1209600000>; + opp-peak-kBps = <(1171200 * 32)>; + }; + opp-1324800000 { + opp-hz = /bits/ 64 <1324800000>; + opp-peak-kBps = <(1267200 * 32)>; + }; + opp-1440000000 { + opp-hz = /bits/ 64 <1440000000>; + opp-peak-kBps = <(1363200 * 32)>; + }; + opp-1555200000 { + opp-hz = /bits/ 64 <1555200000>; + opp-peak-kBps = <(1536000 * 32)>; + }; + opp-1670400000 { + opp-hz = /bits/ 64 <1670400000>; + opp-peak-kBps = <(1612800 * 32)>; + }; + opp-1785600000 { + opp-hz = /bits/ 64 <1785600000>; + opp-peak-kBps = <(1689600 * 32)>; + }; + opp-1881600000 { + opp-hz = /bits/ 64 <1881600000>; + opp-peak-kBps = <(1689600 * 32)>; + }; + opp-1996800000 { + opp-hz = /bits/ 64 <1996800000>; + opp-peak-kBps = <(1689600 * 32)>; + }; + opp-2112000000 { + opp-hz = /bits/ 64 <2112000000>; + opp-peak-kBps = <(1689600 * 32)>; + }; + opp-2227200000 { + opp-hz = /bits/ 64 <2227200000>; + opp-peak-kBps = <(1689600 * 32)>; + }; + opp-2342400000 { + opp-hz = /bits/ 64 <2342400000>; + opp-peak-kBps = <(1689600 * 32)>; + }; + opp-2438400000 { + opp-hz = /bits/ 64 <2438400000>; + opp-peak-kBps = <(1689600 * 32)>; + }; + }; + + cpu4_opp_table: opp-table-cpu4 { + compatible = "operating-points-v2"; + opp-shared; + + opp-825600000 { + opp-hz = /bits/ 64 <825600000>; + opp-peak-kBps = <(768000 * 32)>; + }; + opp-940800000 { + opp-hz = /bits/ 64 <940800000>; + opp-peak-kBps = <(864000 * 32)>; + }; + opp-1056000000 { + opp-hz = /bits/ 64 <1056000000>; + opp-peak-kBps = <(960000 * 32)>; + }; + opp-1171200000 { + opp-hz = /bits/ 64 <1171200000>; + opp-peak-kBps = <(1171200 * 32)>; + }; + opp-1286400000 { + opp-hz = /bits/ 64 <1286400000>; + opp-peak-kBps = <(1267200 * 32)>; + }; + opp-1401600000 { + opp-hz = /bits/ 64 <1401600000>; + opp-peak-kBps = <(1363200 * 32)>; + }; + opp-1516800000 { + opp-hz = /bits/ 64 <1516800000>; + opp-peak-kBps = <(1459200 * 32)>; + }; + opp-1632000000 { + opp-hz = /bits/ 64 <1632000000>; + opp-peak-kBps = <(1612800 * 32)>; + }; + opp-1747200000 { + opp-hz = /bits/ 64 <1747200000>; + opp-peak-kBps = <(1689600 * 32)>; + }; + opp-1862400000 { + opp-hz = /bits/ 64 <1862400000>; + opp-peak-kBps = <(1689600 * 32)>; + }; + opp-1977600000 { + opp-hz = /bits/ 64 <1977600000>; + opp-peak-kBps = <(1689600 * 32)>; + }; + opp-2073600000 { + opp-hz = /bits/ 64 <2073600000>; + opp-peak-kBps = <(1689600 * 32)>; + }; + opp-2169600000 { + opp-hz = /bits/ 64 <2169600000>; + opp-peak-kBps = <(1689600 * 32)>; + }; + opp-2284800000 { + opp-hz = /bits/ 64 <2284800000>; + opp-peak-kBps = <(1689600 * 32)>; + }; + opp-2400000000 { + opp-hz = /bits/ 64 <2400000000>; + opp-peak-kBps = <(1689600 * 32)>; + }; + opp-2496000000 { + opp-hz = /bits/ 64 <2496000000>; + opp-peak-kBps = <(1689600 * 32)>; + }; + opp-2592000000 { + opp-hz = /bits/ 64 <2592000000>; + opp-peak-kBps = <(1689600 * 32)>; + }; + opp-2688000000 { + opp-hz = /bits/ 64 <2688000000>; + opp-peak-kBps = <(1689600 * 32)>; + }; + opp-2803200000 { + opp-hz = /bits/ 64 <2803200000>; + opp-peak-kBps = <(1689600 * 32)>; + }; + opp-2899200000 { + opp-hz = /bits/ 64 <2899200000>; + opp-peak-kBps = <(1689600 * 32)>; + }; + opp-2995200000 { + opp-hz = /bits/ 64 <2995200000>; + opp-peak-kBps = <(1689600 * 32)>; + }; + }; + + qup_opp_table_100mhz: opp-table-qup100mhz { + compatible = "operating-points-v2"; + + opp-75000000 { + opp-hz = /bits/ 64 <75000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + }; + pmu { compatible = "arm,armv8-pmuv3"; interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; @@ -537,74 +564,60 @@ compatible = "arm,psci-1.0"; method = "smc"; - CPU_PD0: cpu0 { + CPU_PD0: power-domain-cpu0 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&LITTLE_CPU_SLEEP_0>; }; - CPU_PD1: cpu1 { + CPU_PD1: power-domain-cpu1 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&LITTLE_CPU_SLEEP_0>; }; - CPU_PD2: cpu2 { + CPU_PD2: power-domain-cpu2 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&LITTLE_CPU_SLEEP_0>; }; - CPU_PD3: cpu3 { + CPU_PD3: power-domain-cpu3 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&LITTLE_CPU_SLEEP_0>; }; - CPU_PD4: cpu4 { + CPU_PD4: power-domain-cpu4 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&BIG_CPU_SLEEP_0>; }; - CPU_PD5: cpu5 { + CPU_PD5: power-domain-cpu5 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&BIG_CPU_SLEEP_0>; }; - CPU_PD6: cpu6 { + CPU_PD6: power-domain-cpu6 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&BIG_CPU_SLEEP_0>; }; - CPU_PD7: cpu7 { + CPU_PD7: power-domain-cpu7 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&BIG_CPU_SLEEP_0>; }; - CLUSTER_PD: cpu-cluster0 { + CLUSTER_PD: power-domain-cpu-cluster0 { #power-domain-cells = <0>; domain-idle-states = <&CLUSTER_SLEEP_0>; }; }; - qup_opp_table_100mhz: qup-100mhz-opp-table { - compatible = "operating-points-v2"; - - opp-75000000 { - opp-hz = /bits/ 64 <75000000>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - required-opps = <&rpmhpd_opp_svs>; - }; - }; - reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -762,7 +775,7 @@ <0>, <0>, <0>, - <&usb_0_ssphy>, + <&usb_0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, <0>, <0>, <0>, @@ -770,7 +783,7 @@ <0>, <0>, <0>, - <&usb_1_ssphy>, + <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, <0>, <0>, <0>, @@ -813,7 +826,71 @@ status = "disabled"; - qup2_uart17: serial@884000 { + i2c16: i2c@880000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00880000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + spi16: spi@880000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00880000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + i2c17: i2c@884000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00884000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + spi17: spi@884000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00884000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + uart17: serial@884000 { compatible = "qcom,geni-uart"; reg = <0 0x00884000 0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; @@ -827,7 +904,103 @@ status = "disabled"; }; - qup2_i2c5: i2c@894000 { + i2c18: i2c@888000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00888000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + spi18: spi@888000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00888000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + i2c19: i2c@88c000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x0088c000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + spi19: spi@88c000 { + compatible = "qcom,geni-spi"; + reg = <0 0x0088c000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + i2c20: i2c@890000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00890000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + spi20: spi@890000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00890000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + i2c21: i2c@894000 { compatible = "qcom,geni-i2c"; reg = <0 0x00894000 0 0x4000>; clock-names = "se"; @@ -842,6 +1015,86 @@ interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; + + spi21: spi@894000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00894000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + i2c22: i2c@898000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00898000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; + interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + spi22: spi@898000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00898000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + i2c23: i2c@89c000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x0089c000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; + interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + spi23: spi@89c000 { + compatible = "qcom,geni-spi"; + reg = <0 0x0089c000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; }; qup0: geniqup@9c0000 { @@ -858,7 +1111,135 @@ status = "disabled"; - qup0_i2c4: i2c@990000 { + i2c0: i2c@980000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00980000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + spi0: spi@980000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00980000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + i2c1: i2c@984000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00984000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + spi1: spi@984000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00984000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + i2c2: i2c@988000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00988000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + spi2: spi@988000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00988000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + i2c3: i2c@98c000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x0098c000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + spi3: spi@98c000 { + compatible = "qcom,geni-spi"; + reg = <0 0x0098c000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + i2c4: i2c@990000 { compatible = "qcom,geni-i2c"; reg = <0 0x00990000 0 0x4000>; clock-names = "se"; @@ -873,6 +1254,118 @@ interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; + + spi4: spi@990000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00990000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + i2c5: i2c@994000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00994000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + spi5: spi@994000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00994000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + i2c6: i2c@998000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00998000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + spi6: spi@998000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00998000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + i2c7: i2c@99c000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x0099c000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + spi7: spi@99c000 { + compatible = "qcom,geni-spi"; + reg = <0 0x0099c000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; }; qup1: geniqup@ac0000 { @@ -888,6 +1381,269 @@ ranges; status = "disabled"; + + i2c8: i2c@a80000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a80000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + spi8: spi@a80000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a80000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + i2c9: i2c@a84000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a84000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + spi9: spi@a84000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a84000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + i2c10: i2c@a88000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a88000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + spi10: spi@a88000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a88000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + i2c11: i2c@a8c000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a8c000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + spi11: spi@a8c000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a8c000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + i2c12: i2c@a90000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a90000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + spi12: spi@a90000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a90000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + i2c13: i2c@a94000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a94000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + spi13: spi@a94000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a94000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + i2c14: i2c@a98000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a98000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + spi14: spi@a98000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a98000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + i2c15: i2c@a9c000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a9c000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + spi15: spi@a9c000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a9c000 0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + }; + + rng: rng@10d3000 { + compatible = "qcom,prng-ee"; + reg = <0 0x010d3000 0 0x1000>; + clocks = <&rpmhcc RPMH_HWKM_CLK>; + clock-names = "core"; }; pcie4: pcie@1c00000 { @@ -1670,45 +2426,396 @@ label = "lpass"; qcom,remote-pid = <2>; + + gpr { + compatible = "qcom,gpr"; + qcom,glink-channels = "adsp_apps"; + qcom,domain = <GPR_DOMAIN_ID_ADSP>; + qcom,intents = <512 20>; + #address-cells = <1>; + #size-cells = <0>; + + q6apm: service@1 { + compatible = "qcom,q6apm"; + reg = <GPR_APM_MODULE_IID>; + #sound-dai-cells = <0>; + qcom,protection-domain = "avs/audio", + "msm/adsp/audio_pd"; + q6apmdai: dais { + compatible = "qcom,q6apm-dais"; + iommus = <&apps_smmu 0x0c01 0x0>; + }; + + q6apmbedai: bedais { + compatible = "qcom,q6apm-lpass-dais"; + #sound-dai-cells = <1>; + }; + }; + + q6prm: service@2 { + compatible = "qcom,q6prm"; + reg = <GPR_PRM_MODULE_IID>; + qcom,protection-domain = "avs/audio", + "msm/adsp/audio_pd"; + q6prmcc: clock-controller { + compatible = "qcom,q6prm-lpass-clocks"; + #clock-cells = <2>; + }; + }; + }; }; }; - usb_0_qmpphy: phy-wrapper@88ec000 { - compatible = "qcom,sc8280xp-qmp-usb43dp-phy"; - reg = <0 0x088ec000 0 0x1e4>, - <0 0x088eb000 0 0x40>, - <0 0x088ed000 0 0x1c8>; + rxmacro: rxmacro@3200000 { + compatible = "qcom,sc8280xp-lpass-rx-macro"; + reg = <0 0x03200000 0 0x1000>; + clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&vamacro>; + clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; + assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + assigned-clock-rates = <19200000>, <19200000>; + + clock-output-names = "mclk"; + #clock-cells = <0>; + #sound-dai-cells = <1>; + + pinctrl-names = "default"; + pinctrl-0 = <&rx_swr_default>; + + status = "disabled"; + }; + + /* RX */ + swr1: soundwire-controller@3210000 { + compatible = "qcom,soundwire-v1.6.0"; + reg = <0 0x03210000 0 0x2000>; + interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rxmacro>; + clock-names = "iface"; + label = "RX"; + + qcom,din-ports = <0>; + qcom,dout-ports = <5>; + + qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>; + qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>; + qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>; + qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; + qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; + qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; + qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; + qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; + qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; + + #sound-dai-cells = <1>; #address-cells = <2>; - #size-cells = <2>; - ranges; + #size-cells = <0>; + + status = "disabled"; + }; + + txmacro: txmacro@3220000 { + compatible = "qcom,sc8280xp-lpass-tx-macro"; + reg = <0 0x03220000 0 0x1000>; + pinctrl-names = "default"; + pinctrl-0 = <&tx_swr_default>; + clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&vamacro>; + + clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; + assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + assigned-clock-rates = <19200000>, <19200000>; + clock-output-names = "mclk"; + + #clock-cells = <0>; + #sound-dai-cells = <1>; + + status = "disabled"; + }; + + wsamacro: codec@3240000 { + compatible = "qcom,sc8280xp-lpass-wsa-macro"; + reg = <0 0x03240000 0 0x1000>; + clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&vamacro>; + clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; + assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + assigned-clock-rates = <19200000>, <19200000>; + + #clock-cells = <0>; + clock-output-names = "mclk"; + #sound-dai-cells = <1>; + + pinctrl-names = "default"; + pinctrl-0 = <&wsa_swr_default>; + + status = "disabled"; + }; + + /* WSA */ + swr0: soundwire-controller@3250000 { + reg = <0 0x03250000 0 0x2000>; + compatible = "qcom,soundwire-v1.6.0"; + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&wsamacro>; + clock-names = "iface"; + + qcom,din-ports = <2>; + qcom,dout-ports = <6>; + + qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; + qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; + qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; + qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>; + qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + + #sound-dai-cells = <1>; + #address-cells = <2>; + #size-cells = <0>; + + status = "disabled"; + }; + + /* TX */ + swr2: soundwire-controller@3330000 { + compatible = "qcom,soundwire-v1.6.0"; + reg = <0 0x03330000 0 0x2000>; + interrupts-extended = <&intc GIC_SPI 959 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "core", "wake"; + + clocks = <&vamacro>; + clock-names = "iface"; + label = "TX"; + #sound-dai-cells = <1>; + #address-cells = <2>; + #size-cells = <0>; + + qcom,din-ports = <4>; + qcom,dout-ports = <0>; + qcom,ports-sinterval-low = /bits/ 8 <0x01 0x03 0x03 0x03>; + qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02 0x01>; + qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; + qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; + qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; + qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; + qcom,ports-word-length = /bits/ 8 <0xff 0x00 0xff 0xff>; + qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; + qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00 0x00>; + + status = "disabled"; + }; + + vamacro: codec@3370000 { + compatible = "qcom,sc8280xp-lpass-va-macro"; + reg = <0 0x03370000 0 0x1000>; + clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "mclk", "macro", "dcodec", "npl"; + assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + assigned-clock-rates = <19200000>; + + #clock-cells = <0>; + clock-output-names = "fsgen"; + #sound-dai-cells = <1>; + + status = "disabled"; + }; + + lpass_tlmm: pinctrl@33c0000 { + compatible = "qcom,sc8280xp-lpass-lpi-pinctrl"; + reg = <0 0x33c0000 0x0 0x20000>, + <0 0x3550000 0x0 0x10000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpass_tlmm 0 0 19>; + + clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "core", "audio"; + + status = "disabled"; + + tx_swr_default: tx-swr-default-state { + clk-pins { + pins = "gpio0"; + function = "swr_tx_clk"; + drive-strength = <2>; + slew-rate = <1>; + bias-disable; + }; + + data-pins { + pins = "gpio1", "gpio2"; + function = "swr_tx_data"; + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; + }; + }; + + rx_swr_default: rx-swr-default-state { + clk-pins { + pins = "gpio3"; + function = "swr_rx_clk"; + drive-strength = <2>; + slew-rate = <1>; + bias-disable; + }; + + data-pins { + pins = "gpio4", "gpio5"; + function = "swr_rx_data"; + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; + }; + }; + + dmic01_default: dmic01-default-state { + clk-pins { + pins = "gpio6"; + function = "dmic1_clk"; + drive-strength = <8>; + output-high; + }; + + data-pins { + pins = "gpio7"; + function = "dmic1_data"; + drive-strength = <8>; + input-enable; + }; + }; + + dmic01_sleep: dmic01-sleep-state { + clk-pins { + pins = "gpio6"; + function = "dmic1_clk"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + data-pins { + pins = "gpio7"; + function = "dmic1_data"; + drive-strength = <2>; + bias-pull-down; + input-enable; + }; + }; + + dmic02_default: dmic02-default-state { + clk-pins { + pins = "gpio8"; + function = "dmic2_clk"; + drive-strength = <8>; + output-high; + }; + + data-pins { + pins = "gpio9"; + function = "dmic2_data"; + drive-strength = <8>; + input-enable; + }; + }; + + dmic02_sleep: dmic02-sleep-state { + clk-pins { + pins = "gpio8"; + function = "dmic2_clk"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + data-pins { + pins = "gpio9"; + function = "dmic2_data"; + drive-strength = <2>; + bias-pull-down; + input-enable; + }; + }; + + wsa_swr_default: wsa-swr-default-state { + clk-pins { + pins = "gpio10"; + function = "wsa_swr_clk"; + drive-strength = <2>; + slew-rate = <1>; + bias-disable; + }; + + data-pins { + pins = "gpio11"; + function = "wsa_swr_data"; + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; + + }; + }; + + wsa2_swr_default: wsa2-swr-default-state { + clk-pins { + pins = "gpio15"; + function = "wsa2_swr_clk"; + drive-strength = <2>; + slew-rate = <1>; + bias-disable; + }; + + data-pins { + pins = "gpio16"; + function = "wsa2_swr_data"; + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; + }; + }; + }; + + usb_0_qmpphy: phy@88eb000 { + compatible = "qcom,sc8280xp-qmp-usb43dp-phy"; + reg = <0 0x088eb000 0 0x4000>; clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, - <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_USB4_EUD_CLKREF_CLK>, - <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; - clock-names = "aux", "ref_clk_src", "ref", "com_aux"; + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "aux", "ref", "com_aux", "usb3_pipe"; + + power-domains = <&gcc USB30_PRIM_GDSC>; resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, - <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; + <&gcc GCC_USB4_DP_PHY_PRIM_BCR>; reset-names = "phy", "common"; - power-domains = <&gcc USB30_PRIM_GDSC>; + #clock-cells = <1>; + #phy-cells = <1>; status = "disabled"; - - usb_0_ssphy: usb3-phy@88eb400 { - reg = <0 0x088eb400 0 0x100>, - <0 0x088eb600 0 0x3ec>, - <0 0x088ec400 0 0x364>, - <0 0x088eba00 0 0x100>, - <0 0x088ebc00 0 0x3ec>, - <0 0x088ec200 0 0x18>; - #phy-cells = <0>; - #clock-cells = <0>; - clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "usb0_phy_pipe_clk_src"; - }; }; usb_1_hsphy: phy@8902000 { @@ -1725,47 +2832,67 @@ status = "disabled"; }; - usb_1_qmpphy: phy-wrapper@8904000 { + usb_1_qmpphy: phy@8903000 { compatible = "qcom,sc8280xp-qmp-usb43dp-phy"; - reg = <0 0x08904000 0 0x1e4>, - <0 0x08903000 0 0x40>, - <0 0x08905000 0 0x1c8>; - #address-cells = <2>; - #size-cells = <2>; - ranges; + reg = <0 0x08903000 0 0x4000>; clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, - <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_USB4_CLKREF_CLK>, - <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; - clock-names = "aux", "ref_clk_src", "ref", "com_aux"; + <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; + clock-names = "aux", "ref", "com_aux", "usb3_pipe"; + + power-domains = <&gcc USB30_SEC_GDSC>; resets = <&gcc GCC_USB3_PHY_SEC_BCR>, <&gcc GCC_USB4_1_DP_PHY_PRIM_BCR>; reset-names = "phy", "common"; - power-domains = <&gcc USB30_SEC_GDSC>; + #clock-cells = <1>; + #phy-cells = <1>; status = "disabled"; + }; - usb_1_ssphy: usb3-phy@8903400 { - reg = <0 0x08903400 0 0x100>, - <0 0x08903600 0 0x3ec>, - <0 0x08904400 0 0x364>, - <0 0x08903a00 0 0x100>, - <0 0x08903c00 0 0x3ec>, - <0 0x08904200 0 0x18>; - #phy-cells = <0>; - #clock-cells = <0>; - clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "usb1_phy_pipe_clk_src"; - }; + mdss1_dp0_phy: phy@8909a00 { + compatible = "qcom,sc8280xp-dp-phy"; + reg = <0 0x08909a00 0 0x19c>, + <0 0x08909200 0 0xec>, + <0 0x08909600 0 0xec>, + <0 0x08909000 0 0x1c8>; + + clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&dispcc1 DISP_CC_MDSS_AHB_CLK>; + clock-names = "aux", "cfg_ahb"; + power-domains = <&rpmhpd SC8280XP_MX>; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + + mdss1_dp1_phy: phy@890ca00 { + compatible = "qcom,sc8280xp-dp-phy"; + reg = <0 0x0890ca00 0 0x19c>, + <0 0x0890c200 0 0xec>, + <0 0x0890c600 0 0xec>, + <0 0x0890c000 0 0x1c8>; + + clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>, + <&dispcc1 DISP_CC_MDSS_AHB_CLK>; + clock-names = "aux", "cfg_ahb"; + power-domains = <&rpmhpd SC8280XP_MX>; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; }; pmu@9091000 { compatible = "qcom,sc8280xp-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; - reg = <0 0x9091000 0 0x1000>; + reg = <0 0x09091000 0 0x1000>; interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; @@ -1894,6 +3021,7 @@ "ss_phy_irq"; power-domains = <&gcc USB30_PRIM_GDSC>; + required-opps = <&rpmhpd_opp_nom>; resets = <&gcc GCC_USB30_PRIM_BCR>; @@ -1910,8 +3038,13 @@ reg = <0 0x0a600000 0 0xcd00>; interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>; iommus = <&apps_smmu 0x820 0x0>; - phys = <&usb_0_hsphy>, <&usb_0_ssphy>; + phys = <&usb_0_hsphy>, <&usb_0_qmpphy QMP_USB43DP_USB3_PHY>; phy-names = "usb2-phy", "usb3-phy"; + + port { + usb_0_role_switch: endpoint { + }; + }; }; }; @@ -1948,6 +3081,7 @@ "ss_phy_irq"; power-domains = <&gcc USB30_SEC_GDSC>; + required-opps = <&rpmhpd_opp_nom>; resets = <&gcc GCC_USB30_SEC_BCR>; @@ -1964,11 +3098,497 @@ reg = <0 0x0a800000 0 0xcd00>; interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>; iommus = <&apps_smmu 0x860 0x0>; - phys = <&usb_1_hsphy>, <&usb_1_ssphy>; + phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; phy-names = "usb2-phy", "usb3-phy"; + + port { + usb_1_role_switch: endpoint { + }; + }; + }; + }; + + mdss0: display-subsystem@ae00000 { + compatible = "qcom,sc8280xp-mdss"; + reg = <0 0x0ae00000 0 0x1000>; + reg-names = "mdss"; + + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&dispcc0 DISP_CC_MDSS_AHB_CLK>, + <&dispcc0 DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", + "ahb", + "core"; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, + <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "mdp0-mem", "mdp1-mem"; + iommus = <&apps_smmu 0x1000 0x402>; + power-domains = <&dispcc0 MDSS_GDSC>; + resets = <&dispcc0 DISP_CC_MDSS_CORE_BCR>; + + interrupt-controller; + #interrupt-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + mdss0_mdp: display-controller@ae01000 { + compatible = "qcom,sc8280xp-dpu"; + reg = <0 0x0ae01000 0 0x8f000>, + <0 0x0aeb0000 0 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc0 DISP_CC_MDSS_AHB_CLK>, + <&dispcc0 DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc0 DISP_CC_MDSS_MDP_CLK>, + <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", + "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + interrupt-parent = <&mdss0>; + interrupts = <0>; + power-domains = <&rpmhpd SC8280XP_MMCX>; + + assigned-clocks = <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + operating-points-v2 = <&mdss0_mdp_opp_table>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss0_intf0_out: endpoint { + remote-endpoint = <&mdss0_dp0_in>; + }; + }; + + port@4 { + reg = <4>; + mdss0_intf4_out: endpoint { + remote-endpoint = <&mdss0_dp1_in>; + }; + }; + + port@5 { + reg = <5>; + mdss0_intf5_out: endpoint { + remote-endpoint = <&mdss0_dp3_in>; + }; + }; + + port@6 { + reg = <6>; + mdss0_intf6_out: endpoint { + remote-endpoint = <&mdss0_dp2_in>; + }; + }; + }; + + mdss0_mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-375000000 { + opp-hz = /bits/ 64 <375000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&rpmhpd_opp_turbo_l1>; + }; + }; + }; + + mdss0_dp0: displayport-controller@ae90000 { + compatible = "qcom,sc8280xp-dp"; + reg = <0 0xae90000 0 0x200>, + <0 0xae90200 0 0x200>, + <0 0xae90400 0 0x600>, + <0 0xae91000 0 0x400>, + <0 0xae91400 0 0x400>; + interrupt-parent = <&mdss0>; + interrupts = <12>; + clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, + <&dispcc0 DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK>, + <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, + <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; + clock-names = "core_iface", "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + + assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, + <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; + assigned-clock-parents = <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; + + phys = <&usb_0_qmpphy QMP_USB43DP_DP_PHY>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + operating-points-v2 = <&mdss0_dp0_opp_table>; + power-domains = <&rpmhpd SC8280XP_CX>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss0_dp0_in: endpoint { + remote-endpoint = <&mdss0_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss0_dp0_out: endpoint { + }; + }; + }; + + mdss0_dp0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss0_dp1: displayport-controller@ae98000 { + compatible = "qcom,sc8280xp-dp"; + reg = <0 0xae98000 0 0x200>, + <0 0xae98200 0 0x200>, + <0 0xae98400 0 0x600>, + <0 0xae99000 0 0x400>, + <0 0xae99400 0 0x400>; + interrupt-parent = <&mdss0>; + interrupts = <13>; + clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, + <&dispcc0 DISP_CC_MDSS_DPTX1_AUX_CLK>, + <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK>, + <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, + <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>; + clock-names = "core_iface", "core_aux", + "ctrl_link", + "ctrl_link_iface", "stream_pixel"; + + assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, + <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>; + assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; + + phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + operating-points-v2 = <&mdss0_dp1_opp_table>; + power-domains = <&rpmhpd SC8280XP_CX>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss0_dp1_in: endpoint { + remote-endpoint = <&mdss0_intf4_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss0_dp1_out: endpoint { + }; + }; + }; + + mdss0_dp1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss0_dp2: displayport-controller@ae9a000 { + compatible = "qcom,sc8280xp-dp"; + reg = <0 0xae9a000 0 0x200>, + <0 0xae9a200 0 0x200>, + <0 0xae9a400 0 0x600>, + <0 0xae9b000 0 0x400>, + <0 0xae9b400 0 0x400>; + + clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, + <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>, + <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK>, + <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, + <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>; + clock-names = "core_iface", "core_aux", + "ctrl_link", + "ctrl_link_iface", "stream_pixel"; + interrupt-parent = <&mdss0>; + interrupts = <14>; + phys = <&mdss0_dp2_phy>; + phy-names = "dp"; + power-domains = <&rpmhpd SC8280XP_MMCX>; + + assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, + <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>; + assigned-clock-parents = <&mdss0_dp2_phy 0>, <&mdss0_dp2_phy 1>; + operating-points-v2 = <&mdss0_dp2_opp_table>; + + #sound-dai-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss0_dp2_in: endpoint { + remote-endpoint = <&mdss0_intf6_out>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + + mdss0_dp2_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss0_dp3: displayport-controller@aea0000 { + compatible = "qcom,sc8280xp-dp"; + reg = <0 0xaea0000 0 0x200>, + <0 0xaea0200 0 0x200>, + <0 0xaea0400 0 0x600>, + <0 0xaea1000 0 0x400>, + <0 0xaea1400 0 0x400>; + + clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, + <&dispcc0 DISP_CC_MDSS_DPTX3_AUX_CLK>, + <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK>, + <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, + <&dispcc0 DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; + clock-names = "core_iface", "core_aux", + "ctrl_link", + "ctrl_link_iface", "stream_pixel"; + interrupt-parent = <&mdss0>; + interrupts = <15>; + phys = <&mdss0_dp3_phy>; + phy-names = "dp"; + power-domains = <&rpmhpd SC8280XP_MMCX>; + + assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, + <&dispcc0 DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; + assigned-clock-parents = <&mdss0_dp3_phy 0>, <&mdss0_dp3_phy 1>; + operating-points-v2 = <&mdss0_dp3_opp_table>; + + #sound-dai-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss0_dp3_in: endpoint { + remote-endpoint = <&mdss0_intf5_out>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + + mdss0_dp3_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; }; }; + mdss0_dp2_phy: phy@aec2a00 { + compatible = "qcom,sc8280xp-dp-phy"; + reg = <0 0x0aec2a00 0 0x19c>, + <0 0x0aec2200 0 0xec>, + <0 0x0aec2600 0 0xec>, + <0 0x0aec2000 0 0x1c8>; + + clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>, + <&dispcc0 DISP_CC_MDSS_AHB_CLK>; + clock-names = "aux", "cfg_ahb"; + power-domains = <&rpmhpd SC8280XP_MX>; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + + mdss0_dp3_phy: phy@aec5a00 { + compatible = "qcom,sc8280xp-dp-phy"; + reg = <0 0x0aec5a00 0 0x19c>, + <0 0x0aec5200 0 0xec>, + <0 0x0aec5600 0 0xec>, + <0 0x0aec5000 0 0x1c8>; + + clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_AUX_CLK>, + <&dispcc0 DISP_CC_MDSS_AHB_CLK>; + clock-names = "aux", "cfg_ahb"; + power-domains = <&rpmhpd SC8280XP_MX>; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + + dispcc0: clock-controller@af00000 { + compatible = "qcom,sc8280xp-dispcc0"; + reg = <0 0x0af00000 0 0x20000>; + + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, + <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, + <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, + <&mdss0_dp2_phy 0>, + <&mdss0_dp2_phy 1>, + <&mdss0_dp3_phy 0>, + <&mdss0_dp3_phy 1>, + <0>, + <0>, + <0>, + <0>; + power-domains = <&rpmhpd SC8280XP_MMCX>; + + #clock-cells = <1>; + #power-domain-cells = <1>; + #reset-cells = <1>; + + status = "disabled"; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sc8280xp-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; @@ -2056,7 +3676,7 @@ #thermal-sensor-cells = <1>; }; - aoss_qmp: power-controller@c300000 { + aoss_qmp: power-management@c300000 { compatible = "qcom,sc8280xp-aoss-qmp", "qcom,aoss-qmp"; reg = <0 0x0c300000 0 0x400>; interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; @@ -2082,8 +3702,8 @@ interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; qcom,ee = <0>; qcom,channel = <0>; - #address-cells = <1>; - #size-cells = <1>; + #address-cells = <2>; + #size-cells = <0>; interrupt-controller; #interrupt-cells = <4>; }; @@ -2591,6 +4211,479 @@ qcom,remote-pid = <12>; }; }; + + mdss1: display-subsystem@22000000 { + compatible = "qcom,sc8280xp-mdss"; + reg = <0 0x22000000 0 0x1000>; + reg-names = "mdss"; + + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&dispcc1 DISP_CC_MDSS_AHB_CLK>, + <&dispcc1 DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", + "ahb", + "core"; + interconnects = <&mmss_noc MASTER_MDP_CORE1_0 0 &mc_virt SLAVE_EBI1 0>, + <&mmss_noc MASTER_MDP_CORE1_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "mdp0-mem", "mdp1-mem"; + interrupts = <GIC_SPI 865 IRQ_TYPE_LEVEL_HIGH>; + + iommus = <&apps_smmu 0x1800 0x402>; + power-domains = <&dispcc1 MDSS_GDSC>; + resets = <&dispcc1 DISP_CC_MDSS_CORE_BCR>; + + interrupt-controller; + #interrupt-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + mdss1_mdp: display-controller@22001000 { + compatible = "qcom,sc8280xp-dpu"; + reg = <0 0x22001000 0 0x8f000>, + <0 0x220b0000 0 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc1 DISP_CC_MDSS_AHB_CLK>, + <&dispcc1 DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc1 DISP_CC_MDSS_MDP_CLK>, + <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", + "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + interrupt-parent = <&mdss1>; + interrupts = <0>; + power-domains = <&rpmhpd SC8280XP_MMCX>; + + assigned-clocks = <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + operating-points-v2 = <&mdss1_mdp_opp_table>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss1_intf0_out: endpoint { + remote-endpoint = <&mdss1_dp0_in>; + }; + }; + + port@4 { + reg = <4>; + mdss1_intf4_out: endpoint { + remote-endpoint = <&mdss1_dp1_in>; + }; + }; + + port@5 { + reg = <5>; + mdss1_intf5_out: endpoint { + remote-endpoint = <&mdss1_dp3_in>; + }; + }; + + port@6 { + reg = <6>; + mdss1_intf6_out: endpoint { + remote-endpoint = <&mdss1_dp2_in>; + }; + }; + }; + + mdss1_mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-375000000 { + opp-hz = /bits/ 64 <375000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&rpmhpd_opp_turbo_l1>; + }; + }; + }; + + mdss1_dp0: displayport-controller@22090000 { + compatible = "qcom,sc8280xp-dp"; + reg = <0 0x22090000 0 0x200>, + <0 0x22090200 0 0x200>, + <0 0x22090400 0 0x600>, + <0 0x22091000 0 0x400>, + <0 0x22091400 0 0x400>; + + clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, + <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK>, + <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, + <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; + clock-names = "core_iface", "core_aux", + "ctrl_link", + "ctrl_link_iface", "stream_pixel"; + interrupt-parent = <&mdss1>; + interrupts = <12>; + phys = <&mdss1_dp0_phy>; + phy-names = "dp"; + power-domains = <&rpmhpd SC8280XP_MMCX>; + + assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, + <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; + assigned-clock-parents = <&mdss1_dp0_phy 0>, <&mdss1_dp0_phy 1>; + operating-points-v2 = <&mdss1_dp0_opp_table>; + + #sound-dai-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss1_dp0_in: endpoint { + remote-endpoint = <&mdss1_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + + mdss1_dp0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + + }; + + mdss1_dp1: displayport-controller@22098000 { + compatible = "qcom,sc8280xp-dp"; + reg = <0 0x22098000 0 0x200>, + <0 0x22098200 0 0x200>, + <0 0x22098400 0 0x600>, + <0 0x22099000 0 0x400>, + <0 0x22099400 0 0x400>; + + clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, + <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>, + <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK>, + <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, + <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>; + clock-names = "core_iface", "core_aux", + "ctrl_link", + "ctrl_link_iface", "stream_pixel"; + interrupt-parent = <&mdss1>; + interrupts = <13>; + phys = <&mdss1_dp1_phy>; + phy-names = "dp"; + power-domains = <&rpmhpd SC8280XP_MMCX>; + + assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, + <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>; + assigned-clock-parents = <&mdss1_dp1_phy 0>, <&mdss1_dp1_phy 1>; + operating-points-v2 = <&mdss1_dp1_opp_table>; + + #sound-dai-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss1_dp1_in: endpoint { + remote-endpoint = <&mdss1_intf4_out>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + + mdss1_dp1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss1_dp2: displayport-controller@2209a000 { + compatible = "qcom,sc8280xp-dp"; + reg = <0 0x2209a000 0 0x200>, + <0 0x2209a200 0 0x200>, + <0 0x2209a400 0 0x600>, + <0 0x2209b000 0 0x400>, + <0 0x2209b400 0 0x400>; + + clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, + <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>, + <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK>, + <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, + <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>; + clock-names = "core_iface", "core_aux", + "ctrl_link", + "ctrl_link_iface", "stream_pixel"; + interrupt-parent = <&mdss1>; + interrupts = <14>; + phys = <&mdss1_dp2_phy>; + phy-names = "dp"; + power-domains = <&rpmhpd SC8280XP_MMCX>; + + assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, + <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>; + assigned-clock-parents = <&mdss1_dp2_phy 0>, <&mdss1_dp2_phy 1>; + operating-points-v2 = <&mdss1_dp2_opp_table>; + + #sound-dai-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss1_dp2_in: endpoint { + remote-endpoint = <&mdss1_intf6_out>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + + mdss1_dp2_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss1_dp3: displayport-controller@220a0000 { + compatible = "qcom,sc8280xp-dp"; + reg = <0 0x220a0000 0 0x200>, + <0 0x220a0200 0 0x200>, + <0 0x220a0400 0 0x600>, + <0 0x220a1000 0 0x400>, + <0 0x220a1400 0 0x400>; + + clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, + <&dispcc1 DISP_CC_MDSS_DPTX3_AUX_CLK>, + <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_CLK>, + <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, + <&dispcc1 DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; + clock-names = "core_iface", "core_aux", + "ctrl_link", + "ctrl_link_iface", "stream_pixel"; + interrupt-parent = <&mdss1>; + interrupts = <15>; + phys = <&mdss1_dp3_phy>; + phy-names = "dp"; + power-domains = <&rpmhpd SC8280XP_MMCX>; + + assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, + <&dispcc1 DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; + assigned-clock-parents = <&mdss1_dp3_phy 0>, <&mdss1_dp3_phy 1>; + operating-points-v2 = <&mdss1_dp3_opp_table>; + + #sound-dai-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss1_dp3_in: endpoint { + remote-endpoint = <&mdss1_intf5_out>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + + mdss1_dp3_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + }; + + mdss1_dp2_phy: phy@220c2a00 { + compatible = "qcom,sc8280xp-dp-phy"; + reg = <0 0x220c2a00 0 0x19c>, + <0 0x220c2200 0 0xec>, + <0 0x220c2600 0 0xec>, + <0 0x220c2000 0 0x1c8>; + + clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>, + <&dispcc1 DISP_CC_MDSS_AHB_CLK>; + clock-names = "aux", "cfg_ahb"; + power-domains = <&rpmhpd SC8280XP_MX>; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + + mdss1_dp3_phy: phy@220c5a00 { + compatible = "qcom,sc8280xp-dp-phy"; + reg = <0 0x220c5a00 0 0x19c>, + <0 0x220c5200 0 0xec>, + <0 0x220c5600 0 0xec>, + <0 0x220c5000 0 0x1c8>; + + clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_AUX_CLK>, + <&dispcc1 DISP_CC_MDSS_AHB_CLK>; + clock-names = "aux", "cfg_ahb"; + power-domains = <&rpmhpd SC8280XP_MX>; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + + dispcc1: clock-controller@22100000 { + compatible = "qcom,sc8280xp-dispcc1"; + reg = <0 0x22100000 0 0x20000>; + + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <0>, + <&mdss1_dp0_phy 0>, + <&mdss1_dp0_phy 1>, + <&mdss1_dp1_phy 0>, + <&mdss1_dp1_phy 1>, + <&mdss1_dp2_phy 0>, + <&mdss1_dp2_phy 1>, + <&mdss1_dp3_phy 0>, + <&mdss1_dp3_phy 1>, + <0>, + <0>, + <0>, + <0>; + power-domains = <&rpmhpd SC8280XP_MMCX>; + + #clock-cells = <1>; + #power-domain-cells = <1>; + #reset-cells = <1>; + + status = "disabled"; + }; + }; + + sound: sound { }; thermal-zones { diff --git a/arch/arm64/boot/dts/qcom/sdm450-motorola-ali.dts b/arch/arm64/boot/dts/qcom/sdm450-motorola-ali.dts new file mode 100644 index 000000000000..362be5719dd2 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm450-motorola-ali.dts @@ -0,0 +1,252 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Julian Braha <julianbraha@gmail.com> + */ +/dts-v1/; + +#include "msm8953.dtsi" +#include "pm8953.dtsi" +#include "pmi8950.dtsi" + +/delete-node/ &qseecom_mem; + +/ { + model = "Motorola Moto G6"; + compatible = "motorola,ali", "qcom,sdm450"; + chassis-type = "handset"; + qcom,msm-id = <338 0>; + qcom,board-id = <0x43 0xc200>; + + gpio-keys { + compatible = "gpio-keys"; + + key-volume-up { + label = "volume_up"; + gpios = <&tlmm 85 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + }; + }; + + reserved-memory { + qseecom_mem: qseecom@84300000 { + reg = <0x0 0x84300000 0x0 0x2000000>; + no-map; + }; + + ramoops@ef000000 { + compatible = "ramoops"; + reg = <0x0 0xef000000 0x0 0xc0000>; + console-size = <0x40000>; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-always-on; + regulator-boot-on; + }; +}; + +&hsusb_phy { + vdd-supply = <&pm8953_l3>; + vdda-pll-supply = <&pm8953_l7>; + vdda-phy-dpdm-supply = <&pm8953_l13>; + + status = "okay"; +}; + +&i2c_3 { + status = "okay"; + + touchscreen@38 { + compatible = "edt,edt-ft5406"; + reg = <0x38>; + interrupt-parent = <&tlmm>; + interrupts = <65 IRQ_TYPE_EDGE_FALLING>; + vcc-supply = <&pm8953_l10>; + + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_active &ts_reset_active>; + + reset-gpios = <&tlmm 64 GPIO_ACTIVE_LOW>; + touchscreen-size-x = <1080>; + touchscreen-size-y = <2160>; + }; +}; + +&pm8953_resin { + linux,code = <KEY_VOLUMEDOWN>; + status = "okay"; +}; + +&pmi8950_wled { + qcom,num-strings = <3>; + qcom,external-pfet; + qcom,cabc; + + status = "okay"; +}; + +&rpm_requests { + regulators { + compatible = "qcom,rpm-pm8953-regulators"; + + vdd_s1-supply = <&vph_pwr>; + vdd_s2-supply = <&vph_pwr>; + vdd_s3-supply = <&vph_pwr>; + vdd_s4-supply = <&vph_pwr>; + vdd_s5-supply = <&vph_pwr>; + vdd_s6-supply = <&vph_pwr>; + vdd_s7-supply = <&vph_pwr>; + vdd_l1-supply = <&pm8953_s3>; + vdd_l2_l3-supply = <&pm8953_s3>; + vdd_l4_l5_l6_l7_l16_l19-supply = <&pm8953_s4>; + vdd_l8_l11_l12_l13_l14_l15-supply = <&vph_pwr>; + vdd_l9_l10_l17_l18_l22-supply = <&vph_pwr>; + + pm8953_s1: s1 { + regulator-min-microvolt = <795000>; + regulator-max-microvolt = <1081000>; + }; + + pm8953_s3: s3 { + regulator-min-microvolt = <1224000>; + regulator-max-microvolt = <1224000>; + }; + + pm8953_s4: s4 { + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <2050000>; + }; + + pm8953_l1: l1 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1100000>; + }; + + pm8953_l2: l2 { + regulator-min-microvolt = <975000>; + regulator-max-microvolt = <1225000>; + }; + + pm8953_l3: l3 { + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <925000>; + }; + + pm8953_l5: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8953_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8953_l7: l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1900000>; + }; + + pm8953_l8: l8 { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + }; + + pm8953_l9: l9 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + }; + + pm8953_l10: l10 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pm8953_l11: l11 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + }; + + pm8953_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8953_l13: l13 { + regulator-min-microvolt = <3125000>; + regulator-max-microvolt = <3125000>; + }; + + pm8953_l16: l16 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8953_l17: l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pm8953_l19: l19 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1350000>; + }; + + pm8953_l22: l22 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2850000>; + }; + + pm8953_l23: l23 { + regulator-min-microvolt = <975000>; + regulator-max-microvolt = <1225000>; + }; + }; +}; + +&sdhc_1 { + vmmc-supply = <&pm8953_l8>; + vqmmc-supply = <&pm8953_l5>; + + status = "okay"; +}; + +&sdhc_2 { + vmmc-supply = <&pm8953_l11>; + vqmmc-supply = <&pm8953_l12>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_off>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <95 5>, <111 1>, <126 1>; + + ts_int_active: ts-int-active-state { + pins = "gpio65"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; + + ts_reset_active: ts-reset-active-state { + pins = "gpio64"; + function = "gpio"; + drive-strength = <0x08>; + bias-pull-up; + }; +}; + +&usb3 { + status = "okay"; +}; + +&usb3_dwc3 { + dr_mode = "peripheral"; +}; diff --git a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-ganges-kirin.dts b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-ganges-kirin.dts index 71b448978e88..9425b2d9536e 100644 --- a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-ganges-kirin.dts +++ b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-ganges-kirin.dts @@ -21,6 +21,11 @@ }; }; +/* Reserve a bigger chunk of RAM for the higher-res display */ +&cont_splash_mem { + reg = <0 0x9d400000 0 (2520 * 1080 * 4)>; +}; + /* Ganges devices feature a Novatek touchscreen instead. */ /delete-node/ &touchscreen; /delete-node/ &vreg_l18a_1v8; diff --git a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi index 3d2b08d551d0..e52580acd5c8 100644 --- a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi @@ -57,7 +57,7 @@ regulator-boot-on; }; - cam_vdig_imx300_219_vreg: cam_vdig_imx300_219_vreg { + cam_vdig_imx300_219_vreg: cam-vdig-imx300-219-regulator { compatible = "regulator-fixed"; regulator-name = "cam_vdig_imx300_219_vreg"; startup-delay-us = <0>; @@ -67,7 +67,7 @@ pinctrl-0 = <&cam_vdig_default>; }; - cam_vana_front_vreg: cam_vana_front_vreg { + cam_vana_front_vreg: cam-vana-front-regulator { compatible = "regulator-fixed"; regulator-name = "cam_vana_front_vreg"; startup-delay-us = <0>; @@ -77,7 +77,7 @@ pinctrl-0 = <&imx219_vana_default>; }; - cam_vana_rear_vreg: cam_vana_rear_vreg { + cam_vana_rear_vreg: cam-vana-rear-regulator { compatible = "regulator-fixed"; regulator-name = "cam_vana_rear_vreg"; startup-delay-us = <0>; @@ -133,15 +133,20 @@ status = "okay"; }; - debug_region@ffb00000 { + debug@ffb00000 { reg = <0x00 0xffb00000 0x00 0x100000>; no-map; }; - removed_region@85800000 { + reserved@85800000 { reg = <0x00 0x85800000 0x00 0x3700000>; no-map; }; + + cont_splash_mem: splash@9d400000 { + reg = <0 0x9d400000 0 (1920 * 1080 * 4)>; + no-map; + }; }; /* diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index 13e6a4fbba27..5827cda270a0 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -678,7 +678,7 @@ mnoc: interconnect@1745000 { compatible = "qcom,sdm660-mnoc"; - reg = <0x01745000 0xA010>; + reg = <0x01745000 0xa010>; #interconnect-cells = <1>; clock-names = "bus", "bus_a", "iface"; clocks = <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK>, @@ -1044,43 +1044,43 @@ opp-hz = /bits/ 64 <775000000>; opp-level = <RPM_SMD_LEVEL_TURBO>; opp-peak-kBps = <5412000>; - opp-supported-hw = <0xA2>; + opp-supported-hw = <0xa2>; }; opp-647000000 { opp-hz = /bits/ 64 <647000000>; opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; opp-peak-kBps = <4068000>; - opp-supported-hw = <0xFF>; + opp-supported-hw = <0xff>; }; opp-588000000 { opp-hz = /bits/ 64 <588000000>; opp-level = <RPM_SMD_LEVEL_NOM>; opp-peak-kBps = <3072000>; - opp-supported-hw = <0xFF>; + opp-supported-hw = <0xff>; }; opp-465000000 { opp-hz = /bits/ 64 <465000000>; opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; opp-peak-kBps = <2724000>; - opp-supported-hw = <0xFF>; + opp-supported-hw = <0xff>; }; opp-370000000 { opp-hz = /bits/ 64 <370000000>; opp-level = <RPM_SMD_LEVEL_SVS>; opp-peak-kBps = <2188000>; - opp-supported-hw = <0xFF>; + opp-supported-hw = <0xff>; }; opp-240000000 { opp-hz = /bits/ 64 <240000000>; opp-level = <RPM_SMD_LEVEL_LOW_SVS>; opp-peak-kBps = <1648000>; - opp-supported-hw = <0xFF>; + opp-supported-hw = <0xff>; }; opp-160000000 { opp-hz = /bits/ 64 <160000000>; opp-level = <RPM_SMD_LEVEL_MIN_SVS>; opp-peak-kBps = <1200000>; - opp-supported-hw = <0xFF>; + opp-supported-hw = <0xff>; }; }; }; @@ -1470,7 +1470,7 @@ }; }; - mdss: mdss@c900000 { + mdss: display-subsystem@c900000 { compatible = "qcom,mdss"; reg = <0x0c900000 0x1000>, <0x0c9b0000 0x1040>; @@ -1497,8 +1497,8 @@ ranges; status = "disabled"; - mdp: mdp@c901000 { - compatible = "qcom,mdp5"; + mdp: display-controller@c901000 { + compatible = "qcom,sdm630-mdp5", "qcom,mdp5"; reg = <0x0c901000 0x89000>; reg-names = "mdp_phys"; @@ -1572,7 +1572,8 @@ }; dsi0: dsi@c994000 { - compatible = "qcom,mdss-dsi-ctrl"; + compatible = "qcom,sdm660-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; reg = <0x0c994000 0x400>; reg-names = "dsi_ctrl"; @@ -2409,7 +2410,7 @@ type = "passive"; }; - cpu0_crit: cpu_crit { + cpu0_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -2430,7 +2431,7 @@ type = "passive"; }; - cpu1_crit: cpu_crit { + cpu1_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -2451,7 +2452,7 @@ type = "passive"; }; - cpu2_crit: cpu_crit { + cpu2_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -2472,7 +2473,7 @@ type = "passive"; }; - cpu3_crit: cpu_crit { + cpu3_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -2499,7 +2500,7 @@ type = "passive"; }; - pwr_cluster_crit: cpu_crit { + pwr_cluster_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; diff --git a/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts b/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts index 3fb513cad0a9..70e683b7e4fc 100644 --- a/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts +++ b/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts @@ -63,6 +63,21 @@ }; }; +&i2c_5 { + status = "okay"; + + nfc@28 { + compatible = "nxp,nq310", "nxp,nxp-nci-i2c"; + reg = <0x28>; + + interrupt-parent = <&tlmm>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; + + enable-gpios = <&tlmm 16 GPIO_ACTIVE_HIGH>; + firmware-gpios = <&tlmm 62 GPIO_ACTIVE_HIGH>; + }; +}; + &pm8953_resin { status = "okay"; linux,code = <KEY_VOLUMEDOWN>; diff --git a/arch/arm64/boot/dts/qcom/sdm632-motorola-ocean.dts b/arch/arm64/boot/dts/qcom/sdm632-motorola-ocean.dts new file mode 100644 index 000000000000..c82d6e628d2c --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm632-motorola-ocean.dts @@ -0,0 +1,291 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Gabriela David + */ +/dts-v1/; + +#include "sdm632.dtsi" +#include "pm8953.dtsi" +#include <dt-bindings/leds/common.h> + +/delete-node/ &cont_splash_mem; +/delete-node/ &qseecom_mem; + +/ { + model = "Motorola G7 Power"; + compatible = "motorola,ocean", "qcom,sdm632"; + chassis-type = "handset"; + qcom,msm-id = <349 0>; + qcom,board-id = <0x141 0xc100>; + qcom,pmic-id = <0x10016 0x25 0x00 0x00>; + + backlight: backlight { + compatible = "led-backlight"; + leds = <&led>; + }; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + framebuffer@90001000 { + compatible = "simple-framebuffer"; + reg = <0 0x90001000 0 (720 * 1520 * 3)>; + + width = <720>; + height = <1520>; + stride = <(720 * 3)>; + format = "r8g8b8"; + + power-domains = <&gcc MDSS_GDSC>; + + clocks = <&gcc GCC_MDSS_AHB_CLK>, + <&gcc GCC_MDSS_AXI_CLK>, + <&gcc GCC_MDSS_VSYNC_CLK>, + <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_BYTE0_CLK>, + <&gcc GCC_MDSS_PCLK0_CLK>, + <&gcc GCC_MDSS_ESC0_CLK>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_key_default>; + + key-volume-up { + label = "Volume Up"; + gpios = <&tlmm 85 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + }; + }; + + reserved-memory { + qseecom_mem: qseecom@84300000 { + reg = <0x0 0x84300000 0x0 0x2000000>; + no-map; + }; + + cont_splash_mem: cont-splash@90001000 { + reg = <0x0 0x90001000 0x0 (720 * 1520 * 3)>; + no-map; + }; + + reserved@eefa1800 { + reg = <0x00 0xeefa1800 0x00 0x5e800>; + no-map; + }; + + ramoops@ef000000 { + compatible = "ramoops"; + reg = <0x0 0xef000000 0x0 0xbf800>; + console-size = <0x40000>; + pmsg-size = <0x40000>; + record-size = <0x3f800>; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-always-on; + regulator-boot-on; + }; +}; + +&hsusb_phy { + vdd-supply = <&pm8953_l3>; + vdda-pll-supply = <&pm8953_l7>; + vdda-phy-dpdm-supply = <&pm8953_l13>; + + status = "okay"; +}; + +&i2c_3 { + status = "okay"; + + touchscreen@41 { + compatible = "ilitek,ili2117"; + reg = <0x41>; + + interrupt-parent = <&tlmm>; + interrupts = <65 IRQ_TYPE_EDGE_FALLING>; + + touchscreen-inverted-x; + }; +}; + +&i2c_5 { + status = "okay"; + + led-controller@36 { + compatible = "ti,lm3697"; + reg = <0x36>; + + #address-cells = <1>; + #size-cells = <0>; + + led: led@1 { + reg = <1>; + default-trigger = "backlight"; + function = LED_FUNCTION_BACKLIGHT; + led-sources = <0 1 2>; + }; + }; +}; + +&pm8953_resin { + linux,code = <KEY_VOLUMEDOWN>; + status = "okay"; +}; + +&rpm_requests { + regulators { + compatible = "qcom,rpm-pm8953-regulators"; + + vdd_l1-supply = <&pm8953_s3>; + vdd_l2_l3-supply = <&pm8953_s3>; + vdd_l4_l5_l6_l7_l16_l19-supply = <&pm8953_s4>; + vdd_l8_l11_l12_l13_l14_l15-supply = <&vph_pwr>; + vdd_l9_l10_l17_l18_l22-supply = <&vph_pwr>; + + pm8953_s3: s3 { + regulator-min-microvolt = <984000>; + regulator-max-microvolt = <1240000>; + }; + + pm8953_s4: s4 { + regulator-min-microvolt = <1036000>; + regulator-max-microvolt = <2040000>; + }; + + pm8953_l1: l1 { + regulator-min-microvolt = <975000>; + regulator-max-microvolt = <1050000>; + }; + + pm8953_l2: l2 { + regulator-min-microvolt = <975000>; + regulator-max-microvolt = <1175000>; + }; + + pm8953_l3: l3 { + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <925000>; + regulator-allow-set-load; + }; + + pm8953_l5: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8953_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + pm8953_l7: l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1900000>; + }; + + pm8953_l8: l8 { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + }; + + pm8953_l9: l9 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + }; + + pm8953_l10: l10 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3000000>; + }; + + pm8953_l11: l11 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + }; + + pm8953_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8953_l13: l13 { + regulator-min-microvolt = <3125000>; + regulator-max-microvolt = <3125000>; + }; + + pm8953_l16: l16 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8953_l17: l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pm8953_l18: l18 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2700000>; + regulator-always-on; + regulator-boot-on; + }; + + pm8953_l19: l19 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1350000>; + }; + + pm8953_l22: l22 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + pm8953_l23: l23 { + regulator-min-microvolt = <975000>; + regulator-max-microvolt = <1225000>; + }; + }; +}; + +&sdhc_1 { + vmmc-supply = <&pm8953_l8>; + vqmmc-supply = <&pm8953_l5>; + + status = "okay"; +}; + +&sdhc_2 { + vmmc-supply = <&pm8953_l11>; + vqmmc-supply = <&pm8953_l12>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <96 4>; +}; + +&usb3 { + status = "okay"; +}; + +&usb3_dwc3 { + dr_mode = "peripheral"; +}; diff --git a/arch/arm64/boot/dts/qcom/sdm660.dtsi b/arch/arm64/boot/dts/qcom/sdm660.dtsi index d52123cb5cd3..f0f27fc12c18 100644 --- a/arch/arm64/boot/dts/qcom/sdm660.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm660.dtsi @@ -37,35 +37,35 @@ opp-hz = /bits/ 64 <700000000>; opp-level = <RPM_SMD_LEVEL_TURBO>; opp-peak-kBps = <5184000>; - opp-supported-hw = <0xFF>; + opp-supported-hw = <0xff>; }; opp-647000000 { opp-hz = /bits/ 64 <647000000>; opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; opp-peak-kBps = <4068000>; - opp-supported-hw = <0xFF>; + opp-supported-hw = <0xff>; }; opp-588000000 { opp-hz = /bits/ 64 <588000000>; opp-level = <RPM_SMD_LEVEL_NOM>; opp-peak-kBps = <3072000>; - opp-supported-hw = <0xFF>; + opp-supported-hw = <0xff>; }; opp-465000000 { opp-hz = /bits/ 64 <465000000>; opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; opp-peak-kBps = <2724000>; - opp-supported-hw = <0xFF>; + opp-supported-hw = <0xff>; }; opp-370000000 { opp-hz = /bits/ 64 <370000000>; opp-level = <RPM_SMD_LEVEL_SVS>; opp-peak-kBps = <2188000>; - opp-supported-hw = <0xFF>; + opp-supported-hw = <0xff>; }; */ @@ -73,14 +73,14 @@ opp-hz = /bits/ 64 <266000000>; opp-level = <RPM_SMD_LEVEL_LOW_SVS>; opp-peak-kBps = <1648000>; - opp-supported-hw = <0xFF>; + opp-supported-hw = <0xff>; }; opp-160000000 { opp-hz = /bits/ 64 <160000000>; opp-level = <RPM_SMD_LEVEL_MIN_SVS>; opp-peak-kBps = <1200000>; - opp-supported-hw = <0xFF>; + opp-supported-hw = <0xff>; }; }; }; @@ -142,6 +142,8 @@ }; &mdp { + compatible = "qcom,sdm660-mdp5", "qcom,mdp5"; + ports { port@1 { reg = <1>; @@ -154,7 +156,8 @@ &mdss { dsi1: dsi@c996000 { - compatible = "qcom,mdss-dsi-ctrl"; + compatible = "qcom,sdm660-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; reg = <0x0c996000 0x400>; reg-names = "dsi_ctrl"; diff --git a/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts b/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts index cf2ae540db12..e3e61b9d1b9d 100644 --- a/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts +++ b/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts @@ -256,6 +256,7 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-enable-ramp-delay = <250>; + regulator-always-on; }; vreg_l9a_1p8: ldo9 { diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi index 47363fde64ac..02f14692dd9d 100644 --- a/arch/arm64/boot/dts/qcom/sdm670.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi @@ -401,6 +401,18 @@ #power-domain-cells = <1>; }; + qfprom: qfprom@784000 { + compatible = "qcom,sdm670-qfprom", "qcom,qfprom"; + reg = <0 0x00784000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + qusb2_hstx_trim: hstx-trim@1eb { + reg = <0x1eb 0x1>; + bits = <1 4>; + }; + }; + sdhc_1: mmc@7c4000 { compatible = "qcom,sdm670-sdhci", "qcom,sdhci-msm-v5"; reg = <0 0x007c4000 0 0x1000>, @@ -776,6 +788,55 @@ }; }; + mem_noc: interconnect@1380000 { + compatible = "qcom,sdm670-mem-noc"; + reg = <0 0x01380000 0 0x27200>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + dc_noc: interconnect@14e0000 { + compatible = "qcom,sdm670-dc-noc"; + reg = <0 0x014e0000 0 0x400>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + config_noc: interconnect@1500000 { + compatible = "qcom,sdm670-config-noc"; + reg = <0 0x01500000 0 0x5080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + system_noc: interconnect@1620000 { + compatible = "qcom,sdm670-system-noc"; + reg = <0 0x01620000 0 0x18080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre1_noc: interconnect@16e0000 { + compatible = "qcom,sdm670-aggre1-noc"; + reg = <0 0x016e0000 0 0x15080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre2_noc: interconnect@1700000 { + compatible = "qcom,sdm670-aggre2-noc"; + reg = <0 0x01700000 0 0x1f300>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mmss_noc: interconnect@1740000 { + compatible = "qcom,sdm670-mmss-noc"; + reg = <0 0x01740000 0 0x1c100>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + tlmm: pinctrl@3400000 { compatible = "qcom,sdm670-tlmm"; reg = <0 0x03400000 0 0xc00000>; @@ -928,6 +989,8 @@ resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + nvmem-cells = <&qusb2_hstx_trim>; + status = "disabled"; }; @@ -1069,6 +1132,13 @@ <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; }; + gladiator_noc: interconnect@17900000 { + compatible = "qcom,sdm670-gladiator-noc"; + reg = <0 0x17900000 0 0xd080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + apps_rsc: rsc@179c0000 { compatible = "qcom,rpmh-rsc"; reg = <0 0x179c0000 0 0x10000>, diff --git a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi index ca676e04687b..f2b48241d15c 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi @@ -339,7 +339,7 @@ &apps_rsc { - pm8998-rpmh-regulators { + regulators-0 { compatible = "qcom,pm8998-rpmh-regulators"; qcom,pmic-id = "a"; @@ -621,7 +621,7 @@ }; }; - pm8005-rpmh-regulators { + regulators-1 { compatible = "qcom,pm8005-rpmh-regulators"; qcom,pmic-id = "c"; @@ -756,8 +756,8 @@ ap_ts_i2c: &i2c14 { }; &ipa { + qcom,gsi-loader = "modem"; status = "okay"; - modem-init; }; &lpasscc { @@ -862,7 +862,7 @@ ap_ts_i2c: &i2c14 { pinctrl-0 = <&qup_uart6_4pin>; - bluetooth: wcn3990-bt { + bluetooth: bluetooth { compatible = "qcom,wcn3990-bt"; vddio-supply = <&src_pp1800_s4a>; vddxo-supply = <&pp1800_l7a_wcn3990>; @@ -995,108 +995,73 @@ ap_ts_i2c: &i2c14 { /* PINCTRL - additions to nodes defined in sdm845.dtsi */ &qspi_cs0 { - pinconf { - pins = "gpio90"; - bias-disable; - }; + bias-disable; }; &qspi_clk { - pinconf { - pins = "gpio95"; - bias-disable; - }; + bias-disable; }; &qspi_data01 { - pinconf { - pins = "gpio91", "gpio92"; - - /* High-Z when no transfers; nice to park the lines */ - bias-pull-up; - }; + /* High-Z when no transfers; nice to park the lines */ + bias-pull-up; }; &qup_i2c3_default { - pinconf { - pins = "gpio41", "gpio42"; - drive-strength = <2>; + drive-strength = <2>; - /* Has external pullup */ - bias-disable; - }; + /* Has external pullup */ + bias-disable; }; &qup_i2c11_default { - pinconf { - pins = "gpio31", "gpio32"; - drive-strength = <2>; + drive-strength = <2>; - /* Has external pullup */ - bias-disable; - }; + /* Has external pullup */ + bias-disable; }; &qup_i2c12_default { - pinconf { - pins = "gpio49", "gpio50"; - drive-strength = <2>; + drive-strength = <2>; - /* Has external pullup */ - bias-disable; - }; + /* Has external pullup */ + bias-disable; }; &qup_i2c14_default { - pinconf { - pins = "gpio33", "gpio34"; - drive-strength = <2>; + drive-strength = <2>; - /* Has external pullup */ - bias-disable; - }; + /* Has external pullup */ + bias-disable; }; &qup_spi0_default { - pinconf { - pins = "gpio0", "gpio1", "gpio2", "gpio3"; - drive-strength = <2>; - bias-disable; - }; + drive-strength = <2>; + bias-disable; }; &qup_spi5_default { - pinconf { - pins = "gpio85", "gpio86", "gpio87", "gpio88"; - drive-strength = <2>; - bias-disable; - }; + drive-strength = <2>; + bias-disable; }; &qup_spi10_default { - pinconf { - pins = "gpio53", "gpio54", "gpio55", "gpio56"; - drive-strength = <2>; - bias-disable; - }; + drive-strength = <2>; + bias-disable; }; -&qup_uart9_default { - pinconf-tx { - pins = "gpio4"; - drive-strength = <2>; - bias-disable; - }; +&qup_uart9_rx { + drive-strength = <2>; + bias-pull-up; +}; - pinconf-rx { - pins = "gpio5"; - drive-strength = <2>; - bias-pull-up; - }; +&qup_uart9_tx { + drive-strength = <2>; + bias-disable; }; /* PINCTRL - board-specific pinctrl */ -&pm8005_gpio { +&pm8005_gpios { gpio-line-names = "", "", "SLB", @@ -1130,7 +1095,7 @@ ap_ts_i2c: &i2c14 { }; }; -&pm8998_gpio { +&pm8998_gpios { gpio-line-names = "", "", "SW_CTRL", @@ -1180,243 +1145,153 @@ ap_ts_i2c: &i2c14 { output-low; }; - ap_edp_bklten: ap-edp-bklten { - pinmux { - pins = "gpio37"; - function = "gpio"; - }; - - pinconf { - pins = "gpio37"; - drive-strength = <2>; - bias-disable; - }; + ap_edp_bklten: ap-edp-bklten-state { + pins = "gpio37"; + function = "gpio"; + drive-strength = <2>; + bias-disable; }; - bios_flash_wp_r_l: bios-flash-wp-r-l { - pinmux { - pins = "gpio128"; - function = "gpio"; - input-enable; - }; - - pinconf { - pins = "gpio128"; - bias-disable; - }; + bios_flash_wp_r_l: bios-flash-wp-r-l-state { + pins = "gpio128"; + function = "gpio"; + input-enable; + bias-disable; }; - ec_ap_int_l: ec-ap-int-l { - pinmux { - pins = "gpio122"; - function = "gpio"; - input-enable; - }; - - pinconf { - pins = "gpio122"; - bias-pull-up; - }; + ec_ap_int_l: ec-ap-int-l-state { + pins = "gpio122"; + function = "gpio"; + input-enable; + bias-pull-up; }; - edp_brij_en: edp-brij-en { - pinmux { - pins = "gpio102"; - function = "gpio"; - }; - - pinconf { - pins = "gpio102"; - drive-strength = <2>; - bias-disable; - }; + edp_brij_en: edp-brij-en-state { + pins = "gpio102"; + function = "gpio"; + drive-strength = <2>; + bias-disable; }; - edp_brij_irq: edp-brij-irq { - pinmux { - pins = "gpio10"; - function = "gpio"; - }; - - pinconf { - pins = "gpio10"; - drive-strength = <2>; - bias-pull-down; - }; + edp_brij_irq: edp-brij-irq-state { + pins = "gpio10"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; }; - en_pp3300_dx_edp: en-pp3300-dx-edp { - pinmux { - pins = "gpio43"; - function = "gpio"; - }; - - pinconf { - pins = "gpio43"; - drive-strength = <2>; - bias-disable; - }; + en_pp3300_dx_edp: en-pp3300-dx-edp-state { + pins = "gpio43"; + function = "gpio"; + drive-strength = <2>; + bias-disable; }; - h1_ap_int_odl: h1-ap-int-odl { - pinmux { - pins = "gpio129"; - function = "gpio"; - input-enable; - }; - - pinconf { - pins = "gpio129"; - bias-pull-up; - }; + h1_ap_int_odl: h1-ap-int-odl-state { + pins = "gpio129"; + function = "gpio"; + input-enable; + bias-pull-up; }; - pen_eject_odl: pen-eject-odl { - pinmux { - pins = "gpio119"; - function = "gpio"; - bias-pull-up; - }; + pen_eject_odl: pen-eject-odl-state { + pins = "gpio119"; + function = "gpio"; + bias-pull-up; }; - pen_irq_l: pen-irq-l { - pinmux { - pins = "gpio24"; - function = "gpio"; - }; + pen_irq_l: pen-irq-l-state { + pins = "gpio24"; + function = "gpio"; - pinconf { - pins = "gpio24"; - - /* Has external pullup */ - bias-disable; - }; + /* Has external pullup */ + bias-disable; }; - pen_pdct_l: pen-pdct-l { - pinmux { - pins = "gpio63"; - function = "gpio"; - }; - - pinconf { - pins = "gpio63"; + pen_pdct_l: pen-pdct-l-state { + pins = "gpio63"; + function = "gpio"; - /* Has external pullup */ - bias-disable; - }; + /* Has external pullup */ + bias-disable; }; - pen_rst_l: pen-rst-l { - pinmux { - pins = "gpio23"; - function = "gpio"; - }; - - pinconf { - pins = "gpio23"; - bias-disable; - drive-strength = <2>; + pen_rst_l: pen-rst-l-state { + pins = "gpio23"; + function = "gpio"; + bias-disable; + drive-strength = <2>; - /* - * The pen driver doesn't currently support - * driving this reset line. By specifying - * output-high here we're relying on the fact - * that this pin has a default pulldown at boot - * (which makes sure the pen was in reset if it - * was powered) and then we set it high here to - * take it out of reset. Better would be if the - * pen driver could control this and we could - * remove "output-high" here. - */ - output-high; - }; + /* + * The pen driver doesn't currently support + * driving this reset line. By specifying + * output-high here we're relying on the fact + * that this pin has a default pulldown at boot + * (which makes sure the pen was in reset if it + * was powered) and then we set it high here to + * take it out of reset. Better would be if the + * pen driver could control this and we could + * remove "output-high" here. + */ + output-high; }; - sdc2_clk: sdc2-clk { - pinconf { - pins = "sdc2_clk"; - bias-disable; + sdc2_clk: sdc2-clk-state { + pins = "sdc2_clk"; + bias-disable; - /* - * It seems that mmc_test reports errors if drive - * strength is not 16. - */ - drive-strength = <16>; - }; + /* + * It seems that mmc_test reports errors if drive + * strength is not 16. + */ + drive-strength = <16>; }; - sdc2_cmd: sdc2-cmd { - pinconf { - pins = "sdc2_cmd"; - bias-pull-up; - drive-strength = <16>; - }; + sdc2_cmd: sdc2-cmd-state { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <16>; }; - sdc2_data: sdc2-data { - pinconf { - pins = "sdc2_data"; - bias-pull-up; - drive-strength = <16>; - }; + sdc2_data: sdc2-data-state { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <16>; }; - sd_cd_odl: sd-cd-odl { - pinmux { - pins = "gpio44"; - function = "gpio"; - }; - - pinconf { - pins = "gpio44"; - bias-pull-up; - }; + sd_cd_odl: sd-cd-odl-state { + pins = "gpio44"; + function = "gpio"; + bias-pull-up; }; - ts_int_l: ts-int-l { - pinmux { - pins = "gpio125"; - function = "gpio"; - }; - - pinconf { - pins = "gpio125"; - bias-pull-up; - }; + ts_int_l: ts-int-l-state { + pins = "gpio125"; + function = "gpio"; + bias-pull-up; }; - ts_reset_l: ts-reset-l { - pinmux { - pins = "gpio118"; - function = "gpio"; - }; - - pinconf { - pins = "gpio118"; - bias-disable; - drive-strength = <2>; - }; + ts_reset_l: ts-reset-l-state { + pins = "gpio118"; + function = "gpio"; + bias-disable; + drive-strength = <2>; }; - ap_suspend_l_assert: ap_suspend_l_assert { - config { - pins = "gpio126"; - function = "gpio"; - bias-disable; - drive-strength = <2>; - output-low; - }; + ap_suspend_l_assert: ap-suspend-l-assert-state { + pins = "gpio126"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + output-low; }; - ap_suspend_l_deassert: ap_suspend_l_deassert { - config { - pins = "gpio126"; - function = "gpio"; - bias-disable; - drive-strength = <2>; - output-high; - }; + ap_suspend_l_deassert: ap-suspend-l-deassert-state { + pins = "gpio126"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + output-high; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index f41c6d600ea8..d4866feef2c4 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -11,6 +11,7 @@ #include <dt-bindings/sound/qcom,q6afe.h> #include <dt-bindings/sound/qcom,q6asm.h> #include "sdm845.dtsi" +#include "sdm845-wcd9340.dtsi" #include "pm8998.dtsi" #include "pmi8998.dtsi" @@ -54,7 +55,7 @@ key-vol-up { label = "Volume Up"; linux,code = <KEY_VOLUMEUP>; - gpios = <&pm8998_gpio 6 GPIO_ACTIVE_LOW>; + gpios = <&pm8998_gpios 6 GPIO_ACTIVE_LOW>; }; }; @@ -65,7 +66,7 @@ label = "green:user4"; function = LED_FUNCTION_INDICATOR; color = <LED_COLOR_ID_GREEN>; - gpios = <&pm8998_gpio 13 GPIO_ACTIVE_HIGH>; + gpios = <&pm8998_gpios 13 GPIO_ACTIVE_HIGH>; linux,default-trigger = "panic-indicator"; default-state = "off"; }; @@ -74,7 +75,7 @@ label = "yellow:wlan"; function = LED_FUNCTION_WLAN; color = <LED_COLOR_ID_YELLOW>; - gpios = <&pm8998_gpio 9 GPIO_ACTIVE_HIGH>; + gpios = <&pm8998_gpios 9 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0tx"; default-state = "off"; }; @@ -83,7 +84,7 @@ label = "blue:bt"; function = LED_FUNCTION_BLUETOOTH; color = <LED_COLOR_ID_BLUE>; - gpios = <&pm8998_gpio 5 GPIO_ACTIVE_HIGH>; + gpios = <&pm8998_gpios 5 GPIO_ACTIVE_HIGH>; linux,default-trigger = "bluetooth-power"; default-state = "off"; }; @@ -142,32 +143,32 @@ */ }; - cam0_dvdd_1v2: reg_cam0_dvdd_1v2 { + cam0_dvdd_1v2: cam0-dvdd-1v2-regulator { compatible = "regulator-fixed"; regulator-name = "CAM0_DVDD_1V2"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; enable-active-high; - gpio = <&pm8998_gpio 12 GPIO_ACTIVE_HIGH>; + gpio = <&pm8998_gpios 12 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&cam0_dvdd_1v2_en_default>; vin-supply = <&vbat>; }; - cam0_avdd_2v8: reg_cam0_avdd_2v8 { + cam0_avdd_2v8: cam0-avdd-2v8-regulator { compatible = "regulator-fixed"; regulator-name = "CAM0_AVDD_2V8"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; enable-active-high; - gpio = <&pm8998_gpio 10 GPIO_ACTIVE_HIGH>; + gpio = <&pm8998_gpios 10 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&cam0_avdd_2v8_en_default>; vin-supply = <&vbat>; }; /* This regulator is enabled when the VREG_LVS1A_1P8 trace is enabled */ - cam3_avdd_2v8: reg_cam3_avdd_2v8 { + cam3_avdd_2v8: cam3-avdd-2v8-regulator { compatible = "regulator-fixed"; regulator-name = "CAM3_AVDD_2V8"; regulator-min-microvolt = <2800000>; @@ -269,7 +270,7 @@ }; &apps_rsc { - pm8998-rpmh-regulators { + regulators-0 { compatible = "qcom,pm8998-rpmh-regulators"; qcom,pmic-id = "a"; vdd-s1-supply = <&vph_pwr>; @@ -394,7 +395,7 @@ }; }; - pmi8998-rpmh-regulators { + regulators-1 { compatible = "qcom,pmi8998-rpmh-regulators"; qcom,pmic-id = "b"; @@ -506,14 +507,12 @@ &i2c11 { /* On Low speed expansion */ clock-frequency = <100000>; - label = "LS-I2C1"; status = "okay"; }; &i2c14 { /* On Low speed expansion */ clock-frequency = <100000>; - label = "LS-I2C0"; status = "okay"; }; @@ -559,7 +558,7 @@ vdda-pll-supply = <&vreg_l26a_1p2>; }; -&pm8998_gpio { +&pm8998_gpios { gpio-line-names = "NC", "NC", @@ -615,14 +614,9 @@ }; }; -&pm8998_pon { - resin { - compatible = "qcom,pm8941-resin"; - interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; - linux,code = <KEY_VOLUMEDOWN>; - }; +&pm8998_resin { + linux,code = <KEY_VOLUMEDOWN>; + status = "okay"; }; &pmi8998_lpg { @@ -709,7 +703,7 @@ }; &sound { - compatible = "qcom,db845c-sndcard"; + compatible = "qcom,db845c-sndcard", "qcom,sdm845-sndcard"; pinctrl-0 = <&quat_mi2s_active &quat_mi2s_sd0_active &quat_mi2s_sd1_active @@ -830,8 +824,8 @@ }; &tlmm { - cam0_default: cam0_default { - rst { + cam0_default: cam0-default-state { + rst-pins { pins = "gpio9"; function = "gpio"; @@ -839,7 +833,7 @@ bias-disable; }; - mclk0 { + mclk0-pins { pins = "gpio13"; function = "cam_mclk"; @@ -848,8 +842,8 @@ }; }; - cam3_default: cam3_default { - rst { + cam3_default: cam3-default-state { + rst-pins { function = "gpio"; pins = "gpio21"; @@ -857,7 +851,7 @@ bias-disable; }; - mclk3 { + mclk3-pins { function = "cam_mclk"; pins = "gpio16"; @@ -866,7 +860,7 @@ }; }; - dsi_sw_sel: dsi-sw-sel { + dsi_sw_sel: dsi-sw-sel-state { pins = "gpio120"; function = "gpio"; @@ -875,20 +869,20 @@ output-high; }; - lt9611_irq_pin: lt9611-irq { + lt9611_irq_pin: lt9611-irq-state { pins = "gpio84"; function = "gpio"; bias-disable; }; - pcie0_default_state: pcie0-default { - clkreq { + pcie0_default_state: pcie0-default-state { + clkreq-pins { pins = "gpio36"; function = "pci_e0"; bias-pull-up; }; - reset-n { + reset-n-pins { pins = "gpio35"; function = "gpio"; @@ -897,7 +891,7 @@ bias-pull-down; }; - wake-n { + wake-n-pins { pins = "gpio37"; function = "gpio"; @@ -906,7 +900,7 @@ }; }; - pcie0_pwren_state: pcie0-pwren { + pcie0_pwren_state: pcie0-pwren-state { pins = "gpio90"; function = "gpio"; @@ -914,8 +908,8 @@ bias-disable; }; - pcie1_default_state: pcie1-default { - perst-n { + pcie1_default_state: pcie1-default-state { + perst-n-pins { pins = "gpio102"; function = "gpio"; @@ -923,13 +917,13 @@ bias-disable; }; - clkreq { + clkreq-pins { pins = "gpio103"; function = "pci_e1"; bias-pull-up; }; - wake-n { + wake-n-pins { pins = "gpio11"; function = "gpio"; @@ -937,7 +931,7 @@ bias-pull-up; }; - reset-n { + reset-n-pins { pins = "gpio75"; function = "gpio"; @@ -947,8 +941,8 @@ }; }; - sdc2_default_state: sdc2-default { - clk { + sdc2_default_state: sdc2-default-state { + clk-pins { pins = "sdc2_clk"; bias-disable; @@ -959,37 +953,30 @@ drive-strength = <16>; }; - cmd { + cmd-pins { pins = "sdc2_cmd"; bias-pull-up; drive-strength = <10>; }; - data { + data-pins { pins = "sdc2_data"; bias-pull-up; drive-strength = <10>; }; }; - sdc2_card_det_n: sd-card-det-n { + sdc2_card_det_n: sd-card-det-n-state { pins = "gpio126"; function = "gpio"; bias-pull-up; }; - - wcd_intr_default: wcd_intr_default { - pins = <54>; - function = "gpio"; - - input-enable; - bias-pull-down; - drive-strength = <2>; - }; }; &uart3 { label = "LS-UART0"; + pinctrl-0 = <&qup_uart3_4pin>; + status = "disabled"; }; @@ -1089,10 +1076,6 @@ }; &wcd9340 { - pinctrl-0 = <&wcd_intr_default>; - pinctrl-names = "default"; - clock-names = "extclk"; - clocks = <&rpmhcc RPMH_LN_BB_CLK2>; reset-gpios = <&tlmm 64 GPIO_ACTIVE_HIGH>; vdd-buck-supply = <&vreg_s4a_1p8>; vdd-buck-sido-supply = <&vreg_s4a_1p8>; @@ -1135,49 +1118,30 @@ /* PINCTRL - additions to nodes defined in sdm845.dtsi */ &qup_spi2_default { - pinconf { - pins = "gpio27", "gpio28", "gpio29", "gpio30"; - drive-strength = <16>; - }; -}; - -&qup_uart3_default { - pinmux { - pins = "gpio41", "gpio42", "gpio43", "gpio44"; - function = "qup3"; - }; + drive-strength = <16>; }; &qup_i2c10_default { - pinconf { - pins = "gpio55", "gpio56"; - drive-strength = <2>; - bias-disable; - }; + drive-strength = <2>; + bias-disable; }; -&qup_uart9_default { - pinconf-tx { - pins = "gpio4"; - drive-strength = <2>; - bias-disable; - }; +&qup_uart9_rx { + drive-strength = <2>; + bias-pull-up; +}; - pinconf-rx { - pins = "gpio5"; - drive-strength = <2>; - bias-pull-up; - }; +&qup_uart9_tx { + drive-strength = <2>; + bias-disable; }; -&pm8998_gpio { +&pm8998_gpios { }; /* PINCTRL - additions to nodes defined in sdm845.dtsi */ &qup_spi0_default { - config { - drive-strength = <6>; - bias-disable; - }; + drive-strength = <6>; + bias-disable; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi index 1eb423e4be24..f942c5afea9b 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi @@ -132,7 +132,7 @@ key-vol-up { label = "Volume up"; linux,code = <KEY_VOLUMEUP>; - gpios = <&pm8998_gpio 6 GPIO_ACTIVE_LOW>; + gpios = <&pm8998_gpios 6 GPIO_ACTIVE_LOW>; }; }; @@ -166,7 +166,7 @@ }; &apps_rsc { - pm8998-rpmh-regulators { + regulators-0 { compatible = "qcom,pm8998-rpmh-regulators"; qcom,pmic-id = "a"; @@ -419,7 +419,7 @@ }; }; - pmi8998-rpmh-regulators { + regulators-1 { compatible = "qcom,pmi8998-rpmh-regulators"; qcom,pmic-id = "b"; @@ -433,7 +433,7 @@ }; }; - pm8005-rpmh-regulators { + regulators-2 { compatible = "qcom,pm8005-rpmh-regulators"; qcom,pmic-id = "c"; @@ -474,22 +474,17 @@ }; &ipa { + qcom,gsi-loader = "modem"; status = "okay"; - modem-init; }; &mss_pil { status = "okay"; }; -&pm8998_pon { - resin { - compatible = "qcom,pm8941-resin"; - interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; - linux,code = <KEY_VOLUMEDOWN>; - }; +&pm8998_resin { + linux,code = <KEY_VOLUMEDOWN>; + status = "okay"; }; &sdhc_2 { @@ -558,52 +553,40 @@ &tlmm { gpio-reserved-ranges = <28 4>, <81 4>; - sdc2_clk: sdc2-clk { - pinconf { - pins = "sdc2_clk"; - bias-disable; - - /* - * It seems that mmc_test reports errors if drive - * strength is not 16 on clk, cmd, and data pins. - * - * TODO: copy-pasted from mtp, try other values - * on these devices. - */ - drive-strength = <16>; - }; + sdc2_clk: sdc2-clk-state { + pins = "sdc2_clk"; + bias-disable; + + /* + * It seems that mmc_test reports errors if drive + * strength is not 16 on clk, cmd, and data pins. + * + * TODO: copy-pasted from mtp, try other values + * on these devices. + */ + drive-strength = <16>; }; - sdc2_cmd: sdc2-cmd { - pinconf { - pins = "sdc2_cmd"; - bias-pull-up; - drive-strength = <16>; - }; + sdc2_cmd: sdc2-cmd-state { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <16>; }; - sdc2_data: sdc2-data { - pinconf { - pins = "sdc2_data"; - bias-pull-up; - drive-strength = <16>; - }; + sdc2_data: sdc2-data-state { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <16>; }; - sd_card_det_n: sd-card-det-n { - pinmux { - pins = "gpio126"; - function = "gpio"; - }; - - pinconf { - pins = "gpio126"; - bias-pull-up; - }; + sd_card_det_n: sd-card-det-n-state { + pins = "gpio126"; + function = "gpio"; + bias-pull-up; }; }; -&pm8998_gpio { +&pm8998_gpios { vol_up_pin_a: vol-up-active-state { pins = "gpio6"; function = "normal"; diff --git a/arch/arm64/boot/dts/qcom/sdm845-lg-judyln.dts b/arch/arm64/boot/dts/qcom/sdm845-lg-judyln.dts index 7d967a104b3e..a12723310c8b 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-lg-judyln.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-lg-judyln.dts @@ -58,7 +58,7 @@ }; &tlmm { - thinq_key_default: thinq-key-default { + thinq_key_default: thinq-key-default-state { pins = "gpio89"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts index de2d10e0315a..d1440b790fa6 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts @@ -117,7 +117,7 @@ }; &apps_rsc { - pm8998-rpmh-regulators { + regulators-0 { compatible = "qcom,pm8998-rpmh-regulators"; qcom,pmic-id = "a"; @@ -382,7 +382,7 @@ }; }; - pmi8998-rpmh-regulators { + regulators-1 { compatible = "qcom,pmi8998-rpmh-regulators"; qcom,pmic-id = "b"; @@ -396,7 +396,7 @@ }; }; - pm8005-rpmh-regulators { + regulators-2 { compatible = "qcom,pm8005-rpmh-regulators"; qcom,pmic-id = "c"; @@ -518,8 +518,9 @@ }; &ipa { - status = "okay"; + qcom,gsi-loader = "self"; memory-region = <&ipa_fw_mem>; + status = "okay"; }; &mdss { @@ -719,68 +720,49 @@ /* PINCTRL - additions to nodes defined in sdm845.dtsi */ &qup_i2c10_default { - pinconf { - pins = "gpio55", "gpio56"; - drive-strength = <2>; - bias-disable; - }; + drive-strength = <2>; + bias-disable; }; -&qup_uart9_default { - pinconf-tx { - pins = "gpio4"; - drive-strength = <2>; - bias-disable; - }; +&qup_uart9_rx { + drive-strength = <2>; + bias-pull-up; +}; - pinconf-rx { - pins = "gpio5"; - drive-strength = <2>; - bias-pull-up; - }; +&qup_uart9_tx { + drive-strength = <2>; + bias-disable; }; &tlmm { gpio-reserved-ranges = <0 4>, <81 4>; - sdc2_clk: sdc2-clk { - pinconf { - pins = "sdc2_clk"; - bias-disable; + sdc2_clk: sdc2-clk-state { + pins = "sdc2_clk"; + bias-disable; - /* - * It seems that mmc_test reports errors if drive - * strength is not 16 on clk, cmd, and data pins. - */ - drive-strength = <16>; - }; + /* + * It seems that mmc_test reports errors if drive + * strength is not 16 on clk, cmd, and data pins. + */ + drive-strength = <16>; }; - sdc2_cmd: sdc2-cmd { - pinconf { - pins = "sdc2_cmd"; - bias-pull-up; - drive-strength = <16>; - }; + sdc2_cmd: sdc2-cmd-state { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <16>; }; - sdc2_data: sdc2-data { - pinconf { - pins = "sdc2_data"; - bias-pull-up; - drive-strength = <16>; - }; + sdc2_data: sdc2-data-state { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <16>; }; - sd_card_det_n: sd-card-det-n { - pinmux { - pins = "gpio126"; - function = "gpio"; - }; - - pinconf { - pins = "gpio126"; - bias-pull-up; - }; + sd_card_det_n: sd-card-det-n-state { + pins = "gpio126"; + function = "gpio"; + bias-pull-up; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi index 42cf4dd5ea28..64638ea94db7 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi @@ -9,8 +9,11 @@ #include <dt-bindings/input/linux-event-codes.h> #include <dt-bindings/regulator/qcom,rpmh-regulator.h> +#include <dt-bindings/sound/qcom,q6afe.h> +#include <dt-bindings/sound/qcom,q6asm.h> #include "sdm845.dtsi" +#include "sdm845-wcd9340.dtsi" #include "pm8998.dtsi" #include "pmi8998.dtsi" @@ -37,14 +40,14 @@ key-vol-down { label = "Volume down"; linux,code = <KEY_VOLUMEDOWN>; - gpios = <&pm8998_gpio 5 GPIO_ACTIVE_LOW>; + gpios = <&pm8998_gpios 5 GPIO_ACTIVE_LOW>; debounce-interval = <15>; }; key-vol-up { label = "Volume up"; linux,code = <KEY_VOLUMEUP>; - gpios = <&pm8998_gpio 6 GPIO_ACTIVE_LOW>; + gpios = <&pm8998_gpios 6 GPIO_ACTIVE_LOW>; debounce-interval = <15>; }; }; @@ -145,7 +148,7 @@ }; &apps_rsc { - pm8998-rpmh-regulators { + regulators-0 { compatible = "qcom,pm8998-rpmh-regulators"; qcom,pmic-id = "a"; @@ -281,7 +284,7 @@ }; }; - pmi8998-rpmh-regulators { + regulators-1 { compatible = "qcom,pmi8998-rpmh-regulators"; qcom,pmic-id = "b"; @@ -295,7 +298,7 @@ }; }; - pm8005-rpmh-regulators { + regulators-2 { compatible = "qcom,pm8005-rpmh-regulators"; qcom,pmic-id = "c"; @@ -424,10 +427,10 @@ }; &ipa { - status = "okay"; - + qcom,gsi-loader = "self"; memory-region = <&ipa_fw_mem>; firmware-name = "qcom/sdm845/oneplus6/ipa_fws.mbn"; + status = "okay"; }; &mdss { @@ -440,7 +443,7 @@ firmware-name = "qcom/sdm845/oneplus6/mba.mbn", "qcom/sdm845/oneplus6/modem.mbn"; }; -&pm8998_gpio { +&pm8998_gpios { volume_down_gpio: pm8998-gpio5-state { pinconf { pins = "gpio5"; @@ -466,6 +469,44 @@ status = "okay"; }; +&q6afedai { + qi2s@22 { + reg = <22>; + qcom,sd-lines = <1>; + }; + + qi2s@23 { + reg = <23>; + qcom,sd-lines = <0>; + }; +}; + +&q6asmdai { + dai@0 { + reg = <0>; + }; + + dai@1 { + reg = <1>; + }; + + dai@2 { + reg = <2>; + }; + + dai@3 { + reg = <3>; + }; + + dai@4 { + reg = <4>; + }; + + dai@5 { + reg = <5>; + }; +}; + &qupv3_id_1 { status = "okay"; }; @@ -474,34 +515,158 @@ status = "okay"; }; +&qup_i2c10_default { + drive-strength = <2>; + bias-disable; +}; + &qup_i2c12_default { - mux { - pins = "gpio49", "gpio50"; - function = "qup12"; - drive-strength = <2>; - bias-disable; - }; + drive-strength = <2>; + bias-disable; }; -&qup_i2c10_default { - pinconf { - pins = "gpio55", "gpio56"; - drive-strength = <2>; - bias-disable; - }; +&qup_uart9_rx { + drive-strength = <2>; + bias-pull-up; }; -&qup_uart9_default { - pinconf-tx { - pins = "gpio4"; - drive-strength = <2>; - bias-disable; +&qup_uart9_tx { + drive-strength = <2>; + bias-disable; +}; + +&sound { + compatible = "qcom,sdm845-sndcard"; + pinctrl-0 = <&quat_mi2s_active &quat_mi2s_sd0_active &quat_mi2s_sd1_active>; + pinctrl-names = "default"; + status = "okay"; + + mm1-dai-link { + link-name = "MultiMedia1"; + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>; + }; }; - pinconf-rx { - pins = "gpio5"; - drive-strength = <2>; - bias-pull-up; + mm2-dai-link { + link-name = "MultiMedia2"; + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA2>; + }; + }; + + mm3-dai-link { + link-name = "MultiMedia3"; + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA3>; + }; + }; + + mm4-dai-link { + link-name = "MultiMedia4"; + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA4>; + }; + }; + + mm5-dai-link { + link-name = "MultiMedia5"; + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA5>; + }; + }; + + mm6-dai-link { + link-name = "MultiMedia6"; + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA6>; + }; + }; + + speaker_playback_dai: speaker-dai-link { + link-name = "Speaker Playback"; + cpu { + sound-dai = <&q6afedai QUATERNARY_MI2S_RX>; + }; + + platform { + sound-dai = <&q6routing>; + }; + }; + + slim-dai-link { + link-name = "SLIM Playback 1"; + cpu { + sound-dai = <&q6afedai SLIMBUS_0_RX>; + }; + + platform { + sound-dai = <&q6routing>; + }; + + codec { + sound-dai = <&wcd9340 0>; + }; + }; + + slimcap-dai-link { + link-name = "SLIM Capture 1"; + cpu { + sound-dai = <&q6afedai SLIMBUS_0_TX>; + }; + + platform { + sound-dai = <&q6routing>; + }; + + codec { + sound-dai = <&wcd9340 1>; + }; + }; + + slim2-dai-link { + link-name = "SLIM Playback 2"; + cpu { + sound-dai = <&q6afedai SLIMBUS_1_RX>; + }; + + platform { + sound-dai = <&q6routing>; + }; + + codec { + sound-dai = <&wcd9340 2>; /* AIF2_PB */ + }; + }; + + slimcap2-dai-link { + link-name = "SLIM Capture 2"; + cpu { + sound-dai = <&q6afedai SLIMBUS_1_TX>; + }; + + platform { + sound-dai = <&q6routing>; + }; + + codec { + sound-dai = <&wcd9340 3>; /* AIF2_CAP */ + }; + }; + + slimcap3-dai-link { + link-name = "SLIM Capture 3"; + cpu { + sound-dai = <&q6afedai SLIMBUS_2_TX>; + }; + + platform { + sound-dai = <&q6routing>; + }; + + codec { + sound-dai = <&wcd9340 5>; /* AIF3_CAP */ + }; }; }; @@ -588,50 +753,50 @@ &tlmm { gpio-reserved-ranges = <0 4>, <81 4>; - tri_state_key_default: tri_state_key_default { - mux { - pins = "gpio40", "gpio42", "gpio26"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; + tri_state_key_default: tri-state-key-default-state { + pins = "gpio40", "gpio42", "gpio26"; + function = "gpio"; + drive-strength = <2>; + bias-disable; }; - ts_default_pins: ts-int { - mux { - pins = "gpio99", "gpio125"; - function = "gpio"; - drive-strength = <16>; - bias-pull-up; - }; + ts_default_pins: ts-int-state { + pins = "gpio99", "gpio125"; + function = "gpio"; + drive-strength = <16>; + bias-pull-up; }; - panel_reset_pins: panel-reset { - mux { - pins = "gpio6", "gpio25", "gpio26"; - function = "gpio"; - drive-strength = <8>; - bias-disable; - }; + panel_reset_pins: panel-reset-state { + pins = "gpio6", "gpio25", "gpio26"; + function = "gpio"; + drive-strength = <8>; + bias-disable; }; - panel_te_pin: panel-te { - mux { - pins = "gpio10"; - function = "mdp_vsync"; - drive-strength = <2>; - bias-disable; - input-enable; - }; + panel_te_pin: panel-te-state { + pins = "gpio10"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-disable; + input-enable; }; - panel_esd_pin: panel-esd { + panel_esd_pin: panel-esd-state { + pins = "gpio30"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + input-enable; + }; + + speaker_default: speaker-default-state { mux { - pins = "gpio30"; + pins = "gpio69"; function = "gpio"; - drive-strength = <2>; - bias-pull-down; - input-enable; + drive-strength = <16>; + bias-pull-up; + output-high; }; }; }; @@ -641,6 +806,17 @@ firmware-name = "qcom/sdm845/oneplus6/venus.mbn"; }; +&wcd9340 { + pinctrl-0 = <&wcd_intr_default>; + pinctrl-names = "default"; + reset-gpios = <&tlmm 64 GPIO_ACTIVE_HIGH>; + vdd-buck-supply = <&vreg_s4a_1p8>; + vdd-buck-sido-supply = <&vreg_s4a_1p8>; + vdd-tx-supply = <&vreg_s4a_1p8>; + vdd-rx-supply = <&vreg_s4a_1p8>; + vdd-io-supply = <&vreg_s4a_1p8>; +}; + &wifi { status = "okay"; vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>; diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts b/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts index bf2cf92e8976..6cdda971bb4b 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts @@ -32,3 +32,43 @@ &bq27441_fg { monitored-battery = <&battery>; }; + +&i2c4 { + status = "okay"; + + max98927_codec: max98927@3a { + compatible = "maxim,max98927"; + reg = <0x3a>; + #sound-dai-cells = <1>; + + pinctrl-0 = <&speaker_default>; + pinctrl-names = "default"; + + reset-gpios = <&tlmm 69 GPIO_ACTIVE_LOW>; + + vmon-slot-no = <1>; + imon-slot-no = <0>; + }; +}; + +&sound { + model = "OnePlus 6"; + audio-routing = "RX_BIAS", "MCLK", + "AMIC2", "MIC BIAS2", + "AMIC3", "MIC BIAS4", + "AMIC4", "MIC BIAS1", + "AMIC5", "MIC BIAS4"; +}; + +&speaker_playback_dai { + codec { + sound-dai = <&max98927_codec 0>; + }; +}; + +&wcd9340 { + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <2700000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; +}; diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts b/arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts index 1b6b5bf368df..086d14e2de92 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts @@ -29,10 +29,39 @@ compatible = "samsung,s6e3fc2x01"; }; +&i2c4 { + /* nxp,tfa9894 @ 0x34 */ +}; + &bq27441_fg { monitored-battery = <&battery>; }; +&sound { + model = "OnePlus 6T"; + audio-routing = "RX_BIAS", "MCLK", + "AMIC1", "MIC BIAS3", + "AMIC2", "MIC BIAS2", + "AMIC3", "MIC BIAS4", + "AMIC4", "MIC BIAS1", + "AMIC5", "MIC BIAS3"; + +}; + +/* + * The TFA9894 codec is currently unsupported. + * We need to delete the node to allow the soundcard + * to probe for headphones/earpiece. + */ +/delete-node/ &speaker_playback_dai; + &rmi4_f12 { touchscreen-y-mm = <148>; }; + +&wcd9340 { + qcom,micbias1-microvolt = <2700000>; + qcom,micbias2-microvolt = <2700000>; + qcom,micbias3-microvolt = <2700000>; + qcom,micbias4-microvolt = <2700000>; +}; diff --git a/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts b/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts index e742c27fe91f..d37a433130b9 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts @@ -73,7 +73,7 @@ &apps_rsc { - pm8998-rpmh-regulators { + regulators-0 { compatible = "qcom,pm8998-rpmh-regulators"; qcom,pmic-id = "a"; @@ -332,7 +332,7 @@ }; }; - pm8005-rpmh-regulators { + regulators-1 { compatible = "qcom,pm8005-rpmh-regulators"; qcom,pmic-id = "c"; diff --git a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts index bb77ccfdc68c..b54e304abf71 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts @@ -54,7 +54,7 @@ key-vol-up { label = "volume_up"; linux,code = <KEY_VOLUMEUP>; - gpios = <&pm8998_gpio 6 GPIO_ACTIVE_LOW>; + gpios = <&pm8998_gpios 6 GPIO_ACTIVE_LOW>; debounce-interval = <15>; }; }; @@ -111,7 +111,7 @@ }; &apps_rsc { - pm8998-rpmh-regulators { + regulators-0 { compatible = "qcom,pm8998-rpmh-regulators"; qcom,pmic-id = "a"; @@ -376,7 +376,7 @@ }; }; - pmi8998-rpmh-regulators { + regulators-1 { compatible = "qcom,pmi8998-rpmh-regulators"; qcom,pmic-id = "b"; @@ -390,7 +390,7 @@ }; }; - pm8005-rpmh-regulators { + regulators-2 { compatible = "qcom,pm8005-rpmh-regulators"; qcom,pmic-id = "c"; @@ -495,10 +495,10 @@ }; &ipa { - status = "okay"; - + qcom,gsi-loader = "self"; memory-region = <&ipa_fw_mem>; firmware-name = "qcom/sdm845/axolotl/ipa_fws.mbn"; + status = "okay"; }; &mdss { @@ -510,7 +510,7 @@ firmware-name = "qcom/sdm845/axolotl/mba.mbn", "qcom/sdm845/axolotl/modem.mbn"; }; -&pm8998_gpio { +&pm8998_gpios { volume_up_gpio: pm8998-gpio6-state { pinconf { pins = "gpio6"; @@ -522,14 +522,9 @@ }; }; -&pm8998_pon { - volume_down_resin: resin { - compatible = "qcom,pm8941-resin"; - interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; - linux,code = <KEY_VOLUMEDOWN>; - }; +&pm8998_resin { + linux,code = <KEY_VOLUMEDOWN>; + status = "okay"; }; &pmi8998_lpg { @@ -559,18 +554,14 @@ }; }; -&qup_uart9_default { - pinconf-rx { - pins = "gpio5"; - drive-strength = <2>; - bias-pull-up; - }; +&qup_uart9_rx { + drive-strength = <2>; + bias-pull-up; +}; - pinconf-tx { - pins = "gpio4"; - drive-strength = <2>; - bias-disable; - }; +&qup_uart9_tx { + drive-strength = <2>; + bias-disable; }; &qupv3_id_0 { @@ -584,110 +575,62 @@ &tlmm { gpio-reserved-ranges = <0 4>, <81 4>; - sde_dsi_active: sde-dsi-active { - mux { - pins = "gpio6", "gpio11"; - function = "gpio"; - }; - - config { - pins = "gpio6", "gpio11"; - drive-strength = <8>; - bias-disable; - }; + sde_dsi_active: sde-dsi-active-state { + pins = "gpio6", "gpio11"; + function = "gpio"; + drive-strength = <8>; + bias-disable; }; - sde_dsi_suspend: sde-dsi-suspend { - mux { - pins = "gpio6", "gpio11"; - function = "gpio"; - }; - - config { - pins = "gpio6", "gpio11"; - drive-strength = <2>; - bias-pull-down; - }; + sde_dsi_suspend: sde-dsi-suspend-state { + pins = "gpio6", "gpio11"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; }; - sde_te_active: sde-te-active { - mux { - pins = "gpio10"; - function = "mdp_vsync"; - }; - - config { - pins = "gpio10"; - drive-strength = <2>; - bias-pull-down; - }; + sde_te_active: sde-te-active-state { + pins = "gpio10"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-pull-down; }; - sde_te_suspend: sde-te-suspend { - mux { - pins = "gpio10"; - function = "mdp_vsync"; - }; - - config { - pins = "gpio10"; - drive-strength = <2>; - bias-pull-down; - }; + sde_te_suspend: sde-te-suspend-state { + pins = "gpio10"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-pull-down; }; - ts_int_active: ts-int-active { - mux { - pins = "gpio125"; - function = "gpio"; - }; - - config { - pins = "gpio125"; - drive-strength = <8>; - bias-pull-up; - input-enable; - }; + ts_int_active: ts-int-active-state { + pins = "gpio125"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + input-enable; }; - ts_int_suspend: ts-int-suspend { - mux { - pins = "gpio125"; - function = "gpio"; - }; - - config { - pins = "gpio125"; - drive-strength = <2>; - bias-pull-down; - input-enable; - }; + ts_int_suspend: ts-int-suspend-state { + pins = "gpio125"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + input-enable; }; - ts_reset_active: ts-reset-active { - mux { - pins = "gpio99"; - function = "gpio"; - }; - - config { - pins = "gpio99"; - drive-strength = <8>; - bias-pull-up; - }; + ts_reset_active: ts-reset-active-state { + pins = "gpio99"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; }; - ts_reset_suspend: ts-reset-suspend { - mux { - pins = "gpio99"; - function = "gpio"; - }; - - config { - pins = "gpio99"; - drive-strength = <2>; - bias-pull-down; - }; + ts_reset_suspend: ts-reset-suspend-state { + pins = "gpio99"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi index 87dd0fc36747..4984c7496c31 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi @@ -4,6 +4,7 @@ */ #include <dt-bindings/input/input.h> +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> #include <dt-bindings/regulator/qcom,rpmh-regulator.h> #include "sdm845.dtsi" #include "pm8005.dtsi" @@ -17,14 +18,43 @@ gpio-keys { compatible = "gpio-keys"; - /* Neither Camera Focus, nor Camera Shutter seem to work... */ + pinctrl-0 = <&focus_n &snapshot_n &vol_down_n &vol_up_n>; + pinctrl-names = "default"; - key-vol-down { - label = "volume_down"; - gpios = <&pm8998_gpio 5 GPIO_ACTIVE_LOW>; + key-camera-focus { + label = "Camera Focus"; + gpios = <&pm8998_gpios 2 GPIO_ACTIVE_LOW>; + linux,code = <KEY_CAMERA_FOCUS>; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + + key-camera-snapshot { + label = "Camera Snapshot"; + gpios = <&pm8998_gpios 7 GPIO_ACTIVE_LOW>; + linux,code = <KEY_CAMERA>; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + + key-volume-down { + label = "Volume Down"; + gpios = <&pm8998_gpios 5 GPIO_ACTIVE_LOW>; linux,code = <KEY_VOLUMEDOWN>; debounce-interval = <15>; - gpio-key,wakeup; + linux,can-disable; + wakeup-source; + }; + + key-volume-up { + label = "Volume Up"; + gpios = <&pm8998_gpios 6 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; }; }; @@ -69,7 +99,7 @@ }; &apps_rsc { - pm8998-rpmh-regulators { + regulators-0 { compatible = "qcom,pm8998-rpmh-regulators"; qcom,pmic-id = "a"; @@ -299,7 +329,7 @@ }; }; - pmi8998-rpmh-regulators { + regulators-1 { compatible = "qcom,pmi8998-rpmh-regulators"; qcom,pmic-id = "b"; @@ -310,7 +340,7 @@ }; }; - pm8005-rpmh-regulators { + regulators-2 { compatible = "qcom,pm8005-rpmh-regulators"; qcom,pmic-id = "c"; @@ -358,6 +388,40 @@ /* AMS TCS3490 RGB+IR color sensor @ 72 */ }; +&pm8998_gpios { + focus_n: focus-n-state { + pins = "gpio2"; + function = PMIC_GPIO_FUNC_NORMAL; + power-source = <0>; + bias-pull-up; + input-enable; + }; + + vol_down_n: vol-down-n-state { + pins = "gpio5"; + function = PMIC_GPIO_FUNC_NORMAL; + power-source = <0>; + bias-pull-up; + input-enable; + }; + + vol_up_n: vol-up-n-state { + pins = "gpio6"; + function = PMIC_GPIO_FUNC_NORMAL; + power-source = <0>; + bias-pull-up; + input-enable; + }; + + snapshot_n: snapshot-n-state { + pins = "gpio7"; + function = PMIC_GPIO_FUNC_NORMAL; + power-source = <0>; + bias-pull-up; + input-enable; + }; +}; + &qupv3_id_0 { status = "okay"; }; @@ -383,19 +447,19 @@ gpio-reserved-ranges = <0 4>, <81 4>; sdc2_default_state: sdc2-default-state { - clk { + clk-pins { pins = "sdc2_clk"; drive-strength = <16>; bias-disable; }; - cmd { + cmd-pins { pins = "sdc2_cmd"; drive-strength = <10>; bias-pull-up; }; - data { + data-pins { pins = "sdc2_data"; drive-strength = <10>; bias-pull-up; diff --git a/arch/arm64/boot/dts/qcom/sdm845-wcd9340.dtsi b/arch/arm64/boot/dts/qcom/sdm845-wcd9340.dtsi new file mode 100644 index 000000000000..0d7c37f39176 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm845-wcd9340.dtsi @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * SDM845 SoC device tree source + * + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + */ + +&slim { + status = "okay"; + + slim@1 { + reg = <1>; + #address-cells = <2>; + #size-cells = <0>; + + wcd9340_ifd: ifd@0,0 { + compatible = "slim217,250"; + reg = <0 0>; + }; + + wcd9340: codec@1,0 { + compatible = "slim217,250"; + reg = <1 0>; + slim-ifc-dev = <&wcd9340_ifd>; + + #sound-dai-cells = <1>; + + interrupts-extended = <&tlmm 54 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + + clock-names = "extclk"; + clocks = <&rpmhcc RPMH_LN_BB_CLK2>; + + #clock-cells = <0>; + clock-frequency = <9600000>; + clock-output-names = "mclk"; + + pinctrl-0 = <&wcd_intr_default>; + pinctrl-names = "default"; + + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; + + #address-cells = <1>; + #size-cells = <1>; + + wcdgpio: gpio-controller@42 { + compatible = "qcom,wcd9340-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x42 0x2>; + }; + + swm: swm@c85 { + compatible = "qcom,soundwire-v1.3.0"; + reg = <0xc85 0x40>; + interrupts-extended = <&wcd9340 20>; + + qcom,dout-ports = <6>; + qcom,din-ports = <2>; + qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x7 0x1f 0x3f 0x0f 0x0f>; + qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x6 0x12 0x0d 0x07 0x0a>; + qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x1f 0x00 0x00 0x1f 0x00 0x00>; + + #sound-dai-cells = <1>; + clocks = <&wcd9340>; + clock-names = "iface"; + #address-cells = <2>; + #size-cells = <0>; + }; + }; + }; +}; + +&tlmm { + wcd_intr_default: wcd-intr-default-state { + pins = "gpio54"; + function = "gpio"; + + input-enable; + bias-pull-down; + drive-strength = <2>; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi index eb6b2b676eca..e0fda4d754fe 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi @@ -7,6 +7,7 @@ #include <dt-bindings/sound/qcom,q6afe.h> #include <dt-bindings/sound/qcom,q6asm.h> #include "sdm845.dtsi" +#include "sdm845-wcd9340.dtsi" #include "pm8998.dtsi" #include "pmi8998.dtsi" @@ -46,7 +47,7 @@ key-vol-up { label = "Volume Up"; linux,code = <KEY_VOLUMEUP>; - gpios = <&pm8998_gpio 6 GPIO_ACTIVE_LOW>; + gpios = <&pm8998_gpios 6 GPIO_ACTIVE_LOW>; }; }; @@ -97,6 +98,12 @@ no-map; }; + /* Cont splash region set up by the bootloader */ + cont_splash_mem: framebuffer@9d400000 { + reg = <0 0x9d400000 0 0x2400000>; + no-map; + }; + rmtfs_mem: memory@f6301000 { compatible = "qcom,rmtfs-mem"; reg = <0 0xf6301000 0 0x200000>; @@ -123,7 +130,7 @@ }; &apps_rsc { - pm8998-rpmh-regulators { + regulators-0 { compatible = "qcom,pm8998-rpmh-regulators"; qcom,pmic-id = "a"; @@ -299,12 +306,13 @@ }; &ipa { - status = "okay"; + qcom,gsi-loader = "self"; memory-region = <&ipa_fw_mem>; firmware-name = "qcom/sdm845/beryllium/ipa_fws.mbn"; + status = "okay"; }; -&pm8998_gpio { +&pm8998_gpios { vol_up_pin_a: vol-up-active-state { pins = "gpio6"; function = "normal"; @@ -325,14 +333,9 @@ qcom,cabc; }; -&pm8998_pon { - resin { - compatible = "qcom,pm8941-resin"; - interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; - linux,code = <KEY_VOLUMEDOWN>; - }; +&pm8998_resin { + linux,code = <KEY_VOLUMEDOWN>; + status = "okay"; }; &pmi8998_rradc { @@ -379,7 +382,7 @@ }; &sound { - compatible = "qcom,db845c-sndcard"; + compatible = "qcom,db845c-sndcard", "qcom,sdm845-sndcard"; pinctrl-0 = <&quat_mi2s_active &quat_mi2s_sd0_active>; pinctrl-names = "default"; @@ -445,40 +448,31 @@ &tlmm { gpio-reserved-ranges = <0 4>, <81 4>; - sdc2_default_state: sdc2-default { - clk { + sdc2_default_state: sdc2-default-state { + clk-pins { pins = "sdc2_clk"; bias-disable; drive-strength = <16>; }; - cmd { + cmd-pins { pins = "sdc2_cmd"; bias-pull-up; drive-strength = <10>; }; - data { + data-pins { pins = "sdc2_data"; bias-pull-up; drive-strength = <10>; }; }; - sdc2_card_det_n: sd-card-det-n { + sdc2_card_det_n: sd-card-det-n-state { pins = "gpio126"; function = "gpio"; bias-pull-up; }; - - wcd_intr_default: wcd_intr_default { - pins = <54>; - function = "gpio"; - - input-enable; - bias-pull-down; - drive-strength = <2>; - }; }; &uart6 { @@ -546,11 +540,7 @@ firmware-name = "qcom/sdm845/beryllium/venus.mbn"; }; -&wcd9340{ - pinctrl-0 = <&wcd_intr_default>; - pinctrl-names = "default"; - clock-names = "extclk"; - clocks = <&rpmhcc RPMH_LN_BB_CLK2>; +&wcd9340 { reset-gpios = <&tlmm 64 GPIO_ACTIVE_HIGH>; vdd-buck-supply = <&vreg_s4a_1p8>; vdd-buck-sido-supply = <&vreg_s4a_1p8>; diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts index 38ba809a95cd..1b7fdbae6a2b 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts @@ -13,6 +13,7 @@ #include <dt-bindings/sound/qcom,q6afe.h> #include <dt-bindings/sound/qcom,q6asm.h> #include "sdm845.dtsi" +#include "sdm845-wcd9340.dtsi" #include "pm8998.dtsi" #include "pmi8998.dtsi" #include "pm8005.dtsi" @@ -55,7 +56,7 @@ key-vol-up { label = "Volume Up"; linux,code = <KEY_VOLUMEUP>; - gpios = <&pm8998_gpio 6 GPIO_ACTIVE_LOW>; + gpios = <&pm8998_gpios 6 GPIO_ACTIVE_LOW>; debounce-interval = <15>; }; }; @@ -143,7 +144,7 @@ }; &apps_rsc { - pm8998-rpmh-regulators { + regulators-0 { compatible = "qcom,pm8998-rpmh-regulators"; qcom,pmic-id = "a"; @@ -343,7 +344,7 @@ }; }; - pmi8998-rpmh-regulators { + regulators-1 { compatible = "qcom,pmi8998-rpmh-regulators"; qcom,pmic-id = "b"; @@ -355,7 +356,7 @@ }; }; - pm8005-rpmh-regulators { + regulators-2 { compatible = "qcom,pm8005-rpmh-regulators"; qcom,pmic-id = "c"; @@ -449,6 +450,7 @@ }; &ipa { + qcom,gsi-loader = "self"; memory-region = <&ipa_fw_mem>; firmware-name = "qcom/sdm845/polaris/ipa_fws.mbn"; status = "okay"; @@ -518,7 +520,7 @@ status = "okay"; }; -&pm8998_gpio { +&pm8998_gpios { volume_up_gpio: pm8998-gpio6-state { pinconf { qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>; @@ -530,14 +532,9 @@ }; }; -&pm8998_pon { - resin { - interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; - compatible = "qcom,pm8941-resin"; - linux,code = <KEY_VOLUMEDOWN>; - debounce = <15625>; - bias-pull-up; - }; +&pm8998_resin { + linux,code = <KEY_VOLUMEDOWN>; + status = "okay"; }; &q6afedai { @@ -570,24 +567,21 @@ }; &qup_i2c14_default { - pinconf { - pins = "gpio33", "gpio34"; - drive-strength = <2>; - bias-disable; - }; + drive-strength = <2>; + bias-disable; }; &tlmm { gpio-reserved-ranges = <0 4>, <81 4>; - ts_reset_default: ts-reset-default { + ts_reset_default: ts-reset-default-state { pins = "gpio99"; function = "gpio"; drive-strength = <16>; output-high; }; - ts_int_default: ts-int-default { + ts_int_default: ts-int-default-state { pins = "gpio125"; function = "gpio"; bias-pull-down; @@ -595,14 +589,14 @@ input-enable; }; - ts_reset_sleep: ts-reset-sleep { + ts_reset_sleep: ts-reset-sleep-state { pins = "gpio99"; function = "gpio"; bias-disable; drive-strength = <2>; }; - ts_int_sleep: ts-int-sleep { + ts_int_sleep: ts-int-sleep-state { pins = "gpio125"; function = "gpio"; bias-pull-down; @@ -610,27 +604,19 @@ input-enable; }; - sde_dsi_active: sde-dsi-active { + sde_dsi_active: sde-dsi-active-state { pins = "gpio6", "gpio10"; function = "gpio"; drive-strength = <8>; bias-disable; }; - sde_dsi_suspend: sde-dsi-suspend { + sde_dsi_suspend: sde-dsi-suspend-state { pins = "gpio6", "gpio10"; function = "gpio"; drive-strength = <2>; bias-pull-down; }; - - wcd_intr_default: wcd-intr-default { - pins = "gpio54"; - function = "gpio"; - input-enable; - bias-pull-down; - drive-strength = <2>; - }; }; &uart6 { @@ -707,10 +693,6 @@ }; &wcd9340 { - pinctrl-0 = <&wcd_intr_default>; - pinctrl-names = "default"; - clock-names = "extclk"; - clocks = <&rpmhcc RPMH_LN_BB_CLK2>; reset-gpios = <&tlmm 64 GPIO_ACTIVE_HIGH>; vdd-buck-sido-supply = <&vreg_s4a_1p8>; vdd-buck-supply = <&vreg_s4a_1p8>; diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 65032b94b46d..479859bd8ab3 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -69,122 +69,18 @@ chosen { }; - memory@80000000 { - device_type = "memory"; - /* We expect the bootloader to fill in the size */ - reg = <0 0x80000000 0 0>; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - hyp_mem: hyp-mem@85700000 { - reg = <0 0x85700000 0 0x600000>; - no-map; - }; - - xbl_mem: xbl-mem@85e00000 { - reg = <0 0x85e00000 0 0x100000>; - no-map; - }; - - aop_mem: aop-mem@85fc0000 { - reg = <0 0x85fc0000 0 0x20000>; - no-map; - }; - - aop_cmd_db_mem: aop-cmd-db-mem@85fe0000 { - compatible = "qcom,cmd-db"; - reg = <0x0 0x85fe0000 0 0x20000>; - no-map; - }; - - smem@86000000 { - compatible = "qcom,smem"; - reg = <0x0 0x86000000 0 0x200000>; - no-map; - hwlocks = <&tcsr_mutex 3>; - }; - - tz_mem: tz@86200000 { - reg = <0 0x86200000 0 0x2d00000>; - no-map; - }; - - rmtfs_mem: rmtfs@88f00000 { - compatible = "qcom,rmtfs-mem"; - reg = <0 0x88f00000 0 0x200000>; - no-map; - - qcom,client-id = <1>; - qcom,vmid = <15>; - }; - - qseecom_mem: qseecom@8ab00000 { - reg = <0 0x8ab00000 0 0x1400000>; - no-map; - }; - - camera_mem: camera-mem@8bf00000 { - reg = <0 0x8bf00000 0 0x500000>; - no-map; - }; - - ipa_fw_mem: ipa-fw@8c400000 { - reg = <0 0x8c400000 0 0x10000>; - no-map; - }; - - ipa_gsi_mem: ipa-gsi@8c410000 { - reg = <0 0x8c410000 0 0x5000>; - no-map; - }; - - gpu_mem: gpu@8c415000 { - reg = <0 0x8c415000 0 0x2000>; - no-map; - }; - - adsp_mem: adsp@8c500000 { - reg = <0 0x8c500000 0 0x1a00000>; - no-map; - }; - - wlan_msa_mem: wlan-msa@8df00000 { - reg = <0 0x8df00000 0 0x100000>; - no-map; - }; - - mpss_region: mpss@8e000000 { - reg = <0 0x8e000000 0 0x7800000>; - no-map; - }; - - venus_mem: venus@95800000 { - reg = <0 0x95800000 0 0x500000>; - no-map; - }; - - cdsp_mem: cdsp@95d00000 { - reg = <0 0x95d00000 0 0x800000>; - no-map; - }; - - mba_region: mba@96500000 { - reg = <0 0x96500000 0 0x200000>; - no-map; - }; - - slpi_mem: slpi@96700000 { - reg = <0 0x96700000 0 0x1400000>; - no-map; + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <38400000>; + clock-output-names = "xo_board"; }; - spss_mem: spss@97b00000 { - reg = <0 0x97b00000 0 0x100000>; - no-map; + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32764>; }; }; @@ -209,9 +105,11 @@ next-level-cache = <&L2_0>; L2_0: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; L3_0: l3-cache { compatible = "cache"; + cache-level = <3>; }; }; }; @@ -233,6 +131,7 @@ next-level-cache = <&L2_100>; L2_100: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -254,6 +153,7 @@ next-level-cache = <&L2_200>; L2_200: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -275,6 +175,7 @@ next-level-cache = <&L2_300>; L2_300: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -296,6 +197,7 @@ next-level-cache = <&L2_400>; L2_400: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -317,6 +219,7 @@ next-level-cache = <&L2_500>; L2_500: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -338,6 +241,7 @@ next-level-cache = <&L2_600>; L2_600: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -359,6 +263,7 @@ next-level-cache = <&L2_700>; L2_700: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -436,6 +341,18 @@ }; }; + firmware { + scm { + compatible = "qcom,scm-sdm845", "qcom,scm"; + }; + }; + + memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0 0x80000000 0 0>; + }; + cpu0_opp_table: opp-table-cpu0 { compatible = "operating-points-v2"; opp-shared; @@ -696,37 +613,262 @@ }; }; + dsi_opp_table: opp-table-dsi { + compatible = "operating-points-v2"; + + opp-19200000 { + opp-hz = /bits/ 64 <19200000>; + required-opps = <&rpmhpd_opp_min_svs>; + }; + + opp-180000000 { + opp-hz = /bits/ 64 <180000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-275000000 { + opp-hz = /bits/ 64 <275000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-328580000 { + opp-hz = /bits/ 64 <328580000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + + qspi_opp_table: opp-table-qspi { + compatible = "operating-points-v2"; + + opp-19200000 { + opp-hz = /bits/ 64 <19200000>; + required-opps = <&rpmhpd_opp_min_svs>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-150000000 { + opp-hz = /bits/ 64 <150000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + + qup_opp_table: opp-table-qup { + compatible = "operating-points-v2"; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + required-opps = <&rpmhpd_opp_min_svs>; + }; + + opp-75000000 { + opp-hz = /bits/ 64 <75000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-128000000 { + opp-hz = /bits/ 64 <128000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + pmu { compatible = "arm,armv8-pmuv3"; interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; }; - timer { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, - <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, - <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, - <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; - }; + psci: psci { + compatible = "arm,psci-1.0"; + method = "smc"; - clocks { - xo_board: xo-board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <38400000>; - clock-output-names = "xo_board"; + CPU_PD0: power-domain-cpu0 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; }; - sleep_clk: sleep-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32764>; + CPU_PD1: power-domain-cpu1 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD2: power-domain-cpu2 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD3: power-domain-cpu3 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD4: power-domain-cpu4 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD5: power-domain-cpu5 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD6: power-domain-cpu6 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD7: power-domain-cpu7 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CLUSTER_PD: power-domain-cluster { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_SLEEP_0>; }; }; - firmware { - scm { - compatible = "qcom,scm-sdm845", "qcom,scm"; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_mem: hyp-mem@85700000 { + reg = <0 0x85700000 0 0x600000>; + no-map; + }; + + xbl_mem: xbl-mem@85e00000 { + reg = <0 0x85e00000 0 0x100000>; + no-map; + }; + + aop_mem: aop-mem@85fc0000 { + reg = <0 0x85fc0000 0 0x20000>; + no-map; + }; + + aop_cmd_db_mem: aop-cmd-db-mem@85fe0000 { + compatible = "qcom,cmd-db"; + reg = <0x0 0x85fe0000 0 0x20000>; + no-map; + }; + + smem@86000000 { + compatible = "qcom,smem"; + reg = <0x0 0x86000000 0 0x200000>; + no-map; + hwlocks = <&tcsr_mutex 3>; + }; + + tz_mem: tz@86200000 { + reg = <0 0x86200000 0 0x2d00000>; + no-map; + }; + + rmtfs_mem: rmtfs@88f00000 { + compatible = "qcom,rmtfs-mem"; + reg = <0 0x88f00000 0 0x200000>; + no-map; + + qcom,client-id = <1>; + qcom,vmid = <15>; + }; + + qseecom_mem: qseecom@8ab00000 { + reg = <0 0x8ab00000 0 0x1400000>; + no-map; + }; + + camera_mem: camera-mem@8bf00000 { + reg = <0 0x8bf00000 0 0x500000>; + no-map; + }; + + ipa_fw_mem: ipa-fw@8c400000 { + reg = <0 0x8c400000 0 0x10000>; + no-map; + }; + + ipa_gsi_mem: ipa-gsi@8c410000 { + reg = <0 0x8c410000 0 0x5000>; + no-map; + }; + + gpu_mem: gpu@8c415000 { + reg = <0 0x8c415000 0 0x2000>; + no-map; + }; + + adsp_mem: adsp@8c500000 { + reg = <0 0x8c500000 0 0x1a00000>; + no-map; + }; + + wlan_msa_mem: wlan-msa@8df00000 { + reg = <0 0x8df00000 0 0x100000>; + no-map; + }; + + mpss_region: mpss@8e000000 { + reg = <0 0x8e000000 0 0x7800000>; + no-map; + }; + + venus_mem: venus@95800000 { + reg = <0 0x95800000 0 0x500000>; + no-map; + }; + + cdsp_mem: cdsp@95d00000 { + reg = <0 0x95d00000 0 0x800000>; + no-map; + }; + + mba_region: mba@96500000 { + reg = <0 0x96500000 0 0x200000>; + no-map; + }; + + slpi_mem: slpi@96700000 { + reg = <0 0x96700000 0 0x1400000>; + no-map; + }; + + spss_mem: spss@97b00000 { + reg = <0 0x97b00000 0 0x100000>; + no-map; + }; + + mdata_mem: mpss-metadata { + alloc-ranges = <0 0xa0000000 0 0x20000000>; + size = <0 0x4000>; + no-map; }; }; @@ -1018,64 +1160,6 @@ }; }; - psci: psci { - compatible = "arm,psci-1.0"; - method = "smc"; - - CPU_PD0: power-domain-cpu0 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_0>; - }; - - CPU_PD1: power-domain-cpu1 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_0>; - }; - - CPU_PD2: power-domain-cpu2 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_0>; - }; - - CPU_PD3: power-domain-cpu3 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_0>; - }; - - CPU_PD4: power-domain-cpu4 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&BIG_CPU_SLEEP_0>; - }; - - CPU_PD5: power-domain-cpu5 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&BIG_CPU_SLEEP_0>; - }; - - CPU_PD6: power-domain-cpu6 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&BIG_CPU_SLEEP_0>; - }; - - CPU_PD7: power-domain-cpu7 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&BIG_CPU_SLEEP_0>; - }; - - CLUSTER_PD: power-domain-cluster { - #power-domain-cells = <0>; - domain-idle-states = <&CLUSTER_SLEEP_0>; - }; - }; - soc: soc@0 { #address-cells = <2>; #size-cells = <2>; @@ -1125,30 +1209,6 @@ clock-names = "core"; }; - qup_opp_table: opp-table-qup { - compatible = "operating-points-v2"; - - opp-50000000 { - opp-hz = /bits/ 64 <50000000>; - required-opps = <&rpmhpd_opp_min_svs>; - }; - - opp-75000000 { - opp-hz = /bits/ 64 <75000000>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - required-opps = <&rpmhpd_opp_svs>; - }; - - opp-128000000 { - opp-hz = /bits/ 64 <128000000>; - required-opps = <&rpmhpd_opp_nom>; - }; - }; - gpi_dma0: dma-controller@800000 { #dma-cells = <3>; compatible = "qcom,sdm845-gpi-dma"; @@ -1636,7 +1696,7 @@ }; }; - gpi_dma1: dma-controller@0xa00000 { + gpi_dma1: dma-controller@a00000 { #dma-cells = <3>; compatible = "qcom,sdm845-gpi-dma"; reg = <0 0x00a00000 0 0x60000>; @@ -2137,6 +2197,12 @@ interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; }; + dma@10a2000 { + compatible = "qcom,sdm845-dcc", "qcom,dcc"; + reg = <0x0 0x010a2000 0x0 0x1000>, + <0x0 0x010ae000 0x0 0x2000>; + }; + pmu@114a000 { compatible = "qcom,sdm845-llcc-bwmon"; reg = <0 0x0114a000 0 0x1000>; @@ -2585,9 +2651,9 @@ iommus = <&apps_smmu 0x720 0x0>, <&apps_smmu 0x722 0x0>; - reg = <0 0x1e40000 0 0x7000>, - <0 0x1e47000 0 0x2000>, - <0 0x1e04000 0 0x2c000>; + reg = <0 0x01e40000 0 0x7000>, + <0 0x01e47000 0 0x2000>, + <0 0x01e04000 0 0x2c000>; reg-names = "ipa-reg", "ipa-shared", "gsi"; @@ -2641,7 +2707,7 @@ gpio-ranges = <&tlmm 0 0 151>; wakeup-parent = <&pdc_intc>; - cci0_default: cci0-default { + cci0_default: cci0-default-state { /* SDA, SCL */ pins = "gpio17", "gpio18"; function = "cci_i2c"; @@ -2650,7 +2716,7 @@ drive-strength = <2>; /* 2 mA */ }; - cci0_sleep: cci0-sleep { + cci0_sleep: cci0-sleep-state { /* SDA, SCL */ pins = "gpio17", "gpio18"; function = "cci_i2c"; @@ -2659,7 +2725,7 @@ bias-pull-down; }; - cci1_default: cci1-default { + cci1_default: cci1-default-state { /* SDA, SCL */ pins = "gpio19", "gpio20"; function = "cci_i2c"; @@ -2668,7 +2734,7 @@ drive-strength = <2>; /* 2 mA */ }; - cci1_sleep: cci1-sleep { + cci1_sleep: cci1-sleep-state { /* SDA, SCL */ pins = "gpio19", "gpio20"; function = "cci_i2c"; @@ -2677,556 +2743,495 @@ bias-pull-down; }; - qspi_clk: qspi-clk { - pinmux { - pins = "gpio95"; - function = "qspi_clk"; - }; + qspi_clk: qspi-clk-state { + pins = "gpio95"; + function = "qspi_clk"; }; - qspi_cs0: qspi-cs0 { - pinmux { - pins = "gpio90"; - function = "qspi_cs"; - }; + qspi_cs0: qspi-cs0-state { + pins = "gpio90"; + function = "qspi_cs"; }; - qspi_cs1: qspi-cs1 { - pinmux { - pins = "gpio89"; - function = "qspi_cs"; - }; + qspi_cs1: qspi-cs1-state { + pins = "gpio89"; + function = "qspi_cs"; }; - qspi_data01: qspi-data01 { - pinmux-data { - pins = "gpio91", "gpio92"; - function = "qspi_data"; - }; + qspi_data01: qspi-data01-state { + pins = "gpio91", "gpio92"; + function = "qspi_data"; }; - qspi_data12: qspi-data12 { - pinmux-data { - pins = "gpio93", "gpio94"; - function = "qspi_data"; - }; + qspi_data12: qspi-data12-state { + pins = "gpio93", "gpio94"; + function = "qspi_data"; }; - qup_i2c0_default: qup-i2c0-default { - pinmux { - pins = "gpio0", "gpio1"; - function = "qup0"; - }; + qup_i2c0_default: qup-i2c0-default-state { + pins = "gpio0", "gpio1"; + function = "qup0"; }; - qup_i2c1_default: qup-i2c1-default { - pinmux { - pins = "gpio17", "gpio18"; - function = "qup1"; - }; + qup_i2c1_default: qup-i2c1-default-state { + pins = "gpio17", "gpio18"; + function = "qup1"; }; - qup_i2c2_default: qup-i2c2-default { - pinmux { - pins = "gpio27", "gpio28"; - function = "qup2"; - }; + qup_i2c2_default: qup-i2c2-default-state { + pins = "gpio27", "gpio28"; + function = "qup2"; }; - qup_i2c3_default: qup-i2c3-default { - pinmux { - pins = "gpio41", "gpio42"; - function = "qup3"; - }; + qup_i2c3_default: qup-i2c3-default-state { + pins = "gpio41", "gpio42"; + function = "qup3"; }; - qup_i2c4_default: qup-i2c4-default { - pinmux { - pins = "gpio89", "gpio90"; - function = "qup4"; - }; + qup_i2c4_default: qup-i2c4-default-state { + pins = "gpio89", "gpio90"; + function = "qup4"; }; - qup_i2c5_default: qup-i2c5-default { - pinmux { - pins = "gpio85", "gpio86"; - function = "qup5"; - }; + qup_i2c5_default: qup-i2c5-default-state { + pins = "gpio85", "gpio86"; + function = "qup5"; }; - qup_i2c6_default: qup-i2c6-default { - pinmux { - pins = "gpio45", "gpio46"; - function = "qup6"; - }; + qup_i2c6_default: qup-i2c6-default-state { + pins = "gpio45", "gpio46"; + function = "qup6"; }; - qup_i2c7_default: qup-i2c7-default { - pinmux { - pins = "gpio93", "gpio94"; - function = "qup7"; - }; + qup_i2c7_default: qup-i2c7-default-state { + pins = "gpio93", "gpio94"; + function = "qup7"; }; - qup_i2c8_default: qup-i2c8-default { - pinmux { - pins = "gpio65", "gpio66"; - function = "qup8"; - }; + qup_i2c8_default: qup-i2c8-default-state { + pins = "gpio65", "gpio66"; + function = "qup8"; }; - qup_i2c9_default: qup-i2c9-default { - pinmux { - pins = "gpio6", "gpio7"; - function = "qup9"; - }; + qup_i2c9_default: qup-i2c9-default-state { + pins = "gpio6", "gpio7"; + function = "qup9"; }; - qup_i2c10_default: qup-i2c10-default { - pinmux { - pins = "gpio55", "gpio56"; - function = "qup10"; - }; + qup_i2c10_default: qup-i2c10-default-state { + pins = "gpio55", "gpio56"; + function = "qup10"; }; - qup_i2c11_default: qup-i2c11-default { - pinmux { - pins = "gpio31", "gpio32"; - function = "qup11"; - }; + qup_i2c11_default: qup-i2c11-default-state { + pins = "gpio31", "gpio32"; + function = "qup11"; }; - qup_i2c12_default: qup-i2c12-default { - pinmux { - pins = "gpio49", "gpio50"; - function = "qup12"; - }; + qup_i2c12_default: qup-i2c12-default-state { + pins = "gpio49", "gpio50"; + function = "qup12"; }; - qup_i2c13_default: qup-i2c13-default { - pinmux { - pins = "gpio105", "gpio106"; - function = "qup13"; - }; + qup_i2c13_default: qup-i2c13-default-state { + pins = "gpio105", "gpio106"; + function = "qup13"; }; - qup_i2c14_default: qup-i2c14-default { - pinmux { - pins = "gpio33", "gpio34"; - function = "qup14"; - }; + qup_i2c14_default: qup-i2c14-default-state { + pins = "gpio33", "gpio34"; + function = "qup14"; }; - qup_i2c15_default: qup-i2c15-default { - pinmux { - pins = "gpio81", "gpio82"; - function = "qup15"; - }; + qup_i2c15_default: qup-i2c15-default-state { + pins = "gpio81", "gpio82"; + function = "qup15"; }; - qup_spi0_default: qup-spi0-default { - pinmux { - pins = "gpio0", "gpio1", - "gpio2", "gpio3"; - function = "qup0"; - }; + qup_spi0_default: qup-spi0-default-state { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "qup0"; + }; - config { - pins = "gpio0", "gpio1", - "gpio2", "gpio3"; - drive-strength = <6>; - bias-disable; - }; + qup_spi1_default: qup-spi1-default-state { + pins = "gpio17", "gpio18", "gpio19", "gpio20"; + function = "qup1"; }; - qup_spi1_default: qup-spi1-default { - pinmux { - pins = "gpio17", "gpio18", - "gpio19", "gpio20"; - function = "qup1"; - }; + qup_spi2_default: qup-spi2-default-state { + pins = "gpio27", "gpio28", "gpio29", "gpio30"; + function = "qup2"; }; - qup_spi2_default: qup-spi2-default { - pinmux { - pins = "gpio27", "gpio28", - "gpio29", "gpio30"; - function = "qup2"; - }; + qup_spi3_default: qup-spi3-default-state { + pins = "gpio41", "gpio42", "gpio43", "gpio44"; + function = "qup3"; }; - qup_spi3_default: qup-spi3-default { - pinmux { - pins = "gpio41", "gpio42", - "gpio43", "gpio44"; - function = "qup3"; - }; + qup_spi4_default: qup-spi4-default-state { + pins = "gpio89", "gpio90", "gpio91", "gpio92"; + function = "qup4"; }; - qup_spi4_default: qup-spi4-default { - pinmux { - pins = "gpio89", "gpio90", - "gpio91", "gpio92"; - function = "qup4"; - }; + qup_spi5_default: qup-spi5-default-state { + pins = "gpio85", "gpio86", "gpio87", "gpio88"; + function = "qup5"; }; - qup_spi5_default: qup-spi5-default { - pinmux { - pins = "gpio85", "gpio86", - "gpio87", "gpio88"; - function = "qup5"; - }; + qup_spi6_default: qup-spi6-default-state { + pins = "gpio45", "gpio46", "gpio47", "gpio48"; + function = "qup6"; }; - qup_spi6_default: qup-spi6-default { - pinmux { - pins = "gpio45", "gpio46", - "gpio47", "gpio48"; - function = "qup6"; - }; + qup_spi7_default: qup-spi7-default-state { + pins = "gpio93", "gpio94", "gpio95", "gpio96"; + function = "qup7"; }; - qup_spi7_default: qup-spi7-default { - pinmux { - pins = "gpio93", "gpio94", - "gpio95", "gpio96"; - function = "qup7"; - }; + qup_spi8_default: qup-spi8-default-state { + pins = "gpio65", "gpio66", "gpio67", "gpio68"; + function = "qup8"; }; - qup_spi8_default: qup-spi8-default { - pinmux { - pins = "gpio65", "gpio66", - "gpio67", "gpio68"; - function = "qup8"; - }; + qup_spi9_default: qup-spi9-default-state { + pins = "gpio6", "gpio7", "gpio4", "gpio5"; + function = "qup9"; }; - qup_spi9_default: qup-spi9-default { - pinmux { - pins = "gpio6", "gpio7", - "gpio4", "gpio5"; - function = "qup9"; - }; + qup_spi10_default: qup-spi10-default-state { + pins = "gpio55", "gpio56", "gpio53", "gpio54"; + function = "qup10"; }; - qup_spi10_default: qup-spi10-default { - pinmux { - pins = "gpio55", "gpio56", - "gpio53", "gpio54"; - function = "qup10"; - }; + qup_spi11_default: qup-spi11-default-state { + pins = "gpio31", "gpio32", "gpio33", "gpio34"; + function = "qup11"; }; - qup_spi11_default: qup-spi11-default { - pinmux { - pins = "gpio31", "gpio32", - "gpio33", "gpio34"; - function = "qup11"; - }; + qup_spi12_default: qup-spi12-default-state { + pins = "gpio49", "gpio50", "gpio51", "gpio52"; + function = "qup12"; }; - qup_spi12_default: qup-spi12-default { - pinmux { - pins = "gpio49", "gpio50", - "gpio51", "gpio52"; - function = "qup12"; - }; + qup_spi13_default: qup-spi13-default-state { + pins = "gpio105", "gpio106", "gpio107", "gpio108"; + function = "qup13"; }; - qup_spi13_default: qup-spi13-default { - pinmux { - pins = "gpio105", "gpio106", - "gpio107", "gpio108"; - function = "qup13"; - }; + qup_spi14_default: qup-spi14-default-state { + pins = "gpio33", "gpio34", "gpio31", "gpio32"; + function = "qup14"; }; - qup_spi14_default: qup-spi14-default { - pinmux { - pins = "gpio33", "gpio34", - "gpio31", "gpio32"; - function = "qup14"; - }; + qup_spi15_default: qup-spi15-default-state { + pins = "gpio81", "gpio82", "gpio83", "gpio84"; + function = "qup15"; }; - qup_spi15_default: qup-spi15-default { - pinmux { - pins = "gpio81", "gpio82", - "gpio83", "gpio84"; - function = "qup15"; + qup_uart0_default: qup-uart0-default-state { + qup_uart0_tx: tx-pins { + pins = "gpio2"; + function = "qup0"; }; - }; - qup_uart0_default: qup-uart0-default { - pinmux { - pins = "gpio2", "gpio3"; + qup_uart0_rx: rx-pins { + pins = "gpio3"; function = "qup0"; }; }; - qup_uart1_default: qup-uart1-default { - pinmux { - pins = "gpio19", "gpio20"; + qup_uart1_default: qup-uart1-default-state { + qup_uart1_tx: tx-pins { + pins = "gpio19"; + function = "qup1"; + }; + + qup_uart1_rx: rx-pins { + pins = "gpio20"; function = "qup1"; }; }; - qup_uart2_default: qup-uart2-default { - pinmux { - pins = "gpio29", "gpio30"; + qup_uart2_default: qup-uart2-default-state { + qup_uart2_tx: tx-pins { + pins = "gpio29"; + function = "qup2"; + }; + + qup_uart2_rx: rx-pins { + pins = "gpio30"; function = "qup2"; }; }; - qup_uart3_default: qup-uart3-default { - pinmux { - pins = "gpio43", "gpio44"; + qup_uart3_default: qup-uart3-default-state { + qup_uart3_tx: tx-pins { + pins = "gpio43"; + function = "qup3"; + }; + + qup_uart3_rx: rx-pins { + pins = "gpio44"; function = "qup3"; }; }; - qup_uart4_default: qup-uart4-default { - pinmux { - pins = "gpio91", "gpio92"; + qup_uart3_4pin: qup-uart3-4pin-state { + qup_uart3_4pin_cts: cts-pins { + pins = "gpio41"; + function = "qup3"; + }; + + qup_uart3_4pin_rts_tx: rts-tx-pins { + pins = "gpio42", "gpio43"; + function = "qup3"; + }; + + qup_uart3_4pin_rx: rx-pins { + pins = "gpio44"; + function = "qup3"; + }; + }; + + qup_uart4_default: qup-uart4-default-state { + qup_uart4_tx: tx-pins { + pins = "gpio91"; + function = "qup4"; + }; + + qup_uart4_rx: rx-pins { + pins = "gpio92"; function = "qup4"; }; }; - qup_uart5_default: qup-uart5-default { - pinmux { - pins = "gpio87", "gpio88"; + qup_uart5_default: qup-uart5-default-state { + qup_uart5_tx: tx-pins { + pins = "gpio87"; + function = "qup5"; + }; + + qup_uart5_rx: rx-pins { + pins = "gpio88"; function = "qup5"; }; }; - qup_uart6_default: qup-uart6-default { - pinmux { - pins = "gpio47", "gpio48"; + qup_uart6_default: qup-uart6-default-state { + qup_uart6_tx: tx-pins { + pins = "gpio47"; + function = "qup6"; + }; + + qup_uart6_rx: rx-pins { + pins = "gpio48"; function = "qup6"; }; }; qup_uart6_4pin: qup-uart6-4pin-state { - - cts-pins { + qup_uart6_4pin_cts: cts-pins { pins = "gpio45"; function = "qup6"; bias-pull-down; }; - rts-tx-pins { + qup_uart6_4pin_rts_tx: rts-tx-pins { pins = "gpio46", "gpio47"; function = "qup6"; drive-strength = <2>; bias-disable; }; - rx-pins { + qup_uart6_4pin_rx: rx-pins { pins = "gpio48"; function = "qup6"; bias-pull-up; }; }; - qup_uart7_default: qup-uart7-default { - pinmux { - pins = "gpio95", "gpio96"; + qup_uart7_default: qup-uart7-default-state { + qup_uart7_tx: tx-pins { + pins = "gpio95"; function = "qup7"; }; - }; - - qup_uart8_default: qup-uart8-default { - pinmux { - pins = "gpio67", "gpio68"; - function = "qup8"; - }; - }; - qup_uart9_default: qup-uart9-default { - pinmux { - pins = "gpio4", "gpio5"; - function = "qup9"; + qup_uart7_rx: rx-pins { + pins = "gpio96"; + function = "qup7"; }; }; - qup_uart10_default: qup-uart10-default { - pinmux { - pins = "gpio53", "gpio54"; - function = "qup10"; + qup_uart8_default: qup-uart8-default-state { + qup_uart8_tx: tx-pins { + pins = "gpio67"; + function = "qup8"; }; - }; - qup_uart11_default: qup-uart11-default { - pinmux { - pins = "gpio33", "gpio34"; - function = "qup11"; + qup_uart8_rx: rx-pins { + pins = "gpio68"; + function = "qup8"; }; }; - qup_uart12_default: qup-uart12-default { - pinmux { - pins = "gpio51", "gpio52"; - function = "qup12"; + qup_uart9_default: qup-uart9-default-state { + qup_uart9_tx: tx-pins { + pins = "gpio4"; + function = "qup9"; }; - }; - qup_uart13_default: qup-uart13-default { - pinmux { - pins = "gpio107", "gpio108"; - function = "qup13"; + qup_uart9_rx: rx-pins { + pins = "gpio5"; + function = "qup9"; }; }; - qup_uart14_default: qup-uart14-default { - pinmux { - pins = "gpio31", "gpio32"; - function = "qup14"; + qup_uart10_default: qup-uart10-default-state { + qup_uart10_tx: tx-pins { + pins = "gpio53"; + function = "qup10"; }; - }; - qup_uart15_default: qup-uart15-default { - pinmux { - pins = "gpio83", "gpio84"; - function = "qup15"; + qup_uart10_rx: rx-pins { + pins = "gpio54"; + function = "qup10"; }; }; - quat_mi2s_sleep: quat_mi2s_sleep { - mux { - pins = "gpio58", "gpio59"; - function = "gpio"; + qup_uart11_default: qup-uart11-default-state { + qup_uart11_tx: tx-pins { + pins = "gpio33"; + function = "qup11"; }; - config { - pins = "gpio58", "gpio59"; - drive-strength = <2>; - bias-pull-down; - input-enable; + qup_uart11_rx: rx-pins { + pins = "gpio34"; + function = "qup11"; }; }; - quat_mi2s_active: quat_mi2s_active { - mux { - pins = "gpio58", "gpio59"; - function = "qua_mi2s"; + qup_uart12_default: qup-uart12-default-state { + qup_uart12_tx: tx-pins { + pins = "gpio51"; + function = "qup0"; }; - config { - pins = "gpio58", "gpio59"; - drive-strength = <8>; - bias-disable; - output-high; + qup_uart12_rx: rx-pins { + pins = "gpio52"; + function = "qup0"; }; }; - quat_mi2s_sd0_sleep: quat_mi2s_sd0_sleep { - mux { - pins = "gpio60"; - function = "gpio"; + qup_uart13_default: qup-uart13-default-state { + qup_uart13_tx: tx-pins { + pins = "gpio107"; + function = "qup13"; }; - config { - pins = "gpio60"; - drive-strength = <2>; - bias-pull-down; - input-enable; + qup_uart13_rx: rx-pins { + pins = "gpio108"; + function = "qup13"; }; }; - quat_mi2s_sd0_active: quat_mi2s_sd0_active { - mux { - pins = "gpio60"; - function = "qua_mi2s"; + qup_uart14_default: qup-uart14-default-state { + qup_uart14_tx: tx-pins { + pins = "gpio31"; + function = "qup14"; }; - config { - pins = "gpio60"; - drive-strength = <8>; - bias-disable; + qup_uart14_rx: rx-pins { + pins = "gpio32"; + function = "qup14"; }; }; - quat_mi2s_sd1_sleep: quat_mi2s_sd1_sleep { - mux { - pins = "gpio61"; - function = "gpio"; + qup_uart15_default: qup-uart15-default-state { + qup_uart15_tx: tx-pins { + pins = "gpio83"; + function = "qup15"; }; - config { - pins = "gpio61"; - drive-strength = <2>; - bias-pull-down; - input-enable; + qup_uart15_rx: rx-pins { + pins = "gpio84"; + function = "qup15"; }; }; - quat_mi2s_sd1_active: quat_mi2s_sd1_active { - mux { - pins = "gpio61"; - function = "qua_mi2s"; - }; + quat_mi2s_sleep: quat-mi2s-sleep-state { + pins = "gpio58", "gpio59"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + input-enable; + }; - config { - pins = "gpio61"; - drive-strength = <8>; - bias-disable; - }; + quat_mi2s_active: quat-mi2s-active-state { + pins = "gpio58", "gpio59"; + function = "qua_mi2s"; + drive-strength = <8>; + bias-disable; + output-high; }; - quat_mi2s_sd2_sleep: quat_mi2s_sd2_sleep { - mux { - pins = "gpio62"; - function = "gpio"; - }; + quat_mi2s_sd0_sleep: quat-mi2s-sd0-sleep-state { + pins = "gpio60"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + input-enable; + }; - config { - pins = "gpio62"; - drive-strength = <2>; - bias-pull-down; - input-enable; - }; + quat_mi2s_sd0_active: quat-mi2s-sd0-active-state { + pins = "gpio60"; + function = "qua_mi2s"; + drive-strength = <8>; + bias-disable; }; - quat_mi2s_sd2_active: quat_mi2s_sd2_active { - mux { - pins = "gpio62"; - function = "qua_mi2s"; - }; + quat_mi2s_sd1_sleep: quat-mi2s-sd1-sleep-state { + pins = "gpio61"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + input-enable; + }; - config { - pins = "gpio62"; - drive-strength = <8>; - bias-disable; - }; + quat_mi2s_sd1_active: quat-mi2s-sd1-active-state { + pins = "gpio61"; + function = "qua_mi2s"; + drive-strength = <8>; + bias-disable; }; - quat_mi2s_sd3_sleep: quat_mi2s_sd3_sleep { - mux { - pins = "gpio63"; - function = "gpio"; - }; + quat_mi2s_sd2_sleep: quat-mi2s-sd2-sleep-state { + pins = "gpio62"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + input-enable; + }; - config { - pins = "gpio63"; - drive-strength = <2>; - bias-pull-down; - input-enable; - }; + quat_mi2s_sd2_active: quat-mi2s-sd2-active-state { + pins = "gpio62"; + function = "qua_mi2s"; + drive-strength = <8>; + bias-disable; }; - quat_mi2s_sd3_active: quat_mi2s_sd3_active { - mux { - pins = "gpio63"; - function = "qua_mi2s"; - }; + quat_mi2s_sd3_sleep: quat-mi2s-sd3-sleep-state { + pins = "gpio63"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + input-enable; + }; - config { - pins = "gpio63"; - drive-strength = <8>; - bias-disable; - }; + quat_mi2s_sd3_active: quat-mi2s-sd3-active-state { + pins = "gpio63"; + function = "qua_mi2s"; + drive-strength = <8>; + bias-disable; }; }; @@ -3283,6 +3288,10 @@ memory-region = <&mpss_region>; }; + metadata { + memory-region = <&mdata_mem>; + }; + glink-edge { interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; label = "modem"; @@ -3807,30 +3816,6 @@ }; }; - qspi_opp_table: opp-table-qspi { - compatible = "operating-points-v2"; - - opp-19200000 { - opp-hz = /bits/ 64 <19200000>; - required-opps = <&rpmhpd_opp_min_svs>; - }; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - - opp-150000000 { - opp-hz = /bits/ 64 <150000000>; - required-opps = <&rpmhpd_opp_svs>; - }; - - opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - required-opps = <&rpmhpd_opp_nom>; - }; - }; - qspi: spi@88df000 { compatible = "qcom,sdm845-qspi", "qcom,qspi-v1"; reg = <0 0x088df000 0 0x600>; @@ -3856,67 +3841,7 @@ iommus = <&apps_smmu 0x1806 0x0>; #address-cells = <1>; #size-cells = <0>; - - slim@1 { - reg = <1>; - #address-cells = <2>; - #size-cells = <0>; - - wcd9340_ifd: ifd@0,0 { - compatible = "slim217,250"; - reg = <0 0>; - }; - - wcd9340: codec@1,0 { - compatible = "slim217,250"; - reg = <1 0>; - slim-ifc-dev = <&wcd9340_ifd>; - - #sound-dai-cells = <1>; - - interrupts-extended = <&tlmm 54 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <1>; - - #clock-cells = <0>; - clock-frequency = <9600000>; - clock-output-names = "mclk"; - qcom,micbias1-microvolt = <1800000>; - qcom,micbias2-microvolt = <1800000>; - qcom,micbias3-microvolt = <1800000>; - qcom,micbias4-microvolt = <1800000>; - - #address-cells = <1>; - #size-cells = <1>; - - wcdgpio: gpio-controller@42 { - compatible = "qcom,wcd9340-gpio"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x42 0x2>; - }; - - swm: swm@c85 { - compatible = "qcom,soundwire-v1.3.0"; - reg = <0xc85 0x40>; - interrupts-extended = <&wcd9340 20>; - - qcom,dout-ports = <6>; - qcom,din-ports = <2>; - qcom,ports-sinterval-low =/bits/ 8 <0x07 0x1F 0x3F 0x7 0x1F 0x3F 0x0F 0x0F>; - qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0C 0x6 0x12 0x0D 0x07 0x0A >; - qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x1F 0x00 0x00 0x1F 0x00 0x00>; - - #sound-dai-cells = <1>; - clocks = <&wcd9340>; - clock-names = "iface"; - #address-cells = <2>; - #size-cells = <0>; - - - }; - }; - }; + status = "disabled"; }; lmh_cluster1: lmh@17d70800 { @@ -3943,9 +3868,6 @@ #interrupt-cells = <1>; }; - sound: sound { - }; - usb_1_hsphy: phy@88e2000 { compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy"; reg = <0 0x088e2000 0 0x400>; @@ -4239,16 +4161,16 @@ camss: camss@a00000 { compatible = "qcom,sdm845-camss"; - reg = <0 0xacb3000 0 0x1000>, - <0 0xacba000 0 0x1000>, - <0 0xacc8000 0 0x1000>, - <0 0xac65000 0 0x1000>, - <0 0xac66000 0 0x1000>, - <0 0xac67000 0 0x1000>, - <0 0xac68000 0 0x1000>, - <0 0xacaf000 0 0x4000>, - <0 0xacb6000 0 0x4000>, - <0 0xacc4000 0 0x4000>; + reg = <0 0x0acb3000 0 0x1000>, + <0 0x0acba000 0 0x1000>, + <0 0x0acc8000 0 0x1000>, + <0 0x0ac65000 0 0x1000>, + <0 0x0ac66000 0 0x1000>, + <0 0x0ac67000 0 0x1000>, + <0 0x0ac68000 0 0x1000>, + <0 0x0acaf000 0 0x4000>, + <0 0x0acb6000 0 0x4000>, + <0 0x0acc4000 0 0x4000>; reg-names = "csid0", "csid1", "csid2", @@ -4388,7 +4310,7 @@ }; cci: cci@ac4a000 { - compatible = "qcom,sdm845-cci"; + compatible = "qcom,sdm845-cci", "qcom,msm8996-cci"; #address-cells = <1>; #size-cells = <0>; @@ -4444,36 +4366,7 @@ clock-names = "bi_tcxo"; }; - dsi_opp_table: opp-table-dsi { - compatible = "operating-points-v2"; - - opp-19200000 { - opp-hz = /bits/ 64 <19200000>; - required-opps = <&rpmhpd_opp_min_svs>; - }; - - opp-180000000 { - opp-hz = /bits/ 64 <180000000>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - - opp-275000000 { - opp-hz = /bits/ 64 <275000000>; - required-opps = <&rpmhpd_opp_svs>; - }; - - opp-328580000 { - opp-hz = /bits/ 64 <328580000>; - required-opps = <&rpmhpd_opp_svs_l1>; - }; - - opp-358000000 { - opp-hz = /bits/ 64 <358000000>; - required-opps = <&rpmhpd_opp_nom>; - }; - }; - - mdss: mdss@ae00000 { + mdss: display-subsystem@ae00000 { compatible = "qcom,sdm845-mdss"; reg = <0 0x0ae00000 0 0x1000>; reg-names = "mdss"; @@ -4577,11 +4470,11 @@ status = "disabled"; compatible = "qcom,sdm845-dp"; - reg = <0 0xae90000 0 0x200>, - <0 0xae90200 0 0x200>, - <0 0xae90400 0 0x600>, - <0 0xae90a00 0 0x600>, - <0 0xae91000 0 0x600>; + reg = <0 0x0ae90000 0 0x200>, + <0 0x0ae90200 0 0x200>, + <0 0x0ae90400 0 0x600>, + <0 0x0ae90a00 0 0x600>, + <0 0x0ae91000 0 0x600>; interrupt-parent = <&mdss>; interrupts = <12>; @@ -4593,7 +4486,6 @@ <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; clock-names = "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", "stream_pixel"; - #clock-cells = <1>; assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; @@ -4619,7 +4511,7 @@ }; }; - dp_opp_table: dp-opp-table { + dp_opp_table: opp-table { compatible = "operating-points-v2"; opp-162000000 { @@ -4645,7 +4537,8 @@ }; dsi0: dsi@ae94000 { - compatible = "qcom,mdss-dsi-ctrl"; + compatible = "qcom,sdm845-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; reg = <0 0x0ae94000 0 0x400>; reg-names = "dsi_ctrl"; @@ -4716,7 +4609,8 @@ }; dsi1: dsi@ae96000 { - compatible = "qcom,mdss-dsi-ctrl"; + compatible = "qcom,sdm845-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; reg = <0 0x0ae96000 0 0x400>; reg-names = "dsi_ctrl"; @@ -4790,7 +4684,7 @@ gpu: gpu@5000000 { compatible = "qcom,adreno-630.2", "qcom,adreno"; - reg = <0 0x5000000 0 0x40000>, <0 0x509e000 0 0x10>; + reg = <0 0x05000000 0 0x40000>, <0 0x509e000 0 0x10>; reg-names = "kgsl_3d0_reg_memory", "cx_mem"; /* @@ -4860,7 +4754,7 @@ adreno_smmu: iommu@5040000 { compatible = "qcom,sdm845-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; - reg = <0 0x5040000 0 0x10000>; + reg = <0 0x05040000 0 0x10000>; #iommu-cells = <1>; #global-interrupts = <2>; interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, @@ -4883,9 +4777,9 @@ gmu: gmu@506a000 { compatible = "qcom,adreno-gmu-630.2", "qcom,adreno-gmu"; - reg = <0 0x506a000 0 0x30000>, - <0 0xb280000 0 0x10000>, - <0 0xb480000 0 0x10000>; + reg = <0 0x0506a000 0 0x30000>, + <0 0x0b280000 0 0x10000>, + <0 0x0b480000 0 0x10000>; reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, @@ -4992,7 +4886,7 @@ #reset-cells = <1>; }; - aoss_qmp: power-controller@c300000 { + aoss_qmp: power-management@c300000 { compatible = "qcom,sdm845-aoss-qmp", "qcom,aoss-qmp"; reg = <0 0x0c300000 0 0x400>; interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; @@ -5365,6 +5259,9 @@ }; }; + sound: sound { + }; + thermal-zones { cpu0-thermal { polling-delay-passive = <250>; @@ -5385,7 +5282,7 @@ type = "passive"; }; - cpu0_crit: cpu_crit { + cpu0_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -5412,7 +5309,7 @@ type = "passive"; }; - cpu1_crit: cpu_crit { + cpu1_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -5439,7 +5336,7 @@ type = "passive"; }; - cpu2_crit: cpu_crit { + cpu2_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -5466,7 +5363,7 @@ type = "passive"; }; - cpu3_crit: cpu_crit { + cpu3_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -5493,7 +5390,7 @@ type = "passive"; }; - cpu4_crit: cpu_crit { + cpu4_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -5520,7 +5417,7 @@ type = "passive"; }; - cpu5_crit: cpu_crit { + cpu5_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -5547,7 +5444,7 @@ type = "passive"; }; - cpu6_crit: cpu_crit { + cpu6_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -5574,7 +5471,7 @@ type = "passive"; }; - cpu7_crit: cpu_crit { + cpu7_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -5787,4 +5684,12 @@ }; }; }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; + }; }; diff --git a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts index f32b7445f7c9..67d2a663ce75 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts @@ -13,6 +13,7 @@ #include <dt-bindings/sound/qcom,q6afe.h> #include <dt-bindings/sound/qcom,q6asm.h> #include "sdm850.dtsi" +#include "sdm845-wcd9340.dtsi" #include "pm8998.dtsi" /* @@ -94,12 +95,12 @@ }; &adsp_pas { - firmware-name = "qcom/LENOVO/81JL/qcadsp850.mbn"; + firmware-name = "qcom/sdm850/LENOVO/81JL/qcadsp850.mbn"; status = "okay"; }; &apps_rsc { - pm8998-rpmh-regulators { + regulators-0 { compatible = "qcom,pm8998-rpmh-regulators"; qcom,pmic-id = "a"; @@ -306,7 +307,7 @@ }; &cdsp_pas { - firmware-name = "qcom/LENOVO/81JL/qccdsp850.mbn"; + firmware-name = "qcom/sdm850/LENOVO/81JL/qccdsp850.mbn"; status = "okay"; }; @@ -345,7 +346,7 @@ status = "okay"; zap-shader { memory-region = <&gpu_mem>; - firmware-name = "qcom/LENOVO/81JL/qcdxkmsuc850.mbn"; + firmware-name = "qcom/sdm850/LENOVO/81JL/qcdxkmsuc850.mbn"; }; }; @@ -465,8 +466,9 @@ }; &ipa { - status = "okay"; + qcom,gsi-loader = "self"; memory-region = <&ipa_fw_mem>; + status = "okay"; }; &mdss { @@ -475,45 +477,17 @@ &mss_pil { status = "okay"; - firmware-name = "qcom/LENOVO/81JL/qcdsp1v2850.mbn", "qcom/LENOVO/81JL/qcdsp2850.mbn"; + firmware-name = "qcom/sdm850/LENOVO/81JL/qcdsp1v2850.mbn", "qcom/sdm850/LENOVO/81JL/qcdsp2850.mbn"; }; &qup_i2c10_default { - pinconf { - pins = "gpio55", "gpio56"; - drive-strength = <2>; - bias-disable; - }; + drive-strength = <2>; + bias-disable; }; &qup_i2c12_default { - pinmux { - drive-strength = <2>; - bias-disable; - }; -}; - -&qup_uart6_default { - pinmux { - pins = "gpio45", "gpio46", "gpio47", "gpio48"; - function = "qup6"; - }; - - cts { - pins = "gpio45"; - bias-pull-down; - }; - - rts-tx { - pins = "gpio46", "gpio47"; - drive-strength = <2>; - bias-disable; - }; - - rx { - pins = "gpio48"; - bias-pull-up; - }; + drive-strength = <2>; + bias-disable; }; &qupv3_id_0 { @@ -539,7 +513,7 @@ }; &sound { - compatible = "qcom,db845c-sndcard"; + compatible = "lenovo,yoga-c630-sndcard", "qcom,sdm845-sndcard"; model = "Lenovo-YOGA-C630-13Q50"; audio-routing = @@ -621,13 +595,14 @@ &tlmm { gpio-reserved-ranges = <0 4>, <81 4>; - sn65dsi86_pin_active: sn65dsi86-enable { + sn65dsi86_pin_active: sn65dsi86-enable-state { pins = "gpio96"; + function = "gpio"; drive-strength = <2>; bias-disable; }; - i2c3_hid_active: i2c2-hid-active { + i2c3_hid_active: i2c2-hid-active-state { pins = "gpio37"; function = "gpio"; @@ -636,7 +611,7 @@ drive-strength = <2>; }; - i2c5_hid_active: i2c5-hid-active { + i2c5_hid_active: i2c5-hid-active-state { pins = "gpio125"; function = "gpio"; @@ -645,7 +620,7 @@ drive-strength = <2>; }; - i2c11_hid_active: i2c11-hid-active { + i2c11_hid_active: i2c11-hid-active-state { pins = "gpio92"; function = "gpio"; @@ -654,16 +629,7 @@ drive-strength = <2>; }; - wcd_intr_default: wcd_intr_default { - pins = "gpio54"; - function = "gpio"; - - input-enable; - bias-pull-down; - drive-strength = <2>; - }; - - lid_pin_active: lid-pin { + lid_pin_active: lid-pin-state { pins = "gpio124"; function = "gpio"; @@ -671,7 +637,7 @@ bias-disable; }; - mode_pin_active: mode-pin { + mode_pin_active: mode-pin-state { pins = "gpio95"; function = "gpio"; @@ -681,6 +647,8 @@ }; &uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart6_4pin>; status = "okay"; bluetooth { @@ -766,14 +734,11 @@ }; &venus { + firmware-name = "qcom/sdm850/LENOVO/81JL/qcvss850.mbn"; status = "okay"; }; -&wcd9340{ - pinctrl-0 = <&wcd_intr_default>; - pinctrl-names = "default"; - clock-names = "extclk"; - clocks = <&rpmhcc RPMH_LN_BB_CLK2>; +&wcd9340 { reset-gpios = <&tlmm 64 GPIO_ACTIVE_HIGH>; vdd-buck-supply = <&vreg_s4a_1p8>; vdd-buck-sido-supply = <&vreg_s4a_1p8>; diff --git a/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts b/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts index daca1e0ad62a..9850140514ba 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts @@ -14,6 +14,7 @@ #include <dt-bindings/sound/qcom,q6afe.h> #include <dt-bindings/sound/qcom,q6asm.h> #include "sdm850.dtsi" +#include "sdm845-wcd9340.dtsi" #include "pm8998.dtsi" /* @@ -129,7 +130,7 @@ }; &apps_rsc { - pm8998-rpmh-regulators { + regulators-0 { compatible = "qcom,pm8998-rpmh-regulators"; qcom,pmic-id = "a"; @@ -383,9 +384,10 @@ }; &ipa { - status = "okay"; + qcom,gsi-loader = "self"; memory-region = <&ipa_fw_mem>; firmware-name = "qcom/sdm850/samsung/w737/ipa_fws.elf"; + status = "okay"; }; /* No idea why it causes an SError when enabled */ @@ -399,49 +401,18 @@ }; &qup_i2c10_default { - pinconf { - pins = "gpio55", "gpio56"; - drive-strength = <2>; - bias-disable; - }; + drive-strength = <2>; + bias-disable; }; &qup_i2c11_default { - pinconf { - pins = "gpio31", "gpio32"; - drive-strength = <2>; - bias-disable; - }; + drive-strength = <2>; + bias-disable; }; &qup_i2c12_default { - pinmux { - drive-strength = <2>; - bias-disable; - }; -}; - -&qup_uart6_default { - pinmux { - pins = "gpio45", "gpio46", "gpio47", "gpio48"; - function = "qup6"; - }; - - cts { - pins = "gpio45"; - bias-pull-down; - }; - - rts-tx { - pins = "gpio46", "gpio47"; - drive-strength = <2>; - bias-disable; - }; - - rx { - pins = "gpio48"; - bias-pull-up; - }; + drive-strength = <2>; + bias-disable; }; &qupv3_id_0 { @@ -549,69 +520,44 @@ &tlmm { gpio-reserved-ranges = <0 6>, <85 4>; - pen_irq_l: pen-irq-l { - pinmux { - pins = "gpio119"; - function = "gpio"; - }; - - pinconf { - pins = "gpio119"; - bias-disable; - }; - }; - - pen_pdct_l: pen-pdct-l { - pinmux { - pins = "gpio124"; - function = "gpio"; - }; - - pinconf { - pins = "gpio124"; - bias-disable; - drive-strength = <2>; - output-high; - }; + pen_irq_l: pen-irq-l-state { + pins = "gpio119"; + function = "gpio"; + bias-disable; }; - pen_rst_l: pen-rst-l { - pinmux { - pins = "gpio21"; - function = "gpio"; - }; - - pinconf { - pins = "gpio21"; - bias-disable; - drive-strength = <2>; - - /* - * The pen driver doesn't currently support - * driving this reset line. By specifying - * output-high here we're relying on the fact - * that this pin has a default pulldown at boot - * (which makes sure the pen was in reset if it - * was powered) and then we set it high here to - * take it out of reset. Better would be if the - * pen driver could control this and we could - * remove "output-high" here. - */ - output-high; - }; + pen_pdct_l: pen-pdct-l-state { + pins = "gpio124"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + output-high; }; - wcd_intr_default: wcd_intr_default { - pins = "gpio54"; + pen_rst_l: pen-rst-l-state { + pins = "gpio21"; function = "gpio"; - - input-enable; - bias-pull-down; + bias-disable; drive-strength = <2>; + + /* + * The pen driver doesn't currently support + * driving this reset line. By specifying + * output-high here we're relying on the fact + * that this pin has a default pulldown at boot + * (which makes sure the pen was in reset if it + * was powered) and then we set it high here to + * take it out of reset. Better would be if the + * pen driver could control this and we could + * remove "output-high" here. + */ + output-high; }; }; &uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart6_4pin>; status = "okay"; bluetooth { @@ -701,11 +647,7 @@ firmware-name = "qcom/sdm850/samsung/w737/qcvss850.mbn"; }; -&wcd9340{ - pinctrl-0 = <&wcd_intr_default>; - pinctrl-names = "default"; - clock-names = "extclk"; - clocks = <&rpmhcc RPMH_LN_BB_CLK2>; +&wcd9340 { reset-gpios = <&tlmm 64 GPIO_ACTIVE_HIGH>; vdd-buck-supply = <&vreg_s4a_1p8>; vdd-buck-sido-supply = <&vreg_s4a_1p8>; diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index 572bf04adf90..4d6ec815b78b 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -296,6 +296,8 @@ rpmcc: clock-controller { compatible = "qcom,rpmcc-sm6115", "qcom,rpmcc"; + clocks = <&xo_board>; + clock-names = "xo"; #clock-cells = <1>; }; @@ -343,25 +345,100 @@ }; }; + smp2p-adsp { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + + interrupts = <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>; + + mboxes = <&apcs_glb 10>; + + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-cdsp { + compatible = "qcom,smp2p"; + qcom,smem = <94>, <432>; + + interrupts = <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>; + + mboxes = <&apcs_glb 30>; + + qcom,local-pid = <0>; + qcom,remote-pid = <5>; + + cdsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + cdsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-mpss { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + + interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>; + + mboxes = <&apcs_glb 14>; + + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + soc: soc@0 { compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0 0xffffffff>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0 0 0 0x10 0>; + dma-ranges = <0 0 0 0 0x10 0>; tcsr_mutex: hwlock@340000 { compatible = "qcom,tcsr-mutex"; - reg = <0x00340000 0x20000>; + reg = <0x0 0x00340000 0x0 0x20000>; #hwlock-cells = <1>; }; tlmm: pinctrl@500000 { compatible = "qcom,sm6115-tlmm"; - reg = <0x00500000 0x400000>, <0x00900000 0x400000>, <0x00d00000 0x400000>; + reg = <0x0 0x00500000 0x0 0x400000>, + <0x0 0x00900000 0x0 0x400000>, + <0x0 0x00d00000 0x0 0x400000>; reg-names = "west", "south", "east"; interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; - gpio-ranges = <&tlmm 0 0 121>; + gpio-ranges = <&tlmm 0 0 114>; /* GPIOs + ufs_reset */ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; @@ -557,7 +634,7 @@ gcc: clock-controller@1400000 { compatible = "qcom,gcc-sm6115"; - reg = <0x01400000 0x1f0000>; + reg = <0x0 0x01400000 0x0 0x1f0000>; clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; clock-names = "bi_tcxo", "sleep_clk"; #clock-cells = <1>; @@ -567,7 +644,7 @@ usb_1_hsphy: phy@1613000 { compatible = "qcom,sm6115-qusb2-phy"; - reg = <0x01613000 0x180>; + reg = <0x0 0x01613000 0x0 0x180>; #phy-cells = <0>; clocks = <&gcc GCC_AHB2PHY_USB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; @@ -581,7 +658,7 @@ qfprom@1b40000 { compatible = "qcom,sm6115-qfprom", "qcom,qfprom"; - reg = <0x01b40000 0x7000>; + reg = <0x0 0x01b40000 0x0 0x7000>; #address-cells = <1>; #size-cells = <1>; @@ -593,18 +670,18 @@ rng: rng@1b53000 { compatible = "qcom,prng-ee"; - reg = <0x01b53000 0x1000>; + reg = <0x0 0x01b53000 0x0 0x1000>; clocks = <&gcc GCC_PRNG_AHB_CLK>; clock-names = "core"; }; spmi_bus: spmi@1c40000 { compatible = "qcom,spmi-pmic-arb"; - reg = <0x01c40000 0x1100>, - <0x01e00000 0x2000000>, - <0x03e00000 0x100000>, - <0x03f00000 0xa0000>, - <0x01c0a000 0x26000>; + reg = <0x0 0x01c40000 0x0 0x1100>, + <0x0 0x01e00000 0x0 0x2000000>, + <0x0 0x03e00000 0x0 0x100000>, + <0x0 0x03f00000 0x0 0xa0000>, + <0x0 0x01c0a000 0x0 0x26000>; reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; interrupt-names = "periph_irq"; interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; @@ -618,8 +695,8 @@ tsens0: thermal-sensor@4410000 { compatible = "qcom,sm6115-tsens", "qcom,tsens-v2"; - reg = <0x04411000 0x1ff>, /* TM */ - <0x04410000 0x8>; /* SROT */ + reg = <0x0 0x04411000 0x0 0x1ff>, /* TM */ + <0x0 0x04410000 0x0 0x8>; /* SROT */ #qcom,sensors = <16>; interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; @@ -629,17 +706,19 @@ rpm_msg_ram: sram@45f0000 { compatible = "qcom,rpm-msg-ram"; - reg = <0x045f0000 0x7000>; + reg = <0x0 0x045f0000 0x0 0x7000>; }; sram@4690000 { compatible = "qcom,rpm-stats"; - reg = <0x04690000 0x10000>; + reg = <0x0 0x04690000 0x0 0x10000>; }; sdhc_1: mmc@4744000 { compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5"; - reg = <0x04744000 0x1000>, <0x04745000 0x1000>, <0x04748000 0x8000>; + reg = <0x0 0x04744000 0x0 0x1000>, + <0x0 0x04745000 0x0 0x1000>, + <0x0 0x04748000 0x0 0x8000>; reg-names = "hc", "cqhci", "ice"; interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, @@ -648,7 +727,7 @@ clocks = <&gcc GCC_SDCC1_AHB_CLK>, <&gcc GCC_SDCC1_APPS_CLK>, - <&xo_board>, + <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GCC_SDCC1_ICE_CORE_CLK>; clock-names = "iface", "core", "xo", "ice"; @@ -662,14 +741,16 @@ sdhc_2: mmc@4784000 { compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5"; - reg = <0x04784000 0x1000>; + reg = <0x0 0x04784000 0x0 0x1000>; reg-names = "hc"; interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; - clocks = <&gcc GCC_SDCC2_AHB_CLK>, <&gcc GCC_SDCC2_APPS_CLK>, <&xo_board>; + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; clock-names = "iface", "core", "xo"; pinctrl-0 = <&sdc2_state_on>; @@ -703,7 +784,8 @@ ufs_mem_hc: ufs@4804000 { compatible = "qcom,sm6115-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; - reg = <0x04804000 0x3000>, <0x04810000 0x8000>; + reg = <0x0 0x04804000 0x0 0x3000>, <0x0 0x04810000 0x0 0x8000>; + reg-names = "std", "ice"; interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; phys = <&ufs_mem_phy_lanes>; phy-names = "ufsphy"; @@ -736,19 +818,19 @@ <0 0>, <0 0>, <37500000 150000000>, - <75000000 300000000>, <0 0>, <0 0>, - <0 0>; + <0 0>, + <75000000 300000000>; status = "disabled"; }; ufs_mem_phy: phy@4807000 { compatible = "qcom,sm6115-qmp-ufs-phy"; - reg = <0x04807000 0x1c4>; - #address-cells = <1>; - #size-cells = <1>; + reg = <0x0 0x04807000 0x0 0x1c4>; + #address-cells = <2>; + #size-cells = <2>; ranges; clocks = <&gcc GCC_UFS_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; @@ -759,16 +841,16 @@ status = "disabled"; ufs_mem_phy_lanes: phy@4807400 { - reg = <0x4807400 0x098>, - <0x4807600 0x130>, - <0x4807c00 0x16c>; + reg = <0x0 0x04807400 0x0 0x098>, + <0x0 0x04807600 0x0 0x130>, + <0x0 0x04807c00 0x0 0x16c>; #phy-cells = <0>; }; }; gpi_dma0: dma-controller@4a00000 { compatible = "qcom,sm6115-gpi-dma", "qcom,sm6350-gpi-dma"; - reg = <0x04a00000 0x60000>; + reg = <0x0 0x04a00000 0x0 0x60000>; interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, @@ -788,19 +870,19 @@ qupv3_id_0: geniqup@4ac0000 { compatible = "qcom,geni-se-qup"; - reg = <0x04ac0000 0x2000>; + reg = <0x0 0x04ac0000 0x0 0x2000>; clock-names = "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; - #address-cells = <1>; - #size-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; iommus = <&apps_smmu 0xe3 0x0>; ranges; status = "disabled"; i2c0: i2c@4a80000 { compatible = "qcom,geni-i2c"; - reg = <0x04a80000 0x4000>; + reg = <0x0 0x04a80000 0x0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; pinctrl-names = "default"; @@ -816,7 +898,7 @@ spi0: spi@4a80000 { compatible = "qcom,geni-spi"; - reg = <0x04a80000 0x4000>; + reg = <0x0 0x04a80000 0x0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; pinctrl-names = "default"; @@ -832,7 +914,7 @@ i2c1: i2c@4a84000 { compatible = "qcom,geni-i2c"; - reg = <0x04a84000 0x4000>; + reg = <0x0 0x04a84000 0x0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; pinctrl-names = "default"; @@ -848,7 +930,7 @@ spi1: spi@4a84000 { compatible = "qcom,geni-spi"; - reg = <0x04a84000 0x4000>; + reg = <0x0 0x04a84000 0x0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; pinctrl-names = "default"; @@ -864,7 +946,7 @@ i2c2: i2c@4a88000 { compatible = "qcom,geni-i2c"; - reg = <0x04a88000 0x4000>; + reg = <0x0 0x04a88000 0x0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; pinctrl-names = "default"; @@ -880,7 +962,7 @@ spi2: spi@4a88000 { compatible = "qcom,geni-spi"; - reg = <0x04a88000 0x4000>; + reg = <0x0 0x04a88000 0x0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; pinctrl-names = "default"; @@ -896,7 +978,7 @@ i2c3: i2c@4a8c000 { compatible = "qcom,geni-i2c"; - reg = <0x04a8c000 0x4000>; + reg = <0x0 0x04a8c000 0x0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; pinctrl-names = "default"; @@ -912,7 +994,7 @@ spi3: spi@4a8c000 { compatible = "qcom,geni-spi"; - reg = <0x04a8c000 0x4000>; + reg = <0x0 0x04a8c000 0x0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; pinctrl-names = "default"; @@ -928,7 +1010,7 @@ i2c4: i2c@4a90000 { compatible = "qcom,geni-i2c"; - reg = <0x04a90000 0x4000>; + reg = <0x0 0x04a90000 0x0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; pinctrl-names = "default"; @@ -944,7 +1026,7 @@ spi4: spi@4a90000 { compatible = "qcom,geni-spi"; - reg = <0x04a90000 0x4000>; + reg = <0x0 0x04a90000 0x0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; pinctrl-names = "default"; @@ -958,9 +1040,18 @@ status = "disabled"; }; + uart4: serial@4a90000 { + compatible = "qcom,geni-debug-uart"; + reg = <0x0 0x04a90000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + i2c5: i2c@4a94000 { compatible = "qcom,geni-i2c"; - reg = <0x04a94000 0x4000>; + reg = <0x0 0x04a94000 0x0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; pinctrl-names = "default"; @@ -976,7 +1067,7 @@ spi5: spi@4a94000 { compatible = "qcom,geni-spi"; - reg = <0x04a94000 0x4000>; + reg = <0x0 0x04a94000 0x0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; pinctrl-names = "default"; @@ -987,15 +1078,14 @@ dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; - status = "disabled"; }; }; usb_1: usb@4ef8800 { compatible = "qcom,sm6115-dwc3", "qcom,dwc3"; - reg = <0x04ef8800 0x400>; - #address-cells = <1>; - #size-cells = <1>; + reg = <0x0 0x04ef8800 0x0 0x400>; + #address-cells = <2>; + #size-cells = <2>; ranges; clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, @@ -1021,7 +1111,7 @@ usb_1_dwc3: usb@4e00000 { compatible = "snps,dwc3"; - reg = <0x04e00000 0xcd00>; + reg = <0x0 0x04e00000 0x0 0xcd00>; interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; phys = <&usb_1_hsphy>; phy-names = "usb2-phy"; @@ -1038,7 +1128,7 @@ mdss: display-subsystem@5e00000 { compatible = "qcom,sm6115-mdss"; - reg = <0x05e00000 0x1000>; + reg = <0x0 0x05e00000 0x0 0x1000>; reg-names = "mdss"; power-domains = <&dispcc MDSS_GDSC>; @@ -1054,16 +1144,16 @@ iommus = <&apps_smmu 0x420 0x2>, <&apps_smmu 0x421 0x0>; - #address-cells = <1>; - #size-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; ranges; status = "disabled"; mdp: display-controller@5e01000 { compatible = "qcom,sm6115-dpu"; - reg = <0x05e01000 0x8f000>, - <0x05eb0000 0x2008>; + reg = <0x0 0x05e01000 0x0 0x8f000>, + <0x0 0x05eb0000 0x0 0x2008>; reg-names = "mdp", "vbif"; clocks = <&gcc GCC_DISP_HF_AXI_CLK>, @@ -1092,7 +1182,7 @@ port@0 { reg = <0>; dpu_intf1_out: endpoint { - remote-endpoint = <&dsi0_in>; + remote-endpoint = <&mdss_dsi0_in>; }; }; }; @@ -1127,9 +1217,9 @@ }; }; - dsi0: dsi@5e94000 { + mdss_dsi0: dsi@5e94000 { compatible = "qcom,dsi-ctrl-6g-qcm2290"; - reg = <0x05e94000 0x400>; + reg = <0x0 0x05e94000 0x0 0x400>; reg-names = "dsi_ctrl"; interrupt-parent = <&mdss>; @@ -1150,11 +1240,11 @@ assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; - assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; operating-points-v2 = <&dsi_opp_table>; power-domains = <&rpmpd SM6115_VDDCX>; - phys = <&dsi0_phy>; + phys = <&mdss_dsi0_phy>; #address-cells = <1>; #size-cells = <0>; @@ -1167,14 +1257,14 @@ port@0 { reg = <0>; - dsi0_in: endpoint { + mdss_dsi0_in: endpoint { remote-endpoint = <&dpu_intf1_out>; }; }; port@1 { reg = <1>; - dsi0_out: endpoint { + mdss_dsi0_out: endpoint { }; }; }; @@ -1199,11 +1289,11 @@ }; }; - dsi0_phy: phy@5e94400 { + mdss_dsi0_phy: phy@5e94400 { compatible = "qcom,dsi-phy-14nm-2290"; - reg = <0x05e94400 0x100>, - <0x05e94500 0x300>, - <0x05e94800 0x188>; + reg = <0x0 0x05e94400 0x0 0x100>, + <0x0 0x05e94500 0x0 0x300>, + <0x0 0x05e94800 0x0 0x188>; reg-names = "dsi_phy", "dsi_phy_lane", "dsi_pll"; @@ -1221,20 +1311,632 @@ dispcc: clock-controller@5f00000 { compatible = "qcom,sm6115-dispcc"; - reg = <0x05f00000 0x20000>; + reg = <0x0 0x05f00000 0 0x20000>; clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>, - <&dsi0_phy 0>, - <&dsi0_phy 1>, + <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>, <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; }; + stm@8002000 { + compatible = "arm,coresight-stm", "arm,primecell"; + reg = <0x0 0x08002000 0x0 0x1000>, + <0x0 0x0e280000 0x0 0x180000>; + reg-names = "stm-base", "stm-stimulus-base"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + + out-ports { + port { + stm_out: endpoint { + remote-endpoint = <&funnel_in0_in>; + }; + }; + }; + }; + + cti0: cti@8010000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x08010000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + }; + + cti1: cti@8011000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x08011000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + }; + + cti2: cti@8012000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x08012000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + }; + + cti3: cti@8013000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x08013000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + }; + + cti4: cti@8014000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x08014000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + }; + + cti5: cti@8015000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x08015000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + }; + + cti6: cti@8016000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x08016000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + }; + + cti7: cti@8017000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x08017000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + }; + + cti8: cti@8018000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x08018000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + }; + + cti9: cti@8019000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x08019000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + }; + + cti10: cti@801a000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x0801a000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + }; + + cti11: cti@801b000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x0801b000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + }; + + cti12: cti@801c000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x0801c000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + }; + + cti13: cti@801d000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x0801d000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + }; + + cti14: cti@801e000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x0801e000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + }; + + cti15: cti@801f000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x0801f000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + }; + + replicator@8046000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0x0 0x08046000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + + out-ports { + port { + replicator_out: endpoint { + remote-endpoint = <&etr_in>; + }; + }; + }; + + in-ports { + port { + replicator_in: endpoint { + remote-endpoint = <&etf_out>; + }; + }; + }; + }; + + etf@8047000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x0 0x08047000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + + in-ports { + port { + etf_in: endpoint { + remote-endpoint = <&merge_funnel_out>; + }; + }; + }; + + out-ports { + port { + etf_out: endpoint { + remote-endpoint = <&replicator_in>; + }; + }; + }; + }; + + etr@8048000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x0 0x08048000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + + in-ports { + port { + etr_in: endpoint { + remote-endpoint = <&replicator_out>; + }; + }; + }; + }; + + funnel@8041000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x08041000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + + out-ports { + port { + funnel_in0_out: endpoint { + remote-endpoint = <&merge_funnel_in0>; + }; + }; + }; + + in-ports { + port { + funnel_in0_in: endpoint { + remote-endpoint = <&stm_out>; + }; + }; + }; + }; + + funnel@8042000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x08042000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + + out-ports { + port { + funnel_in1_out: endpoint { + remote-endpoint = <&merge_funnel_in1>; + }; + }; + }; + + in-ports { + port { + funnel_in1_in: endpoint { + remote-endpoint = <&funnel_apss1_out>; + }; + }; + }; + }; + + funnel@8045000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x08045000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + + out-ports { + port { + merge_funnel_out: endpoint { + remote-endpoint = <&etf_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + merge_funnel_in0: endpoint { + remote-endpoint = <&funnel_in0_out>; + }; + }; + + port@1 { + reg = <1>; + merge_funnel_in1: endpoint { + remote-endpoint = <&funnel_in1_out>; + }; + }; + }; + }; + + etm@9040000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x0 0x09040000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + + cpu = <&CPU0>; + + status = "disabled"; + + out-ports { + port { + etm0_out: endpoint { + remote-endpoint = <&funnel_apss0_in0>; + }; + }; + }; + }; + + etm@9140000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x0 0x09140000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + + cpu = <&CPU1>; + + status = "disabled"; + + out-ports { + port { + etm1_out: endpoint { + remote-endpoint = <&funnel_apss0_in1>; + }; + }; + }; + }; + + etm@9240000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x0 0x09240000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + + cpu = <&CPU2>; + + status = "disabled"; + + out-ports { + port { + etm2_out: endpoint { + remote-endpoint = <&funnel_apss0_in2>; + }; + }; + }; + }; + + etm@9340000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x0 0x09340000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + + cpu = <&CPU3>; + + status = "disabled"; + + out-ports { + port { + etm3_out: endpoint { + remote-endpoint = <&funnel_apss0_in3>; + }; + }; + }; + }; + + etm@9440000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x0 0x09440000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + + cpu = <&CPU4>; + + status = "disabled"; + + out-ports { + port { + etm4_out: endpoint { + remote-endpoint = <&funnel_apss0_in4>; + }; + }; + }; + }; + + etm@9540000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x0 0x09540000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + + cpu = <&CPU5>; + + status = "disabled"; + + out-ports { + port { + etm5_out: endpoint { + remote-endpoint = <&funnel_apss0_in5>; + }; + }; + }; + }; + + etm@9640000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x0 0x09640000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + + cpu = <&CPU6>; + + status = "disabled"; + + out-ports { + port { + etm6_out: endpoint { + remote-endpoint = <&funnel_apss0_in6>; + }; + }; + }; + }; + + etm@9740000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x0 0x09740000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + + cpu = <&CPU7>; + + status = "disabled"; + + out-ports { + port { + etm7_out: endpoint { + remote-endpoint = <&funnel_apss0_in7>; + }; + }; + }; + }; + + funnel@9800000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x09800000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + + out-ports { + port { + funnel_apss0_out: endpoint { + remote-endpoint = <&funnel_apss1_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_apss0_in0: endpoint { + remote-endpoint = <&etm0_out>; + }; + }; + + port@1 { + reg = <1>; + funnel_apss0_in1: endpoint { + remote-endpoint = <&etm1_out>; + }; + }; + + port@2 { + reg = <2>; + funnel_apss0_in2: endpoint { + remote-endpoint = <&etm2_out>; + }; + }; + + port@3 { + reg = <3>; + funnel_apss0_in3: endpoint { + remote-endpoint = <&etm3_out>; + }; + }; + + port@4 { + reg = <4>; + funnel_apss0_in4: endpoint { + remote-endpoint = <&etm4_out>; + }; + }; + + port@5 { + reg = <5>; + funnel_apss0_in5: endpoint { + remote-endpoint = <&etm5_out>; + }; + }; + + port@6 { + reg = <6>; + funnel_apss0_in6: endpoint { + remote-endpoint = <&etm6_out>; + }; + }; + + port@7 { + reg = <7>; + funnel_apss0_in7: endpoint { + remote-endpoint = <&etm7_out>; + }; + }; + }; + }; + + funnel@9810000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x09810000 0x0 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + + out-ports { + port { + funnel_apss1_out: endpoint { + remote-endpoint = <&funnel_in1_in>; + }; + }; + }; + + in-ports { + port { + funnel_apss1_in: endpoint { + remote-endpoint = <&funnel_apss0_out>; + }; + }; + }; + }; + apps_smmu: iommu@c600000 { compatible = "qcom,sm6115-smmu-500", "qcom,smmu-500", "arm,mmu-500"; - reg = <0x0c600000 0x80000>; + reg = <0x0 0x0c600000 0x0 0x80000>; #iommu-cells = <2>; #global-interrupts = <1>; @@ -1307,7 +2009,7 @@ wifi: wifi@c800000 { compatible = "qcom,wcn3990-wifi"; - reg = <0x0c800000 0x800000>; + reg = <0x0 0x0c800000 0x0 0x800000>; reg-names = "membase"; memory-region = <&wlan_msa_mem>; interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, @@ -1327,65 +2029,72 @@ status = "disabled"; }; + watchdog@f017000 { + compatible = "qcom,apss-wdt-sm6115", "qcom,kpss-wdt"; + reg = <0x0 0x0f017000 0x0 0x1000>; + clocks = <&sleep_clk>; + interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; + }; + apcs_glb: mailbox@f111000 { compatible = "qcom,sm6115-apcs-hmss-global"; - reg = <0x0f111000 0x1000>; + reg = <0x0 0x0f111000 0x0 0x1000>; #mbox-cells = <1>; }; timer@f120000 { compatible = "arm,armv7-timer-mem"; - reg = <0x0f120000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; + reg = <0x0 0x0f120000 0x0 0x1000>; + #address-cells = <2>; + #size-cells = <2>; ranges; clock-frequency = <19200000>; frame@f121000 { - reg = <0x0f121000 0x1000>, <0x0f122000 0x1000>; + reg = <0x0 0x0f121000 0x0 0x1000>, <0x0 0x0f122000 0x0 0x1000>; frame-number = <0>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; }; frame@f123000 { - reg = <0x0f123000 0x1000>; + reg = <0x0 0x0f123000 0x0 0x1000>; frame-number = <1>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; frame@f124000 { - reg = <0x0f124000 0x1000>; + reg = <0x0 0x0f124000 0x0 0x1000>; frame-number = <2>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; frame@f125000 { - reg = <0x0f125000 0x1000>; + reg = <0x0 0x0f125000 0x0 0x1000>; frame-number = <3>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; frame@f126000 { - reg = <0x0f126000 0x1000>; + reg = <0x0 0x0f126000 0x0 0x1000>; frame-number = <4>; interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; frame@f127000 { - reg = <0x0f127000 0x1000>; + reg = <0x0 0x0f127000 0x0 0x1000>; frame-number = <5>; interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; frame@f128000 { - reg = <0x0f128000 0x1000>; + reg = <0x0 0x0f128000 0x0 0x1000>; frame-number = <6>; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; @@ -1394,7 +2103,8 @@ intc: interrupt-controller@f200000 { compatible = "arm,gic-v3"; - reg = <0x0f200000 0x10000>, <0x0f300000 0x100000>; + reg = <0x0 0x0f200000 0x0 0x10000>, + <0x0 0x0f300000 0x0 0x100000>; #interrupt-cells = <3>; interrupt-controller; interrupt-parent = <&intc>; @@ -1405,7 +2115,8 @@ cpufreq_hw: cpufreq@f521000 { compatible = "qcom,cpufreq-hw"; - reg = <0x0f521000 0x1000>, <0x0f523000 0x1000>; + reg = <0x0 0x0f521000 0x0 0x1000>, + <0x0 0x0f523000 0x0 0x1000>; reg-names = "freq-domain0", "freq-domain1"; clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; @@ -1415,6 +2126,370 @@ }; }; + thermal-zones { + mapss-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 0>; + + trips { + trip-point0 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cdsp-hvx-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 1>; + + trips { + trip-point0 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + wlan-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 2>; + + trips { + trip-point0 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + camera-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 3>; + + trips { + trip-point0 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + video-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 4>; + + trips { + trip-point0 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + modem1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 5>; + + trips { + trip-point0 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cpu4-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 6>; + + trips { + cpu4_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu4_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu4_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu5-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 7>; + + trips { + cpu5_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu5_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu5_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu6-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 8>; + + trips { + cpu6_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu6_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu6_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu7-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 9>; + + trips { + cpu7_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu7_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu7_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu45-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 10>; + + trips { + cpu45_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu45_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu45_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu67-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 11>; + + trips { + cpu67_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu67_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu67_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu0123-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 12>; + + trips { + cpu0123_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu0123_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu0123_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + modem0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 13>; + + trips { + trip-point0 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + display-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 14>; + + trips { + trip-point0 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + gpu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 15>; + + trips { + trip-point0 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + trip-point1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, diff --git a/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts b/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts new file mode 100644 index 000000000000..4ce2d905d70e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts @@ -0,0 +1,289 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) 2022 Linaro Limited + */ + +/dts-v1/; + +#include "sm6115.dtsi" +#include "pm6125.dtsi" + +/ { + model = "Lenovo Tab P11"; + compatible = "lenovo,j606f", "qcom,sm6115p", "qcom,sm6115"; + chassis-type = "tablet"; + + /* required for bootloader to select correct board */ + qcom,msm-id = <445 0x10000>, <420 0x10000>; + qcom,board-id = <34 3>; + + aliases { + mmc0 = &sdhc_2; + }; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + framebuffer0: framebuffer@5c000000 { + compatible = "simple-framebuffer"; + reg = <0 0x5c000000 0 (2000 * 1200 * 4)>; + width = <1200>; + height = <2000>; + stride = <(1200 * 4)>; + format = "a8r8g8b8"; + clocks = <&gcc GCC_DISP_HF_AXI_CLK>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&vol_up_n>; + + key-volume-up { + label = "Volume Up"; + linux,code = <KEY_VOLUMEUP>; + gpios = <&pm6125_gpios 5 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + linux,can-disable; + gpio-key,wakeup; + }; + }; +}; + +&dispcc { + /* HACK: disable until a panel driver is ready to retain simplefb */ + status = "disabled"; +}; + +&pm6125_gpios { + vol_up_n: vol-up-n-state { + pins = "gpio5"; + function = "normal"; + power-source = <0>; + bias-pull-up; + input-enable; + }; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + linux,code = <KEY_VOLUMEDOWN>; + status = "okay"; +}; + +&rpm_requests { + regulators-0 { + compatible = "qcom,rpm-pm6125-regulators"; + + pm6125_s6: s6 { + regulator-min-microvolt = <304000>; + regulator-max-microvolt = <1456000>; + }; + + pm6125_s7: s7 { + regulator-min-microvolt = <1280000>; + regulator-max-microvolt = <2080000>; + }; + + pm6125_s8: s8 { + regulator-min-microvolt = <1064000>; + regulator-max-microvolt = <1304000>; + }; + + pm6125_l1: l1 { + regulator-min-microvolt = <952000>; + regulator-max-microvolt = <1152000>; + }; + + pm6125_l4: l4 { + regulator-min-microvolt = <488000>; + regulator-max-microvolt = <1000000>; + }; + + pm6125_l5: l5 { + regulator-min-microvolt = <1648000>; + /* 3.056V capped to 2.96V for SDHCI */ + regulator-max-microvolt = <2960000>; + regulator-allow-set-load; + /* Broken hw, this one can't be turned off or SDHCI will break! */ + regulator-always-on; + }; + + pm6125_l6: l6 { + regulator-min-microvolt = <576000>; + regulator-max-microvolt = <656000>; + }; + + pm6125_l7: l7 { + /* 1.2V-1.304V fixed at 1.256V for SDHCI bias */ + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1256000>; + /* + * TODO: SDHCI seems to also work with this one turned off, however + * there exists a possibility that it may not work with some very + * specific SDCard types, perhaps validating this against a wide + * range of models could rule that out, saving some power would + * certainly be nice.. + */ + regulator-always-on; + }; + + pm6125_l8: l8 { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <728000>; + }; + + pm6125_l9: l9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + }; + + pm6125_l10: l10 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1904000>; + }; + + pm6125_l11: l11 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1952000>; + }; + + pm6125_l12: l12 { + regulator-min-microvolt = <1624000>; + regulator-max-microvolt = <1984000>; + }; + + pm6125_l13: l13 { + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <1952000>; + }; + + pm6125_l14: l14 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1904000>; + }; + + pm6125_l15: l15 { + regulator-min-microvolt = <2920000>; + regulator-max-microvolt = <3232000>; + }; + + pm6125_l16: l16 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1904000>; + }; + + pm6125_l17: l17 { + regulator-min-microvolt = <1152000>; + regulator-max-microvolt = <1384000>; + }; + + pm6125_l18: l18 { + regulator-min-microvolt = <1104000>; + regulator-max-microvolt = <1312000>; + }; + + pm6125_l19: l19 { + regulator-min-microvolt = <1624000>; + regulator-max-microvolt = <3304000>; + }; + + pm6125_l20: l20 { + regulator-min-microvolt = <1624000>; + regulator-max-microvolt = <3304000>; + }; + + pm6125_l21: l21 { + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3600000>; + }; + + pm6125_l22: l22 { + regulator-min-microvolt = <2952000>; + /* 3.304V capped to 2.96V for SDHCI */ + regulator-max-microvolt = <2960000>; + regulator-allow-set-load; + /* Broken hw, this one can't be turned off or SDHCI will break! */ + regulator-always-on; + }; + + pm6125_l23: l23 { + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3400000>; + }; + + pm6125_l24: l24 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <3600000>; + }; + }; +}; + +&sdhc_2 { + cd-gpios = <&tlmm 88 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_state_on &sdc2_gate_pin>; + pinctrl-1 = <&sdc2_state_off>; + vmmc-supply = <&pm6125_l22>; + vqmmc-supply = <&pm6125_l5>; + no-sdio; + no-mmc; + status = "okay"; +}; + +&sleep_clk { + clock-frequency = <32764>; +}; + +&tlmm { + gpio-reserved-ranges = <14 4>; + + /* + * This is a wholly undocumented pin (other than a single vague "pwr-gpios" reference) + * that needs to be toggled for the SD Card slot to work properly.. + */ + sdc2_gate_pin: sdc2-gate-state { + pins = "gpio45"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + output-high; + }; +}; + +&ufs_mem_hc { + vcc-supply = <&pm6125_l24>; + vcc-max-microamp = <600000>; + vccq2-supply = <&pm6125_l11>; + vccq2-max-microamp = <600000>; + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&pm6125_l4>; + vdda-pll-supply = <&pm6125_l12>; + vddp-ref-clk-supply = <&pm6125_l18>; + status = "okay"; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_hsphy { + vdd-supply = <&pm6125_l4>; + vdda-pll-supply = <&pm6125_l12>; + vdda-phy-dpdm-supply = <&pm6125_l15>; + status = "okay"; +}; + +&xo_board { + clock-frequency = <19200000>; +}; diff --git a/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts b/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts index 0de6c5b7f742..b22b3f9a910d 100644 --- a/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts +++ b/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts @@ -20,6 +20,11 @@ compatible = "sony,pdx201", "qcom,sm6125"; chassis-type = "handset"; + aliases { + mmc0 = &sdhc_1; /* SDC1 eMMC slot */ + mmc1 = &sdhc_2; /* SDC2 SD card slot */ + }; + chosen { #address-cells = <2>; #size-cells = <2>; @@ -41,21 +46,22 @@ }; gpio-keys { - status = "okay"; compatible = "gpio-keys"; - autorepeat; - key-vol-dn { + pinctrl-0 = <&vol_down_n>; + pinctrl-names = "default"; + + key-volume-down { label = "Volume Down"; gpios = <&tlmm 47 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; linux,code = <KEY_VOLUMEDOWN>; - gpio-key,wakeup; debounce-interval = <15>; + linux,can-disable; + wakeup-source; }; }; - reserved_memory { + reserved-memory { #address-cells = <2>; #size-cells = <2>; debug_mem: memory@ffb00000 { @@ -141,10 +147,38 @@ }; }; +&gpi_dma0 { + status = "okay"; +}; + &hsusb_phy1 { + vdd-supply = <&pm6125_l7>; + vdda-pll-supply = <&pm6125_l10>; + vdda-phy-dpdm-supply = <&pm6125_l15>; status = "okay"; }; +&i2c1 { + clock-frequency = <400000>; + status = "okay"; + + /* NXP PN553 NFC @ 28 */ +}; + +&i2c2 { + clock-frequency = <400000>; + status = "okay"; + + /* Samsung touchscreen @ 48 */ +}; + +&i2c3 { + clock-frequency = <1000000>; + status = "okay"; + + /* Cirrus Logic CS35L41 boosted audio amplifier @ 40 */ +}; + &pm6125_adc { pinctrl-names = "default"; pinctrl-0 = <&camera_flash_therm &emmc_ufs_therm &rf_pa1_therm>; @@ -217,7 +251,7 @@ }; }; -&pm6125_gpio { +&pm6125_gpios { camera_flash_therm: camera-flash-therm-state { pins = "gpio3"; function = PMIC_GPIO_FUNC_NORMAL; @@ -246,6 +280,153 @@ linux,code = <KEY_VOLUMEUP>; }; +&rpm_requests { + regulators-0 { + compatible = "qcom,rpm-pm6125-regulators"; + + vdd_l2_l3_l4-supply = <&pm6125_l7>; + vdd_l5_l15_l19_l20_l21_l22-supply = <&pm6125_l10>; + + /* + * S3/S4 is VDD_CX + * S5 is VDD_MX/WCSS_MX + */ + + pm6125_s6: s6 { + regulator-min-microvolt = <936000>; + regulator-max-microvolt = <1422000>; + }; + + pm6125_l1: l1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1256000>; + }; + + pm6125_l2: l2 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1056000>; + }; + + pm6125_l3: l3 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1064000>; + }; + + pm6125_l4: l4 { + regulator-min-microvolt = <872000>; + regulator-max-microvolt = <976000>; + }; + + pm6125_l5: l5 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <2950000>; + regulator-allow-set-load; + }; + + pm6125_l6: l6 { + regulator-min-microvolt = <576000>; + regulator-max-microvolt = <656000>; + }; + + pm6125_l7: l7 { + regulator-min-microvolt = <872000>; + regulator-max-microvolt = <976000>; + }; + + pm6125_l8: l8 { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <728000>; + }; + + pm6125_l9: l9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1896000>; + }; + + pm6125_l10: l10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1896000>; + }; + + pm6125_l11: l11 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-allow-set-load; + }; + + pm6125_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1996000>; + }; + + pm6125_l13: l13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1832000>; + }; + + pm6125_l14: l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1904000>; + }; + + pm6125_l15: l15 { + regulator-min-microvolt = <3104000>; + regulator-max-microvolt = <3232000>; + }; + + pm6125_l16: l16 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1904000>; + }; + + pm6125_l17: l17 { + regulator-min-microvolt = <1248000>; + regulator-max-microvolt = <1304000>; + }; + + pm6125_l18: l18 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1264000>; + }; + + pm6125_l19: l19 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <2952000>; + }; + + pm6125_l20: l20 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <2952000>; + }; + + pm6125_l21: l21 { + regulator-min-microvolt = <2600000>; + regulator-max-microvolt = <2856000>; + }; + + pm6125_l22: l22 { + regulator-min-microvolt = <2944000>; + regulator-max-microvolt = <2950000>; + regulator-allow-set-load; + }; + + pm6125_l23: l23 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3400000>; + }; + + pm6125_l24: l24 { + regulator-min-microvolt = <2944000>; + regulator-max-microvolt = <2950000>; + regulator-allow-set-load; + }; + }; +}; + +&qupv3_id_0 { + status = "okay"; +}; + &sdc2_off_state { sd-cd-pins { pins = "gpio98"; @@ -265,11 +446,30 @@ }; &sdhc_1 { + vmmc-supply = <&pm6125_l24>; + vqmmc-supply = <&pm6125_l11>; + status = "okay"; +}; + +&sdhc_2 { + cd-gpios = <&tlmm 98 GPIO_ACTIVE_HIGH>; + vmmc-supply = <&pm6125_l22>; + vqmmc-supply = <&pm6125_l5>; + no-sdio; + no-mmc; status = "okay"; }; &tlmm { gpio-reserved-ranges = <22 2>, <28 6>; + + vol_down_n: vol-down-n-state { + pins = "gpio47"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + input-enable; + }; }; &usb3 { diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi index 7e25a4f85594..65033227718a 100644 --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi @@ -5,6 +5,7 @@ #include <dt-bindings/clock/qcom,gcc-sm6125.h> #include <dt-bindings/clock/qcom,rpmcc.h> +#include <dt-bindings/dma/qcom-gpi.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/power/qcom-rpmpd.h> @@ -45,6 +46,7 @@ next-level-cache = <&L2_0>; L2_0: l2-cache { compatible = "cache"; + cache-level = <2>; }; }; @@ -84,6 +86,7 @@ next-level-cache = <&L2_1>; L2_1: l2-cache { compatible = "cache"; + cache-level = <2>; }; }; @@ -425,6 +428,230 @@ bias-pull-up; }; }; + + qup_i2c0_default: qup-i2c0-default-state { + pins = "gpio0", "gpio1"; + function = "qup00"; + drive-strength = <2>; + bias-disable; + }; + + qup_i2c0_sleep: qup-i2c0-sleep-state { + pins = "gpio0", "gpio1"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c1_default: qup-i2c1-default-state { + pins = "gpio4", "gpio5"; + function = "qup01"; + drive-strength = <2>; + bias-disable; + }; + + qup_i2c1_sleep: qup-i2c1-sleep-state { + pins = "gpio4", "gpio5"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c2_default: qup-i2c2-default-state { + pins = "gpio6", "gpio7"; + function = "qup02"; + drive-strength = <2>; + bias-disable; + }; + + qup_i2c2_sleep: qup-i2c2-sleep-state { + pins = "gpio6", "gpio7"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c3_default: qup-i2c3-default-state { + pins = "gpio14", "gpio15"; + function = "qup03"; + drive-strength = <2>; + bias-disable; + }; + + qup_i2c3_sleep: qup-i2c3-sleep-state { + pins = "gpio14", "gpio15"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c4_default: qup-i2c4-default-state { + pins = "gpio16", "gpio17"; + function = "qup04"; + drive-strength = <2>; + bias-disable; + }; + + qup_i2c4_sleep: qup-i2c4-sleep-state { + pins = "gpio16", "gpio17"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c5_default: qup-i2c5-default-state { + pins = "gpio22", "gpio23"; + function = "qup10"; + drive-strength = <2>; + bias-disable; + }; + + qup_i2c5_sleep: qup-i2c5-sleep-state { + pins = "gpio22", "gpio23"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c6_default: qup-i2c6-default-state { + pins = "gpio30", "gpio31"; + function = "qup11"; + drive-strength = <2>; + bias-disable; + }; + + qup_i2c6_sleep: qup-i2c6-sleep-state { + pins = "gpio30", "gpio31"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c7_default: qup-i2c7-default-state { + pins = "gpio28", "gpio29"; + function = "qup12"; + drive-strength = <2>; + bias-disable; + }; + + qup_i2c7_sleep: qup-i2c7-sleep-state { + pins = "gpio28", "gpio29"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c8_default: qup-i2c8-default-state { + pins = "gpio18", "gpio19"; + function = "qup13"; + drive-strength = <2>; + bias-disable; + }; + + qup_i2c8_sleep: qup-i2c8-sleep-state { + pins = "gpio18", "gpio19"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c9_default: qup-i2c9-default-state { + pins = "gpio10", "gpio11"; + function = "qup14"; + drive-strength = <2>; + bias-disable; + }; + + qup_i2c9_sleep: qup-i2c9-sleep-state { + pins = "gpio10", "gpio11"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi0_default: qup-spi0-default-state { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "qup00"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi0_sleep: qup-spi0-sleep-state { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "gpio"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi2_default: qup-spi2-default-state { + pins = "gpio6", "gpio7", "gpio8", "gpio9"; + function = "qup02"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi2_sleep: qup-spi2-sleep-state { + pins = "gpio6", "gpio7", "gpio8", "gpio9"; + function = "gpio"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi5_default: qup-spi5-default-state { + pins = "gpio22", "gpio23", "gpio24", "gpio25"; + function = "qup10"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi5_sleep: qup-spi5-sleep-state { + pins = "gpio22", "gpio23", "gpio24", "gpio25"; + function = "gpio"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi6_default: qup-spi6-default-state { + pins = "gpio30", "gpio31", "gpio32", "gpio33"; + function = "qup11"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi6_sleep: qup-spi6-sleep-state { + pins = "gpio30", "gpio31", "gpio32", "gpio33"; + function = "gpio"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi8_default: qup-spi8-default-state { + pins = "gpio18", "gpio19", "gpio20", "gpio21"; + function = "qup13"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi8_sleep: qup-spi8-sleep-state { + pins = "gpio18", "gpio19", "gpio20", "gpio21"; + function = "gpio"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi9_default: qup-spi9-default-state { + pins = "gpio10", "gpio11", "gpio12", "gpio13"; + function = "qup14"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi9_sleep: qup-spi9-sleep-state { + pins = "gpio10", "gpio11", "gpio12", "gpio13"; + function = "gpio"; + drive-strength = <6>; + bias-disable; + }; }; gcc: clock-controller@1400000 { @@ -442,9 +669,9 @@ reg = <0x01613000 0x180>; #phy-cells = <0>; - clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, - <&gcc GCC_AHB2PHY_USB_CLK>; - clock-names = "ref", "cfg_ahb"; + clocks = <&gcc GCC_AHB2PHY_USB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "cfg_ahb", "ref"; resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; status = "disabled"; @@ -468,6 +695,7 @@ <&gcc GCC_SDCC1_APPS_CLK>, <&xo_board>; clock-names = "iface", "core", "xo"; + iommus = <&apps_smmu 0x160 0x0>; power-domains = <&rpmpd SM6125_VDDCX>; @@ -494,6 +722,7 @@ <&gcc GCC_SDCC2_APPS_CLK>, <&xo_board>; clock-names = "iface", "core", "xo"; + iommus = <&apps_smmu 0x180 0x0>; pinctrl-0 = <&sdc2_on_state>; pinctrl-1 = <&sdc2_off_state>; @@ -508,6 +737,340 @@ status = "disabled"; }; + gpi_dma0: dma-controller@4a00000 { + compatible = "qcom,sm6125-gpi-dma", "qcom,sdm845-gpi-dma"; + reg = <0x04a00000 0x60000>; + interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>; + dma-channels = <8>; + dma-channel-mask = <0x1f>; + iommus = <&apps_smmu 0x136 0x0>; + #dma-cells = <3>; + status = "disabled"; + }; + + qupv3_id_0: geniqup@4ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x04ac0000 0x2000>; + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + clock-names = "m-ahb", "s-ahb"; + iommus = <&apps_smmu 0x123 0x0>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + i2c0: i2c@4a80000 { + compatible = "qcom,geni-i2c"; + reg = <0x04a80000 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&qup_i2c0_default>; + pinctrl-1 = <&qup_i2c0_sleep>; + pinctrl-names = "default", "sleep"; + dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, + <&gpi_dma0 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi0: spi@4a80000 { + compatible = "qcom,geni-spi"; + reg = <0x04a80000 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&qup_spi0_default>; + pinctrl-1 = <&qup_spi0_sleep>; + pinctrl-names = "default", "sleep"; + dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, + <&gpi_dma0 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@4a84000 { + compatible = "qcom,geni-i2c"; + reg = <0x04a84000 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&qup_i2c1_default>; + pinctrl-1 = <&qup_i2c1_sleep>; + pinctrl-names = "default", "sleep"; + dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, + <&gpi_dma0 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@4a88000 { + compatible = "qcom,geni-i2c"; + reg = <0x04a88000 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&qup_i2c2_default>; + pinctrl-1 = <&qup_i2c2_sleep>; + pinctrl-names = "default", "sleep"; + dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, + <&gpi_dma0 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@4a88000 { + compatible = "qcom,geni-spi"; + reg = <0x04a88000 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&qup_spi2_default>; + pinctrl-1 = <&qup_spi2_sleep>; + pinctrl-names = "default", "sleep"; + dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, + <&gpi_dma0 1 2 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@4a8c000 { + compatible = "qcom,geni-i2c"; + reg = <0x04a8c000 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&qup_i2c3_default>; + pinctrl-1 = <&qup_i2c3_sleep>; + pinctrl-names = "default", "sleep"; + dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, + <&gpi_dma0 1 3 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@4a90000 { + compatible = "qcom,geni-i2c"; + reg = <0x04a90000 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&qup_i2c4_default>; + pinctrl-1 = <&qup_i2c4_sleep>; + pinctrl-names = "default", "sleep"; + dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, + <&gpi_dma0 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + gpi_dma1: dma-controller@4c00000 { + compatible = "qcom,sm6125-gpi-dma", "qcom,sdm845-gpi-dma"; + reg = <0x04c00000 0x60000>; + interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; + dma-channels = <8>; + dma-channel-mask = <0x0f>; + iommus = <&apps_smmu 0x156 0x0>; + #dma-cells = <3>; + status = "disabled"; + }; + + qupv3_id_1: geniqup@4cc0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x04cc0000 0x2000>; + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + clock-names = "m-ahb", "s-ahb"; + iommus = <&apps_smmu 0x143 0x0>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + i2c5: i2c@4c80000 { + compatible = "qcom,geni-i2c"; + reg = <0x04c80000 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&qup_i2c5_default>; + pinctrl-1 = <&qup_i2c5_sleep>; + pinctrl-names = "default", "sleep"; + dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, + <&gpi_dma1 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi5: spi@4c80000 { + compatible = "qcom,geni-spi"; + reg = <0x04c80000 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&qup_spi5_default>; + pinctrl-1 = <&qup_spi5_sleep>; + pinctrl-names = "default", "sleep"; + dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, + <&gpi_dma1 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c6: i2c@4c84000 { + compatible = "qcom,geni-i2c"; + reg = <0x04c84000 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&qup_i2c6_default>; + pinctrl-1 = <&qup_i2c6_sleep>; + pinctrl-names = "default", "sleep"; + dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, + <&gpi_dma1 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi6: spi@4c84000 { + compatible = "qcom,geni-spi"; + reg = <0x04c84000 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&qup_spi6_default>; + pinctrl-1 = <&qup_spi6_sleep>; + pinctrl-names = "default", "sleep"; + dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, + <&gpi_dma1 1 1 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c7: i2c@4c88000 { + compatible = "qcom,geni-i2c"; + reg = <0x04c88000 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&qup_i2c7_default>; + pinctrl-1 = <&qup_i2c7_sleep>; + pinctrl-names = "default", "sleep"; + dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, + <&gpi_dma1 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c8: i2c@4c8c000 { + compatible = "qcom,geni-i2c"; + reg = <0x04c8c000 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&qup_i2c8_default>; + pinctrl-1 = <&qup_i2c8_sleep>; + pinctrl-names = "default", "sleep"; + dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, + <&gpi_dma1 1 3 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi8: spi@4c8c000 { + compatible = "qcom,geni-spi"; + reg = <0x04c8c000 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&qup_spi8_default>; + pinctrl-1 = <&qup_spi8_sleep>; + pinctrl-names = "default", "sleep"; + dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, + <&gpi_dma1 1 3 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c9: i2c@4c90000 { + compatible = "qcom,geni-i2c"; + reg = <0x04c90000 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&qup_i2c9_default>; + pinctrl-1 = <&qup_i2c9_sleep>; + pinctrl-names = "default", "sleep"; + dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, + <&gpi_dma1 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi9: spi@4c90000 { + compatible = "qcom,geni-spi"; + reg = <0x04c90000 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names = "se"; + interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&qup_spi9_default>; + pinctrl-1 = <&qup_spi9_sleep>; + pinctrl-names = "default", "sleep"; + dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, + <&gpi_dma1 1 4 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + usb3: usb@4ef8800 { compatible = "qcom,sm6125-dwc3", "qcom,dwc3"; reg = <0x04ef8800 0x400>; @@ -540,6 +1103,7 @@ compatible = "snps,dwc3"; reg = <0x04e00000 0xcd00>; interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; + iommus = <&apps_smmu 0x100 0x0>; phys = <&hsusb_phy1>; phy-names = "usb2-phy"; snps,dis_u2_susphy_quirk; @@ -573,6 +1137,79 @@ cell-index = <0>; }; + apps_smmu: iommu@c600000 { + compatible = "qcom,sm6125-smmu-500", "qcom,smmu-500", "arm,mmu-500"; + reg = <0xc600000 0x80000>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; + + #global-interrupts = <1>; + #iommu-cells = <2>; + }; + apcs_glb: mailbox@f111000 { compatible = "qcom,sm6125-apcs-hmss-global"; reg = <0x0f111000 0x1000>; diff --git a/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts b/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts index 94f77d376662..4916d0db5b47 100644 --- a/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts +++ b/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts @@ -35,10 +35,10 @@ gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; - pinctrl-0 = <&gpio_keys_state>; + pinctrl-0 = <&vol_down_n>; key-volume-down { - label = "volume_down"; + label = "Volume Down"; linux,code = <KEY_VOLUMEDOWN>; gpios = <&pm6350_gpios 2 GPIO_ACTIVE_LOW>; }; @@ -305,14 +305,12 @@ }; &pm6350_gpios { - gpio_keys_state: gpio-keys-state { - key-volume-down-pins { - pins = "gpio2"; - function = PMIC_GPIO_FUNC_NORMAL; - power-source = <0>; - bias-disable; - input-enable; - }; + vol_down_n: vol-down-n-state { + pins = "gpio2"; + function = PMIC_GPIO_FUNC_NORMAL; + power-source = <0>; + bias-disable; + input-enable; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 43324bf291c3..1e1d366c92c1 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -6,11 +6,15 @@ #include <dt-bindings/clock/qcom,gcc-sm6350.h> #include <dt-bindings/clock/qcom,rpmh.h> +#include <dt-bindings/clock/qcom,sm6350-camcc.h> #include <dt-bindings/dma/qcom-gpi.h> #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interconnect/qcom,icc.h> +#include <dt-bindings/interconnect/qcom,osm-l3.h> #include <dt-bindings/interconnect/qcom,sm6350.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/mailbox/qcom-ipcc.h> +#include <dt-bindings/phy/phy-qcom-qmp.h> #include <dt-bindings/power/qcom-rpmpd.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> @@ -47,12 +51,18 @@ dynamic-power-coefficient = <100>; next-level-cache = <&L2_0>; qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY + &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; #cooling-cells = <2>; L2_0: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; L3_0: l3-cache { compatible = "cache"; + cache-level = <3>; }; }; }; @@ -66,9 +76,14 @@ dynamic-power-coefficient = <100>; next-level-cache = <&L2_100>; qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY + &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; #cooling-cells = <2>; L2_100: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -82,9 +97,14 @@ dynamic-power-coefficient = <100>; next-level-cache = <&L2_200>; qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY + &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; #cooling-cells = <2>; L2_200: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -98,9 +118,14 @@ dynamic-power-coefficient = <100>; next-level-cache = <&L2_300>; qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY + &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; #cooling-cells = <2>; L2_300: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -114,9 +139,14 @@ dynamic-power-coefficient = <100>; next-level-cache = <&L2_400>; qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY + &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; #cooling-cells = <2>; L2_400: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -130,9 +160,14 @@ dynamic-power-coefficient = <100>; next-level-cache = <&L2_500>; qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY + &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; #cooling-cells = <2>; L2_500: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; @@ -147,9 +182,14 @@ dynamic-power-coefficient = <703>; next-level-cache = <&L2_600>; qcom,freq-domain = <&cpufreq_hw 1>; + operating-points-v2 = <&cpu6_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY + &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; #cooling-cells = <2>; L2_600: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -163,9 +203,14 @@ dynamic-power-coefficient = <703>; next-level-cache = <&L2_700>; qcom,freq-domain = <&cpufreq_hw 1>; + operating-points-v2 = <&cpu6_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY + &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; #cooling-cells = <2>; L2_700: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -220,6 +265,112 @@ reg = <0x0 0x80000000 0x0 0x0>; }; + cpu0_opp_table: opp-table-cpu0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + /* DDR: 4-wide, 2 channels, double data rate, L3: 16-wide, 2 channels */ + opp-peak-kBps = <(200000 * 4 * 2 * 2) (300000 * 16 * 2)>; + }; + + opp-576000000 { + opp-hz = /bits/ 64 <576000000>; + opp-peak-kBps = <(547000 * 4 * 2 * 2) (556800 * 16 * 2)>; + }; + + opp-768000000 { + opp-hz = /bits/ 64 <768000000>; + opp-peak-kBps = <(768000 * 4 * 2 * 2) (652800 * 16 * 2)>; + }; + + opp-1017600000 { + opp-hz = /bits/ 64 <1017600000>; + opp-peak-kBps = <(1017000 * 4 * 2 * 2) (940800 * 16 * 2)>; + }; + + opp-1248000000 { + opp-hz = /bits/ 64 <1248000000>; + opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1209600 * 16 * 2)>; + }; + + opp-1324800000 { + opp-hz = /bits/ 64 <1324800000>; + opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1286400 * 16 * 2)>; + }; + + opp-1516800000 { + opp-hz = /bits/ 64 <1516800000>; + opp-peak-kBps = <(1353000 * 4 * 2 * 2) (1459200 * 16 * 2)>; + }; + + opp-1612800000 { + opp-hz = /bits/ 64 <1612800000>; + opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>; + }; + + opp-1708800000 { + opp-hz = /bits/ 64 <1708800000>; + opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>; + }; + }; + + cpu6_opp_table: opp-table-cpu6 { + compatible = "operating-points-v2"; + opp-shared; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-peak-kBps = <(200000 * 4 * 2 * 2) (300000 * 16 * 2)>; + }; + + opp-787200000 { + opp-hz = /bits/ 64 <787200000>; + opp-peak-kBps = <(768000 * 4 * 2 * 2) (652800 * 16 * 2)>; + }; + + opp-979200000 { + opp-hz = /bits/ 64 <979200000>; + opp-peak-kBps = <(768000 * 4 * 2 * 2) (940800 * 16 * 2)>; + }; + + opp-1036800000 { + opp-hz = /bits/ 64 <1036800000>; + opp-peak-kBps = <(1017000 * 4 * 2 * 2) (940800 * 16 * 2)>; + }; + + opp-1248000000 { + opp-hz = /bits/ 64 <1248000000>; + opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1209600 * 16 * 2)>; + }; + + opp-1401600000 { + opp-hz = /bits/ 64 <1401600000>; + opp-peak-kBps = <(1353000 * 4 * 2 * 2) (1401600 * 16 * 2)>; + }; + + opp-1555200000 { + opp-hz = /bits/ 64 <1555200000>; + opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>; + }; + + opp-1766400000 { + opp-hz = /bits/ 64 <1766400000>; + opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>; + }; + + opp-1900800000 { + opp-hz = /bits/ 64 <1900800000>; + opp-peak-kBps = <(1804000 * 4 * 2 * 2) (1459200 * 16 * 2)>; + }; + + opp-2073600000 { + opp-hz = /bits/ 64 <2073600000>; + opp-peak-kBps = <(2092000 * 4 * 2 * 2) (1459200 * 16 * 2)>; + }; + }; + pmu { compatible = "arm,armv8-pmuv3"; interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_LOW>; @@ -342,13 +493,12 @@ }; ramoops: ramoops@ffc00000 { - compatible = "removed-dma-pool", "ramoops"; - reg = <0 0xffc00000 0 0x00100000>; + compatible = "ramoops"; + reg = <0 0xffc00000 0 0x100000>; record-size = <0x1000>; console-size = <0x40000>; - ftrace-size = <0x0>; msg-size = <0x20000 0x20000>; - cc-size = <0x0>; + ecc-size = <16>; no-map; }; @@ -432,7 +582,17 @@ modem_smp2p_in: slave-kernel { qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + ipa_smp2p_out: ipa-ap-to-modem { + qcom,entry-name = "ipa"; + #qcom,smem-state-cells = <1>; + }; + ipa_smp2p_in: ipa-modem-to-ap { + qcom,entry-name = "ipa"; interrupt-controller; #interrupt-cells = <2>; }; @@ -544,7 +704,7 @@ qupv3_id_0: geniqup@8c0000 { compatible = "qcom,geni-se-qup"; - reg = <0x0 0x8c0000 0x0 0x2000>; + reg = <0x0 0x008c0000 0x0 0x2000>; clock-names = "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; @@ -617,7 +777,7 @@ qupv3_id_1: geniqup@9c0000 { compatible = "qcom,geni-se-qup"; - reg = <0x0 0x9c0000 0x0 0x2000>; + reg = <0x0 0x009c0000 0x0 0x2000>; clock-names = "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; @@ -689,7 +849,7 @@ uart9: serial@98c000 { compatible = "qcom,geni-debug-uart"; - reg = <0 0x98c000 0 0x4000>; + reg = <0 0x0098c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; pinctrl-names = "default"; @@ -847,6 +1007,43 @@ }; }; + ipa: ipa@1e40000 { + compatible = "qcom,sm6350-ipa"; + + iommus = <&apps_smmu 0x440 0x0>, + <&apps_smmu 0x442 0x0>; + reg = <0 0x01e40000 0 0x8000>, + <0 0x01e50000 0 0x3000>, + <0 0x01e04000 0 0x23000>; + reg-names = "ipa-reg", + "ipa-shared", + "gsi"; + + interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, + <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ipa", + "gsi", + "ipa-clock-query", + "ipa-setup-ready"; + + clocks = <&rpmhcc RPMH_IPA_CLK>; + clock-names = "core"; + + interconnects = <&aggre2_noc MASTER_IPA 0 &clk_virt SLAVE_EBI_CH0 0>, + <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_OCIMEM 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_IPA_CFG 0>; + interconnect-names = "memory", "imem", "config"; + + qcom,smem-states = <&ipa_smp2p_out 0>, + <&ipa_smp2p_out 1>; + qcom,smem-state-names = "ipa-clock-enabled-valid", + "ipa-clock-enabled"; + + status = "disabled"; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x40000>; @@ -1119,49 +1316,26 @@ resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; }; - usb_1_qmpphy: phy@88e9000 { - compatible = "qcom,sc7180-qmp-usb3-dp-phy"; - reg = <0 0x088e9000 0 0x200>, - <0 0x088e8000 0 0x40>, - <0 0x088ea000 0 0x200>; - status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; - ranges; + usb_1_qmpphy: phy@88e8000 { + compatible = "qcom,sm6350-qmp-usb3-dp-phy"; + reg = <0 0x088e8000 0 0x3000>; clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, - <&xo_board>, - <&rpmhcc RPMH_QLINK_CLK>, - <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; - clock-names = "aux", "cfg_ahb", "ref", "com_aux"; + <&gcc GCC_USB3_PRIM_CLKREF_CLK>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "aux", "ref", "com_aux", "usb3_pipe"; + + power-domains = <&gcc USB30_PRIM_GDSC>; - resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, - <&gcc GCC_USB3_PHY_PRIM_BCR>; + resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, + <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; reset-names = "phy", "common"; - usb_1_ssphy: usb3-phy@88e9200 { - reg = <0 0x088e9200 0 0x200>, - <0 0x088e9400 0 0x200>, - <0 0x088e9c00 0 0x400>, - <0 0x088e9600 0 0x200>, - <0 0x088e9800 0 0x200>, - <0 0x088e9a00 0 0x100>; - #clock-cells = <0>; - #phy-cells = <0>; - clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "usb3_phy_pipe_clk_src"; - }; + #clock-cells = <1>; + #phy-cells = <1>; - dp_phy: dp-phy@88ea200 { - reg = <0 0x088ea200 0 0x200>, - <0 0x088ea400 0 0x200>, - <0 0x088eaa00 0 0x200>, - <0 0x088ea600 0 0x200>, - <0 0x088ea800 0 0x200>; - #phy-cells = <0>; - #clock-cells = <1>; - }; + status = "disabled"; }; dc_noc: interconnect@9160000 { @@ -1235,11 +1409,109 @@ snps,dis_enblslpm_quirk; snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x10>; - phys = <&usb_1_hsphy>, <&usb_1_ssphy>; + phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; phy-names = "usb2-phy", "usb3-phy"; }; }; + cci0: cci@ac4a000 { + compatible = "qcom,sm6350-cci", "qcom,msm8996-cci"; + reg = <0 0x0ac4a000 0 0x1000>; + interrupts = <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>; + power-domains = <&camcc TITAN_TOP_GDSC>; + + clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, + <&camcc CAMCC_SOC_AHB_CLK>, + <&camcc CAMCC_SLOW_AHB_CLK_SRC>, + <&camcc CAMCC_CPAS_AHB_CLK>, + <&camcc CAMCC_CCI_0_CLK>, + <&camcc CAMCC_CCI_0_CLK_SRC>; + clock-names = "camnoc_axi", + "soc_ahb", + "slow_ahb_src", + "cpas_ahb", + "cci", + "cci_src"; + + assigned-clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, + <&camcc CAMCC_CCI_0_CLK>; + assigned-clock-rates = <80000000>, <37500000>; + + pinctrl-0 = <&cci0_default &cci1_default>; + pinctrl-1 = <&cci0_sleep &cci1_sleep>; + pinctrl-names = "default", "sleep"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + cci0_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci0_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + cci1: cci@ac4b000 { + compatible = "qcom,sm6350-cci", "qcom,msm8996-cci"; + reg = <0 0x0ac4b000 0 0x1000>; + interrupts = <GIC_SPI 462 IRQ_TYPE_EDGE_RISING>; + power-domains = <&camcc TITAN_TOP_GDSC>; + + clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, + <&camcc CAMCC_SOC_AHB_CLK>, + <&camcc CAMCC_SLOW_AHB_CLK_SRC>, + <&camcc CAMCC_CPAS_AHB_CLK>, + <&camcc CAMCC_CCI_1_CLK>, + <&camcc CAMCC_CCI_1_CLK_SRC>; + clock-names = "camnoc_axi", + "soc_ahb", + "slow_ahb_src", + "cpas_ahb", + "cci", + "cci_src"; + + assigned-clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, + <&camcc CAMCC_CCI_1_CLK>; + assigned-clock-rates = <80000000>, <37500000>; + + pinctrl-0 = <&cci2_default>; + pinctrl-1 = <&cci2_sleep>; + pinctrl-names = "default", "sleep"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + cci1_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + /* SM6350 seems to have cci1_i2c1 on gpio2 & gpio3 but unused downstream */ + }; + + camcc: clock-controller@ad00000 { + compatible = "qcom,sm6350-camcc"; + reg = <0 0x0ad00000 0 0x16000>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sm6350-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x64>; @@ -1272,7 +1544,7 @@ #thermal-sensor-cells = <1>; }; - aoss_qmp: power-controller@c300000 { + aoss_qmp: power-management@c300000 { compatible = "qcom,sm6350-aoss-qmp", "qcom,aoss-qmp"; reg = <0 0x0c300000 0 0x1000>; interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP @@ -1284,11 +1556,11 @@ spmi_bus: spmi@c440000 { compatible = "qcom,spmi-pmic-arb"; - reg = <0 0xc440000 0 0x1100>, - <0 0xc600000 0 0x2000000>, - <0 0xe600000 0 0x100000>, - <0 0xe700000 0 0xa0000>, - <0 0xc40a000 0 0x26000>; + reg = <0 0x0c440000 0 0x1100>, + <0 0x0c600000 0 0x2000000>, + <0 0x0e600000 0 0x100000>, + <0 0x0e700000 0 0xa0000>, + <0 0x0c40a000 0 0x26000>; reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; interrupt-names = "periph_irq"; interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; @@ -1318,6 +1590,48 @@ #interrupt-cells = <2>; gpio-ranges = <&tlmm 0 0 157>; + cci0_default: cci0-default-state { + pins = "gpio39", "gpio40"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; + }; + + cci0_sleep: cci0-sleep-state { + pins = "gpio39", "gpio40"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + + cci1_default: cci1-default-state { + pins = "gpio41", "gpio42"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; + }; + + cci1_sleep: cci1-sleep-state { + pins = "gpio41", "gpio42"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + + cci2_default: cci2-default-state { + pins = "gpio43", "gpio44"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-up; + }; + + cci2_sleep: cci2-sleep-state { + pins = "gpio43", "gpio44"; + function = "cci_i2c"; + drive-strength = <2>; + bias-pull-down; + }; + sdc2_off_state: sdc2-off-state { clk-pins { pins = "sdc2_clk"; @@ -1670,6 +1984,16 @@ }; }; + osm_l3: interconnect@18321000 { + compatible = "qcom,sm6350-osm-l3", "qcom,osm-l3"; + reg = <0x0 0x18321000 0x0 0x1000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + + #interconnect-cells = <1>; + }; + cpufreq_hw: cpufreq@18323000 { compatible = "qcom,cpufreq-hw"; reg = <0 0x18323000 0 0x1000>, <0 0x18325800 0 0x1000>; diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi index 12cf5dbe5bd6..31b88c738510 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -264,55 +264,55 @@ compatible = "arm,psci-1.0"; method = "smc"; - CPU_PD0: cpu0 { + CPU_PD0: power-domain-cpu0 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&LITTLE_CPU_SLEEP_0>; }; - CPU_PD1: cpu1 { + CPU_PD1: power-domain-cpu1 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&LITTLE_CPU_SLEEP_0>; }; - CPU_PD2: cpu2 { + CPU_PD2: power-domain-cpu2 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&LITTLE_CPU_SLEEP_0>; }; - CPU_PD3: cpu3 { + CPU_PD3: power-domain-cpu3 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&LITTLE_CPU_SLEEP_0>; }; - CPU_PD4: cpu4 { + CPU_PD4: power-domain-cpu4 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&LITTLE_CPU_SLEEP_0>; }; - CPU_PD5: cpu5 { + CPU_PD5: power-domain-cpu5 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&LITTLE_CPU_SLEEP_0>; }; - CPU_PD6: cpu6 { + CPU_PD6: power-domain-cpu6 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&BIG_CPU_SLEEP_0>; }; - CPU_PD7: cpu7 { + CPU_PD7: power-domain-cpu7 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&BIG_CPU_SLEEP_0>; }; - CLUSTER_PD: cpu-cluster0 { + CLUSTER_PD: power-domain-cpu-cluster0 { #power-domain-cells = <0>; domain-idle-states = <&CLUSTER_SLEEP_0>; }; diff --git a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts index c456e9594ea5..7ae6aba5d2ec 100644 --- a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts +++ b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts @@ -5,14 +5,20 @@ /dts-v1/; +/* PMK8350 (in reality a PMK8003) is configured to use SID6 instead of 0 */ +#define PMK8350_SID 6 + #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h> #include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> #include <dt-bindings/regulator/qcom,rpmh-regulator.h> #include "sm7225.dtsi" #include "pm6150l.dtsi" #include "pm6350.dtsi" #include "pm7250b.dtsi" +#include "pmk8350.dtsi" / { model = "Fairphone 4"; @@ -104,12 +110,12 @@ }; &adsp { - status = "okay"; firmware-name = "qcom/sm7225/fairphone4/adsp.mdt"; + status = "okay"; }; &apps_rsc { - pm6350-rpmh-regulators { + regulators-0 { compatible = "qcom,pm6350-rpmh-regulators"; qcom,pmic-id = "a"; @@ -238,7 +244,7 @@ }; }; - pm6150l-rpmh-regulators { + regulators-1 { compatible = "qcom,pm6150l-rpmh-regulators"; qcom,pmic-id = "e"; @@ -328,14 +334,63 @@ }; }; -&cdsp { +&cci0 { + status = "okay"; +}; + +&cci0_i2c0 { + /* IMX582 @ 0x1a */ +}; + +&cci0_i2c1 { + /* IMX582 @ 0x1a */ +}; + +&cci1 { status = "okay"; +}; + +&cci1_i2c0 { + /* IMX576 @ 0x10 */ +}; + +&cdsp { firmware-name = "qcom/sm7225/fairphone4/cdsp.mdt"; + status = "okay"; }; -&i2c10 { +&gpi_dma0 { + status = "okay"; +}; + +&gpi_dma1 { status = "okay"; +}; + +&i2c0 { clock-frequency = <400000>; + status = "okay"; + + /* ST21NFCD NFC @ 8 */ + /* VL53L3 ToF @ 29 */ + /* AW88264A amplifier @ 34 */ + /* AW88264A amplifier @ 35 */ +}; + +&i2c8 { + clock-frequency = <400000>; + status = "okay"; + + /* HX83112A touchscreen @ 48 */ +}; + +&i2c10 { + clock-frequency = <400000>; + status = "okay"; + + /* PM8008 PMIC @ 8 and 9 */ + /* PX8618 @ 26 */ + /* SMB1395 PMIC @ 34 */ haptics@5a { compatible = "awinic,aw8695"; @@ -362,17 +417,46 @@ }; }; -&mpss { +&ipa { + qcom,gsi-loader = "self"; + memory-region = <&pil_ipa_fw_mem>; + firmware-name = "qcom/sm7225/fairphone4/ipa_fws.mdt"; status = "okay"; +}; + +&mpss { firmware-name = "qcom/sm7225/fairphone4/modem.mdt"; + status = "okay"; }; -&pm6150l_wled { +&pm6150l_flash { status = "okay"; + led-0 { + function = LED_FUNCTION_FLASH; + color = <LED_COLOR_ID_YELLOW>; + led-sources = <1>; + led-max-microamp = <180000>; + flash-max-microamp = <1000000>; + flash-max-timeout-us = <1280000>; + }; + + led-1 { + function = LED_FUNCTION_FLASH; + color = <LED_COLOR_ID_WHITE>; + led-sources = <2>; + led-max-microamp = <180000>; + flash-max-microamp = <1000000>; + flash-max-timeout-us = <1280000>; + }; +}; + +&pm6150l_wled { qcom,switching-freq = <800>; qcom,current-limit-microamp = <20000>; qcom,num-strings = <2>; + + status = "okay"; }; &pm6350_gpios { @@ -386,8 +470,8 @@ }; &pm6350_resin { - status = "okay"; linux,code = <KEY_VOLUMEDOWN>; + status = "okay"; }; &pm7250b_adc { @@ -426,6 +510,24 @@ }; }; +&pmk8350_rtc { + status = "okay"; +}; + +&pmk8350_vadc { + adc-chan@644 { + reg = <PMK8350_ADC7_AMUX_THM1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "xo_therm"; + }; +}; + +&qupv3_id_0 { + status = "okay"; +}; + &qupv3_id_1 { status = "okay"; }; @@ -466,21 +568,21 @@ }; &ufs_mem_hc { - status = "okay"; - reset-gpios = <&tlmm 156 GPIO_ACTIVE_LOW>; vcc-supply = <&vreg_l7e>; vcc-max-microamp = <800000>; vccq2-supply = <&vreg_l12a>; vccq2-max-microamp = <800000>; -}; -&ufs_mem_phy { status = "okay"; +}; +&ufs_mem_phy { vdda-phy-supply = <&vreg_l18a>; vdda-pll-supply = <&vreg_l22a>; + + status = "okay"; }; &usb_1 { @@ -493,26 +595,26 @@ }; &usb_1_hsphy { - status = "okay"; - vdd-supply = <&vreg_l18a>; vdda-pll-supply = <&vreg_l2a>; vdda-phy-dpdm-supply = <&vreg_l3a>; -}; -&usb_1_qmpphy { status = "okay"; +}; +&usb_1_qmpphy { vdda-phy-supply = <&vreg_l22a>; vdda-pll-supply = <&vreg_l16a>; -}; -&wifi { status = "okay"; +}; +&wifi { vdd-0.8-cx-mx-supply = <&vreg_l4a>; vdd-1.8-xo-supply = <&vreg_l7a>; vdd-1.3-rfa-supply = <&vreg_l2e>; vdd-3.3-ch0-supply = <&vreg_l10e>; vdd-3.3-ch1-supply = <&vreg_l11e>; + + status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm7225.dtsi b/arch/arm64/boot/dts/qcom/sm7225.dtsi index 7b2a002ca7ff..b7b4044e9bb0 100644 --- a/arch/arm64/boot/dts/qcom/sm7225.dtsi +++ b/arch/arm64/boot/dts/qcom/sm7225.dtsi @@ -14,3 +14,22 @@ &CPU5 { compatible = "qcom,kryo570"; }; &CPU6 { compatible = "qcom,kryo570"; }; &CPU7 { compatible = "qcom,kryo570"; }; + +&cpu0_opp_table { + opp-1804800000 { + opp-hz = /bits/ 64 <1804800000>; + opp-peak-kBps = <(1804000 * 4 * 2 * 2) (1459200 * 16 * 2)>; + }; +}; + +&cpu6_opp_table { + opp-2131200000 { + opp-hz = /bits/ 64 <2131200000>; + opp-peak-kBps = <(2092000 * 4 * 2 * 2) (1459200 * 16 * 2)>; + }; + + opp-2208000000 { + opp-hz = /bits/ 64 <2208000000>; + opp-peak-kBps = <(2092000 * 4 * 2 * 2) (1459200 * 16 * 2)>; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts index 3331ee957d64..8f014a232526 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts @@ -56,7 +56,7 @@ }; &apps_rsc { - pm8150-rpmh-regulators { + regulators-0 { compatible = "qcom,pm8150-rpmh-regulators"; qcom,pmic-id = "a"; @@ -211,7 +211,7 @@ }; }; - pm8150l-rpmh-regulators { + regulators-1 { compatible = "qcom,pm8150l-rpmh-regulators"; qcom,pmic-id = "c"; @@ -324,7 +324,7 @@ }; }; - pm8009-rpmh-regulators { + regulators-2 { compatible = "qcom,pm8009-rpmh-regulators"; qcom,pmic-id = "f"; diff --git a/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts b/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts index 5397fba9417b..69024f7c7f10 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts +++ b/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts @@ -61,7 +61,7 @@ }; &apps_rsc { - pm8150-rpmh-regulators { + regulators-0 { compatible = "qcom,pm8150-rpmh-regulators"; qcom,pmic-id = "a"; @@ -216,7 +216,7 @@ }; }; - pm8150l-rpmh-regulators { + regulators-1 { compatible = "qcom,pm8150l-rpmh-regulators"; qcom,pmic-id = "c"; @@ -329,7 +329,7 @@ }; }; - pm8009-rpmh-regulators { + regulators-2 { compatible = "qcom,pm8009-rpmh-regulators"; qcom,pmic-id = "f"; diff --git a/arch/arm64/boot/dts/qcom/sm8150-mtp.dts b/arch/arm64/boot/dts/qcom/sm8150-mtp.dts index 46b5cf9a1192..eff995a07ab7 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8150-mtp.dts @@ -51,7 +51,7 @@ }; &apps_rsc { - pm8150-rpmh-regulators { + regulators-0 { compatible = "qcom,pm8150-rpmh-regulators"; qcom,pmic-id = "a"; @@ -206,7 +206,7 @@ }; }; - pm8150l-rpmh-regulators { + regulators-1 { compatible = "qcom,pm8150l-rpmh-regulators"; qcom,pmic-id = "c"; @@ -319,7 +319,7 @@ }; }; - pm8009-rpmh-regulators { + regulators-2 { compatible = "qcom,pm8009-rpmh-regulators"; qcom,pmic-id = "f"; diff --git a/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi b/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi index c958a8b16730..ff77cc3c879a 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi @@ -33,9 +33,10 @@ framebuffer: framebuffer@9c000000 { compatible = "simple-framebuffer"; reg = <0 0x9c000000 0 0x2300000>; - width = <1644>; - height = <3840>; - stride = <(1644 * 4)>; + /* Griffin BL initializes in 2.5k mode, not 4k */ + width = <1096>; + height = <2560>; + stride = <(1096 * 4)>; format = "a8r8g8b8"; /* * That's (going to be) a lot of clocks, but it's necessary due @@ -46,6 +47,40 @@ }; }; + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&focus_n &snapshot_n &vol_down_n>; + + key-camera-focus { + label = "Camera Focus"; + linux,code = <KEY_CAMERA_FOCUS>; + gpios = <&pm8150b_gpios 2 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + linux,can-disable; + gpio-key,wakeup; + }; + + key-camera-snapshot { + label = "Camera Snapshot"; + linux,code = <KEY_CAMERA>; + gpios = <&pm8150b_gpios 1 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + linux,can-disable; + gpio-key,wakeup; + }; + + key-vol-down { + label = "Volume Down"; + linux,code = <KEY_VOLUMEDOWN>; + gpios = <&pm8150_gpios 1 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + linux,can-disable; + gpio-key,wakeup; + }; + }; + vph_pwr: vph-pwr-regulator { compatible = "regulator-fixed"; regulator-name = "vph_pwr"; @@ -138,7 +173,7 @@ }; &apps_rsc { - pm8150-rpmh-regulators { + regulators-0 { compatible = "qcom,pm8150-rpmh-regulators"; qcom,pmic-id = "a"; @@ -271,7 +306,7 @@ }; }; - pm8150l-rpmh-regulators { + regulators-1 { compatible = "qcom,pm8150l-rpmh-regulators"; qcom,pmic-id = "c"; @@ -394,8 +429,18 @@ /* Qcom SMB1355 @ c */ /* Qcom SMB1390 @ 10 */ - /* NXP PN553 NFC @ 28 */ /* Qcom FSA4480 USB-C audio switch @ 43 */ + + nfc@28 { + compatible = "nxp,nxp-nci-i2c"; + reg = <0x28>; + + interrupt-parent = <&tlmm>; + interrupts = <47 IRQ_TYPE_EDGE_RISING>; + + enable-gpios = <&tlmm 41 GPIO_ACTIVE_HIGH>; + firmware-gpios = <&tlmm 48 GPIO_ACTIVE_HIGH>; + }; }; &i2c7 { @@ -410,10 +455,43 @@ /* Samsung touchscreen @ 48 */ }; +&pm8150_gpios { + vol_down_n: vol-down-n-state { + pins = "gpio1"; + function = "normal"; + power-source = <0>; + bias-pull-up; + input-enable; + }; +}; + +&pm8150b_gpios { + snapshot_n: snapshot-n-state { + pins = "gpio1"; + function = "normal"; + power-source = <0>; + bias-pull-up; + input-enable; + }; + + focus_n: focus-n-state { + pins = "gpio2"; + function = "normal"; + power-source = <0>; + bias-pull-up; + input-enable; + }; +}; + &pon_pwrkey { status = "okay"; }; +&pon_resin { + linux,code = <KEY_VOLUMEUP>; + status = "okay"; +}; + &qupv3_id_0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index a0c57fb798d3..fd20096cfc6e 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -9,6 +9,7 @@ #include <dt-bindings/power/qcom-rpmpd.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> #include <dt-bindings/clock/qcom,rpmh.h> +#include <dt-bindings/clock/qcom,dispcc-sm8150.h> #include <dt-bindings/clock/qcom,gcc-sm8150.h> #include <dt-bindings/clock/qcom,gpucc-sm8150.h> #include <dt-bindings/interconnect/qcom,osm-l3.h> @@ -60,9 +61,11 @@ #cooling-cells = <2>; L2_0: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; L3_0: l3-cache { compatible = "cache"; + cache-level = <3>; }; }; }; @@ -84,6 +87,7 @@ #cooling-cells = <2>; L2_100: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; @@ -106,6 +110,7 @@ #cooling-cells = <2>; L2_200: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -127,6 +132,7 @@ #cooling-cells = <2>; L2_300: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -148,6 +154,7 @@ #cooling-cells = <2>; L2_400: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -169,6 +176,7 @@ #cooling-cells = <2>; L2_500: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -190,6 +198,7 @@ #cooling-cells = <2>; L2_600: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -211,6 +220,7 @@ #cooling-cells = <2>; L2_700: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -600,55 +610,55 @@ compatible = "arm,psci-1.0"; method = "smc"; - CPU_PD0: cpu0 { + CPU_PD0: power-domain-cpu0 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&LITTLE_CPU_SLEEP_0>; }; - CPU_PD1: cpu1 { + CPU_PD1: power-domain-cpu1 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&LITTLE_CPU_SLEEP_0>; }; - CPU_PD2: cpu2 { + CPU_PD2: power-domain-cpu2 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&LITTLE_CPU_SLEEP_0>; }; - CPU_PD3: cpu3 { + CPU_PD3: power-domain-cpu3 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&LITTLE_CPU_SLEEP_0>; }; - CPU_PD4: cpu4 { + CPU_PD4: power-domain-cpu4 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&BIG_CPU_SLEEP_0>; }; - CPU_PD5: cpu5 { + CPU_PD5: power-domain-cpu5 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&BIG_CPU_SLEEP_0>; }; - CPU_PD6: cpu6 { + CPU_PD6: power-domain-cpu6 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&BIG_CPU_SLEEP_0>; }; - CPU_PD7: cpu7 { + CPU_PD7: power-domain-cpu7 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&BIG_CPU_SLEEP_0>; }; - CLUSTER_PD: cpu-cluster0 { + CLUSTER_PD: power-domain-cpu-cluster0 { #power-domain-cells = <0>; domain-idle-states = <&CLUSTER_SLEEP_0>; }; @@ -888,7 +898,7 @@ gpi_dma0: dma-controller@800000 { compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma"; - reg = <0 0x800000 0 0x60000>; + reg = <0 0x00800000 0 0x60000>; interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, @@ -926,7 +936,7 @@ power-domains = <&gcc EMAC_GDSC>; resets = <&gcc GCC_EMAC_BCR>; - iommus = <&apps_smmu 0x3C0 0x0>; + iommus = <&apps_smmu 0x3c0 0x0>; snps,tso; rx-fifo-depth = <4096>; @@ -966,7 +976,7 @@ spi0: spi@880000 { compatible = "qcom,geni-spi"; - reg = <0 0x880000 0 0x4000>; + reg = <0 0x00880000 0 0x4000>; reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; @@ -1000,7 +1010,7 @@ spi1: spi@884000 { compatible = "qcom,geni-spi"; - reg = <0 0x884000 0 0x4000>; + reg = <0 0x00884000 0 0x4000>; reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; @@ -1034,7 +1044,7 @@ spi2: spi@888000 { compatible = "qcom,geni-spi"; - reg = <0 0x888000 0 0x4000>; + reg = <0 0x00888000 0 0x4000>; reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; @@ -1068,7 +1078,7 @@ spi3: spi@88c000 { compatible = "qcom,geni-spi"; - reg = <0 0x88c000 0 0x4000>; + reg = <0 0x0088c000 0 0x4000>; reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; @@ -1102,7 +1112,7 @@ spi4: spi@890000 { compatible = "qcom,geni-spi"; - reg = <0 0x890000 0 0x4000>; + reg = <0 0x00890000 0 0x4000>; reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; @@ -1136,7 +1146,7 @@ spi5: spi@894000 { compatible = "qcom,geni-spi"; - reg = <0 0x894000 0 0x4000>; + reg = <0 0x00894000 0 0x4000>; reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; @@ -1170,7 +1180,7 @@ spi6: spi@898000 { compatible = "qcom,geni-spi"; - reg = <0 0x898000 0 0x4000>; + reg = <0 0x00898000 0 0x4000>; reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; @@ -1204,7 +1214,7 @@ spi7: spi@89c000 { compatible = "qcom,geni-spi"; - reg = <0 0x89c000 0 0x4000>; + reg = <0 0x0089c000 0 0x4000>; reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; @@ -1223,7 +1233,7 @@ gpi_dma1: dma-controller@a00000 { compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma"; - reg = <0 0xa00000 0 0x60000>; + reg = <0 0x00a00000 0 0x60000>; interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, @@ -1274,7 +1284,7 @@ spi8: spi@a80000 { compatible = "qcom,geni-spi"; - reg = <0 0xa80000 0 0x4000>; + reg = <0 0x00a80000 0 0x4000>; reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; @@ -1308,7 +1318,7 @@ spi9: spi@a84000 { compatible = "qcom,geni-spi"; - reg = <0 0xa84000 0 0x4000>; + reg = <0 0x00a84000 0 0x4000>; reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; @@ -1342,7 +1352,7 @@ spi10: spi@a88000 { compatible = "qcom,geni-spi"; - reg = <0 0xa88000 0 0x4000>; + reg = <0 0x00a88000 0 0x4000>; reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; @@ -1376,7 +1386,7 @@ spi11: spi@a8c000 { compatible = "qcom,geni-spi"; - reg = <0 0xa8c000 0 0x4000>; + reg = <0 0x00a8c000 0 0x4000>; reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; @@ -1419,7 +1429,7 @@ spi12: spi@a90000 { compatible = "qcom,geni-spi"; - reg = <0 0xa90000 0 0x4000>; + reg = <0 0x00a90000 0 0x4000>; reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; @@ -1437,7 +1447,7 @@ i2c16: i2c@94000 { compatible = "qcom,geni-i2c"; - reg = <0 0x0094000 0 0x4000>; + reg = <0 0x00094000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, @@ -1453,7 +1463,7 @@ spi16: spi@a94000 { compatible = "qcom,geni-spi"; - reg = <0 0xa94000 0 0x4000>; + reg = <0 0x00a94000 0 0x4000>; reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; @@ -1472,7 +1482,7 @@ gpi_dma2: dma-controller@c00000 { compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma"; - reg = <0 0xc00000 0 0x60000>; + reg = <0 0x00c00000 0 0x60000>; interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, @@ -1524,7 +1534,7 @@ spi17: spi@c80000 { compatible = "qcom,geni-spi"; - reg = <0 0xc80000 0 0x4000>; + reg = <0 0x00c80000 0 0x4000>; reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; @@ -1558,7 +1568,7 @@ spi18: spi@c84000 { compatible = "qcom,geni-spi"; - reg = <0 0xc84000 0 0x4000>; + reg = <0 0x00c84000 0 0x4000>; reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; @@ -1592,7 +1602,7 @@ spi19: spi@c88000 { compatible = "qcom,geni-spi"; - reg = <0 0xc88000 0 0x4000>; + reg = <0 0x00c88000 0 0x4000>; reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; @@ -1626,7 +1636,7 @@ spi13: spi@c8c000 { compatible = "qcom,geni-spi"; - reg = <0 0xc8c000 0 0x4000>; + reg = <0 0x00c8c000 0 0x4000>; reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; @@ -1660,7 +1670,7 @@ spi14: spi@c90000 { compatible = "qcom,geni-spi"; - reg = <0 0xc90000 0 0x4000>; + reg = <0 0x00c90000 0 0x4000>; reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; @@ -1694,7 +1704,7 @@ spi15: spi@c94000 { compatible = "qcom,geni-spi"; - reg = <0 0xc94000 0 0x4000>; + reg = <0 0x00c94000 0 0x4000>; reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; @@ -1767,6 +1777,12 @@ interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; }; + dma@10a2000 { + compatible = "qcom,sm8150-dcc", "qcom,dcc"; + reg = <0x0 0x010a2000 0x0 0x1000>, + <0x0 0x010ad000 0x0 0x3000>; + }; + pcie0: pci@1c00000 { compatible = "qcom,pcie-sm8150", "snps,dw-pcie"; reg = <0 0x01c00000 0 0x3000>, @@ -1851,10 +1867,10 @@ status = "disabled"; pcie0_lane: phy@1c06200 { - reg = <0 0x1c06200 0 0x170>, /* tx */ - <0 0x1c06400 0 0x200>, /* rx */ - <0 0x1c06800 0 0x1f0>, /* pcs */ - <0 0x1c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */ + reg = <0 0x01c06200 0 0x170>, /* tx */ + <0 0x01c06400 0 0x200>, /* rx */ + <0 0x01c06800 0 0x1f0>, /* pcs */ + <0 0x01c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */ clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; clock-names = "pipe0"; @@ -1950,12 +1966,12 @@ status = "disabled"; pcie1_lane: phy@1c0e200 { - reg = <0 0x1c0e200 0 0x170>, /* tx0 */ - <0 0x1c0e400 0 0x200>, /* rx0 */ - <0 0x1c0ea00 0 0x1f0>, /* pcs */ - <0 0x1c0e600 0 0x170>, /* tx1 */ - <0 0x1c0e800 0 0x200>, /* rx1 */ - <0 0x1c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ + reg = <0 0x01c0e200 0 0x170>, /* tx0 */ + <0 0x01c0e400 0 0x200>, /* rx0 */ + <0 0x01c0ea00 0 0x1f0>, /* pcs */ + <0 0x01c0e600 0 0x170>, /* tx1 */ + <0 0x01c0e800 0 0x200>, /* rx1 */ + <0 0x01c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; clock-names = "pipe0"; @@ -2041,13 +2057,6 @@ }; }; - ipa_virt: interconnect@1e00000 { - compatible = "qcom,sm8150-ipa-virt"; - reg = <0 0x01e00000 0 0x1000>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x20000>; @@ -2240,7 +2249,7 @@ }; adreno_smmu: iommu@2ca0000 { - compatible = "qcom,sm8150-smmu-500", "arm,mmu-500"; + compatible = "qcom,sm8150-smmu-500", "qcom,adreno-smmu", "arm,mmu-500"; reg = <0 0x02ca0000 0 0x10000>; #iommu-cells = <2>; #global-interrupts = <1>; @@ -3579,6 +3588,291 @@ qcom,bcm-voters = <&apps_bcm_voter>; }; + mdss: display-subsystem@ae00000 { + compatible = "qcom,sm8150-mdss"; + reg = <0 0x0ae00000 0 0x1000>; + reg-names = "mdss"; + + interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>, + <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>; + interconnect-names = "mdp0-mem", "mdp1-mem"; + + power-domains = <&dispcc MDSS_GDSC>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "bus", "nrt_bus", "core"; + + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x800 0x420>; + + status = "disabled"; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + mdss_mdp: display-controller@ae01000 { + compatible = "qcom,sm8150-dpu"; + reg = <0 0x0ae01000 0 0x8f000>, + <0 0x0aeb0000 0 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "iface", "bus", "core", "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd SM8150_MMCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf2_out: endpoint { + remote-endpoint = <&mdss_dsi1_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-171428571 { + opp-hz = /bits/ 64 <171428571>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-345000000 { + opp-hz = /bits/ 64 <345000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-460000000 { + opp-hz = /bits/ 64 <460000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss_dsi0: dsi@ae94000 { + compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae94000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SM8150_MMCX>; + + phys = <&mdss_dsi0_phy>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dsi0_out: endpoint { + }; + }; + }; + + dsi_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + mdss_dsi0_phy: phy@ae94400 { + compatible = "qcom,dsi-phy-7nm"; + reg = <0 0x0ae94400 0 0x200>, + <0 0x0ae94600 0 0x280>, + <0 0x0ae94900 0 0x260>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + + mdss_dsi1: dsi@ae96000 { + compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae96000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <5>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi1_phy 0>, + <&mdss_dsi1_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SM8150_MMCX>; + + phys = <&mdss_dsi1_phy>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dsi1_in: endpoint { + remote-endpoint = <&dpu_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dsi1_out: endpoint { + }; + }; + }; + }; + + mdss_dsi1_phy: phy@ae96400 { + compatible = "qcom,dsi-phy-7nm"; + reg = <0 0x0ae96400 0 0x200>, + <0 0x0ae96600 0 0x280>, + <0 0x0ae96900 0 0x260>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + }; + + dispcc: clock-controller@af00000 { + compatible = "qcom,sm8150-dispcc"; + reg = <0 0x0af00000 0 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>, + <&mdss_dsi1_phy 0>, + <&mdss_dsi1_phy 1>, + <0>, + <0>; + clock-names = "bi_tcxo", + "dsi0_phy_pll_out_byteclk", + "dsi0_phy_pll_out_dsiclk", + "dsi1_phy_pll_out_byteclk", + "dsi1_phy_pll_out_dsiclk", + "dp_phy_pll_link_clk", + "dp_phy_pll_vco_div_clk"; + power-domains = <&rpmhpd SM8150_MMCX>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sm8150-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x400>; @@ -3589,7 +3883,7 @@ interrupt-controller; }; - aoss_qmp: power-controller@c300000 { + aoss_qmp: power-management@c300000 { compatible = "qcom,sm8150-aoss-qmp", "qcom,aoss-qmp"; reg = <0x0 0x0c300000 0x0 0x400>; interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; @@ -3823,7 +4117,7 @@ reg = <0x0 0x17c20000 0x0 0x1000>; clock-frequency = <19200000>; - frame@17c21000{ + frame@17c21000 { frame-number = <0>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; @@ -4057,7 +4351,7 @@ type = "passive"; }; - cpu0_crit: cpu_crit { + cpu0_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -4101,7 +4395,7 @@ type = "passive"; }; - cpu1_crit: cpu_crit { + cpu1_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -4145,7 +4439,7 @@ type = "passive"; }; - cpu2_crit: cpu_crit { + cpu2_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -4189,7 +4483,7 @@ type = "passive"; }; - cpu3_crit: cpu_crit { + cpu3_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -4233,7 +4527,7 @@ type = "passive"; }; - cpu4_top_crit: cpu_crit { + cpu4_top_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -4277,7 +4571,7 @@ type = "passive"; }; - cpu5_top_crit: cpu_crit { + cpu5_top_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -4321,7 +4615,7 @@ type = "passive"; }; - cpu6_top_crit: cpu_crit { + cpu6_top_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -4365,7 +4659,7 @@ type = "passive"; }; - cpu7_top_crit: cpu_crit { + cpu7_top_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -4409,7 +4703,7 @@ type = "passive"; }; - cpu4_bottom_crit: cpu_crit { + cpu4_bottom_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -4453,7 +4747,7 @@ type = "passive"; }; - cpu5_bottom_crit: cpu_crit { + cpu5_bottom_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -4497,7 +4791,7 @@ type = "passive"; }; - cpu6_bottom_crit: cpu_crit { + cpu6_bottom_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -4541,7 +4835,7 @@ type = "passive"; }; - cpu7_bottom_crit: cpu_crit { + cpu7_bottom_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; diff --git a/arch/arm64/boot/dts/qcom/sm8250-hdk.dts b/arch/arm64/boot/dts/qcom/sm8250-hdk.dts index 632e98193d27..0aee7f8658b4 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-hdk.dts @@ -65,7 +65,7 @@ }; &apps_rsc { - pm8150-rpmh-regulators { + regulators-0 { compatible = "qcom,pm8150-rpmh-regulators"; qcom,pmic-id = "a"; @@ -199,7 +199,7 @@ }; }; - pm8150l-rpmh-regulators { + regulators-1 { compatible = "qcom,pm8150l-rpmh-regulators"; qcom,pmic-id = "c"; @@ -310,7 +310,7 @@ }; }; - pm8009-rpmh-regulators { + regulators-2 { compatible = "qcom,pm8009-rpmh-regulators"; qcom,pmic-id = "f"; diff --git a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts index 3ed8c84e25b8..e54cdc8bc31f 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts @@ -23,6 +23,29 @@ serial0 = &uart12; }; + wcd938x: audio-codec { + compatible = "qcom,wcd9380-codec"; + + reset-gpios = <&tlmm 32 GPIO_ACTIVE_LOW>; + + vdd-buck-supply = <&vreg_s4a_1p8>; + vdd-rxtx-supply = <&vreg_s4a_1p8>; + vdd-io-supply = <&vreg_s4a_1p8>; + vdd-mic-bias-supply = <&vreg_bob>; + + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; + qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt = <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt = <50000>; + qcom,rx-device = <&wcd_rx>; + qcom,tx-device = <&wcd_tx>; + + #sound-dai-cells = <1>; + }; + chosen { stdout-path = "serial0:115200n8"; }; @@ -164,7 +187,7 @@ }; &apps_rsc { - pm8150-rpmh-regulators { + regulators-0 { compatible = "qcom,pm8150-rpmh-regulators"; qcom,pmic-id = "a"; @@ -298,7 +321,7 @@ }; }; - pm8150l-rpmh-regulators { + regulators-1 { compatible = "qcom,pm8150l-rpmh-regulators"; qcom,pmic-id = "c"; @@ -409,7 +432,7 @@ }; }; - pm8009-rpmh-regulators { + regulators-2 { compatible = "qcom,pm8009-rpmh-regulators"; qcom,pmic-id = "f"; @@ -631,27 +654,6 @@ firmware-name = "qcom/sm8250/slpi.mbn"; }; -&soc { - wcd938x: codec { - compatible = "qcom,wcd9380-codec"; - #sound-dai-cells = <1>; - reset-gpios = <&tlmm 32 GPIO_ACTIVE_LOW>; - vdd-buck-supply = <&vreg_s4a_1p8>; - vdd-rxtx-supply = <&vreg_s4a_1p8>; - vdd-io-supply = <&vreg_s4a_1p8>; - vdd-mic-bias-supply = <&vreg_bob>; - qcom,micbias1-microvolt = <1800000>; - qcom,micbias2-microvolt = <1800000>; - qcom,micbias3-microvolt = <1800000>; - qcom,micbias4-microvolt = <1800000>; - qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>; - qcom,mbhc-headset-vthreshold-microvolt = <1700000>; - qcom,mbhc-headphone-vthreshold-microvolt = <50000>; - qcom,rx-device = <&wcd_rx>; - qcom,tx-device = <&wcd_tx>; - }; -}; - &sound { compatible = "qcom,sm8250-sndcard"; model = "SM8250-MTP-WCD9380-WSA8810-VA-DMIC"; @@ -757,6 +759,8 @@ }; &swr0 { + status = "okay"; + left_spkr: speaker@0,3 { compatible = "sdw10217211000"; reg = <0 3>; @@ -890,3 +894,7 @@ &venus { status = "okay"; }; + +&wsamacro { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi index 09a31f707639..b9c982a059df 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi @@ -123,7 +123,7 @@ }; &apps_rsc { - pm8150-rpmh-regulators { + regulators-0 { compatible = "qcom,pm8150-rpmh-regulators"; qcom,pmic-id = "a"; @@ -247,7 +247,7 @@ * ab: 4600000-6100000 * ibb: 800000-5400000 */ - pm8150l-rpmh-regulators { + regulators-1 { compatible = "qcom,pm8150l-rpmh-regulators"; qcom,pmic-id = "c"; @@ -360,7 +360,7 @@ }; }; - pm8009-rpmh-regulators { + regulators-2 { compatible = "qcom,pm8009-rpmh-regulators"; qcom,pmic-id = "f"; @@ -454,7 +454,7 @@ status = "okay"; clock-frequency = <1000000>; - cs35l41_l: cs35l41@40 { + cs35l41_l: speaker-amp@40 { compatible = "cirrus,cs35l41"; reg = <0x40>; interrupt-parent = <&tlmm>; @@ -469,7 +469,7 @@ #sound-dai-cells = <1>; }; - cs35l41_r: cs35l41@41 { + cs35l41_r: speaker-amp@41 { compatible = "cirrus,cs35l41"; reg = <0x41>; interrupt-parent = <&tlmm>; @@ -522,10 +522,8 @@ clock-frequency = <400000>; /* Qcom SMB1390 @ 10 */ - /* Silicon Labs SI4704 FM Radio Receiver @ 11 */ /* Qcom SMB1390_slave @ 18 */ /* HALO HL6111R Qi charger @ 25 */ - /* Richwave RTC6226 FM Radio Receiver @ 64 */ }; &pcie0 { diff --git a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish.dts b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish.dts new file mode 100644 index 000000000000..acaa99c5ff8b --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish.dts @@ -0,0 +1,630 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, 2023 Jianhua Lu <lujianhua000@gmail.com> + */ + +/dts-v1/; + +#include <dt-bindings/arm/qcom,ids.h> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> +#include "sm8250.dtsi" +#include "pm8150.dtsi" +#include "pm8150b.dtsi" +#include "pm8150l.dtsi" +#include "pm8009.dtsi" + +/* + * Delete following upstream (sm8250.dtsi) reserved + * memory mappings which are different on this device. + */ +/delete-node/ &adsp_mem; +/delete-node/ &cdsp_secure_heap; +/delete-node/ &slpi_mem; +/delete-node/ &spss_mem; +/delete-node/ &xbl_aop_mem; + +/ { + model = "Xiaomi Mi Pad 5 Pro"; + compatible = "xiaomi,elish", "qcom,sm8250"; + classis-type = "tablet"; + + /* required for bootloader to select correct board */ + qcom,msm-id = <QCOM_ID_SM8250 0x20001>; /* SM8250 v2.1 */ + qcom,board-id = <0x10008 0>; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + framebuffer: framebuffer@9c000000 { + compatible = "simple-framebuffer"; + reg = <0x0 0x9c000000 0x0 0x2300000>; + width = <1600>; + height = <2560>; + stride = <(1600 * 4)>; + format = "a8r8g8b8"; + }; + }; + + battery_l: battery-l { + compatible = "simple-battery"; + voltage-min-design-microvolt = <3870000>; + energy-full-design-microwatt-hours = <16600000>; + charge-full-design-microamp-hours = <4300000>; + }; + + battery_r: battery-r { + compatible = "simple-battery"; + voltage-min-design-microvolt = <3870000>; + energy-full-design-microwatt-hours = <16600000>; + charge-full-design-microamp-hours = <4300000>; + }; + + bl_vddpos_5p5: bl-vddpos-regulator { + compatible = "regulator-fixed"; + regulator-name = "bl_vddpos_5p5"; + regulator-min-microvolt = <5500000>; + regulator-max-microvolt = <5500000>; + regulator-enable-ramp-delay = <233>; + gpio = <&tlmm 130 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + }; + + bl_vddneg_5p5: bl-vddneg-regulator { + compatible = "regulator-fixed"; + regulator-name = "bl_vddneg_5p5"; + regulator-min-microvolt = <5500000>; + regulator-max-microvolt = <5500000>; + regulator-enable-ramp-delay = <233>; + gpio = <&tlmm 131 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&vol_up_n>; + + key-vol-up { + label = "Volume Up"; + gpios = <&pm8150_gpios 6 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + debounce-interval = <15>; + linux,can-disable; + gpio-key,wakeup; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; + + /* S6c is really ebi.lvl but it's there for supply map completeness sake. */ + vreg_s6c_0p88: smpc6-regulator { + compatible = "regulator-fixed"; + regulator-name = "vreg_s6c_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-always-on; + vin-supply = <&vph_pwr>; + }; + + reserved-memory { + xbl_aop_mem: xbl-aop@80700000 { + reg = <0x0 0x80600000 0x0 0x260000>; + no-map; + }; + + slpi_mem: slpi@88c00000 { + reg = <0x0 0x88c00000 0x0 0x2f00000>; + no-map; + }; + + adsp_mem: adsp@8bb00000 { + reg = <0x0 0x8bb00000 0x0 0x2500000>; + no-map; + }; + + spss_mem: spss@8e000000 { + reg = <0x0 0x8e000000 0x0 0x100000>; + no-map; + }; + + cdsp_secure_heap: cdsp-secure-heap@8e100000 { + reg = <0x0 0x8e100000 0x0 0x4600000>; + no-map; + }; + + cont_splash_mem: cont-splash@9c000000 { + reg = <0x0 0x9c000000 0x0 0x2300000>; + no-map; + }; + + ramoops@b0000000 { + compatible = "ramoops"; + reg = <0x0 0xb0000000 0x0 0x400000>; + record-size = <0x1000>; + console-size = <0x200000>; + ecc-size = <16>; + no-map; + }; + }; +}; + +&adsp { + firmware-name = "qcom/sm8250/xiaomi/elish/adsp.mbn"; + status = "okay"; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm8150-rpmh-regulators"; + qcom,pmic-id = "a"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + vdd-l1-l8-l11-supply = <&vreg_s6c_0p88>; + vdd-l2-l10-supply = <&vreg_bob>; + vdd-l3-l4-l5-l18-supply = <&vreg_s6a_0p95>; + vdd-l6-l9-supply = <&vreg_s8c_1p35>; + vdd-l7-l12-l14-l15-supply = <&vreg_s5a_1p9>; + vdd-l13-l16-l17-supply = <&vreg_bob>; + + /* (S1+S2+S3) - cx.lvl (ARC) */ + + vreg_s4a_1p8: smps4 { + regulator-name = "vreg_s4a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1920000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s5a_1p9: smps5 { + regulator-name = "vreg_s5a_1p9"; + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <2040000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s6a_0p95: smps6 { + regulator-name = "vreg_s6a_0p95"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1128000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2a_3p1: ldo2 { + regulator-name = "vreg_l2a_3p1"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3a_0p9: ldo3 { + regulator-name = "vreg_l3a_0p9"; + regulator-min-microvolt = <928000>; + regulator-max-microvolt = <932000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + /* L4 - lmx.lvl (ARC) */ + + vreg_l5a_0p88: ldo5 { + regulator-name = "vreg_l5a_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l6a_1p2: ldo6 { + regulator-name = "vreg_l6a_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + /* L7 is unused. */ + + vreg_l9a_1p2: ldo9 { + regulator-name = "vreg_l9a_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + /* L10 is unused, L11 - lcx.lvl (ARC) */ + + vreg_l12a_1p8: ldo12 { + regulator-name = "vreg_l12a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + /* L13 is unused. */ + + vreg_l14a_1p88: ldo14 { + regulator-name = "vreg_l14a_1p88"; + regulator-min-microvolt = <1880000>; + regulator-max-microvolt = <1880000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + /* L15 & L16 are unused. */ + + vreg_l17a_3p0: ldo17 { + regulator-name = "vreg_l17a_3p0"; + regulator-min-microvolt = <2496000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l18a_0p9: ldo18 { + regulator-name = "vreg_l18a_0p9"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + /* + * Remaining regulators that are not yet supported: + * OLEDB: 4925000-8100000 + * ab: 4600000-6100000 + * ibb: 800000-5400000 + */ + regulators-1 { + compatible = "qcom,pm8150l-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-l1-l8-supply = <&vreg_s4a_1p8>; + vdd-l2-l3-supply = <&vreg_s8c_1p35>; + vdd-l4-l5-l6-supply = <&vreg_bob>; + vdd-l7-l11-supply = <&vreg_bob>; + vdd-l9-l10-supply = <&vreg_bob>; + vdd-bob-supply = <&vph_pwr>; + + vreg_bob: bob { + regulator-name = "vreg_bob"; + regulator-min-microvolt = <3350000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>; + }; + + /* + * S1-S6 are ARCs: + * (S1+S2) - gfx.lvl, + * S3 - mx.lvl, + * (S4+S5) - mmcx.lvl, + * S6 - ebi.lvl + */ + + vreg_s7c_0p35: smps7 { + regulator-name = "vreg_s7c_0p35"; + regulator-min-microvolt = <348000>; + regulator-max-microvolt = <1000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s8c_1p35: smps8 { + regulator-name = "vreg_s8c_1p35"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1400000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l1c_1p8: ldo1 { + regulator-name = "vreg_l1c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + /* L2-4 are unused. */ + + vreg_l5c_1p8: ldo5 { + regulator-name = "vreg_l5c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l6c_2p9: ldo6 { + regulator-name = "vreg_l6c_2p9"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l7c_2p85: ldo7 { + regulator-name = "vreg_l7c_2p85"; + regulator-min-microvolt = <2856000>; + regulator-max-microvolt = <3104000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l8c_1p8: ldo8 { + regulator-name = "vreg_l8c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l9c_2p9: ldo9 { + regulator-name = "vreg_l9c_2p9"; + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l10c_3p3: ldo10 { + regulator-name = "vreg_l10c_3p3"; + regulator-min-microvolt = <3296000>; + regulator-max-microvolt = <3296000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l11c_3p0: ldo11 { + regulator-name = "vreg_l11c_3p0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-2 { + compatible = "qcom,pm8009-rpmh-regulators"; + qcom,pmic-id = "f"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vreg_bob>; + vdd-l2-supply = <&vreg_s8c_1p35>; + vdd-l5-l6-supply = <&vreg_bob>; + vdd-l7-supply = <&vreg_s4a_1p8>; + + vreg_s1f_1p2: smps1 { + regulator-name = "vreg_s1f_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s2f_0p5: smps2 { + regulator-name = "vreg_s2f_0p5"; + regulator-min-microvolt = <512000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + /* L1 is unused. */ + + vreg_l2f_1p3: ldo2 { + regulator-name = "vreg_l2f_1p3"; + regulator-min-microvolt = <1304000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + /* L3 & L4 are unused. */ + + vreg_l5f_2p8: ldo5 { + regulator-name = "vreg_l5f_2p85"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l6f_2p8: ldo6 { + regulator-name = "vreg_l6f_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l7f_1p8: ldo7 { + regulator-name = "vreg_l7f_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; +}; + +&cdsp { + firmware-name = "qcom/sm8250/xiaomi/elish/cdsp.mbn"; + status = "okay"; +}; + +&gmu { + status = "okay"; +}; + +&gpi_dma0 { + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&gpi_dma2 { + status = "okay"; +}; + +&gpu { + status = "okay"; + + zap-shader { + memory-region = <&gpu_mem>; + firmware-name = "qcom/sm8250/xiaomi/elish/a650_zap.mbn"; + }; +}; + +&i2c0 { + clock-frequency = <400000>; + status = "okay"; + + fuel-gauge@55 { + compatible = "ti,bq27z561"; + reg = <0x55>; + monitored-battery = <&battery_r>; + }; +}; + +&i2c11 { + clock-frequency = <400000>; + status = "okay"; + + backlight: backlight@11 { + compatible = "kinetic,ktz8866"; + reg = <0x11>; + vddpos-supply = <&bl_vddpos_5p5>; + vddneg-supply = <&bl_vddneg_5p5>; + enable-gpios = <&tlmm 139 GPIO_ACTIVE_HIGH>; + current-num-sinks = <5>; + kinetic,current-ramp-delay-ms = <128>; + kinetic,led-enable-ramp-delay-ms = <1>; + kinetic,enable-lcd-bias; + }; +}; + +&i2c13 { + clock-frequency = <400000>; + status = "okay"; + + fuel-gauge@55 { + compatible = "ti,bq27z561"; + reg = <0x55>; + monitored-battery = <&battery_l>; + }; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie0_phy { + vdda-phy-supply = <&vreg_l5a_0p88>; + vdda-pll-supply = <&vreg_l9a_1p2>; + status = "okay"; +}; + +&pm8150_gpios { + vol_up_n: vol-up-n-state { + pins = "gpio6"; + function = "normal"; + power-source = <1>; + input-enable; + bias-pull-up; + }; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + linux,code = <KEY_VOLUMEDOWN>; + status = "okay"; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&qupv3_id_2 { + status = "okay"; +}; + +&slpi { + firmware-name = "qcom/sm8250/xiaomi/elish/slpi.mbn"; + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <40 4>; +}; + +&usb_1 { + /* USB 2.0 only */ + qcom,select-utmi-as-pipe-clk; + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "peripheral"; + maximum-spped = "high-speed"; + /* Remove USB3 phy */ + phys = <&usb_1_hsphy>; + phy-names = "usb2-phy"; +}; + +&usb_1_hsphy { + vdda-pll-supply = <&vreg_l5a_0p88>; + vdda18-supply = <&vreg_l12a_1p8>; + vdda33-supply = <&vreg_l2a_3p1>; + status = "okay"; +}; + +&ufs_mem_hc { + vcc-supply = <&vreg_l17a_3p0>; + vcc-max-microamp = <800000>; + vccq-supply = <&vreg_l6a_1p2>; + vccq-max-microamp = <800000>; + vccq2-supply = <&vreg_s4a_1p8>; + vccq2-max-microamp = <800000>; + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l5a_0p88>; + vdda-pll-supply = <&vreg_l9a_1p2>; + status = "okay"; +}; + +&venus { + firmware-name = "qcom/sm8250/elish/venus.mbn"; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index dab5579946f3..f69fa68a1222 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -110,9 +110,15 @@ #cooling-cells = <2>; L2_0: l2-cache { compatible = "cache"; + cache-level = <2>; + cache-size = <0x20000>; + cache-unified; next-level-cache = <&L3_0>; L3_0: l3-cache { compatible = "cache"; + cache-level = <3>; + cache-size = <0x400000>; + cache-unified; }; }; }; @@ -134,6 +140,9 @@ #cooling-cells = <2>; L2_100: l2-cache { compatible = "cache"; + cache-level = <2>; + cache-size = <0x20000>; + cache-unified; next-level-cache = <&L3_0>; }; }; @@ -155,6 +164,9 @@ #cooling-cells = <2>; L2_200: l2-cache { compatible = "cache"; + cache-level = <2>; + cache-size = <0x20000>; + cache-unified; next-level-cache = <&L3_0>; }; }; @@ -176,6 +188,9 @@ #cooling-cells = <2>; L2_300: l2-cache { compatible = "cache"; + cache-level = <2>; + cache-size = <0x20000>; + cache-unified; next-level-cache = <&L3_0>; }; }; @@ -197,6 +212,9 @@ #cooling-cells = <2>; L2_400: l2-cache { compatible = "cache"; + cache-level = <2>; + cache-size = <0x40000>; + cache-unified; next-level-cache = <&L3_0>; }; }; @@ -218,6 +236,9 @@ #cooling-cells = <2>; L2_500: l2-cache { compatible = "cache"; + cache-level = <2>; + cache-size = <0x40000>; + cache-unified; next-level-cache = <&L3_0>; }; @@ -240,6 +261,9 @@ #cooling-cells = <2>; L2_600: l2-cache { compatible = "cache"; + cache-level = <2>; + cache-size = <0x40000>; + cache-unified; next-level-cache = <&L3_0>; }; }; @@ -261,6 +285,9 @@ #cooling-cells = <2>; L2_700: l2-cache { compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; + cache-unified; next-level-cache = <&L3_0>; }; }; @@ -334,7 +361,6 @@ exit-latency-us = <6562>; min-residency-us = <9987>; local-timer-stop; - status = "disabled"; }; }; }; @@ -651,55 +677,55 @@ compatible = "arm,psci-1.0"; method = "smc"; - CPU_PD0: cpu0 { + CPU_PD0: power-domain-cpu0 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&LITTLE_CPU_SLEEP_0>; }; - CPU_PD1: cpu1 { + CPU_PD1: power-domain-cpu1 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&LITTLE_CPU_SLEEP_0>; }; - CPU_PD2: cpu2 { + CPU_PD2: power-domain-cpu2 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&LITTLE_CPU_SLEEP_0>; }; - CPU_PD3: cpu3 { + CPU_PD3: power-domain-cpu3 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&LITTLE_CPU_SLEEP_0>; }; - CPU_PD4: cpu4 { + CPU_PD4: power-domain-cpu4 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&BIG_CPU_SLEEP_0>; }; - CPU_PD5: cpu5 { + CPU_PD5: power-domain-cpu5 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&BIG_CPU_SLEEP_0>; }; - CPU_PD6: cpu6 { + CPU_PD6: power-domain-cpu6 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&BIG_CPU_SLEEP_0>; }; - CPU_PD7: cpu7 { + CPU_PD7: power-domain-cpu7 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&BIG_CPU_SLEEP_0>; }; - CLUSTER_PD: cpu-cluster0 { + CLUSTER_PD: power-domain-cpu-cluster0 { #power-domain-cells = <0>; domain-idle-states = <&CLUSTER_SLEEP_0>; }; @@ -1887,10 +1913,10 @@ status = "disabled"; pcie0_lane: phy@1c06200 { - reg = <0 0x1c06200 0 0x170>, /* tx */ - <0 0x1c06400 0 0x200>, /* rx */ - <0 0x1c06800 0 0x1f0>, /* pcs */ - <0 0x1c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */ + reg = <0 0x01c06200 0 0x170>, /* tx */ + <0 0x01c06400 0 0x200>, /* rx */ + <0 0x01c06800 0 0x1f0>, /* pcs */ + <0 0x01c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */ clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; clock-names = "pipe0"; @@ -1993,12 +2019,12 @@ status = "disabled"; pcie1_lane: phy@1c0e200 { - reg = <0 0x1c0e200 0 0x170>, /* tx0 */ - <0 0x1c0e400 0 0x200>, /* rx0 */ - <0 0x1c0ea00 0 0x1f0>, /* pcs */ - <0 0x1c0e600 0 0x170>, /* tx1 */ - <0 0x1c0e800 0 0x200>, /* rx1 */ - <0 0x1c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ + reg = <0 0x01c0e200 0 0x170>, /* tx0 */ + <0 0x01c0e400 0 0x200>, /* rx0 */ + <0 0x01c0ea00 0 0x1f0>, /* pcs */ + <0 0x01c0e600 0 0x170>, /* tx1 */ + <0 0x01c0e800 0 0x200>, /* rx1 */ + <0 0x01c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; clock-names = "pipe0"; @@ -2082,7 +2108,7 @@ pcie2_phy: phy@1c16000 { compatible = "qcom,sm8250-qmp-modem-pcie-phy"; - reg = <0 0x1c16000 0 0x1c0>; + reg = <0 0x01c16000 0 0x1c0>; #address-cells = <2>; #size-cells = <2>; ranges; @@ -2101,12 +2127,12 @@ status = "disabled"; pcie2_lane: phy@1c16200 { - reg = <0 0x1c16200 0 0x170>, /* tx0 */ - <0 0x1c16400 0 0x200>, /* rx0 */ - <0 0x1c16a00 0 0x1f0>, /* pcs */ - <0 0x1c16600 0 0x170>, /* tx1 */ - <0 0x1c16800 0 0x200>, /* rx1 */ - <0 0x1c16e00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ + reg = <0 0x01c16200 0 0x170>, /* tx0 */ + <0 0x01c16400 0 0x200>, /* rx0 */ + <0 0x01c16a00 0 0x1f0>, /* pcs */ + <0 0x01c16600 0 0x170>, /* tx1 */ + <0 0x01c16800 0 0x200>, /* rx1 */ + <0 0x01c16e00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; clock-names = "pipe0"; @@ -2189,13 +2215,6 @@ }; }; - ipa_virt: interconnect@1e00000 { - compatible = "qcom,sm8250-ipa-virt"; - reg = <0 0x01e00000 0 0x1000>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x40000>; @@ -2215,12 +2234,13 @@ clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen"; #clock-cells = <0>; - clock-frequency = <9600000>; clock-output-names = "mclk"; #sound-dai-cells = <1>; pinctrl-names = "default"; pinctrl-0 = <&wsa_swr_active>; + + status = "disabled"; }; swr0: soundwire-controller@3250000 { @@ -2241,6 +2261,8 @@ #sound-dai-cells = <1>; #address-cells = <2>; #size-cells = <0>; + + status = "disabled"; }; audiocc: clock-controller@3300000 { @@ -2263,7 +2285,6 @@ clock-names = "mclk", "macro", "dcodec"; #clock-cells = <0>; - clock-frequency = <9600000>; clock-output-names = "fsgen"; #sound-dai-cells = <1>; }; @@ -2284,7 +2305,6 @@ clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; #clock-cells = <0>; - clock-frequency = <9600000>; clock-output-names = "mclk"; #sound-dai-cells = <1>; }; @@ -2300,15 +2320,15 @@ qcom,din-ports = <0>; qcom,dout-ports = <5>; - qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1F 0x1F 0x07 0x00>; - qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>; - qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>; - qcom,ports-hstart = /bits/ 8 <0xFF 0x03 0xFF 0xFF 0xFF>; - qcom,ports-hstop = /bits/ 8 <0xFF 0x06 0xFF 0xFF 0xFF>; - qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xFF 0xFF>; - qcom,ports-block-pack-mode = /bits/ 8 <0xFF 0x00 0x01 0xFF 0xFF>; + qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>; + qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>; + qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; + qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; + qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; + qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; + qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; - qcom,ports-block-group-count = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0x00>; + qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; #sound-dai-cells = <1>; #address-cells = <2>; @@ -2331,10 +2351,7 @@ clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; #clock-cells = <0>; - clock-frequency = <9600000>; clock-output-names = "mclk"; - #address-cells = <2>; - #size-cells = <2>; #sound-dai-cells = <1>; }; @@ -2352,15 +2369,15 @@ qcom,din-ports = <5>; qcom,dout-ports = <0>; - qcom,ports-sinterval-low = /bits/ 8 <0xFF 0x01 0x01 0x03 0x03>; - qcom,ports-offset1 = /bits/ 8 <0xFF 0x01 0x00 0x02 0x00>; - qcom,ports-offset2 = /bits/ 8 <0xFF 0x00 0x00 0x00 0x00>; - qcom,ports-block-pack-mode = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>; - qcom,ports-hstart = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>; - qcom,ports-hstop = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>; - qcom,ports-word-length = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>; - qcom,ports-block-group-count = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF>; - qcom,ports-lane-control = /bits/ 8 <0xFF 0x00 0x01 0x00 0x01>; + qcom,ports-sinterval-low = /bits/ 8 <0xff 0x01 0x01 0x03 0x03>; + qcom,ports-offset1 = /bits/ 8 <0xff 0x01 0x00 0x02 0x00>; + qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x00 0x00 0x00>; + qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; + qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; + qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; + qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; + qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; + qcom,ports-lane-control = /bits/ 8 <0xff 0x00 0x01 0x00 0x01>; #sound-dai-cells = <1>; #address-cells = <2>; #size-cells = <0>; @@ -2376,7 +2393,7 @@ clock-names = "core", "audio", "bus"; }; - lpass_tlmm: pinctrl@33c0000{ + lpass_tlmm: pinctrl@33c0000 { compatible = "qcom,sm8250-lpass-lpi-pinctrl"; reg = <0 0x033c0000 0x0 0x20000>, <0 0x03550000 0x0 0x10000>; @@ -3323,9 +3340,6 @@ }; }; - sound: sound { - }; - usb_1_hsphy: phy@88e3000 { compatible = "qcom,sm8250-usb-hs-phy", "qcom,usb-snps-hs-7nm-phy"; @@ -3676,7 +3690,7 @@ }; cci0: cci@ac4f000 { - compatible = "qcom,sm8250-cci"; + compatible = "qcom,sm8250-cci", "qcom,msm8996-cci"; #address-cells = <1>; #size-cells = <0>; @@ -3717,7 +3731,7 @@ }; cci1: cci@ac50000 { - compatible = "qcom,sm8250-cci"; + compatible = "qcom,sm8250-cci", "qcom,msm8996-cci"; #address-cells = <1>; #size-cells = <0>; @@ -3761,16 +3775,16 @@ compatible = "qcom,sm8250-camss"; status = "disabled"; - reg = <0 0xac6a000 0 0x2000>, - <0 0xac6c000 0 0x2000>, - <0 0xac6e000 0 0x1000>, - <0 0xac70000 0 0x1000>, - <0 0xac72000 0 0x1000>, - <0 0xac74000 0 0x1000>, - <0 0xacb4000 0 0xd000>, - <0 0xacc3000 0 0xd000>, - <0 0xacd9000 0 0x2200>, - <0 0xacdb200 0 0x2200>; + reg = <0 0x0ac6a000 0 0x2000>, + <0 0x0ac6c000 0 0x2000>, + <0 0x0ac6e000 0 0x1000>, + <0 0x0ac70000 0 0x1000>, + <0 0x0ac72000 0 0x1000>, + <0 0x0ac74000 0 0x1000>, + <0 0x0acb4000 0 0xd000>, + <0 0x0acc3000 0 0xd000>, + <0 0x0acd9000 0 0x2200>, + <0 0x0acdb200 0 0x2200>; reg-names = "csiphy0", "csiphy1", "csiphy2", @@ -3955,7 +3969,7 @@ #power-domain-cells = <1>; }; - mdss: mdss@ae00000 { + mdss: display-subsystem@ae00000 { compatible = "qcom,sm8250-mdss"; reg = <0 0x0ae00000 0 0x1000>; reg-names = "mdss"; @@ -4050,7 +4064,8 @@ }; dsi0: dsi@ae94000 { - compatible = "qcom,mdss-dsi-ctrl"; + compatible = "qcom,sm8250-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; reg = <0 0x0ae94000 0 0x400>; reg-names = "dsi_ctrl"; @@ -4141,7 +4156,8 @@ }; dsi1: dsi@ae96000 { - compatible = "qcom,mdss-dsi-ctrl"; + compatible = "qcom,sm8250-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; reg = <0 0x0ae96000 0 0x400>; reg-names = "dsi_ctrl"; @@ -4269,7 +4285,7 @@ #thermal-sensor-cells = <1>; }; - aoss_qmp: power-controller@c300000 { + aoss_qmp: power-management@c300000 { compatible = "qcom,sm8250-aoss-qmp", "qcom,aoss-qmp"; reg = <0 0x0c300000 0 0x400>; interrupts-extended = <&ipcc IPCC_CLIENT_AOP @@ -5468,6 +5484,9 @@ }; }; + sound: sound { + }; + timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 13 @@ -5500,7 +5519,7 @@ type = "passive"; }; - cpu0_crit: cpu_crit { + cpu0_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -5544,7 +5563,7 @@ type = "passive"; }; - cpu1_crit: cpu_crit { + cpu1_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -5588,7 +5607,7 @@ type = "passive"; }; - cpu2_crit: cpu_crit { + cpu2_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -5632,7 +5651,7 @@ type = "passive"; }; - cpu3_crit: cpu_crit { + cpu3_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -5676,7 +5695,7 @@ type = "passive"; }; - cpu4_top_crit: cpu_crit { + cpu4_top_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -5720,7 +5739,7 @@ type = "passive"; }; - cpu5_top_crit: cpu_crit { + cpu5_top_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -5764,7 +5783,7 @@ type = "passive"; }; - cpu6_top_crit: cpu_crit { + cpu6_top_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -5808,7 +5827,7 @@ type = "passive"; }; - cpu7_top_crit: cpu_crit { + cpu7_top_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -5852,7 +5871,7 @@ type = "passive"; }; - cpu4_bottom_crit: cpu_crit { + cpu4_bottom_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -5896,7 +5915,7 @@ type = "passive"; }; - cpu5_bottom_crit: cpu_crit { + cpu5_bottom_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -5940,7 +5959,7 @@ type = "passive"; }; - cpu6_bottom_crit: cpu_crit { + cpu6_bottom_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -5984,7 +6003,7 @@ type = "passive"; }; - cpu7_bottom_crit: cpu_crit { + cpu7_bottom_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts index 26a608144886..09baf6959c71 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts @@ -20,6 +20,17 @@ stdout-path = "serial0:115200n8"; }; + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <<9611_out>; + }; + }; + }; + vph_pwr: vph-pwr-regulator { compatible = "regulator-fixed"; regulator-name = "vph_pwr"; @@ -29,6 +40,31 @@ regulator-always-on; regulator-boot-on; }; + + lt9611_1v2: lt9611-1v2-regulator { + compatible = "regulator-fixed"; + regulator-name = "LT9611_1V2"; + + vin-supply = <&vph_pwr>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + gpio = <&tlmm 49 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + }; + + lt9611_3v3: lt9611-3v3-regulator { + compatible = "regulator-fixed"; + regulator-name = "LT9611_3V3"; + + vin-supply = <&vreg_bob>; + gpio = <&tlmm 47 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + regulator-boot-on; + regulator-always-on; + }; }; &adsp { @@ -37,7 +73,7 @@ }; &apps_rsc { - pm8350-rpmh-regulators { + regulators-0 { compatible = "qcom,pm8350-rpmh-regulators"; qcom,pmic-id = "b"; @@ -142,7 +178,7 @@ }; }; - pm8350c-rpmh-regulators { + regulators-1 { compatible = "qcom,pm8350c-rpmh-regulators"; qcom,pmic-id = "c"; @@ -221,19 +257,135 @@ firmware-name = "qcom/sm8350/cdsp.mbn"; }; +&dispcc { + status = "okay"; +}; + +&mdss_dsi0 { + vdda-supply = <&vreg_l6b_1p2>; + status = "okay"; + + ports { + port@1 { + endpoint { + remote-endpoint = <<9611_a>; + data-lanes = <0 1 2 3>; + }; + }; + }; +}; + +&mdss_dsi0_phy { + vdds-supply = <&vreg_l5b_0p88>; + status = "okay"; +}; + &gpi_dma1 { status = "okay"; }; +&gpu { + status = "okay"; + + zap-shader { + firmware-name = "qcom/sm8350/a660_zap.mbn"; + }; +}; + +&i2c15 { + clock-frequency = <400000>; + status = "okay"; + + lt9611_codec: hdmi-bridge@2b { + compatible = "lontium,lt9611uxc"; + reg = <0x2b>; + + interrupts-extended = <&tlmm 50 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&tlmm 48 GPIO_ACTIVE_HIGH>; + + vdd-supply = <<9611_1v2>; + vcc-supply = <<9611_3v3>; + + pinctrl-names = "default"; + pinctrl-0 = <<9611_state>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lt9611_a: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + + port@2 { + reg = <2>; + + lt9611_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; +}; + +&mdss { + status = "okay"; +}; + +&mdss_mdp { + status = "okay"; +}; + &mpss { status = "okay"; firmware-name = "qcom/sm8350/modem.mbn"; }; +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_default_state>; + + perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + + status = "okay"; +}; + +&pcie0_phy { + vdda-phy-supply = <&vreg_l5b_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; + + status = "okay"; +}; + +&pcie1 { + perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_default_state>; + + status = "okay"; +}; + +&pcie1_phy { + status = "okay"; + vdda-phy-supply = <&vreg_l5b_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; +}; + &qupv3_id_0 { status = "okay"; }; +&qupv3_id_2 { + status = "okay"; +}; + &slpi { status = "okay"; firmware-name = "qcom/sm8350/slpi.mbn"; @@ -241,6 +393,258 @@ &tlmm { gpio-reserved-ranges = <52 8>; + + gpio-line-names = + "APPS_I2C_SDA", /* GPIO_0 */ + "APPS_I2C_SCL", + "FSA_INT_N", + "USER_LED3_EN", + "SMBUS_SDA_1P8", + "SMBUS_SCL_1P8", + "2M2_3P3_EN", + "ALERT_DUAL_M2_N", + "EXP_UART_CTS", + "EXP_UART_RFR", + "EXP_UART_TX", /* GPIO_10 */ + "EXP_UART_RX", + "NC", + "NC", + "RCM_MARKER1", + "WSA0_EN", + "CAM1_RESET_N", + "CAM0_RESET_N", + "DEBUG_UART_TX", + "DEBUG_UART_RX", + "TS_I2C_SDA", /* GPIO_20 */ + "TS_I2C_SCL", + "TS_RESET_N", + "TS_INT_N", + "DISP0_RESET_N", + "DISP1_RESET_N", + "ETH_RESET", + "RCM_MARKER2", + "CAM_DC_MIPI_MUX_EN", + "CAM_DC_MIPI_MUX_SEL", + "AFC_PHY_TA_D_PLUS", /* GPIO_30 */ + "AFC_PHY_TA_D_MINUS", + "PM8008_1_IRQ", + "PM8008_1_RESET_N", + "PM8008_2_IRQ", + "PM8008_2_RESET_N", + "CAM_DC_I3C_SDA", + "CAM_DC_I3C_SCL", + "FP_INT_N", + "FP_WUHB_INT_N", + "SMB_SPMI_DATA", /* GPIO_40 */ + "SMB_SPMI_CLK", + "USB_HUB_RESET", + "FORCE_USB_BOOT", + "LRF_IRQ", + "NC", + "IMU2_INT", + "HDMI_3P3_EN", + "HDMI_RSTN", + "HDMI_1P2_EN", + "HDMI_INT", /* GPIO_50 */ + "USB1_ID", + "FP_SPI_MISO", + "FP_SPI_MOSI", + "FP_SPI_CLK", + "FP_SPI_CS_N", + "NFC_ESE_SPI_MISO", + "NFC_ESE_SPI_MOSI", + "NFC_ESE_SPI_CLK", + "NFC_ESE_SPI_CS", + "NFC_I2C_SDA", /* GPIO_60 */ + "NFC_I2C_SCLC", + "NFC_EN", + "NFC_CLK_REQ", + "HST_WLAN_EN", + "HST_BT_EN", + "HST_SW_CTRL", + "NC", + "HST_BT_UART_CTS", + "HST_BT_UART_RFR", + "HST_BT_UART_TX", /* GPIO_70 */ + "HST_BT_UART_RX", + "CAM_DC_SPI0_MISO", + "CAM_DC_SPI0_MOSI", + "CAM_DC_SPI0_CLK", + "CAM_DC_SPI0_CS_N", + "CAM_DC_SPI1_MISO", + "CAM_DC_SPI1_MOSI", + "CAM_DC_SPI1_CLK", + "CAM_DC_SPI1_CS_N", + "HALL_INT_N", /* GPIO_80 */ + "USB_PHY_PS", + "MDP_VSYNC_P", + "MDP_VSYNC_S", + "ETH_3P3_EN", + "RADAR_INT", + "NFC_DWL_REQ", + "SM_GPIO_87", + "WCD_RESET_N", + "ALSP_INT_N", + "PRESS_INT", /* GPIO_90 */ + "SAR_INT_N", + "SD_CARD_DET_N", + "NC", + "PCIE0_RESET_N", + "PCIE0_CLK_REQ_N", + "PCIE0_WAKE_N", + "PCIE1_RESET_N", + "PCIE1_CLK_REQ_N", + "PCIE1_WAKE_N", + "CAM_MCLK0", /* GPIO_100 */ + "CAM_MCLK1", + "CAM_MCLK2", + "CAM_MCLK3", + "CAM_MCLK4", + "CAM_MCLK5", + "CAM2_RESET_N", + "CCI_I2C0_SDA", + "CCI_I2C0_SCL", + "CCI_I2C1_SDA", + "CCI_I2C1_SCL", /* GPIO_110 */ + "CCI_I2C2_SDA", + "CCI_I2C2_SCL", + "CCI_I2C3_SDA", + "CCI_I2C3_SCL", + "CAM5_RESET_N", + "CAM4_RESET_N", + "CAM3_RESET_N", + "IMU1_INT", + "MAG_INT_N", + "MI2S2_I2S_SCK", /* GPIO_120 */ + "MI2S2_I2S_DAT0", + "MI2S2_I2S_WS", + "HIFI_DAC_I2S_MCLK", + "MI2S2_I2S_DAT1", + "HIFI_DAC_I2S_SCK", + "HIFI_DAC_I2S_DAT0", + "NC", + "HIFI_DAC_I2S_WS", + "HST_BT_WLAN_SLIMBUS_CLK", + "HST_BT_WLAN_SLIMBUS_DAT0", /* GPIO_130 */ + "BT_LED_EN", + "WLAN_LED_EN", + "NC", + "NC", + "NC", + "UIM2_PRESENT", + "NC", + "NC", + "NC", + "UIM1_PRESENT", /* GPIO_140 */ + "NC", + "SM_RFFE0_DATA", + "NC", + "SM_RFFE1_DATA", + "SM_MSS_GRFC4", + "SM_MSS_GRFC5", + "SM_MSS_GRFC6", + "SM_MSS_GRFC7", + "SM_RFFE4_CLK", + "SM_RFFE4_DATA", /* GPIO_150 */ + "WLAN_COEX_UART1_RX", + "WLAN_COEX_UART1_TX", + "HST_SW_CTRL", + "DSI0_STATUS", + "DSI1_STATUS", + "APPS_PBL_BOOT_SPEED_1", + "APPS_BOOT_FROM_ROM", + "APPS_PBL_BOOT_SPEED_0", + "QLINK0_REQ", + "QLINK0_EN", /* GPIO_160 */ + "QLINK0_WMSS_RESET_N", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "WCD_SWR_TX_CLK", + "WCD_SWR_TX_DATA0", + "WCD_SWR_TX_DATA1", /* GPIO_170 */ + "WCD_SWR_RX_CLK", + "WCD_SWR_RX_DATA0", + "WCD_SWR_RX_DATA1", + "DMIC01_CLK", + "DMIC01_DATA", + "DMIC23_CLK", + "DMIC23_DATA", + "WSA_SWR_CLK", + "WSA_SWR_DATA", + "DMIC45_CLK", /* GPIO_180 */ + "DMIC45_DATA", + "WCD_SWR_TX_DATA2", + "SENSOR_I3C_SDA", + "SENSOR_I3C_SCL", + "CAM_OIS0_I3C_SDA", + "CAM_OIS0_I3C_SCL", + "IMU_SPI_MISO", + "IMU_SPI_MOSI", + "IMU_SPI_CLK", + "IMU_SPI_CS_N", /* GPIO_190 */ + "MAG_I2C_SDA", + "MAG_I2C_SCL", + "SENSOR_I2C_SDA", + "SENSOR_I2C_SCL", + "RADAR_SPI_MISO", + "RADAR_SPI_MOSI", + "RADAR_SPI_CLK", + "RADAR_SPI_CS_N", + "HST_BLE_UART_TX", + "HST_BLE_UART_RX", /* GPIO_200 */ + "HST_WLAN_UART_TX", + "HST_WLAN_UART_RX"; + + pcie0_default_state: pcie0-default-state { + perst-pins { + pins = "gpio94"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + clkreq-pins { + pins = "gpio95"; + function = "pcie0_clkreqn"; + drive-strength = <2>; + bias-pull-up; + }; + + wake-pins { + pins = "gpio96"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie1_default_state: pcie1-default-state { + perst-pins { + pins = "gpio97"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + clkreq-pins { + pins = "gpio98"; + function = "pcie1_clkreqn"; + drive-strength = <2>; + bias-pull-up; + }; + + wake-pins { + pins = "gpio99"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; &uart2 { @@ -325,4 +729,20 @@ drive-strength = <2>; output-low; }; + + lt9611_state: lt9611-state { + rst-pins { + pins = "gpio48"; + function = "gpio"; + + output-high; + input-disable; + }; + + irq-pins { + pins = "gpio50"; + function = "gpio"; + bias-disable; + }; + }; }; diff --git a/arch/arm64/boot/dts/qcom/sm8350-microsoft-surface-duo2.dts b/arch/arm64/boot/dts/qcom/sm8350-microsoft-surface-duo2.dts index 9c4cfd995ff2..b536ae36ae6d 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-microsoft-surface-duo2.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-microsoft-surface-duo2.dts @@ -44,7 +44,7 @@ }; &apps_rsc { - pm8350-rpmh-regulators { + regulators-0 { compatible = "qcom,pm8350-rpmh-regulators"; qcom,pmic-id = "b"; @@ -135,7 +135,7 @@ }; }; - pm8350c-rpmh-regulators { + regulators-1 { compatible = "qcom,pm8350c-rpmh-regulators"; qcom,pmic-id = "c"; @@ -290,9 +290,9 @@ }; &ipa { - status = "okay"; - + qcom,gsi-loader = "self"; memory-region = <&pil_ipa_fw_mem>; + status = "okay"; }; &mpss { diff --git a/arch/arm64/boot/dts/qcom/sm8350-mtp.dts b/arch/arm64/boot/dts/qcom/sm8350-mtp.dts index 52cf3045602f..d21d2aacf201 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-mtp.dts @@ -43,7 +43,7 @@ }; &apps_rsc { - pm8350-rpmh-regulators { + regulators-0 { compatible = "qcom,pm8350-rpmh-regulators"; qcom,pmic-id = "b"; @@ -134,7 +134,7 @@ }; }; - pm8350c-rpmh-regulators { + regulators-1 { compatible = "qcom,pm8350c-rpmh-regulators"; qcom,pmic-id = "c"; @@ -376,7 +376,7 @@ }; &ipa { - status = "okay"; - + qcom,gsi-loader = "self"; memory-region = <&pil_ipa_fw_mem>; + status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami-pdx214.dts b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami-pdx214.dts index cc650508dc2d..e6824c8c2774 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami-pdx214.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami-pdx214.dts @@ -17,3 +17,26 @@ height = <2520>; stride = <(1080 * 4)>; }; + +&pm8350b_gpios { + gpio-line-names = "NC", /* GPIO_1 */ + "NC", + "NC", + "NC", + "SNAPSHOT_N", + "NC", + "NC", + "FOCUS_N"; +}; + +&pm8350c_gpios { + gpio-line-names = "FL_STROBE_TRIG_WIDE", /* GPIO_1 */ + "FL_STROBE_TRIG_TELE", + "NC", + "NC", + "NC", + "RGBC_IR_PWR_EN", + "NC", + "NC", + "WIDEC_PWR_EN"; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami-pdx215.dts b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami-pdx215.dts index c74c973a69d2..c6f402c3ef35 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami-pdx215.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami-pdx215.dts @@ -12,6 +12,93 @@ compatible = "sony,pdx215-generic", "qcom,sm8350"; }; +&i2c13 { + pmic@75 { + compatible = "dlg,slg51000"; + reg = <0x75>; + dlg,cs-gpios = <&pm8350b_gpios 1 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&cam_pwr_a_cs>; + + regulators { + slg51000_a_ldo1: ldo1 { + regulator-name = "slg51000_a_ldo1"; + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3300000>; + }; + + slg51000_a_ldo2: ldo2 { + regulator-name = "slg51000_a_ldo2"; + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3300000>; + }; + + slg51000_a_ldo3: ldo3 { + regulator-name = "slg51000_a_ldo3"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3750000>; + }; + + slg51000_a_ldo4: ldo4 { + regulator-name = "slg51000_a_ldo4"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3750000>; + }; + + slg51000_a_ldo5: ldo5 { + regulator-name = "slg51000_a_ldo5"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1200000>; + }; + + slg51000_a_ldo6: ldo6 { + regulator-name = "slg51000_a_ldo6"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1200000>; + }; + + slg51000_a_ldo7: ldo7 { + regulator-name = "slg51000_a_ldo7"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3750000>; + }; + }; + }; +}; + +&pm8350b_gpios { + gpio-line-names = "CAM_PWR_A_CS", /* GPIO_1 */ + "NC", + "NC", + "NC", + "SNAPSHOT_N", + "CAM_PWR_LD_EN", + "NC", + "FOCUS_N"; + + cam_pwr_a_cs: cam-pwr-a-cs-state { + pins = "gpio1"; + function = "normal"; + qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>; + power-source = <1>; + drive-push-pull; + output-high; + }; +}; + +&pm8350c_gpios { + gpio-line-names = "FL_STROBE_TRIG_WIDE", /* GPIO_1 */ + "FL_STROBE_TRIG_TELE", + "NC", + "WLC_TXPWR_EN", + "NC", + "RGBC_IR_PWR_EN", + "NC", + "NC", + "WIDEC_PWR_EN"; +}; + &tlmm { gpio-line-names = "APPS_I2C_0_SDA", /* GPIO_0 */ "APPS_I2C_0_SCL", diff --git a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi index 1f2d660f8f86..89382ad73133 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi @@ -3,6 +3,7 @@ * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org> */ +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> #include <dt-bindings/regulator/qcom,rpmh-regulator.h> #include "sm8350.dtsi" #include "pm8350.dtsi" @@ -48,7 +49,35 @@ gpio-keys { compatible = "gpio-keys"; - /* For reasons still unknown, GAssist key and Camera Focus/Shutter don't work.. */ + pinctrl-names = "default"; + pinctrl-0 = <&focus_n &snapshot_n &vol_down_n &g_assist_n>; + + key-camera-focus { + label = "Camera Focus"; + linux,code = <KEY_CAMERA_FOCUS>; + gpios = <&pm8350b_gpios 8 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + + key-camera-snapshot { + label = "Camera Snapshot"; + linux,code = <KEY_CAMERA>; + gpios = <&pm8350b_gpios 5 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + + key-google-assist { + label = "Google Assistant Key"; + gpios = <&pm8350_gpios 9 GPIO_ACTIVE_LOW>; + linux,code = <KEY_LEFTMETA>; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; key-vol-down { label = "Volume Down"; @@ -56,7 +85,7 @@ gpios = <&pmk8350_gpios 3 GPIO_ACTIVE_LOW>; debounce-interval = <15>; linux,can-disable; - gpio-key,wakeup; + wakeup-source; }; }; @@ -171,6 +200,8 @@ regulator-max-microvolt = <888000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; }; pm8350_l6: ldo6 { @@ -179,6 +210,8 @@ regulator-max-microvolt = <1208000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; }; pm8350_l7: ldo7 { @@ -187,6 +220,8 @@ regulator-max-microvolt = <3008000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; }; /* L8 - lcx.lvl (ARC) */ @@ -197,6 +232,8 @@ regulator-max-microvolt = <1200000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; }; }; @@ -443,13 +480,6 @@ /* Some subset of SONY IMX663 camera sensor @ 38 */ }; -&i2c2 { - status = "okay"; - clock-frequency = <400000>; - - /* Richwave RTC6226 FM Radio Receiver @ 64 */ -}; - &i2c4 { status = "okay"; clock-frequency = <400000>; @@ -461,7 +491,7 @@ status = "okay"; clock-frequency = <1000000>; - cs35l41_l: cs35l41@40 { + cs35l41_l: speaker-amp@40 { compatible = "cirrus,cs35l41"; reg = <0x40>; interrupt-parent = <&tlmm>; @@ -476,7 +506,7 @@ #sound-dai-cells = <1>; }; - cs35l41_r: cs35l41@41 { + cs35l41_r: speaker-amp@41 { compatible = "cirrus,cs35l41"; reg = <0x41>; interrupt-parent = <&tlmm>; @@ -506,7 +536,6 @@ clock-frequency = <100000>; /* Qualcomm PM8008i/PM8008j (?) @ 8, 9, c, d */ - /* Dialog SLG51000 CMIC @ 75 */ }; &i2c15 { @@ -524,9 +553,10 @@ }; &ipa { - status = "okay"; + qcom,gsi-loader = "self"; memory-region = <&pil_ipa_fw_mem>; firmware-name = "qcom/sm8350/Sony/sagami/ipa_fws.mbn"; + status = "okay"; }; &mpss { @@ -534,6 +564,60 @@ firmware-name = "qcom/sm8350/Sony/sagami/modem.mbn"; }; +&pm8350_gpios { + gpio-line-names = "ASSIGN1_THERM", /* GPIO_1 */ + "LCD_ID", + "SDR_MMW_THERM", + "RF_ID", + "NC", + "FP_LDO_EN", + "SP_ARI_PWR_ALARM", + "NC", + "G_ASSIST_N", + "PM8350_OPTION"; /* GPIO_10 */ + + g_assist_n: g-assist-n-state { + pins = "gpio9"; + function = "normal"; + power-source = <1>; + bias-pull-up; + input-enable; + }; +}; + +&pm8350b_gpios { + snapshot_n: snapshot-n-state { + pins = "gpio5"; + function = "normal"; + power-source = <0>; + bias-pull-up; + input-enable; + }; + + focus_n: focus-n-state { + pins = "gpio8"; + function = "normal"; + power-source = <0>; + input-enable; + bias-pull-up; + }; +}; + +&pmk8350_gpios { + gpio-line-names = "NC", /* GPIO_1 */ + "NC", + "VOL_DOWN_N", + "PMK8350_OPTION"; + + vol_down_n: vol-down-n-state { + pins = "gpio3"; + function = "normal"; + power-source = <0>; + bias-pull-up; + input-enable; + }; +}; + &pmk8350_rtc { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 245dce24ec59..1c97e28da6ad 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -3,9 +3,11 @@ * Copyright (c) 2020, Linaro Limited */ +#include <dt-bindings/interconnect/qcom,sm8350.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/qcom,dispcc-sm8350.h> #include <dt-bindings/clock/qcom,gcc-sm8350.h> +#include <dt-bindings/clock/qcom,gpucc-sm8350.h> #include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/dma/qcom-gpi.h> #include <dt-bindings/gpio/gpio.h> @@ -37,24 +39,6 @@ clock-frequency = <32000>; #clock-cells = <0>; }; - - ufs_phy_rx_symbol_0_clk: ufs-phy-rx-symbol-0 { - compatible = "fixed-clock"; - clock-frequency = <1000>; - #clock-cells = <0>; - }; - - ufs_phy_rx_symbol_1_clk: ufs-phy-rx-symbol-1 { - compatible = "fixed-clock"; - clock-frequency = <1000>; - #clock-cells = <0>; - }; - - ufs_phy_tx_symbol_0_clk: ufs-phy-tx-symbol-0 { - compatible = "fixed-clock"; - clock-frequency = <1000>; - #clock-cells = <0>; - }; }; cpus { @@ -73,9 +57,11 @@ #cooling-cells = <2>; L2_0: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; L3_0: l3-cache { compatible = "cache"; + cache-level = <3>; }; }; }; @@ -92,6 +78,7 @@ #cooling-cells = <2>; L2_100: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -108,6 +95,7 @@ #cooling-cells = <2>; L2_200: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -124,6 +112,7 @@ #cooling-cells = <2>; L2_300: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -140,6 +129,7 @@ #cooling-cells = <2>; L2_400: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -156,6 +146,7 @@ #cooling-cells = <2>; L2_500: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; @@ -173,6 +164,7 @@ #cooling-cells = <2>; L2_600: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -189,6 +181,7 @@ #cooling-cells = <2>; L2_700: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -288,55 +281,55 @@ compatible = "arm,psci-1.0"; method = "smc"; - CPU_PD0: cpu0 { + CPU_PD0: power-domain-cpu0 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&LITTLE_CPU_SLEEP_0>; }; - CPU_PD1: cpu1 { + CPU_PD1: power-domain-cpu1 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&LITTLE_CPU_SLEEP_0>; }; - CPU_PD2: cpu2 { + CPU_PD2: power-domain-cpu2 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&LITTLE_CPU_SLEEP_0>; }; - CPU_PD3: cpu3 { + CPU_PD3: power-domain-cpu3 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&LITTLE_CPU_SLEEP_0>; }; - CPU_PD4: cpu4 { + CPU_PD4: power-domain-cpu4 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&BIG_CPU_SLEEP_0>; }; - CPU_PD5: cpu5 { + CPU_PD5: power-domain-cpu5 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&BIG_CPU_SLEEP_0>; }; - CPU_PD6: cpu6 { + CPU_PD6: power-domain-cpu6 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&BIG_CPU_SLEEP_0>; }; - CPU_PD7: cpu7 { + CPU_PD7: power-domain-cpu7 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&BIG_CPU_SLEEP_0>; }; - CLUSTER_PD: cpu-cluster0 { + CLUSTER_PD: power-domain-cpu-cluster0 { #power-domain-cells = <0>; domain-idle-states = <&CLUSTER_SLEEP_0>; }; @@ -406,8 +399,10 @@ no-map; }; - smem_mem: memory@80900000 { + smem@80900000 { + compatible = "qcom,smem"; reg = <0x0 0x80900000 0x0 0x200000>; + hwlocks = <&tcsr_mutex 3>; no-map; }; @@ -516,12 +511,6 @@ }; }; - smem: qcom,smem { - compatible = "qcom,smem"; - memory-region = <&smem_mem>; - hwlocks = <&tcsr_mutex 3>; - }; - smp2p-adsp { compatible = "qcom,smp2p"; qcom,smem = <443>, <429>; @@ -656,14 +645,14 @@ "usb3_uni_phy_sec_gcc_usb30_pipe_clk"; clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, + <&pcie0_phy>, + <&pcie1_phy>, <0>, <0>, <0>, - <0>, - <0>, - <&ufs_phy_rx_symbol_0_clk>, - <&ufs_phy_rx_symbol_1_clk>, - <&ufs_phy_tx_symbol_0_clk>, + <&ufs_mem_phy_lanes 0>, + <&ufs_mem_phy_lanes 1>, + <&ufs_mem_phy_lanes 2>, <0>, <0>; }; @@ -1043,8 +1032,6 @@ interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; - #address-cells = <1>; - #size-cells = <0>; status = "disabled"; }; @@ -1435,165 +1422,303 @@ }; }; - apps_smmu: iommu@15000000 { - compatible = "qcom,sm8350-smmu-500", "arm,mmu-500"; - reg = <0 0x15000000 0 0x100000>; - #iommu-cells = <2>; - #global-interrupts = <2>; - interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>; + rng: rng@10d3000 { + compatible = "qcom,prng-ee"; + reg = <0 0x010d3000 0 0x1000>; + clocks = <&rpmhcc RPMH_HWKM_CLK>; + clock-names = "core"; }; config_noc: interconnect@1500000 { compatible = "qcom,sm8350-config-noc"; reg = <0 0x01500000 0 0xa580>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; mc_virt: interconnect@1580000 { compatible = "qcom,sm8350-mc-virt"; reg = <0 0x01580000 0 0x1000>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; system_noc: interconnect@1680000 { compatible = "qcom,sm8350-system-noc"; reg = <0 0x01680000 0 0x1c200>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; aggre1_noc: interconnect@16e0000 { compatible = "qcom,sm8350-aggre1-noc"; reg = <0 0x016e0000 0 0x1f180>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; aggre2_noc: interconnect@1700000 { compatible = "qcom,sm8350-aggre2-noc"; reg = <0 0x01700000 0 0x33000>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; mmss_noc: interconnect@1740000 { compatible = "qcom,sm8350-mmss-noc"; reg = <0 0x01740000 0 0x1f080>; - #interconnect-cells = <1>; + #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; - lpass_ag_noc: interconnect@3c40000 { - compatible = "qcom,sm8350-lpass-ag-noc"; - reg = <0 0x03c40000 0 0xf080>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; + pcie0: pci@1c00000 { + compatible = "qcom,pcie-sm8350"; + reg = <0 0x01c00000 0 0x3000>, + <0 0x60000000 0 0xf1d>, + <0 0x60000f20 0 0xa8>, + <0 0x60001000 0 0x1000>, + <0 0x60100000 0 0x100000>; + reg-names = "parf", "dbi", "elbi", "atu", "config"; + device_type = "pci"; + linux,pci-domain = <0>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; + + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "tbu", + "ddrss_sf_tbu", + "aggre1", + "aggre0"; + + iommus = <&apps_smmu 0x1c00 0x7f>; + iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, + <0x100 &apps_smmu 0x1c01 0x1>; + + resets = <&gcc GCC_PCIE_0_BCR>; + reset-names = "pci"; + + power-domains = <&gcc PCIE_0_GDSC>; + + phys = <&pcie0_phy>; + phy-names = "pciephy"; + + status = "disabled"; }; - compute_noc: interconnect@a0c0000{ - compatible = "qcom,sm8350-compute-noc"; - reg = <0 0x0a0c0000 0 0xa180>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; + pcie0_phy: phy@1c06000 { + compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy"; + reg = <0 0x01c06000 0 0x2000>; + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_CLKREF_EN>, + <&gcc GCC_PCIE0_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_0_PIPE_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe"; + + resets = <&gcc GCC_PCIE_0_PHY_BCR>; + reset-names = "phy"; + + assigned-clocks = <&gcc GCC_PCIE0_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + #clock-cells = <0>; + clock-output-names = "pcie_0_pipe_clk"; + + #phy-cells = <0>; + + status = "disabled"; + }; + + pcie1: pci@1c08000 { + compatible = "qcom,pcie-sm8350"; + reg = <0 0x01c08000 0 0x3000>, + <0 0x40000000 0 0xf1d>, + <0 0x40000f20 0 0xa8>, + <0 0x40001000 0 0x1000>, + <0 0x40100000 0 0x100000>; + reg-names = "parf", "dbi", "elbi", "atu", "config"; + device_type = "pci"; + linux,pci-domain = <1>; + bus-range = <0x00 0xff>; + num-lanes = <2>; + + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x01000000 0x0 0x40200000 0 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0 0x40300000 0x0 0x1fd00000>; + + interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks = <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "tbu", + "ddrss_sf_tbu", + "aggre1"; + + iommus = <&apps_smmu 0x1c80 0x7f>; + iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, + <0x100 &apps_smmu 0x1c81 0x1>; + + resets = <&gcc GCC_PCIE_1_BCR>; + reset-names = "pci"; + + power-domains = <&gcc PCIE_1_GDSC>; + + phys = <&pcie1_phy>; + phy-names = "pciephy"; + + status = "disabled"; + }; + + pcie1_phy: phy@1c0f000 { + compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy"; + reg = <0 0x01c0e000 0 0x2000>; + clocks = <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_CLKREF_EN>, + <&gcc GCC_PCIE1_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_1_PIPE_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe"; + + resets = <&gcc GCC_PCIE_1_PHY_BCR>; + reset-names = "phy"; + + assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + #clock-cells = <0>; + clock-output-names = "pcie_1_pipe_clk"; + + #phy-cells = <0>; + + status = "disabled"; + }; + + ufs_mem_hc: ufshc@1d84000 { + compatible = "qcom,sm8350-ufshc", "qcom,ufshc", + "jedec,ufs-2.0"; + reg = <0 0x01d84000 0 0x3000>; + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; + phys = <&ufs_mem_phy_lanes>; + phy-names = "ufsphy"; + lanes-per-direction = <2>; + #reset-cells = <1>; + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + power-domains = <&gcc UFS_PHY_GDSC>; + + iommus = <&apps_smmu 0xe0 0x0>; + + clock-names = + "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + clocks = + <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + freq-table-hz = + <75000000 300000000>, + <0 0>, + <0 0>, + <75000000 300000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>; + status = "disabled"; + }; + + ufs_mem_phy: phy@1d87000 { + compatible = "qcom,sm8350-qmp-ufs-phy"; + reg = <0 0x01d87000 0 0x1c4>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clock-names = "ref", + "ref_aux"; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + + resets = <&ufs_mem_hc 0>; + reset-names = "ufsphy"; + status = "disabled"; + + ufs_mem_phy_lanes: phy@1d87400 { + reg = <0 0x01d87400 0 0x188>, + <0 0x01d87600 0 0x200>, + <0 0x01d87c00 0 0x200>, + <0 0x01d87800 0 0x188>, + <0 0x01d87a00 0 0x200>; + #clock-cells = <1>; + #phy-cells = <0>; + }; }; ipa: ipa@1e40000 { @@ -1601,9 +1726,9 @@ iommus = <&apps_smmu 0x5c0 0x0>, <&apps_smmu 0x5c2 0x0>; - reg = <0 0x1e40000 0 0x8000>, - <0 0x1e50000 0 0x4b20>, - <0 0x1e04000 0 0x23000>; + reg = <0 0x01e40000 0 0x8000>, + <0 0x01e50000 0 0x4b20>, + <0 0x01e04000 0 0x23000>; reg-names = "ipa-reg", "ipa-shared", "gsi"; @@ -1620,8 +1745,8 @@ clocks = <&rpmhcc RPMH_IPA_CLK>; clock-names = "core"; - interconnects = <&aggre2_noc MASTER_IPA &mc_virt SLAVE_EBI1>, - <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_IPA_CFG>; + interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; interconnect-names = "memory", "config"; @@ -1641,6 +1766,190 @@ #hwlock-cells = <1>; }; + gpu: gpu@3d00000 { + compatible = "qcom,adreno-660.1", "qcom,adreno"; + + reg = <0 0x03d00000 0 0x40000>, + <0 0x03d9e000 0 0x1000>, + <0 0x03d61000 0 0x800>; + reg-names = "kgsl_3d0_reg_memory", + "cx_mem", + "cx_dbgc"; + + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; + + iommus = <&adreno_smmu 0 0x400>, <&adreno_smmu 1 0x400>; + + operating-points-v2 = <&gpu_opp_table>; + + qcom,gmu = <&gmu>; + + status = "disabled"; + + zap-shader { + memory-region = <&pil_gpu_mem>; + }; + + /* note: downstream checks gpu binning for 670 Mhz */ + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-840000000 { + opp-hz = /bits/ 64 <840000000>; + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; + }; + + opp-778000000 { + opp-hz = /bits/ 64 <778000000>; + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; + }; + + opp-738000000 { + opp-hz = /bits/ 64 <738000000>; + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; + }; + + opp-676000000 { + opp-hz = /bits/ 64 <676000000>; + opp-level = <RPMH_REGULATOR_LEVEL_NOM>; + }; + + opp-608000000 { + opp-hz = /bits/ 64 <608000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; + }; + + opp-491000000 { + opp-hz = /bits/ 64 <491000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; + }; + + opp-443000000 { + opp-hz = /bits/ 64 <443000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS>; + }; + + opp-379000000 { + opp-hz = /bits/ 64 <379000000>; + opp-level = <80 /* RPMH_REGULATOR_LEVEL_LOW_SVS_L1 */>; + }; + + opp-315000000 { + opp-hz = /bits/ 64 <315000000>; + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; + }; + }; + }; + + gmu: gmu@3d6a000 { + compatible = "qcom,adreno-gmu-660.1", "qcom,adreno-gmu"; + + reg = <0 0x03d6a000 0 0x34000>, + <0 0x03de0000 0 0x10000>, + <0 0x0b290000 0 0x10000>; + reg-names = "gmu", "rscc", "gmu_pdc"; + + interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hfi", "gmu"; + + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; + clock-names = "gmu", + "cxo", + "axi", + "memnoc", + "ahb", + "hub", + "smmu_vote"; + + power-domains = <&gpucc GPU_CX_GDSC>, + <&gpucc GPU_GX_GDSC>; + power-domain-names = "cx", + "gx"; + + iommus = <&adreno_smmu 5 0x400>; + + operating-points-v2 = <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; + }; + }; + }; + + gpucc: clock-controller@3d90000 { + compatible = "qcom,sm8350-gpucc"; + reg = <0 0x03d90000 0 0x9000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + clock-names = "bi_tcxo", + "gcc_gpu_gpll0_clk_src", + "gcc_gpu_gpll0_div_clk_src"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + adreno_smmu: iommu@3da0000 { + compatible = "qcom,sm8350-smmu-500", "qcom,adreno-smmu", "arm,mmu-500"; + reg = <0 0x03da0000 0 0x20000>; + #iommu-cells = <2>; + #global-interrupts = <2>; + interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_HUB_AON_CLK>; + clock-names = "bus", + "iface", + "ahb", + "hlos1_vote_gpu_smmu", + "cx_gmu", + "hub_cx_int", + "hub_aon"; + + power-domains = <&gpucc GPU_CX_GDSC>; + dma-coherent; + }; + + lpass_ag_noc: interconnect@3c40000 { + compatible = "qcom,sm8350-lpass-ag-noc"; + reg = <0 0x03c40000 0 0xf080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + mpss: remoteproc@4080000 { compatible = "qcom,sm8350-mpss-pas"; reg = <0x0 0x04080000 0x0 0x4040>; @@ -1661,7 +1970,7 @@ <&rpmhpd SM8350_MSS>; power-domain-names = "cx", "mss"; - interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; + interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; memory-region = <&pil_modem_mem>; @@ -1683,6 +1992,653 @@ }; }; + slpi: remoteproc@5c00000 { + compatible = "qcom,sm8350-slpi-pas"; + reg = <0 0x05c00000 0 0x4000>; + + interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, + <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd SM8350_LCX>, + <&rpmhpd SM8350_LMX>; + power-domain-names = "lcx", "lmx"; + + memory-region = <&pil_slpi_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_slpi_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_SLPI + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_SLPI + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "slpi"; + qcom,remote-pid = <3>; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "sdsp"; + qcom,non-secure-domain; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <1>; + iommus = <&apps_smmu 0x0541 0x0>; + }; + + compute-cb@2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <2>; + iommus = <&apps_smmu 0x0542 0x0>; + }; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x0543 0x0>; + /* note: shared-cb = <4> in downstream */ + }; + }; + }; + }; + + sdhc_2: mmc@8804000 { + compatible = "qcom,sm8350-sdhci", "qcom,sdhci-msm-v5"; + reg = <0 0x08804000 0 0x1000>; + + interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "core", "xo"; + resets = <&gcc GCC_SDCC2_BCR>; + interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; + interconnect-names = "sdhc-ddr","cpu-sdhc"; + iommus = <&apps_smmu 0x4a0 0x0>; + power-domains = <&rpmhpd SM8350_CX>; + operating-points-v2 = <&sdhc2_opp_table>; + bus-width = <4>; + dma-coherent; + + status = "disabled"; + + sdhc2_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-202000000 { + opp-hz = /bits/ 64 <202000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + usb_1_hsphy: phy@88e3000 { + compatible = "qcom,sm8350-usb-hs-phy", + "qcom,usb-snps-hs-7nm-phy"; + reg = <0 0x088e3000 0 0x400>; + status = "disabled"; + #phy-cells = <0>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + }; + + usb_2_hsphy: phy@88e4000 { + compatible = "qcom,sm8250-usb-hs-phy", + "qcom,usb-snps-hs-7nm-phy"; + reg = <0 0x088e4000 0 0x400>; + status = "disabled"; + #phy-cells = <0>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; + }; + + usb_1_qmpphy: phy-wrapper@88e9000 { + compatible = "qcom,sm8350-qmp-usb3-phy"; + reg = <0 0x088e9000 0 0x200>, + <0 0x088e8000 0 0x20>; + status = "disabled"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; + clock-names = "aux", "ref_clk_src", "com_aux"; + + resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, + <&gcc GCC_USB3_PHY_PRIM_BCR>; + reset-names = "phy", "common"; + + usb_1_ssphy: phy@88e9200 { + reg = <0 0x088e9200 0 0x200>, + <0 0x088e9400 0 0x200>, + <0 0x088e9c00 0 0x400>, + <0 0x088e9600 0 0x200>, + <0 0x088e9800 0 0x200>, + <0 0x088e9a00 0 0x100>; + #phy-cells = <0>; + #clock-cells = <0>; + clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "pipe0"; + clock-output-names = "usb3_phy_pipe_clk_src"; + }; + }; + + usb_2_qmpphy: phy-wrapper@88eb000 { + compatible = "qcom,sm8350-qmp-usb3-uni-phy"; + reg = <0 0x088eb000 0 0x200>; + status = "disabled"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_SEC_CLKREF_EN>, + <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; + clock-names = "aux", "ref_clk_src", "ref", "com_aux"; + + resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, + <&gcc GCC_USB3_PHY_SEC_BCR>; + reset-names = "phy", "common"; + + usb_2_ssphy: phy@88ebe00 { + reg = <0 0x088ebe00 0 0x200>, + <0 0x088ec000 0 0x200>, + <0 0x088eb200 0 0x1100>; + #phy-cells = <0>; + #clock-cells = <0>; + clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; + clock-names = "pipe0"; + clock-output-names = "usb3_uni_phy_pipe_clk_src"; + }; + }; + + dc_noc: interconnect@90c0000 { + compatible = "qcom,sm8350-dc-noc"; + reg = <0 0x090c0000 0 0x4200>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + gem_noc: interconnect@9100000 { + compatible = "qcom,sm8350-gem-noc"; + reg = <0 0x09100000 0 0xb4000>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + system-cache-controller@9200000 { + compatible = "qcom,sm8350-llcc"; + reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>; + reg-names = "llcc_base", "llcc_broadcast_base"; + }; + + compute_noc: interconnect@a0c0000 { + compatible = "qcom,sm8350-compute-noc"; + reg = <0 0x0a0c0000 0 0xa180>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + usb_1: usb@a6f8800 { + compatible = "qcom,sm8350-dwc3", "qcom,dwc3"; + reg = <0 0x0a6f8800 0 0x400>; + status = "disabled"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi"; + + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + + interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 15 IRQ_TYPE_EDGE_BOTH>, + <&pdc 14 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "hs_phy_irq", + "ss_phy_irq", + "dm_hs_phy_irq", + "dp_hs_phy_irq"; + + power-domains = <&gcc USB30_PRIM_GDSC>; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + + usb_1_dwc3: usb@a600000 { + compatible = "snps,dwc3"; + reg = <0 0x0a600000 0 0xcd00>; + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; + iommus = <&apps_smmu 0x0 0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + phys = <&usb_1_hsphy>, <&usb_1_ssphy>; + phy-names = "usb2-phy", "usb3-phy"; + }; + }; + + usb_2: usb@a8f8800 { + compatible = "qcom,sm8350-dwc3", "qcom,dwc3"; + reg = <0 0x0a8f8800 0 0x400>; + status = "disabled"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, + <&gcc GCC_USB30_SEC_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, + <&gcc GCC_USB30_SEC_SLEEP_CLK>, + <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, + <&gcc GCC_USB3_SEC_CLKREF_EN>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "xo"; + + assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_SEC_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + + interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 16 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 13 IRQ_TYPE_EDGE_BOTH>, + <&pdc 12 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "hs_phy_irq", + "ss_phy_irq", + "dm_hs_phy_irq", + "dp_hs_phy_irq"; + + power-domains = <&gcc USB30_SEC_GDSC>; + + resets = <&gcc GCC_USB30_SEC_BCR>; + + usb_2_dwc3: usb@a800000 { + compatible = "snps,dwc3"; + reg = <0 0x0a800000 0 0xcd00>; + interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; + iommus = <&apps_smmu 0x20 0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + phys = <&usb_2_hsphy>, <&usb_2_ssphy>; + phy-names = "usb2-phy", "usb3-phy"; + }; + }; + + mdss: display-subsystem@ae00000 { + compatible = "qcom,sm8350-mdss"; + reg = <0 0x0ae00000 0 0x1000>; + reg-names = "mdss"; + + interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, + <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "mdp0-mem", "mdp1-mem"; + + power-domains = <&dispcc MDSS_GDSC>; + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "bus", "nrt_bus", "core"; + + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x820 0x402>; + + status = "disabled"; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + dpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + /* TODO: opp-200000000 should work with + * &rpmhpd_opp_low_svs, but one some of + * sm8350_hdk boards reboot using this + * opp. + */ + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-345000000 { + opp-hz = /bits/ 64 <345000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-460000000 { + opp-hz = /bits/ 64 <460000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + + mdss_mdp: display-controller@ae01000 { + compatible = "qcom,sm8350-dpu"; + reg = <0 0x0ae01000 0 0x8f000>, + <0 0x0aeb0000 0 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", + "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&dpu_opp_table>; + power-domains = <&rpmhpd SM8350_MMCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf2_out: endpoint { + remote-endpoint = <&mdss_dsi1_in>; + }; + }; + }; + }; + + mdss_dsi0: dsi@ae94000 { + compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae94000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>; + + operating-points-v2 = <&dsi0_opp_table>; + power-domains = <&rpmhpd SM8350_MMCX>; + + phys = <&mdss_dsi0_phy>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + dsi0_opp_table: opp-table { + compatible = "operating-points-v2"; + + /* TODO: opp-187500000 should work with + * &rpmhpd_opp_low_svs, but one some of + * sm8350_hdk boards reboot using this + * opp. + */ + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dsi0_out: endpoint { + }; + }; + }; + }; + + mdss_dsi0_phy: phy@ae94400 { + compatible = "qcom,sm8350-dsi-phy-5nm"; + reg = <0 0x0ae94400 0 0x200>, + <0 0x0ae94600 0 0x280>, + <0 0x0ae94900 0 0x27c>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + + mdss_dsi1: dsi@ae96000 { + compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae96000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <5>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi1_phy 0>, + <&mdss_dsi1_phy 1>; + + operating-points-v2 = <&dsi1_opp_table>; + power-domains = <&rpmhpd SM8350_MMCX>; + + phys = <&mdss_dsi1_phy>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + dsi1_opp_table: opp-table { + compatible = "operating-points-v2"; + + /* TODO: opp-187500000 should work with + * &rpmhpd_opp_low_svs, but one some of + * sm8350_hdk boards reboot using this + * opp. + */ + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dsi1_in: endpoint { + remote-endpoint = <&dpu_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dsi1_out: endpoint { + }; + }; + }; + }; + + mdss_dsi1_phy: phy@ae96400 { + compatible = "qcom,sm8350-dsi-phy-5nm"; + reg = <0 0x0ae96400 0 0x200>, + <0 0x0ae96600 0 0x280>, + <0 0x0ae96900 0 0x27c>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + }; + + dispcc: clock-controller@af00000 { + compatible = "qcom,sm8350-dispcc"; + reg = <0 0x0af00000 0 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>, + <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>, + <0>, + <0>; + clock-names = "bi_tcxo", + "dsi0_phy_pll_out_byteclk", + "dsi0_phy_pll_out_dsiclk", + "dsi1_phy_pll_out_byteclk", + "dsi1_phy_pll_out_dsiclk", + "dp_phy_pll_link_clk", + "dp_phy_pll_vco_div_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + + power-domains = <&rpmhpd SM8350_MMCX>; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sm8350-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; @@ -1717,7 +2673,7 @@ #thermal-sensor-cells = <1>; }; - aoss_qmp: power-controller@c300000 { + aoss_qmp: power-management@c300000 { compatible = "qcom,sm8350-aoss-qmp", "qcom,aoss-qmp"; reg = <0 0x0c300000 0 0x400>; interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP @@ -1734,11 +2690,11 @@ spmi_bus: spmi@c440000 { compatible = "qcom,spmi-pmic-arb"; - reg = <0x0 0xc440000 0x0 0x1100>, - <0x0 0xc600000 0x0 0x2000000>, - <0x0 0xe600000 0x0 0x100000>, - <0x0 0xe700000 0x0 0xa0000>, - <0x0 0xc40a000 0x0 0x26000>; + reg = <0x0 0x0c440000 0x0 0x1100>, + <0x0 0x0c600000 0x0 0x2000000>, + <0x0 0x0e600000 0x0 0x100000>, + <0x0 0x0e700000 0x0 0xa0000>, + <0x0 0x0c40a000 0x0 0x26000>; reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; interrupt-names = "periph_irq"; interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; @@ -1953,11 +2909,176 @@ }; }; - rng: rng@10d3000 { - compatible = "qcom,prng-ee"; - reg = <0 0x010d3000 0 0x1000>; - clocks = <&rpmhcc RPMH_HWKM_CLK>; - clock-names = "core"; + apps_smmu: iommu@15000000 { + compatible = "qcom,sm8350-smmu-500", "arm,mmu-500"; + reg = <0 0x15000000 0 0x100000>; + #iommu-cells = <2>; + #global-interrupts = <2>; + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>; + }; + + adsp: remoteproc@17300000 { + compatible = "qcom,sm8350-adsp-pas"; + reg = <0 0x17300000 0 0x100>; + + interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, + <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd SM8350_LCX>, + <&rpmhpd SM8350_LMX>; + power-domain-names = "lcx", "lmx"; + + memory-region = <&pil_adsp_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_adsp_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "lpass"; + qcom,remote-pid = <2>; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "adsp"; + qcom,non-secure-domain; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x1803 0x0>; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x1804 0x0>; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x1805 0x0>; + }; + }; + }; }; intc: interrupt-controller@17a00000 { @@ -2121,145 +3242,6 @@ #freq-domain-cells = <1>; }; - ufs_mem_hc: ufshc@1d84000 { - compatible = "qcom,sm8350-ufshc", "qcom,ufshc", - "jedec,ufs-2.0"; - reg = <0 0x01d84000 0 0x3000>; - interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; - phys = <&ufs_mem_phy_lanes>; - phy-names = "ufsphy"; - lanes-per-direction = <2>; - #reset-cells = <1>; - resets = <&gcc GCC_UFS_PHY_BCR>; - reset-names = "rst"; - - power-domains = <&gcc UFS_PHY_GDSC>; - - iommus = <&apps_smmu 0xe0 0x0>; - - clock-names = - "core_clk", - "bus_aggr_clk", - "iface_clk", - "core_clk_unipro", - "ref_clk", - "tx_lane0_sync_clk", - "rx_lane0_sync_clk", - "rx_lane1_sync_clk"; - clocks = - <&gcc GCC_UFS_PHY_AXI_CLK>, - <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, - <&gcc GCC_UFS_PHY_AHB_CLK>, - <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; - freq-table-hz = - <75000000 300000000>, - <0 0>, - <0 0>, - <75000000 300000000>, - <0 0>, - <0 0>, - <0 0>, - <0 0>; - status = "disabled"; - }; - - ufs_mem_phy: phy@1d87000 { - compatible = "qcom,sm8350-qmp-ufs-phy"; - reg = <0 0x01d87000 0 0x1c4>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - clock-names = "ref", - "ref_aux"; - clocks = <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; - - resets = <&ufs_mem_hc 0>; - reset-names = "ufsphy"; - status = "disabled"; - - ufs_mem_phy_lanes: phy@1d87400 { - reg = <0 0x01d87400 0 0x188>, - <0 0x01d87600 0 0x200>, - <0 0x01d87c00 0 0x200>, - <0 0x01d87800 0 0x188>, - <0 0x01d87a00 0 0x200>; - #phy-cells = <0>; - }; - }; - - slpi: remoteproc@5c00000 { - compatible = "qcom,sm8350-slpi-pas"; - reg = <0 0x05c00000 0 0x4000>; - - interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, - <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, - <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, - <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, - <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - power-domains = <&rpmhpd SM8350_LCX>, - <&rpmhpd SM8350_LMX>; - power-domain-names = "lcx", "lmx"; - - memory-region = <&pil_slpi_mem>; - - qcom,qmp = <&aoss_qmp>; - - qcom,smem-states = <&smp2p_slpi_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts-extended = <&ipcc IPCC_CLIENT_SLPI - IPCC_MPROC_SIGNAL_GLINK_QMP - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_SLPI - IPCC_MPROC_SIGNAL_GLINK_QMP>; - - label = "slpi"; - qcom,remote-pid = <3>; - - fastrpc { - compatible = "qcom,fastrpc"; - qcom,glink-channels = "fastrpcglink-apps-dsp"; - label = "sdsp"; - qcom,non-secure-domain; - #address-cells = <1>; - #size-cells = <0>; - - compute-cb@1 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <1>; - iommus = <&apps_smmu 0x0541 0x0>; - }; - - compute-cb@2 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <2>; - iommus = <&apps_smmu 0x0542 0x0>; - }; - - compute-cb@3 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <3>; - iommus = <&apps_smmu 0x0543 0x0>; - /* note: shared-cb = <4> in downstream */ - }; - }; - }; - }; - cdsp: remoteproc@98900000 { compatible = "qcom,sm8350-cdsp-pas"; reg = <0 0x98900000 0 0x1400000>; @@ -2279,7 +3261,7 @@ <&rpmhpd SM8350_MXC>; power-domain-names = "cx", "mxc"; - interconnects = <&compute_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>; + interconnects = <&compute_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; memory-region = <&pil_cdsp_mem>; @@ -2368,344 +3350,6 @@ }; }; }; - - sdhc_2: sdhci@8804000 { - compatible = "qcom,sm8350-sdhci", "qcom,sdhci-msm-v5"; - reg = <0 0x08804000 0 0x1000>; - - interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hc_irq", "pwr_irq"; - - clocks = <&gcc GCC_SDCC2_AHB_CLK>, - <&gcc GCC_SDCC2_APPS_CLK>, - <&rpmhcc RPMH_CXO_CLK>; - clock-names = "iface", "core", "xo"; - resets = <&gcc GCC_SDCC2_BCR>; - interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; - interconnect-names = "sdhc-ddr","cpu-sdhc"; - iommus = <&apps_smmu 0x4a0 0x0>; - power-domains = <&rpmhpd SM8350_CX>; - operating-points-v2 = <&sdhc2_opp_table>; - bus-width = <4>; - dma-coherent; - - status = "disabled"; - - sdhc2_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - - opp-202000000 { - opp-hz = /bits/ 64 <202000000>; - required-opps = <&rpmhpd_opp_svs_l1>; - }; - }; - }; - - usb_1_hsphy: phy@88e3000 { - compatible = "qcom,sm8350-usb-hs-phy", - "qcom,usb-snps-hs-7nm-phy"; - reg = <0 0x088e3000 0 0x400>; - status = "disabled"; - #phy-cells = <0>; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "ref"; - - resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; - }; - - usb_2_hsphy: phy@88e4000 { - compatible = "qcom,sm8250-usb-hs-phy", - "qcom,usb-snps-hs-7nm-phy"; - reg = <0 0x088e4000 0 0x400>; - status = "disabled"; - #phy-cells = <0>; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "ref"; - - resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; - }; - - usb_1_qmpphy: phy-wrapper@88e9000 { - compatible = "qcom,sm8350-qmp-usb3-phy"; - reg = <0 0x088e9000 0 0x200>, - <0 0x088e8000 0 0x20>; - status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; - clock-names = "aux", "ref_clk_src", "com_aux"; - - resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, - <&gcc GCC_USB3_PHY_PRIM_BCR>; - reset-names = "phy", "common"; - - usb_1_ssphy: phy@88e9200 { - reg = <0 0x088e9200 0 0x200>, - <0 0x088e9400 0 0x200>, - <0 0x088e9c00 0 0x400>, - <0 0x088e9600 0 0x200>, - <0 0x088e9800 0 0x200>, - <0 0x088e9a00 0 0x100>; - #phy-cells = <0>; - #clock-cells = <0>; - clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "usb3_phy_pipe_clk_src"; - }; - }; - - usb_2_qmpphy: phy-wrapper@88eb000 { - compatible = "qcom,sm8350-qmp-usb3-uni-phy"; - reg = <0 0x088eb000 0 0x200>; - status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_USB3_SEC_CLKREF_EN>, - <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; - clock-names = "aux", "ref_clk_src", "ref", "com_aux"; - - resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, - <&gcc GCC_USB3_PHY_SEC_BCR>; - reset-names = "phy", "common"; - - usb_2_ssphy: phy@88ebe00 { - reg = <0 0x088ebe00 0 0x200>, - <0 0x088ec000 0 0x200>, - <0 0x088eb200 0 0x1100>; - #phy-cells = <0>; - #clock-cells = <0>; - clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "usb3_uni_phy_pipe_clk_src"; - }; - }; - - dc_noc: interconnect@90c0000 { - compatible = "qcom,sm8350-dc-noc"; - reg = <0 0x090c0000 0 0x4200>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - gem_noc: interconnect@9100000 { - compatible = "qcom,sm8350-gem-noc"; - reg = <0 0x09100000 0 0xb4000>; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - system-cache-controller@9200000 { - compatible = "qcom,sm8350-llcc"; - reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>; - reg-names = "llcc_base", "llcc_broadcast_base"; - }; - - usb_1: usb@a6f8800 { - compatible = "qcom,sm8350-dwc3", "qcom,dwc3"; - reg = <0 0x0a6f8800 0 0x400>; - status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, - <&gcc GCC_USB30_PRIM_MASTER_CLK>, - <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, - <&gcc GCC_USB30_PRIM_SLEEP_CLK>, - <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; - clock-names = "cfg_noc", - "core", - "iface", - "sleep", - "mock_utmi"; - - assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_PRIM_MASTER_CLK>; - assigned-clock-rates = <19200000>, <200000000>; - - interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 15 IRQ_TYPE_EDGE_BOTH>, - <&pdc 14 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "hs_phy_irq", - "ss_phy_irq", - "dm_hs_phy_irq", - "dp_hs_phy_irq"; - - power-domains = <&gcc USB30_PRIM_GDSC>; - - resets = <&gcc GCC_USB30_PRIM_BCR>; - - usb_1_dwc3: usb@a600000 { - compatible = "snps,dwc3"; - reg = <0 0x0a600000 0 0xcd00>; - interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; - iommus = <&apps_smmu 0x0 0x0>; - snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; - phys = <&usb_1_hsphy>, <&usb_1_ssphy>; - phy-names = "usb2-phy", "usb3-phy"; - }; - }; - - usb_2: usb@a8f8800 { - compatible = "qcom,sm8350-dwc3", "qcom,dwc3"; - reg = <0 0x0a8f8800 0 0x400>; - status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, - <&gcc GCC_USB30_SEC_MASTER_CLK>, - <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, - <&gcc GCC_USB30_SEC_SLEEP_CLK>, - <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, - <&gcc GCC_USB3_SEC_CLKREF_EN>; - clock-names = "cfg_noc", - "core", - "iface", - "sleep", - "mock_utmi", - "xo"; - - assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_SEC_MASTER_CLK>; - assigned-clock-rates = <19200000>, <200000000>; - - interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 16 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 13 IRQ_TYPE_EDGE_BOTH>, - <&pdc 12 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "hs_phy_irq", - "ss_phy_irq", - "dm_hs_phy_irq", - "dp_hs_phy_irq"; - - power-domains = <&gcc USB30_SEC_GDSC>; - - resets = <&gcc GCC_USB30_SEC_BCR>; - - usb_2_dwc3: usb@a800000 { - compatible = "snps,dwc3"; - reg = <0 0x0a800000 0 0xcd00>; - interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; - iommus = <&apps_smmu 0x20 0x0>; - snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; - phys = <&usb_2_hsphy>, <&usb_2_ssphy>; - phy-names = "usb2-phy", "usb3-phy"; - }; - }; - - dispcc: clock-controller@af00000 { - compatible = "qcom,sm8350-dispcc"; - reg = <0 0x0af00000 0 0x10000>; - clocks = <&rpmhcc RPMH_CXO_CLK>, - <0>, - <0>, - <0>, - <0>, - <0>, - <0>; - clock-names = "bi_tcxo", - "dsi0_phy_pll_out_byteclk", - "dsi0_phy_pll_out_dsiclk", - "dsi1_phy_pll_out_byteclk", - "dsi1_phy_pll_out_dsiclk", - "dp_phy_pll_link_clk", - "dp_phy_pll_vco_div_clk"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - - power-domains = <&rpmhpd SM8350_MMCX>; - power-domain-names = "mmcx"; - }; - - adsp: remoteproc@17300000 { - compatible = "qcom,sm8350-adsp-pas"; - reg = <0 0x17300000 0 0x100>; - - interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, - <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, - <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, - <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, - <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - power-domains = <&rpmhpd SM8350_LCX>, - <&rpmhpd SM8350_LMX>; - power-domain-names = "lcx", "lmx"; - - memory-region = <&pil_adsp_mem>; - - qcom,qmp = <&aoss_qmp>; - - qcom,smem-states = <&smp2p_adsp_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts-extended = <&ipcc IPCC_CLIENT_LPASS - IPCC_MPROC_SIGNAL_GLINK_QMP - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_LPASS - IPCC_MPROC_SIGNAL_GLINK_QMP>; - - label = "lpass"; - qcom,remote-pid = <2>; - - fastrpc { - compatible = "qcom,fastrpc"; - qcom,glink-channels = "fastrpcglink-apps-dsp"; - label = "adsp"; - qcom,non-secure-domain; - #address-cells = <1>; - #size-cells = <0>; - - compute-cb@3 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <3>; - iommus = <&apps_smmu 0x1803 0x0>; - }; - - compute-cb@4 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <4>; - iommus = <&apps_smmu 0x1804 0x0>; - }; - - compute-cb@5 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <5>; - iommus = <&apps_smmu 0x1805 0x0>; - }; - }; - }; - }; }; thermal_zones: thermal-zones { @@ -2728,7 +3372,7 @@ type = "passive"; }; - cpu0_crit: cpu_crit { + cpu0_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -2772,7 +3416,7 @@ type = "passive"; }; - cpu1_crit: cpu_crit { + cpu1_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -2816,7 +3460,7 @@ type = "passive"; }; - cpu2_crit: cpu_crit { + cpu2_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -2860,7 +3504,7 @@ type = "passive"; }; - cpu3_crit: cpu_crit { + cpu3_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -2904,7 +3548,7 @@ type = "passive"; }; - cpu4_top_crit: cpu_crit { + cpu4_top_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -2948,7 +3592,7 @@ type = "passive"; }; - cpu5_top_crit: cpu_crit { + cpu5_top_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -2992,7 +3636,7 @@ type = "passive"; }; - cpu6_top_crit: cpu_crit { + cpu6_top_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -3036,7 +3680,7 @@ type = "passive"; }; - cpu7_top_crit: cpu_crit { + cpu7_top_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -3080,7 +3724,7 @@ type = "passive"; }; - cpu4_bottom_crit: cpu_crit { + cpu4_bottom_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -3124,7 +3768,7 @@ type = "passive"; }; - cpu5_bottom_crit: cpu_crit { + cpu5_bottom_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -3168,7 +3812,7 @@ type = "passive"; }; - cpu6_bottom_crit: cpu_crit { + cpu6_bottom_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -3212,7 +3856,7 @@ type = "passive"; }; - cpu7_bottom_crit: cpu_crit { + cpu7_bottom_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts index 4de3e1f1c39c..feef3837e4cd 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -8,6 +8,13 @@ #include <dt-bindings/regulator/qcom,rpmh-regulator.h> #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> #include "sm8450.dtsi" +#include "pm8350.dtsi" +#include "pm8350b.dtsi" +#include "pm8350c.dtsi" +#include "pm8450.dtsi" +#include "pmk8350.dtsi" +#include "pmr735a.dtsi" +#include "pmr735b.dtsi" / { model = "Qualcomm Technologies, Inc. SM8450 HDK"; @@ -17,10 +24,69 @@ serial0 = &uart7; }; + wcd938x: audio-codec { + compatible = "qcom,wcd9380-codec"; + + pinctrl-names = "default"; + pinctrl-0 = <&wcd_default>; + + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; + qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt = <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt = <50000>; + qcom,rx-device = <&wcd_rx>; + qcom,tx-device = <&wcd_tx>; + + reset-gpios = <&tlmm 43 GPIO_ACTIVE_LOW>; + + vdd-buck-supply = <&vreg_s10b_1p8>; + vdd-rxtx-supply = <&vreg_s10b_1p8>; + vdd-io-supply = <&vreg_s10b_1p8>; + vdd-mic-bias-supply = <&vreg_bob>; + + #sound-dai-cells = <1>; + }; + chosen { stdout-path = "serial0:115200n8"; }; + hdmi-out { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_connector_out: endpoint { + remote-endpoint = <<9611_out>; + }; + }; + }; + + lt9611_1v2: lt9611-vdd12-regulator { + compatible = "regulator-fixed"; + regulator-name = "LT9611_1V2"; + + vin-supply = <&vph_pwr>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + gpio = <&tlmm 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + lt9611_3v3: lt9611-3v3-regulator { + compatible = "regulator-fixed"; + regulator-name = "LT9611_3V3"; + + vin-supply = <&vreg_bob>; + gpio = <&tlmm 109 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + }; + vph_pwr: vph-pwr-regulator { compatible = "regulator-fixed"; regulator-name = "vph_pwr"; @@ -33,7 +99,7 @@ }; &apps_rsc { - pm8350-rpmh-regulators { + regulators-0 { compatible = "qcom,pm8350-rpmh-regulators"; qcom,pmic-id = "b"; @@ -124,7 +190,7 @@ }; }; - pm8350c-rpmh-regulators { + regulators-1 { compatible = "qcom,pm8350c-rpmh-regulators"; qcom,pmic-id = "c"; @@ -237,7 +303,7 @@ }; }; - pm8450-rpmh-regulators { + regulators-2 { compatible = "qcom,pm8450-rpmh-regulators"; qcom,pmic-id = "h"; @@ -280,7 +346,7 @@ }; - pmr735a-rpmh-regulators { + regulators-3 { compatible = "qcom,pmr735a-rpmh-regulators"; qcom,pmic-id = "e"; @@ -350,6 +416,74 @@ }; }; +&dispcc { + status = "okay"; +}; + +&i2c9 { + clock-frequency = <400000>; + status = "okay"; + + lt9611_codec: hdmi-bridge@2b { + compatible = "lontium,lt9611uxc"; + reg = <0x2b>; + + interrupts-extended = <&tlmm 44 IRQ_TYPE_EDGE_FALLING>; + + reset-gpios = <&tlmm 107 GPIO_ACTIVE_HIGH>; + + vdd-supply = <<9611_1v2>; + vcc-supply = <<9611_3v3>; + + pinctrl-names = "default"; + pinctrl-0 = <<9611_irq_pin <9611_rst_pin>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lt9611_a: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + + port@2 { + reg = <2>; + + lt9611_out: endpoint { + remote-endpoint = <&hdmi_connector_out>; + }; + }; + }; + }; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { + vdda-supply = <&vreg_l6b_1p2>; + status = "okay"; +}; + +&mdss_dsi0_out { + remote-endpoint = <<9611_a>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + vdds-supply = <&vreg_l5b_0p88>; + status = "okay"; +}; + +&mdss_mdp { + status = "okay"; +}; + &pcie0 { status = "okay"; max-link-speed = <2>; @@ -395,6 +529,10 @@ status = "okay"; }; +&qupv3_id_1 { + status = "okay"; +}; + &sdhc_2 { cd-gpios = <&tlmm 92 GPIO_ACTIVE_HIGH>; pinctrl-names = "default", "sleep"; @@ -407,33 +545,6 @@ status = "okay"; }; -&soc { - wcd938x: codec { - compatible = "qcom,wcd9380-codec"; - - pinctrl-names = "default"; - pinctrl-0 = <&wcd_default>; - - qcom,micbias1-microvolt = <1800000>; - qcom,micbias2-microvolt = <1800000>; - qcom,micbias3-microvolt = <1800000>; - qcom,micbias4-microvolt = <1800000>; - qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>; - qcom,mbhc-headset-vthreshold-microvolt = <1700000>; - qcom,mbhc-headphone-vthreshold-microvolt = <50000>; - qcom,rx-device = <&wcd_rx>; - qcom,tx-device = <&wcd_tx>; - - reset-gpios = <&tlmm 43 GPIO_ACTIVE_LOW>; - #sound-dai-cells = <1>; - - vdd-buck-supply = <&vreg_s10b_1p8>; - vdd-rxtx-supply = <&vreg_s10b_1p8>; - vdd-io-supply = <&vreg_s10b_1p8>; - vdd-mic-bias-supply = <&vreg_bob>; - }; -}; - &sound { compatible = "qcom,sm8450-sndcard"; model = "SM8450-HDK"; @@ -516,6 +627,8 @@ }; &swr0 { + status = "okay"; + left_spkr: speaker@0,1 { compatible = "sdw10217020200"; reg = <0 1>; @@ -564,6 +677,18 @@ &tlmm { gpio-reserved-ranges = <28 4>, <36 4>; + lt9611_irq_pin: lt9611-irq-state { + pins = "gpio44"; + function = "gpio"; + bias-disable; + }; + + lt9611_rst_pin: lt9611-rst-state { + pins = "gpio107"; + function = "gpio"; + output-high; + }; + sdc2_card_det_n: sd-card-det-n-state { pins = "gpio92"; function = "gpio"; @@ -622,6 +747,8 @@ pinctrl-names = "default"; vdd-micb-supply = <&vreg_s10b_1p8>; qcom,dmic-sample-rate = <600000>; + + status = "okay"; }; &tlmm { diff --git a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts index ee62514fff68..f7592946c783 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts @@ -7,6 +7,13 @@ #include <dt-bindings/regulator/qcom,rpmh-regulator.h> #include "sm8450.dtsi" +#include "pm8350.dtsi" +#include "pm8350b.dtsi" +#include "pm8350c.dtsi" +#include "pm8450.dtsi" +#include "pmk8350.dtsi" +#include "pmr735a.dtsi" +#include "pmr735b.dtsi" / { model = "Qualcomm Technologies, Inc. SM8450 QRD"; @@ -32,7 +39,7 @@ }; &apps_rsc { - pm8350-rpmh-regulators { + regulators-0 { compatible = "qcom,pm8350-rpmh-regulators"; qcom,pmic-id = "b"; @@ -123,7 +130,7 @@ }; }; - pm8350c-rpmh-regulators { + regulators-1 { compatible = "qcom,pm8350c-rpmh-regulators"; qcom,pmic-id = "c"; @@ -235,7 +242,7 @@ }; }; - pm8450-rpmh-regulators { + regulators-2 { compatible = "qcom,pm8450-rpmh-regulators"; qcom,pmic-id = "h"; @@ -278,7 +285,7 @@ }; - pmr735a-rpmh-regulators { + regulators-3 { compatible = "qcom,pmr735a-rpmh-regulators"; qcom,pmic-id = "e"; diff --git a/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara-pdx223.dts b/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara-pdx223.dts index b83500316a81..daf2f91f356e 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara-pdx223.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara-pdx223.dts @@ -11,6 +11,67 @@ / { model = "Sony Xperia 1 IV"; compatible = "sony,pdx223", "qcom,sm8450"; + + imx316_lvdd_regulator: imx316-lvdd-regulator { + compatible = "regulator-fixed"; + regulator-name = "imx316_lvdd_regulator"; + gpio = <&pm8350b_gpios 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&cam_pwr_ld_en>; + }; + + tcs3490_vdd_regulator: rgbcir-vdd-regulator { + compatible = "regulator-fixed"; + regulator-name = "tcs3490_vdd_regulator"; + gpio = <&pm8350c_gpios 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&rgbc_ir_pwr_en>; + }; +}; + +&pm8350b_gpios { + gpio-line-names = "CAM_PWR_A_CS", /* GPIO_1 */ + "NC", + "NC", + "NC", + "SNAPSHOT_N", + "CAM_PWR_LD_EN", + "NC", + "FOCUS_N"; + + cam_pwr_ld_en: cam-pwr-ld-en-state { + pins = "gpio6"; + function = "normal"; + qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>; + power-source = <0>; + drive-push-pull; + output-low; + }; +}; + +&pm8350c_gpios { + gpio-line-names = "FL_STROBE_TRIG_WIDE", /* GPIO_1 */ + "FL_STROBE_TRIG_TELE", + "WLC_ID", + "WLC_TXPWR_EN", + "NC", + "RGBC_IR_PWR_EN", + "NC", + "NC", + "WIDEC_PWR_EN"; + + rgbc_ir_pwr_en: rgbc-ir-pwr-en-state { + pins = "gpio6"; + function = "normal"; + qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>; + power-source = <1>; + drive-push-pull; + output-low; + }; }; &tlmm { diff --git a/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara-pdx224.dts b/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara-pdx224.dts index 13c2fc4bccfc..dc4de2d3fe48 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara-pdx224.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara-pdx224.dts @@ -12,14 +12,40 @@ model = "Sony Xperia 5 IV"; compatible = "sony,pdx224", "qcom,sm8450"; - imx563_vdig_vreg: imx563-vdig-regulator { + imx563_vdig_regulator: imx563-vdig-regulator { compatible = "regulator-fixed"; - regulator-name = "imx563_vdig_vreg"; + regulator-name = "imx563_vdig_regulator"; gpio = <&tlmm 22 GPIO_ACTIVE_HIGH>; enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&uwidec_pwr_en>; }; }; +&pm8350b_gpios { + gpio-line-names = "CAM_PWR_A_CS", /* GPIO_1 */ + "NC", + "NC", + "NC", + "SNAPSHOT_N", + "NC", + "NC", + "FOCUS_N"; +}; + +&pm8350c_gpios { + gpio-line-names = "FL_STROBE_TRIG_WIDE", /* GPIO_1 */ + "FL_STROBE_TRIG_TELE", + "WLC_ID", + "WLC_TXPWR_EN", + "NC", + "NC", /* RGBCIR uses a PMIC vreg, so it's most likely NC. */ + "NC", + "NC", + "WIDEC_PWR_EN"; +}; + &tlmm { gpio-line-names = "TELE_SPI_MISO", /* GPIO_0 */ "TELE_SPI_MOSI", /* SONY says NC, but it only makes sense this way.. */ @@ -231,4 +257,12 @@ "APPS_I2C_0_SCL", "CCI_I2C3_SDA", "CCI_I2C3_SCL"; + + uwidec_pwr_en: uwidec-pwr-en-state { + pins = "gpio22"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; }; diff --git a/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi b/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi index 38256226d229..67538b5a557e 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi @@ -3,8 +3,15 @@ * Copyright (c) 2022, Konrad Dybcio <konrad.dybcio@somainline.org> */ +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> #include <dt-bindings/regulator/qcom,rpmh-regulator.h> #include "sm8450.dtsi" +#include "pm8350.dtsi" +#include "pm8350b.dtsi" +#include "pm8350c.dtsi" +#include "pm8450.dtsi" +#include "pmk8350.dtsi" +#include "pmr735a.dtsi" /delete-node/ &adsp_mem; /delete-node/ &rmtfs_mem; @@ -21,6 +28,41 @@ stdout-path = "serial0:115200n8"; }; + gpio-keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&focus_n &snapshot_n &vol_down_n>; + + key-camera-focus { + label = "Camera Focus"; + linux,code = <KEY_CAMERA_FOCUS>; + gpios = <&pm8350b_gpios 8 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + + key-camera-snapshot { + label = "Camera Snapshot"; + linux,code = <KEY_CAMERA>; + gpios = <&pm8350b_gpios 5 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + + key-volume-down { + label = "Volume Down"; + linux,code = <KEY_VOLUMEDOWN>; + gpios = <&pm8350_gpios 6 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + }; + reserved-memory { adsp_mem: memory@85700000 { reg = <0x0 0x85700000 0x0 0x2800000>; @@ -52,11 +94,14 @@ }; /* Sadly, the voltages for these GPIO regulators are unknown. */ - imx650_vana_vreg: imx650-vana-regulator { + imx650_vana_regulator: imx650-vana-regulator { compatible = "regulator-fixed"; - regulator-name = "imx650_vana_vreg"; + regulator-name = "imx650_vana_regulator"; gpio = <&tlmm 23 GPIO_ACTIVE_HIGH>; enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&telec_pwr_en>; }; vph_pwr: vph-pwr-regulator { @@ -71,7 +116,7 @@ }; &apps_rsc { - pm8350-rpmh-regulators { + regulators-0 { compatible = "qcom,pm8350-rpmh-regulators"; qcom,pmic-id = "b"; @@ -167,7 +212,7 @@ }; }; - pm8350c-rpmh-regulators { + regulators-1 { compatible = "qcom,pm8350c-rpmh-regulators"; qcom,pmic-id = "c"; @@ -303,7 +348,7 @@ }; }; - pm8450-rpmh-regulators { + regulators-2 { compatible = "qcom,pm8450-rpmh-regulators"; qcom,pmic-id = "h"; @@ -347,7 +392,7 @@ }; }; - pmr735a-rpmh-regulators { + regulators-3 { compatible = "qcom,pmr735a-rpmh-regulators"; qcom,pmic-id = "e"; @@ -456,7 +501,58 @@ clock-frequency = <400000>; status = "okay"; - /* Dialog SLG51000 CMIC @ 75 */ + pmic@75 { + compatible = "dlg,slg51000"; + reg = <0x75>; + dlg,cs-gpios = <&pm8350b_gpios 1 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&cam_pwr_a_cs>; + + regulators { + slg51000_a_ldo1: ldo1 { + regulator-name = "slg51000_a_ldo1"; + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3300000>; + }; + + slg51000_a_ldo2: ldo2 { + regulator-name = "slg51000_a_ldo2"; + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3300000>; + }; + + slg51000_a_ldo3: ldo3 { + regulator-name = "slg51000_a_ldo3"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3750000>; + }; + + slg51000_a_ldo4: ldo4 { + regulator-name = "slg51000_a_ldo4"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3750000>; + }; + + slg51000_a_ldo5: ldo5 { + regulator-name = "slg51000_a_ldo5"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1200000>; + }; + + slg51000_a_ldo6: ldo6 { + regulator-name = "slg51000_a_ldo6"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1200000>; + }; + + slg51000_a_ldo7: ldo7 { + regulator-name = "slg51000_a_ldo7"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3750000>; + }; + }; + }; }; &i2c9 { @@ -466,13 +562,6 @@ /* NXP SN1X0 NFC @ 28 */ }; -&i2c13 { - clock-frequency = <400000>; - status = "okay"; - - /* Richwave RTC6226 FM Radio Receiver @ 64 */ -}; - &i2c14 { clock-frequency = <1000000>; status = "okay"; @@ -533,18 +622,89 @@ status = "okay"; }; +&pm8350_gpios { + gpio-line-names = "ASSIGN1_THERM", /* GPIO_1 */ + "LCD_ID", + "SDR_MMW_THERM", + "RF_ID", + "NC", + "VOL_DOWN_N", + "NC", + "NC", + "NC", + "PM8350_OPTION"; /* GPIO_10 */ + + vol_down_n: vol-down-n-state { + pins = "gpio6"; + function = "normal"; + power-source = <1>; + bias-pull-up; + input-enable; + }; +}; + +&pm8350b_gpios { + cam_pwr_a_cs: cam-pwr-a-cs-state { + pins = "gpio1"; + function = "normal"; + qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>; + power-source = <1>; + drive-push-pull; + output-high; + }; + + snapshot_n: snapshot-n-state { + pins = "gpio5"; + function = "normal"; + power-source = <0>; + bias-pull-up; + input-enable; + }; + + focus_n: focus-n-state { + pins = "gpio8"; + function = "normal"; + power-source = <0>; + bias-pull-up; + input-enable; + }; +}; + +&pm8450_gpios { + gpio-line-names = "FP_LDO_EN", /* GPIO_1 */ + "", + "", + ""; +}; + +&pmk8350_gpios { + gpio-line-names = "NC", /* GPIO_1 */ + "NC", + "DISP_THERM", + "PMK8350_OPTION"; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + linux,code = <KEY_VOLUMEUP>; + status = "okay"; +}; + &remoteproc_adsp { - firmware-name = "qcom/sm8350/Sony/nagara/adsp.mbn"; + firmware-name = "qcom/sm8450/Sony/nagara/adsp.mbn"; status = "okay"; }; &remoteproc_cdsp { - firmware-name = "qcom/sm8350/Sony/nagara/cdsp.mbn"; + firmware-name = "qcom/sm8450/Sony/nagara/cdsp.mbn"; status = "okay"; }; &remoteproc_slpi { - firmware-name = "qcom/sm8350/Sony/nagara/slpi.mbn"; + firmware-name = "qcom/sm8450/Sony/nagara/slpi.mbn"; status = "okay"; }; @@ -597,6 +757,14 @@ input-enable; }; + telec_pwr_en: telec-pwr-en-state { + pins = "gpio23"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + sdc2_card_det_n: sd-card-det-n-state { pins = "gpio92"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 570475040d95..1a744a33bcf4 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -57,9 +57,11 @@ clocks = <&cpufreq_hw 0>; L2_0: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; L3_0: l3-cache { compatible = "cache"; + cache-level = <3>; }; }; }; @@ -77,6 +79,7 @@ clocks = <&cpufreq_hw 0>; L2_100: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -94,6 +97,7 @@ clocks = <&cpufreq_hw 0>; L2_200: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -111,6 +115,7 @@ clocks = <&cpufreq_hw 0>; L2_300: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -128,6 +133,7 @@ clocks = <&cpufreq_hw 1>; L2_400: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -145,6 +151,7 @@ clocks = <&cpufreq_hw 1>; L2_500: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; @@ -163,6 +170,7 @@ clocks = <&cpufreq_hw 1>; L2_600: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -180,6 +188,7 @@ clocks = <&cpufreq_hw 2>; L2_700: l2-cache { compatible = "cache"; + cache-level = <2>; next-level-cache = <&L3_0>; }; }; @@ -270,6 +279,7 @@ firmware { scm: scm { compatible = "qcom,scm-sm8450", "qcom,scm"; + qcom,dload-mode = <&tcsr 0x13000>; interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; #reset-cells = <1>; }; @@ -302,55 +312,55 @@ compatible = "arm,psci-1.0"; method = "smc"; - CPU_PD0: cpu0 { + CPU_PD0: power-domain-cpu0 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&LITTLE_CPU_SLEEP_0>; }; - CPU_PD1: cpu1 { + CPU_PD1: power-domain-cpu1 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&LITTLE_CPU_SLEEP_0>; }; - CPU_PD2: cpu2 { + CPU_PD2: power-domain-cpu2 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&LITTLE_CPU_SLEEP_0>; }; - CPU_PD3: cpu3 { + CPU_PD3: power-domain-cpu3 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&LITTLE_CPU_SLEEP_0>; }; - CPU_PD4: cpu4 { + CPU_PD4: power-domain-cpu4 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&BIG_CPU_SLEEP_0>; }; - CPU_PD5: cpu5 { + CPU_PD5: power-domain-cpu5 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&BIG_CPU_SLEEP_0>; }; - CPU_PD6: cpu6 { + CPU_PD6: power-domain-cpu6 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&BIG_CPU_SLEEP_0>; }; - CPU_PD7: cpu7 { + CPU_PD7: power-domain-cpu7 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&BIG_CPU_SLEEP_0>; }; - CLUSTER_PD: cpu-cluster0 { + CLUSTER_PD: power-domain-cpu-cluster0 { #power-domain-cells = <0>; domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>; }; @@ -731,19 +741,29 @@ #reset-cells = <1>; #power-domain-cells = <1>; clocks = <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, <&pcie0_lane>, <&pcie1_lane>, - <&sleep_clk>; + <0>, + <&ufs_mem_phy_lanes 0>, + <&ufs_mem_phy_lanes 1>, + <&ufs_mem_phy_lanes 2>, + <0>; clock-names = "bi_tcxo", + "sleep_clk", "pcie_0_pipe_clk", "pcie_1_pipe_clk", - "sleep_clk"; + "pcie_1_phy_aux_clk", + "ufs_phy_rx_symbol_0_clk", + "ufs_phy_rx_symbol_1_clk", + "ufs_phy_tx_symbol_0_clk", + "usb3_phy_wrapper_gcc_usb30_pipe_clk"; }; gpi_dma2: dma-controller@800000 { compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma"; #dma-cells = <3>; - reg = <0 0x800000 0 0x60000>; + reg = <0 0x00800000 0 0x60000>; interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, @@ -997,8 +1017,6 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart20_default>; interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; status = "disabled"; }; @@ -1064,7 +1082,7 @@ gpi_dma0: dma-controller@900000 { compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma"; #dma-cells = <3>; - reg = <0 0x900000 0 0x60000>; + reg = <0 0x00900000 0 0x60000>; interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, @@ -1345,7 +1363,7 @@ i2c6: i2c@998000 { compatible = "qcom,geni-i2c"; - reg = <0x0 0x998000 0x0 0x4000>; + reg = <0x0 0x00998000 0x0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; pinctrl-names = "default"; @@ -1365,7 +1383,7 @@ spi6: spi@998000 { compatible = "qcom,geni-spi"; - reg = <0x0 0x998000 0x0 0x4000>; + reg = <0x0 0x00998000 0x0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; @@ -1391,8 +1409,6 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; status = "disabled"; }; }; @@ -1400,7 +1416,7 @@ gpi_dma1: dma-controller@a00000 { compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma"; #dma-cells = <3>; - reg = <0 0xa00000 0 0x60000>; + reg = <0 0x00a00000 0 0x60000>; interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, @@ -1733,6 +1749,13 @@ ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; + /* + * MSIs for BDF (1:0.0) only works with Device ID 0x5980. + * Hence, the IDs are swapped. + */ + msi-map = <0x0 &gic_its 0x5981 0x1>, + <0x100 &gic_its 0x5980 0x1>; + msi-map-mask = <0xff00>; interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "msi"; #interrupt-cells = <1>; @@ -1810,10 +1833,10 @@ status = "disabled"; pcie0_lane: phy@1c06200 { - reg = <0 0x1c06e00 0 0x200>, /* tx */ - <0 0x1c07000 0 0x200>, /* rx */ - <0 0x1c06200 0 0x200>, /* pcs */ - <0 0x1c06600 0 0x200>; /* pcs_pcie */ + reg = <0 0x01c06e00 0 0x200>, /* tx */ + <0 0x01c07000 0 0x200>, /* rx */ + <0 0x01c06200 0 0x200>, /* pcs */ + <0 0x01c06600 0 0x200>; /* pcs_pcie */ clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; clock-names = "pipe0"; @@ -1842,6 +1865,13 @@ ranges = <0x01000000 0x0 0x40200000 0 0x40200000 0x0 0x100000>, <0x02000000 0x0 0x40300000 0 0x40300000 0x0 0x1fd00000>; + /* + * MSIs for BDF (1:0.0) only works with Device ID 0x5a00. + * Hence, the IDs are swapped. + */ + msi-map = <0x0 &gic_its 0x5a01 0x1>, + <0x100 &gic_its 0x5a00 0x1>; + msi-map-mask = <0xff00>; interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "msi"; #interrupt-cells = <1>; @@ -1917,12 +1947,12 @@ status = "disabled"; pcie1_lane: phy@1c0e000 { - reg = <0 0x1c0e000 0 0x200>, /* tx */ - <0 0x1c0e200 0 0x300>, /* rx */ - <0 0x1c0f200 0 0x200>, /* pcs */ - <0 0x1c0e800 0 0x200>, /* tx */ - <0 0x1c0ea00 0 0x300>, /* rx */ - <0 0x1c0f400 0 0xc00>; /* pcs_pcie */ + reg = <0 0x01c0e000 0 0x200>, /* tx */ + <0 0x01c0e200 0 0x300>, /* rx */ + <0 0x01c0f200 0 0x200>, /* pcs */ + <0 0x01c0e800 0 0x200>, /* tx */ + <0 0x01c0ea00 0 0x300>, /* rx */ + <0 0x01c0f400 0 0xc00>; /* pcs_pcie */ clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; clock-names = "pipe0"; @@ -1986,6 +2016,11 @@ #hwlock-cells = <1>; }; + tcsr: syscon@1fc0000 { + compatible = "qcom,sm8450-tcsr", "syscon"; + reg = <0x0 0x1fc0000 0x0 0x30000>; + }; + usb_1_hsphy: phy@88e3000 { compatible = "qcom,sm8450-usb-hs-phy", "qcom,usb-snps-hs-7nm-phy"; @@ -2143,11 +2178,12 @@ #address-cells = <2>; #size-cells = <0>; #sound-dai-cells = <1>; + status = "disabled"; }; rxmacro: codec@3200000 { compatible = "qcom,sm8450-lpass-rx-macro"; - reg = <0 0x3200000 0 0x1000>; + reg = <0 0x03200000 0 0x1000>; clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, @@ -2168,7 +2204,7 @@ swr1: soundwire-controller@3210000 { compatible = "qcom,soundwire-v1.7.0"; - reg = <0 0x3210000 0 0x2000>; + reg = <0 0x03210000 0 0x2000>; interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rxmacro>; clock-names = "iface"; @@ -2189,11 +2225,12 @@ #address-cells = <2>; #size-cells = <0>; #sound-dai-cells = <1>; + status = "disabled"; }; txmacro: codec@3220000 { compatible = "qcom,sm8450-lpass-tx-macro"; - reg = <0 0x3220000 0 0x1000>; + reg = <0 0x03220000 0 0x1000>; clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, @@ -2256,14 +2293,15 @@ #address-cells = <2>; #size-cells = <0>; #sound-dai-cells = <1>; + status = "disabled"; }; swr2: soundwire-controller@33b0000 { compatible = "qcom,soundwire-v1.7.0"; - reg = <0 0x33b0000 0 0x2000>; + reg = <0 0x033b0000 0 0x2000>; interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "core", "wake"; + interrupt-names = "core", "wakeup"; clocks = <&vamacro>; clock-names = "iface"; @@ -2284,6 +2322,7 @@ #address-cells = <2>; #size-cells = <0>; #sound-dai-cells = <1>; + status = "disabled"; }; vamacro: codec@33f0000 { @@ -2300,6 +2339,7 @@ #clock-cells = <0>; clock-output-names = "fsgen"; #sound-dai-cells = <1>; + status = "disabled"; }; remoteproc_adsp: remoteproc@30000000 { @@ -2554,8 +2594,8 @@ }; cci0: cci@ac15000 { - compatible = "qcom,sm8450-cci"; - reg = <0 0xac15000 0 0x1000>; + compatible = "qcom,sm8450-cci", "qcom,msm8996-cci"; + reg = <0 0x0ac15000 0 0x1000>; interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; power-domains = <&camcc TITAN_TOP_GDSC>; @@ -2593,8 +2633,8 @@ }; cci1: cci@ac16000 { - compatible = "qcom,sm8450-cci"; - reg = <0 0xac16000 0 0x1000>; + compatible = "qcom,sm8450-cci", "qcom,msm8996-cci"; + reg = <0 0x0ac16000 0 0x1000>; interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>; power-domains = <&camcc TITAN_TOP_GDSC>; @@ -2646,6 +2686,281 @@ status = "disabled"; }; + mdss: display-subsystem@ae00000 { + compatible = "qcom,sm8450-mdss"; + reg = <0 0x0ae00000 0 0x1000>; + reg-names = "mdss"; + + /* same path used twice */ + interconnects = <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>, + <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>; + interconnect-names = "mdp0-mem", "mdp1-mem"; + + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; + + power-domains = <&dispcc MDSS_GDSC>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x2800 0x402>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + mdss_mdp: display-controller@ae01000 { + compatible = "qcom,sm8450-dpu"; + reg = <0 0x0ae01000 0 0x8f000>, + <0 0x0aeb0000 0 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", + "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd SM8450_MMCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf2_out: endpoint { + remote-endpoint = <&mdss_dsi1_in>; + }; + }; + + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-172000000 { + opp-hz = /bits/ 64 <172000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-325000000 { + opp-hz = /bits/ 64 <325000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-375000000 { + opp-hz = /bits/ 64 <375000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss_dsi0: dsi@ae94000 { + compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae94000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; + + operating-points-v2 = <&mdss_dsi_opp_table>; + power-domains = <&rpmhpd SM8450_MMCX>; + + phys = <&mdss_dsi0_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dsi0_out: endpoint { + }; + }; + }; + + mdss_dsi_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + mdss_dsi0_phy: phy@ae94400 { + compatible = "qcom,sm8450-dsi-phy-5nm"; + reg = <0 0x0ae94400 0 0x200>, + <0 0x0ae94600 0 0x280>, + <0 0x0ae94900 0 0x260>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + + mdss_dsi1: dsi@ae96000 { + compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae96000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <5>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; + + operating-points-v2 = <&mdss_dsi_opp_table>; + power-domains = <&rpmhpd SM8450_MMCX>; + + phys = <&mdss_dsi1_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dsi1_in: endpoint { + remote-endpoint = <&dpu_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dsi1_out: endpoint { + }; + }; + }; + }; + + mdss_dsi1_phy: phy@ae96400 { + compatible = "qcom,sm8450-dsi-phy-5nm"; + reg = <0 0x0ae96400 0 0x200>, + <0 0x0ae96600 0 0x280>, + <0 0x0ae96900 0 0x260>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + }; + dispcc: clock-controller@af00000 { compatible = "qcom,sm8450-dispcc"; reg = <0 0x0af00000 0 0x20000>; @@ -2653,10 +2968,10 @@ <&rpmhcc RPMH_CXO_CLK_A>, <&gcc GCC_DISP_AHB_CLK>, <&sleep_clk>, - <0>, /* dsi0 */ - <0>, - <0>, /* dsi1 */ - <0>, + <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>, + <&mdss_dsi1_phy 0>, + <&mdss_dsi1_phy 1>, <0>, /* dp0 */ <0>, <0>, /* dp1 */ @@ -2705,7 +3020,7 @@ #thermal-sensor-cells = <1>; }; - aoss_qmp: power-controller@c300000 { + aoss_qmp: power-management@c300000 { compatible = "qcom,sm8450-aoss-qmp", "qcom,aoss-qmp"; reg = <0 0x0c300000 0 0x400>; interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP @@ -2715,6 +3030,28 @@ #clock-cells = <0>; }; + spmi_bus: spmi@c400000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0 0x0c400000 0 0x00003000>, + <0 0x0c500000 0 0x00400000>, + <0 0x0c440000 0 0x00080000>, + <0 0x0c4c0000 0 0x00010000>, + <0 0x0c42d000 0 0x00010000>; + reg-names = "core", + "chnls", + "obsrvr", + "intr", + "cnfg"; + interrupt-names = "periph_irq"; + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + qcom,ee = <0>; + qcom,channel = <0>; + interrupt-controller; + #interrupt-cells = <4>; + #address-cells = <2>; + #size-cells = <0>; + }; + ipcc: mailbox@ed18000 { compatible = "qcom,sm8450-ipcc", "qcom,ipcc"; reg = <0 0x0ed18000 0 0x1000>; @@ -3235,10 +3572,10 @@ }; - lpass_tlmm: pinctrl@3440000{ + lpass_tlmm: pinctrl@3440000 { compatible = "qcom,sm8450-lpass-lpi-pinctrl"; - reg = <0 0x3440000 0x0 0x20000>, - <0 0x34d0000 0x0 0x10000>; + reg = <0 0x03440000 0x0 0x20000>, + <0 0x034d0000 0x0 0x10000>; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&lpass_tlmm 0 0 23>; @@ -3580,35 +3917,39 @@ opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; }; - rpmhpd_opp_low_svs: opp3 { + rpmhpd_opp_low_svs_d1: opp3 { + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; + }; + + rpmhpd_opp_low_svs: opp4 { opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; }; - rpmhpd_opp_svs: opp4 { + rpmhpd_opp_svs: opp5 { opp-level = <RPMH_REGULATOR_LEVEL_SVS>; }; - rpmhpd_opp_svs_l1: opp5 { + rpmhpd_opp_svs_l1: opp6 { opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; }; - rpmhpd_opp_nom: opp6 { + rpmhpd_opp_nom: opp7 { opp-level = <RPMH_REGULATOR_LEVEL_NOM>; }; - rpmhpd_opp_nom_l1: opp7 { + rpmhpd_opp_nom_l1: opp8 { opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; }; - rpmhpd_opp_nom_l2: opp8 { + rpmhpd_opp_nom_l2: opp9 { opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; }; - rpmhpd_opp_turbo: opp9 { + rpmhpd_opp_turbo: opp10 { opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; }; - rpmhpd_opp_turbo_l1: opp10 { + rpmhpd_opp_turbo_l1: opp11 { opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; }; }; @@ -3720,6 +4061,7 @@ <0 0x01d87c00 0 0x200>, <0 0x01d87800 0 0x188>, <0 0x01d87a00 0 0x200>; + #clock-cells = <1>; #phy-cells = <0>; }; }; @@ -3825,7 +4167,7 @@ lpass_ag_noc: interconnect@3c40000 { compatible = "qcom,sm8450-lpass-ag-noc"; - reg = <0 0x3c40000 0 0x17200>; + reg = <0 0x03c40000 0 0x17200>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; @@ -3953,7 +4295,7 @@ type = "passive"; }; - cpu4_top_crit: cpu_crit { + cpu4_top_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -3979,7 +4321,7 @@ type = "passive"; }; - cpu4_bottom_crit: cpu_crit { + cpu4_bottom_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -4005,7 +4347,7 @@ type = "passive"; }; - cpu5_top_crit: cpu_crit { + cpu5_top_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -4031,7 +4373,7 @@ type = "passive"; }; - cpu5_bottom_crit: cpu_crit { + cpu5_bottom_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -4057,7 +4399,7 @@ type = "passive"; }; - cpu6_top_crit: cpu_crit { + cpu6_top_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -4083,7 +4425,7 @@ type = "passive"; }; - cpu6_bottom_crit: cpu_crit { + cpu6_bottom_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -4109,7 +4451,7 @@ type = "passive"; }; - cpu7_top_crit: cpu_crit { + cpu7_top_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -4135,7 +4477,7 @@ type = "passive"; }; - cpu7_middle_crit: cpu_crit { + cpu7_middle_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -4161,7 +4503,7 @@ type = "passive"; }; - cpu7_bottom_crit: cpu_crit { + cpu7_bottom_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -4193,7 +4535,7 @@ type = "passive"; }; - gpu0_tj_cfg: tj_cfg { + gpu0_tj_cfg: tj-cfg { temperature = <95000>; hysteresis = <5000>; type = "passive"; @@ -4225,7 +4567,7 @@ type = "passive"; }; - gpu1_tj_cfg: tj_cfg { + gpu1_tj_cfg: tj-cfg { temperature = <95000>; hysteresis = <5000>; type = "passive"; @@ -4271,7 +4613,7 @@ type = "passive"; }; - cpu0_crit: cpu_crit { + cpu0_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -4297,7 +4639,7 @@ type = "passive"; }; - cpu1_crit: cpu_crit { + cpu1_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -4323,7 +4665,7 @@ type = "passive"; }; - cpu2_crit: cpu_crit { + cpu2_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; @@ -4349,7 +4691,7 @@ type = "passive"; }; - cpu3_crit: cpu_crit { + cpu3_crit: cpu-crit { temperature = <110000>; hysteresis = <1000>; type = "critical"; diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts new file mode 100644 index 000000000000..5db6e789e6b8 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts @@ -0,0 +1,568 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Linaro Limited + */ + +/dts-v1/; + +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> +#include "sm8550.dtsi" +#include "pm8010.dtsi" +#include "pm8550.dtsi" +#include "pm8550b.dtsi" +#include "pm8550ve.dtsi" +#include "pm8550vs.dtsi" +#include "pmk8550.dtsi" +#include "pmr735d.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SM8550 MTP"; + compatible = "qcom,sm8550-mtp", "qcom,sm8550"; + + aliases { + serial0 = &uart7; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm8550-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-bob1-supply = <&vph_pwr>; + vdd-bob2-supply = <&vph_pwr>; + vdd-l2-l13-l14-supply = <&vreg_bob1>; + vdd-l3-supply = <&vreg_s4g_1p3>; + vdd-l5-l16-supply = <&vreg_bob1>; + vdd-l6-l7-supply = <&vreg_bob1>; + vdd-l8-l9-supply = <&vreg_bob1>; + vdd-l11-supply = <&vreg_s4g_1p3>; + vdd-l12-supply = <&vreg_s6g_1p8>; + vdd-l15-supply = <&vreg_s6g_1p8>; + vdd-l17-supply = <&vreg_bob2>; + + vreg_bob1: bob1 { + regulator-name = "vreg_bob1"; + regulator-min-microvolt = <3296000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_bob2: bob2 { + regulator-name = "vreg_bob2"; + regulator-min-microvolt = <2720000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l1b_1p8: ldo1 { + regulator-name = "vreg_l1b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2b_3p0: ldo2 { + regulator-name = "vreg_l2b_3p0"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l5b_3p1: ldo5 { + regulator-name = "vreg_l5b_3p1"; + regulator-min-microvolt = <3104000>; + regulator-max-microvolt = <3104000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l6b_1p8: ldo6 { + regulator-name = "vreg_l6b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l7b_1p8: ldo7 { + regulator-name = "vreg_l7b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l8b_1p8: ldo8 { + regulator-name = "vreg_l8b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l9b_2p9: ldo9 { + regulator-name = "vreg_l9b_2p9"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l11b_1p2: ldo11 { + regulator-name = "vreg_l11b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1504000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l12b_1p8: ldo12 { + regulator-name = "vreg_l12b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l13b_3p0: ldo13 { + regulator-name = "vreg_l13b_3p0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l14b_3p2: ldo14 { + regulator-name = "vreg_l14b_3p2"; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l15b_1p8: ldo15 { + regulator-name = "vreg_l15b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l16b_2p8: ldo16 { + regulator-name = "vreg_l16b_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l17b_2p5: ldo17 { + regulator-name = "vreg_l17b_2p5"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-1 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-l3-supply = <&vreg_s4e_0p9>; + + vreg_l3c_0p91: ldo3 { + regulator-name = "vreg_l3c_0p9"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-2 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id = "d"; + + vdd-l1-supply = <&vreg_s4e_0p9>; + + vreg_l1d_0p88: ldo1 { + regulator-name = "vreg_l1d_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-3 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id = "e"; + + vdd-l1-supply = <&vreg_s4e_0p9>; + vdd-l2-supply = <&vreg_s4e_0p9>; + vdd-l3-supply = <&vreg_s4g_1p3>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + + vreg_s4e_0p9: smps4 { + regulator-name = "vreg_s4e_0p9"; + regulator-min-microvolt = <904000>; + regulator-max-microvolt = <984000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s5e_1p1: smps5 { + regulator-name = "vreg_s5e_1p1"; + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1120000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l1e_0p88: ldo1 { + regulator-name = "vreg_l1e_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2e_0p9: ldo2 { + regulator-name = "vreg_l2e_0p9"; + regulator-min-microvolt = <904000>; + regulator-max-microvolt = <970000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3e_1p2: ldo3 { + regulator-name = "vreg_l3e_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-4 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "f"; + + vdd-l1-supply = <&vreg_s4e_0p9>; + vdd-l2-supply = <&vreg_s4e_0p9>; + vdd-l3-supply = <&vreg_s4e_0p9>; + vdd-s4-supply = <&vph_pwr>; + + vreg_s4f_0p5: smps4 { + regulator-name = "vreg_s4f_0p5"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <700000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l1f_0p9: ldo1 { + regulator-name = "vreg_l1f_0p9"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2f_0p88: ldo2 { + regulator-name = "vreg_l2f_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3f_0p91: ldo3 { + regulator-name = "vreg_l3f_0p91"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-5 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id = "g"; + + vdd-l1-supply = <&vreg_s4g_1p3>; + vdd-l2-supply = <&vreg_s4g_1p3>; + vdd-l3-supply = <&vreg_s4g_1p3>; + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + + vreg_s1g_1p2: smps1 { + regulator-name = "vreg_s1g_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1300000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s2g_0p8: smps2 { + regulator-name = "vreg_s2g_0p8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s3g_0p7: smps3 { + regulator-name = "vreg_s3g_0p7"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1004000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s4g_1p3: smps4 { + regulator-name = "vreg_s4g_1p3"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1352000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s5g_0p8: smps5 { + regulator-name = "vreg_s5g_0p8"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1004000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s6g_1p8: smps6 { + regulator-name = "vreg_s6g_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l1g_1p2: ldo1 { + regulator-name = "vreg_l1g_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2g_1p2: ldo2 { + regulator-name = "vreg_l2g_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3g_1p2: ldo3 { + regulator-name = "vreg_l3g_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; +}; + +&dispcc { + status = "okay"; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { + vdda-supply = <&vreg_l3e_1p2>; + status = "okay"; + + panel@0 { + compatible = "visionox,vtdr6130"; + reg = <0>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sde_dsi_active>, <&sde_te_active>; + pinctrl-1 = <&sde_dsi_suspend>, <&sde_te_suspend>; + + vddio-supply = <&vreg_l12b_1p8>; + vci-supply = <&vreg_l13b_3p0>; + vdd-supply = <&vreg_l11b_1p2>; + + reset-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>; + + port { + panel0_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + remote-endpoint = <&panel0_in>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + vdds-supply = <&vreg_l1e_0p88>; + status = "okay"; +}; + +&mdss_mdp { + status = "okay"; +}; + +&pcie_1_phy_aux_clk { + clock-frequency = <1000>; +}; + +&pcie0 { + wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pcie0_phy { + vdda-phy-supply = <&vreg_l1e_0p88>; + vdda-pll-supply = <&vreg_l3e_1p2>; + status = "okay"; +}; + +&pcie1 { + wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; + perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pcie1_phy { + vdda-phy-supply = <&vreg_l3c_0p91>; + vdda-pll-supply = <&vreg_l3e_1p2>; + vdda-qref-supply = <&vreg_l1e_0p88>; + status = "okay"; +}; + +&pm8550_gpios { + sdc2_card_det_n: sdc2-card-det-state { + pins = "gpio12"; + function = "normal"; + input-enable; + output-disable; + bias-pull-up; + power-source = <1>; /* 1.8 V */ + }; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/sm8550/adsp.mbn", + "qcom/sm8550/adsp_dtb.mbn"; + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/sm8550/cdsp.mbn", + "qcom/sm8550/cdsp_dtb.mbn"; + status = "okay"; +}; + +&remoteproc_mpss { + firmware-name = "qcom/sm8550/modem.mbn", + "qcom/sm8550/modem_dtb.mbn"; + status = "okay"; +}; + +&sdhc_2 { + cd-gpios = <&pm8550_gpios 12 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_default &sdc2_card_det_n>; + pinctrl-1 = <&sdc2_sleep &sdc2_card_det_n>; + vmmc-supply = <&vreg_l9b_2p9>; + vqmmc-supply = <&vreg_l8b_1p8>; + bus-width = <4>; + no-sdio; + no-mmc; + status = "okay"; +}; + +&sleep_clk { + clock-frequency = <32000>; +}; + +&tlmm { + gpio-reserved-ranges = <32 8>; + + sde_dsi_active: sde-dsi-active-state { + pins = "gpio133"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + sde_dsi_suspend: sde-dsi-suspend-state { + pins = "gpio133"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + sde_te_active: sde-te-active-state { + pins = "gpio86"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-pull-down; + }; + + sde_te_suspend: sde-te-suspend-state { + pins = "gpio86"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-pull-down; + }; +}; + +&uart7 { + status = "okay"; +}; + +&ufs_mem_hc { + reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>; + vcc-supply = <&vreg_l17b_2p5>; + vcc-max-microamp = <1300000>; + vccq-supply = <&vreg_l1g_1p2>; + vccq-max-microamp = <1200000>; + vccq2-supply = <&vreg_l3g_1p2>; + vccq2-max-microamp = <100>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l1d_0p88>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "peripheral"; +}; + +&usb_1_hsphy { + vdd-supply = <&vreg_l1e_0p88>; + vdda12-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&usb_dp_qmpphy { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l3f_0p91>; + + status = "okay"; +}; + +&xo_board { + clock-frequency = <76800000>; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi new file mode 100644 index 000000000000..ff4d342c0725 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -0,0 +1,4806 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Linaro Limited + */ + +#include <dt-bindings/clock/qcom,rpmh.h> +#include <dt-bindings/clock/qcom,sm8550-gcc.h> +#include <dt-bindings/clock/qcom,sm8550-tcsr.h> +#include <dt-bindings/clock/qcom,sm8550-dispcc.h> +#include <dt-bindings/dma/qcom-gpi.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interconnect/qcom,sm8550-rpmh.h> +#include <dt-bindings/mailbox/qcom-ipcc.h> +#include <dt-bindings/power/qcom-rpmpd.h> +#include <dt-bindings/soc/qcom,gpr.h> +#include <dt-bindings/soc/qcom,rpmh-rsc.h> +#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> +#include <dt-bindings/phy/phy-qcom-qmp.h> +#include <dt-bindings/thermal/thermal.h> + +/ { + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + bi_tcxo_div2: bi-tcxo-div2-clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-mult = <1>; + clock-div = <2>; + }; + + bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&rpmhcc RPMH_CXO_CLK_A>; + clock-mult = <1>; + clock-div = <2>; + }; + + pcie_1_phy_aux_clk: pcie-1-phy-aux-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0 0>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + #cooling-cells = <2>; + L2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + L3_0: l3-cache { + compatible = "cache"; + cache-level = <3>; + }; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0 0x100>; + enable-method = "psci"; + next-level-cache = <&L2_100>; + power-domains = <&CPU_PD1>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + #cooling-cells = <2>; + L2_100: l2-cache { + compatible = "cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0 0x200>; + enable-method = "psci"; + next-level-cache = <&L2_200>; + power-domains = <&CPU_PD2>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + #cooling-cells = <2>; + L2_200: l2-cache { + compatible = "cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0 0x300>; + enable-method = "psci"; + next-level-cache = <&L2_300>; + power-domains = <&CPU_PD3>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; + capacity-dmips-mhz = <1792>; + dynamic-power-coefficient = <270>; + #cooling-cells = <2>; + L2_300: l2-cache { + compatible = "cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU4: cpu@400 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0 0x400>; + enable-method = "psci"; + next-level-cache = <&L2_400>; + power-domains = <&CPU_PD4>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; + capacity-dmips-mhz = <1792>; + dynamic-power-coefficient = <270>; + #cooling-cells = <2>; + L2_400: l2-cache { + compatible = "cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU5: cpu@500 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0 0x500>; + enable-method = "psci"; + next-level-cache = <&L2_500>; + power-domains = <&CPU_PD5>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; + capacity-dmips-mhz = <1792>; + dynamic-power-coefficient = <270>; + #cooling-cells = <2>; + L2_500: l2-cache { + compatible = "cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU6: cpu@600 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0 0x600>; + enable-method = "psci"; + next-level-cache = <&L2_600>; + power-domains = <&CPU_PD6>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; + capacity-dmips-mhz = <1792>; + dynamic-power-coefficient = <270>; + #cooling-cells = <2>; + L2_600: l2-cache { + compatible = "cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU7: cpu@700 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0 0x700>; + enable-method = "psci"; + next-level-cache = <&L2_700>; + power-domains = <&CPU_PD7>; + power-domain-names = "psci"; + qcom,freq-domain = <&cpufreq_hw 2>; + capacity-dmips-mhz = <1894>; + dynamic-power-coefficient = <588>; + #cooling-cells = <2>; + L2_700: l2-cache { + compatible = "cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + + core4 { + cpu = <&CPU4>; + }; + + core5 { + cpu = <&CPU5>; + }; + + core6 { + cpu = <&CPU6>; + }; + + core7 { + cpu = <&CPU7>; + }; + }; + }; + + idle-states { + entry-method = "psci"; + + LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { + compatible = "arm,idle-state"; + idle-state-name = "silver-rail-power-collapse"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <800>; + exit-latency-us = <750>; + min-residency-us = <4090>; + local-timer-stop; + }; + + BIG_CPU_SLEEP_0: cpu-sleep-1-0 { + compatible = "arm,idle-state"; + idle-state-name = "gold-rail-power-collapse"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <600>; + exit-latency-us = <1550>; + min-residency-us = <4791>; + local-timer-stop; + }; + }; + + domain-idle-states { + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x41000044>; + entry-latency-us = <1050>; + exit-latency-us = <2500>; + min-residency-us = <5309>; + }; + + CLUSTER_SLEEP_1: cluster-sleep-1 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x4100c344>; + entry-latency-us = <2700>; + exit-latency-us = <3500>; + min-residency-us = <13959>; + }; + }; + }; + + firmware { + scm: scm { + compatible = "qcom,scm-sm8550", "qcom,scm"; + interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; + }; + }; + + clk_virt: interconnect-0 { + compatible = "qcom,sm8550-clk-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mc_virt: interconnect-1 { + compatible = "qcom,sm8550-mc-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + memory@a0000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0 0xa0000000 0 0>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + + CPU_PD0: power-domain-cpu0 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD1: power-domain-cpu1 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD2: power-domain-cpu2 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD3: power-domain-cpu3 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD4: power-domain-cpu4 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD5: power-domain-cpu5 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD6: power-domain-cpu6 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD7: power-domain-cpu7 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CLUSTER_PD: power-domain-cluster { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>; + }; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_mem: hyp-region@80000000 { + reg = <0 0x80000000 0 0xa00000>; + no-map; + }; + + cpusys_vm_mem: cpusys-vm-region@80a00000 { + reg = <0 0x80a00000 0 0x400000>; + no-map; + }; + + hyp_tags_mem: hyp-tags-region@80e00000 { + reg = <0 0x80e00000 0 0x3d0000>; + no-map; + }; + + xbl_sc_mem: xbl-sc-region@d8100000 { + reg = <0 0xd8100000 0 0x40000>; + no-map; + }; + + + hyp_tags_reserved_mem: hyp-tags-reserved-region@811d0000 { + reg = <0 0x811d0000 0 0x30000>; + no-map; + }; + + /* merged xbl_dt_log, xbl_ramdump, aop_image */ + xbl_dt_log_merged_mem: xbl-dt-log-merged-region@81a00000 { + reg = <0 0x81a00000 0 0x260000>; + no-map; + }; + + aop_cmd_db_mem: aop-cmd-db-region@81c60000 { + compatible = "qcom,cmd-db"; + reg = <0 0x81c60000 0 0x20000>; + no-map; + }; + + /* merged aop_config, tme_crash_dump, tme_log, uefi_log */ + aop_config_merged_mem: aop-config-merged-region@81c80000 { + reg = <0 0x81c80000 0 0x74000>; + no-map; + }; + + /* secdata region can be reused by apps */ + smem: smem@81d00000 { + compatible = "qcom,smem"; + reg = <0 0x81d00000 0 0x200000>; + hwlocks = <&tcsr_mutex 3>; + no-map; + }; + + adsp_mhi_mem: adsp-mhi-region@81f00000 { + reg = <0 0x81f00000 0 0x20000>; + no-map; + }; + + global_sync_mem: global-sync-region@82600000 { + reg = <0 0x82600000 0 0x100000>; + no-map; + }; + + tz_stat_mem: tz-stat-region@82700000 { + reg = <0 0x82700000 0 0x100000>; + no-map; + }; + + cdsp_secure_heap_mem: cdsp-secure-heap-region@82800000 { + reg = <0 0x82800000 0 0x4600000>; + no-map; + }; + + mpss_mem: mpss-region@8a800000 { + reg = <0 0x8a800000 0 0x10800000>; + no-map; + }; + + q6_mpss_dtb_mem: q6-mpss-dtb-region@9b000000 { + reg = <0 0x9b000000 0 0x80000>; + no-map; + }; + + ipa_fw_mem: ipa-fw-region@9b080000 { + reg = <0 0x9b080000 0 0x10000>; + no-map; + }; + + ipa_gsi_mem: ipa-gsi-region@9b090000 { + reg = <0 0x9b090000 0 0xa000>; + no-map; + }; + + gpu_micro_code_mem: gpu-micro-code-region@9b09a000 { + reg = <0 0x9b09a000 0 0x2000>; + no-map; + }; + + spss_region_mem: spss-region@9b100000 { + reg = <0 0x9b100000 0 0x180000>; + no-map; + }; + + /* First part of the "SPU secure shared memory" region */ + spu_tz_shared_mem: spu-tz-shared-region@9b280000 { + reg = <0 0x9b280000 0 0x60000>; + no-map; + }; + + /* Second part of the "SPU secure shared memory" region */ + spu_modem_shared_mem: spu-modem-shared-region@9b2e0000 { + reg = <0 0x9b2e0000 0 0x20000>; + no-map; + }; + + camera_mem: camera-region@9b300000 { + reg = <0 0x9b300000 0 0x800000>; + no-map; + }; + + video_mem: video-region@9bb00000 { + reg = <0 0x9bb00000 0 0x700000>; + no-map; + }; + + cvp_mem: cvp-region@9c200000 { + reg = <0 0x9c200000 0 0x700000>; + no-map; + }; + + cdsp_mem: cdsp-region@9c900000 { + reg = <0 0x9c900000 0 0x2000000>; + no-map; + }; + + q6_cdsp_dtb_mem: q6-cdsp-dtb-region@9e900000 { + reg = <0 0x9e900000 0 0x80000>; + no-map; + }; + + q6_adsp_dtb_mem: q6-adsp-dtb-region@9e980000 { + reg = <0 0x9e980000 0 0x80000>; + no-map; + }; + + adspslpi_mem: adspslpi-region@9ea00000 { + reg = <0 0x9ea00000 0 0x4080000>; + no-map; + }; + + /* uefi region can be reused by apps */ + + /* Linux kernel image is loaded at 0xa8000000 */ + + rmtfs_mem: rmtfs-region@d4a80000 { + compatible = "qcom,rmtfs-mem"; + reg = <0x0 0xd4a80000 0x0 0x280000>; + no-map; + + qcom,client-id = <1>; + qcom,vmid = <15>; + }; + + mpss_dsm_mem: mpss-dsm-region@d4d00000 { + reg = <0 0xd4d00000 0 0x3300000>; + no-map; + }; + + tz_reserved_mem: tz-reserved-region@d8000000 { + reg = <0 0xd8000000 0 0x100000>; + no-map; + }; + + cpucp_fw_mem: cpucp-fw-region@d8140000 { + reg = <0 0xd8140000 0 0x1c0000>; + no-map; + }; + + qtee_mem: qtee-region@d8300000 { + reg = <0 0xd8300000 0 0x500000>; + no-map; + }; + + ta_mem: ta-region@d8800000 { + reg = <0 0xd8800000 0 0x8a00000>; + no-map; + }; + + tz_tags_mem: tz-tags-region@e1200000 { + reg = <0 0xe1200000 0 0x2740000>; + no-map; + }; + + hwfence_shbuf: hwfence-shbuf-region@e6440000 { + reg = <0 0xe6440000 0 0x279000>; + no-map; + }; + + trust_ui_vm_mem: trust-ui-vm-region@f3600000 { + reg = <0 0xf3600000 0 0x4aee000>; + no-map; + }; + + trust_ui_vm_dump: trust-ui-vm-dump-region@f80ee000 { + reg = <0 0xf80ee000 0 0x1000>; + no-map; + }; + + trust_ui_vm_qrtr: trust-ui-vm-qrt-region@f80ef000 { + reg = <0 0xf80ef000 0 0x9000>; + no-map; + }; + + trust_ui_vm_vblk0_ring: trust-ui-vm-vblk0-ring-region@f80f8000 { + reg = <0 0xf80f8000 0 0x4000>; + no-map; + }; + + trust_ui_vm_vblk1_ring: trust-ui-vm-vblk1-ring-region@f80fc000 { + reg = <0 0xf80fc000 0 0x4000>; + no-map; + }; + + trust_ui_vm_swiotlb: trust-ui-vm-swiotlb-region@f8100000 { + reg = <0 0xf8100000 0 0x100000>; + no-map; + }; + + oem_vm_mem: oem-vm-region@f8400000 { + reg = <0 0xf8400000 0 0x4800000>; + no-map; + }; + + oem_vm_vblk0_ring: oem-vm-vblk0-ring-region@fcc00000 { + reg = <0 0xfcc00000 0 0x4000>; + no-map; + }; + + oem_vm_swiotlb: oem-vm-swiotlb-region@fcc04000 { + reg = <0 0xfcc04000 0 0x100000>; + no-map; + }; + + hyp_ext_tags_mem: hyp-ext-tags-region@fce00000 { + reg = <0 0xfce00000 0 0x2900000>; + no-map; + }; + + hyp_ext_reserved_mem: hyp-ext-reserved-region@ff700000 { + reg = <0 0xff700000 0 0x100000>; + no-map; + }; + }; + + smp2p-adsp { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + smp2p_adsp_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_adsp_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-cdsp { + compatible = "qcom,smp2p"; + qcom,smem = <94>, <432>; + interrupts-extended = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid = <0>; + qcom,remote-pid = <5>; + + smp2p_cdsp_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_cdsp_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-modem { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + interrupts-extended = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + smp2p_modem_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_modem_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + ipa_smp2p_out: ipa-ap-to-modem { + qcom,entry-name = "ipa"; + #qcom,smem-state-cells = <1>; + }; + + ipa_smp2p_in: ipa-modem-to-ap { + qcom,entry-name = "ipa"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + soc: soc@0 { + compatible = "simple-bus"; + ranges = <0 0 0 0 0x10 0>; + dma-ranges = <0 0 0 0 0x10 0>; + + #address-cells = <2>; + #size-cells = <2>; + + gcc: clock-controller@100000 { + compatible = "qcom,sm8550-gcc"; + reg = <0 0x00100000 0 0x1f4200>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + clocks = <&bi_tcxo_div2>, <&sleep_clk>, + <&pcie0_phy>, + <&pcie1_phy>, + <&pcie_1_phy_aux_clk>, + <&ufs_mem_phy 0>, + <&ufs_mem_phy 1>, + <&ufs_mem_phy 2>, + <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; + }; + + ipcc: mailbox@408000 { + compatible = "qcom,sm8550-ipcc", "qcom,ipcc"; + reg = <0 0x00408000 0 0x1000>; + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + }; + + gpi_dma2: dma-controller@800000 { + compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma"; + #dma-cells = <3>; + reg = <0 0x00800000 0 0x60000>; + interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; + dma-channels = <12>; + dma-channel-mask = <0x3e>; + iommus = <&apps_smmu 0x436 0>; + status = "disabled"; + }; + + qupv3_id_1: geniqup@8c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0 0x008c0000 0 0x2000>; + ranges; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + iommus = <&apps_smmu 0x423 0>; + #address-cells = <2>; + #size-cells = <2>; + status = "disabled"; + + i2c8: i2c@880000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00880000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c8_data_clk>; + interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, + <&gpi_dma2 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi8: spi@880000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00880000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, + <&gpi_dma2 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c9: i2c@884000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00884000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c9_data_clk>; + interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, + <&gpi_dma2 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi9: spi@884000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00884000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, + <&gpi_dma2 1 1 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c10: i2c@888000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00888000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c10_data_clk>; + interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, + <&gpi_dma2 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi10: spi@888000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00888000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, + <&gpi_dma2 1 2 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c11: i2c@88c000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x0088c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c11_data_clk>; + interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, + <&gpi_dma2 1 3 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi11: spi@88c000 { + compatible = "qcom,geni-spi"; + reg = <0 0x0088c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, + <&gpi_dma2 1 3 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c12: i2c@890000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00890000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c12_data_clk>; + interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, + <&gpi_dma2 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi12: spi@890000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00890000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, + <&gpi_dma2 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c13: i2c@894000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00894000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c13_data_clk>; + interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, + <&gpi_dma2 1 5 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi13: spi@894000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00894000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, + <&gpi_dma2 1 5 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c15: i2c@89c000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x0089c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c15_data_clk>; + interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>, + <&gpi_dma2 1 7 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi15: spi@89c000 { + compatible = "qcom,geni-spi"; + reg = <0 0x0089c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; + interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>, + <&gpi_dma2 1 7 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + i2c_master_hub_0: geniqup@9c0000 { + compatible = "qcom,geni-se-i2c-master-hub"; + reg = <0x0 0x009c0000 0x0 0x2000>; + clock-names = "s-ahb"; + clocks = <&gcc GCC_QUPV3_I2C_S_AHB_CLK>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + i2c_hub_0: i2c@980000 { + compatible = "qcom,geni-i2c-master-hub"; + reg = <0x0 0x00980000 0x0 0x4000>; + clock-names = "se", "core"; + clocks = <&gcc GCC_QUPV3_I2C_S0_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&hub_i2c0_data_clk>; + interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c_hub_1: i2c@984000 { + compatible = "qcom,geni-i2c-master-hub"; + reg = <0x0 0x00984000 0x0 0x4000>; + clock-names = "se", "core"; + clocks = <&gcc GCC_QUPV3_I2C_S1_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&hub_i2c1_data_clk>; + interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c_hub_2: i2c@988000 { + compatible = "qcom,geni-i2c-master-hub"; + reg = <0x0 0x00988000 0x0 0x4000>; + clock-names = "se", "core"; + clocks = <&gcc GCC_QUPV3_I2C_S2_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&hub_i2c2_data_clk>; + interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c_hub_3: i2c@98c000 { + compatible = "qcom,geni-i2c-master-hub"; + reg = <0x0 0x0098c000 0x0 0x4000>; + clock-names = "se", "core"; + clocks = <&gcc GCC_QUPV3_I2C_S3_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&hub_i2c3_data_clk>; + interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c_hub_4: i2c@990000 { + compatible = "qcom,geni-i2c-master-hub"; + reg = <0x0 0x00990000 0x0 0x4000>; + clock-names = "se", "core"; + clocks = <&gcc GCC_QUPV3_I2C_S4_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&hub_i2c4_data_clk>; + interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c_hub_5: i2c@994000 { + compatible = "qcom,geni-i2c-master-hub"; + reg = <0 0x00994000 0 0x4000>; + clock-names = "se", "core"; + clocks = <&gcc GCC_QUPV3_I2C_S5_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&hub_i2c5_data_clk>; + interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c_hub_6: i2c@998000 { + compatible = "qcom,geni-i2c-master-hub"; + reg = <0 0x00998000 0 0x4000>; + clock-names = "se", "core"; + clocks = <&gcc GCC_QUPV3_I2C_S6_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&hub_i2c6_data_clk>; + interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c_hub_7: i2c@99c000 { + compatible = "qcom,geni-i2c-master-hub"; + reg = <0 0x0099c000 0 0x4000>; + clock-names = "se", "core"; + clocks = <&gcc GCC_QUPV3_I2C_S7_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&hub_i2c7_data_clk>; + interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c_hub_8: i2c@9a0000 { + compatible = "qcom,geni-i2c-master-hub"; + reg = <0 0x009a0000 0 0x4000>; + clock-names = "se", "core"; + clocks = <&gcc GCC_QUPV3_I2C_S8_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&hub_i2c8_data_clk>; + interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c_hub_9: i2c@9a4000 { + compatible = "qcom,geni-i2c-master-hub"; + reg = <0 0x009a4000 0 0x4000>; + clock-names = "se", "core"; + clocks = <&gcc GCC_QUPV3_I2C_S9_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&hub_i2c9_data_clk>; + interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_I2C 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + }; + + gpi_dma1: dma-controller@a00000 { + compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma"; + #dma-cells = <3>; + reg = <0 0x00a00000 0 0x60000>; + interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; + dma-channels = <12>; + dma-channel-mask = <0x1e>; + iommus = <&apps_smmu 0xb6 0>; + status = "disabled"; + }; + + qupv3_id_0: geniqup@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0 0x00ac0000 0 0x2000>; + ranges; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + iommus = <&apps_smmu 0xa3 0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>; + interconnect-names = "qup-core"; + #address-cells = <2>; + #size-cells = <2>; + status = "disabled"; + + i2c0: i2c@a80000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a80000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c0_data_clk>; + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, + <&gpi_dma1 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi0: spi@a80000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a80000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, + <&gpi_dma1 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@a84000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a84000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c1_data_clk>; + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, + <&gpi_dma1 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi1: spi@a84000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a84000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, + <&gpi_dma1 1 1 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@a88000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a88000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c2_data_clk>; + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, + <&gpi_dma1 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi2: spi@a88000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a88000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, + <&gpi_dma1 1 2 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@a8c000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a8c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c3_data_clk>; + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, + <&gpi_dma1 1 3 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi3: spi@a8c000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a8c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, + <&gpi_dma1 1 3 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@a90000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a90000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c4_data_clk>; + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, + <&gpi_dma1 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi4: spi@a90000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a90000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, + <&gpi_dma1 1 4 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@a94000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a94000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c5_data_clk>; + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, + <&gpi_dma1 1 5 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi5: spi@a94000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a94000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, + <&gpi_dma1 1 5 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c6: i2c@a98000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a98000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c6_data_clk>; + interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, + <&gpi_dma1 1 6 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi6: spi@a98000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a98000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, + <&gpi_dma1 1 6 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart7: serial@a9c000 { + compatible = "qcom,geni-debug-uart"; + reg = <0 0x00a9c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart7_default>; + interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; + interconnect-names = "qup-core", "qup-config"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; + status = "disabled"; + }; + }; + + cnoc_main: interconnect@1500000 { + compatible = "qcom,sm8550-cnoc-main"; + reg = <0 0x01500000 0 0x13080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + config_noc: interconnect@1600000 { + compatible = "qcom,sm8550-config-noc"; + reg = <0 0x01600000 0 0x6200>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + system_noc: interconnect@1680000 { + compatible = "qcom,sm8550-system-noc"; + reg = <0 0x01680000 0 0x1d080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + pcie_noc: interconnect@16c0000 { + compatible = "qcom,sm8550-pcie-anoc"; + reg = <0 0x016c0000 0 0x12200>; + #interconnect-cells = <2>; + clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, + <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre1_noc: interconnect@16e0000 { + compatible = "qcom,sm8550-aggre1-noc"; + reg = <0 0x016e0000 0 0x14400>; + #interconnect-cells = <2>; + clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre2_noc: interconnect@1700000 { + compatible = "qcom,sm8550-aggre2-noc"; + reg = <0 0x01700000 0 0x1e400>; + #interconnect-cells = <2>; + clocks = <&rpmhcc RPMH_IPA_CLK>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mmss_noc: interconnect@1780000 { + compatible = "qcom,sm8550-mmss-noc"; + reg = <0 0x01780000 0 0x5b800>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + pcie0: pci@1c00000 { + device_type = "pci"; + compatible = "qcom,pcie-sm8550"; + reg = <0 0x01c00000 0 0x3000>, + <0 0x60000000 0 0xf1d>, + <0 0x60000f20 0 0xa8>, + <0 0x60001000 0 0x1000>, + <0 0x60100000 0 0x100000>; + reg-names = "parf", "dbi", "elbi", "atu", "config"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; + bus-range = <0x00 0xff>; + + dma-coherent; + + linux,pci-domain = <0>; + num-lanes = <2>; + + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, + <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>; + clock-names = "pipe", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ddrss_sf_tbu", + "aggre0"; + + interconnect-names = "pcie-mem"; + interconnects = <&pcie_noc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>; + + iommus = <&apps_smmu 0x1400 0x7f>; + iommu-map = <0x0 &apps_smmu 0x1400 0x1>, + <0x100 &apps_smmu 0x1401 0x1>; + + resets = <&gcc GCC_PCIE_0_BCR>; + reset-names = "pci"; + + power-domains = <&gcc PCIE_0_GDSC>; + + phys = <&pcie0_phy>; + phy-names = "pciephy"; + + perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_default_state>; + + status = "disabled"; + }; + + pcie0_phy: phy@1c06000 { + compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy"; + reg = <0 0x01c06000 0 0x2000>; + + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&tcsr TCSR_PCIE_0_CLKREF_EN>, + <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_0_PIPE_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "rchng", + "pipe"; + + resets = <&gcc GCC_PCIE_0_PHY_BCR>; + reset-names = "phy"; + + assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + power-domains = <&gcc PCIE_0_PHY_GDSC>; + + #clock-cells = <0>; + clock-output-names = "pcie0_pipe_clk"; + + #phy-cells = <0>; + + status = "disabled"; + }; + + pcie1: pci@1c08000 { + device_type = "pci"; + compatible = "qcom,pcie-sm8550"; + reg = <0x0 0x01c08000 0x0 0x3000>, + <0x0 0x40000000 0x0 0xf1d>, + <0x0 0x40000f20 0x0 0xa8>, + <0x0 0x40001000 0x0 0x1000>, + <0x0 0x40100000 0x0 0x100000>; + reg-names = "parf", "dbi", "elbi", "atu", "config"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x40200000 0 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0 0x40300000 0x0 0x1fd00000>; + bus-range = <0x00 0xff>; + + dma-coherent; + + linux,pci-domain = <1>; + num-lanes = <2>; + + interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, + <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, + <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; + clock-names = "pipe", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ddrss_sf_tbu", + "aggre1", + "cnoc_pcie_sf_axi"; + + assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; + assigned-clock-rates = <19200000>; + + interconnect-names = "pcie-mem"; + interconnects = <&pcie_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>; + + iommus = <&apps_smmu 0x1480 0x7f>; + iommu-map = <0x0 &apps_smmu 0x1480 0x1>, + <0x100 &apps_smmu 0x1481 0x1>; + + resets = <&gcc GCC_PCIE_1_BCR>, + <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; + reset-names = "pci", + "pcie_1_link_down_reset"; + + power-domains = <&gcc PCIE_1_GDSC>; + + phys = <&pcie1_phy>; + phy-names = "pciephy"; + + perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; + enable-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_default_state>; + + status = "disabled"; + }; + + pcie1_phy: phy@1c0e000 { + compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy"; + reg = <0x0 0x01c0e000 0x0 0x2000>; + + clocks = <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&tcsr TCSR_PCIE_1_CLKREF_EN>, + <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_1_PIPE_CLK>, + <&gcc GCC_PCIE_1_PHY_AUX_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "rchng", + "pipe", "aux_phy"; + + resets = <&gcc GCC_PCIE_1_PHY_BCR>, + <&gcc GCC_PCIE_1_NOCSR_COM_PHY_BCR>; + reset-names = "phy", "nocsr"; + + assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + power-domains = <&gcc PCIE_1_PHY_GDSC>; + + #clock-cells = <0>; + clock-output-names = "pcie1_pipe_clk"; + + #phy-cells = <0>; + + status = "disabled"; + }; + + cryptobam: dma-controller@1dc4000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x0 0x01dc4000 0x0 0x28000>; + interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + qcom,ee = <0>; + qcom,controlled-remotely; + iommus = <&apps_smmu 0x480 0x0>, + <&apps_smmu 0x481 0x0>; + }; + + crypto: crypto@1de0000 { + compatible = "qcom,sm8550-qce"; + reg = <0x0 0x01dfa000 0x0 0x6000>; + dmas = <&cryptobam 4>, <&cryptobam 5>; + dma-names = "rx", "tx"; + iommus = <&apps_smmu 0x480 0x0>, + <&apps_smmu 0x481 0x0>; + interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "memory"; + }; + + ufs_mem_phy: phy@1d80000 { + compatible = "qcom,sm8550-qmp-ufs-phy"; + reg = <0x0 0x01d80000 0x0 0x2000>; + clocks = <&tcsr TCSR_UFS_CLKREF_EN>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + clock-names = "ref", "ref_aux"; + + power-domains = <&gcc UFS_MEM_PHY_GDSC>; + + resets = <&ufs_mem_hc 0>; + reset-names = "ufsphy"; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + + ufs_mem_hc: ufs@1d84000 { + compatible = "qcom,sm8550-ufshc", "qcom,ufshc", + "jedec,ufs-2.0"; + reg = <0x0 0x01d84000 0x0 0x3000>; + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; + phys = <&ufs_mem_phy>; + phy-names = "ufsphy"; + lanes-per-direction = <2>; + #reset-cells = <1>; + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + power-domains = <&gcc UFS_PHY_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + iommus = <&apps_smmu 0x60 0x0>; + + interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>; + + interconnect-names = "ufs-ddr", "cpu-ufs"; + clock-names = "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&tcsr TCSR_UFS_PAD_CLKREF_EN>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + freq-table-hz = + <75000000 300000000>, + <0 0>, + <0 0>, + <75000000 300000000>, + <100000000 403000000>, + <0 0>, + <0 0>, + <0 0>; + status = "disabled"; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + reg = <0 0x01f40000 0 0x20000>; + #hwlock-cells = <1>; + }; + + tcsr: clock-controller@1fc0000 { + compatible = "qcom,sm8550-tcsr", "syscon"; + reg = <0 0x01fc0000 0 0x30000>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + remoteproc_mpss: remoteproc@4080000 { + compatible = "qcom,sm8550-mpss-pas"; + reg = <0x0 0x04080000 0x0 0x4040>; + + interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", "handover", + "stop-ack", "shutdown-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd SM8550_CX>, + <&rpmhpd SM8550_MSS>; + power-domain-names = "cx", "mss"; + + interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; + + memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>, <&mpss_dsm_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_modem_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + label = "mpss"; + qcom,remote-pid = <1>; + }; + }; + + lpass_tlmm: pinctrl@6e80000 { + compatible = "qcom,sm8550-lpass-lpi-pinctrl"; + reg = <0 0x06e80000 0 0x20000>, + <0 0x0725a000 0 0x10000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpass_tlmm 0 0 23>; + + clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "core", "audio"; + }; + + lpass_lpiaon_noc: interconnect@7400000 { + compatible = "qcom,sm8550-lpass-lpiaon-noc"; + reg = <0 0x07400000 0 0x19080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + lpass_lpicx_noc: interconnect@7430000 { + compatible = "qcom,sm8550-lpass-lpicx-noc"; + reg = <0 0x07430000 0 0x3a200>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + lpass_ag_noc: interconnect@7e40000 { + compatible = "qcom,sm8550-lpass-ag-noc"; + reg = <0 0x07e40000 0 0xe080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + sdhc_2: mmc@8804000 { + compatible = "qcom,sm8550-sdhci", "qcom,sdhci-msm-v5"; + reg = <0 0x08804000 0 0x1000>; + + interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "core", "xo"; + iommus = <&apps_smmu 0x540 0>; + qcom,dll-config = <0x0007642c>; + qcom,ddr-config = <0x80040868>; + power-domains = <&rpmhpd SM8550_CX>; + operating-points-v2 = <&sdhc2_opp_table>; + + interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; + interconnect-names = "sdhc-ddr", "cpu-sdhc"; + bus-width = <4>; + dma-coherent; + + /* Forbid SDR104/SDR50 - broken hw! */ + sdhci-caps-mask = <0x3 0>; + + status = "disabled"; + + sdhc2_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-19200000 { + opp-hz = /bits/ 64 <19200000>; + required-opps = <&rpmhpd_opp_min_svs>; + }; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-202000000 { + opp-hz = /bits/ 64 <202000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + mdss: display-subsystem@ae00000 { + compatible = "qcom,sm8550-mdss"; + reg = <0 0x0ae00000 0 0x1000>; + reg-names = "mdss"; + + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; + + power-domains = <&dispcc MDSS_GDSC>; + + interconnects = <&mmss_noc MASTER_MDP 0 &gem_noc SLAVE_LLCC 0>, + <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "mdp0-mem", "mdp1-mem"; + + iommus = <&apps_smmu 0x1c00 0x2>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + mdss_mdp: display-controller@ae01000 { + compatible = "qcom,sm8550-dpu"; + reg = <0 0x0ae01000 0 0x8f000>, + <0 0x0aeb0000 0 0x2008>; + reg-names = "mdp", "vbif"; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", + "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + power-domains = <&rpmhpd SM8550_MMCX>; + + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf2_out: endpoint { + remote-endpoint = <&mdss_dsi1_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-325000000 { + opp-hz = /bits/ 64 <325000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-375000000 { + opp-hz = /bits/ 64 <375000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-514000000 { + opp-hz = /bits/ 64 <514000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss_dsi0: dsi@ae94000 { + compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae94000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + power-domains = <&rpmhpd SM8550_MMCX>; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; + + operating-points-v2 = <&mdss_dsi_opp_table>; + + phys = <&mdss_dsi0_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dsi0_out: endpoint { + }; + }; + }; + + mdss_dsi_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + mdss_dsi0_phy: phy@ae95000 { + compatible = "qcom,sm8550-dsi-phy-4nm"; + reg = <0 0x0ae95000 0 0x200>, + <0 0x0ae95200 0 0x280>, + <0 0x0ae95500 0 0x400>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + + mdss_dsi1: dsi@ae96000 { + compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae96000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <5>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + power-domains = <&rpmhpd SM8550_MMCX>; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; + + operating-points-v2 = <&mdss_dsi_opp_table>; + + phys = <&mdss_dsi1_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dsi1_in: endpoint { + remote-endpoint = <&dpu_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dsi1_out: endpoint { + }; + }; + }; + }; + + mdss_dsi1_phy: phy@ae97000 { + compatible = "qcom,sm8550-dsi-phy-4nm"; + reg = <0 0x0ae97000 0 0x200>, + <0 0x0ae97200 0 0x280>, + <0 0x0ae97500 0 0x400>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + }; + + dispcc: clock-controller@af00000 { + compatible = "qcom,sm8550-dispcc"; + reg = <0 0x0af00000 0 0x20000>; + clocks = <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&gcc GCC_DISP_AHB_CLK>, + <&sleep_clk>, + <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>, + <&mdss_dsi1_phy 0>, + <&mdss_dsi1_phy 1>, + <0>, /* dp0 */ + <0>, + <0>, /* dp1 */ + <0>, + <0>, /* dp2 */ + <0>, + <0>, /* dp3 */ + <0>; + power-domains = <&rpmhpd SM8550_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + status = "disabled"; + }; + + usb_1_hsphy: phy@88e3000 { + compatible = "qcom,sm8550-snps-eusb2-phy"; + reg = <0x0 0x088e3000 0x0 0x154>; + #phy-cells = <0>; + + clocks = <&tcsr TCSR_USB2_CLKREF_EN>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + + status = "disabled"; + }; + + usb_dp_qmpphy: phy@88e8000 { + compatible = "qcom,sm8550-qmp-usb3-dp-phy"; + reg = <0x0 0x088e8000 0x0 0x3000>; + + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "aux", "ref", "com_aux", "usb3_pipe"; + + power-domains = <&gcc USB3_PHY_GDSC>; + + resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, + <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; + reset-names = "phy", "common"; + + #clock-cells = <1>; + #phy-cells = <1>; + + status = "disabled"; + }; + + usb_1: usb@a6f8800 { + compatible = "qcom,sm8550-dwc3", "qcom,dwc3"; + reg = <0x0 0x0a6f8800 0x0 0x400>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&tcsr TCSR_USB3_CLKREF_EN>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "xo"; + + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 15 IRQ_TYPE_EDGE_RISING>, + <&pdc 14 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "hs_phy_irq", + "ss_phy_irq", + "dm_hs_phy_irq", + "dp_hs_phy_irq"; + + power-domains = <&gcc USB30_PRIM_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + + status = "disabled"; + + usb_1_dwc3: usb@a600000 { + compatible = "snps,dwc3"; + reg = <0x0 0x0a600000 0x0 0xcd00>; + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; + iommus = <&apps_smmu 0x40 0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,usb3_lpm_capable; + phys = <&usb_1_hsphy>, + <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; + phy-names = "usb2-phy", "usb3-phy"; + }; + }; + + pdc: interrupt-controller@b220000 { + compatible = "qcom,sm8550-pdc", "qcom,pdc"; + reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; + qcom,pdc-ranges = <0 480 94>, <94 609 31>, + <125 63 1>, <126 716 12>, + <138 251 5>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + + tsens0: thermal-sensor@c271000 { + compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; + reg = <0 0x0c271000 0 0x1000>, /* TM */ + <0 0x0c222000 0 0x1000>; /* SROT */ + #qcom,sensors = <16>; + interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow", "critical"; + #thermal-sensor-cells = <1>; + }; + + tsens1: thermal-sensor@c272000 { + compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; + reg = <0 0x0c272000 0 0x1000>, /* TM */ + <0 0x0c223000 0 0x1000>; /* SROT */ + #qcom,sensors = <16>; + interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow", "critical"; + #thermal-sensor-cells = <1>; + }; + + tsens2: thermal-sensor@c273000 { + compatible = "qcom,sm8550-tsens", "qcom,tsens-v2"; + reg = <0 0x0c273000 0 0x1000>, /* TM */ + <0 0x0c224000 0 0x1000>; /* SROT */ + #qcom,sensors = <16>; + interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow", "critical"; + #thermal-sensor-cells = <1>; + }; + + aoss_qmp: power-management@c300000 { + compatible = "qcom,sm8550-aoss-qmp", "qcom,aoss-qmp"; + reg = <0 0x0c300000 0 0x400>; + interrupt-parent = <&ipcc>; + interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; + + #clock-cells = <0>; + }; + + sram@c3f0000 { + compatible = "qcom,rpmh-stats"; + reg = <0 0x0c3f0000 0 0x400>; + }; + + spmi_bus: spmi@c400000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0 0x0c400000 0 0x3000>, + <0 0x0c500000 0 0x4000000>, + <0 0x0c440000 0 0x80000>, + <0 0x0c4c0000 0 0x20000>, + <0 0x0c42d000 0 0x4000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + qcom,ee = <0>; + qcom,channel = <0>; + qcom,bus-id = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + }; + + tlmm: pinctrl@f000000 { + compatible = "qcom,sm8550-tlmm"; + reg = <0 0x0f100000 0 0x300000>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 211>; + wakeup-parent = <&pdc>; + + hub_i2c0_data_clk: hub-i2c0-data-clk-state { + /* SDA, SCL */ + pins = "gpio16", "gpio17"; + function = "i2chub0_se0"; + drive-strength = <2>; + bias-pull-up; + }; + + hub_i2c1_data_clk: hub-i2c1-data-clk-state { + /* SDA, SCL */ + pins = "gpio18", "gpio19"; + function = "i2chub0_se1"; + drive-strength = <2>; + bias-pull-up; + }; + + hub_i2c2_data_clk: hub-i2c2-data-clk-state { + /* SDA, SCL */ + pins = "gpio20", "gpio21"; + function = "i2chub0_se2"; + drive-strength = <2>; + bias-pull-up; + }; + + hub_i2c3_data_clk: hub-i2c3-data-clk-state { + /* SDA, SCL */ + pins = "gpio22", "gpio23"; + function = "i2chub0_se3"; + drive-strength = <2>; + bias-pull-up; + }; + + hub_i2c4_data_clk: hub-i2c4-data-clk-state { + /* SDA, SCL */ + pins = "gpio4", "gpio5"; + function = "i2chub0_se4"; + drive-strength = <2>; + bias-pull-up; + }; + + hub_i2c5_data_clk: hub-i2c5-data-clk-state { + /* SDA, SCL */ + pins = "gpio6", "gpio7"; + function = "i2chub0_se5"; + drive-strength = <2>; + bias-pull-up; + }; + + hub_i2c6_data_clk: hub-i2c6-data-clk-state { + /* SDA, SCL */ + pins = "gpio8", "gpio9"; + function = "i2chub0_se6"; + drive-strength = <2>; + bias-pull-up; + }; + + hub_i2c7_data_clk: hub-i2c7-data-clk-state { + /* SDA, SCL */ + pins = "gpio10", "gpio11"; + function = "i2chub0_se7"; + drive-strength = <2>; + bias-pull-up; + }; + + hub_i2c8_data_clk: hub-i2c8-data-clk-state { + /* SDA, SCL */ + pins = "gpio206", "gpio207"; + function = "i2chub0_se8"; + drive-strength = <2>; + bias-pull-up; + }; + + hub_i2c9_data_clk: hub-i2c9-data-clk-state { + /* SDA, SCL */ + pins = "gpio84", "gpio85"; + function = "i2chub0_se9"; + drive-strength = <2>; + bias-pull-up; + }; + + pcie0_default_state: pcie0-default-state { + perst-pins { + pins = "gpio94"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + clkreq-pins { + pins = "gpio95"; + function = "pcie0_clk_req_n"; + drive-strength = <2>; + bias-pull-up; + }; + + wake-pins { + pins = "gpio96"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie1_default_state: pcie1-default-state { + perst-pins { + pins = "gpio97"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + clkreq-pins { + pins = "gpio98"; + function = "pcie1_clk_req_n"; + drive-strength = <2>; + bias-pull-up; + }; + + wake-pins { + pins = "gpio99"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qup_i2c0_data_clk: qup-i2c0-data-clk-state { + /* SDA, SCL */ + pins = "gpio28", "gpio29"; + function = "qup1_se0"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c1_data_clk: qup-i2c1-data-clk-state { + /* SDA, SCL */ + pins = "gpio32", "gpio33"; + function = "qup1_se1"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c2_data_clk: qup-i2c2-data-clk-state { + /* SDA, SCL */ + pins = "gpio36", "gpio37"; + function = "qup1_se2"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c3_data_clk: qup-i2c3-data-clk-state { + /* SDA, SCL */ + pins = "gpio40", "gpio41"; + function = "qup1_se3"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c4_data_clk: qup-i2c4-data-clk-state { + /* SDA, SCL */ + pins = "gpio44", "gpio45"; + function = "qup1_se4"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c5_data_clk: qup-i2c5-data-clk-state { + /* SDA, SCL */ + pins = "gpio52", "gpio53"; + function = "qup1_se5"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c6_data_clk: qup-i2c6-data-clk-state { + /* SDA, SCL */ + pins = "gpio48", "gpio49"; + function = "qup1_se6"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c8_data_clk: qup-i2c8-data-clk-state { + scl-pins { + pins = "gpio57"; + function = "qup2_se0_l1_mira"; + drive-strength = <2>; + bias-pull-up; + }; + + sda-pins { + pins = "gpio56"; + function = "qup2_se0_l0_mira"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qup_i2c9_data_clk: qup-i2c9-data-clk-state { + /* SDA, SCL */ + pins = "gpio60", "gpio61"; + function = "qup2_se1"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c10_data_clk: qup-i2c10-data-clk-state { + /* SDA, SCL */ + pins = "gpio64", "gpio65"; + function = "qup2_se2"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c11_data_clk: qup-i2c11-data-clk-state { + /* SDA, SCL */ + pins = "gpio68", "gpio69"; + function = "qup2_se3"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c12_data_clk: qup-i2c12-data-clk-state { + /* SDA, SCL */ + pins = "gpio2", "gpio3"; + function = "qup2_se4"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c13_data_clk: qup-i2c13-data-clk-state { + /* SDA, SCL */ + pins = "gpio80", "gpio81"; + function = "qup2_se5"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c15_data_clk: qup-i2c15-data-clk-state { + /* SDA, SCL */ + pins = "gpio72", "gpio106"; + function = "qup2_se7"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi0_cs: qup-spi0-cs-state { + cs-pins { + pins = "gpio31"; + function = "qup1_se0"; + }; + }; + + qup_spi0_data_clk: qup-spi0-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio28", "gpio29", "gpio30"; + function = "qup1_se0"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi1_cs: qup-spi1-cs-state { + pins = "gpio35"; + function = "qup1_se1"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi1_data_clk: qup-spi1-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio32", "gpio33", "gpio34"; + function = "qup1_se1"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi2_cs: qup-spi2-cs-state { + pins = "gpio39"; + function = "qup1_se2"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi2_data_clk: qup-spi2-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio36", "gpio37", "gpio38"; + function = "qup1_se2"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi3_cs: qup-spi3-cs-state { + pins = "gpio43"; + function = "qup1_se3"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi3_data_clk: qup-spi3-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio40", "gpio41", "gpio42"; + function = "qup1_se3"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi4_cs: qup-spi4-cs-state { + pins = "gpio47"; + function = "qup1_se4"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi4_data_clk: qup-spi4-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio44", "gpio45", "gpio46"; + function = "qup1_se4"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi5_cs: qup-spi5-cs-state { + pins = "gpio55"; + function = "qup1_se5"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi5_data_clk: qup-spi5-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio52", "gpio53", "gpio54"; + function = "qup1_se5"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi6_cs: qup-spi6-cs-state { + pins = "gpio51"; + function = "qup1_se6"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi6_data_clk: qup-spi6-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio48", "gpio49", "gpio50"; + function = "qup1_se6"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi8_cs: qup-spi8-cs-state { + pins = "gpio59"; + function = "qup2_se0_l3_mira"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi8_data_clk: qup-spi8-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio56", "gpio57", "gpio58"; + function = "qup2_se0_l2_mira"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi9_cs: qup-spi9-cs-state { + pins = "gpio63"; + function = "qup2_se1"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi9_data_clk: qup-spi9-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio60", "gpio61", "gpio62"; + function = "qup2_se1"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi10_cs: qup-spi10-cs-state { + pins = "gpio67"; + function = "qup2_se2"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi10_data_clk: qup-spi10-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio64", "gpio65", "gpio66"; + function = "qup2_se2"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi11_cs: qup-spi11-cs-state { + pins = "gpio71"; + function = "qup2_se3"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi11_data_clk: qup-spi11-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio68", "gpio69", "gpio70"; + function = "qup2_se3"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi12_cs: qup-spi12-cs-state { + pins = "gpio119"; + function = "qup2_se4"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi12_data_clk: qup-spi12-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio2", "gpio3", "gpio118"; + function = "qup2_se4"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi13_cs: qup-spi13-cs-state { + pins = "gpio83"; + function = "qup2_se5"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi13_data_clk: qup-spi13-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio80", "gpio81", "gpio82"; + function = "qup2_se5"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi15_cs: qup-spi15-cs-state { + pins = "gpio75"; + function = "qup2_se7"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi15_data_clk: qup-spi15-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio72", "gpio106", "gpio74"; + function = "qup2_se7"; + drive-strength = <6>; + bias-disable; + }; + + qup_uart7_default: qup-uart7-default-state { + /* TX, RX */ + pins = "gpio26", "gpio27"; + function = "qup1_se7"; + drive-strength = <2>; + bias-disable; + }; + + sdc2_sleep: sdc2-sleep-state { + clk-pins { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd-pins { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data-pins { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + sdc2_default: sdc2-default-state { + clk-pins { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd-pins { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data-pins { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <10>; + }; + }; + }; + + apps_smmu: iommu@15000000 { + compatible = "qcom,sm8550-smmu-500", "qcom,smmu-500", "arm,mmu-500"; + reg = <0 0x15000000 0 0x100000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>; + }; + + intc: interrupt-controller@17100000 { + compatible = "arm,gic-v3"; + reg = <0 0x17100000 0 0x10000>, /* GICD */ + <0 0x17180000 0 0x200000>; /* GICR * 8 */ + ranges; + #interrupt-cells = <3>; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0 0x40000>; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; + #address-cells = <2>; + #size-cells = <2>; + + gic_its: msi-controller@17140000 { + compatible = "arm,gic-v3-its"; + reg = <0 0x17140000 0 0x20000>; + msi-controller; + #msi-cells = <1>; + }; + }; + + timer@17420000 { + compatible = "arm,armv7-timer-mem"; + reg = <0 0x17420000 0 0x1000>; + ranges = <0 0 0 0x20000000>; + #address-cells = <1>; + #size-cells = <1>; + + frame@17421000 { + reg = <0x17421000 0x1000>, + <0x17422000 0x1000>; + frame-number = <0>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + }; + + frame@17423000 { + reg = <0x17423000 0x1000>; + frame-number = <1>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + frame@17425000 { + reg = <0x17425000 0x1000>; + frame-number = <2>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + frame@17427000 { + reg = <0x17427000 0x1000>; + frame-number = <3>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + frame@17429000 { + reg = <0x17429000 0x1000>; + frame-number = <4>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + frame@1742b000 { + reg = <0x1742b000 0x1000>; + frame-number = <5>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + frame@1742d000 { + reg = <0x1742d000 0x1000>; + frame-number = <6>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + }; + + apps_rsc: rsc@17a00000 { + label = "apps_rsc"; + compatible = "qcom,rpmh-rsc"; + reg = <0 0x17a00000 0 0x10000>, + <0 0x17a10000 0 0x10000>, + <0 0x17a20000 0 0x10000>, + <0 0x17a30000 0 0x10000>; + reg-names = "drv-0", "drv-1", "drv-2", "drv-3"; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <2>; + qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, + <WAKE_TCS 2>, <CONTROL_TCS 0>; + + apps_bcm_voter: bcm-voter { + compatible = "qcom,bcm-voter"; + }; + + rpmhcc: clock-controller { + compatible = "qcom,sm8550-rpmh-clk"; + #clock-cells = <1>; + clock-names = "xo"; + clocks = <&xo_board>; + }; + + rpmhpd: power-controller { + compatible = "qcom,sm8550-rpmhpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmhpd_opp_table>; + + rpmhpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmhpd_opp_ret: opp1 { + opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; + }; + + rpmhpd_opp_min_svs: opp2 { + opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; + }; + + rpmhpd_opp_low_svs: opp3 { + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; + }; + + rpmhpd_opp_svs: opp4 { + opp-level = <RPMH_REGULATOR_LEVEL_SVS>; + }; + + rpmhpd_opp_svs_l1: opp5 { + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; + }; + + rpmhpd_opp_nom: opp6 { + opp-level = <RPMH_REGULATOR_LEVEL_NOM>; + }; + + rpmhpd_opp_nom_l1: opp7 { + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; + }; + + rpmhpd_opp_nom_l2: opp8 { + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; + }; + + rpmhpd_opp_turbo: opp9 { + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; + }; + + rpmhpd_opp_turbo_l1: opp10 { + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; + }; + }; + }; + }; + + cpufreq_hw: cpufreq@17d91000 { + compatible = "qcom,sm8550-cpufreq-epss", "qcom,cpufreq-epss"; + reg = <0 0x17d91000 0 0x1000>, + <0 0x17d92000 0 0x1000>, + <0 0x17d93000 0 0x1000>; + reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; + clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; + #freq-domain-cells = <1>; + }; + + pmu@24091000 { + compatible = "qcom,sm8550-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; + reg = <0 0x24091000 0 0x1000>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; + interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; + + operating-points-v2 = <&llcc_bwmon_opp_table>; + + llcc_bwmon_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-0 { + opp-peak-kBps = <2086000>; + }; + + opp-1 { + opp-peak-kBps = <2929000>; + }; + + opp-2 { + opp-peak-kBps = <5931000>; + }; + + opp-3 { + opp-peak-kBps = <6515000>; + }; + + opp-4 { + opp-peak-kBps = <7980000>; + }; + + opp-5 { + opp-peak-kBps = <10437000>; + }; + + opp-6 { + opp-peak-kBps = <12157000>; + }; + + opp-7 { + opp-peak-kBps = <14060000>; + }; + + opp-8 { + opp-peak-kBps = <16113000>; + }; + }; + }; + + pmu@240b6400 { + compatible = "qcom,sm8550-cpu-bwmon", "qcom,msm8998-bwmon"; + reg = <0 0x240b6400 0 0x600>; + interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; + interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; + + operating-points-v2 = <&cpu_bwmon_opp_table>; + + cpu_bwmon_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-0 { + opp-peak-kBps = <4577000>; + }; + + opp-1 { + opp-peak-kBps = <7110000>; + }; + + opp-2 { + opp-peak-kBps = <9155000>; + }; + + opp-3 { + opp-peak-kBps = <12298000>; + }; + + opp-4 { + opp-peak-kBps = <14236000>; + }; + + opp-5 { + opp-peak-kBps = <16265000>; + }; + }; + }; + + gem_noc: interconnect@24100000 { + compatible = "qcom,sm8550-gem-noc"; + reg = <0 0x24100000 0 0xbb800>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + system-cache-controller@25000000 { + compatible = "qcom,sm8550-llcc"; + reg = <0 0x25000000 0 0x800000>, + <0 0x25800000 0 0x200000>; + reg-names = "llcc_base", "llcc_broadcast_base"; + interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; + }; + + remoteproc_adsp: remoteproc@30000000 { + compatible = "qcom,sm8550-adsp-pas"; + reg = <0x0 0x30000000 0x0 0x100>; + + interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd SM8550_LCX>, + <&rpmhpd SM8550_LMX>; + power-domain-names = "lcx", "lmx"; + + interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC 0 &mc_virt SLAVE_EBI1 0>; + + memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_adsp_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + remoteproc_adsp_glink: glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "lpass"; + qcom,remote-pid = <2>; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "adsp"; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x1003 0x80>, + <&apps_smmu 0x1063 0x0>; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x1004 0x80>, + <&apps_smmu 0x1064 0x0>; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x1005 0x80>, + <&apps_smmu 0x1065 0x0>; + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + iommus = <&apps_smmu 0x1006 0x80>, + <&apps_smmu 0x1066 0x0>; + }; + + compute-cb@7 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <7>; + iommus = <&apps_smmu 0x1007 0x80>, + <&apps_smmu 0x1067 0x0>; + }; + }; + + gpr { + compatible = "qcom,gpr"; + qcom,glink-channels = "adsp_apps"; + qcom,domain = <GPR_DOMAIN_ID_ADSP>; + qcom,intents = <512 20>; + #address-cells = <1>; + #size-cells = <0>; + + q6apm: service@1 { + compatible = "qcom,q6apm"; + reg = <GPR_APM_MODULE_IID>; + #sound-dai-cells = <0>; + qcom,protection-domain = "avs/audio", + "msm/adsp/audio_pd"; + + q6apmdai: dais { + compatible = "qcom,q6apm-dais"; + iommus = <&apps_smmu 0x1001 0x80>, + <&apps_smmu 0x1061 0x0>; + }; + + q6apmbedai: bedais { + compatible = "qcom,q6apm-lpass-dais"; + #sound-dai-cells = <1>; + }; + }; + + q6prm: service@2 { + compatible = "qcom,q6prm"; + reg = <GPR_PRM_MODULE_IID>; + qcom,protection-domain = "avs/audio", + "msm/adsp/audio_pd"; + + q6prmcc: clock-controller { + compatible = "qcom,q6prm-lpass-clocks"; + #clock-cells = <2>; + }; + }; + }; + }; + }; + + nsp_noc: interconnect@320c0000 { + compatible = "qcom,sm8550-nsp-noc"; + reg = <0 0x320c0000 0 0xe080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + remoteproc_cdsp: remoteproc@32300000 { + compatible = "qcom,sm8550-cdsp-pas"; + reg = <0x0 0x32300000 0x0 0x1400000>; + + interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd SM8550_CX>, + <&rpmhpd SM8550_MXC>, + <&rpmhpd SM8550_NSP>; + power-domain-names = "cx", "mxc", "nsp"; + + interconnects = <&nsp_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; + + memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_cdsp_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "cdsp"; + qcom,remote-pid = <5>; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "cdsp"; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <1>; + iommus = <&apps_smmu 0x1961 0x0>, + <&apps_smmu 0x0c01 0x20>, + <&apps_smmu 0x19c1 0x10>; + }; + + compute-cb@2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <2>; + iommus = <&apps_smmu 0x1962 0x0>, + <&apps_smmu 0x0c02 0x20>, + <&apps_smmu 0x19c2 0x10>; + }; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x1963 0x0>, + <&apps_smmu 0x0c03 0x20>, + <&apps_smmu 0x19c3 0x10>; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x1964 0x0>, + <&apps_smmu 0x0c04 0x20>, + <&apps_smmu 0x19c4 0x10>; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x1965 0x0>, + <&apps_smmu 0x0c05 0x20>, + <&apps_smmu 0x19c5 0x10>; + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + iommus = <&apps_smmu 0x1966 0x0>, + <&apps_smmu 0x0c06 0x20>, + <&apps_smmu 0x19c6 0x10>; + }; + + compute-cb@7 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <7>; + iommus = <&apps_smmu 0x1967 0x0>, + <&apps_smmu 0x0c07 0x20>, + <&apps_smmu 0x19c7 0x10>; + }; + + compute-cb@8 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <8>; + iommus = <&apps_smmu 0x1968 0x0>, + <&apps_smmu 0x0c08 0x20>, + <&apps_smmu 0x19c8 0x10>; + }; + + /* note: secure cb9 in downstream */ + }; + }; + }; + }; + + thermal-zones { + aoss0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 0>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 1>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 2>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss2-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 3>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss3-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 4>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu3-top-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 5>; + + trips { + cpu3_top_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu3_top_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu3_top_crit: cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu3-bottom-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 6>; + + trips { + cpu3_bottom_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu3_bottom_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu3_bottom_crit: cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu4-top-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 7>; + + trips { + cpu4_top_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu4_top_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu4_top_crit: cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu4-bottom-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 8>; + + trips { + cpu4_bottom_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu4_bottom_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu4_bottom_crit: cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu5-top-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 9>; + + trips { + cpu5_top_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu5_top_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu5_top_crit: cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu5-bottom-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 10>; + + trips { + cpu5_bottom_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu5_bottom_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu5_bottom_crit: cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu6-top-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 11>; + + trips { + cpu6_top_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu6_top_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu6_top_crit: cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu6-bottom-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 12>; + + trips { + cpu6_bottom_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu6_bottom_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu6_bottom_crit: cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu7-top-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 13>; + + trips { + cpu7_top_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu7_top_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu7_top_crit: cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu7-middle-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 14>; + + trips { + cpu7_middle_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu7_middle_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu7_middle_crit: cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu7-bottom-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 15>; + + trips { + cpu7_bottom_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu7_bottom_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu7_bottom_crit: cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + aoss1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 0>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 1>; + + trips { + cpu0_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu0_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu0_crit: cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 2>; + + trips { + cpu1_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu1_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu1_crit: cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu2-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 3>; + + trips { + cpu2_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu2_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu2_crit: cpu-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cdsp0-thermal { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens2 4>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + cdsp0_junction_config: junction-config { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cdsp1-thermal { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens2 5>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + cdsp1_junction_config: junction-config { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cdsp2-thermal { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens2 6>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + cdsp2_junction_config: junction-config { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cdsp3-thermal { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens2 7>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + cdsp3_junction_config: junction-config { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + video-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 8>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + mem-thermal { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens1 9>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + ddr_config0: ddr0-config { + temperature = <90000>; + hysteresis = <5000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + modem0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 10>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + mdmss0_config0: mdmss0-config0 { + temperature = <102000>; + hysteresis = <3000>; + type = "passive"; + }; + + mdmss0_config1: mdmss0-config1 { + temperature = <105000>; + hysteresis = <3000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + modem1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 11>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + mdmss1_config0: mdmss1-config0 { + temperature = <102000>; + hysteresis = <3000>; + type = "passive"; + }; + + mdmss1_config1: mdmss1-config1 { + temperature = <105000>; + hysteresis = <3000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + modem2-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 12>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + mdmss2_config0: mdmss2-config0 { + temperature = <102000>; + hysteresis = <3000>; + type = "passive"; + }; + + mdmss2_config1: mdmss2-config1 { + temperature = <105000>; + hysteresis = <3000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + modem3-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 13>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + mdmss3_config0: mdmss3-config0 { + temperature = <102000>; + hysteresis = <3000>; + type = "passive"; + }; + + mdmss3_config1: mdmss3-config1 { + temperature = <105000>; + hysteresis = <3000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + camera0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 14>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + camera1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 15>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + aoss2-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens2 0>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + gpuss-0-thermal { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens2 1>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + gpu0_junction_config: junction-config { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + gpuss-1-thermal { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens2 2>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + gpu1_junction_config: junction-config { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + gpuss-2-thermal { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens2 3>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + gpu2_junction_config: junction-config { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + gpuss-3-thermal { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens2 4>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + gpu3_junction_config: junction-config { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + gpuss-4-thermal { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens2 5>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + gpu4_junction_config: junction-config { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + gpuss-5-thermal { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens2 6>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + gpu5_junction_config: junction-config { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + gpuss-6-thermal { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens2 7>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + gpu6_junction_config: junction-config { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + gpuss-7-thermal { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens2 8>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-config { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + gpu7_junction_config: junction-config { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; + }; +}; |