diff options
Diffstat (limited to 'arch/arm64/boot/dts/qcom/msm8996.dtsi')
-rw-r--r-- | arch/arm64/boot/dts/qcom/msm8996.dtsi | 33 |
1 files changed, 23 insertions, 10 deletions
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 7ae082ea14ea..14827adebd94 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -443,10 +443,13 @@ #reset-cells = <1>; #power-domain-cells = <1>; reg = <0x00300000 0x90000>; + + clocks = <&rpmcc RPM_SMD_LN_BB_CLK>; + clock-names = "cxo2"; }; tsens0: thermal-sensor@4a9000 { - compatible = "qcom,msm8996-tsens"; + compatible = "qcom,msm8996-tsens", "qcom,tsens-v2"; reg = <0x004a9000 0x1000>, /* TM */ <0x004a8000 0x1000>; /* SROT */ #qcom,sensors = <13>; @@ -457,7 +460,7 @@ }; tsens1: thermal-sensor@4ad000 { - compatible = "qcom,msm8996-tsens"; + compatible = "qcom,msm8996-tsens", "qcom,tsens-v2"; reg = <0x004ad000 0x1000>, /* TM */ <0x004ac000 0x1000>; /* SROT */ #qcom,sensors = <8>; @@ -695,6 +698,7 @@ reg = <0x01010000 0x300000>; interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; + gpio-ranges = <&msmgpio 0 0 150>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; @@ -882,7 +886,7 @@ reg = <0x00624000 0x2500>; interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; - phys = <&ufsphy>; + phys = <&ufsphy_lane>; phy-names = "ufsphy"; power-domains = <&gcc UFS_GDSC>; @@ -934,16 +938,25 @@ }; ufsphy: phy@627000 { - compatible = "qcom,msm8996-ufs-phy-qmp-14nm"; - reg = <0x00627000 0xda8>; - reg-names = "phy_mem"; - #phy-cells = <0>; + compatible = "qcom,msm8996-qmp-ufs-phy"; + reg = <0x00627000 0x1c4>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_UFS_CLKREF_CLK>; + clock-names = "ref"; - clock-names = "ref_clk_src", "ref_clk"; - clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, - <&gcc GCC_UFS_CLKREF_CLK>; resets = <&ufshc 0>; + reset-names = "ufsphy"; status = "disabled"; + + ufsphy_lane: lanes@627400 { + reg = <0x627400 0x12c>, + <0x627600 0x200>, + <0x627c00 0x1b4>; + #phy-cells = <0>; + }; }; camss: camss@a00000 { |