diff options
Diffstat (limited to 'arch/arm/mach-spear3xx/include/mach/spear310.h')
| -rw-r--r-- | arch/arm/mach-spear3xx/include/mach/spear310.h | 44 |
1 files changed, 22 insertions, 22 deletions
diff --git a/arch/arm/mach-spear3xx/include/mach/spear310.h b/arch/arm/mach-spear3xx/include/mach/spear310.h index 1e853479b8cd..1567d0da725f 100644 --- a/arch/arm/mach-spear3xx/include/mach/spear310.h +++ b/arch/arm/mach-spear3xx/include/mach/spear310.h @@ -29,29 +29,29 @@ #define SPEAR310_SOC_CONFIG_BASE UL(0xB4000000) /* Interrupt registers offsets and masks */ -#define INT_STS_MASK_REG 0x04 -#define SMII0_IRQ_MASK (1 << 0) -#define SMII1_IRQ_MASK (1 << 1) -#define SMII2_IRQ_MASK (1 << 2) -#define SMII3_IRQ_MASK (1 << 3) -#define WAKEUP_SMII0_IRQ_MASK (1 << 4) -#define WAKEUP_SMII1_IRQ_MASK (1 << 5) -#define WAKEUP_SMII2_IRQ_MASK (1 << 6) -#define WAKEUP_SMII3_IRQ_MASK (1 << 7) -#define UART1_IRQ_MASK (1 << 8) -#define UART2_IRQ_MASK (1 << 9) -#define UART3_IRQ_MASK (1 << 10) -#define UART4_IRQ_MASK (1 << 11) -#define UART5_IRQ_MASK (1 << 12) -#define EMI_IRQ_MASK (1 << 13) -#define TDM_HDLC_IRQ_MASK (1 << 14) -#define RS485_0_IRQ_MASK (1 << 15) -#define RS485_1_IRQ_MASK (1 << 16) +#define SPEAR310_INT_STS_MASK_REG 0x04 +#define SPEAR310_SMII0_IRQ_MASK (1 << 0) +#define SPEAR310_SMII1_IRQ_MASK (1 << 1) +#define SPEAR310_SMII2_IRQ_MASK (1 << 2) +#define SPEAR310_SMII3_IRQ_MASK (1 << 3) +#define SPEAR310_WAKEUP_SMII0_IRQ_MASK (1 << 4) +#define SPEAR310_WAKEUP_SMII1_IRQ_MASK (1 << 5) +#define SPEAR310_WAKEUP_SMII2_IRQ_MASK (1 << 6) +#define SPEAR310_WAKEUP_SMII3_IRQ_MASK (1 << 7) +#define SPEAR310_UART1_IRQ_MASK (1 << 8) +#define SPEAR310_UART2_IRQ_MASK (1 << 9) +#define SPEAR310_UART3_IRQ_MASK (1 << 10) +#define SPEAR310_UART4_IRQ_MASK (1 << 11) +#define SPEAR310_UART5_IRQ_MASK (1 << 12) +#define SPEAR310_EMI_IRQ_MASK (1 << 13) +#define SPEAR310_TDM_HDLC_IRQ_MASK (1 << 14) +#define SPEAR310_RS485_0_IRQ_MASK (1 << 15) +#define SPEAR310_RS485_1_IRQ_MASK (1 << 16) -#define SHIRQ_RAS1_MASK 0x000FF -#define SHIRQ_RAS2_MASK 0x01F00 -#define SHIRQ_RAS3_MASK 0x02000 -#define SHIRQ_INTRCOMM_RAS_MASK 0x1C000 +#define SPEAR310_SHIRQ_RAS1_MASK 0x000FF +#define SPEAR310_SHIRQ_RAS2_MASK 0x01F00 +#define SPEAR310_SHIRQ_RAS3_MASK 0x02000 +#define SPEAR310_SHIRQ_INTRCOMM_RAS_MASK 0x1C000 #endif /* __MACH_SPEAR310_H */ |