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-rw-r--r--Documentation/admin-guide/kernel-parameters.txt4
-rw-r--r--Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml3
-rw-r--r--Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml6
-rw-r--r--Documentation/devicetree/bindings/pci/qcom,pcie.yaml103
-rw-r--r--Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml76
5 files changed, 126 insertions, 66 deletions
diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
index 8faec13961cd..46268d6baa43 100644
--- a/Documentation/admin-guide/kernel-parameters.txt
+++ b/Documentation/admin-guide/kernel-parameters.txt
@@ -4303,7 +4303,9 @@
specified, e.g., 12@pci:8086:9c22:103c:198f
for 4096-byte alignment.
ecrc= Enable/disable PCIe ECRC (transaction layer
- end-to-end CRC checking).
+ end-to-end CRC checking). Only effective if
+ OS has native AER control (either granted by
+ ACPI _OSC or forced via "pcie_ports=native")
bios: Use BIOS/firmware settings. This is the
the default.
off: Turn ECRC off
diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
index bad980902f66..f13f87fddb3d 100644
--- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
@@ -24,6 +24,9 @@ properties:
- fsl,imx8mq-pcie
- fsl,imx8mm-pcie
- fsl,imx8mp-pcie
+ - fsl,imx8mm-pcie-ep
+ - fsl,imx8mq-pcie-ep
+ - fsl,imx8mp-pcie-ep
reg:
items:
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
index 8d7eb51edcb4..89cfdee4b89f 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
@@ -47,8 +47,10 @@ properties:
enable registers
$ref: "/schemas/types.yaml#/definitions/phandle-array"
items:
- minItems: 3
- maxItems: 3
+ - items:
+ - description: Syscon to TCSR system registers
+ - description: Perst enable offset
+ - description: Perst separation enable offset
interrupts:
items:
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
index a5859bb3dc28..fb32c43dd12d 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
@@ -16,25 +16,31 @@ description: |
properties:
compatible:
- enum:
- - qcom,pcie-ipq8064
- - qcom,pcie-ipq8064-v2
- - qcom,pcie-apq8064
- - qcom,pcie-apq8084
- - qcom,pcie-msm8996
- - qcom,pcie-ipq4019
- - qcom,pcie-ipq8074
- - qcom,pcie-qcs404
- - qcom,pcie-sa8540p
- - qcom,pcie-sc7280
- - qcom,pcie-sc8180x
- - qcom,pcie-sc8280xp
- - qcom,pcie-sdm845
- - qcom,pcie-sm8150
- - qcom,pcie-sm8250
- - qcom,pcie-sm8450-pcie0
- - qcom,pcie-sm8450-pcie1
- - qcom,pcie-ipq6018
+ oneOf:
+ - enum:
+ - qcom,pcie-apq8064
+ - qcom,pcie-apq8084
+ - qcom,pcie-ipq4019
+ - qcom,pcie-ipq6018
+ - qcom,pcie-ipq8064
+ - qcom,pcie-ipq8064-v2
+ - qcom,pcie-ipq8074
+ - qcom,pcie-ipq8074-gen3
+ - qcom,pcie-msm8996
+ - qcom,pcie-qcs404
+ - qcom,pcie-sa8540p
+ - qcom,pcie-sc7280
+ - qcom,pcie-sc8180x
+ - qcom,pcie-sc8280xp
+ - qcom,pcie-sdm845
+ - qcom,pcie-sm8150
+ - qcom,pcie-sm8250
+ - qcom,pcie-sm8350
+ - qcom,pcie-sm8450-pcie0
+ - qcom,pcie-sm8450-pcie1
+ - items:
+ - const: qcom,pcie-msm8998
+ - const: qcom,pcie-msm8996
reg:
minItems: 4
@@ -153,6 +159,7 @@ allOf:
contains:
enum:
- qcom,pcie-ipq6018
+ - qcom,pcie-ipq8074-gen3
then:
properties:
reg:
@@ -195,6 +202,7 @@ allOf:
- qcom,pcie-sc8180x
- qcom,pcie-sc8280xp
- qcom,pcie-sm8250
+ - qcom,pcie-sm8350
- qcom,pcie-sm8450-pcie0
- qcom,pcie-sm8450-pcie1
then:
@@ -312,27 +320,17 @@ allOf:
enum:
- qcom,pcie-msm8996
then:
- oneOf:
- - properties:
- clock-names:
- items:
- - const: pipe # Pipe Clock driving internal logic
- - const: aux # Auxiliary (AUX) clock
- - const: cfg # Configuration clock
- - const: bus_master # Master AXI clock
- - const: bus_slave # Slave AXI clock
- - properties:
- clock-names:
- items:
- - const: pipe # Pipe Clock driving internal logic
- - const: bus_master # Master AXI clock
- - const: bus_slave # Slave AXI clock
- - const: cfg # Configuration clock
- - const: aux # Auxiliary (AUX) clock
properties:
clocks:
minItems: 5
maxItems: 5
+ clock-names:
+ items:
+ - const: pipe # Pipe Clock driving internal logic
+ - const: aux # Auxiliary (AUX) clock
+ - const: cfg # Configuration clock
+ - const: bus_master # Master AXI clock
+ - const: bus_slave # Slave AXI clock
resets: false
reset-names: false
@@ -373,6 +371,7 @@ allOf:
contains:
enum:
- qcom,pcie-ipq6018
+ - qcom,pcie-ipq8074-gen3
then:
properties:
clocks:
@@ -555,6 +554,35 @@ allOf:
compatible:
contains:
enum:
+ - qcom,pcie-sm8350
+ then:
+ properties:
+ clocks:
+ minItems: 8
+ maxItems: 9
+ clock-names:
+ minItems: 8
+ items:
+ - const: aux # Auxiliary clock
+ - const: cfg # Configuration clock
+ - const: bus_master # Master AXI clock
+ - const: bus_slave # Slave AXI clock
+ - const: slave_q2a # Slave Q2A clock
+ - const: tbu # PCIe TBU clock
+ - const: ddrss_sf_tbu # PCIe SF TBU clock
+ - const: aggre1 # Aggre NoC PCIe1 AXI clock
+ - const: aggre0 # Aggre NoC PCIe0 AXI clock
+ resets:
+ maxItems: 1
+ reset-names:
+ items:
+ - const: pci # PCIe core reset
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
- qcom,pcie-sm8450-pcie0
then:
properties:
@@ -664,6 +692,7 @@ allOf:
- qcom,pcie-ipq8064
- qcom,pcie-ipq8064v2
- qcom,pcie-ipq8074
+ - qcom,pcie-ipq8074-gen3
- qcom,pcie-qcs404
then:
required:
@@ -692,6 +721,7 @@ allOf:
- qcom,pcie-sdm845
- qcom,pcie-sm8150
- qcom,pcie-sm8250
+ - qcom,pcie-sm8350
- qcom,pcie-sm8450-pcie0
- qcom,pcie-sm8450-pcie1
then:
@@ -746,6 +776,7 @@ allOf:
- qcom,pcie-ipq8064
- qcom,pcie-ipq8064-v2
- qcom,pcie-ipq8074
+ - qcom,pcie-ipq8074-gen3
- qcom,pcie-qcs404
- qcom,pcie-sa8540p
then:
diff --git a/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml
index 437e61618d06..f0d8e486a07d 100644
--- a/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml
@@ -15,9 +15,6 @@ description: |
maintainers:
- Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
-allOf:
- - $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
-
properties:
compatible:
enum:
@@ -29,40 +26,25 @@ properties:
maxItems: 5
reg-names:
- oneOf:
- - items:
- - const: dbi
- - const: dbi2
- - const: link
- - const: addr_space
- - items:
- - const: dbi
- - const: dbi2
- - const: link
- - const: addr_space
- - const: atu
+ minItems: 4
+ items:
+ - const: dbi
+ - const: dbi2
+ - const: link
+ - const: addr_space
+ - const: atu
clocks:
minItems: 1
maxItems: 2
- clock-names:
- oneOf:
- - items: # for Pro5
- - const: gio
- - const: link
- - const: link # for NX1
+ clock-names: true
resets:
minItems: 1
maxItems: 2
- reset-names:
- oneOf:
- - items: # for Pro5
- - const: gio
- - const: link
- - const: link # for NX1
+ reset-names: true
num-ib-windows:
const: 16
@@ -78,6 +60,46 @@ properties:
phy-names:
const: pcie-phy
+allOf:
+ - $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: socionext,uniphier-pro5-pcie-ep
+ then:
+ properties:
+ reg:
+ maxItems: 4
+ reg-names:
+ maxItems: 4
+ clocks:
+ minItems: 2
+ clock-names:
+ items:
+ - const: gio
+ - const: link
+ resets:
+ minItems: 2
+ reset-names:
+ items:
+ - const: gio
+ - const: link
+ else:
+ properties:
+ reg:
+ minItems: 5
+ reg-names:
+ minItems: 5
+ clocks:
+ maxItems: 1
+ clock-names:
+ const: link
+ resets:
+ maxItems: 1
+ reset-names:
+ const: link
+
required:
- compatible
- reg