diff options
Diffstat (limited to 'Documentation')
14 files changed, 243 insertions, 70 deletions
diff --git a/Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml b/Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml new file mode 100644 index 000000000000..f1770360798f --- /dev/null +++ b/Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/microchip,mpfs-ccc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PolarFire SoC Fabric Clock Conditioning Circuitry + +maintainers: + - Conor Dooley <conor.dooley@microchip.com> + +description: | + Microchip PolarFire SoC has 4 Clock Conditioning Circuitry blocks. Each of + these blocks contains two PLLs and 2 DLLs & are located in the four corners of + the FPGA. For more information see "PolarFire SoC FPGA Clocking Resources" at: + https://onlinedocs.microchip.com/pr/GUID-8F0CC4C0-0317-4262-89CA-CE7773ED1931-en-US-1/index.html + +properties: + compatible: + const: microchip,mpfs-ccc + + reg: + items: + - description: PLL0's control registers + - description: PLL1's control registers + - description: DLL0's control registers + - description: DLL1's control registers + + clocks: + description: + The CCC PLL's have two input clocks. It is required that even if the input + clocks are identical that both are provided. + minItems: 2 + items: + - description: PLL0's refclk0 + - description: PLL0's refclk1 + - description: PLL1's refclk0 + - description: PLL1's refclk1 + - description: DLL0's refclk + - description: DLL1's refclk + + clock-names: + minItems: 2 + items: + - const: pll0_ref0 + - const: pll0_ref1 + - const: pll1_ref0 + - const: pll1_ref1 + - const: dll0_ref + - const: dll1_ref + + '#clock-cells': + const: 1 + description: | + The clock consumer should specify the desired clock by having the clock + ID in its "clocks" phandle cell. + See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of + PolarFire clock IDs. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller@38100000 { + compatible = "microchip,mpfs-ccc"; + reg = <0x38010000 0x1000>, <0x38020000 0x1000>, + <0x39010000 0x1000>, <0x39020000 0x1000>; + #clock-cells = <1>; + clocks = <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, + <&refclk_ccc>, <&refclk_ccc>; + clock-names = "pll0_ref0", "pll0_ref1", "pll1_ref0", "pll1_ref1", + "dll0_ref", "dll1_ref"; + }; diff --git a/Documentation/devicetree/bindings/clock/microchip,mpfs.yaml b/Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml index 016a4f378b9b..b2ce78722247 100644 --- a/Documentation/devicetree/bindings/clock/microchip,mpfs.yaml +++ b/Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/clock/microchip,mpfs.yaml# +$id: http://devicetree.org/schemas/clock/microchip,mpfs-clkcfg.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Microchip PolarFire Clock Control Module Binding @@ -40,8 +40,21 @@ properties: const: 1 description: | The clock consumer should specify the desired clock by having the clock - ID in its "clocks" phandle cell. See include/dt-bindings/clock/microchip,mpfs-clock.h - for the full list of PolarFire clock IDs. + ID in its "clocks" phandle cell. + See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of + PolarFire clock IDs. + + resets: + maxItems: 1 + + '#reset-cells': + description: + The AHB/AXI peripherals on the PolarFire SoC have reset support, so from + CLK_ENVM to CLK_CFM. The reset consumer should specify the desired + peripheral via the clock ID in its "resets" phandle cell. + See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of + PolarFire clock IDs. + const: 1 required: - compatible diff --git a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml index d036675e0779..487f74cdc749 100644 --- a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml +++ b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml @@ -24,7 +24,7 @@ description: | properties: compatible: enum: - - renesas,r9a07g043-cpg # RZ/G2UL{Type-1,Type-2} + - renesas,r9a07g043-cpg # RZ/G2UL{Type-1,Type-2} and RZ/Five - renesas,r9a07g044-cpg # RZ/G2{L,LC} - renesas,r9a07g054-cpg # RZ/V2L - renesas,r9a09g011-cpg # RZ/V2M diff --git a/Documentation/devicetree/bindings/clock/rockchip,px30-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,px30-cru.yaml index 3eec381c7cf5..0f0f64b6f8cb 100644 --- a/Documentation/devicetree/bindings/clock/rockchip,px30-cru.yaml +++ b/Documentation/devicetree/bindings/clock/rockchip,px30-cru.yaml @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: (GPL-2.0+ OR MIT) %YAML 1.2 --- $id: http://devicetree.org/schemas/clock/rockchip,px30-cru.yaml# diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.yaml index 1376230fede6..ba5b45464315 100644 --- a/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.yaml +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.yaml @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: (GPL-2.0+ OR MIT) %YAML 1.2 --- $id: http://devicetree.org/schemas/clock/rockchip,rk3036-cru.yaml# diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3128-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3128-cru.txt deleted file mode 100644 index 6f8744fd301b..000000000000 --- a/Documentation/devicetree/bindings/clock/rockchip,rk3128-cru.txt +++ /dev/null @@ -1,58 +0,0 @@ -* Rockchip RK3126/RK3128 Clock and Reset Unit - -The RK3126/RK3128 clock controller generates and supplies clock to various -controllers within the SoC and also implements a reset controller for SoC -peripherals. - -Required Properties: - -- compatible: should be "rockchip,rk3126-cru" or "rockchip,rk3128-cru" - "rockchip,rk3126-cru" - controller compatible with RK3126 SoC. - "rockchip,rk3128-cru" - controller compatible with RK3128 SoC. -- reg: physical base address of the controller and length of memory mapped - region. -- #clock-cells: should be 1. -- #reset-cells: should be 1. - -Optional Properties: - -- rockchip,grf: phandle to the syscon managing the "general register files" - If missing pll rates are not changeable, due to the missing pll lock status. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. All available clocks are defined as -preprocessor macros in the dt-bindings/clock/rk3128-cru.h headers and can be -used in device tree sources. Similar macros exist for the reset sources in -these files. - -External clocks: - -There are several clocks that are generated outside the SoC. It is expected -that they are defined using standard clock bindings with following -clock-output-names: - - "xin24m" - crystal input - required, - - "ext_i2s" - external I2S clock - optional, - - "gmac_clkin" - external GMAC clock - optional - -Example: Clock controller node: - - cru: cru@20000000 { - compatible = "rockchip,rk3128-cru"; - reg = <0x20000000 0x1000>; - rockchip,grf = <&grf>; - - #clock-cells = <1>; - #reset-cells = <1>; - }; - -Example: UART controller node that consumes the clock generated by the clock - controller: - - uart2: serial@20068000 { - compatible = "rockchip,serial"; - reg = <0x20068000 0x100>; - interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; - clock-names = "sclk_uart", "pclk_uart"; - }; diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3128-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3128-cru.yaml new file mode 100644 index 000000000000..b3d9c8eca989 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3128-cru.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: (GPL-2.0+ OR MIT) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/rockchip,rk3128-cru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip RK3126/RK3128 Clock and Reset Unit (CRU) + +maintainers: + - Elaine Zhang <zhangqing@rock-chips.com> + - Heiko Stuebner <heiko@sntech.de> + +description: | + The RK3126/RK3128 clock controller generates and supplies clock to various + controllers within the SoC and also implements a reset controller for SoC + peripherals. + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All available clocks are defined as + preprocessor macros in the dt-bindings/clock/rk3128-cru.h headers and can be + used in device tree sources. Similar macros exist for the reset sources in + these files. + +properties: + compatible: + enum: + - rockchip,rk3126-cru + - rockchip,rk3128-cru + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + + clocks: + minItems: 1 + maxItems: 3 + + clock-names: + minItems: 1 + items: + - const: xin24m + - enum: + - ext_i2s + - gmac_clkin + - enum: + - ext_i2s + - gmac_clkin + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the syscon managing the "general register files" (GRF), + if missing pll rates are not changeable, due to the missing pll + lock status. + +required: + - compatible + - reg + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + cru: clock-controller@20000000 { + compatible = "rockchip,rk3128-cru"; + reg = <0x20000000 0x1000>; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3228-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3228-cru.yaml index cf7dc01d9478..1050fff72ade 100644 --- a/Documentation/devicetree/bindings/clock/rockchip,rk3228-cru.yaml +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3228-cru.yaml @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: (GPL-2.0+ OR MIT) %YAML 1.2 --- $id: http://devicetree.org/schemas/clock/rockchip,rk3228-cru.yaml# diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3288-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3288-cru.yaml index 96bc05749e1a..6655e97d52e4 100644 --- a/Documentation/devicetree/bindings/clock/rockchip,rk3288-cru.yaml +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3288-cru.yaml @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: (GPL-2.0+ OR MIT) %YAML 1.2 --- $id: http://devicetree.org/schemas/clock/rockchip,rk3288-cru.yaml# diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3308-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3308-cru.yaml index 523ee578a586..fec37f5b80f6 100644 --- a/Documentation/devicetree/bindings/clock/rockchip,rk3308-cru.yaml +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3308-cru.yaml @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: (GPL-2.0+ OR MIT) %YAML 1.2 --- $id: http://devicetree.org/schemas/clock/rockchip,rk3308-cru.yaml# diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3368-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3368-cru.yaml index adb67877720d..90af242b41c1 100644 --- a/Documentation/devicetree/bindings/clock/rockchip,rk3368-cru.yaml +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3368-cru.yaml @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: (GPL-2.0+ OR MIT) %YAML 1.2 --- $id: http://devicetree.org/schemas/clock/rockchip,rk3368-cru.yaml# diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml index 54da1e31ea73..0b758e015ee3 100644 --- a/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0-only +# SPDX-License-Identifier: (GPL-2.0+ OR MIT) %YAML 1.2 --- $id: http://devicetree.org/schemas/clock/rockchip,rk3399-cru.yaml# diff --git a/Documentation/devicetree/bindings/clock/rockchip,rv1108-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rv1108-cru.yaml index 20421c22f184..4611d920b8df 100644 --- a/Documentation/devicetree/bindings/clock/rockchip,rv1108-cru.yaml +++ b/Documentation/devicetree/bindings/clock/rockchip,rv1108-cru.yaml @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: (GPL-2.0+ OR MIT) %YAML 1.2 --- $id: http://devicetree.org/schemas/clock/rockchip,rv1108-cru.yaml# diff --git a/Documentation/devicetree/bindings/clock/rockchip,rv1126-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rv1126-cru.yaml new file mode 100644 index 000000000000..0998f8b922bd --- /dev/null +++ b/Documentation/devicetree/bindings/clock/rockchip,rv1126-cru.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/rockchip,rv1126-cru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip RV1126 Clock and Reset Unit + +maintainers: + - Jagan Teki <jagan@edgeble.ai> + - Finley Xiao <finley.xiao@rock-chips.com> + - Heiko Stuebner <heiko@sntech.de> + +description: + The RV1126 clock controller generates the clock and also implements a + reset controller for SoC peripherals. + +properties: + compatible: + enum: + - rockchip,rv1126-cru + - rockchip,rv1126-pmucru + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + + clocks: + maxItems: 1 + + clock-names: + const: xin24m + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the syscon managing the "general register files" (GRF), + if missing pll rates are not changeable, due to the missing pll + lock status. + +required: + - compatible + - reg + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + cru: clock-controller@ff490000 { + compatible = "rockchip,rv1126-cru"; + reg = <0xff490000 0x1000>; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; |