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Diffstat (limited to 'Documentation')
5 files changed, 227 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/hwmon/starfive,jh7100-temp.yaml b/Documentation/devicetree/bindings/hwmon/starfive,jh7100-temp.yaml new file mode 100644 index 000000000000..c63afc4c2549 --- /dev/null +++ b/Documentation/devicetree/bindings/hwmon/starfive,jh7100-temp.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwmon/starfive,jh7100-temp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7100 Temperature Sensor + +maintainers: + - Emil Renner Berthing <kernel@esmil.dk> + +description: | + StarFive Technology Co. JH7100 embedded temperature sensor + +properties: + compatible: + enum: + - starfive,jh7100-temp + - starfive,jh7110-temp + + reg: + maxItems: 1 + + clocks: + minItems: 2 + maxItems: 2 + + clock-names: + items: + - const: "sense" + - const: "bus" + + '#thermal-sensor-cells': + const: 0 + + interrupts: + maxItems: 1 + + resets: + minItems: 2 + maxItems: 2 + + reset-names: + items: + - const: "sense" + - const: "bus" + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - resets + - reset-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/starfive-jh7100.h> + #include <dt-bindings/reset/starfive-jh7100.h> + + tmon: tmon@124a0000 { + compatible = "starfive,jh7100-temp"; + reg = <0x124a0000 0x10000>; + clocks = <&clkgen JH7100_CLK_TEMP_SENSE>, + <&clkgen JH7100_CLK_TEMP_APB>; + clock-names = "sense", "bus"; + #thermal-sensor-cells = <0>; + interrupts = <122>; + resets = <&rstgen JH7100_RSTN_TEMP_SENSE>, + <&rstgen JH7100_RSTN_TEMP_APB>; + reset-names = "sense", "bus"; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-pinctrl.yaml new file mode 100644 index 000000000000..6973fedeeb02 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-pinctrl.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/starfive,jh7110-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 Pin Controller Device Tree Bindings + +description: | + Bindings for the JH7110 RISC-V SoC from StarFive Ltd. + +maintainers: + - Jianlong Huang <jianlong.huang@starfivetech.com> + +properties: + compatible: + enum: + - starfive,jh7110-sys-pinctrl + - starfive,jh7110-aon-pinctrl + + reg: + minItems: 2 + maxItems: 2 + + reg-names: + items: + - const: control + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + "#gpio-cells": + const: 2 + + interrupts: + maxItems: 1 + description: The GPIO parent interrupt. + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + ngpios: + enum: + - 64 + - 4 + +required: + - compatible + - reg + - reg-names + - clocks + - "#gpio-cells" + - interrupts + - interrupt-controller + - "#interrupt-cells" + +examples: + - | + gpio: gpio@13040000 { + compatible = "starfive,jh7110-sys-pinctrl"; + reg = <0x0 0x13040000 0x0 0x10000>; + reg-names = "control"; + clocks = <&clkgen JH7110_SYS_IOMUX_PCLK>; + resets = <&rstgen RSTN_U0_SYS_IOMUX_PRESETN>; + interrupts = <86>; + interrupt-controller; + #gpio-cells = <2>; + ngpios = <64>; + status = "okay"; + }; + +... diff --git a/Documentation/devicetree/bindings/reset/starfive,jh7110.yaml b/Documentation/devicetree/bindings/reset/starfive,jh7110.yaml new file mode 100644 index 000000000000..23d01da66a68 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/starfive,jh7110.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/starfive,jh7110-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 SoC Reset Controller Device Tree Bindings + +maintainers: + - samin <samin.guo@starfivetech.com> + +properties: + compatible: + enum: + - starfive,jh7110-reset + + reg: + maxItems: 5 + + "#reset-cells": + const: 1 + +required: + - compatible + - reg + - "#reset-cells" + +additionalProperties: false + +examples: + - | + rstgen: reset-controller { + compatible = "starfive,jh7110-reset"; + reg = <0x0 0x13020000 0x0 0x10000>, + <0x0 0x10230000 0x0 0x10000>, + <0x0 0x17000000 0x0 0x10000>, + <0x0 0x19810000 0x0 0x10000>, + <0x0 0x295C0000 0x0 0x10000>; + reg-names = "syscrg", "stgcrg", "aoncrg", "ispcrg", "voutcrg"; + #reset-cells = <1>; + }; +... diff --git a/Documentation/hwmon/index.rst b/Documentation/hwmon/index.rst index c1d11cf13eef..f7ede608b6e3 100644 --- a/Documentation/hwmon/index.rst +++ b/Documentation/hwmon/index.rst @@ -179,6 +179,7 @@ Hardware Monitoring Kernel Drivers sch5627 sch5636 scpi-hwmon + sfctemp sht15 sht21 sht3x diff --git a/Documentation/hwmon/sfctemp.rst b/Documentation/hwmon/sfctemp.rst new file mode 100644 index 000000000000..465edce2fea5 --- /dev/null +++ b/Documentation/hwmon/sfctemp.rst @@ -0,0 +1,32 @@ +.. SPDX-License-Identifier: GPL-2.0 + +Kernel driver sfctemp +===================== + +Supported chips: + - StarFive JH7100 + +Authors: + - Emil Renner Berthing <kernel@esmil.dk> + +Description +----------- + +This driver adds support for reading the built-in temperature sensor on the +JH7100 RISC-V SoC by StarFive Technology Co. Ltd. + +``sysfs`` interface +------------------- + +The temperature sensor can be enabled, disabled and queried via the standard +hwmon interface in sysfs under ``/sys/class/hwmon/hwmonX`` for some value of +``X``: + +================ ==== ============================================= +Name Perm Description +================ ==== ============================================= +temp1_enable RW Enable or disable temperature sensor. + Automatically enabled by the driver, + but may be disabled to save power. +temp1_input RO Temperature reading in milli-degrees Celsius. +================ ==== ============================================= |