diff options
90 files changed, 12288 insertions, 415 deletions
diff --git a/Documentation/devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml b/Documentation/devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml index 885d47dd5724..e803a1fc3681 100644 --- a/Documentation/devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml +++ b/Documentation/devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml @@ -34,6 +34,8 @@ properties: - enum: - atmel,at91rm9200-pmc - atmel,at91sam9260-pmc + - atmel,at91sam9261-pmc + - atmel,at91sam9263-pmc - atmel,at91sam9g45-pmc - atmel,at91sam9n12-pmc - atmel,at91sam9rl-pmc @@ -111,6 +113,8 @@ allOf: enum: - atmel,at91rm9200-pmc - atmel,at91sam9260-pmc + - atmel,at91sam9261-pmc + - atmel,at91sam9263-pmc - atmel,at91sam9g20-pmc then: properties: diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml index 860570320545..2985c8c717d7 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml @@ -57,6 +57,27 @@ required: - reg - '#clock-cells' +allOf: + - if: + properties: + compatible: + contains: + enum: + - mediatek,mt8188-camsys-rawa + - mediatek,mt8188-camsys-rawb + - mediatek,mt8188-camsys-yuva + - mediatek,mt8188-camsys-yuvb + - mediatek,mt8188-imgsys-wpe1 + - mediatek,mt8188-imgsys-wpe2 + - mediatek,mt8188-imgsys-wpe3 + - mediatek,mt8188-imgsys1-dip-nr + - mediatek,mt8188-imgsys1-dip-top + - mediatek,mt8188-ipesys + + then: + required: + - '#reset-cells' + additionalProperties: false examples: diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3528-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3528-cru.yaml new file mode 100644 index 000000000000..5a3ec902351c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3528-cru.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/rockchip,rk3528-cru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip RK3528 Clock and Reset Controller + +maintainers: + - Yao Zi <ziyao@disroot.org> + +description: | + The RK3528 clock controller generates the clock and also implements a reset + controller for SoC peripherals. For example, it provides SCLK_UART0 and + PCLK_UART0 as well as SRST_P_UART0 and SRST_S_UART0 for the first UART + module. + Each clock is assigned an identifier, consumer nodes can use it to specify + the clock. All available clock and reset IDs are defined in dt-binding + headers. + +properties: + compatible: + const: rockchip,rk3528-cru + + reg: + maxItems: 1 + + clocks: + items: + - description: External 24MHz oscillator clock + - description: > + 50MHz clock generated by PHY module, for generating GMAC0 clocks only. + + clock-names: + items: + - const: xin24m + - const: gmac0 + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + clock-controller@ff4a0000 { + compatible = "rockchip,rk3528-cru"; + reg = <0xff4a0000 0x30000>; + clocks = <&xin24m>, <&gmac0_clk>; + clock-names = "xin24m", "gmac0"; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3562-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3562-cru.yaml new file mode 100644 index 000000000000..36a353f5c42a --- /dev/null +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3562-cru.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/rockchip,rk3562-cru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip rk3562 Clock and Reset Control Module + +maintainers: + - Elaine Zhang <zhangqing@rock-chips.com> + - Heiko Stuebner <heiko@sntech.de> + +description: + The RK3562 clock controller generates the clock and also implements a reset + controller for SoC peripherals. For example it provides SCLK_UART2 and + PCLK_UART2, as well as SRST_P_UART2 and SRST_S_UART2 for the second UART + module. + +properties: + compatible: + const: rockchip,rk3562-cru + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: xin24m + - const: xin32k + +required: + - compatible + - reg + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + clock-controller@ff100000 { + compatible = "rockchip,rk3562-cru"; + reg = <0xff100000 0x40000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos2200-cmu.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos2200-cmu.yaml new file mode 100644 index 000000000000..89433e6d3518 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/samsung,exynos2200-cmu.yaml @@ -0,0 +1,247 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/samsung,exynos2200-cmu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos2200 SoC clock controller + +maintainers: + - Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> + - Chanwoo Choi <cw00.choi@samsung.com> + - Krzysztof Kozlowski <krzk@kernel.org> + +description: | + Exynos2200 clock controller is comprised of several CMU units, generating + clocks for different domains. Those CMU units are modeled as separate device + tree nodes, and might depend on each other. The root clocks in that root tree + are two external clocks: XTCXO (76.8 MHz) and RTCCLK (32768 Hz). XTCXO must be + defined as a fixed-rate clock in dts, whereas RTCCLK originates from PMIC. + + CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and + dividers; all other clocks of function blocks (other CMUs) are usually + derived from CMU_TOP. + + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All clocks available for usage + in clock consumer nodes are defined as preprocessor macros in + 'include/dt-bindings/clock/samsung,exynos2200-cmu.h' header. + +properties: + compatible: + enum: + - samsung,exynos2200-cmu-alive + - samsung,exynos2200-cmu-cmgp + - samsung,exynos2200-cmu-hsi0 + - samsung,exynos2200-cmu-peric0 + - samsung,exynos2200-cmu-peric1 + - samsung,exynos2200-cmu-peric2 + - samsung,exynos2200-cmu-peris + - samsung,exynos2200-cmu-top + - samsung,exynos2200-cmu-ufs + - samsung,exynos2200-cmu-vts + + clocks: + minItems: 1 + maxItems: 6 + + clock-names: + minItems: 1 + maxItems: 6 + + "#clock-cells": + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - clocks + - clock-names + - reg + - "#clock-cells" + +allOf: + - if: + properties: + compatible: + contains: + const: samsung,exynos2200-cmu-alive + + then: + properties: + clocks: + items: + - description: External reference clock (76.8 MHz) + - description: CMU_ALIVE NOC clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: noc + + - if: + properties: + compatible: + contains: + const: samsung,exynos2200-cmu-cmgp + + then: + properties: + clocks: + items: + - description: External reference clock (76.8 MHz) + - description: CMU_CMGP NOC clock (from CMU_TOP) + - description: CMU_CMGP PERI clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: noc + - const: peri + + - if: + properties: + compatible: + contains: + const: samsung,exynos2200-cmu-hsi0 + + then: + properties: + clocks: + items: + - description: External reference clock (76.8 MHz) + - description: External RTC clock (32768 Hz) + - description: CMU_HSI0 NOC clock (from CMU_TOP) + - description: CMU_HSI0 DPGTC clock (from CMU_TOP) + - description: CMU_HSI0 DPOSC clock (from CMU_TOP) + - description: CMU_HSI0 USB32DRD clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: rtcclk + - const: noc + - const: dpgtc + - const: dposc + - const: usb + + - if: + properties: + compatible: + contains: + enum: + - samsung,exynos2200-cmu-peric0 + - samsung,exynos2200-cmu-peric1 + - samsung,exynos2200-cmu-peric2 + + then: + properties: + clocks: + items: + - description: External reference clock (76.8 MHz) + - description: CMU_PERICn NOC clock (from CMU_TOP) + - description: CMU_PERICn IP0 clock (from CMU_TOP) + - description: CMU_PERICn IP1 clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: noc + - const: ip0 + - const: ip1 + + - if: + properties: + compatible: + contains: + const: samsung,exynos2200-cmu-peris + + then: + properties: + clocks: + items: + - description: External reference clock (25.6 MHz) + - description: CMU_PERIS NOC clock (from CMU_TOP) + - description: CMU_PERIS GIC clock (from CMU_TOP) + + clock-names: + items: + - const: tcxo_div3 + - const: noc + - const: gic + + - if: + properties: + compatible: + contains: + const: samsung,exynos2200-cmu-top + + then: + properties: + clocks: + items: + - description: External reference clock (76.8 MHz) + + clock-names: + items: + - const: oscclk + + - if: + properties: + compatible: + contains: + const: samsung,exynos2200-cmu-ufs + + then: + properties: + clocks: + items: + - description: External reference clock (76.8 MHz) + - description: CMU_UFS NOC clock (from CMU_TOP) + - description: CMU_UFS MMC clock (from CMU_TOP) + - description: CMU_UFS UFS clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: noc + - const: mmc + - const: ufs + + - if: + properties: + compatible: + contains: + const: samsung,exynos2200-cmu-vts + + then: + properties: + clocks: + items: + - description: External reference clock (76.8 MHz) + - description: CMU_VTS DMIC clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dmic + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/samsung,exynos2200-cmu.h> + + cmu_vts: clock-controller@15300000 { + compatible = "samsung,exynos2200-cmu-vts"; + reg = <0x15300000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, + <&cmu_top CLK_DOUT_CMU_VTS_DMIC>; + clock-names = "oscclk", "dmic"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos7870-cmu.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos7870-cmu.yaml new file mode 100644 index 000000000000..3c58712f12b9 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/samsung,exynos7870-cmu.yaml @@ -0,0 +1,227 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/samsung,exynos7870-cmu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos7870 SoC clock controller + +maintainers: + - Kaustabh Chakraborty <kauschluss@disroot.org> + +description: | + Exynos7870 clock controller is comprised of several CMU units, generating + clocks for different domains. Those CMU units are modeled as separate device + tree nodes, and might depend on each other. The root clock in that root tree + is an external clock: OSCCLK (26 MHz). This external clock must be defined + as a fixed-rate clock in dts. + + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All clocks available for usage + in clock consumer nodes are defined as preprocessor macros in + include/dt-bindings/clock/samsung,exynos7870-cmu.h header. + +properties: + compatible: + enum: + - samsung,exynos7870-cmu-mif + - samsung,exynos7870-cmu-dispaud + - samsung,exynos7870-cmu-fsys + - samsung,exynos7870-cmu-g3d + - samsung,exynos7870-cmu-isp + - samsung,exynos7870-cmu-mfcmscl + - samsung,exynos7870-cmu-peri + + clocks: + minItems: 1 + maxItems: 10 + + clock-names: + minItems: 1 + maxItems: 10 + + "#clock-cells": + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - clocks + - clock-names + - "#clock-cells" + - reg + +allOf: + - if: + properties: + compatible: + contains: + const: samsung,exynos7870-cmu-mif + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + + clock-names: + items: + - const: oscclk + + - if: + properties: + compatible: + contains: + const: samsung,exynos7870-cmu-dispaud + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_DISPAUD bus clock (from CMU_MIF) + - description: DECON external clock (from CMU_MIF) + - description: DECON vertical clock (from CMU_MIF) + + clock-names: + items: + - const: oscclk + - const: bus + - const: decon_eclk + - const: decon_vclk + + - if: + properties: + compatible: + contains: + const: samsung,exynos7870-cmu-fsys + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_FSYS bus clock (from CMU_MIF) + - description: USB20DRD clock (from CMU_MIF) + + clock-names: + items: + - const: oscclk + - const: bus + - const: usb20drd + + - if: + properties: + compatible: + contains: + const: samsung,exynos7870-cmu-g3d + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: G3D switch clock (from CMU_MIF) + + clock-names: + items: + - const: oscclk + - const: switch + + - if: + properties: + compatible: + contains: + const: samsung,exynos7870-cmu-isp + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: ISP camera clock (from CMU_MIF) + - description: ISP clock (from CMU_MIF) + - description: ISP VRA clock (from CMU_MIF) + + clock-names: + items: + - const: oscclk + - const: cam + - const: isp + - const: vra + + - if: + properties: + compatible: + contains: + const: samsung,exynos7870-cmu-mfcmscl + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: MSCL clock (from CMU_MIF) + - description: MFC clock (from CMU_MIF) + + clock-names: + items: + - const: oscclk + - const: mfc + - const: mscl + + - if: + properties: + compatible: + contains: + const: samsung,exynos7870-cmu-peri + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_PERI bus clock (from CMU_MIF) + - description: SPI0 clock (from CMU_MIF) + - description: SPI1 clock (from CMU_MIF) + - description: SPI2 clock (from CMU_MIF) + - description: SPI3 clock (from CMU_MIF) + - description: SPI4 clock (from CMU_MIF) + - description: UART0 clock (from CMU_MIF) + - description: UART1 clock (from CMU_MIF) + - description: UART2 clock (from CMU_MIF) + + clock-names: + items: + - const: oscclk + - const: bus + - const: spi0 + - const: spi1 + - const: spi2 + - const: spi3 + - const: spi4 + - const: uart0 + - const: uart1 + - const: uart2 + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/samsung,exynos7870-cmu.h> + + cmu_peri: clock-controller@101f0000 { + compatible = "samsung,exynos7870-cmu-peri"; + reg = <0x101f0000 0x1000>; + #clock-cells = <1>; + + clock-names = "oscclk", "bus", "spi0", "spi1", "spi2", + "spi3", "spi4", "uart0", "uart1", "uart2"; + clocks = <&oscclk>, + <&cmu_mif CLK_GOUT_MIF_CMU_PERI_BUS>, + <&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI0>, + <&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI1>, + <&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI2>, + <&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI3>, + <&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI4>, + <&cmu_mif CLK_GOUT_MIF_CMU_PERI_UART0>, + <&cmu_mif CLK_GOUT_MIF_CMU_PERI_UART1>, + <&cmu_mif CLK_GOUT_MIF_CMU_PERI_UART2>; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos990-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos990-clock.yaml index 9e7944b5f13b..c15cc1752b02 100644 --- a/Documentation/devicetree/bindings/clock/samsung,exynos990-clock.yaml +++ b/Documentation/devicetree/bindings/clock/samsung,exynos990-clock.yaml @@ -31,6 +31,7 @@ properties: compatible: enum: - samsung,exynos990-cmu-hsi0 + - samsung,exynos990-cmu-peris - samsung,exynos990-cmu-top clocks: @@ -83,6 +84,24 @@ allOf: properties: compatible: contains: + const: samsung,exynos990-cmu-peris + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_PERIS BUS clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: bus + + - if: + properties: + compatible: + contains: const: samsung,exynos990-cmu-top then: diff --git a/Documentation/devicetree/bindings/clock/ti,clkctrl.yaml b/Documentation/devicetree/bindings/clock/ti,clkctrl.yaml new file mode 100644 index 000000000000..49787550ce45 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/ti,clkctrl.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/ti,clkctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments clkctrl clock + +maintainers: + - Tony Lindgren <tony@atomide.com> + - Andreas Kemnade <andreas@kemnade.info> + +description: | + Texas Instruments SoCs can have a clkctrl clock controller for each + interconnect target module. The clkctrl clock controller manages functional + and interface clocks for each module. Each clkctrl controller can also + gate one or more optional functional clocks for a module, and can have one + or more clock muxes. There is a clkctrl clock controller typically for each + interconnect target module on omap4 and later variants. + + The clock consumers can specify the index of the clkctrl clock using + the hardware offset from the clkctrl instance register space. The optional + clocks can be specified by clkctrl hardware offset and the index of the + optional clock. + +properties: + compatible: + enum: + - ti,clkctrl + - ti,clkctrl-l4-cfg + - ti,clkctrl-l4-per + - ti,clkctrl-l4-secure + - ti,clkctrl-l4-wkup + + "#clock-cells": + const: 2 + + clock-output-names: + maxItems: 1 + + reg: + minItems: 1 + maxItems: 8 # arbitrary, should be enough + +required: + - compatible + - "#clock-cells" + - clock-output-names + - reg + +additionalProperties: false + +examples: + - | + bus { + #address-cells = <1>; + #size-cells = <1>; + + clock@20 { + compatible = "ti,clkctrl"; + clock-output-names = "l4_per"; + reg = <0x20 0x1b0>; + #clock-cells = <2>; + }; + }; diff --git a/Documentation/devicetree/bindings/clock/ti-clkctrl.txt b/Documentation/devicetree/bindings/clock/ti-clkctrl.txt deleted file mode 100644 index d20db7974a38..000000000000 --- a/Documentation/devicetree/bindings/clock/ti-clkctrl.txt +++ /dev/null @@ -1,63 +0,0 @@ -Texas Instruments clkctrl clock binding - -Texas Instruments SoCs can have a clkctrl clock controller for each -interconnect target module. The clkctrl clock controller manages functional -and interface clocks for each module. Each clkctrl controller can also -gate one or more optional functional clocks for a module, and can have one -or more clock muxes. There is a clkctrl clock controller typically for each -interconnect target module on omap4 and later variants. - -The clock consumers can specify the index of the clkctrl clock using -the hardware offset from the clkctrl instance register space. The optional -clocks can be specified by clkctrl hardware offset and the index of the -optional clock. - -For more information, please see the Linux clock framework binding at -Documentation/devicetree/bindings/clock/clock-bindings.txt. - -Required properties : -- compatible : shall be "ti,clkctrl" or a clock domain specific name: - "ti,clkctrl-l4-cfg" - "ti,clkctrl-l4-per" - "ti,clkctrl-l4-secure" - "ti,clkctrl-l4-wkup" -- clock-output-names : from common clock binding -- #clock-cells : shall contain 2 with the first entry being the instance - offset from the clock domain base and the second being the - clock index -- reg : clock registers - -Example: Clock controller node on omap 4430: - -&cm2 { - l4per: cm@1400 { - cm_l4per@0 { - cm_l4per_clkctrl: clock@20 { - compatible = "ti,clkctrl"; - clock-output-names = "l4_per"; - reg = <0x20 0x1b0>; - #clock-cells = <2>; - }; - }; - }; -}; - -Example: Preprocessor helper macros in dt-bindings/clock/ti-clkctrl.h - -#define OMAP4_CLKCTRL_OFFSET 0x20 -#define OMAP4_CLKCTRL_INDEX(offset) ((offset) - OMAP4_CLKCTRL_OFFSET) -#define MODULEMODE_HWCTRL 1 -#define MODULEMODE_SWCTRL 2 - -#define OMAP4_GPTIMER10_CLKTRL OMAP4_CLKCTRL_INDEX(0x28) -#define OMAP4_GPTIMER11_CLKTRL OMAP4_CLKCTRL_INDEX(0x30) -#define OMAP4_GPTIMER2_CLKTRL OMAP4_CLKCTRL_INDEX(0x38) -... -#define OMAP4_GPIO2_CLKCTRL OMAP_CLKCTRL_INDEX(0x60) - -Example: Clock consumer node for GPIO2: - -&gpio2 { - clocks = <&cm_l4per_clkctrl OMAP4_GPIO2_CLKCTRL 0 - &cm_l4per_clkctrl OMAP4_GPIO2_CLKCTRL 8>; -}; diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c index f476883bc93b..85e23961ec34 100644 --- a/drivers/clk/clk-stm32f4.c +++ b/drivers/clk/clk-stm32f4.c @@ -888,7 +888,6 @@ static int __init stm32f4_pll_ssc_parse_dt(struct device_node *np, struct stm32f4_pll_ssc *conf) { int ret; - const char *s; if (!conf) return -EINVAL; @@ -916,7 +915,8 @@ static int __init stm32f4_pll_ssc_parse_dt(struct device_node *np, conf->mod_type = ret; pr_debug("%pOF: SSCG settings: mod_freq: %d, mod_depth: %d mod_method: %s [%d]\n", - np, conf->mod_freq, conf->mod_depth, s, conf->mod_type); + np, conf->mod_freq, conf->mod_depth, + stm32f4_ssc_mod_methods[ret], conf->mod_type); return 0; } diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index cf7720b9172f..0565c87656cf 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -2283,7 +2283,7 @@ static struct clk_core *clk_calc_new_rates(struct clk_core *core, unsigned long min_rate; unsigned long max_rate; int p_index = 0; - long ret; + int ret; /* sanity */ if (IS_ERR_OR_NULL(core)) @@ -4397,6 +4397,13 @@ fail_ops: fail_name: kref_put(&core->ref, __clk_release); fail_out: + if (dev) { + dev_err_probe(dev, ret, "failed to register clk '%s' (%pS)\n", + init->name, hw); + } else { + pr_err("%pOF: error %pe: failed to register clk '%s' (%pS)\n", + np, ERR_PTR(ret), init->name, hw); + } return ERR_PTR(ret); } @@ -5258,6 +5265,10 @@ of_clk_get_hw_from_clkspec(struct of_phandle_args *clkspec) if (!clkspec) return ERR_PTR(-EINVAL); + /* Check if node in clkspec is in disabled/fail state */ + if (!of_device_is_available(clkspec->np)) + return ERR_PTR(-ENOENT); + mutex_lock(&of_clk_mutex); list_for_each_entry(provider, &of_clk_providers, link) { if (provider->node == clkspec->np) { diff --git a/drivers/clk/davinci/Makefile b/drivers/clk/davinci/Makefile index 5d0ae1ee72ec..f9d5c9a392e4 100644 --- a/drivers/clk/davinci/Makefile +++ b/drivers/clk/davinci/Makefile @@ -4,10 +4,8 @@ ifeq ($(CONFIG_COMMON_CLK), y) obj-$(CONFIG_ARCH_DAVINCI_DA8XX) += da8xx-cfgchip.o obj-y += pll.o -obj-$(CONFIG_ARCH_DAVINCI_DA830) += pll-da830.o obj-$(CONFIG_ARCH_DAVINCI_DA850) += pll-da850.o obj-y += psc.o -obj-$(CONFIG_ARCH_DAVINCI_DA830) += psc-da830.o obj-$(CONFIG_ARCH_DAVINCI_DA850) += psc-da850.o endif diff --git a/drivers/clk/davinci/pll-da830.c b/drivers/clk/davinci/pll-da830.c deleted file mode 100644 index 0a0d06fb25fd..000000000000 --- a/drivers/clk/davinci/pll-da830.c +++ /dev/null @@ -1,71 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * PLL clock descriptions for TI DA830/OMAP-L137/AM17XX - * - * Copyright (C) 2018 David Lechner <david@lechnology.com> - */ - -#include <linux/clkdev.h> -#include <linux/clk/davinci.h> -#include <linux/bitops.h> -#include <linux/init.h> -#include <linux/types.h> - -#include "pll.h" - -static const struct davinci_pll_clk_info da830_pll_info = { - .name = "pll0", - .pllm_mask = GENMASK(4, 0), - .pllm_min = 4, - .pllm_max = 32, - .pllout_min_rate = 300000000, - .pllout_max_rate = 600000000, - .flags = PLL_HAS_CLKMODE | PLL_HAS_PREDIV | PLL_HAS_POSTDIV, -}; - -/* - * NB: Technically, the clocks flagged as SYSCLK_FIXED_DIV are "fixed ratio", - * meaning that we could change the divider as long as we keep the correct - * ratio between all of the clocks, but we don't support that because there is - * currently not a need for it. - */ - -SYSCLK(2, pll0_sysclk2, pll0_pllen, 5, SYSCLK_FIXED_DIV); -SYSCLK(3, pll0_sysclk3, pll0_pllen, 5, 0); -SYSCLK(4, pll0_sysclk4, pll0_pllen, 5, SYSCLK_FIXED_DIV); -SYSCLK(5, pll0_sysclk5, pll0_pllen, 5, 0); -SYSCLK(6, pll0_sysclk6, pll0_pllen, 5, SYSCLK_FIXED_DIV); -SYSCLK(7, pll0_sysclk7, pll0_pllen, 5, 0); - -int da830_pll_init(struct device *dev, void __iomem *base, struct regmap *cfgchip) -{ - struct clk *clk; - - davinci_pll_clk_register(dev, &da830_pll_info, "ref_clk", base, cfgchip); - - clk = davinci_pll_sysclk_register(dev, &pll0_sysclk2, base); - clk_register_clkdev(clk, "pll0_sysclk2", "da830-psc0"); - clk_register_clkdev(clk, "pll0_sysclk2", "da830-psc1"); - - clk = davinci_pll_sysclk_register(dev, &pll0_sysclk3, base); - clk_register_clkdev(clk, "pll0_sysclk3", "da830-psc0"); - - clk = davinci_pll_sysclk_register(dev, &pll0_sysclk4, base); - clk_register_clkdev(clk, "pll0_sysclk4", "da830-psc0"); - clk_register_clkdev(clk, "pll0_sysclk4", "da830-psc1"); - - clk = davinci_pll_sysclk_register(dev, &pll0_sysclk5, base); - clk_register_clkdev(clk, "pll0_sysclk5", "da830-psc1"); - - clk = davinci_pll_sysclk_register(dev, &pll0_sysclk6, base); - clk_register_clkdev(clk, "pll0_sysclk6", "da830-psc0"); - - clk = davinci_pll_sysclk_register(dev, &pll0_sysclk7, base); - - clk = davinci_pll_auxclk_register(dev, "pll0_auxclk", base); - clk_register_clkdev(clk, NULL, "i2c_davinci.1"); - clk_register_clkdev(clk, "timer0", NULL); - clk_register_clkdev(clk, NULL, "davinci-wdt"); - - return 0; -} diff --git a/drivers/clk/davinci/pll.c b/drivers/clk/davinci/pll.c index 82727b1fc67a..6807a2efa93b 100644 --- a/drivers/clk/davinci/pll.c +++ b/drivers/clk/davinci/pll.c @@ -840,25 +840,16 @@ int of_davinci_pll_init(struct device *dev, struct device_node *node, } /* needed in early boot for clocksource/clockevent */ -#ifdef CONFIG_ARCH_DAVINCI_DA850 CLK_OF_DECLARE(da850_pll0, "ti,da850-pll0", of_da850_pll0_init); -#endif static const struct of_device_id davinci_pll_of_match[] = { -#ifdef CONFIG_ARCH_DAVINCI_DA850 { .compatible = "ti,da850-pll1", .data = of_da850_pll1_init }, -#endif { } }; static const struct platform_device_id davinci_pll_id_table[] = { -#ifdef CONFIG_ARCH_DAVINCI_DA830 - { .name = "da830-pll", .driver_data = (kernel_ulong_t)da830_pll_init }, -#endif -#ifdef CONFIG_ARCH_DAVINCI_DA850 { .name = "da850-pll0", .driver_data = (kernel_ulong_t)da850_pll0_init }, { .name = "da850-pll1", .driver_data = (kernel_ulong_t)da850_pll1_init }, -#endif { } }; diff --git a/drivers/clk/davinci/psc-da830.c b/drivers/clk/davinci/psc-da830.c deleted file mode 100644 index 6481337382a6..000000000000 --- a/drivers/clk/davinci/psc-da830.c +++ /dev/null @@ -1,118 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * PSC clock descriptions for TI DA830/OMAP-L137/AM17XX - * - * Copyright (C) 2018 David Lechner <david@lechnology.com> - */ - -#include <linux/clk-provider.h> -#include <linux/clk.h> -#include <linux/clkdev.h> -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/types.h> - -#include "psc.h" - -LPSC_CLKDEV1(aemif_clkdev, NULL, "ti-aemif"); -LPSC_CLKDEV1(spi0_clkdev, NULL, "spi_davinci.0"); -LPSC_CLKDEV1(mmcsd_clkdev, NULL, "da830-mmc.0"); -LPSC_CLKDEV1(uart0_clkdev, NULL, "serial8250.0"); - -static const struct davinci_lpsc_clk_info da830_psc0_info[] = { - LPSC(0, 0, tpcc, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED), - LPSC(1, 0, tptc0, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED), - LPSC(2, 0, tptc1, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED), - LPSC(3, 0, aemif, pll0_sysclk3, aemif_clkdev, LPSC_ALWAYS_ENABLED), - LPSC(4, 0, spi0, pll0_sysclk2, spi0_clkdev, 0), - LPSC(5, 0, mmcsd, pll0_sysclk2, mmcsd_clkdev, 0), - LPSC(6, 0, aintc, pll0_sysclk4, NULL, LPSC_ALWAYS_ENABLED), - LPSC(7, 0, arm_rom, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED), - LPSC(8, 0, secu_mgr, pll0_sysclk4, NULL, LPSC_ALWAYS_ENABLED), - LPSC(9, 0, uart0, pll0_sysclk2, uart0_clkdev, 0), - LPSC(10, 0, scr0_ss, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED), - LPSC(11, 0, scr1_ss, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED), - LPSC(12, 0, scr2_ss, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED), - LPSC(13, 0, pruss, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED), - LPSC(14, 0, arm, pll0_sysclk6, NULL, LPSC_ALWAYS_ENABLED), - { } -}; - -static int da830_psc0_init(struct device *dev, void __iomem *base) -{ - return davinci_psc_register_clocks(dev, da830_psc0_info, 16, base); -} - -static struct clk_bulk_data da830_psc0_parent_clks[] = { - { .id = "pll0_sysclk2" }, - { .id = "pll0_sysclk3" }, - { .id = "pll0_sysclk4" }, - { .id = "pll0_sysclk6" }, -}; - -const struct davinci_psc_init_data da830_psc0_init_data = { - .parent_clks = da830_psc0_parent_clks, - .num_parent_clks = ARRAY_SIZE(da830_psc0_parent_clks), - .psc_init = &da830_psc0_init, -}; - -LPSC_CLKDEV3(usb0_clkdev, "fck", "da830-usb-phy-clks", - NULL, "musb-da8xx", - NULL, "cppi41-dmaengine"); -LPSC_CLKDEV1(usb1_clkdev, NULL, "ohci-da8xx"); -/* REVISIT: gpio-davinci.c should be modified to drop con_id */ -LPSC_CLKDEV1(gpio_clkdev, "gpio", NULL); -LPSC_CLKDEV2(emac_clkdev, NULL, "davinci_emac.1", - "fck", "davinci_mdio.0"); -LPSC_CLKDEV1(mcasp0_clkdev, NULL, "davinci-mcasp.0"); -LPSC_CLKDEV1(mcasp1_clkdev, NULL, "davinci-mcasp.1"); -LPSC_CLKDEV1(mcasp2_clkdev, NULL, "davinci-mcasp.2"); -LPSC_CLKDEV1(spi1_clkdev, NULL, "spi_davinci.1"); -LPSC_CLKDEV1(i2c1_clkdev, NULL, "i2c_davinci.2"); -LPSC_CLKDEV1(uart1_clkdev, NULL, "serial8250.1"); -LPSC_CLKDEV1(uart2_clkdev, NULL, "serial8250.2"); -LPSC_CLKDEV1(lcdc_clkdev, "fck", "da8xx_lcdc.0"); -LPSC_CLKDEV2(pwm_clkdev, "fck", "ehrpwm.0", - "fck", "ehrpwm.1"); -LPSC_CLKDEV3(ecap_clkdev, "fck", "ecap.0", - "fck", "ecap.1", - "fck", "ecap.2"); -LPSC_CLKDEV2(eqep_clkdev, NULL, "eqep.0", - NULL, "eqep.1"); - -static const struct davinci_lpsc_clk_info da830_psc1_info[] = { - LPSC(1, 0, usb0, pll0_sysclk2, usb0_clkdev, 0), - LPSC(2, 0, usb1, pll0_sysclk4, usb1_clkdev, 0), - LPSC(3, 0, gpio, pll0_sysclk4, gpio_clkdev, 0), - LPSC(5, 0, emac, pll0_sysclk4, emac_clkdev, 0), - LPSC(6, 0, emif3, pll0_sysclk5, NULL, LPSC_ALWAYS_ENABLED), - LPSC(7, 0, mcasp0, pll0_sysclk2, mcasp0_clkdev, 0), - LPSC(8, 0, mcasp1, pll0_sysclk2, mcasp1_clkdev, 0), - LPSC(9, 0, mcasp2, pll0_sysclk2, mcasp2_clkdev, 0), - LPSC(10, 0, spi1, pll0_sysclk2, spi1_clkdev, 0), - LPSC(11, 0, i2c1, pll0_sysclk4, i2c1_clkdev, 0), - LPSC(12, 0, uart1, pll0_sysclk2, uart1_clkdev, 0), - LPSC(13, 0, uart2, pll0_sysclk2, uart2_clkdev, 0), - LPSC(16, 0, lcdc, pll0_sysclk2, lcdc_clkdev, 0), - LPSC(17, 0, pwm, pll0_sysclk2, pwm_clkdev, 0), - LPSC(20, 0, ecap, pll0_sysclk2, ecap_clkdev, 0), - LPSC(21, 0, eqep, pll0_sysclk2, eqep_clkdev, 0), - { } -}; - -static int da830_psc1_init(struct device *dev, void __iomem *base) -{ - return davinci_psc_register_clocks(dev, da830_psc1_info, 32, base); -} - -static struct clk_bulk_data da830_psc1_parent_clks[] = { - { .id = "pll0_sysclk2" }, - { .id = "pll0_sysclk4" }, - { .id = "pll0_sysclk5" }, -}; - -const struct davinci_psc_init_data da830_psc1_init_data = { - .parent_clks = da830_psc1_parent_clks, - .num_parent_clks = ARRAY_SIZE(da830_psc1_parent_clks), - .psc_init = &da830_psc1_init, -}; diff --git a/drivers/clk/davinci/psc.c b/drivers/clk/davinci/psc.c index 355d1be0b5d8..b48322176c21 100644 --- a/drivers/clk/davinci/psc.c +++ b/drivers/clk/davinci/psc.c @@ -494,22 +494,14 @@ int of_davinci_psc_clk_init(struct device *dev, } static const struct of_device_id davinci_psc_of_match[] = { -#ifdef CONFIG_ARCH_DAVINCI_DA850 { .compatible = "ti,da850-psc0", .data = &of_da850_psc0_init_data }, { .compatible = "ti,da850-psc1", .data = &of_da850_psc1_init_data }, -#endif { } }; static const struct platform_device_id davinci_psc_id_table[] = { -#ifdef CONFIG_ARCH_DAVINCI_DA830 - { .name = "da830-psc0", .driver_data = (kernel_ulong_t)&da830_psc0_init_data }, - { .name = "da830-psc1", .driver_data = (kernel_ulong_t)&da830_psc1_init_data }, -#endif -#ifdef CONFIG_ARCH_DAVINCI_DA850 { .name = "da850-psc0", .driver_data = (kernel_ulong_t)&da850_psc0_init_data }, { .name = "da850-psc1", .driver_data = (kernel_ulong_t)&da850_psc1_init_data }, -#endif { } }; diff --git a/drivers/clk/davinci/psc.h b/drivers/clk/davinci/psc.h index bd23f6fd56df..742672843776 100644 --- a/drivers/clk/davinci/psc.h +++ b/drivers/clk/davinci/psc.h @@ -94,14 +94,9 @@ struct davinci_psc_init_data { int (*psc_init)(struct device *dev, void __iomem *base); }; -#ifdef CONFIG_ARCH_DAVINCI_DA830 -extern const struct davinci_psc_init_data da830_psc0_init_data; -extern const struct davinci_psc_init_data da830_psc1_init_data; -#endif -#ifdef CONFIG_ARCH_DAVINCI_DA850 extern const struct davinci_psc_init_data da850_psc0_init_data; extern const struct davinci_psc_init_data da850_psc1_init_data; extern const struct davinci_psc_init_data of_da850_psc0_init_data; extern const struct davinci_psc_init_data of_da850_psc1_init_data; -#endif + #endif /* __CLK_DAVINCI_PSC_H__ */ diff --git a/drivers/clk/imgtec/clk-boston.c b/drivers/clk/imgtec/clk-boston.c index b00cbd045af5..db96f8bea630 100644 --- a/drivers/clk/imgtec/clk-boston.c +++ b/drivers/clk/imgtec/clk-boston.c @@ -67,21 +67,21 @@ static void __init clk_boston_setup(struct device_node *np) hw = clk_hw_register_fixed_rate(NULL, "input", NULL, 0, in_freq); if (IS_ERR(hw)) { - pr_err("failed to register input clock: %ld\n", PTR_ERR(hw)); + pr_err("failed to register input clock: %pe\n", hw); goto fail_input; } onecell->hws[BOSTON_CLK_INPUT] = hw; hw = clk_hw_register_fixed_rate(NULL, "sys", "input", 0, sys_freq); if (IS_ERR(hw)) { - pr_err("failed to register sys clock: %ld\n", PTR_ERR(hw)); + pr_err("failed to register sys clock: %pe\n", hw); goto fail_sys; } onecell->hws[BOSTON_CLK_SYS] = hw; hw = clk_hw_register_fixed_rate(NULL, "cpu", "input", 0, cpu_freq); if (IS_ERR(hw)) { - pr_err("failed to register cpu clock: %ld\n", PTR_ERR(hw)); + pr_err("failed to register cpu clock: %pe\n", hw); goto fail_cpu; } onecell->hws[BOSTON_CLK_CPU] = hw; diff --git a/drivers/clk/keystone/syscon-clk.c b/drivers/clk/keystone/syscon-clk.c index 935d9a2d8c2b..c509929da854 100644 --- a/drivers/clk/keystone/syscon-clk.c +++ b/drivers/clk/keystone/syscon-clk.c @@ -105,6 +105,12 @@ static struct clk_hw return &priv->hw; } +static const struct regmap_config ti_syscon_regmap_cfg = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, +}; + static int ti_syscon_gate_clk_probe(struct platform_device *pdev) { const struct ti_syscon_gate_clk_data *data, *p; @@ -113,12 +119,17 @@ static int ti_syscon_gate_clk_probe(struct platform_device *pdev) int num_clks, num_parents, i; const char *parent_name; struct regmap *regmap; + void __iomem *base; data = device_get_match_data(dev); if (!data) return -EINVAL; - regmap = device_node_to_regmap(dev->of_node); + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + regmap = regmap_init_mmio(dev, base, &ti_syscon_regmap_cfg); if (IS_ERR(regmap)) return dev_err_probe(dev, PTR_ERR(regmap), "failed to get regmap\n"); diff --git a/drivers/clk/mediatek/clk-mt8188-cam.c b/drivers/clk/mediatek/clk-mt8188-cam.c index 7500bd25387f..9b029fdd584e 100644 --- a/drivers/clk/mediatek/clk-mt8188-cam.c +++ b/drivers/clk/mediatek/clk-mt8188-cam.c @@ -20,6 +20,8 @@ static const struct mtk_gate_regs cam_cg_regs = { #define GATE_CAM(_id, _name, _parent, _shift) \ GATE_MTK(_id, _name, _parent, &cam_cg_regs, _shift, &mtk_clk_gate_ops_setclr) +#define CAM_SYS_SMI_LARB_RST_OFF (0xA0) + static const struct mtk_gate cam_main_clks[] = { GATE_CAM(CLK_CAM_MAIN_LARB13, "cam_main_larb13", "top_cam", 0), GATE_CAM(CLK_CAM_MAIN_LARB14, "cam_main_larb14", "top_cam", 1), @@ -72,6 +74,17 @@ static const struct mtk_gate cam_yuvb_clks[] = { GATE_CAM(CLK_CAM_YUVB_CAMTG, "cam_yuvb_camtg", "top_cam", 2), }; +/* Reset for SMI larb 16a/16b/17a/17b */ +static u16 cam_sys_rst_ofs[] = { + CAM_SYS_SMI_LARB_RST_OFF, +}; + +static const struct mtk_clk_rst_desc cam_sys_rst_desc = { + .version = MTK_RST_SIMPLE, + .rst_bank_ofs = cam_sys_rst_ofs, + .rst_bank_nr = ARRAY_SIZE(cam_sys_rst_ofs), +}; + static const struct mtk_clk_desc cam_main_desc = { .clks = cam_main_clks, .num_clks = ARRAY_SIZE(cam_main_clks), @@ -80,21 +93,25 @@ static const struct mtk_clk_desc cam_main_desc = { static const struct mtk_clk_desc cam_rawa_desc = { .clks = cam_rawa_clks, .num_clks = ARRAY_SIZE(cam_rawa_clks), + .rst_desc = &cam_sys_rst_desc, }; static const struct mtk_clk_desc cam_rawb_desc = { .clks = cam_rawb_clks, .num_clks = ARRAY_SIZE(cam_rawb_clks), + .rst_desc = &cam_sys_rst_desc, }; static const struct mtk_clk_desc cam_yuva_desc = { .clks = cam_yuva_clks, .num_clks = ARRAY_SIZE(cam_yuva_clks), + .rst_desc = &cam_sys_rst_desc, }; static const struct mtk_clk_desc cam_yuvb_desc = { .clks = cam_yuvb_clks, .num_clks = ARRAY_SIZE(cam_yuvb_clks), + .rst_desc = &cam_sys_rst_desc, }; static const struct of_device_id of_match_clk_mt8188_cam[] = { diff --git a/drivers/clk/mediatek/clk-mt8188-img.c b/drivers/clk/mediatek/clk-mt8188-img.c index cb2fbd4136b9..d44bfbd8308a 100644 --- a/drivers/clk/mediatek/clk-mt8188-img.c +++ b/drivers/clk/mediatek/clk-mt8188-img.c @@ -20,6 +20,8 @@ static const struct mtk_gate_regs imgsys_cg_regs = { #define GATE_IMGSYS(_id, _name, _parent, _shift) \ GATE_MTK(_id, _name, _parent, &imgsys_cg_regs, _shift, &mtk_clk_gate_ops_setclr) +#define IMG_SYS_SMI_LARB_RST_OFF (0xC) + static const struct mtk_gate imgsys_main_clks[] = { GATE_IMGSYS(CLK_IMGSYS_MAIN_LARB9, "imgsys_main_larb9", "top_img", 0), GATE_IMGSYS(CLK_IMGSYS_MAIN_TRAW0, "imgsys_main_traw0", "top_img", 1), @@ -58,6 +60,17 @@ static const struct mtk_gate imgsys1_dip_nr_clks[] = { GATE_IMGSYS(CLK_IMGSYS1_DIP_NR_DIP_NR, "imgsys1_dip_nr_dip_nr", "top_img", 1), }; +/* Reset for SMI larb 10/11a/11b/11c/15 */ +static u16 img_sys_rst_ofs[] = { + IMG_SYS_SMI_LARB_RST_OFF, +}; + +static const struct mtk_clk_rst_desc img_sys_rst_desc = { + .version = MTK_RST_SIMPLE, + .rst_bank_ofs = img_sys_rst_ofs, + .rst_bank_nr = ARRAY_SIZE(img_sys_rst_ofs), +}; + static const struct mtk_clk_desc imgsys_main_desc = { .clks = imgsys_main_clks, .num_clks = ARRAY_SIZE(imgsys_main_clks), @@ -66,26 +79,31 @@ static const struct mtk_clk_desc imgsys_main_desc = { static const struct mtk_clk_desc imgsys_wpe1_desc = { .clks = imgsys_wpe1_clks, .num_clks = ARRAY_SIZE(imgsys_wpe1_clks), + .rst_desc = &img_sys_rst_desc, }; static const struct mtk_clk_desc imgsys_wpe2_desc = { .clks = imgsys_wpe2_clks, .num_clks = ARRAY_SIZE(imgsys_wpe2_clks), + .rst_desc = &img_sys_rst_desc, }; static const struct mtk_clk_desc imgsys_wpe3_desc = { .clks = imgsys_wpe3_clks, .num_clks = ARRAY_SIZE(imgsys_wpe3_clks), + .rst_desc = &img_sys_rst_desc, }; static const struct mtk_clk_desc imgsys1_dip_top_desc = { .clks = imgsys1_dip_top_clks, .num_clks = ARRAY_SIZE(imgsys1_dip_top_clks), + .rst_desc = &img_sys_rst_desc, }; static const struct mtk_clk_desc imgsys1_dip_nr_desc = { .clks = imgsys1_dip_nr_clks, .num_clks = ARRAY_SIZE(imgsys1_dip_nr_clks), + .rst_desc = &img_sys_rst_desc, }; static const struct of_device_id of_match_clk_mt8188_imgsys_main[] = { diff --git a/drivers/clk/mediatek/clk-mt8188-ipe.c b/drivers/clk/mediatek/clk-mt8188-ipe.c index 8f1933b71e28..70a011c1f9ce 100644 --- a/drivers/clk/mediatek/clk-mt8188-ipe.c +++ b/drivers/clk/mediatek/clk-mt8188-ipe.c @@ -20,6 +20,8 @@ static const struct mtk_gate_regs ipe_cg_regs = { #define GATE_IPE(_id, _name, _parent, _shift) \ GATE_MTK(_id, _name, _parent, &ipe_cg_regs, _shift, &mtk_clk_gate_ops_setclr) +#define IPE_SYS_SMI_LARB_RST_OFF (0xC) + static const struct mtk_gate ipe_clks[] = { GATE_IPE(CLK_IPE_DPE, "ipe_dpe", "top_ipe", 0), GATE_IPE(CLK_IPE_FDVT, "ipe_fdvt", "top_ipe", 1), @@ -28,9 +30,21 @@ static const struct mtk_gate ipe_clks[] = { GATE_IPE(CLK_IPE_SMI_LARB12, "ipe_smi_larb12", "top_ipe", 4), }; +/* Reset for SMI larb 12 */ +static u16 ipe_sys_rst_ofs[] = { + IPE_SYS_SMI_LARB_RST_OFF, +}; + +static const struct mtk_clk_rst_desc ipe_sys_rst_desc = { + .version = MTK_RST_SIMPLE, + .rst_bank_ofs = ipe_sys_rst_ofs, + .rst_bank_nr = ARRAY_SIZE(ipe_sys_rst_ofs), +}; + static const struct mtk_clk_desc ipe_desc = { .clks = ipe_clks, .num_clks = ARRAY_SIZE(ipe_clks), + .rst_desc = &ipe_sys_rst_desc, }; static const struct of_device_id of_match_clk_mt8188_ipe[] = { diff --git a/drivers/clk/mediatek/clk-mt8188-vdo1.c b/drivers/clk/mediatek/clk-mt8188-vdo1.c index 4fa355f8f0c2..f715d45e545e 100644 --- a/drivers/clk/mediatek/clk-mt8188-vdo1.c +++ b/drivers/clk/mediatek/clk-mt8188-vdo1.c @@ -43,6 +43,12 @@ static const struct mtk_gate_regs vdo1_4_cg_regs = { .sta_ofs = 0x140, }; +static const struct mtk_gate_regs vdo1_5_cg_regs = { + .set_ofs = 0x400, + .clr_ofs = 0x400, + .sta_ofs = 0x400, +}; + #define GATE_VDO1_0(_id, _name, _parent, _shift) \ GATE_MTK(_id, _name, _parent, &vdo1_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr) @@ -62,6 +68,9 @@ static const struct mtk_gate_regs vdo1_4_cg_regs = { #define GATE_VDO1_4(_id, _name, _parent, _shift) \ GATE_MTK(_id, _name, _parent, &vdo1_4_cg_regs, _shift, &mtk_clk_gate_ops_setclr) +#define GATE_VDO1_5(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &vdo1_5_cg_regs, _shift, &mtk_clk_gate_ops_setclr) + static const struct mtk_gate vdo1_clks[] = { /* VDO1_0 */ GATE_VDO1_0(CLK_VDO1_SMI_LARB2, "vdo1_smi_larb2", "top_vpp", 0), @@ -129,6 +138,8 @@ static const struct mtk_gate vdo1_clks[] = { GATE_VDO1_3(CLK_VDO1_DISP_MONITOR_DPINTF, "vdo1_disp_monitor_dpintf_ck", "top_vpp", 17), /* VDO1_4 */ GATE_VDO1_4(CLK_VDO1_26M_SLOW, "vdo1_26m_slow_ck", "clk26m", 8), + /* VDO1_5 */ + GATE_VDO1_5(CLK_VDO1_DPI1_HDMI, "vdo1_dpi1_hdmi", "hdmi_txpll", 0), }; static const struct mtk_clk_desc vdo1_desc = { diff --git a/drivers/clk/mmp/clk-pxa1908-apmu.c b/drivers/clk/mmp/clk-pxa1908-apmu.c index 8cfb1258202f..d3a070687fc5 100644 --- a/drivers/clk/mmp/clk-pxa1908-apmu.c +++ b/drivers/clk/mmp/clk-pxa1908-apmu.c @@ -87,8 +87,8 @@ static int pxa1908_apmu_probe(struct platform_device *pdev) struct pxa1908_clk_unit *pxa_unit; pxa_unit = devm_kzalloc(&pdev->dev, sizeof(*pxa_unit), GFP_KERNEL); - if (IS_ERR(pxa_unit)) - return PTR_ERR(pxa_unit); + if (!pxa_unit) + return -ENOMEM; pxa_unit->base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(pxa_unit->base)) diff --git a/drivers/clk/renesas/r7s9210-cpg-mssr.c b/drivers/clk/renesas/r7s9210-cpg-mssr.c index a85227c248f3..e1812867a6da 100644 --- a/drivers/clk/renesas/r7s9210-cpg-mssr.c +++ b/drivers/clk/renesas/r7s9210-cpg-mssr.c @@ -170,11 +170,12 @@ static struct clk * __init rza2_cpg_clk_register(struct device *dev, if (IS_ERR(parent)) return ERR_CAST(parent); - switch (core->id) { - case CLK_MAIN: + switch (core->type) { + case CLK_TYPE_RZA_MAIN: + r7s9210_update_clk_table(parent, base); break; - case CLK_PLL: + case CLK_TYPE_RZA_PLL: if (cpg_mode) mult = 44; /* Divider 1 is 1/2 */ else @@ -185,9 +186,6 @@ static struct clk * __init rza2_cpg_clk_register(struct device *dev, return ERR_PTR(-EINVAL); } - if (core->id == CLK_MAIN) - r7s9210_update_clk_table(parent, base); - return clk_register_fixed_factor(NULL, core->name, __clk_get_name(parent), 0, mult, div); } diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c b/drivers/clk/renesas/r8a779a0-cpg-mssr.c index 9c7e4094705c..1be7b9592aa6 100644 --- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c @@ -138,6 +138,10 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = { }; static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = { + DEF_MOD("isp0", 16, R8A779A0_CLK_S1D1), + DEF_MOD("isp1", 17, R8A779A0_CLK_S1D1), + DEF_MOD("isp2", 18, R8A779A0_CLK_S1D1), + DEF_MOD("isp3", 19, R8A779A0_CLK_S1D1), DEF_MOD("avb0", 211, R8A779A0_CLK_S3D2), DEF_MOD("avb1", 212, R8A779A0_CLK_S3D2), DEF_MOD("avb2", 213, R8A779A0_CLK_S3D2), @@ -238,6 +242,10 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = { DEF_MOD("vspx1", 1029, R8A779A0_CLK_S1D1), DEF_MOD("vspx2", 1030, R8A779A0_CLK_S1D1), DEF_MOD("vspx3", 1031, R8A779A0_CLK_S1D1), + DEF_MOD("fcpvx0", 1100, R8A779A0_CLK_S1D1), + DEF_MOD("fcpvx1", 1101, R8A779A0_CLK_S1D1), + DEF_MOD("fcpvx2", 1102, R8A779A0_CLK_S1D1), + DEF_MOD("fcpvx3", 1103, R8A779A0_CLK_S1D1), }; static const unsigned int r8a779a0_crit_mod_clks[] __initconst = { diff --git a/drivers/clk/renesas/r8a779g0-cpg-mssr.c b/drivers/clk/renesas/r8a779g0-cpg-mssr.c index d45571096b96..015b9773cc55 100644 --- a/drivers/clk/renesas/r8a779g0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c @@ -163,6 +163,8 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = { }; static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = { + DEF_MOD("isp0", 16, R8A779G0_CLK_S0D2_VIO), + DEF_MOD("isp1", 17, R8A779G0_CLK_S0D2_VIO), DEF_MOD("avb0", 211, R8A779G0_CLK_S0D4_HSC), DEF_MOD("avb1", 212, R8A779G0_CLK_S0D4_HSC), DEF_MOD("avb2", 213, R8A779G0_CLK_S0D4_HSC), diff --git a/drivers/clk/renesas/r8a779h0-cpg-mssr.c b/drivers/clk/renesas/r8a779h0-cpg-mssr.c index 607fa815b6c1..ffea06d77d5e 100644 --- a/drivers/clk/renesas/r8a779h0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779h0-cpg-mssr.c @@ -171,6 +171,7 @@ static const struct cpg_core_clk r8a779h0_core_clks[] __initconst = { }; static const struct mssr_mod_clk r8a779h0_mod_clks[] __initconst = { + DEF_MOD("isp0", 16, R8A779H0_CLK_S0D2_VIO), DEF_MOD("avb0:rgmii0", 211, R8A779H0_CLK_S0D8_HSC), DEF_MOD("avb1:rgmii1", 212, R8A779H0_CLK_S0D8_HSC), DEF_MOD("avb2:rgmii2", 213, R8A779H0_CLK_S0D8_HSC), @@ -238,6 +239,8 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] __initconst = { DEF_MOD("pfc1", 916, R8A779H0_CLK_CP), DEF_MOD("pfc2", 917, R8A779H0_CLK_CP), DEF_MOD("tsc2:tsc1", 919, R8A779H0_CLK_CL16M), + DEF_MOD("vspx0", 1028, R8A779H0_CLK_S0D1_VIO), + DEF_MOD("fcpvx0", 1100, R8A779H0_CLK_S0D1_VIO), DEF_MOD("ssiu", 2926, R8A779H0_CLK_S0D6_PER), DEF_MOD("ssi", 2927, R8A779H0_CLK_S0D6_PER), }; diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c index c3c2b0c43983..fce2eecfa8c0 100644 --- a/drivers/clk/renesas/r9a07g043-cpg.c +++ b/drivers/clk/renesas/r9a07g043-cpg.c @@ -89,7 +89,9 @@ static const struct clk_div_table dtable_1_32[] = { /* Mux clock tables */ static const char * const sel_pll3_3[] = { ".pll3_533", ".pll3_400" }; +#ifdef CONFIG_ARM64 static const char * const sel_pll6_2[] = { ".pll6_250", ".pll5_250" }; +#endif static const char * const sel_sdhi[] = { ".clk_533", ".clk_400", ".clk_266" }; static const u32 mtable_sdhi[] = { 1, 2, 3 }; @@ -137,7 +139,12 @@ static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = { DEF_DIV("P2", R9A07G043_CLK_P2, CLK_PLL3_DIV2_4_2, DIVPL3A, dtable_1_32), DEF_FIXED("M0", R9A07G043_CLK_M0, CLK_PLL3_DIV2_4, 1, 1), DEF_FIXED("ZT", R9A07G043_CLK_ZT, CLK_PLL3_DIV2_4_2, 1, 1), +#ifdef CONFIG_ARM64 DEF_MUX("HP", R9A07G043_CLK_HP, SEL_PLL6_2, sel_pll6_2), +#endif +#ifdef CONFIG_RISCV + DEF_FIXED("HP", R9A07G043_CLK_HP, CLK_PLL6_250, 1, 1), +#endif DEF_FIXED("SPI0", R9A07G043_CLK_SPI0, CLK_DIV_PLL3_C, 1, 2), DEF_FIXED("SPI1", R9A07G043_CLK_SPI1, CLK_DIV_PLL3_C, 1, 4), DEF_SD_MUX("SD0", R9A07G043_CLK_SD0, SEL_SDHI0, SEL_SDHI0_STS, sel_sdhi, diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c index f6df3f7a31b5..77ca3a789568 100644 --- a/drivers/clk/renesas/r9a07g044-cpg.c +++ b/drivers/clk/renesas/r9a07g044-cpg.c @@ -94,6 +94,41 @@ static const struct clk_div_table dtable_1_32[] = { {0, 0}, }; +#ifdef CONFIG_CLK_R9A07G054 +static const struct clk_div_table dtable_4_32[] = { + {3, 4}, + {4, 5}, + {5, 6}, + {6, 7}, + {7, 8}, + {8, 9}, + {9, 10}, + {10, 11}, + {11, 12}, + {12, 13}, + {13, 14}, + {14, 15}, + {15, 16}, + {16, 17}, + {17, 18}, + {18, 19}, + {19, 20}, + {20, 21}, + {21, 22}, + {22, 23}, + {23, 24}, + {24, 25}, + {25, 26}, + {26, 27}, + {27, 28}, + {28, 29}, + {29, 30}, + {30, 31}, + {31, 32}, + {0, 0}, +}; +#endif + static const struct clk_div_table dtable_16_128[] = { {0, 16}, {1, 32}, @@ -114,7 +149,7 @@ static const u32 mtable_sdhi[] = { 1, 2, 3 }; static const struct { struct cpg_core_clk common[56]; #ifdef CONFIG_CLK_R9A07G054 - struct cpg_core_clk drp[0]; + struct cpg_core_clk drp[3]; #endif } core_clks __initconst = { .common = { @@ -192,6 +227,9 @@ static const struct { }, #ifdef CONFIG_CLK_R9A07G054 .drp = { + DEF_FIXED("DRP_M", R9A07G054_CLK_DRP_M, CLK_PLL3, 1, 5), + DEF_FIXED("DRP_D", R9A07G054_CLK_DRP_D, CLK_PLL3, 1, 2), + DEF_DIV("DRP_A", R9A07G054_CLK_DRP_A, CLK_PLL3, DIVPL3E, dtable_4_32), }, #endif }; @@ -199,7 +237,7 @@ static const struct { static const struct { struct rzg2l_mod_clk common[79]; #ifdef CONFIG_CLK_R9A07G054 - struct rzg2l_mod_clk drp[0]; + struct rzg2l_mod_clk drp[5]; #endif } mod_clks = { .common = { @@ -364,6 +402,16 @@ static const struct { }, #ifdef CONFIG_CLK_R9A07G054 .drp = { + DEF_MOD("stpai_initclk", R9A07G054_STPAI_INITCLK, R9A07G044_OSCCLK, + 0x5e8, 0), + DEF_MOD("stpai_aclk", R9A07G054_STPAI_ACLK, R9A07G044_CLK_P1, + 0x5e8, 1), + DEF_MOD("stpai_mclk", R9A07G054_STPAI_MCLK, R9A07G054_CLK_DRP_M, + 0x5e8, 2), + DEF_MOD("stpai_dclkin", R9A07G054_STPAI_DCLKIN, R9A07G054_CLK_DRP_D, + 0x5e8, 3), + DEF_MOD("stpai_aclk_drp", R9A07G054_STPAI_ACLK_DRP, R9A07G054_CLK_DRP_A, + 0x5e8, 4), }, #endif }; @@ -430,6 +478,9 @@ static const struct rzg2l_reset r9a07g044_resets[] = { DEF_RST(R9A07G044_ADC_PRESETN, 0x8a8, 0), DEF_RST(R9A07G044_ADC_ADRST_N, 0x8a8, 1), DEF_RST(R9A07G044_TSU_PRESETN, 0x8ac, 0), +#ifdef CONFIG_CLK_R9A07G054 + DEF_RST(R9A07G054_STPAI_ARESETN, 0x8e8, 0), +#endif }; static const unsigned int r9a07g044_crit_mod_clks[] __initconst = { diff --git a/drivers/clk/renesas/r9a08g045-cpg.c b/drivers/clk/renesas/r9a08g045-cpg.c index 0e7e3bf05b52..4035f3443598 100644 --- a/drivers/clk/renesas/r9a08g045-cpg.c +++ b/drivers/clk/renesas/r9a08g045-cpg.c @@ -51,7 +51,7 @@ #define G3S_SEL_SDHI2 SEL_PLL_PACK(G3S_CPG_SDHI_DSEL, 8, 2) /* PLL 1/4/6 configuration registers macro. */ -#define G3S_PLL146_CONF(clk1, clk2) ((clk1) << 22 | (clk2) << 12) +#define G3S_PLL146_CONF(clk1, clk2, setting) ((clk1) << 22 | (clk2) << 12 | (setting)) #define DEF_G3S_MUX(_name, _id, _conf, _parent_names, _mux_flags, _clk_flags) \ DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = (_conf), \ @@ -134,7 +134,8 @@ static const struct cpg_core_clk r9a08g045_core_clks[] __initconst = { /* Internal Core Clocks */ DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000), - DEF_G3S_PLL(".pll1", CLK_PLL1, CLK_EXTAL, G3S_PLL146_CONF(0x4, 0x8)), + DEF_G3S_PLL(".pll1", CLK_PLL1, CLK_EXTAL, G3S_PLL146_CONF(0x4, 0x8, 0x100), + 1100000000UL), DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3), DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3), DEF_FIXED(".pll4", CLK_PLL4, CLK_EXTAL, 100, 3), @@ -241,6 +242,7 @@ static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = { DEF_MOD("gpio_hclk", R9A08G045_GPIO_HCLK, R9A08G045_OSCCLK, 0x598, 0), DEF_MOD("adc_adclk", R9A08G045_ADC_ADCLK, R9A08G045_CLK_TSU, 0x5a8, 0), DEF_MOD("adc_pclk", R9A08G045_ADC_PCLK, R9A08G045_CLK_TSU, 0x5a8, 1), + DEF_MOD("tsu_pclk", R9A08G045_TSU_PCLK, R9A08G045_CLK_TSU, 0x5ac, 0), DEF_MOD("vbat_bclk", R9A08G045_VBAT_BCLK, R9A08G045_OSCCLK, 0x614, 0), }; @@ -279,6 +281,7 @@ static const struct rzg2l_reset r9a08g045_resets[] = { DEF_RST(R9A08G045_GPIO_SPARE_RESETN, 0x898, 2), DEF_RST(R9A08G045_ADC_PRESETN, 0x8a8, 0), DEF_RST(R9A08G045_ADC_ADRST_N, 0x8a8, 1), + DEF_RST(R9A08G045_TSU_PRESETN, 0x8ac, 0), DEF_RST(R9A08G045_VBAT_BRESETN, 0x914, 0), }; @@ -353,6 +356,8 @@ static const struct rzg2l_cpg_pm_domain_init_data r9a08g045_pm_domains[] = { DEF_REG_CONF(CPG_BUS_MCPU3_MSTOP, BIT(4)), 0), DEF_PD("adc", R9A08G045_PD_ADC, DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(14)), 0), + DEF_PD("tsu", R9A08G045_PD_TSU, + DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(15)), 0), DEF_PD("vbat", R9A08G045_PD_VBAT, DEF_REG_CONF(CPG_BUS_MCPU3_MSTOP, BIT(8)), GENPD_FLAG_ALWAYS_ON), diff --git a/drivers/clk/renesas/r9a09g047-cpg.c b/drivers/clk/renesas/r9a09g047-cpg.c index 536d922bed70..e9cf4342d0cf 100644 --- a/drivers/clk/renesas/r9a09g047-cpg.c +++ b/drivers/clk/renesas/r9a09g047-cpg.c @@ -28,12 +28,19 @@ enum clk_ids { CLK_PLLCLN, CLK_PLLDTY, CLK_PLLCA55, + CLK_PLLVDO, /* Internal Core Clocks */ CLK_PLLCM33_DIV16, + CLK_PLLCLN_DIV2, + CLK_PLLCLN_DIV8, CLK_PLLCLN_DIV16, + CLK_PLLCLN_DIV20, CLK_PLLDTY_ACPU, + CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU_DIV4, + CLK_PLLDTY_DIV16, + CLK_PLLVDO_CRU0, /* Module Clocks */ MOD_CLK_BASE, @@ -47,6 +54,12 @@ static const struct clk_div_table dtable_1_8[] = { {0, 0}, }; +static const struct clk_div_table dtable_2_4[] = { + {0, 2}, + {1, 4}, + {0, 0}, +}; + static const struct clk_div_table dtable_2_64[] = { {0, 2}, {1, 4}, @@ -67,14 +80,22 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = { DEF_FIXED(".pllcln", CLK_PLLCLN, CLK_QEXTAL, 200, 3), DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3), DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLL_CONF(0x64)), + DEF_FIXED(".pllvdo", CLK_PLLVDO, CLK_QEXTAL, 105, 2), /* Internal Core Clocks */ DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16), + DEF_FIXED(".pllcln_div2", CLK_PLLCLN_DIV2, CLK_PLLCLN, 1, 2), + DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8), DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16), + DEF_FIXED(".pllcln_div20", CLK_PLLCLN_DIV20, CLK_PLLCLN, 1, 20), DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64), + DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1, 2), DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4), + DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16), + + DEF_DDIV(".pllvdo_cru0", CLK_PLLVDO_CRU0, CLK_PLLVDO, CDDIV3_DIVCTL3, dtable_2_4), /* Core Clocks */ DEF_FIXED("sys_0_pclk", R9A09G047_SYS_0_PCLK, CLK_QEXTAL, 1, 1), @@ -90,8 +111,22 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = { }; static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = { + DEF_MOD_CRITICAL("icu_0_pclk_i", CLK_PLLCM33_DIV16, 0, 5, 0, 5, + BUS_MSTOP_NONE), DEF_MOD_CRITICAL("gic_0_gicclk", CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19, BUS_MSTOP(3, BIT(5))), + DEF_MOD("wdt_1_clkp", CLK_PLLCLN_DIV16, 4, 13, 2, 13, + BUS_MSTOP(1, BIT(0))), + DEF_MOD("wdt_1_clk_loco", CLK_QEXTAL, 4, 14, 2, 14, + BUS_MSTOP(1, BIT(0))), + DEF_MOD("wdt_2_clkp", CLK_PLLCLN_DIV16, 4, 15, 2, 15, + BUS_MSTOP(5, BIT(12))), + DEF_MOD("wdt_2_clk_loco", CLK_QEXTAL, 5, 0, 2, 16, + BUS_MSTOP(5, BIT(12))), + DEF_MOD("wdt_3_clkp", CLK_PLLCLN_DIV16, 5, 1, 2, 17, + BUS_MSTOP(5, BIT(13))), + DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18, + BUS_MSTOP(5, BIT(13))), DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15, BUS_MSTOP(3, BIT(14))), DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19, @@ -112,12 +147,54 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = { BUS_MSTOP(1, BIT(7))), DEF_MOD("riic_7_ckm", CLK_PLLCLN_DIV16, 9, 11, 4, 27, BUS_MSTOP(1, BIT(8))), + DEF_MOD("canfd_0_pclk", CLK_PLLCLN_DIV16, 9, 12, 4, 28, + BUS_MSTOP(10, BIT(14))), + DEF_MOD("canfd_0_clk_ram", CLK_PLLCLN_DIV8, 9, 13, 4, 29, + BUS_MSTOP(10, BIT(14))), + DEF_MOD("canfd_0_clkc", CLK_PLLCLN_DIV20, 9, 14, 4, 30, + BUS_MSTOP(10, BIT(14))), + DEF_MOD("sdhi_0_imclk", CLK_PLLCLN_DIV8, 10, 3, 5, 3, + BUS_MSTOP(8, BIT(2))), + DEF_MOD("sdhi_0_imclk2", CLK_PLLCLN_DIV8, 10, 4, 5, 4, + BUS_MSTOP(8, BIT(2))), + DEF_MOD("sdhi_0_clk_hs", CLK_PLLCLN_DIV2, 10, 5, 5, 5, + BUS_MSTOP(8, BIT(2))), + DEF_MOD("sdhi_0_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 6, 5, 6, + BUS_MSTOP(8, BIT(2))), + DEF_MOD("sdhi_1_imclk", CLK_PLLCLN_DIV8, 10, 7, 5, 7, + BUS_MSTOP(8, BIT(3))), + DEF_MOD("sdhi_1_imclk2", CLK_PLLCLN_DIV8, 10, 8, 5, 8, + BUS_MSTOP(8, BIT(3))), + DEF_MOD("sdhi_1_clk_hs", CLK_PLLCLN_DIV2, 10, 9, 5, 9, + BUS_MSTOP(8, BIT(3))), + DEF_MOD("sdhi_1_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 10, 5, 10, + BUS_MSTOP(8, BIT(3))), + DEF_MOD("sdhi_2_imclk", CLK_PLLCLN_DIV8, 10, 11, 5, 11, + BUS_MSTOP(8, BIT(4))), + DEF_MOD("sdhi_2_imclk2", CLK_PLLCLN_DIV8, 10, 12, 5, 12, + BUS_MSTOP(8, BIT(4))), + DEF_MOD("sdhi_2_clk_hs", CLK_PLLCLN_DIV2, 10, 13, 5, 13, + BUS_MSTOP(8, BIT(4))), + DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14, + BUS_MSTOP(8, BIT(4))), + DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18, + BUS_MSTOP(9, BIT(4))), + DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19, + BUS_MSTOP(9, BIT(4))), + DEF_MOD("cru_0_pclk", CLK_PLLDTY_DIV16, 13, 4, 6, 20, + BUS_MSTOP(9, BIT(4))), + DEF_MOD("tsu_1_pclk", CLK_QEXTAL, 16, 10, 8, 10, + BUS_MSTOP(2, BIT(15))), }; static const struct rzv2h_reset r9a09g047_resets[] __initconst = { DEF_RST(3, 0, 1, 1), /* SYS_0_PRESETN */ + DEF_RST(3, 6, 1, 7), /* ICU_0_PRESETN_I */ DEF_RST(3, 8, 1, 9), /* GIC_0_GICRESET_N */ DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */ + DEF_RST(7, 6, 3, 7), /* WDT_1_RESET */ + DEF_RST(7, 7, 3, 8), /* WDT_2_RESET */ + DEF_RST(7, 8, 3, 9), /* WDT_3_RESET */ DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */ DEF_RST(9, 8, 4, 9), /* RIIC_0_MRST */ DEF_RST(9, 9, 4, 10), /* RIIC_1_MRST */ @@ -128,6 +205,15 @@ static const struct rzv2h_reset r9a09g047_resets[] __initconst = { DEF_RST(9, 14, 4, 15), /* RIIC_6_MRST */ DEF_RST(9, 15, 4, 16), /* RIIC_7_MRST */ DEF_RST(10, 0, 4, 17), /* RIIC_8_MRST */ + DEF_RST(10, 1, 4, 18), /* CANFD_0_RSTP_N */ + DEF_RST(10, 2, 4, 19), /* CANFD_0_RSTC_N */ + DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */ + DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */ + DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */ + DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */ + DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */ + DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */ + DEF_RST(15, 8, 7, 9), /* TSU_1_PRESETN */ }; const struct rzv2h_cpg_info r9a09g047_cpg_info __initconst = { diff --git a/drivers/clk/renesas/r9a09g057-cpg.c b/drivers/clk/renesas/r9a09g057-cpg.c index 3705e18f66ad..d63eafbca780 100644 --- a/drivers/clk/renesas/r9a09g057-cpg.c +++ b/drivers/clk/renesas/r9a09g057-cpg.c @@ -31,6 +31,8 @@ enum clk_ids { CLK_PLLVDO, /* Internal Core Clocks */ + CLK_PLLCM33_DIV4, + CLK_PLLCM33_DIV4_PLLCM33, CLK_PLLCM33_DIV16, CLK_PLLCLN_DIV2, CLK_PLLCLN_DIV8, @@ -39,6 +41,8 @@ enum clk_ids { CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_DIV16, + CLK_PLLDTY_RCPU, + CLK_PLLDTY_RCPU_DIV4, CLK_PLLVDO_CRU0, CLK_PLLVDO_CRU1, CLK_PLLVDO_CRU2, @@ -85,6 +89,9 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = { DEF_FIXED(".pllvdo", CLK_PLLVDO, CLK_QEXTAL, 105, 2), /* Internal Core Clocks */ + DEF_FIXED(".pllcm33_div4", CLK_PLLCM33_DIV4, CLK_PLLCM33, 1, 4), + DEF_DDIV(".pllcm33_div4_pllcm33", CLK_PLLCM33_DIV4_PLLCM33, + CLK_PLLCM33_DIV4, CDDIV0_DIVCTL1, dtable_2_64), DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16), DEF_FIXED(".pllcln_div2", CLK_PLLCLN_DIV2, CLK_PLLCLN, 1, 2), @@ -95,6 +102,8 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = { DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1, 2), DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4), DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16), + DEF_DDIV(".plldty_rcpu", CLK_PLLDTY_RCPU, CLK_PLLDTY, CDDIV3_DIVCTL2, dtable_2_64), + DEF_FIXED(".plldty_rcpu_div4", CLK_PLLDTY_RCPU_DIV4, CLK_PLLDTY_RCPU, 1, 4), DEF_DDIV(".pllvdo_cru0", CLK_PLLVDO_CRU0, CLK_PLLVDO, CDDIV3_DIVCTL3, dtable_2_4), DEF_DDIV(".pllvdo_cru1", CLK_PLLVDO_CRU1, CLK_PLLVDO, CDDIV4_DIVCTL0, dtable_2_4), @@ -115,6 +124,16 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = { }; static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = { + DEF_MOD("dmac_0_aclk", CLK_PLLCM33_DIV4_PLLCM33, 0, 0, 0, 0, + BUS_MSTOP(5, BIT(9))), + DEF_MOD("dmac_1_aclk", CLK_PLLDTY_ACPU_DIV2, 0, 1, 0, 1, + BUS_MSTOP(3, BIT(2))), + DEF_MOD("dmac_2_aclk", CLK_PLLDTY_ACPU_DIV2, 0, 2, 0, 2, + BUS_MSTOP(3, BIT(3))), + DEF_MOD("dmac_3_aclk", CLK_PLLDTY_RCPU_DIV4, 0, 3, 0, 3, + BUS_MSTOP(10, BIT(11))), + DEF_MOD("dmac_4_aclk", CLK_PLLDTY_RCPU_DIV4, 0, 4, 0, 4, + BUS_MSTOP(10, BIT(12))), DEF_MOD_CRITICAL("icu_0_pclk_i", CLK_PLLCM33_DIV16, 0, 5, 0, 5, BUS_MSTOP_NONE), DEF_MOD_CRITICAL("gic_0_gicclk", CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19, @@ -223,6 +242,11 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = { static const struct rzv2h_reset r9a09g057_resets[] __initconst = { DEF_RST(3, 0, 1, 1), /* SYS_0_PRESETN */ + DEF_RST(3, 1, 1, 2), /* DMAC_0_ARESETN */ + DEF_RST(3, 2, 1, 3), /* DMAC_1_ARESETN */ + DEF_RST(3, 3, 1, 4), /* DMAC_2_ARESETN */ + DEF_RST(3, 4, 1, 5), /* DMAC_3_ARESETN */ + DEF_RST(3, 5, 1, 6), /* DMAC_4_ARESETN */ DEF_RST(3, 6, 1, 7), /* ICU_0_PRESETN_I */ DEF_RST(3, 8, 1, 9), /* GIC_0_GICRESET_N */ DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */ diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c index bf85501709f0..da021ee446ec 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.c +++ b/drivers/clk/renesas/renesas-cpg-mssr.c @@ -338,11 +338,6 @@ static void __init cpg_mssr_register_core_clk(const struct cpg_core_clk *core, WARN_DEBUG(id >= priv->num_core_clks); WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT); - if (!core->name) { - /* Skip NULLified clock */ - return; - } - switch (core->type) { case CLK_TYPE_IN: clk = of_clk_get_by_name(priv->np, core->name); diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index ddf722ca79eb..b91dfbfb01e3 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -51,6 +51,7 @@ #define RZG3S_DIV_M GENMASK(25, 22) #define RZG3S_DIV_NI GENMASK(21, 13) #define RZG3S_DIV_NF GENMASK(12, 1) +#define RZG3S_SEL_PLL BIT(0) #define CLK_ON_R(reg) (reg) #define CLK_MON_R(reg) (0x180 + (reg)) @@ -60,6 +61,7 @@ #define GET_REG_OFFSET(val) ((val >> 20) & 0xfff) #define GET_REG_SAMPLL_CLK1(val) ((val >> 22) & 0xfff) #define GET_REG_SAMPLL_CLK2(val) ((val >> 12) & 0xfff) +#define GET_REG_SAMPLL_SETTING(val) ((val) & 0xfff) #define CPG_WEN_BIT BIT(16) @@ -943,6 +945,7 @@ rzg2l_cpg_sipll5_register(const struct cpg_core_clk *core, struct pll_clk { struct clk_hw hw; + unsigned long default_rate; unsigned int conf; unsigned int type; void __iomem *base; @@ -980,12 +983,19 @@ static unsigned long rzg3s_cpg_pll_clk_recalc_rate(struct clk_hw *hw, { struct pll_clk *pll_clk = to_pll(hw); struct rzg2l_cpg_priv *priv = pll_clk->priv; - u32 nir, nfr, mr, pr, val; + u32 nir, nfr, mr, pr, val, setting; u64 rate; if (pll_clk->type != CLK_TYPE_G3S_PLL) return parent_rate; + setting = GET_REG_SAMPLL_SETTING(pll_clk->conf); + if (setting) { + val = readl(priv->base + setting); + if (val & RZG3S_SEL_PLL) + return pll_clk->default_rate; + } + val = readl(priv->base + GET_REG_SAMPLL_CLK1(pll_clk->conf)); pr = 1 << FIELD_GET(RZG3S_DIV_P, val); @@ -1038,6 +1048,7 @@ rzg2l_cpg_pll_clk_register(const struct cpg_core_clk *core, pll_clk->base = priv->base; pll_clk->priv = priv; pll_clk->type = core->type; + pll_clk->default_rate = core->default_rate; ret = devm_clk_hw_register(dev, &pll_clk->hw); if (ret) @@ -1105,11 +1116,6 @@ rzg2l_cpg_register_core_clk(const struct cpg_core_clk *core, WARN_DEBUG(id >= priv->num_core_clks); WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT); - if (!core->name) { - /* Skip NULLified clock */ - return; - } - switch (core->type) { case CLK_TYPE_IN: clk = of_clk_get_by_name(priv->dev->of_node, core->name); @@ -1228,8 +1234,8 @@ static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable) error = readl_poll_timeout_atomic(priv->base + CLK_MON_R(reg), value, value & bitmask, 0, 10); if (error) - dev_err(dev, "Failed to enable CLK_ON %p\n", - priv->base + CLK_ON_R(reg)); + dev_err(dev, "Failed to enable CLK_ON 0x%x/%pC\n", + CLK_ON_R(reg), hw->clk); return error; } @@ -1344,11 +1350,6 @@ rzg2l_cpg_register_mod_clk(const struct rzg2l_mod_clk *mod, WARN_DEBUG(mod->parent >= priv->num_core_clks + priv->num_mod_clks); WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT); - if (!mod->name) { - /* Skip NULLified clock */ - return; - } - parent = priv->clks[mod->parent]; if (IS_ERR(parent)) { clk = parent; @@ -1538,28 +1539,6 @@ static int rzg2l_cpg_reset_controller_register(struct rzg2l_cpg_priv *priv) return devm_reset_controller_register(priv->dev, &priv->rcdev); } -static bool rzg2l_cpg_is_pm_clk(struct rzg2l_cpg_priv *priv, - const struct of_phandle_args *clkspec) -{ - const struct rzg2l_cpg_info *info = priv->info; - unsigned int id; - unsigned int i; - - if (clkspec->args_count != 2) - return false; - - if (clkspec->args[0] != CPG_MOD) - return false; - - id = clkspec->args[1] + info->num_total_core_clks; - for (i = 0; i < info->num_no_pm_mod_clks; i++) { - if (info->no_pm_mod_clks[i] == id) - return false; - } - - return true; -} - /** * struct rzg2l_cpg_pm_domains - RZ/G2L PM domains data structure * @onecell_data: cell data @@ -1584,45 +1563,73 @@ struct rzg2l_cpg_pd { u16 id; }; +static bool rzg2l_cpg_is_pm_clk(struct rzg2l_cpg_pd *pd, + const struct of_phandle_args *clkspec) +{ + if (clkspec->np != pd->genpd.dev.of_node || clkspec->args_count != 2) + return false; + + switch (clkspec->args[0]) { + case CPG_MOD: { + struct rzg2l_cpg_priv *priv = pd->priv; + const struct rzg2l_cpg_info *info = priv->info; + unsigned int id = clkspec->args[1]; + + if (id >= priv->num_mod_clks) + return false; + + id += info->num_total_core_clks; + + for (unsigned int i = 0; i < info->num_no_pm_mod_clks; i++) { + if (info->no_pm_mod_clks[i] == id) + return false; + } + + return true; + } + + case CPG_CORE: + default: + return false; + } +} + static int rzg2l_cpg_attach_dev(struct generic_pm_domain *domain, struct device *dev) { struct rzg2l_cpg_pd *pd = container_of(domain, struct rzg2l_cpg_pd, genpd); - struct rzg2l_cpg_priv *priv = pd->priv; struct device_node *np = dev->of_node; struct of_phandle_args clkspec; bool once = true; struct clk *clk; + unsigned int i; int error; - int i = 0; - - while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i, - &clkspec)) { - if (rzg2l_cpg_is_pm_clk(priv, &clkspec)) { - if (once) { - once = false; - error = pm_clk_create(dev); - if (error) { - of_node_put(clkspec.np); - goto err; - } - } - clk = of_clk_get_from_provider(&clkspec); + + for (i = 0; !of_parse_phandle_with_args(np, "clocks", "#clock-cells", i, &clkspec); i++) { + if (!rzg2l_cpg_is_pm_clk(pd, &clkspec)) { of_node_put(clkspec.np); - if (IS_ERR(clk)) { - error = PTR_ERR(clk); - goto fail_destroy; - } + continue; + } - error = pm_clk_add_clk(dev, clk); + if (once) { + once = false; + error = pm_clk_create(dev); if (error) { - dev_err(dev, "pm_clk_add_clk failed %d\n", - error); - goto fail_put; + of_node_put(clkspec.np); + goto err; } - } else { - of_node_put(clkspec.np); } - i++; + clk = of_clk_get_from_provider(&clkspec); + of_node_put(clkspec.np); + if (IS_ERR(clk)) { + error = PTR_ERR(clk); + goto fail_destroy; + } + + error = pm_clk_add_clk(dev, clk); + if (error) { + dev_err(dev, "pm_clk_add_clk failed %d\n", error); + goto fail_put; + } } return 0; diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h index 881a89b5a710..b6eece5ffa20 100644 --- a/drivers/clk/renesas/rzg2l-cpg.h +++ b/drivers/clk/renesas/rzg2l-cpg.h @@ -21,6 +21,7 @@ #define CPG_PL2_DDIV (0x204) #define CPG_PL3A_DDIV (0x208) #define CPG_PL6_DDIV (0x210) +#define CPG_PL3C_SDIV (0x214) #define CPG_CLKSTATUS (0x280) #define CPG_PL3_SSEL (0x408) #define CPG_PL6_SSEL (0x414) @@ -70,6 +71,7 @@ #define DIVPL3A DDIV_PACK(CPG_PL3A_DDIV, 0, 3) #define DIVPL3B DDIV_PACK(CPG_PL3A_DDIV, 4, 3) #define DIVPL3C DDIV_PACK(CPG_PL3A_DDIV, 8, 3) +#define DIVPL3E DDIV_PACK(CPG_PL3C_SDIV, 8, 5) #define DIVGPU DDIV_PACK(CPG_PL6_DDIV, 0, 2) #define SEL_PLL_PACK(offset, bitpos, size) \ @@ -102,7 +104,10 @@ struct cpg_core_clk { const struct clk_div_table *dtable; const u32 *mtable; const unsigned long invalid_rate; - const unsigned long max_rate; + union { + const unsigned long max_rate; + const unsigned long default_rate; + }; const char * const *parent_names; notifier_fn_t notifier; u32 flag; @@ -144,8 +149,9 @@ enum clk_types { DEF_TYPE(_name, _id, _type, .parent = _parent) #define DEF_SAMPLL(_name, _id, _parent, _conf) \ DEF_TYPE(_name, _id, CLK_TYPE_SAM_PLL, .parent = _parent, .conf = _conf) -#define DEF_G3S_PLL(_name, _id, _parent, _conf) \ - DEF_TYPE(_name, _id, CLK_TYPE_G3S_PLL, .parent = _parent, .conf = _conf) +#define DEF_G3S_PLL(_name, _id, _parent, _conf, _default_rate) \ + DEF_TYPE(_name, _id, CLK_TYPE_G3S_PLL, .parent = _parent, .conf = _conf, \ + .default_rate = _default_rate) #define DEF_INPUT(_name, _id) \ DEF_TYPE(_name, _id, CLK_TYPE_IN) #define DEF_FIXED(_name, _id, _parent, _mult, _div) \ diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cpg.c index a4c1e92e1fd7..2b9771ab2b3f 100644 --- a/drivers/clk/renesas/rzv2h-cpg.c +++ b/drivers/clk/renesas/rzv2h-cpg.c @@ -447,8 +447,7 @@ static void rzv2h_mod_clock_mstop_enable(struct rzv2h_cpg_priv *priv, { unsigned long mstop_mask = FIELD_GET(BUS_MSTOP_BITS_MASK, mstop_data); u16 mstop_index = FIELD_GET(BUS_MSTOP_IDX_MASK, mstop_data); - unsigned int index = (mstop_index - 1) * 16; - atomic_t *mstop = &priv->mstop_count[index]; + atomic_t *mstop = &priv->mstop_count[mstop_index * 16]; unsigned long flags; unsigned int i; u32 val = 0; @@ -469,8 +468,7 @@ static void rzv2h_mod_clock_mstop_disable(struct rzv2h_cpg_priv *priv, { unsigned long mstop_mask = FIELD_GET(BUS_MSTOP_BITS_MASK, mstop_data); u16 mstop_index = FIELD_GET(BUS_MSTOP_IDX_MASK, mstop_data); - unsigned int index = (mstop_index - 1) * 16; - atomic_t *mstop = &priv->mstop_count[index]; + atomic_t *mstop = &priv->mstop_count[mstop_index * 16]; unsigned long flags; unsigned int i; u32 val = 0; @@ -541,8 +539,8 @@ static int rzv2h_mod_clock_endisable(struct clk_hw *hw, bool enable) error = readl_poll_timeout_atomic(priv->base + reg, value, value & bitmask, 0, 10); if (error) - dev_err(dev, "Failed to enable CLK_ON %p\n", - priv->base + reg); + dev_err(dev, "Failed to enable CLK_ON 0x%x/%pC\n", + GET_CLK_ON_OFFSET(clock->on_index), hw->clk); return error; } @@ -630,8 +628,7 @@ rzv2h_cpg_register_mod_clk(const struct rzv2h_mod_clk *mod, } else if (clock->mstop_data != BUS_MSTOP_NONE && mod->critical) { unsigned long mstop_mask = FIELD_GET(BUS_MSTOP_BITS_MASK, clock->mstop_data); u16 mstop_index = FIELD_GET(BUS_MSTOP_IDX_MASK, clock->mstop_data); - unsigned int index = (mstop_index - 1) * 16; - atomic_t *mstop = &priv->mstop_count[index]; + atomic_t *mstop = &priv->mstop_count[mstop_index * 16]; unsigned long flags; unsigned int i; u32 val = 0; @@ -926,6 +923,9 @@ static int __init rzv2h_cpg_probe(struct platform_device *pdev) if (!priv->mstop_count) return -ENOMEM; + /* Adjust for CPG_BUS_m_MSTOP starting from m = 1 */ + priv->mstop_count -= 16; + priv->resets = devm_kmemdup(dev, info->resets, sizeof(*info->resets) * info->num_resets, GFP_KERNEL); if (!priv->resets) diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cpg.h index fd8eb985c75b..576a070763cb 100644 --- a/drivers/clk/renesas/rzv2h-cpg.h +++ b/drivers/clk/renesas/rzv2h-cpg.h @@ -38,11 +38,13 @@ struct ddiv { #define CPG_CDDIV3 (0x40C) #define CPG_CDDIV4 (0x410) +#define CDDIV0_DIVCTL1 DDIV_PACK(CPG_CDDIV0, 4, 3, 1) #define CDDIV0_DIVCTL2 DDIV_PACK(CPG_CDDIV0, 8, 3, 2) #define CDDIV1_DIVCTL0 DDIV_PACK(CPG_CDDIV1, 0, 2, 4) #define CDDIV1_DIVCTL1 DDIV_PACK(CPG_CDDIV1, 4, 2, 5) #define CDDIV1_DIVCTL2 DDIV_PACK(CPG_CDDIV1, 8, 2, 6) #define CDDIV1_DIVCTL3 DDIV_PACK(CPG_CDDIV1, 12, 2, 7) +#define CDDIV3_DIVCTL2 DDIV_PACK(CPG_CDDIV3, 8, 3, 14) #define CDDIV3_DIVCTL3 DDIV_PACK(CPG_CDDIV3, 12, 1, 15) #define CDDIV4_DIVCTL0 DDIV_PACK(CPG_CDDIV4, 0, 1, 16) #define CDDIV4_DIVCTL1 DDIV_PACK(CPG_CDDIV4, 4, 1, 17) diff --git a/drivers/clk/rockchip/Kconfig b/drivers/clk/rockchip/Kconfig index 570ad90835d3..febb7944f34b 100644 --- a/drivers/clk/rockchip/Kconfig +++ b/drivers/clk/rockchip/Kconfig @@ -93,6 +93,20 @@ config CLK_RK3399 help Build the driver for RK3399 Clock Driver. +config CLK_RK3528 + bool "Rockchip RK3528 clock controller support" + depends on ARM64 || COMPILE_TEST + default y + help + Build the driver for RK3528 Clock Controller. + +config CLK_RK3562 + bool "Rockchip RK3562 clock controller support" + depends on ARM64 || COMPILE_TEST + default y + help + Build the driver for RK3562 Clock Controller. + config CLK_RK3568 bool "Rockchip RK3568 clock controller support" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile index 3fe7616f0ebe..e8ece20aebfd 100644 --- a/drivers/clk/rockchip/Makefile +++ b/drivers/clk/rockchip/Makefile @@ -28,6 +28,8 @@ obj-$(CONFIG_CLK_RK3308) += clk-rk3308.o obj-$(CONFIG_CLK_RK3328) += clk-rk3328.o obj-$(CONFIG_CLK_RK3368) += clk-rk3368.o obj-$(CONFIG_CLK_RK3399) += clk-rk3399.o +obj-$(CONFIG_CLK_RK3528) += clk-rk3528.o rst-rk3528.o +obj-$(CONFIG_CLK_RK3562) += clk-rk3562.o rst-rk3562.o obj-$(CONFIG_CLK_RK3568) += clk-rk3568.o obj-$(CONFIG_CLK_RK3576) += clk-rk3576.o rst-rk3576.o obj-$(CONFIG_CLK_RK3588) += clk-rk3588.o rst-rk3588.o diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c index fe76756e592e..2c2abb3b4210 100644 --- a/drivers/clk/rockchip/clk-pll.c +++ b/drivers/clk/rockchip/clk-pll.c @@ -204,10 +204,12 @@ static int rockchip_rk3036_pll_set_params(struct rockchip_clk_pll *pll, rockchip_rk3036_pll_get_params(pll, &cur); cur.rate = 0; - cur_parent = pll_mux_ops->get_parent(&pll_mux->hw); - if (cur_parent == PLL_MODE_NORM) { - pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); - rate_change_remuxed = 1; + if (!(pll->flags & ROCKCHIP_PLL_FIXED_MODE)) { + cur_parent = pll_mux_ops->get_parent(&pll_mux->hw); + if (cur_parent == PLL_MODE_NORM) { + pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); + rate_change_remuxed = 1; + } } /* update pll values */ diff --git a/drivers/clk/rockchip/clk-rk3188.c b/drivers/clk/rockchip/clk-rk3188.c index 30e670c8afba..318c8ddc8a76 100644 --- a/drivers/clk/rockchip/clk-rk3188.c +++ b/drivers/clk/rockchip/clk-rk3188.c @@ -337,7 +337,7 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = { GATE(0, "pclkin_cif0", "ext_cif0", 0, RK2928_CLKGATE_CON(3), 3, GFLAGS), - INVERTER(0, "pclk_cif0", "pclkin_cif0", + INVERTER(PCLK_CIF0, "pclk_cif0", "pclkin_cif0", RK2928_CLKSEL_CON(30), 8, IFLAGS), FACTOR(0, "xin12m", "xin24m", 0, 1, 2), @@ -595,7 +595,7 @@ static struct rockchip_clk_branch rk3066a_clk_branches[] __initdata = { GATE(0, "pclkin_cif1", "ext_cif1", 0, RK2928_CLKGATE_CON(3), 4, GFLAGS), - INVERTER(0, "pclk_cif1", "pclkin_cif1", + INVERTER(PCLK_CIF1, "pclk_cif1", "pclkin_cif1", RK2928_CLKSEL_CON(30), 12, IFLAGS), COMPOSITE(0, "aclk_gpu_src", mux_pll_src_cpll_gpll_p, 0, diff --git a/drivers/clk/rockchip/clk-rk3328.c b/drivers/clk/rockchip/clk-rk3328.c index 3bb87b27b662..cf60fcf2fa5c 100644 --- a/drivers/clk/rockchip/clk-rk3328.c +++ b/drivers/clk/rockchip/clk-rk3328.c @@ -201,7 +201,7 @@ PNAME(mux_aclk_peri_pre_p) = { "cpll_peri", "gpll_peri", "hdmiphy_peri" }; PNAME(mux_ref_usb3otg_src_p) = { "xin24m", - "clk_usb3otg_ref" }; + "clk_ref_usb3otg_src" }; PNAME(mux_xin24m_32k_p) = { "xin24m", "clk_rtc32k" }; PNAME(mux_mac2io_src_p) = { "clk_mac2io_src", diff --git a/drivers/clk/rockchip/clk-rk3528.c b/drivers/clk/rockchip/clk-rk3528.c new file mode 100644 index 000000000000..b8b577b902a0 --- /dev/null +++ b/drivers/clk/rockchip/clk-rk3528.c @@ -0,0 +1,1116 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 Rockchip Electronics Co. Ltd. + * Copyright (c) 2024 Yao Zi <ziyao@disroot.org> + * Author: Joseph Chen <chenjh@rock-chips.com> + */ + +#include <linux/clk-provider.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> + +#include <dt-bindings/clock/rockchip,rk3528-cru.h> + +#include "clk.h" + +#define RK3528_GRF_SOC_STATUS0 0x1a0 + +enum rk3528_plls { + apll, cpll, gpll, ppll, dpll, +}; + +static struct rockchip_pll_rate_table rk3528_pll_rates[] = { + RK3036_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0), + RK3036_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0), + RK3036_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0), + RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0), + RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0), + RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0), + RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0), + RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0), + RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0), /* GPLL */ + RK3036_PLL_RATE(1092000000, 2, 91, 1, 1, 1, 0), + RK3036_PLL_RATE(1008000000, 1, 42, 1, 1, 1, 0), + RK3036_PLL_RATE(1000000000, 1, 125, 3, 1, 1, 0), /* PPLL */ + RK3036_PLL_RATE(996000000, 2, 83, 1, 1, 1, 0), /* CPLL */ + RK3036_PLL_RATE(960000000, 1, 40, 1, 1, 1, 0), + RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0), + RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0), + RK3036_PLL_RATE(600000000, 1, 50, 2, 1, 1, 0), + RK3036_PLL_RATE(594000000, 2, 99, 2, 1, 1, 0), + RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0), + RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0), + RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0), + RK3036_PLL_RATE(96000000, 1, 24, 3, 2, 1, 0), + { /* sentinel */ }, +}; + +#define RK3528_DIV_ACLK_M_CORE_MASK 0x1f +#define RK3528_DIV_ACLK_M_CORE_SHIFT 11 +#define RK3528_DIV_PCLK_DBG_MASK 0x1f +#define RK3528_DIV_PCLK_DBG_SHIFT 1 + +#define RK3528_CLKSEL39(_aclk_m_core) \ +{ \ + .reg = RK3528_CLKSEL_CON(39), \ + .val = HIWORD_UPDATE(_aclk_m_core, RK3528_DIV_ACLK_M_CORE_MASK, \ + RK3528_DIV_ACLK_M_CORE_SHIFT), \ +} + +#define RK3528_CLKSEL40(_pclk_dbg) \ +{ \ + .reg = RK3528_CLKSEL_CON(40), \ + .val = HIWORD_UPDATE(_pclk_dbg, RK3528_DIV_PCLK_DBG_MASK, \ + RK3528_DIV_PCLK_DBG_SHIFT), \ +} + +#define RK3528_CPUCLK_RATE(_prate, _aclk_m_core, _pclk_dbg) \ +{ \ + .prate = _prate, \ + .divs = { \ + RK3528_CLKSEL39(_aclk_m_core), \ + RK3528_CLKSEL40(_pclk_dbg), \ + }, \ +} + +static struct rockchip_cpuclk_rate_table rk3528_cpuclk_rates[] __initdata = { + RK3528_CPUCLK_RATE(1896000000, 1, 13), + RK3528_CPUCLK_RATE(1800000000, 1, 12), + RK3528_CPUCLK_RATE(1704000000, 1, 11), + RK3528_CPUCLK_RATE(1608000000, 1, 11), + RK3528_CPUCLK_RATE(1512000000, 1, 11), + RK3528_CPUCLK_RATE(1416000000, 1, 9), + RK3528_CPUCLK_RATE(1296000000, 1, 8), + RK3528_CPUCLK_RATE(1200000000, 1, 8), + RK3528_CPUCLK_RATE(1188000000, 1, 8), + RK3528_CPUCLK_RATE(1092000000, 1, 7), + RK3528_CPUCLK_RATE(1008000000, 1, 6), + RK3528_CPUCLK_RATE(1000000000, 1, 6), + RK3528_CPUCLK_RATE(996000000, 1, 6), + RK3528_CPUCLK_RATE(960000000, 1, 6), + RK3528_CPUCLK_RATE(912000000, 1, 6), + RK3528_CPUCLK_RATE(816000000, 1, 5), + RK3528_CPUCLK_RATE(600000000, 1, 3), + RK3528_CPUCLK_RATE(594000000, 1, 3), + RK3528_CPUCLK_RATE(408000000, 1, 2), + RK3528_CPUCLK_RATE(312000000, 1, 2), + RK3528_CPUCLK_RATE(216000000, 1, 1), + RK3528_CPUCLK_RATE(96000000, 1, 0), +}; + +static const struct rockchip_cpuclk_reg_data rk3528_cpuclk_data = { + .core_reg[0] = RK3528_CLKSEL_CON(39), + .div_core_shift[0] = 5, + .div_core_mask[0] = 0x1f, + .num_cores = 1, + .mux_core_alt = 1, + .mux_core_main = 0, + .mux_core_shift = 10, + .mux_core_mask = 0x1, +}; + +PNAME(mux_pll_p) = { "xin24m" }; +PNAME(mux_armclk) = { "apll", "gpll" }; +PNAME(mux_24m_32k_p) = { "xin24m", "clk_32k" }; +PNAME(mux_gpll_cpll_p) = { "gpll", "cpll" }; +PNAME(mux_gpll_cpll_xin24m_p) = { "gpll", "cpll", "xin24m" }; +PNAME(mux_100m_50m_24m_p) = { "clk_100m_src", "clk_50m_src", + "xin24m" }; +PNAME(mux_150m_100m_24m_p) = { "clk_150m_src", "clk_100m_src", + "xin24m" }; +PNAME(mux_200m_100m_24m_p) = { "clk_200m_src", "clk_100m_src", + "xin24m" }; +PNAME(mux_200m_100m_50m_24m_p) = { "clk_200m_src", "clk_100m_src", + "clk_50m_src", "xin24m" }; +PNAME(mux_300m_200m_100m_24m_p) = { "clk_300m_src", "clk_200m_src", + "clk_100m_src", "xin24m" }; +PNAME(mux_339m_200m_100m_24m_p) = { "clk_339m_src", "clk_200m_src", + "clk_100m_src", "xin24m" }; +PNAME(mux_500m_200m_100m_24m_p) = { "clk_500m_src", "clk_200m_src", + "clk_100m_src", "xin24m" }; +PNAME(mux_500m_300m_100m_24m_p) = { "clk_500m_src", "clk_300m_src", + "clk_100m_src", "xin24m" }; +PNAME(mux_600m_300m_200m_24m_p) = { "clk_600m_src", "clk_300m_src", + "clk_200m_src", "xin24m" }; +PNAME(aclk_gpu_p) = { "aclk_gpu_root", + "clk_gpu_pvtpll_src" }; +PNAME(aclk_rkvdec_pvtmux_root_p) = { "aclk_rkvdec_root", + "clk_rkvdec_pvtpll_src" }; +PNAME(clk_i2c2_p) = { "clk_200m_src", "clk_100m_src", + "xin24m", "clk_32k" }; +PNAME(clk_ref_pcie_inner_phy_p) = { "clk_ppll_100m_src", "xin24m" }; +PNAME(dclk_vop0_p) = { "dclk_vop_src0", + "clk_hdmiphy_pixel_io" }; +PNAME(mclk_i2s0_2ch_sai_src_p) = { "clk_i2s0_2ch_src", + "clk_i2s0_2ch_frac", "xin12m" }; +PNAME(mclk_i2s1_8ch_sai_src_p) = { "clk_i2s1_8ch_src", + "clk_i2s1_8ch_frac", "xin12m" }; +PNAME(mclk_i2s2_2ch_sai_src_p) = { "clk_i2s2_2ch_src", + "clk_i2s2_2ch_frac", "xin12m" }; +PNAME(mclk_i2s3_8ch_sai_src_p) = { "clk_i2s3_8ch_src", + "clk_i2s3_8ch_frac", "xin12m" }; +PNAME(mclk_sai_i2s0_p) = { "mclk_i2s0_2ch_sai_src", + "i2s0_mclkin" }; +PNAME(mclk_sai_i2s1_p) = { "mclk_i2s1_8ch_sai_src", + "i2s1_mclkin" }; +PNAME(mclk_spdif_src_p) = { "clk_spdif_src", "clk_spdif_frac", + "xin12m" }; +PNAME(sclk_uart0_src_p) = { "clk_uart0_src", "clk_uart0_frac", + "xin24m" }; +PNAME(sclk_uart1_src_p) = { "clk_uart1_src", "clk_uart1_frac", + "xin24m" }; +PNAME(sclk_uart2_src_p) = { "clk_uart2_src", "clk_uart2_frac", + "xin24m" }; +PNAME(sclk_uart3_src_p) = { "clk_uart3_src", "clk_uart3_frac", + "xin24m" }; +PNAME(sclk_uart4_src_p) = { "clk_uart4_src", "clk_uart4_frac", + "xin24m" }; +PNAME(sclk_uart5_src_p) = { "clk_uart5_src", "clk_uart5_frac", + "xin24m" }; +PNAME(sclk_uart6_src_p) = { "clk_uart6_src", "clk_uart6_frac", + "xin24m" }; +PNAME(sclk_uart7_src_p) = { "clk_uart7_src", "clk_uart7_frac", + "xin24m" }; +PNAME(clk_32k_p) = { "xin_osc0_div", "clk_pvtm_32k" }; + +static struct rockchip_pll_clock rk3528_pll_clks[] __initdata = { + [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p, + CLK_IS_CRITICAL, RK3528_PLL_CON(0), + RK3528_MODE_CON, 0, 0, 0, rk3528_pll_rates), + + [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p, + CLK_IS_CRITICAL, RK3528_PLL_CON(8), + RK3528_MODE_CON, 2, 0, 0, rk3528_pll_rates), + + [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p, + CLK_IS_CRITICAL, RK3528_PLL_CON(24), + RK3528_MODE_CON, 4, 0, 0, rk3528_pll_rates), + + [ppll] = PLL(pll_rk3328, PLL_PPLL, "ppll", mux_pll_p, + CLK_IS_CRITICAL, RK3528_PCIE_PLL_CON(32), + RK3528_MODE_CON, 6, 0, ROCKCHIP_PLL_FIXED_MODE, rk3528_pll_rates), + + [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p, + CLK_IGNORE_UNUSED, RK3528_DDRPHY_PLL_CON(16), + RK3528_DDRPHY_MODE_CON, 0, 0, 0, rk3528_pll_rates), +}; + +#define MFLAGS CLK_MUX_HIWORD_MASK +#define DFLAGS CLK_DIVIDER_HIWORD_MASK +#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) + +static struct rockchip_clk_branch rk3528_uart0_fracmux __initdata = + MUX(CLK_UART0, "clk_uart0", sclk_uart0_src_p, CLK_SET_RATE_PARENT, + RK3528_CLKSEL_CON(6), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3528_uart1_fracmux __initdata = + MUX(CLK_UART1, "clk_uart1", sclk_uart1_src_p, CLK_SET_RATE_PARENT, + RK3528_CLKSEL_CON(8), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3528_uart2_fracmux __initdata = + MUX(CLK_UART2, "clk_uart2", sclk_uart2_src_p, CLK_SET_RATE_PARENT, + RK3528_CLKSEL_CON(10), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3528_uart3_fracmux __initdata = + MUX(CLK_UART3, "clk_uart3", sclk_uart3_src_p, CLK_SET_RATE_PARENT, + RK3528_CLKSEL_CON(12), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3528_uart4_fracmux __initdata = + MUX(CLK_UART4, "clk_uart4", sclk_uart4_src_p, CLK_SET_RATE_PARENT, + RK3528_CLKSEL_CON(14), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3528_uart5_fracmux __initdata = + MUX(CLK_UART5, "clk_uart5", sclk_uart5_src_p, CLK_SET_RATE_PARENT, + RK3528_CLKSEL_CON(16), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3528_uart6_fracmux __initdata = + MUX(CLK_UART6, "clk_uart6", sclk_uart6_src_p, CLK_SET_RATE_PARENT, + RK3528_CLKSEL_CON(18), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3528_uart7_fracmux __initdata = + MUX(CLK_UART7, "clk_uart7", sclk_uart7_src_p, CLK_SET_RATE_PARENT, + RK3528_CLKSEL_CON(20), 0, 2, MFLAGS); + +static struct rockchip_clk_branch mclk_i2s0_2ch_sai_src_fracmux __initdata = + MUX(MCLK_I2S0_2CH_SAI_SRC_PRE, "mclk_i2s0_2ch_sai_src_pre", mclk_i2s0_2ch_sai_src_p, CLK_SET_RATE_PARENT, + RK3528_CLKSEL_CON(22), 0, 2, MFLAGS); + +static struct rockchip_clk_branch mclk_i2s1_8ch_sai_src_fracmux __initdata = + MUX(MCLK_I2S1_8CH_SAI_SRC_PRE, "mclk_i2s1_8ch_sai_src_pre", mclk_i2s1_8ch_sai_src_p, CLK_SET_RATE_PARENT, + RK3528_CLKSEL_CON(26), 0, 2, MFLAGS); + +static struct rockchip_clk_branch mclk_i2s2_2ch_sai_src_fracmux __initdata = + MUX(MCLK_I2S2_2CH_SAI_SRC_PRE, "mclk_i2s2_2ch_sai_src_pre", mclk_i2s2_2ch_sai_src_p, CLK_SET_RATE_PARENT, + RK3528_CLKSEL_CON(28), 0, 2, MFLAGS); + +static struct rockchip_clk_branch mclk_i2s3_8ch_sai_src_fracmux __initdata = + MUX(MCLK_I2S3_8CH_SAI_SRC_PRE, "mclk_i2s3_8ch_sai_src_pre", mclk_i2s3_8ch_sai_src_p, CLK_SET_RATE_PARENT, + RK3528_CLKSEL_CON(24), 0, 2, MFLAGS); + +static struct rockchip_clk_branch mclk_spdif_src_fracmux __initdata = + MUX(MCLK_SDPDIF_SRC_PRE, "mclk_spdif_src_pre", mclk_spdif_src_p, CLK_SET_RATE_PARENT, + RK3528_CLKSEL_CON(32), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3528_clk_branches[] __initdata = { + /* top */ + FACTOR(0, "xin12m", "xin24m", 0, 1, 2), + + COMPOSITE(CLK_MATRIX_250M_SRC, "clk_250m_src", mux_gpll_cpll_p, CLK_IS_CRITICAL, + RK3528_CLKSEL_CON(1), 15, 1, MFLAGS, 10, 5, DFLAGS, + RK3528_CLKGATE_CON(0), 5, GFLAGS), + COMPOSITE(CLK_MATRIX_500M_SRC, "clk_500m_src", mux_gpll_cpll_p, CLK_IS_CRITICAL, + RK3528_CLKSEL_CON(3), 11, 1, MFLAGS, 6, 5, DFLAGS, + RK3528_CLKGATE_CON(0), 10, GFLAGS), + COMPOSITE_NOMUX(CLK_MATRIX_50M_SRC, "clk_50m_src", "cpll", CLK_IS_CRITICAL, + RK3528_CLKSEL_CON(0), 2, 5, DFLAGS, + RK3528_CLKGATE_CON(0), 1, GFLAGS), + COMPOSITE_NOMUX(CLK_MATRIX_100M_SRC, "clk_100m_src", "cpll", CLK_IS_CRITICAL, + RK3528_CLKSEL_CON(0), 7, 5, DFLAGS, + RK3528_CLKGATE_CON(0), 2, GFLAGS), + COMPOSITE_NOMUX(CLK_MATRIX_150M_SRC, "clk_150m_src", "gpll", CLK_IS_CRITICAL, + RK3528_CLKSEL_CON(1), 0, 5, DFLAGS, + RK3528_CLKGATE_CON(0), 3, GFLAGS), + COMPOSITE_NOMUX(CLK_MATRIX_200M_SRC, "clk_200m_src", "gpll", CLK_IS_CRITICAL, + RK3528_CLKSEL_CON(1), 5, 5, DFLAGS, + RK3528_CLKGATE_CON(0), 4, GFLAGS), + COMPOSITE_NOMUX(CLK_MATRIX_300M_SRC, "clk_300m_src", "gpll", CLK_IS_CRITICAL, + RK3528_CLKSEL_CON(2), 0, 5, DFLAGS, + RK3528_CLKGATE_CON(0), 6, GFLAGS), + COMPOSITE_NOMUX_HALFDIV(CLK_MATRIX_339M_SRC, "clk_339m_src", "gpll", CLK_IS_CRITICAL, + RK3528_CLKSEL_CON(2), 5, 5, DFLAGS, + RK3528_CLKGATE_CON(0), 7, GFLAGS), + COMPOSITE_NOMUX(CLK_MATRIX_400M_SRC, "clk_400m_src", "gpll", CLK_IS_CRITICAL, + RK3528_CLKSEL_CON(2), 10, 5, DFLAGS, + RK3528_CLKGATE_CON(0), 8, GFLAGS), + COMPOSITE_NOMUX(CLK_MATRIX_600M_SRC, "clk_600m_src", "gpll", CLK_IS_CRITICAL, + RK3528_CLKSEL_CON(4), 0, 5, DFLAGS, + RK3528_CLKGATE_CON(0), 11, GFLAGS), + COMPOSITE(DCLK_VOP_SRC0, "dclk_vop_src0", mux_gpll_cpll_p, 0, + RK3528_CLKSEL_CON(32), 10, 1, MFLAGS, 2, 8, DFLAGS, + RK3528_CLKGATE_CON(3), 7, GFLAGS), + COMPOSITE(DCLK_VOP_SRC1, "dclk_vop_src1", mux_gpll_cpll_p, 0, + RK3528_CLKSEL_CON(33), 8, 1, MFLAGS, 0, 8, DFLAGS, + RK3528_CLKGATE_CON(3), 8, GFLAGS), + COMPOSITE_NOMUX(CLK_HSM, "clk_hsm", "xin24m", 0, + RK3528_CLKSEL_CON(36), 5, 5, DFLAGS, + RK3528_CLKGATE_CON(3), 13, GFLAGS), + + COMPOSITE_NOMUX(CLK_UART0_SRC, "clk_uart0_src", "gpll", 0, + RK3528_CLKSEL_CON(4), 5, 5, DFLAGS, + RK3528_CLKGATE_CON(0), 12, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART0_FRAC, "clk_uart0_frac", "clk_uart0_src", CLK_SET_RATE_PARENT, + RK3528_CLKSEL_CON(5), 0, + RK3528_CLKGATE_CON(0), 13, GFLAGS, + &rk3528_uart0_fracmux), + GATE(SCLK_UART0, "sclk_uart0", "clk_uart0", 0, + RK3528_CLKGATE_CON(0), 14, GFLAGS), + + COMPOSITE_NOMUX(CLK_UART1_SRC, "clk_uart1_src", "gpll", 0, + RK3528_CLKSEL_CON(6), 2, 5, DFLAGS, + RK3528_CLKGATE_CON(0), 15, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART1_FRAC, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT, + RK3528_CLKSEL_CON(7), 0, + RK3528_CLKGATE_CON(1), 0, GFLAGS, + &rk3528_uart1_fracmux), + GATE(SCLK_UART1, "sclk_uart1", "clk_uart1", 0, + RK3528_CLKGATE_CON(1), 1, GFLAGS), + + COMPOSITE_NOMUX(CLK_UART2_SRC, "clk_uart2_src", "gpll", 0, + RK3528_CLKSEL_CON(8), 2, 5, DFLAGS, + RK3528_CLKGATE_CON(1), 2, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART2_FRAC, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT, + RK3528_CLKSEL_CON(9), 0, + RK3528_CLKGATE_CON(1), 3, GFLAGS, + &rk3528_uart2_fracmux), + GATE(SCLK_UART2, "sclk_uart2", "clk_uart2", 0, + RK3528_CLKGATE_CON(1), 4, GFLAGS), + + COMPOSITE_NOMUX(CLK_UART3_SRC, "clk_uart3_src", "gpll", 0, + RK3528_CLKSEL_CON(10), 2, 5, DFLAGS, + RK3528_CLKGATE_CON(1), 5, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART3_FRAC, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT, + RK3528_CLKSEL_CON(11), 0, + RK3528_CLKGATE_CON(1), 6, GFLAGS, + &rk3528_uart3_fracmux), + GATE(SCLK_UART3, "sclk_uart3", "clk_uart3", 0, + RK3528_CLKGATE_CON(1), 7, GFLAGS), + + COMPOSITE_NOMUX(CLK_UART4_SRC, "clk_uart4_src", "gpll", 0, + RK3528_CLKSEL_CON(12), 2, 5, DFLAGS, + RK3528_CLKGATE_CON(1), 8, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART4_FRAC, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT, + RK3528_CLKSEL_CON(13), 0, + RK3528_CLKGATE_CON(1), 9, GFLAGS, + &rk3528_uart4_fracmux), + GATE(SCLK_UART4, "sclk_uart4", "clk_uart4", 0, + RK3528_CLKGATE_CON(1), 10, GFLAGS), + + COMPOSITE_NOMUX(CLK_UART5_SRC, "clk_uart5_src", "gpll", 0, + RK3528_CLKSEL_CON(14), 2, 5, DFLAGS, + RK3528_CLKGATE_CON(1), 11, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART5_FRAC, "clk_uart5_frac", "clk_uart5_src", CLK_SET_RATE_PARENT, + RK3528_CLKSEL_CON(15), 0, + RK3528_CLKGATE_CON(1), 12, GFLAGS, + &rk3528_uart5_fracmux), + GATE(SCLK_UART5, "sclk_uart5", "clk_uart5", 0, + RK3528_CLKGATE_CON(1), 13, GFLAGS), + + COMPOSITE_NOMUX(CLK_UART6_SRC, "clk_uart6_src", "gpll", 0, + RK3528_CLKSEL_CON(16), 2, 5, DFLAGS, + RK3528_CLKGATE_CON(1), 14, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART6_FRAC, "clk_uart6_frac", "clk_uart6_src", CLK_SET_RATE_PARENT, + RK3528_CLKSEL_CON(17), 0, + RK3528_CLKGATE_CON(1), 15, GFLAGS, + &rk3528_uart6_fracmux), + GATE(SCLK_UART6, "sclk_uart6", "clk_uart6", 0, + RK3528_CLKGATE_CON(2), 0, GFLAGS), + + COMPOSITE_NOMUX(CLK_UART7_SRC, "clk_uart7_src", "gpll", 0, + RK3528_CLKSEL_CON(18), 2, 5, DFLAGS, + RK3528_CLKGATE_CON(2), 1, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART7_FRAC, "clk_uart7_frac", "clk_uart7_src", CLK_SET_RATE_PARENT, + RK3528_CLKSEL_CON(19), 0, + RK3528_CLKGATE_CON(2), 2, GFLAGS, + &rk3528_uart7_fracmux), + GATE(SCLK_UART7, "sclk_uart7", "clk_uart7", 0, + RK3528_CLKGATE_CON(2), 3, GFLAGS), + + COMPOSITE_NOMUX(CLK_I2S0_2CH_SRC, "clk_i2s0_2ch_src", "gpll", 0, + RK3528_CLKSEL_CON(20), 8, 5, DFLAGS, + RK3528_CLKGATE_CON(2), 5, GFLAGS), + COMPOSITE_FRACMUX(CLK_I2S0_2CH_FRAC, "clk_i2s0_2ch_frac", "clk_i2s0_2ch_src", CLK_SET_RATE_PARENT, + RK3528_CLKSEL_CON(21), 0, + RK3528_CLKGATE_CON(2), 6, GFLAGS, + &mclk_i2s0_2ch_sai_src_fracmux), + GATE(MCLK_I2S0_2CH_SAI_SRC, "mclk_i2s0_2ch_sai_src", "mclk_i2s0_2ch_sai_src_pre", 0, + RK3528_CLKGATE_CON(2), 7, GFLAGS), + + COMPOSITE_NOMUX(CLK_I2S1_8CH_SRC, "clk_i2s1_8ch_src", "gpll", 0, + RK3528_CLKSEL_CON(24), 3, 5, DFLAGS, + RK3528_CLKGATE_CON(2), 11, GFLAGS), + COMPOSITE_FRACMUX(CLK_I2S1_8CH_FRAC, "clk_i2s1_8ch_frac", "clk_i2s1_8ch_src", CLK_SET_RATE_PARENT, + RK3528_CLKSEL_CON(25), 0, + RK3528_CLKGATE_CON(2), 12, GFLAGS, + &mclk_i2s1_8ch_sai_src_fracmux), + GATE(MCLK_I2S1_8CH_SAI_SRC, "mclk_i2s1_8ch_sai_src", "mclk_i2s1_8ch_sai_src_pre", 0, + RK3528_CLKGATE_CON(2), 13, GFLAGS), + + COMPOSITE_NOMUX(CLK_I2S2_2CH_SRC, "clk_i2s2_2ch_src", "gpll", 0, + RK3528_CLKSEL_CON(26), 3, 5, DFLAGS, + RK3528_CLKGATE_CON(2), 14, GFLAGS), + COMPOSITE_FRACMUX(CLK_I2S2_2CH_FRAC, "clk_i2s2_2ch_frac", "clk_i2s2_2ch_src", CLK_SET_RATE_PARENT, + RK3528_CLKSEL_CON(27), 0, + RK3528_CLKGATE_CON(2), 15, GFLAGS, + &mclk_i2s2_2ch_sai_src_fracmux), + GATE(MCLK_I2S2_2CH_SAI_SRC, "mclk_i2s2_2ch_sai_src", "mclk_i2s2_2ch_sai_src_pre", 0, + RK3528_CLKGATE_CON(3), 0, GFLAGS), + + COMPOSITE_NOMUX(CLK_I2S3_8CH_SRC, "clk_i2s3_8ch_src", "gpll", 0, + RK3528_CLKSEL_CON(22), 3, 5, DFLAGS, + RK3528_CLKGATE_CON(2), 8, GFLAGS), + COMPOSITE_FRACMUX(CLK_I2S3_8CH_FRAC, "clk_i2s3_8ch_frac", "clk_i2s3_8ch_src", CLK_SET_RATE_PARENT, + RK3528_CLKSEL_CON(23), 0, + RK3528_CLKGATE_CON(2), 9, GFLAGS, + &mclk_i2s3_8ch_sai_src_fracmux), + GATE(MCLK_I2S3_8CH_SAI_SRC, "mclk_i2s3_8ch_sai_src", "mclk_i2s3_8ch_sai_src_pre", 0, + RK3528_CLKGATE_CON(2), 10, GFLAGS), + + COMPOSITE_NOMUX(CLK_SPDIF_SRC, "clk_spdif_src", "gpll", 0, + RK3528_CLKSEL_CON(30), 2, 5, DFLAGS, + RK3528_CLKGATE_CON(3), 4, GFLAGS), + COMPOSITE_FRACMUX(CLK_SPDIF_FRAC, "clk_spdif_frac", "clk_spdif_src", CLK_SET_RATE_PARENT, + RK3528_CLKSEL_CON(31), 0, + RK3528_CLKGATE_CON(3), 5, GFLAGS, + &mclk_spdif_src_fracmux), + GATE(MCLK_SPDIF_SRC, "mclk_spdif_src", "mclk_spdif_src_pre", 0, + RK3528_CLKGATE_CON(3), 6, GFLAGS), + + /* bus */ + COMPOSITE_NODIV(ACLK_BUS_M_ROOT, "aclk_bus_m_root", mux_300m_200m_100m_24m_p, CLK_IS_CRITICAL, + RK3528_CLKSEL_CON(43), 12, 2, MFLAGS, + RK3528_CLKGATE_CON(8), 7, GFLAGS), + GATE(ACLK_GIC, "aclk_gic", "aclk_bus_m_root", CLK_IS_CRITICAL, + RK3528_CLKGATE_CON(9), 1, GFLAGS), + + COMPOSITE_NODIV(ACLK_BUS_ROOT, "aclk_bus_root", mux_200m_100m_24m_p, CLK_IS_CRITICAL, + RK3528_CLKSEL_CON(43), 6, 2, MFLAGS, + RK3528_CLKGATE_CON(8), 4, GFLAGS), + GATE(ACLK_SPINLOCK, "aclk_spinlock", "aclk_bus_root", 0, + RK3528_CLKGATE_CON(9), 2, GFLAGS), + GATE(ACLK_DMAC, "aclk_dmac", "aclk_bus_root", 0, + RK3528_CLKGATE_CON(9), 4, GFLAGS), + GATE(ACLK_DCF, "aclk_dcf", "aclk_bus_root", 0, + RK3528_CLKGATE_CON(11), 11, GFLAGS), + COMPOSITE(ACLK_BUS_VOPGL_ROOT, "aclk_bus_vopgl_root", mux_gpll_cpll_p, CLK_IS_CRITICAL, + RK3528_CLKSEL_CON(43), 3, 1, MFLAGS, 0, 3, DFLAGS, + RK3528_CLKGATE_CON(8), 0, GFLAGS), + COMPOSITE_NODIV(ACLK_BUS_H_ROOT, "aclk_bus_h_root", mux_500m_200m_100m_24m_p, CLK_IS_CRITICAL, + RK3528_CLKSEL_CON(43), 4, 2, MFLAGS, + RK3528_CLKGATE_CON(8), 2, GFLAGS), + GATE(ACLK_DMA2DDR, "aclk_dma2ddr", "aclk_bus_h_root", 0, + RK3528_CLKGATE_CON(10), 14, GFLAGS), + + COMPOSITE_NODIV(HCLK_BUS_ROOT, "hclk_bus_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL, + RK3528_CLKSEL_CON(43), 8, 2, MFLAGS, + RK3528_CLKGATE_CON(8), 5, GFLAGS), + + COMPOSITE_NODIV(PCLK_BUS_ROOT, "pclk_bus_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL, + RK3528_CLKSEL_CON(43), 10, 2, MFLAGS, + RK3528_CLKGATE_CON(8), 6, GFLAGS), + GATE(PCLK_DFT2APB, "pclk_dft2apb", "pclk_bus_root", 0, + RK3528_CLKGATE_CON(8), 13, GFLAGS), + GATE(PCLK_BUS_GRF, "pclk_bus_grf", "pclk_bus_root", CLK_IS_CRITICAL, + RK3528_CLKGATE_CON(8), 15, GFLAGS), + GATE(PCLK_TIMER, "pclk_timer", "pclk_bus_root", 0, + RK3528_CLKGATE_CON(9), 5, GFLAGS), + GATE(PCLK_JDBCK_DAP, "pclk_jdbck_dap", "pclk_bus_root", 0, + RK3528_CLKGATE_CON(9), 12, GFLAGS), + GATE(PCLK_WDT_NS, "pclk_wdt_ns", "pclk_bus_root", 0, + RK3528_CLKGATE_CON(9), 15, GFLAGS), + GATE(PCLK_UART0, "pclk_uart0", "pclk_bus_root", 0, + RK3528_CLKGATE_CON(10), 7, GFLAGS), + GATE(PCLK_PWM0, "pclk_pwm0", "pclk_bus_root", 0, + RK3528_CLKGATE_CON(11), 4, GFLAGS), + GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus_root", 0, + RK3528_CLKGATE_CON(11), 7, GFLAGS), + GATE(PCLK_DMA2DDR, "pclk_dma2ddr", "pclk_bus_root", 0, + RK3528_CLKGATE_CON(10), 13, GFLAGS), + GATE(PCLK_SCR, "pclk_scr", "pclk_bus_root", 0, + RK3528_CLKGATE_CON(11), 10, GFLAGS), + GATE(PCLK_INTMUX, "pclk_intmux", "pclk_bus_root", CLK_IGNORE_UNUSED, + RK3528_CLKGATE_CON(11), 12, GFLAGS), + + COMPOSITE_NODIV(CLK_PWM0, "clk_pwm0", mux_100m_50m_24m_p, 0, + RK3528_CLKSEL_CON(44), 6, 2, MFLAGS, + RK3528_CLKGATE_CON(11), 5, GFLAGS), + COMPOSITE_NODIV(CLK_PWM1, "clk_pwm1", mux_100m_50m_24m_p, 0, + RK3528_CLKSEL_CON(44), 8, 2, MFLAGS, + RK3528_CLKGATE_CON(11), 8, GFLAGS), + + GATE(CLK_CAPTURE_PWM1, "clk_capture_pwm1", "xin24m", 0, + RK3528_CLKGATE_CON(11), 9, GFLAGS), + GATE(CLK_CAPTURE_PWM0, "clk_capture_pwm0", "xin24m", 0, + RK3528_CLKGATE_CON(11), 6, GFLAGS), + GATE(CLK_JDBCK_DAP, "clk_jdbck_dap", "xin24m", 0, + RK3528_CLKGATE_CON(9), 13, GFLAGS), + GATE(TCLK_WDT_NS, "tclk_wdt_ns", "xin24m", 0, + RK3528_CLKGATE_CON(10), 0, GFLAGS), + + GATE(CLK_TIMER_ROOT, "clk_timer_root", "xin24m", 0, + RK3528_CLKGATE_CON(8), 9, GFLAGS), + GATE(CLK_TIMER0, "clk_timer0", "clk_timer_root", 0, + RK3528_CLKGATE_CON(9), 6, GFLAGS), + GATE(CLK_TIMER1, "clk_timer1", "clk_timer_root", 0, + RK3528_CLKGATE_CON(9), 7, GFLAGS), + GATE(CLK_TIMER2, "clk_timer2", "clk_timer_root", 0, + RK3528_CLKGATE_CON(9), 8, GFLAGS), + GATE(CLK_TIMER3, "clk_timer3", "clk_timer_root", 0, + RK3528_CLKGATE_CON(9), 9, GFLAGS), + GATE(CLK_TIMER4, "clk_timer4", "clk_timer_root", 0, + RK3528_CLKGATE_CON(9), 10, GFLAGS), + GATE(CLK_TIMER5, "clk_timer5", "clk_timer_root", 0, + RK3528_CLKGATE_CON(9), 11, GFLAGS), + + /* pmu */ + GATE(HCLK_PMU_ROOT, "hclk_pmu_root", "clk_100m_src", CLK_IGNORE_UNUSED, + RK3528_PMU_CLKGATE_CON(0), 1, GFLAGS), + GATE(PCLK_PMU_ROOT, "pclk_pmu_root", "clk_100m_src", CLK_IGNORE_UNUSED, + RK3528_PMU_CLKGATE_CON(0), 0, GFLAGS), + + GATE(FCLK_MCU, "fclk_mcu", "hclk_pmu_root", 0, + RK3528_PMU_CLKGATE_CON(0), 7, GFLAGS), + GATE(HCLK_PMU_SRAM, "hclk_pmu_sram", "hclk_pmu_root", CLK_IS_CRITICAL, + RK3528_PMU_CLKGATE_CON(5), 4, GFLAGS), + + GATE(PCLK_I2C2, "pclk_i2c2", "pclk_pmu_root", 0, + RK3528_PMU_CLKGATE_CON(0), 2, GFLAGS), + GATE(PCLK_PMU_HP_TIMER, "pclk_pmu_hp_timer", "pclk_pmu_root", 0, + RK3528_PMU_CLKGATE_CON(1), 2, GFLAGS), + GATE(PCLK_PMU_IOC, "pclk_pmu_ioc", "pclk_pmu_root", CLK_IS_CRITICAL, + RK3528_PMU_CLKGATE_CON(1), 5, GFLAGS), + GATE(PCLK_PMU_CRU, "pclk_pmu_cru", "pclk_pmu_root", CLK_IS_CRITICAL, + RK3528_PMU_CLKGATE_CON(1), 6, GFLAGS), + GATE(PCLK_PMU_GRF, "pclk_pmu_grf", "pclk_pmu_root", CLK_IS_CRITICAL, + RK3528_PMU_CLKGATE_CON(1), 7, GFLAGS), + GATE(PCLK_PMU_WDT, "pclk_pmu_wdt", "pclk_pmu_root", 0, + RK3528_PMU_CLKGATE_CON(1), 10, GFLAGS), + GATE(PCLK_PMU, "pclk_pmu", "pclk_pmu_root", CLK_IS_CRITICAL, + RK3528_PMU_CLKGATE_CON(0), 13, GFLAGS), + GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pmu_root", 0, + RK3528_PMU_CLKGATE_CON(0), 14, GFLAGS), + GATE(PCLK_OSCCHK, "pclk_oscchk", "pclk_pmu_root", 0, + RK3528_PMU_CLKGATE_CON(0), 9, GFLAGS), + GATE(PCLK_PMU_MAILBOX, "pclk_pmu_mailbox", "pclk_pmu_root", 0, + RK3528_PMU_CLKGATE_CON(1), 12, GFLAGS), + GATE(PCLK_SCRKEYGEN, "pclk_scrkeygen", "pclk_pmu_root", 0, + RK3528_PMU_CLKGATE_CON(1), 15, GFLAGS), + GATE(PCLK_PVTM_PMU, "pclk_pvtm_pmu", "pclk_pmu_root", 0, + RK3528_PMU_CLKGATE_CON(5), 1, GFLAGS), + + COMPOSITE_NODIV(CLK_I2C2, "clk_i2c2", clk_i2c2_p, 0, + RK3528_PMU_CLKSEL_CON(0), 0, 2, MFLAGS, + RK3528_PMU_CLKGATE_CON(0), 3, GFLAGS), + + GATE(CLK_REFOUT, "clk_refout", "xin24m", 0, + RK3528_PMU_CLKGATE_CON(2), 4, GFLAGS), + COMPOSITE_NOMUX(CLK_PVTM_PMU, "clk_pvtm_pmu", "xin24m", 0, + RK3528_PMU_CLKSEL_CON(5), 0, 5, DFLAGS, + RK3528_PMU_CLKGATE_CON(5), 0, GFLAGS), + + COMPOSITE_FRAC(XIN_OSC0_DIV, "xin_osc0_div", "xin24m", 0, + RK3528_PMU_CLKSEL_CON(1), 0, + RK3528_PMU_CLKGATE_CON(1), 0, GFLAGS), + /* clk_32k: internal! No path from external osc 32k */ + MUX(CLK_DEEPSLOW, "clk_32k", clk_32k_p, CLK_IS_CRITICAL, + RK3528_PMU_CLKSEL_CON(2), 0, 1, MFLAGS), + GATE(RTC_CLK_MCU, "rtc_clk_mcu", "clk_32k", 0, + RK3528_PMU_CLKGATE_CON(0), 8, GFLAGS), + GATE(CLK_DDR_FAIL_SAFE, "clk_ddr_fail_safe", "xin24m", CLK_IGNORE_UNUSED, + RK3528_PMU_CLKGATE_CON(1), 1, GFLAGS), + + COMPOSITE_NODIV(DBCLK_GPIO0, "dbclk_gpio0", mux_24m_32k_p, 0, + RK3528_PMU_CLKSEL_CON(0), 2, 1, MFLAGS, + RK3528_PMU_CLKGATE_CON(0), 15, GFLAGS), + COMPOSITE_NODIV(TCLK_PMU_WDT, "tclk_pmu_wdt", mux_24m_32k_p, 0, + RK3528_PMU_CLKSEL_CON(2), 1, 1, MFLAGS, + RK3528_PMU_CLKGATE_CON(1), 11, GFLAGS), + + /* core */ + COMPOSITE_NOMUX(ACLK_M_CORE_BIU, "aclk_m_core", "armclk", CLK_IS_CRITICAL, + RK3528_CLKSEL_CON(39), 11, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, + RK3528_CLKGATE_CON(5), 12, GFLAGS), + COMPOSITE_NOMUX(PCLK_DBG, "pclk_dbg", "armclk", CLK_IS_CRITICAL, + RK3528_CLKSEL_CON(40), 1, 5, DFLAGS | CLK_DIVIDER_READ_ONLY, + RK3528_CLKGATE_CON(5), 13, GFLAGS), + GATE(PCLK_CPU_ROOT, "pclk_cpu_root", "pclk_dbg", CLK_IS_CRITICAL, + RK3528_CLKGATE_CON(6), 1, GFLAGS), + GATE(PCLK_CORE_GRF, "pclk_core_grf", "pclk_cpu_root", CLK_IS_CRITICAL, + RK3528_CLKGATE_CON(6), 2, GFLAGS), + + /* ddr */ + GATE(CLK_DDRC_SRC, "clk_ddrc_src", "dpll", CLK_IS_CRITICAL, + RK3528_DDRPHY_CLKGATE_CON(0), 0, GFLAGS), + GATE(CLK_DDR_PHY, "clk_ddr_phy", "dpll", CLK_IS_CRITICAL, + RK3528_DDRPHY_CLKGATE_CON(0), 1, GFLAGS), + + COMPOSITE_NODIV(PCLK_DDR_ROOT, "pclk_ddr_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL, + RK3528_CLKSEL_CON(90), 0, 2, MFLAGS, + RK3528_CLKGATE_CON(45), 0, GFLAGS), + GATE(PCLK_DDRMON, "pclk_ddrmon", "pclk_ddr_root", CLK_IGNORE_UNUSED, + RK3528_CLKGATE_CON(45), 3, GFLAGS), + GATE(PCLK_DDR_HWLP, "pclk_ddr_hwlp", "pclk_ddr_root", CLK_IGNORE_UNUSED, + RK3528_CLKGATE_CON(45), 8, GFLAGS), + GATE(CLK_TIMER_DDRMON, "clk_timer_ddrmon", "xin24m", CLK_IGNORE_UNUSED, + RK3528_CLKGATE_CON(45), 4, GFLAGS), + + GATE(PCLK_DDRC, "pclk_ddrc", "pclk_ddr_root", CLK_IS_CRITICAL, + RK3528_CLKGATE_CON(45), 2, GFLAGS), + GATE(PCLK_DDR_GRF, "pclk_ddr_grf", "pclk_ddr_root", CLK_IS_CRITICAL, + RK3528_CLKGATE_CON(45), 6, GFLAGS), + GATE(PCLK_DDRPHY, "pclk_ddrphy", "pclk_ddr_root", CLK_IS_CRITICAL, + RK3528_CLKGATE_CON(45), 9, GFLAGS), + + GATE(ACLK_DDR_UPCTL, "aclk_ddr_upctl", "clk_ddrc_src", CLK_IS_CRITICAL, + RK3528_CLKGATE_CON(45), 11, GFLAGS), + GATE(CLK_DDR_UPCTL, "clk_ddr_upctl", "clk_ddrc_src", CLK_IS_CRITICAL, + RK3528_CLKGATE_CON(45), 12, GFLAGS), + GATE(CLK_DDRMON, "clk_ddrmon", "clk_ddrc_src", CLK_IS_CRITICAL, + RK3528_CLKGATE_CON(45), 13, GFLAGS), + GATE(ACLK_DDR_SCRAMBLE, "aclk_ddr_scramble", "clk_ddrc_src", CLK_IS_CRITICAL, + RK3528_CLKGATE_CON(45), 14, GFLAGS), + GATE(ACLK_SPLIT, "aclk_split", "clk_ddrc_src", CLK_IS_CRITICAL, + RK3528_CLKGATE_CON(45), 15, GFLAGS), + + /* gpu */ + COMPOSITE_NODIV(ACLK_GPU_ROOT, "aclk_gpu_root", mux_500m_300m_100m_24m_p, CLK_IS_CRITICAL, + RK3528_CLKSEL_CON(76), 0, 2, MFLAGS, + RK3528_CLKGATE_CON(34), 0, GFLAGS), + COMPOSITE_NODIV(ACLK_GPU, "aclk_gpu", aclk_gpu_p, CLK_SET_RATE_PARENT, + RK3528_CLKSEL_CON(76), 6, 1, MFLAGS, + RK3528_CLKGATE_CON(34), 7, GFLAGS), + GATE(ACLK_GPU_MALI, "aclk_gpu_mali", "aclk_gpu", 0, + RK3528_CLKGATE_CON(34), 8, GFLAGS), + COMPOSITE_NODIV(PCLK_GPU_ROOT, "pclk_gpu_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL, + RK3528_CLKSEL_CON(76), 4, 2, MFLAGS, + RK3528_CLKGATE_CON(34), 2, GFLAGS), + + /* rkvdec */ + COMPOSITE_NODIV(ACLK_RKVDEC_ROOT_NDFT, "aclk_rkvdec_root", mux_339m_200m_100m_24m_p, CLK_IS_CRITICAL, + RK3528_CLKSEL_CON(88), 6, 2, MFLAGS, + RK3528_CLKGATE_CON(44), 3, GFLAGS), + COMPOSITE_NODIV(HCLK_RKVDEC_ROOT, "hclk_rkvdec_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL, + RK3528_CLKSEL_CON(88), 4, 2, MFLAGS, + RK3528_CLKGATE_CON(44), 2, GFLAGS), + GATE(PCLK_DDRPHY_CRU, "pclk_ddrphy_cru", "hclk_rkvdec_root", CLK_IS_CRITICAL, + RK3528_CLKGATE_CON(44), 4, GFLAGS), + GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_root", 0, + RK3528_CLKGATE_CON(44), 9, GFLAGS), + COMPOSITE_NODIV(CLK_HEVC_CA_RKVDEC, "clk_hevc_ca_rkvdec", mux_600m_300m_200m_24m_p, 0, + RK3528_CLKSEL_CON(88), 11, 2, MFLAGS, + RK3528_CLKGATE_CON(44), 11, GFLAGS), + MUX(ACLK_RKVDEC_PVTMUX_ROOT, "aclk_rkvdec_pvtmux_root", aclk_rkvdec_pvtmux_root_p, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, + RK3528_CLKSEL_CON(88), 13, 1, MFLAGS), + GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pvtmux_root", 0, + RK3528_CLKGATE_CON(44), 8, GFLAGS), + + /* rkvenc */ + COMPOSITE_NODIV(ACLK_RKVENC_ROOT, "aclk_rkvenc_root", mux_300m_200m_100m_24m_p, CLK_IS_CRITICAL, + RK3528_CLKSEL_CON(79), 2, 2, MFLAGS, + RK3528_CLKGATE_CON(36), 1, GFLAGS), + GATE(ACLK_RKVENC, "aclk_rkvenc", "aclk_rkvenc_root", 0, + RK3528_CLKGATE_CON(36), 7, GFLAGS), + + COMPOSITE_NODIV(PCLK_RKVENC_ROOT, "pclk_rkvenc_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL, + RK3528_CLKSEL_CON(79), 4, 2, MFLAGS, + RK3528_CLKGATE_CON(36), 2, GFLAGS), + GATE(PCLK_RKVENC_IOC, "pclk_rkvenc_ioc", "pclk_rkvenc_root", CLK_IS_CRITICAL, + RK3528_CLKGATE_CON(37), 10, GFLAGS), + GATE(PCLK_RKVENC_GRF, "pclk_rkvenc_grf", "pclk_rkvenc_root", CLK_IS_CRITICAL, + RK3528_CLKGATE_CON(38), 6, GFLAGS), + GATE(PCLK_I2C1, "pclk_i2c1", "pclk_rkvenc_root", 0, + RK3528_CLKGATE_CON(36), 11, GFLAGS), + GATE(PCLK_I2C0, "pclk_i2c0", "pclk_rkvenc_root", 0, + RK3528_CLKGATE_CON(36), 13, GFLAGS), + GATE(PCLK_SPI0, "pclk_spi0", "pclk_rkvenc_root", 0, + RK3528_CLKGATE_CON(37), 2, GFLAGS), + GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_rkvenc_root", 0, + RK3528_CLKGATE_CON(37), 8, GFLAGS), + GATE(PCLK_UART1, "pclk_uart1", "pclk_rkvenc_root", 0, + RK3528_CLKGATE_CON(38), 2, GFLAGS), + GATE(PCLK_UART3, "pclk_uart3", "pclk_rkvenc_root", 0, + RK3528_CLKGATE_CON(38), 4, GFLAGS), + GATE(PCLK_CAN0, "pclk_can0", "pclk_rkvenc_root", 0, + RK3528_CLKGATE_CON(38), 7, GFLAGS), + GATE(PCLK_CAN1, "pclk_can1", "pclk_rkvenc_root", 0, + RK3528_CLKGATE_CON(38), 9, GFLAGS), + + COMPOSITE_NODIV(MCLK_PDM, "mclk_pdm", mux_150m_100m_24m_p, 0, + RK3528_CLKSEL_CON(80), 12, 2, MFLAGS, + RK3528_CLKGATE_CON(38), 1, GFLAGS), + COMPOSITE(CLK_CAN0, "clk_can0", mux_gpll_cpll_p, 0, + RK3528_CLKSEL_CON(81), 6, 1, MFLAGS, 0, 6, DFLAGS, + RK3528_CLKGATE_CON(38), 8, GFLAGS), + COMPOSITE(CLK_CAN1, "clk_can1", mux_gpll_cpll_p, 0, + RK3528_CLKSEL_CON(81), 13, 1, MFLAGS, 7, 6, DFLAGS, + RK3528_CLKGATE_CON(38), 10, GFLAGS), + + COMPOSITE_NODIV(HCLK_RKVENC_ROOT, "hclk_rkvenc_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL, + RK3528_CLKSEL_CON(79), 0, 2, MFLAGS, + RK3528_CLKGATE_CON(36), 0, GFLAGS), + GATE(HCLK_SAI_I2S1, "hclk_sai_i2s1", "hclk_rkvenc_root", 0, + RK3528_CLKGATE_CON(36), 9, GFLAGS), + GATE(HCLK_SPDIF, "hclk_spdif", "hclk_rkvenc_root", 0, + RK3528_CLKGATE_CON(37), 14, GFLAGS), + GATE(HCLK_PDM, "hclk_pdm", "hclk_rkvenc_root", 0, + RK3528_CLKGATE_CON(38), 0, GFLAGS), + GATE(HCLK_RKVENC, "hclk_rkvenc", "hclk_rkvenc_root", 0, + RK3528_CLKGATE_CON(36), 6, GFLAGS), + + COMPOSITE_NODIV(CLK_CORE_RKVENC, "clk_core_rkvenc", mux_300m_200m_100m_24m_p, 0, + RK3528_CLKSEL_CON(79), 6, 2, MFLAGS, + RK3528_CLKGATE_CON(36), 8, GFLAGS), + COMPOSITE_NODIV(CLK_I2C0, "clk_i2c0", mux_200m_100m_50m_24m_p, 0, + RK3528_CLKSEL_CON(79), 11, 2, MFLAGS, + RK3528_CLKGATE_CON(36), 14, GFLAGS), + COMPOSITE_NODIV(CLK_I2C1, "clk_i2c1", mux_200m_100m_50m_24m_p, 0, + RK3528_CLKSEL_CON(79), 9, 2, MFLAGS, + RK3528_CLKGATE_CON(36), 12, GFLAGS), + + COMPOSITE_NODIV(CLK_SPI0, "clk_spi0", mux_200m_100m_50m_24m_p, 0, + RK3528_CLKSEL_CON(79), 13, 2, MFLAGS, + RK3528_CLKGATE_CON(37), 3, GFLAGS), + COMPOSITE_NODIV(MCLK_SAI_I2S1, "mclk_sai_i2s1", mclk_sai_i2s1_p, CLK_SET_RATE_PARENT, + RK3528_CLKSEL_CON(79), 8, 1, MFLAGS, + RK3528_CLKGATE_CON(36), 10, GFLAGS), + GATE(DBCLK_GPIO4, "dbclk_gpio4", "xin24m", 0, + RK3528_CLKGATE_CON(37), 9, GFLAGS), + + /* vo */ + COMPOSITE_NODIV(HCLK_VO_ROOT, "hclk_vo_root", mux_150m_100m_24m_p, CLK_IS_CRITICAL, + RK3528_CLKSEL_CON(83), 2, 2, MFLAGS, + RK3528_CLKGATE_CON(39), 1, GFLAGS), + GATE(HCLK_VOP, "hclk_vop", "hclk_vo_root", 0, + RK3528_CLKGATE_CON(40), 2, GFLAGS), + GATE(HCLK_USBHOST, "hclk_usbhost", "hclk_vo_root", 0, + RK3528_CLKGATE_CON(43), 3, GFLAGS), + GATE(HCLK_JPEG_DECODER, "hclk_jpeg_decoder", "hclk_vo_root", 0, + RK3528_CLKGATE_CON(41), 7, GFLAGS), + GATE(HCLK_VDPP, "hclk_vdpp", "hclk_vo_root", 0, + RK3528_CLKGATE_CON(39), 10, GFLAGS), + GATE(HCLK_CVBS, "hclk_cvbs", "hclk_vo_root", 0, + RK3528_CLKGATE_CON(41), 3, GFLAGS), + GATE(HCLK_USBHOST_ARB, "hclk_usbhost_arb", "hclk_vo_root", 0, + RK3528_CLKGATE_CON(43), 4, GFLAGS), + GATE(HCLK_SAI_I2S3, "hclk_sai_i2s3", "hclk_vo_root", 0, + RK3528_CLKGATE_CON(42), 1, GFLAGS), + GATE(HCLK_HDCP, "hclk_hdcp", "hclk_vo_root", 0, + RK3528_CLKGATE_CON(41), 1, GFLAGS), + GATE(HCLK_RGA2E, "hclk_rga2e", "hclk_vo_root", 0, + RK3528_CLKGATE_CON(39), 7, GFLAGS), + GATE(HCLK_SDMMC0, "hclk_sdmmc0", "hclk_vo_root", 0, + RK3528_CLKGATE_CON(42), 9, GFLAGS), + GATE(HCLK_HDCP_KEY, "hclk_hdcp_key", "hclk_vo_root", 0, + RK3528_CLKGATE_CON(40), 15, GFLAGS), + + COMPOSITE_NODIV(ACLK_VO_L_ROOT, "aclk_vo_l_root", mux_150m_100m_24m_p, CLK_IS_CRITICAL, + RK3528_CLKSEL_CON(84), 1, 2, MFLAGS, + RK3528_CLKGATE_CON(41), 8, GFLAGS), + GATE(ACLK_MAC_VO, "aclk_gmac0", "aclk_vo_l_root", 0, + RK3528_CLKGATE_CON(41), 10, GFLAGS), + + COMPOSITE_NODIV(PCLK_VO_ROOT, "pclk_vo_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL, + RK3528_CLKSEL_CON(83), 4, 2, MFLAGS, + RK3528_CLKGATE_CON(39), 2, GFLAGS), + GATE(PCLK_MAC_VO, "pclk_gmac0", "pclk_vo_root", 0, + RK3528_CLKGATE_CON(41), 11, GFLAGS), + GATE(PCLK_VCDCPHY, "pclk_vcdcphy", "pclk_vo_root", 0, + RK3528_CLKGATE_CON(42), 4, GFLAGS), + GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_vo_root", 0, + RK3528_CLKGATE_CON(42), 5, GFLAGS), + GATE(PCLK_VO_IOC, "pclk_vo_ioc", "pclk_vo_root", CLK_IS_CRITICAL, + RK3528_CLKGATE_CON(42), 7, GFLAGS), + GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "pclk_vo_root", 0, + RK3528_CLKGATE_CON(42), 11, GFLAGS), + GATE(PCLK_UART4, "pclk_uart4", "pclk_vo_root", 0, + RK3528_CLKGATE_CON(43), 7, GFLAGS), + GATE(PCLK_I2C4, "pclk_i2c4", "pclk_vo_root", 0, + RK3528_CLKGATE_CON(43), 9, GFLAGS), + GATE(PCLK_I2C7, "pclk_i2c7", "pclk_vo_root", 0, + RK3528_CLKGATE_CON(43), 11, GFLAGS), + + GATE(PCLK_USBPHY, "pclk_usbphy", "pclk_vo_root", 0, + RK3528_CLKGATE_CON(43), 13, GFLAGS), + + GATE(PCLK_VO_GRF, "pclk_vo_grf", "pclk_vo_root", CLK_IS_CRITICAL, + RK3528_CLKGATE_CON(39), 13, GFLAGS), + GATE(PCLK_CRU, "pclk_cru", "pclk_vo_root", CLK_IS_CRITICAL, + RK3528_CLKGATE_CON(39), 15, GFLAGS), + GATE(PCLK_HDMI, "pclk_hdmi", "pclk_vo_root", 0, + RK3528_CLKGATE_CON(40), 6, GFLAGS), + GATE(PCLK_HDMIPHY, "pclk_hdmiphy", "pclk_vo_root", 0, + RK3528_CLKGATE_CON(40), 14, GFLAGS), + GATE(PCLK_HDCP, "pclk_hdcp", "pclk_vo_root", 0, + RK3528_CLKGATE_CON(41), 2, GFLAGS), + + COMPOSITE_NODIV(CLK_CORE_VDPP, "clk_core_vdpp", mux_339m_200m_100m_24m_p, 0, + RK3528_CLKSEL_CON(83), 10, 2, MFLAGS, + RK3528_CLKGATE_CON(39), 12, GFLAGS), + COMPOSITE_NODIV(CLK_CORE_RGA2E, "clk_core_rga2e", mux_339m_200m_100m_24m_p, 0, + RK3528_CLKSEL_CON(83), 8, 2, MFLAGS, + RK3528_CLKGATE_CON(39), 9, GFLAGS), + COMPOSITE_NODIV(ACLK_JPEG_ROOT, "aclk_jpeg_root", mux_339m_200m_100m_24m_p, CLK_IS_CRITICAL, + RK3528_CLKSEL_CON(84), 9, 2, MFLAGS, + RK3528_CLKGATE_CON(41), 15, GFLAGS), + GATE(ACLK_JPEG_DECODER, "aclk_jpeg_decoder", "aclk_jpeg_root", 0, + RK3528_CLKGATE_CON(41), 6, GFLAGS), + + COMPOSITE_NODIV(ACLK_VO_ROOT, "aclk_vo_root", mux_339m_200m_100m_24m_p, CLK_IS_CRITICAL, + RK3528_CLKSEL_CON(83), 0, 2, MFLAGS, + RK3528_CLKGATE_CON(39), 0, GFLAGS), + GATE(ACLK_RGA2E, "aclk_rga2e", "aclk_vo_root", 0, + RK3528_CLKGATE_CON(39), 8, GFLAGS), + GATE(ACLK_VDPP, "aclk_vdpp", "aclk_vo_root", 0, + RK3528_CLKGATE_CON(39), 11, GFLAGS), + GATE(ACLK_HDCP, "aclk_hdcp", "aclk_vo_root", 0, + RK3528_CLKGATE_CON(41), 0, GFLAGS), + + COMPOSITE(CCLK_SRC_SDMMC0, "cclk_src_sdmmc0", mux_gpll_cpll_xin24m_p, 0, + RK3528_CLKSEL_CON(85), 6, 2, MFLAGS, 0, 6, DFLAGS, + RK3528_CLKGATE_CON(42), 8, GFLAGS), + + COMPOSITE(ACLK_VOP_ROOT, "aclk_vop_root", mux_gpll_cpll_p, CLK_IS_CRITICAL, + RK3528_CLKSEL_CON(83), 15, 1, MFLAGS, 12, 3, DFLAGS, + RK3528_CLKGATE_CON(40), 0, GFLAGS), + GATE(ACLK_VOP, "aclk_vop", "aclk_vop_root", 0, + RK3528_CLKGATE_CON(40), 5, GFLAGS), + + COMPOSITE_NODIV(CLK_I2C4, "clk_i2c4", mux_200m_100m_50m_24m_p, 0, + RK3528_CLKSEL_CON(85), 13, 2, MFLAGS, + RK3528_CLKGATE_CON(43), 10, GFLAGS), + COMPOSITE_NODIV(CLK_I2C7, "clk_i2c7", mux_200m_100m_50m_24m_p, 0, + RK3528_CLKSEL_CON(86), 0, 2, MFLAGS, + RK3528_CLKGATE_CON(43), 12, GFLAGS), + GATE(DBCLK_GPIO2, "dbclk_gpio2", "xin24m", 0, + RK3528_CLKGATE_CON(42), 6, GFLAGS), + + GATE(CLK_HDMIHDP0, "clk_hdmihdp0", "xin24m", 0, + RK3528_CLKGATE_CON(43), 2, GFLAGS), + GATE(CLK_MACPHY, "clk_macphy", "xin24m", 0, + RK3528_CLKGATE_CON(42), 3, GFLAGS), + GATE(CLK_REF_USBPHY, "clk_ref_usbphy", "xin24m", 0, + RK3528_CLKGATE_CON(43), 14, GFLAGS), + GATE(CLK_SBPI_OTPC_NS, "clk_sbpi_otpc_ns", "xin24m", 0, + RK3528_CLKGATE_CON(42), 12, GFLAGS), + FACTOR(CLK_USER_OTPC_NS, "clk_user_otpc_ns", "clk_sbpi_otpc_ns", + 0, 1, 2), + + GATE(MCLK_SAI_I2S3, "mclk_sai_i2s3", "mclk_i2s3_8ch_sai_src", 0, + RK3528_CLKGATE_CON(42), 2, GFLAGS), + COMPOSITE_NODIV(DCLK_VOP0, "dclk_vop0", dclk_vop0_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, + RK3528_CLKSEL_CON(84), 0, 1, MFLAGS, + RK3528_CLKGATE_CON(40), 3, GFLAGS), + GATE(DCLK_VOP1, "dclk_vop1", "dclk_vop_src1", CLK_SET_RATE_PARENT, + RK3528_CLKGATE_CON(40), 4, GFLAGS), + FACTOR_GATE(DCLK_CVBS, "dclk_cvbs", "dclk_vop1", 0, 1, 4, + RK3528_CLKGATE_CON(41), 4, GFLAGS), + GATE(DCLK_4X_CVBS, "dclk_4x_cvbs", "dclk_vop1", 0, + RK3528_CLKGATE_CON(41), 5, GFLAGS), + + FACTOR_GATE(CLK_SFR_HDMI, "clk_sfr_hdmi", "dclk_vop_src1", 0, 1, 4, + RK3528_CLKGATE_CON(40), 7, GFLAGS), + + GATE(CLK_SPDIF_HDMI, "clk_spdif_hdmi", "mclk_spdif_src", 0, + RK3528_CLKGATE_CON(40), 10, GFLAGS), + GATE(MCLK_SPDIF, "mclk_spdif", "mclk_spdif_src", 0, + RK3528_CLKGATE_CON(37), 15, GFLAGS), + GATE(CLK_CEC_HDMI, "clk_cec_hdmi", "clk_32k", 0, + RK3528_CLKGATE_CON(40), 8, GFLAGS), + + /* vpu */ + GATE(DBCLK_GPIO1, "dbclk_gpio1", "xin24m", 0, + RK3528_CLKGATE_CON(26), 5, GFLAGS), + GATE(DBCLK_GPIO3, "dbclk_gpio3", "xin24m", 0, + RK3528_CLKGATE_CON(27), 1, GFLAGS), + GATE(CLK_SUSPEND_USB3OTG, "clk_suspend_usb3otg", "xin24m", 0, + RK3528_CLKGATE_CON(33), 4, GFLAGS), + GATE(CLK_PCIE_AUX, "clk_pcie_aux", "xin24m", 0, + RK3528_CLKGATE_CON(30), 2, GFLAGS), + GATE(TCLK_EMMC, "tclk_emmc", "xin24m", 0, + RK3528_CLKGATE_CON(26), 3, GFLAGS), + GATE(CLK_REF_USB3OTG, "clk_ref_usb3otg", "xin24m", 0, + RK3528_CLKGATE_CON(33), 2, GFLAGS), + COMPOSITE(CCLK_SRC_SDIO0, "cclk_src_sdio0", mux_gpll_cpll_xin24m_p, 0, + RK3528_CLKSEL_CON(72), 6, 2, MFLAGS, 0, 6, DFLAGS, + RK3528_CLKGATE_CON(32), 1, GFLAGS), + + COMPOSITE_NODIV(PCLK_VPU_ROOT, "pclk_vpu_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL, + RK3528_CLKSEL_CON(61), 4, 2, MFLAGS, + RK3528_CLKGATE_CON(25), 5, GFLAGS), + GATE(PCLK_VPU_GRF, "pclk_vpu_grf", "pclk_vpu_root", CLK_IS_CRITICAL, + RK3528_CLKGATE_CON(25), 12, GFLAGS), + GATE(PCLK_CRU_PCIE, "pclk_cru_pcie", "pclk_vpu_root", CLK_IS_CRITICAL, + RK3528_CLKGATE_CON(25), 11, GFLAGS), + GATE(PCLK_UART6, "pclk_uart6", "pclk_vpu_root", 0, + RK3528_CLKGATE_CON(27), 11, GFLAGS), + GATE(PCLK_CAN2, "pclk_can2", "pclk_vpu_root", 0, + RK3528_CLKGATE_CON(32), 7, GFLAGS), + GATE(PCLK_SPI1, "pclk_spi1", "pclk_vpu_root", 0, + RK3528_CLKGATE_CON(27), 4, GFLAGS), + GATE(PCLK_CAN3, "pclk_can3", "pclk_vpu_root", 0, + RK3528_CLKGATE_CON(32), 9, GFLAGS), + GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_vpu_root", 0, + RK3528_CLKGATE_CON(27), 0, GFLAGS), + GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_vpu_root", 0, + RK3528_CLKGATE_CON(26), 4, GFLAGS), + GATE(PCLK_SARADC, "pclk_saradc", "pclk_vpu_root", 0, + RK3528_CLKGATE_CON(32), 11, GFLAGS), + GATE(PCLK_ACODEC, "pclk_acodec", "pclk_vpu_root", 0, + RK3528_CLKGATE_CON(26), 13, GFLAGS), + GATE(PCLK_UART7, "pclk_uart7", "pclk_vpu_root", 0, + RK3528_CLKGATE_CON(27), 13, GFLAGS), + GATE(PCLK_UART5, "pclk_uart5", "pclk_vpu_root", 0, + RK3528_CLKGATE_CON(27), 9, GFLAGS), + GATE(PCLK_TSADC, "pclk_tsadc", "pclk_vpu_root", 0, + RK3528_CLKGATE_CON(32), 14, GFLAGS), + GATE(PCLK_PCIE, "pclk_pcie", "pclk_vpu_root", 0, + RK3528_CLKGATE_CON(30), 1, GFLAGS), + GATE(PCLK_UART2, "pclk_uart2", "pclk_vpu_root", 0, + RK3528_CLKGATE_CON(27), 7, GFLAGS), + GATE(PCLK_VPU_IOC, "pclk_vpu_ioc", "pclk_vpu_root", CLK_IS_CRITICAL, + RK3528_CLKGATE_CON(26), 8, GFLAGS), + GATE(PCLK_PIPE_GRF, "pclk_pipe_grf", "pclk_vpu_root", CLK_IS_CRITICAL, + RK3528_CLKGATE_CON(30), 7, GFLAGS), + GATE(PCLK_I2C5, "pclk_i2c5", "pclk_vpu_root", 0, + RK3528_CLKGATE_CON(28), 1, GFLAGS), + GATE(PCLK_PCIE_PHY, "pclk_pcie_phy", "pclk_vpu_root", 0, + RK3528_CLKGATE_CON(30), 6, GFLAGS), + GATE(PCLK_I2C3, "pclk_i2c3", "pclk_vpu_root", 0, + RK3528_CLKGATE_CON(27), 15, GFLAGS), + GATE(PCLK_MAC_VPU, "pclk_gmac1", "pclk_vpu_root", CLK_IS_CRITICAL, + RK3528_CLKGATE_CON(28), 6, GFLAGS), + GATE(PCLK_I2C6, "pclk_i2c6", "pclk_vpu_root", 0, + RK3528_CLKGATE_CON(28), 3, GFLAGS), + + COMPOSITE_NODIV(ACLK_VPU_L_ROOT, "aclk_vpu_l_root", mux_200m_100m_24m_p, CLK_IS_CRITICAL, + RK3528_CLKSEL_CON(60), 0, 2, MFLAGS, + RK3528_CLKGATE_CON(25), 0, GFLAGS), + GATE(ACLK_EMMC, "aclk_emmc", "aclk_vpu_l_root", 0, + RK3528_CLKGATE_CON(26), 1, GFLAGS), + GATE(ACLK_MAC_VPU, "aclk_gmac1", "aclk_vpu_l_root", 0, + RK3528_CLKGATE_CON(28), 5, GFLAGS), + GATE(ACLK_PCIE, "aclk_pcie", "aclk_vpu_l_root", 0, + RK3528_CLKGATE_CON(30), 3, GFLAGS), + + GATE(ACLK_USB3OTG, "aclk_usb3otg", "aclk_vpu_l_root", 0, + RK3528_CLKGATE_CON(33), 1, GFLAGS), + + COMPOSITE_NODIV(HCLK_VPU_ROOT, "hclk_vpu_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL, + RK3528_CLKSEL_CON(61), 2, 2, MFLAGS, + RK3528_CLKGATE_CON(25), 4, GFLAGS), + GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_root", 0, + RK3528_CLKGATE_CON(25), 10, GFLAGS), + GATE(HCLK_SFC, "hclk_sfc", "hclk_vpu_root", 0, + RK3528_CLKGATE_CON(25), 13, GFLAGS), + GATE(HCLK_EMMC, "hclk_emmc", "hclk_vpu_root", 0, + RK3528_CLKGATE_CON(26), 0, GFLAGS), + GATE(HCLK_SAI_I2S0, "hclk_sai_i2s0", "hclk_vpu_root", 0, + RK3528_CLKGATE_CON(26), 9, GFLAGS), + GATE(HCLK_SAI_I2S2, "hclk_sai_i2s2", "hclk_vpu_root", 0, + RK3528_CLKGATE_CON(26), 11, GFLAGS), + + GATE(HCLK_PCIE_SLV, "hclk_pcie_slv", "hclk_vpu_root", 0, + RK3528_CLKGATE_CON(30), 4, GFLAGS), + GATE(HCLK_PCIE_DBI, "hclk_pcie_dbi", "hclk_vpu_root", 0, + RK3528_CLKGATE_CON(30), 5, GFLAGS), + GATE(HCLK_SDIO0, "hclk_sdio0", "hclk_vpu_root", 0, + RK3528_CLKGATE_CON(32), 2, GFLAGS), + GATE(HCLK_SDIO1, "hclk_sdio1", "hclk_vpu_root", 0, + RK3528_CLKGATE_CON(32), 4, GFLAGS), + + COMPOSITE_NOMUX(CLK_GMAC1_VPU_25M, "clk_gmac1_25m", "ppll", 0, + RK3528_CLKSEL_CON(60), 2, 8, DFLAGS, + RK3528_CLKGATE_CON(25), 1, GFLAGS), + COMPOSITE_NOMUX(CLK_PPLL_125M_MATRIX, "clk_ppll_125m_src", "ppll", 0, + RK3528_CLKSEL_CON(60), 10, 5, DFLAGS, + RK3528_CLKGATE_CON(25), 2, GFLAGS), + + COMPOSITE(CLK_CAN3, "clk_can3", mux_gpll_cpll_p, 0, + RK3528_CLKSEL_CON(73), 13, 1, MFLAGS, 7, 6, DFLAGS, + RK3528_CLKGATE_CON(32), 10, GFLAGS), + COMPOSITE_NODIV(CLK_I2C6, "clk_i2c6", mux_200m_100m_50m_24m_p, 0, + RK3528_CLKSEL_CON(64), 0, 2, MFLAGS, + RK3528_CLKGATE_CON(28), 4, GFLAGS), + + COMPOSITE(SCLK_SFC, "sclk_sfc", mux_gpll_cpll_xin24m_p, 0, + RK3528_CLKSEL_CON(61), 12, 2, MFLAGS, 6, 6, DFLAGS, + RK3528_CLKGATE_CON(25), 14, GFLAGS), + COMPOSITE(CCLK_SRC_EMMC, "cclk_src_emmc", mux_gpll_cpll_xin24m_p, 0, + RK3528_CLKSEL_CON(62), 6, 2, MFLAGS, 0, 6, DFLAGS, + RK3528_CLKGATE_CON(25), 15, GFLAGS), + + COMPOSITE_NODIV(ACLK_VPU_ROOT, "aclk_vpu_root", + mux_300m_200m_100m_24m_p, CLK_IS_CRITICAL, + RK3528_CLKSEL_CON(61), 0, 2, MFLAGS, + RK3528_CLKGATE_CON(25), 3, GFLAGS), + GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_root", 0, + RK3528_CLKGATE_CON(25), 9, GFLAGS), + + COMPOSITE_NODIV(CLK_SPI1, "clk_spi1", mux_200m_100m_50m_24m_p, 0, + RK3528_CLKSEL_CON(63), 10, 2, MFLAGS, + RK3528_CLKGATE_CON(27), 5, GFLAGS), + COMPOSITE(CCLK_SRC_SDIO1, "cclk_src_sdio1", mux_gpll_cpll_xin24m_p, 0, + RK3528_CLKSEL_CON(72), 14, 2, MFLAGS, 8, 6, DFLAGS, + RK3528_CLKGATE_CON(32), 3, GFLAGS), + COMPOSITE(CLK_CAN2, "clk_can2", mux_gpll_cpll_p, 0, + RK3528_CLKSEL_CON(73), 6, 1, MFLAGS, 0, 6, DFLAGS, + RK3528_CLKGATE_CON(32), 8, GFLAGS), + COMPOSITE_NOMUX(CLK_TSADC, "clk_tsadc", "xin24m", 0, + RK3528_CLKSEL_CON(74), 3, 5, DFLAGS, + RK3528_CLKGATE_CON(32), 15, GFLAGS), + COMPOSITE_NOMUX(CLK_SARADC, "clk_saradc", "xin24m", 0, + RK3528_CLKSEL_CON(74), 0, 3, DFLAGS, + RK3528_CLKGATE_CON(32), 12, GFLAGS), + COMPOSITE_NOMUX(CLK_TSADC_TSEN, "clk_tsadc_tsen", "xin24m", 0, + RK3528_CLKSEL_CON(74), 8, 5, DFLAGS, + RK3528_CLKGATE_CON(33), 0, GFLAGS), + COMPOSITE_NODIV(BCLK_EMMC, "bclk_emmc", mux_200m_100m_50m_24m_p, 0, + RK3528_CLKSEL_CON(62), 8, 2, MFLAGS, + RK3528_CLKGATE_CON(26), 2, GFLAGS), + COMPOSITE_NOMUX(MCLK_ACODEC_TX, "mclk_acodec_tx", "mclk_i2s2_2ch_sai_src", 0, + RK3528_CLKSEL_CON(63), 0, 8, DFLAGS, + RK3528_CLKGATE_CON(26), 14, GFLAGS), + COMPOSITE_NODIV(CLK_I2C3, "clk_i2c3", mux_200m_100m_50m_24m_p, 0, + RK3528_CLKSEL_CON(63), 12, 2, MFLAGS, + RK3528_CLKGATE_CON(28), 0, GFLAGS), + COMPOSITE_NODIV(CLK_I2C5, "clk_i2c5", mux_200m_100m_50m_24m_p, 0, + RK3528_CLKSEL_CON(63), 14, 2, MFLAGS, + RK3528_CLKGATE_CON(28), 2, GFLAGS), + COMPOSITE_NODIV(MCLK_SAI_I2S0, "mclk_sai_i2s0", mclk_sai_i2s0_p, CLK_SET_RATE_PARENT, + RK3528_CLKSEL_CON(62), 10, 1, MFLAGS, + RK3528_CLKGATE_CON(26), 10, GFLAGS), + GATE(MCLK_SAI_I2S2, "mclk_sai_i2s2", "mclk_i2s2_2ch_sai_src", 0, + RK3528_CLKGATE_CON(26), 12, GFLAGS), + + /* pcie */ + COMPOSITE_NOMUX(CLK_PPLL_100M_MATRIX, "clk_ppll_100m_src", "ppll", CLK_IS_CRITICAL, + RK3528_PCIE_CLKSEL_CON(1), 2, 5, DFLAGS, + RK3528_PCIE_CLKGATE_CON(0), 1, GFLAGS), + COMPOSITE_NOMUX(CLK_PPLL_50M_MATRIX, "clk_ppll_50m_src", "ppll", CLK_IS_CRITICAL, + RK3528_PCIE_CLKSEL_CON(1), 7, 5, DFLAGS, + RK3528_PCIE_CLKGATE_CON(0), 2, GFLAGS), + MUX(CLK_REF_PCIE_INNER_PHY, "clk_ref_pcie_inner_phy", clk_ref_pcie_inner_phy_p, 0, + RK3528_PCIE_CLKSEL_CON(1), 13, 1, MFLAGS), + FACTOR(CLK_REF_PCIE_100M_PHY, "clk_ref_pcie_100m_phy", "clk_ppll_100m_src", + 0, 1, 1), + + /* gmac */ + DIV(CLK_GMAC0_SRC, "clk_gmac0_src", "gmac0", 0, + RK3528_CLKSEL_CON(84), 3, 6, DFLAGS), + GATE(CLK_GMAC0_TX, "clk_gmac0_tx", "clk_gmac0_src", 0, + RK3528_CLKGATE_CON(41), 13, GFLAGS), + GATE(CLK_GMAC0_RX, "clk_gmac0_rx", "clk_gmac0_src", 0, + RK3528_CLKGATE_CON(41), 14, GFLAGS), + GATE(CLK_GMAC0_RMII_50M, "clk_gmac0_rmii_50m", "gmac0", 0, + RK3528_CLKGATE_CON(41), 12, GFLAGS), + + FACTOR(CLK_GMAC1_RMII_VPU, "clk_gmac1_50m", "clk_ppll_50m_src", + 0, 1, 1), + FACTOR(CLK_GMAC1_SRC_VPU, "clk_gmac1_125m", "clk_ppll_125m_src", + 0, 1, 1), +}; + +static int __init clk_rk3528_probe(struct platform_device *pdev) +{ + struct rockchip_clk_provider *ctx; + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + unsigned long nr_branches = ARRAY_SIZE(rk3528_clk_branches); + unsigned long nr_clks; + void __iomem *reg_base; + + nr_clks = rockchip_clk_find_max_clk_id(rk3528_clk_branches, + nr_branches) + 1; + + reg_base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(reg_base)) + return dev_err_probe(dev, PTR_ERR(reg_base), + "could not map cru region"); + + ctx = rockchip_clk_init(np, reg_base, nr_clks); + if (IS_ERR(ctx)) + return dev_err_probe(dev, PTR_ERR(ctx), + "rockchip clk init failed"); + + rockchip_clk_register_plls(ctx, rk3528_pll_clks, + ARRAY_SIZE(rk3528_pll_clks), + RK3528_GRF_SOC_STATUS0); + rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", + mux_armclk, ARRAY_SIZE(mux_armclk), + &rk3528_cpuclk_data, rk3528_cpuclk_rates, + ARRAY_SIZE(rk3528_cpuclk_rates)); + rockchip_clk_register_branches(ctx, rk3528_clk_branches, nr_branches); + + rk3528_rst_init(np, reg_base); + + rockchip_register_restart_notifier(ctx, RK3528_GLB_SRST_FST, NULL); + + rockchip_clk_of_add_provider(np, ctx); + + return 0; +} + +static const struct of_device_id clk_rk3528_match_table[] = { + { .compatible = "rockchip,rk3528-cru" }, + { /* end */ } +}; + +static struct platform_driver clk_rk3528_driver = { + .driver = { + .name = "clk-rk3528", + .of_match_table = clk_rk3528_match_table, + .suppress_bind_attrs = true, + }, +}; +builtin_platform_driver_probe(clk_rk3528_driver, clk_rk3528_probe); diff --git a/drivers/clk/rockchip/clk-rk3562.c b/drivers/clk/rockchip/clk-rk3562.c new file mode 100644 index 000000000000..b8858e5d5530 --- /dev/null +++ b/drivers/clk/rockchip/clk-rk3562.c @@ -0,0 +1,1101 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * Author: Elaine Zhang <zhangqing@rock-chips.com> + * Author: Finley Xiao <finley.xiao@rock-chips.com> + */ + +#include <linux/clk-provider.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/of_address.h> +#include <linux/platform_device.h> +#include <linux/syscore_ops.h> +#include <dt-bindings/clock/rockchip,rk3562-cru.h> +#include "clk.h" + +#define RK3562_GRF_SOC_STATUS0 0x430 +#define ROCKCHIP_PLL_ALLOW_POWER_DOWN BIT(2) + +enum rk3562_plls { + apll, gpll, vpll, hpll, cpll, dpll, +}; + +static struct rockchip_pll_rate_table rk3562_pll_rates[] = { + /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ + RK3036_PLL_RATE(2208000000, 1, 92, 1, 1, 1, 0), + RK3036_PLL_RATE(2184000000, 1, 91, 1, 1, 1, 0), + RK3036_PLL_RATE(2160000000, 1, 90, 1, 1, 1, 0), + RK3036_PLL_RATE(2088000000, 1, 87, 1, 1, 1, 0), + RK3036_PLL_RATE(2064000000, 1, 86, 1, 1, 1, 0), + RK3036_PLL_RATE(2040000000, 1, 85, 1, 1, 1, 0), + RK3036_PLL_RATE(2016000000, 1, 84, 1, 1, 1, 0), + RK3036_PLL_RATE(1992000000, 1, 83, 1, 1, 1, 0), + RK3036_PLL_RATE(1920000000, 1, 80, 1, 1, 1, 0), + RK3036_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0), + RK3036_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0), + RK3036_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0), + RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0), + RK3036_PLL_RATE(1600000000, 3, 200, 1, 1, 1, 0), + RK3036_PLL_RATE(1584000000, 1, 132, 2, 1, 1, 0), + RK3036_PLL_RATE(1560000000, 1, 130, 2, 1, 1, 0), + RK3036_PLL_RATE(1536000000, 1, 128, 2, 1, 1, 0), + RK3036_PLL_RATE(1512000000, 1, 126, 2, 1, 1, 0), + RK3036_PLL_RATE(1488000000, 1, 124, 2, 1, 1, 0), + RK3036_PLL_RATE(1464000000, 1, 122, 2, 1, 1, 0), + RK3036_PLL_RATE(1440000000, 1, 120, 2, 1, 1, 0), + RK3036_PLL_RATE(1416000000, 1, 118, 2, 1, 1, 0), + RK3036_PLL_RATE(1400000000, 3, 350, 2, 1, 1, 0), + RK3036_PLL_RATE(1392000000, 1, 116, 2, 1, 1, 0), + RK3036_PLL_RATE(1368000000, 1, 114, 2, 1, 1, 0), + RK3036_PLL_RATE(1344000000, 1, 112, 2, 1, 1, 0), + RK3036_PLL_RATE(1320000000, 1, 110, 2, 1, 1, 0), + RK3036_PLL_RATE(1296000000, 1, 108, 2, 1, 1, 0), + RK3036_PLL_RATE(1272000000, 1, 106, 2, 1, 1, 0), + RK3036_PLL_RATE(1248000000, 1, 104, 2, 1, 1, 0), + RK3036_PLL_RATE(1200000000, 1, 100, 2, 1, 1, 0), + RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0), + RK3036_PLL_RATE(1104000000, 1, 92, 2, 1, 1, 0), + RK3036_PLL_RATE(1100000000, 3, 275, 2, 1, 1, 0), + RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0), + RK3036_PLL_RATE(1000000000, 3, 250, 2, 1, 1, 0), + RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0), + RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0), + RK3036_PLL_RATE(800000000, 3, 200, 2, 1, 1, 0), + RK3036_PLL_RATE(700000000, 3, 350, 4, 1, 1, 0), + RK3036_PLL_RATE(696000000, 1, 116, 4, 1, 1, 0), + RK3036_PLL_RATE(600000000, 1, 100, 4, 1, 1, 0), + RK3036_PLL_RATE(594000000, 1, 99, 4, 1, 1, 0), + RK3036_PLL_RATE(500000000, 1, 125, 6, 1, 1, 0), + RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0), + RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0), + RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0), + RK3036_PLL_RATE(200000000, 1, 100, 3, 4, 1, 0), + RK3036_PLL_RATE(148500000, 1, 99, 4, 4, 1, 0), + RK3036_PLL_RATE(100000000, 1, 150, 6, 6, 1, 0), + RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0), + RK3036_PLL_RATE(74250000, 2, 99, 4, 4, 1, 0), + { /* sentinel */ }, +}; + +PNAME(mux_pll_p) = { "xin24m" }; +PNAME(gpll_cpll_p) = { "gpll", "cpll" }; +PNAME(gpll_cpll_hpll_p) = { "gpll", "cpll", "hpll" }; +PNAME(gpll_cpll_pvtpll_dmyapll_p) = { "gpll", "cpll", "log_pvtpll", "dummy_apll" }; +PNAME(gpll_cpll_hpll_xin24m_p) = { "gpll", "cpll", "hpll", "xin24m" }; +PNAME(gpll_cpll_vpll_dmyhpll_p) = { "gpll", "cpll", "vpll", "dummy_hpll" }; +PNAME(gpll_dmyhpll_vpll_apll_p) = { "gpll", "dummy_hpll", "vpll", "apll" }; +PNAME(gpll_cpll_xin24m_p) = { "gpll", "cpll", "xin24m" }; +PNAME(gpll_cpll_xin24m_dmyapll_p) = { "gpll", "cpll", "xin24m", "dummy_apll" }; +PNAME(gpll_cpll_xin24m_dmyhpll_p) = { "gpll", "cpll", "xin24m", "dummy_hpll" }; +PNAME(vpll_dmyhpll_gpll_cpll_p) = { "vpll", "dummy_hpll", "gpll", "cpll" }; +PNAME(mux_xin24m_32k_p) = { "xin24m", "clk_rtc_32k" }; +PNAME(mux_50m_xin24m_p) = { "clk_matrix_50m_src", "xin24m" }; +PNAME(mux_100m_50m_xin24m_p) = { "clk_matrix_100m_src", "clk_matrix_50m_src", "xin24m" }; +PNAME(mux_125m_xin24m_p) = { "clk_matrix_125m_src", "xin24m" }; +PNAME(mux_200m_xin24m_32k_p) = { "clk_200m_pmu", "xin24m", "clk_rtc_32k" }; +PNAME(mux_200m_100m_p) = { "clk_matrix_200m_src", "clk_matrix_100m_src" }; +PNAME(mux_200m_100m_50m_xin24m_p) = { "clk_matrix_200m_src", "clk_matrix_100m_src", "clk_matrix_50m_src", "xin24m" }; +PNAME(clk_sai0_p) = { "clk_sai0_src", "clk_sai0_frac", "xin_osc0_half", "mclk_sai0_from_io" }; +PNAME(mclk_sai0_out2io_p) = { "mclk_sai0", "xin_osc0_half" }; +PNAME(clk_sai1_p) = { "clk_sai1_src", "clk_sai1_frac", "xin_osc0_half", "mclk_sai1_from_io" }; +PNAME(mclk_sai1_out2io_p) = { "mclk_sai1", "xin_osc0_half" }; +PNAME(clk_sai2_p) = { "clk_sai2_src", "clk_sai2_frac", "xin_osc0_half", "mclk_sai2_from_io" }; +PNAME(mclk_sai2_out2io_p) = { "mclk_sai2", "xin_osc0_half" }; +PNAME(clk_spdif_p) = { "clk_spdif_src", "clk_spdif_frac", "xin_osc0_half" }; +PNAME(clk_uart1_p) = { "clk_uart1_src", "clk_uart1_frac", "xin24m" }; +PNAME(clk_uart2_p) = { "clk_uart2_src", "clk_uart2_frac", "xin24m" }; +PNAME(clk_uart3_p) = { "clk_uart3_src", "clk_uart3_frac", "xin24m" }; +PNAME(clk_uart4_p) = { "clk_uart4_src", "clk_uart4_frac", "xin24m" }; +PNAME(clk_uart5_p) = { "clk_uart5_src", "clk_uart5_frac", "xin24m" }; +PNAME(clk_uart6_p) = { "clk_uart6_src", "clk_uart6_frac", "xin24m" }; +PNAME(clk_uart7_p) = { "clk_uart7_src", "clk_uart7_frac", "xin24m" }; +PNAME(clk_uart8_p) = { "clk_uart8_src", "clk_uart8_frac", "xin24m" }; +PNAME(clk_uart9_p) = { "clk_uart9_src", "clk_uart9_frac", "xin24m" }; +PNAME(clk_rtc32k_pmu_p) = { "clk_rtc32k_frac", "xin32k", "clk_32k_pvtm" }; +PNAME(clk_pmu1_uart0_p) = { "clk_pmu1_uart0_src", "clk_pmu1_uart0_frac", "xin24m" }; +PNAME(clk_pipephy_ref_p) = { "clk_pipephy_div", "clk_pipephy_xin24m" }; +PNAME(clk_usbphy_ref_p) = { "clk_usb2phy_xin24m", "clk_24m_sscsrc" }; +PNAME(clk_mipidsi_ref_p) = { "clk_mipidsiphy_xin24m", "clk_24m_sscsrc" }; + +static struct rockchip_pll_clock rk3562_pll_clks[] __initdata = { + [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p, + 0, RK3562_PLL_CON(0), + RK3562_MODE_CON, 0, 0, + ROCKCHIP_PLL_ALLOW_POWER_DOWN, rk3562_pll_rates), + [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p, + 0, RK3562_PLL_CON(24), + RK3562_MODE_CON, 2, 3, 0, rk3562_pll_rates), + [vpll] = PLL(pll_rk3328, PLL_VPLL, "vpll", mux_pll_p, + 0, RK3562_PLL_CON(32), + RK3562_MODE_CON, 6, 4, + ROCKCHIP_PLL_ALLOW_POWER_DOWN, rk3562_pll_rates), + [hpll] = PLL(pll_rk3328, PLL_HPLL, "hpll", mux_pll_p, + 0, RK3562_PLL_CON(40), + RK3562_MODE_CON, 8, 5, + ROCKCHIP_PLL_ALLOW_POWER_DOWN, rk3562_pll_rates), + [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p, + 0, RK3562_PMU1_PLL_CON(0), + RK3562_PMU1_MODE_CON, 0, 2, 0, rk3562_pll_rates), + [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p, + CLK_IS_CRITICAL, RK3562_SUBDDR_PLL_CON(0), + RK3562_SUBDDR_MODE_CON, 0, 1, 0, NULL), +}; + +#define MFLAGS CLK_MUX_HIWORD_MASK +#define DFLAGS CLK_DIVIDER_HIWORD_MASK +#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) + +static struct rockchip_clk_branch rk3562_clk_sai0_fracmux __initdata = + MUX(CLK_SAI0, "clk_sai0", clk_sai0_p, CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(3), 6, 2, MFLAGS); + +static struct rockchip_clk_branch rk3562_clk_sai1_fracmux __initdata = + MUX(CLK_SAI1, "clk_sai1", clk_sai1_p, CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(5), 6, 2, MFLAGS); + +static struct rockchip_clk_branch rk3562_clk_sai2_fracmux __initdata = + MUX(CLK_SAI2, "clk_sai2", clk_sai2_p, CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(8), 6, 2, MFLAGS); + +static struct rockchip_clk_branch rk3562_clk_spdif_fracmux __initdata = + MUX(CLK_SPDIF, "clk_spdif", clk_spdif_p, CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(15), 6, 2, MFLAGS); + +static struct rockchip_clk_branch rk3562_clk_uart1_fracmux __initdata = + MUX(CLK_UART1, "clk_uart1", clk_uart1_p, CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(21), 14, 2, MFLAGS); + +static struct rockchip_clk_branch rk3562_clk_uart2_fracmux __initdata = + MUX(CLK_UART2, "clk_uart2", clk_uart2_p, CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(23), 14, 2, MFLAGS); + +static struct rockchip_clk_branch rk3562_clk_uart3_fracmux __initdata = + MUX(CLK_UART3, "clk_uart3", clk_uart3_p, CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(25), 14, 2, MFLAGS); + +static struct rockchip_clk_branch rk3562_clk_uart4_fracmux __initdata = + MUX(CLK_UART4, "clk_uart4", clk_uart4_p, CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(27), 14, 2, MFLAGS); + +static struct rockchip_clk_branch rk3562_clk_uart5_fracmux __initdata = + MUX(CLK_UART5, "clk_uart5", clk_uart5_p, CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(29), 14, 2, MFLAGS); + +static struct rockchip_clk_branch rk3562_clk_uart6_fracmux __initdata = + MUX(CLK_UART6, "clk_uart6", clk_uart6_p, CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(31), 14, 2, MFLAGS); + +static struct rockchip_clk_branch rk3562_clk_uart7_fracmux __initdata = + MUX(CLK_UART7, "clk_uart7", clk_uart7_p, CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(33), 14, 2, MFLAGS); + +static struct rockchip_clk_branch rk3562_clk_uart8_fracmux __initdata = + MUX(CLK_UART8, "clk_uart8", clk_uart8_p, CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(35), 14, 2, MFLAGS); + +static struct rockchip_clk_branch rk3562_clk_uart9_fracmux __initdata = + MUX(CLK_UART9, "clk_uart9", clk_uart9_p, CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(37), 14, 2, MFLAGS); + +static struct rockchip_clk_branch rk3562_rtc32k_pmu_fracmux __initdata = + MUX(CLK_RTC_32K, "clk_rtc_32k", clk_rtc32k_pmu_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, + RK3562_PMU0_CLKSEL_CON(1), 0, 2, MFLAGS); + +static struct rockchip_clk_branch rk3562_clk_pmu1_uart0_fracmux __initdata = + MUX(CLK_PMU1_UART0, "clk_pmu1_uart0", clk_pmu1_uart0_p, CLK_SET_RATE_PARENT, + RK3562_PMU1_CLKSEL_CON(2), 6, 2, MFLAGS); + +static struct rockchip_clk_branch rk3562_clk_branches[] __initdata = { + /* + * CRU Clock-Architecture + */ + /* PD_TOP */ + COMPOSITE(CLK_MATRIX_50M_SRC, "clk_matrix_50m_src", gpll_cpll_p, 0, + RK3562_CLKSEL_CON(0), 7, 1, MFLAGS, 0, 5, DFLAGS, + RK3562_CLKGATE_CON(0), 0, GFLAGS), + COMPOSITE(CLK_MATRIX_100M_SRC, "clk_matrix_100m_src", gpll_cpll_p, CLK_IS_CRITICAL, + RK3562_CLKSEL_CON(0), 15, 1, MFLAGS, 8, 4, DFLAGS, + RK3562_CLKGATE_CON(0), 1, GFLAGS), + COMPOSITE(CLK_MATRIX_125M_SRC, "clk_matrix_125m_src", gpll_cpll_p, 0, + RK3562_CLKSEL_CON(1), 7, 1, MFLAGS, 0, 4, DFLAGS, + RK3562_CLKGATE_CON(0), 2, GFLAGS), + COMPOSITE(CLK_MATRIX_200M_SRC, "clk_matrix_200m_src", gpll_cpll_p, CLK_IS_CRITICAL, + RK3562_CLKSEL_CON(2), 7, 1, MFLAGS, 0, 4, DFLAGS, + RK3562_CLKGATE_CON(0), 4, GFLAGS), + COMPOSITE(CLK_MATRIX_300M_SRC, "clk_matrix_300m_src", gpll_cpll_p, CLK_IS_CRITICAL, + RK3562_CLKSEL_CON(3), 7, 1, MFLAGS, 0, 4, DFLAGS, + RK3562_CLKGATE_CON(0), 6, GFLAGS), + COMPOSITE(ACLK_TOP, "aclk_top", gpll_cpll_p, CLK_IS_CRITICAL, + RK3562_CLKSEL_CON(5), 7, 1, MFLAGS, 0, 4, DFLAGS, + RK3562_CLKGATE_CON(1), 0, GFLAGS), + COMPOSITE(ACLK_TOP_VIO, "aclk_top_vio", gpll_cpll_p, 0, + RK3562_CLKSEL_CON(5), 15, 1, MFLAGS, 8, 4, DFLAGS, + RK3562_CLKGATE_CON(1), 1, GFLAGS), + COMPOSITE(CLK_24M_SSCSRC, "clk_24m_sscsrc", vpll_dmyhpll_gpll_cpll_p, 0, + RK3562_CLKSEL_CON(6), 6, 2, MFLAGS, 0, 6, DFLAGS, + RK3562_CLKGATE_CON(1), 9, GFLAGS), + COMPOSITE(CLK_CAM0_OUT2IO, "clk_cam0_out2io", gpll_cpll_xin24m_dmyapll_p, 0, + RK3562_CLKSEL_CON(8), 6, 2, MFLAGS, 0, 6, DFLAGS, + RK3562_CLKGATE_CON(1), 12, GFLAGS), + COMPOSITE(CLK_CAM1_OUT2IO, "clk_cam1_out2io", gpll_cpll_xin24m_dmyapll_p, 0, + RK3562_CLKSEL_CON(8), 14, 2, MFLAGS, 8, 6, DFLAGS, + RK3562_CLKGATE_CON(1), 13, GFLAGS), + COMPOSITE(CLK_CAM2_OUT2IO, "clk_cam2_out2io", gpll_cpll_xin24m_dmyapll_p, 0, + RK3562_CLKSEL_CON(9), 6, 2, MFLAGS, 0, 6, DFLAGS, + RK3562_CLKGATE_CON(1), 14, GFLAGS), + COMPOSITE(CLK_CAM3_OUT2IO, "clk_cam3_out2io", gpll_cpll_xin24m_dmyapll_p, 0, + RK3562_CLKSEL_CON(9), 14, 2, MFLAGS, 8, 6, DFLAGS, + RK3562_CLKGATE_CON(1), 15, GFLAGS), + FACTOR(0, "xin_osc0_half", "xin24m", 0, 1, 2), + + /* PD_BUS */ + COMPOSITE(ACLK_BUS, "aclk_bus", gpll_cpll_p, CLK_IS_CRITICAL, + RK3562_CLKSEL_CON(40), 7, 1, MFLAGS, 0, 5, DFLAGS, + RK3562_CLKGATE_CON(18), 0, GFLAGS), + COMPOSITE(HCLK_BUS, "hclk_bus", gpll_cpll_p, CLK_IS_CRITICAL, + RK3562_CLKSEL_CON(40), 15, 1, MFLAGS, 8, 6, DFLAGS, + RK3562_CLKGATE_CON(18), 1, GFLAGS), + COMPOSITE(PCLK_BUS, "pclk_bus", gpll_cpll_p, CLK_IS_CRITICAL, + RK3562_CLKSEL_CON(41), 7, 1, MFLAGS, 0, 5, DFLAGS, + RK3562_CLKGATE_CON(18), 2, GFLAGS), + GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus", 0, + RK3562_CLKGATE_CON(19), 0, GFLAGS), + GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus", 0, + RK3562_CLKGATE_CON(19), 1, GFLAGS), + GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus", 0, + RK3562_CLKGATE_CON(19), 2, GFLAGS), + GATE(PCLK_I2C4, "pclk_i2c4", "pclk_bus", 0, + RK3562_CLKGATE_CON(19), 3, GFLAGS), + GATE(PCLK_I2C5, "pclk_i2c5", "pclk_bus", 0, + RK3562_CLKGATE_CON(19), 4, GFLAGS), + COMPOSITE_NODIV(CLK_I2C, "clk_i2c", mux_200m_100m_50m_xin24m_p, 0, + RK3562_CLKSEL_CON(41), 8, 2, MFLAGS, + RK3562_CLKGATE_CON(19), 5, GFLAGS), + GATE(CLK_I2C1, "clk_i2c1", "clk_i2c", 0, + RK3562_CLKGATE_CON(19), 6, GFLAGS), + GATE(CLK_I2C2, "clk_i2c2", "clk_i2c", 0, + RK3562_CLKGATE_CON(19), 7, GFLAGS), + GATE(CLK_I2C3, "clk_i2c3", "clk_i2c", 0, + RK3562_CLKGATE_CON(19), 8, GFLAGS), + GATE(CLK_I2C4, "clk_i2c4", "clk_i2c", 0, + RK3562_CLKGATE_CON(19), 9, GFLAGS), + GATE(CLK_I2C5, "clk_i2c5", "clk_i2c", 0, + RK3562_CLKGATE_CON(19), 10, GFLAGS), + COMPOSITE_NODIV(DCLK_BUS_GPIO, "dclk_bus_gpio", mux_xin24m_32k_p, 0, + RK3562_CLKSEL_CON(41), 15, 1, MFLAGS, + RK3562_CLKGATE_CON(20), 4, GFLAGS), + GATE(DCLK_BUS_GPIO3, "dclk_bus_gpio3", "dclk_bus_gpio", 0, + RK3562_CLKGATE_CON(20), 5, GFLAGS), + GATE(DCLK_BUS_GPIO4, "dclk_bus_gpio4", "dclk_bus_gpio", 0, + RK3562_CLKGATE_CON(20), 6, GFLAGS), + GATE(PCLK_TIMER, "pclk_timer", "pclk_bus", 0, + RK3562_CLKGATE_CON(21), 0, GFLAGS), + GATE(CLK_TIMER0, "clk_timer0", "xin24m", 0, + RK3562_CLKGATE_CON(21), 1, GFLAGS), + GATE(CLK_TIMER1, "clk_timer1", "xin24m", 0, + RK3562_CLKGATE_CON(21), 2, GFLAGS), + GATE(CLK_TIMER2, "clk_timer2", "xin24m", 0, + RK3562_CLKGATE_CON(21), 3, GFLAGS), + GATE(CLK_TIMER3, "clk_timer3", "xin24m", 0, + RK3562_CLKGATE_CON(21), 4, GFLAGS), + GATE(CLK_TIMER4, "clk_timer4", "xin24m", 0, + RK3562_CLKGATE_CON(21), 5, GFLAGS), + GATE(CLK_TIMER5, "clk_timer5", "xin24m", 0, + RK3562_CLKGATE_CON(21), 6, GFLAGS), + GATE(PCLK_STIMER, "pclk_stimer", "pclk_bus", CLK_IGNORE_UNUSED, + RK3562_CLKGATE_CON(21), 7, GFLAGS), + GATE(CLK_STIMER0, "clk_stimer0", "xin24m", CLK_IGNORE_UNUSED, + RK3562_CLKGATE_CON(21), 8, GFLAGS), + GATE(CLK_STIMER1, "clk_stimer1", "xin24m", CLK_IGNORE_UNUSED, + RK3562_CLKGATE_CON(21), 9, GFLAGS), + GATE(PCLK_WDTNS, "pclk_wdtns", "pclk_bus", 0, + RK3562_CLKGATE_CON(22), 0, GFLAGS), + GATE(CLK_WDTNS, "clk_wdtns", "xin24m", 0, + RK3562_CLKGATE_CON(22), 1, GFLAGS), + GATE(PCLK_GRF, "pclk_grf", "pclk_bus", CLK_IGNORE_UNUSED, + RK3562_CLKGATE_CON(22), 2, GFLAGS), + GATE(PCLK_SGRF, "pclk_sgrf", "pclk_bus", CLK_IGNORE_UNUSED, + RK3562_CLKGATE_CON(22), 3, GFLAGS), + GATE(PCLK_MAILBOX, "pclk_mailbox", "pclk_bus", 0, + RK3562_CLKGATE_CON(22), 4, GFLAGS), + GATE(PCLK_INTC, "pclk_intc", "pclk_bus", 0, + RK3562_CLKGATE_CON(22), 5, GFLAGS), + GATE(ACLK_BUS_GIC400, "aclk_bus_gic400", "aclk_bus", CLK_IGNORE_UNUSED, + RK3562_CLKGATE_CON(22), 6, GFLAGS), + GATE(ACLK_BUS_SPINLOCK, "aclk_bus_spinlock", "aclk_bus", 0, + RK3562_CLKGATE_CON(23), 0, GFLAGS), + GATE(ACLK_DCF, "aclk_dcf", "aclk_bus", CLK_IGNORE_UNUSED, + RK3562_CLKGATE_CON(23), 1, GFLAGS), + GATE(PCLK_DCF, "pclk_dcf", "pclk_bus", CLK_IGNORE_UNUSED, + RK3562_CLKGATE_CON(23), 2, GFLAGS), + GATE(FCLK_BUS_CM0_CORE, "fclk_bus_cm0_core", "hclk_bus", 0, + RK3562_CLKGATE_CON(23), 3, GFLAGS), + GATE(CLK_BUS_CM0_RTC, "clk_bus_cm0_rtc", "clk_rtc_32k", 0, + RK3562_CLKGATE_CON(23), 4, GFLAGS), + GATE(HCLK_ICACHE, "hclk_icache", "hclk_bus", CLK_IGNORE_UNUSED, + RK3562_CLKGATE_CON(23), 8, GFLAGS), + GATE(HCLK_DCACHE, "hclk_dcache", "hclk_bus", CLK_IGNORE_UNUSED, + RK3562_CLKGATE_CON(23), 9, GFLAGS), + GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus", 0, + RK3562_CLKGATE_CON(24), 0, GFLAGS), + COMPOSITE_NOMUX(CLK_TSADC, "clk_tsadc", "xin24m", 0, + RK3562_CLKSEL_CON(43), 0, 11, DFLAGS, + RK3562_CLKGATE_CON(24), 1, GFLAGS), + COMPOSITE_NOMUX(CLK_TSADC_TSEN, "clk_tsadc_tsen", "xin24m", 0, + RK3562_CLKSEL_CON(43), 11, 5, DFLAGS, + RK3562_CLKGATE_CON(24), 3, GFLAGS), + GATE(PCLK_DFT2APB, "pclk_dft2apb", "pclk_bus", CLK_IGNORE_UNUSED, + RK3562_CLKGATE_CON(24), 4, GFLAGS), + COMPOSITE_NOMUX(CLK_SARADC_VCCIO156, "clk_saradc_vccio156", "xin24m", 0, + RK3562_CLKSEL_CON(44), 0, 12, DFLAGS, + RK3562_CLKGATE_CON(24), 9, GFLAGS), + GATE(PCLK_GMAC, "pclk_gmac", "pclk_bus", 0, + RK3562_CLKGATE_CON(25), 0, GFLAGS), + GATE(ACLK_GMAC, "aclk_gmac", "aclk_bus", 0, + RK3562_CLKGATE_CON(25), 1, GFLAGS), + COMPOSITE_NODIV(CLK_GMAC_125M_CRU_I, "clk_gmac_125m_cru_i", mux_125m_xin24m_p, 0, + RK3562_CLKSEL_CON(45), 8, 1, MFLAGS, + RK3562_CLKGATE_CON(25), 2, GFLAGS), + COMPOSITE_NODIV(CLK_GMAC_50M_CRU_I, "clk_gmac_50m_cru_i", mux_50m_xin24m_p, 0, + RK3562_CLKSEL_CON(45), 7, 1, MFLAGS, + RK3562_CLKGATE_CON(25), 3, GFLAGS), + COMPOSITE(CLK_GMAC_ETH_OUT2IO, "clk_gmac_eth_out2io", gpll_cpll_p, 0, + RK3562_CLKSEL_CON(46), 7, 1, MFLAGS, 0, 7, DFLAGS, + RK3562_CLKGATE_CON(25), 4, GFLAGS), + GATE(PCLK_APB2ASB_VCCIO156, "pclk_apb2asb_vccio156", "pclk_bus", CLK_IS_CRITICAL, + RK3562_CLKGATE_CON(25), 5, GFLAGS), + GATE(PCLK_TO_VCCIO156, "pclk_to_vccio156", "pclk_bus", CLK_IS_CRITICAL, + RK3562_CLKGATE_CON(25), 6, GFLAGS), + GATE(PCLK_DSIPHY, "pclk_dsiphy", "pclk_bus", 0, + RK3562_CLKGATE_CON(25), 8, GFLAGS), + GATE(PCLK_DSITX, "pclk_dsitx", "pclk_bus", 0, + RK3562_CLKGATE_CON(25), 9, GFLAGS), + GATE(PCLK_CPU_EMA_DET, "pclk_cpu_ema_det", "pclk_bus", CLK_IGNORE_UNUSED, + RK3562_CLKGATE_CON(25), 10, GFLAGS), + GATE(PCLK_HASH, "pclk_hash", "pclk_bus", 0, + RK3562_CLKGATE_CON(25), 11, GFLAGS), + GATE(PCLK_TOPCRU, "pclk_topcru", "pclk_bus", CLK_IGNORE_UNUSED, + RK3562_CLKGATE_CON(25), 15, GFLAGS), + GATE(PCLK_ASB2APB_VCCIO156, "pclk_asb2apb_vccio156", "pclk_to_vccio156", CLK_IS_CRITICAL, + RK3562_CLKGATE_CON(26), 0, GFLAGS), + GATE(PCLK_IOC_VCCIO156, "pclk_ioc_vccio156", "pclk_to_vccio156", CLK_IS_CRITICAL, + RK3562_CLKGATE_CON(26), 1, GFLAGS), + GATE(PCLK_GPIO3_VCCIO156, "pclk_gpio3_vccio156", "pclk_to_vccio156", 0, + RK3562_CLKGATE_CON(26), 2, GFLAGS), + GATE(PCLK_GPIO4_VCCIO156, "pclk_gpio4_vccio156", "pclk_to_vccio156", 0, + RK3562_CLKGATE_CON(26), 3, GFLAGS), + GATE(PCLK_SARADC_VCCIO156, "pclk_saradc_vccio156", "pclk_to_vccio156", 0, + RK3562_CLKGATE_CON(26), 4, GFLAGS), + GATE(PCLK_MAC100, "pclk_mac100", "pclk_bus", 0, + RK3562_CLKGATE_CON(27), 0, GFLAGS), + GATE(ACLK_MAC100, "aclk_mac100", "aclk_bus", 0, + RK3562_CLKGATE_CON(27), 1, GFLAGS), + COMPOSITE_NODIV(CLK_MAC100_50M_MATRIX, "clk_mac100_50m_matrix", mux_50m_xin24m_p, 0, + RK3562_CLKSEL_CON(47), 7, 1, MFLAGS, + RK3562_CLKGATE_CON(27), 2, GFLAGS), + + /* PD_CORE */ + COMPOSITE_NOMUX(0, "aclk_core_pre", "scmi_clk_cpu", CLK_IGNORE_UNUSED, + RK3562_CLKSEL_CON(11), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, + RK3562_CLKGATE_CON(4), 3, GFLAGS), + COMPOSITE_NOMUX(0, "pclk_dbg_pre", "scmi_clk_cpu", CLK_IGNORE_UNUSED, + RK3562_CLKSEL_CON(12), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, + RK3562_CLKGATE_CON(4), 5, GFLAGS), + COMPOSITE_NOMUX(HCLK_CORE, "hclk_core", "gpll", CLK_IS_CRITICAL, + RK3562_CLKSEL_CON(13), 0, 6, DFLAGS, + RK3562_CLKGATE_CON(5), 2, GFLAGS), + GATE(0, "pclk_dbg_daplite", "pclk_dbg_pre", CLK_IGNORE_UNUSED, + RK3562_CLKGATE_CON(4), 10, GFLAGS), + + /* PD_DDR */ + FACTOR_GATE(0, "clk_gpll_mux_to_ddr", "gpll", 0, 1, 4, + RK3328_CLKGATE_CON(1), 6, GFLAGS), + COMPOSITE_NOMUX(PCLK_DDR, "pclk_ddr", "clk_gpll_mux_to_ddr", CLK_IS_CRITICAL, + RK3562_DDR_CLKSEL_CON(1), 8, 5, DFLAGS, + RK3562_DDR_CLKGATE_CON(0), 3, GFLAGS), + COMPOSITE_NOMUX(CLK_MSCH_BRG_BIU, "clk_msch_brg_biu", "clk_gpll_mux_to_ddr", CLK_IS_CRITICAL, + RK3562_DDR_CLKSEL_CON(1), 0, 4, DFLAGS, + RK3562_DDR_CLKGATE_CON(0), 4, GFLAGS), + GATE(PCLK_DDR_HWLP, "pclk_ddr_hwlp", "pclk_ddr", CLK_IGNORE_UNUSED, + RK3562_DDR_CLKGATE_CON(0), 6, GFLAGS), + GATE(PCLK_DDR_UPCTL, "pclk_ddr_upctl", "pclk_ddr", CLK_IGNORE_UNUSED, + RK3562_DDR_CLKGATE_CON(0), 7, GFLAGS), + GATE(PCLK_DDR_PHY, "pclk_ddr_phy", "pclk_ddr", CLK_IGNORE_UNUSED, + RK3562_DDR_CLKGATE_CON(0), 8, GFLAGS), + GATE(PCLK_DDR_DFICTL, "pclk_ddr_dfictl", "pclk_ddr", CLK_IGNORE_UNUSED, + RK3562_DDR_CLKGATE_CON(0), 9, GFLAGS), + GATE(PCLK_DDR_DMA2DDR, "pclk_ddr_dma2ddr", "pclk_ddr", CLK_IGNORE_UNUSED, + RK3562_DDR_CLKGATE_CON(0), 10, GFLAGS), + GATE(PCLK_DDR_MON, "pclk_ddr_mon", "pclk_ddr", CLK_IGNORE_UNUSED, + RK3562_DDR_CLKGATE_CON(1), 0, GFLAGS), + GATE(TMCLK_DDR_MON, "tmclk_ddr_mon", "xin24m", CLK_IGNORE_UNUSED, + RK3562_DDR_CLKGATE_CON(1), 1, GFLAGS), + GATE(PCLK_DDR_GRF, "pclk_ddr_grf", "pclk_ddr", CLK_IGNORE_UNUSED, + RK3562_DDR_CLKGATE_CON(1), 2, GFLAGS), + GATE(PCLK_DDR_CRU, "pclk_ddr_cru", "pclk_ddr", CLK_IGNORE_UNUSED, + RK3562_DDR_CLKGATE_CON(1), 3, GFLAGS), + GATE(PCLK_SUBDDR_CRU, "pclk_subddr_cru", "pclk_ddr", CLK_IGNORE_UNUSED, + RK3562_DDR_CLKGATE_CON(1), 4, GFLAGS), + + /* PD_GPU */ + COMPOSITE(CLK_GPU_PRE, "clk_gpu_pre", gpll_cpll_p, 0, + RK3562_CLKSEL_CON(18), 7, 1, MFLAGS, 0, 4, DFLAGS, + RK3562_CLKGATE_CON(8), 0, GFLAGS), + COMPOSITE_NOMUX(ACLK_GPU_PRE, "aclk_gpu_pre", "clk_gpu_pre", 0, + RK3562_CLKSEL_CON(19), 0, 4, DFLAGS, + RK3562_CLKGATE_CON(8), 2, GFLAGS), + GATE(CLK_GPU, "clk_gpu", "clk_gpu_pre", 0, + RK3562_CLKGATE_CON(8), 4, GFLAGS), + COMPOSITE_NODIV(CLK_GPU_BRG, "clk_gpu_brg", mux_200m_100m_p, 0, + RK3562_CLKSEL_CON(19), 15, 1, MFLAGS, + RK3562_CLKGATE_CON(8), 8, GFLAGS), + + /* PD_NPU */ + COMPOSITE(CLK_NPU_PRE, "clk_npu_pre", gpll_cpll_p, 0, + RK3562_CLKSEL_CON(15), 7, 1, MFLAGS, 0, 4, DFLAGS, + RK3562_CLKGATE_CON(6), 0, GFLAGS), + COMPOSITE_NOMUX(HCLK_NPU_PRE, "hclk_npu_pre", "clk_npu_pre", 0, + RK3562_CLKSEL_CON(16), 0, 4, DFLAGS, + RK3562_CLKGATE_CON(6), 1, GFLAGS), + GATE(ACLK_RKNN, "aclk_rknn", "clk_npu_pre", 0, + RK3562_CLKGATE_CON(6), 4, GFLAGS), + GATE(HCLK_RKNN, "hclk_rknn", "hclk_npu_pre", 0, + RK3562_CLKGATE_CON(6), 5, GFLAGS), + + /* PD_PERI */ + COMPOSITE(ACLK_PERI, "aclk_peri", gpll_cpll_p, CLK_IS_CRITICAL, + RK3562_PERI_CLKSEL_CON(0), 7, 1, MFLAGS, 0, 5, DFLAGS, + RK3562_PERI_CLKGATE_CON(1), 0, GFLAGS), + COMPOSITE(HCLK_PERI, "hclk_peri", gpll_cpll_p, CLK_IS_CRITICAL, + RK3562_PERI_CLKSEL_CON(0), 15, 1, MFLAGS, 8, 6, DFLAGS, + RK3562_PERI_CLKGATE_CON(1), 1, GFLAGS), + COMPOSITE(PCLK_PERI, "pclk_peri", gpll_cpll_p, CLK_IS_CRITICAL, + RK3562_PERI_CLKSEL_CON(1), 7, 1, MFLAGS, 0, 5, DFLAGS, + RK3562_PERI_CLKGATE_CON(1), 2, GFLAGS), + GATE(PCLK_PERICRU, "pclk_pericru", "pclk_peri", CLK_IGNORE_UNUSED, + RK3562_PERI_CLKGATE_CON(1), 6, GFLAGS), + GATE(HCLK_SAI0, "hclk_sai0", "hclk_peri", 0, + RK3562_PERI_CLKGATE_CON(2), 0, GFLAGS), + COMPOSITE(CLK_SAI0_SRC, "clk_sai0_src", gpll_cpll_hpll_p, 0, + RK3562_PERI_CLKSEL_CON(1), 14, 2, MFLAGS, 8, 6, DFLAGS, + RK3562_PERI_CLKGATE_CON(2), 1, GFLAGS), + COMPOSITE_FRACMUX(CLK_SAI0_FRAC, "clk_sai0_frac", "clk_sai0_src", CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(2), 0, + RK3562_PERI_CLKGATE_CON(2), 2, GFLAGS, + &rk3562_clk_sai0_fracmux), + GATE(MCLK_SAI0, "mclk_sai0", "clk_sai0", 0, + RK3562_PERI_CLKGATE_CON(2), 3, GFLAGS), + COMPOSITE_NODIV(MCLK_SAI0_OUT2IO, "mclk_sai0_out2io", mclk_sai0_out2io_p, CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(3), 5, 1, MFLAGS, + RK3562_PERI_CLKGATE_CON(2), 4, GFLAGS), + GATE(HCLK_SAI1, "hclk_sai1", "hclk_peri", 0, + RK3562_PERI_CLKGATE_CON(2), 5, GFLAGS), + COMPOSITE(CLK_SAI1_SRC, "clk_sai1_src", gpll_cpll_hpll_p, 0, + RK3562_PERI_CLKSEL_CON(3), 14, 2, MFLAGS, 8, 6, DFLAGS, + RK3562_PERI_CLKGATE_CON(2), 6, GFLAGS), + COMPOSITE_FRACMUX(CLK_SAI1_FRAC, "clk_sai1_frac", "clk_sai1_src", CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(4), 0, + RK3562_PERI_CLKGATE_CON(2), 7, GFLAGS, + &rk3562_clk_sai1_fracmux), + GATE(MCLK_SAI1, "mclk_sai1", "clk_sai1", 0, + RK3562_PERI_CLKGATE_CON(2), 8, GFLAGS), + COMPOSITE_NODIV(MCLK_SAI1_OUT2IO, "mclk_sai1_out2io", mclk_sai1_out2io_p, CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(5), 5, 1, MFLAGS, + RK3562_PERI_CLKGATE_CON(2), 9, GFLAGS), + GATE(HCLK_SAI2, "hclk_sai2", "hclk_peri", 0, + RK3562_PERI_CLKGATE_CON(2), 10, GFLAGS), + COMPOSITE(CLK_SAI2_SRC, "clk_sai2_src", gpll_cpll_hpll_p, 0, + RK3562_PERI_CLKSEL_CON(6), 14, 2, MFLAGS, 8, 6, DFLAGS, + RK3562_PERI_CLKGATE_CON(2), 11, GFLAGS), + COMPOSITE_FRACMUX(CLK_SAI2_FRAC, "clk_sai2_frac", "clk_sai2_src", CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(7), 0, + RK3562_PERI_CLKGATE_CON(2), 12, GFLAGS, + &rk3562_clk_sai2_fracmux), + GATE(MCLK_SAI2, "mclk_sai2", "clk_sai2", 0, + RK3562_PERI_CLKGATE_CON(2), 13, GFLAGS), + COMPOSITE_NODIV(MCLK_SAI2_OUT2IO, "mclk_sai2_out2io", mclk_sai2_out2io_p, CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(8), 5, 1, MFLAGS, + RK3562_PERI_CLKGATE_CON(2), 14, GFLAGS), + GATE(HCLK_DSM, "hclk_dsm", "hclk_peri", 0, + RK3562_PERI_CLKGATE_CON(3), 1, GFLAGS), + GATE(CLK_DSM, "clk_dsm", "mclk_sai1", 0, + RK3562_PERI_CLKGATE_CON(3), 2, GFLAGS), + GATE(HCLK_PDM, "hclk_pdm", "hclk_peri", 0, + RK3562_PERI_CLKGATE_CON(3), 4, GFLAGS), + COMPOSITE(MCLK_PDM, "mclk_pdm", gpll_cpll_hpll_xin24m_p, 0, + RK3562_PERI_CLKSEL_CON(12), 6, 2, MFLAGS, 0, 5, DFLAGS, + RK3562_PERI_CLKGATE_CON(3), 5, GFLAGS), + GATE(HCLK_SPDIF, "hclk_spdif", "hclk_peri", 0, + RK3562_PERI_CLKGATE_CON(3), 8, GFLAGS), + COMPOSITE(CLK_SPDIF_SRC, "clk_spdif_src", gpll_cpll_hpll_p, 0, + RK3562_PERI_CLKSEL_CON(13), 14, 2, MFLAGS, 8, 6, DFLAGS, + RK3562_PERI_CLKGATE_CON(3), 9, GFLAGS), + COMPOSITE_FRACMUX(CLK_SPDIF_FRAC, "clk_spdif_frac", "clk_spdif_src", CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(14), 0, + RK3562_PERI_CLKGATE_CON(3), 10, GFLAGS, + &rk3562_clk_spdif_fracmux), + GATE(MCLK_SPDIF, "mclk_spdif", "clk_spdif", 0, + RK3562_PERI_CLKGATE_CON(3), 11, GFLAGS), + GATE(HCLK_SDMMC0, "hclk_sdmmc0", "hclk_peri", 0, + RK3562_PERI_CLKGATE_CON(4), 0, GFLAGS), + COMPOSITE(CCLK_SDMMC0, "cclk_sdmmc0", gpll_cpll_xin24m_dmyhpll_p, 0, + RK3562_PERI_CLKSEL_CON(16), 14, 2, MFLAGS, 0, 8, DFLAGS, + RK3562_PERI_CLKGATE_CON(4), 1, GFLAGS), + MMC(SCLK_SDMMC0_DRV, "sdmmc0_drv", "cclk_sdmmc0", RK3562_SDMMC0_CON0, 1), + MMC(SCLK_SDMMC0_SAMPLE, "sdmmc0_sample", "cclk_sdmmc0", RK3562_SDMMC0_CON1, 1), + GATE(HCLK_SDMMC1, "hclk_sdmmc1", "hclk_peri", 0, + RK3562_PERI_CLKGATE_CON(4), 2, GFLAGS), + COMPOSITE(CCLK_SDMMC1, "cclk_sdmmc1", gpll_cpll_xin24m_dmyhpll_p, 0, + RK3562_PERI_CLKSEL_CON(17), 14, 2, MFLAGS, 0, 8, DFLAGS, + RK3562_PERI_CLKGATE_CON(4), 3, GFLAGS), + MMC(SCLK_SDMMC1_DRV, "sdmmc1_drv", "cclk_sdmmc1", RK3562_SDMMC1_CON0, 1), + MMC(SCLK_SDMMC1_SAMPLE, "sdmmc1_sample", "cclk_sdmmc1", RK3562_SDMMC1_CON1, 1), + GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, + RK3562_PERI_CLKGATE_CON(4), 8, GFLAGS), + GATE(ACLK_EMMC, "aclk_emmc", "aclk_peri", 0, + RK3562_PERI_CLKGATE_CON(4), 9, GFLAGS), + COMPOSITE(CCLK_EMMC, "cclk_emmc", gpll_cpll_xin24m_dmyhpll_p, 0, + RK3562_PERI_CLKSEL_CON(18), 14, 2, MFLAGS, 0, 8, DFLAGS, + RK3562_PERI_CLKGATE_CON(4), 10, GFLAGS), + COMPOSITE(BCLK_EMMC, "bclk_emmc", gpll_cpll_p, 0, + RK3562_PERI_CLKSEL_CON(19), 15, 1, MFLAGS, 8, 7, DFLAGS, + RK3562_PERI_CLKGATE_CON(4), 11, GFLAGS), + GATE(TMCLK_EMMC, "tmclk_emmc", "xin24m", 0, + RK3562_PERI_CLKGATE_CON(4), 12, GFLAGS), + COMPOSITE(SCLK_SFC, "sclk_sfc", gpll_cpll_xin24m_p, 0, + RK3562_PERI_CLKSEL_CON(20), 8, 2, MFLAGS, 0, 8, DFLAGS, + RK3562_PERI_CLKGATE_CON(4), 13, GFLAGS), + GATE(HCLK_SFC, "hclk_sfc", "hclk_peri", 0, + RK3562_PERI_CLKGATE_CON(4), 14, GFLAGS), + GATE(HCLK_USB2HOST, "hclk_usb2host", "hclk_peri", 0, + RK3562_PERI_CLKGATE_CON(5), 0, GFLAGS), + GATE(HCLK_USB2HOST_ARB, "hclk_usb2host_arb", "hclk_peri", 0, + RK3562_PERI_CLKGATE_CON(5), 1, GFLAGS), + GATE(PCLK_SPI1, "pclk_spi1", "pclk_peri", 0, + RK3562_PERI_CLKGATE_CON(6), 0, GFLAGS), + COMPOSITE_NODIV(CLK_SPI1, "clk_spi1", mux_200m_100m_50m_xin24m_p, 0, + RK3562_PERI_CLKSEL_CON(20), 12, 2, MFLAGS, + RK3562_PERI_CLKGATE_CON(6), 1, GFLAGS), + GATE(SCLK_IN_SPI1, "sclk_in_spi1", "sclk_in_spi1_io", 0, + RK3562_PERI_CLKGATE_CON(6), 2, GFLAGS), + GATE(PCLK_SPI2, "pclk_spi2", "pclk_peri", 0, + RK3562_PERI_CLKGATE_CON(6), 3, GFLAGS), + COMPOSITE_NODIV(CLK_SPI2, "clk_spi2", mux_200m_100m_50m_xin24m_p, 0, + RK3562_PERI_CLKSEL_CON(20), 14, 2, MFLAGS, + RK3562_PERI_CLKGATE_CON(6), 4, GFLAGS), + GATE(SCLK_IN_SPI2, "sclk_in_spi2", "sclk_in_spi2_io", 0, + RK3562_PERI_CLKGATE_CON(6), 5, GFLAGS), + GATE(PCLK_UART1, "pclk_uart1", "pclk_peri", 0, + RK3562_PERI_CLKGATE_CON(7), 0, GFLAGS), + GATE(PCLK_UART2, "pclk_uart2", "pclk_peri", 0, + RK3562_PERI_CLKGATE_CON(7), 1, GFLAGS), + GATE(PCLK_UART3, "pclk_uart3", "pclk_peri", 0, + RK3562_PERI_CLKGATE_CON(7), 2, GFLAGS), + GATE(PCLK_UART4, "pclk_uart4", "pclk_peri", 0, + RK3562_PERI_CLKGATE_CON(7), 3, GFLAGS), + GATE(PCLK_UART5, "pclk_uart5", "pclk_peri", 0, + RK3562_PERI_CLKGATE_CON(7), 4, GFLAGS), + GATE(PCLK_UART6, "pclk_uart6", "pclk_peri", 0, + RK3562_PERI_CLKGATE_CON(7), 5, GFLAGS), + GATE(PCLK_UART7, "pclk_uart7", "pclk_peri", 0, + RK3562_PERI_CLKGATE_CON(7), 6, GFLAGS), + GATE(PCLK_UART8, "pclk_uart8", "pclk_peri", 0, + RK3562_PERI_CLKGATE_CON(7), 7, GFLAGS), + GATE(PCLK_UART9, "pclk_uart9", "pclk_peri", 0, + RK3562_PERI_CLKGATE_CON(7), 8, GFLAGS), + COMPOSITE(CLK_UART1_SRC, "clk_uart1_src", gpll_cpll_p, 0, + RK3562_PERI_CLKSEL_CON(21), 8, 1, MFLAGS, 0, 7, DFLAGS, + RK3562_PERI_CLKGATE_CON(7), 9, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART1_FRAC, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(22), 0, + RK3562_PERI_CLKGATE_CON(7), 10, GFLAGS, + &rk3562_clk_uart1_fracmux), + GATE(SCLK_UART1, "sclk_uart1", "clk_uart1", 0, + RK3562_PERI_CLKGATE_CON(7), 11, GFLAGS), + COMPOSITE(CLK_UART2_SRC, "clk_uart2_src", gpll_cpll_p, 0, + RK3562_PERI_CLKSEL_CON(23), 8, 1, MFLAGS, 0, 7, DFLAGS, + RK3562_PERI_CLKGATE_CON(7), 12, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART2_FRAC, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(24), 0, + RK3562_PERI_CLKGATE_CON(7), 13, GFLAGS, + &rk3562_clk_uart2_fracmux), + GATE(SCLK_UART2, "sclk_uart2", "clk_uart2", 0, + RK3562_PERI_CLKGATE_CON(7), 14, GFLAGS), + COMPOSITE(CLK_UART3_SRC, "clk_uart3_src", gpll_cpll_p, 0, + RK3562_PERI_CLKSEL_CON(25), 8, 1, MFLAGS, 0, 7, DFLAGS, + RK3562_PERI_CLKGATE_CON(7), 15, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART3_FRAC, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(26), 0, + RK3562_PERI_CLKGATE_CON(8), 0, GFLAGS, + &rk3562_clk_uart3_fracmux), + GATE(SCLK_UART3, "sclk_uart3", "clk_uart3", 0, + RK3562_PERI_CLKGATE_CON(8), 1, GFLAGS), + COMPOSITE(CLK_UART4_SRC, "clk_uart4_src", gpll_cpll_p, 0, + RK3562_PERI_CLKSEL_CON(27), 8, 1, MFLAGS, 0, 7, DFLAGS, + RK3562_PERI_CLKGATE_CON(8), 2, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART4_FRAC, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(28), 0, + RK3562_PERI_CLKGATE_CON(8), 3, GFLAGS, + &rk3562_clk_uart4_fracmux), + GATE(SCLK_UART4, "sclk_uart4", "clk_uart4", 0, + RK3562_PERI_CLKGATE_CON(8), 4, GFLAGS), + COMPOSITE(CLK_UART5_SRC, "clk_uart5_src", gpll_cpll_p, 0, + RK3562_PERI_CLKSEL_CON(29), 8, 1, MFLAGS, 0, 7, DFLAGS, + RK3562_PERI_CLKGATE_CON(8), 5, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART5_FRAC, "clk_uart5_frac", "clk_uart5_src", CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(30), 0, + RK3562_PERI_CLKGATE_CON(8), 6, GFLAGS, + &rk3562_clk_uart5_fracmux), + GATE(SCLK_UART5, "sclk_uart5", "clk_uart5", 0, + RK3562_PERI_CLKGATE_CON(8), 7, GFLAGS), + COMPOSITE(CLK_UART6_SRC, "clk_uart6_src", gpll_cpll_p, 0, + RK3562_PERI_CLKSEL_CON(31), 8, 1, MFLAGS, 0, 7, DFLAGS, + RK3562_PERI_CLKGATE_CON(8), 8, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART6_FRAC, "clk_uart6_frac", "clk_uart6_src", CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(32), 0, + RK3562_PERI_CLKGATE_CON(8), 9, GFLAGS, + &rk3562_clk_uart6_fracmux), + GATE(SCLK_UART6, "sclk_uart6", "clk_uart6", 0, + RK3562_PERI_CLKGATE_CON(8), 10, GFLAGS), + COMPOSITE(CLK_UART7_SRC, "clk_uart7_src", gpll_cpll_p, 0, + RK3562_PERI_CLKSEL_CON(33), 8, 1, MFLAGS, 0, 7, DFLAGS, + RK3562_PERI_CLKGATE_CON(8), 11, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART7_FRAC, "clk_uart7_frac", "clk_uart7_src", CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(34), 0, + RK3562_PERI_CLKGATE_CON(8), 12, GFLAGS, + &rk3562_clk_uart7_fracmux), + GATE(SCLK_UART7, "sclk_uart7", "clk_uart7", 0, + RK3562_PERI_CLKGATE_CON(8), 13, GFLAGS), + COMPOSITE(CLK_UART8_SRC, "clk_uart8_src", gpll_cpll_p, 0, + RK3562_PERI_CLKSEL_CON(35), 8, 1, MFLAGS, 0, 7, DFLAGS, + RK3562_PERI_CLKGATE_CON(8), 14, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART8_FRAC, "clk_uart8_frac", "clk_uart8_src", CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(36), 0, + RK3562_PERI_CLKGATE_CON(8), 15, GFLAGS, + &rk3562_clk_uart8_fracmux), + GATE(SCLK_UART8, "sclk_uart8", "clk_uart8", 0, + RK3562_PERI_CLKGATE_CON(9), 0, GFLAGS), + COMPOSITE(CLK_UART9_SRC, "clk_uart9_src", gpll_cpll_p, 0, + RK3562_PERI_CLKSEL_CON(37), 8, 1, MFLAGS, 0, 7, DFLAGS, + RK3562_PERI_CLKGATE_CON(9), 1, GFLAGS), + COMPOSITE_FRACMUX(CLK_UART9_FRAC, "clk_uart9_frac", "clk_uart9_src", CLK_SET_RATE_PARENT, + RK3562_PERI_CLKSEL_CON(38), 0, + RK3562_PERI_CLKGATE_CON(9), 2, GFLAGS, + &rk3562_clk_uart9_fracmux), + GATE(SCLK_UART9, "sclk_uart9", "clk_uart9", 0, + RK3562_PERI_CLKGATE_CON(9), 3, GFLAGS), + GATE(PCLK_PWM1_PERI, "pclk_pwm1_peri", "pclk_peri", 0, + RK3562_PERI_CLKGATE_CON(10), 0, GFLAGS), + COMPOSITE_NODIV(CLK_PWM1_PERI, "clk_pwm1_peri", mux_100m_50m_xin24m_p, 0, + RK3562_PERI_CLKSEL_CON(40), 0, 2, MFLAGS, + RK3562_PERI_CLKGATE_CON(10), 1, GFLAGS), + GATE(CLK_CAPTURE_PWM1_PERI, "clk_capture_pwm1_peri", "xin24m", 0, + RK3562_PERI_CLKGATE_CON(10), 2, GFLAGS), + GATE(PCLK_PWM2_PERI, "pclk_pwm2_peri", "pclk_peri", 0, + RK3562_PERI_CLKGATE_CON(10), 3, GFLAGS), + COMPOSITE_NODIV(CLK_PWM2_PERI, "clk_pwm2_peri", mux_100m_50m_xin24m_p, 0, + RK3562_PERI_CLKSEL_CON(40), 6, 2, MFLAGS, + RK3562_PERI_CLKGATE_CON(10), 4, GFLAGS), + GATE(CLK_CAPTURE_PWM2_PERI, "clk_capture_pwm2_peri", "xin24m", 0, + RK3562_PERI_CLKGATE_CON(10), 5, GFLAGS), + GATE(PCLK_PWM3_PERI, "pclk_pwm3_peri", "pclk_peri", 0, + RK3562_PERI_CLKGATE_CON(10), 6, GFLAGS), + COMPOSITE_NODIV(CLK_PWM3_PERI, "clk_pwm3_peri", mux_100m_50m_xin24m_p, 0, + RK3562_PERI_CLKSEL_CON(40), 8, 2, MFLAGS, + RK3562_PERI_CLKGATE_CON(10), 7, GFLAGS), + GATE(CLK_CAPTURE_PWM3_PERI, "clk_capture_pwm3_peri", "xin24m", 0, + RK3562_PERI_CLKGATE_CON(10), 8, GFLAGS), + GATE(PCLK_CAN0, "pclk_can0", "pclk_peri", 0, + RK3562_PERI_CLKGATE_CON(11), 0, GFLAGS), + COMPOSITE(CLK_CAN0, "clk_can0", gpll_cpll_p, 0, + RK3562_PERI_CLKSEL_CON(41), 7, 1, MFLAGS, 0, 5, DFLAGS, + RK3562_PERI_CLKGATE_CON(11), 1, GFLAGS), + GATE(PCLK_CAN1, "pclk_can1", "pclk_peri", 0, + RK3562_PERI_CLKGATE_CON(11), 2, GFLAGS), + COMPOSITE(CLK_CAN1, "clk_can1", gpll_cpll_p, 0, + RK3562_PERI_CLKSEL_CON(41), 15, 1, MFLAGS, 8, 5, DFLAGS, + RK3562_PERI_CLKGATE_CON(11), 3, GFLAGS), + GATE(PCLK_PERI_WDT, "pclk_peri_wdt", "pclk_peri", 0, + RK3562_PERI_CLKGATE_CON(13), 0, GFLAGS), + COMPOSITE_NODIV(TCLK_PERI_WDT, "tclk_peri_wdt", mux_xin24m_32k_p, 0, + RK3562_PERI_CLKSEL_CON(43), 15, 1, MFLAGS, + RK3562_PERI_CLKGATE_CON(13), 1, GFLAGS), + GATE(ACLK_SYSMEM, "aclk_sysmem", "aclk_peri", CLK_IGNORE_UNUSED, + RK3562_PERI_CLKGATE_CON(13), 2, GFLAGS), + GATE(HCLK_BOOTROM, "hclk_bootrom", "hclk_peri", CLK_IGNORE_UNUSED, + RK3562_PERI_CLKGATE_CON(13), 3, GFLAGS), + GATE(PCLK_PERI_GRF, "pclk_peri_grf", "pclk_peri", CLK_IGNORE_UNUSED, + RK3562_PERI_CLKGATE_CON(13), 4, GFLAGS), + GATE(ACLK_DMAC, "aclk_dmac", "aclk_peri", 0, + RK3562_PERI_CLKGATE_CON(13), 5, GFLAGS), + GATE(ACLK_RKDMAC, "aclk_rkdmac", "aclk_peri", 0, + RK3562_PERI_CLKGATE_CON(13), 6, GFLAGS), + GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "pclk_peri", 0, + RK3562_PERI_CLKGATE_CON(14), 0, GFLAGS), + GATE(CLK_SBPI_OTPC_NS, "clk_sbpi_otpc_ns", "xin24m", 0, + RK3562_PERI_CLKGATE_CON(14), 1, GFLAGS), + COMPOSITE_NOMUX(CLK_USER_OTPC_NS, "clk_user_otpc_ns", "xin24m", 0, + RK3562_PERI_CLKSEL_CON(44), 0, 8, DFLAGS, + RK3562_PERI_CLKGATE_CON(14), 2, GFLAGS), + GATE(PCLK_OTPC_S, "pclk_otpc_s", "pclk_peri", CLK_IGNORE_UNUSED, + RK3562_PERI_CLKGATE_CON(14), 3, GFLAGS), + GATE(CLK_SBPI_OTPC_S, "clk_sbpi_otpc_s", "xin24m", CLK_IGNORE_UNUSED, + RK3562_PERI_CLKGATE_CON(14), 4, GFLAGS), + COMPOSITE_NOMUX(CLK_USER_OTPC_S, "clk_user_otpc_s", "xin24m", CLK_IGNORE_UNUSED, + RK3562_PERI_CLKSEL_CON(44), 8, 8, DFLAGS, + RK3562_PERI_CLKGATE_CON(14), 5, GFLAGS), + GATE(CLK_OTPC_ARB, "clk_otpc_arb", "xin24m", 0, + RK3562_PERI_CLKGATE_CON(14), 6, GFLAGS), + GATE(PCLK_OTPPHY, "pclk_otpphy", "pclk_peri", 0, + RK3562_PERI_CLKGATE_CON(14), 7, GFLAGS), + GATE(PCLK_USB2PHY, "pclk_usb2phy", "pclk_peri", 0, + RK3562_PERI_CLKGATE_CON(15), 0, GFLAGS), + GATE(PCLK_PIPEPHY, "pclk_pipephy", "pclk_peri", 0, + RK3562_PERI_CLKGATE_CON(15), 7, GFLAGS), + GATE(PCLK_SARADC, "pclk_saradc", "pclk_peri", 0, + RK3562_PERI_CLKGATE_CON(16), 4, GFLAGS), + COMPOSITE_NOMUX(CLK_SARADC, "clk_saradc", "xin24m", 0, + RK3562_PERI_CLKSEL_CON(46), 0, 12, DFLAGS, + RK3562_PERI_CLKGATE_CON(16), 5, GFLAGS), + GATE(PCLK_IOC_VCCIO234, "pclk_ioc_vccio234", "pclk_peri", CLK_IS_CRITICAL, + RK3562_PERI_CLKGATE_CON(16), 12, GFLAGS), + GATE(PCLK_PERI_GPIO1, "pclk_peri_gpio1", "pclk_peri", 0, + RK3562_PERI_CLKGATE_CON(17), 0, GFLAGS), + GATE(PCLK_PERI_GPIO2, "pclk_peri_gpio2", "pclk_peri", 0, + RK3562_PERI_CLKGATE_CON(17), 1, GFLAGS), + COMPOSITE_NODIV(DCLK_PERI_GPIO, "dclk_peri_gpio", mux_xin24m_32k_p, 0, + RK3562_PERI_CLKSEL_CON(47), 8, 1, MFLAGS, + RK3562_PERI_CLKGATE_CON(17), 4, GFLAGS), + GATE(DCLK_PERI_GPIO1, "dclk_peri_gpio1", "dclk_peri_gpio", 0, + RK3562_PERI_CLKGATE_CON(17), 2, GFLAGS), + GATE(DCLK_PERI_GPIO2, "dclk_peri_gpio2", "dclk_peri_gpio", 0, + RK3562_PERI_CLKGATE_CON(17), 3, GFLAGS), + + /* PD_PHP */ + COMPOSITE(ACLK_PHP, "aclk_php", gpll_cpll_p, 0, + RK3562_CLKSEL_CON(36), 7, 1, MFLAGS, 0, 4, DFLAGS, + RK3562_CLKGATE_CON(16), 0, GFLAGS), + COMPOSITE_NOMUX(PCLK_PHP, "pclk_php", "aclk_php", 0, + RK3562_CLKSEL_CON(36), 8, 4, DFLAGS, + RK3562_CLKGATE_CON(16), 1, GFLAGS), + GATE(ACLK_PCIE20_MST, "aclk_pcie20_mst", "aclk_php", 0, + RK3562_CLKGATE_CON(16), 4, GFLAGS), + GATE(ACLK_PCIE20_SLV, "aclk_pcie20_slv", "aclk_php", 0, + RK3562_CLKGATE_CON(16), 5, GFLAGS), + GATE(ACLK_PCIE20_DBI, "aclk_pcie20_dbi", "aclk_php", 0, + RK3562_CLKGATE_CON(16), 6, GFLAGS), + GATE(PCLK_PCIE20, "pclk_pcie20", "pclk_php", 0, + RK3562_CLKGATE_CON(16), 7, GFLAGS), + GATE(CLK_PCIE20_AUX, "clk_pcie20_aux", "xin24m", 0, + RK3562_CLKGATE_CON(16), 8, GFLAGS), + GATE(ACLK_USB3OTG, "aclk_usb3otg", "aclk_php", 0, + RK3562_CLKGATE_CON(16), 10, GFLAGS), + COMPOSITE_NODIV(CLK_USB3OTG_SUSPEND, "clk_usb3otg_suspend", mux_xin24m_32k_p, 0, + RK3562_CLKSEL_CON(36), 15, 1, MFLAGS, + RK3562_CLKGATE_CON(16), 11, GFLAGS), + GATE(CLK_USB3OTG_REF, "clk_usb3otg_ref", "xin24m", 0, + RK3562_CLKGATE_CON(16), 12, GFLAGS), + GATE(CLK_PIPEPHY_REF_FUNC, "clk_pipephy_ref_func", "pclk_pcie20", 0, + RK3562_CLKGATE_CON(17), 3, GFLAGS), + + /* PD_PMU1 */ + COMPOSITE_NOMUX(CLK_200M_PMU, "clk_200m_pmu", "cpll", CLK_IS_CRITICAL, + RK3562_PMU1_CLKSEL_CON(0), 0, 5, DFLAGS, + RK3562_PMU1_CLKGATE_CON(0), 1, GFLAGS), + /* PD_PMU0 */ + COMPOSITE_FRACMUX(CLK_RTC32K_FRAC, "clk_rtc32k_frac", "xin24m", CLK_IS_CRITICAL, + RK3562_PMU0_CLKSEL_CON(0), 0, + RK3562_PMU0_CLKGATE_CON(0), 15, GFLAGS, + &rk3562_rtc32k_pmu_fracmux), + COMPOSITE_NOMUX(BUSCLK_PDPMU0, "busclk_pdpmu0", "clk_200m_pmu", CLK_IS_CRITICAL, + RK3562_PMU0_CLKSEL_CON(1), 3, 2, DFLAGS, + RK3562_PMU0_CLKGATE_CON(0), 14, GFLAGS), + GATE(PCLK_PMU0_CRU, "pclk_pmu0_cru", "busclk_pdpmu0", CLK_IGNORE_UNUSED, + RK3562_PMU0_CLKGATE_CON(0), 0, GFLAGS), + GATE(PCLK_PMU0_PMU, "pclk_pmu0_pmu", "busclk_pdpmu0", CLK_IGNORE_UNUSED, + RK3562_PMU0_CLKGATE_CON(0), 1, GFLAGS), + GATE(CLK_PMU0_PMU, "clk_pmu0_pmu", "xin24m", CLK_IGNORE_UNUSED, + RK3562_PMU0_CLKGATE_CON(0), 2, GFLAGS), + GATE(PCLK_PMU0_HP_TIMER, "pclk_pmu0_hp_timer", "busclk_pdpmu0", CLK_IGNORE_UNUSED, + RK3562_PMU0_CLKGATE_CON(0), 3, GFLAGS), + GATE(CLK_PMU0_HP_TIMER, "clk_pmu0_hp_timer", "xin24m", CLK_IGNORE_UNUSED, + RK3562_PMU0_CLKGATE_CON(0), 4, GFLAGS), + GATE(CLK_PMU0_32K_HP_TIMER, "clk_pmu0_32k_hp_timer", "clk_rtc_32k", CLK_IGNORE_UNUSED, + RK3562_PMU0_CLKGATE_CON(0), 5, GFLAGS), + GATE(PCLK_PMU0_PVTM, "pclk_pmu0_pvtm", "busclk_pdpmu0", 0, + RK3562_PMU0_CLKGATE_CON(0), 6, GFLAGS), + GATE(CLK_PMU0_PVTM, "clk_pmu0_pvtm", "xin24m", 0, + RK3562_PMU0_CLKGATE_CON(0), 7, GFLAGS), + GATE(PCLK_IOC_PMUIO, "pclk_ioc_pmuio", "busclk_pdpmu0", CLK_IS_CRITICAL, + RK3562_PMU0_CLKGATE_CON(0), 8, GFLAGS), + GATE(PCLK_PMU0_GPIO0, "pclk_pmu0_gpio0", "busclk_pdpmu0", 0, + RK3562_PMU0_CLKGATE_CON(0), 9, GFLAGS), + GATE(DBCLK_PMU0_GPIO0, "dbclk_pmu0_gpio0", "xin24m", 0, + RK3562_PMU0_CLKGATE_CON(0), 10, GFLAGS), + GATE(PCLK_PMU0_GRF, "pclk_pmu0_grf", "busclk_pdpmu0", CLK_IGNORE_UNUSED, + RK3562_PMU0_CLKGATE_CON(0), 11, GFLAGS), + GATE(PCLK_PMU0_SGRF, "pclk_pmu0_sgrf", "busclk_pdpmu0", CLK_IGNORE_UNUSED, + RK3562_PMU0_CLKGATE_CON(0), 12, GFLAGS), + GATE(CLK_DDR_FAIL_SAFE, "clk_ddr_fail_safe", "xin24m", CLK_IGNORE_UNUSED, + RK3562_PMU0_CLKGATE_CON(1), 0, GFLAGS), + GATE(PCLK_PMU0_SCRKEYGEN, "pclk_pmu0_scrkeygen", "busclk_pdpmu0", CLK_IGNORE_UNUSED, + RK3562_PMU0_CLKGATE_CON(1), 1, GFLAGS), + COMPOSITE_NOMUX(CLK_PIPEPHY_DIV, "clk_pipephy_div", "cpll", 0, + RK3562_PMU0_CLKSEL_CON(2), 0, 6, DFLAGS, + RK3562_PMU0_CLKGATE_CON(2), 0, GFLAGS), + GATE(CLK_PIPEPHY_XIN24M, "clk_pipephy_xin24m", "xin24m", 0, + RK3562_PMU0_CLKGATE_CON(2), 1, GFLAGS), + COMPOSITE_NODIV(CLK_PIPEPHY_REF, "clk_pipephy_ref", clk_pipephy_ref_p, 0, + RK3562_PMU0_CLKSEL_CON(2), 7, 1, MFLAGS, + RK3562_PMU0_CLKGATE_CON(2), 2, GFLAGS), + GATE(CLK_USB2PHY_XIN24M, "clk_usb2phy_xin24m", "xin24m", 0, + RK3562_PMU0_CLKGATE_CON(2), 4, GFLAGS), + COMPOSITE_NODIV(CLK_USB2PHY_REF, "clk_usb2phy_ref", clk_usbphy_ref_p, 0, + RK3562_PMU0_CLKSEL_CON(2), 8, 1, MFLAGS, + RK3562_PMU0_CLKGATE_CON(2), 5, GFLAGS), + GATE(CLK_MIPIDSIPHY_XIN24M, "clk_mipidsiphy_xin24m", "xin24m", 0, + RK3562_PMU0_CLKGATE_CON(2), 6, GFLAGS), + COMPOSITE_NODIV(CLK_MIPIDSIPHY_REF, "clk_mipidsiphy_ref", clk_mipidsi_ref_p, 0, + RK3562_PMU0_CLKSEL_CON(2), 15, 1, MFLAGS, + RK3562_PMU0_CLKGATE_CON(2), 7, GFLAGS), + GATE(PCLK_PMU0_I2C0, "pclk_pmu0_i2c0", "busclk_pdpmu0", 0, + RK3562_PMU0_CLKGATE_CON(2), 8, GFLAGS), + COMPOSITE(CLK_PMU0_I2C0, "clk_pmu0_i2c0", mux_200m_xin24m_32k_p, 0, + RK3562_PMU0_CLKSEL_CON(3), 14, 2, MFLAGS, 8, 5, DFLAGS, + RK3562_PMU0_CLKGATE_CON(2), 9, GFLAGS), + /* PD_PMU1 */ + GATE(PCLK_PMU1_CRU, "pclk_pmu1_cru", "busclk_pdpmu0", CLK_IGNORE_UNUSED, + RK3562_PMU1_CLKGATE_CON(0), 0, GFLAGS), + GATE(HCLK_PMU1_MEM, "hclk_pmu1_mem", "busclk_pdpmu0", CLK_IGNORE_UNUSED, + RK3562_PMU1_CLKGATE_CON(0), 2, GFLAGS), + GATE(PCLK_PMU1_UART0, "pclk_pmu1_uart0", "busclk_pdpmu0", 0, + RK3562_PMU1_CLKGATE_CON(0), 7, GFLAGS), + COMPOSITE_NOMUX(CLK_PMU1_UART0_SRC, "clk_pmu1_uart0_src", "cpll", 0, + RK3562_PMU1_CLKSEL_CON(2), 0, 4, DFLAGS, + RK3562_PMU1_CLKGATE_CON(0), 8, GFLAGS), + COMPOSITE_FRACMUX(CLK_PMU1_UART0_FRAC, "clk_pmu1_uart0_frac", "clk_pmu1_uart0_src", CLK_SET_RATE_PARENT, + RK3562_PMU1_CLKSEL_CON(3), 0, + RK3562_PMU1_CLKGATE_CON(0), 9, GFLAGS, + &rk3562_clk_pmu1_uart0_fracmux), + GATE(SCLK_PMU1_UART0, "sclk_pmu1_uart0", "clk_pmu1_uart0", 0, + RK3562_PMU1_CLKGATE_CON(0), 10, GFLAGS), + GATE(PCLK_PMU1_SPI0, "pclk_pmu1_spi0", "busclk_pdpmu0", 0, + RK3562_PMU1_CLKGATE_CON(1), 0, GFLAGS), + COMPOSITE(CLK_PMU1_SPI0, "clk_pmu1_spi0", mux_200m_xin24m_32k_p, 0, + RK3562_PMU1_CLKSEL_CON(4), 6, 2, MFLAGS, 0, 2, DFLAGS, + RK3562_PMU1_CLKGATE_CON(1), 1, GFLAGS), + GATE(SCLK_IN_PMU1_SPI0, "sclk_in_pmu1_spi0", "sclk_in_pmu1_spi0_io", 0, + RK3562_PMU1_CLKGATE_CON(1), 2, GFLAGS), + GATE(PCLK_PMU1_PWM0, "pclk_pmu1_pwm0", "busclk_pdpmu0", 0, + RK3562_PMU1_CLKGATE_CON(1), 3, GFLAGS), + COMPOSITE(CLK_PMU1_PWM0, "clk_pmu1_pwm0", mux_200m_xin24m_32k_p, 0, + RK3562_PMU1_CLKSEL_CON(4), 14, 2, MFLAGS, 8, 2, DFLAGS, + RK3562_PMU1_CLKGATE_CON(1), 4, GFLAGS), + GATE(CLK_CAPTURE_PMU1_PWM0, "clk_capture_pmu1_pwm0", "xin24m", 0, + RK3562_PMU1_CLKGATE_CON(1), 5, GFLAGS), + GATE(CLK_PMU1_WIFI, "clk_pmu1_wifi", "xin24m", 0, + RK3562_PMU1_CLKGATE_CON(1), 6, GFLAGS), + GATE(FCLK_PMU1_CM0_CORE, "fclk_pmu1_cm0_core", "busclk_pdpmu0", 0, + RK3562_PMU1_CLKGATE_CON(2), 0, GFLAGS), + GATE(CLK_PMU1_CM0_RTC, "clk_pmu1_cm0_rtc", "clk_rtc_32k", 0, + RK3562_PMU1_CLKGATE_CON(2), 1, GFLAGS), + GATE(PCLK_PMU1_WDTNS, "pclk_pmu1_wdtns", "busclk_pdpmu0", 0, + RK3562_PMU1_CLKGATE_CON(2), 3, GFLAGS), + GATE(CLK_PMU1_WDTNS, "clk_pmu1_wdtns", "xin24m", 0, + RK3562_PMU1_CLKGATE_CON(2), 4, GFLAGS), + GATE(PCLK_PMU1_MAILBOX, "pclk_pmu1_mailbox", "busclk_pdpmu0", 0, + RK3562_PMU1_CLKGATE_CON(3), 8, GFLAGS), + + /* PD_RGA */ + COMPOSITE(ACLK_RGA_PRE, "aclk_rga_pre", gpll_cpll_pvtpll_dmyapll_p, 0, + RK3562_CLKSEL_CON(32), 6, 2, MFLAGS, 0, 4, DFLAGS, + RK3562_CLKGATE_CON(14), 0, GFLAGS), + COMPOSITE_NOMUX(HCLK_RGA_PRE, "hclk_rga_pre", "aclk_rga_jdec", 0, + RK3562_CLKSEL_CON(32), 8, 3, DFLAGS, + RK3562_CLKGATE_CON(14), 1, GFLAGS), + GATE(ACLK_RGA, "aclk_rga", "aclk_rga_jdec", 0, + RK3562_CLKGATE_CON(14), 6, GFLAGS), + GATE(HCLK_RGA, "hclk_rga", "hclk_rga_pre", 0, + RK3562_CLKGATE_CON(14), 7, GFLAGS), + COMPOSITE(CLK_RGA_CORE, "clk_rga_core", gpll_cpll_pvtpll_dmyapll_p, 0, + RK3562_CLKSEL_CON(33), 6, 2, MFLAGS, 0, 4, DFLAGS, + RK3562_CLKGATE_CON(14), 8, GFLAGS), + GATE(ACLK_JDEC, "aclk_jdec", "aclk_rga_jdec", 0, + RK3562_CLKGATE_CON(14), 9, GFLAGS), + GATE(HCLK_JDEC, "hclk_jdec", "hclk_rga_pre", 0, + RK3562_CLKGATE_CON(14), 10, GFLAGS), + + /* PD_VDPU */ + COMPOSITE(ACLK_VDPU_PRE, "aclk_vdpu_pre", gpll_cpll_pvtpll_dmyapll_p, 0, + RK3562_CLKSEL_CON(22), 6, 2, MFLAGS, 0, 5, DFLAGS, + RK3562_CLKGATE_CON(10), 0, GFLAGS), + COMPOSITE(CLK_RKVDEC_HEVC_CA, "clk_rkvdec_hevc_ca", gpll_cpll_pvtpll_dmyapll_p, 0, + RK3562_CLKSEL_CON(23), 14, 2, MFLAGS, 8, 5, DFLAGS, + RK3562_CLKGATE_CON(10), 3, GFLAGS), + COMPOSITE_NOMUX(HCLK_VDPU_PRE, "hclk_vdpu_pre", "aclk_vdpu", 0, + RK3562_CLKSEL_CON(24), 0, 4, DFLAGS, + RK3562_CLKGATE_CON(10), 4, GFLAGS), + GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_vdpu", 0, + RK3562_CLKGATE_CON(10), 7, GFLAGS), + GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_vdpu_pre", 0, + RK3562_CLKGATE_CON(10), 8, GFLAGS), + + /* PD_VEPU */ + COMPOSITE(CLK_RKVENC_CORE, "clk_rkvenc_core", gpll_cpll_pvtpll_dmyapll_p, 0, + RK3562_CLKSEL_CON(20), 6, 2, MFLAGS, 0, 5, DFLAGS, + RK3562_CLKGATE_CON(9), 0, GFLAGS), + COMPOSITE(ACLK_VEPU_PRE, "aclk_vepu_pre", gpll_cpll_pvtpll_dmyapll_p, 0, + RK3562_CLKSEL_CON(20), 14, 2, MFLAGS, 8, 5, DFLAGS, + RK3562_CLKGATE_CON(9), 1, GFLAGS), + COMPOSITE_NOMUX(HCLK_VEPU_PRE, "hclk_vepu_pre", "aclk_vepu", 0, + RK3562_CLKSEL_CON(21), 0, 4, DFLAGS, + RK3562_CLKGATE_CON(9), 2, GFLAGS), + GATE(ACLK_RKVENC, "aclk_rkvenc", "aclk_vepu", 0, + RK3562_CLKGATE_CON(9), 5, GFLAGS), + GATE(HCLK_RKVENC, "hclk_rkvenc", "hclk_vepu", 0, + RK3562_CLKGATE_CON(9), 6, GFLAGS), + + /* PD_VI */ + COMPOSITE(ACLK_VI, "aclk_vi", gpll_cpll_pvtpll_dmyapll_p, 0, + RK3562_CLKSEL_CON(25), 6, 2, MFLAGS, 0, 4, DFLAGS, + RK3562_CLKGATE_CON(11), 0, GFLAGS), + COMPOSITE_NOMUX(HCLK_VI, "hclk_vi", "aclk_vi_isp", 0, + RK3562_CLKSEL_CON(26), 0, 4, DFLAGS, + RK3562_CLKGATE_CON(11), 1, GFLAGS), + COMPOSITE_NOMUX(PCLK_VI, "pclk_vi", "aclk_vi_isp", 0, + RK3562_CLKSEL_CON(26), 8, 4, DFLAGS, + RK3562_CLKGATE_CON(11), 2, GFLAGS), + GATE(ACLK_ISP, "aclk_isp", "aclk_vi_isp", 0, + RK3562_CLKGATE_CON(11), 6, GFLAGS), + GATE(HCLK_ISP, "hclk_isp", "hclk_vi", 0, + RK3562_CLKGATE_CON(11), 7, GFLAGS), + COMPOSITE(CLK_ISP, "clk_isp", gpll_cpll_pvtpll_dmyapll_p, 0, + RK3562_CLKSEL_CON(27), 6, 2, MFLAGS, 0, 4, DFLAGS, + RK3562_CLKGATE_CON(11), 8, GFLAGS), + GATE(ACLK_VICAP, "aclk_vicap", "aclk_vi_isp", 0, + RK3562_CLKGATE_CON(11), 9, GFLAGS), + GATE(HCLK_VICAP, "hclk_vicap", "hclk_vi", 0, + RK3562_CLKGATE_CON(11), 10, GFLAGS), + COMPOSITE(DCLK_VICAP, "dclk_vicap", gpll_cpll_pvtpll_dmyapll_p, 0, + RK3562_CLKSEL_CON(27), 14, 2, MFLAGS, 8, 4, DFLAGS, + RK3562_CLKGATE_CON(11), 11, GFLAGS), + GATE(CSIRX0_CLK_DATA, "csirx0_clk_data", "csirx0_clk_data_io", 0, + RK3562_CLKGATE_CON(11), 12, GFLAGS), + GATE(CSIRX1_CLK_DATA, "csirx1_clk_data", "csirx1_clk_data_io", 0, + RK3562_CLKGATE_CON(11), 13, GFLAGS), + GATE(CSIRX2_CLK_DATA, "csirx2_clk_data", "csirx2_clk_data_io", 0, + RK3562_CLKGATE_CON(11), 14, GFLAGS), + GATE(CSIRX3_CLK_DATA, "csirx3_clk_data", "csirx3_clk_data_io", 0, + RK3562_CLKGATE_CON(11), 15, GFLAGS), + GATE(PCLK_CSIHOST0, "pclk_csihost0", "pclk_vi", 0, + RK3562_CLKGATE_CON(12), 0, GFLAGS), + GATE(PCLK_CSIHOST1, "pclk_csihost1", "pclk_vi", 0, + RK3562_CLKGATE_CON(12), 1, GFLAGS), + GATE(PCLK_CSIHOST2, "pclk_csihost2", "pclk_vi", 0, + RK3562_CLKGATE_CON(12), 2, GFLAGS), + GATE(PCLK_CSIHOST3, "pclk_csihost3", "pclk_vi", 0, + RK3562_CLKGATE_CON(12), 3, GFLAGS), + GATE(PCLK_CSIPHY0, "pclk_csiphy0", "pclk_vi", 0, + RK3562_CLKGATE_CON(12), 4, GFLAGS), + GATE(PCLK_CSIPHY1, "pclk_csiphy1", "pclk_vi", 0, + RK3562_CLKGATE_CON(12), 5, GFLAGS), + + /* PD_VO */ + COMPOSITE(ACLK_VO_PRE, "aclk_vo_pre", gpll_cpll_vpll_dmyhpll_p, 0, + RK3562_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 5, DFLAGS, + RK3562_CLKGATE_CON(13), 0, GFLAGS), + COMPOSITE_NOMUX(HCLK_VO_PRE, "hclk_vo_pre", "aclk_vo", 0, + RK3562_CLKSEL_CON(29), 0, 5, DFLAGS, + RK3562_CLKGATE_CON(13), 1, GFLAGS), + GATE(ACLK_VOP, "aclk_vop", "aclk_vo", 0, + RK3562_CLKGATE_CON(13), 6, GFLAGS), + GATE(HCLK_VOP, "hclk_vop", "hclk_vo_pre", 0, + RK3562_CLKGATE_CON(13), 7, GFLAGS), + COMPOSITE(DCLK_VOP, "dclk_vop", gpll_dmyhpll_vpll_apll_p, CLK_SET_RATE_NO_REPARENT, + RK3562_CLKSEL_CON(30), 14, 2, MFLAGS, 0, 8, DFLAGS, + RK3562_CLKGATE_CON(13), 8, GFLAGS), + COMPOSITE(DCLK_VOP1, "dclk_vop1", gpll_dmyhpll_vpll_apll_p, CLK_SET_RATE_NO_REPARENT, + RK3562_CLKSEL_CON(31), 14, 2, MFLAGS, 0, 8, DFLAGS, + RK3562_CLKGATE_CON(13), 9, GFLAGS), +}; + +static void __init rk3562_clk_init(struct device_node *np) +{ + struct rockchip_clk_provider *ctx; + unsigned long clk_nr_clks; + void __iomem *reg_base; + + clk_nr_clks = rockchip_clk_find_max_clk_id(rk3562_clk_branches, + ARRAY_SIZE(rk3562_clk_branches)) + 1; + + reg_base = of_iomap(np, 0); + if (!reg_base) { + pr_err("%s: could not map cru region\n", __func__); + return; + } + + ctx = rockchip_clk_init(np, reg_base, clk_nr_clks); + if (IS_ERR(ctx)) { + pr_err("%s: rockchip clk init failed\n", __func__); + iounmap(reg_base); + return; + } + + rockchip_clk_register_plls(ctx, rk3562_pll_clks, + ARRAY_SIZE(rk3562_pll_clks), + RK3562_GRF_SOC_STATUS0); + + rockchip_clk_register_branches(ctx, rk3562_clk_branches, + ARRAY_SIZE(rk3562_clk_branches)); + + rk3562_rst_init(np, reg_base); + + rockchip_register_restart_notifier(ctx, RK3562_GLB_SRST_FST, NULL); + + rockchip_clk_of_add_provider(np, ctx); +} + +CLK_OF_DECLARE(rk3562_cru, "rockchip,rk3562-cru", rk3562_clk_init); + +struct clk_rk3562_inits { + void (*inits)(struct device_node *np); +}; + +static const struct clk_rk3562_inits clk_rk3562_cru_init = { + .inits = rk3562_clk_init, +}; + +static const struct of_device_id clk_rk3562_match_table[] = { + { + .compatible = "rockchip,rk3562-cru", + .data = &clk_rk3562_cru_init, + }, + { } +}; + +static int clk_rk3562_probe(struct platform_device *pdev) +{ + const struct clk_rk3562_inits *init_data; + struct device *dev = &pdev->dev; + + init_data = device_get_match_data(dev); + if (!init_data) + return -EINVAL; + + if (init_data->inits) + init_data->inits(dev->of_node); + + return 0; +} + +static struct platform_driver clk_rk3562_driver = { + .probe = clk_rk3562_probe, + .driver = { + .name = "clk-rk3562", + .of_match_table = clk_rk3562_match_table, + .suppress_bind_attrs = true, + }, +}; +builtin_platform_driver_probe(clk_rk3562_driver, clk_rk3562_probe); diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c index 53d10b1c627b..7d9279291e76 100644 --- a/drivers/clk/rockchip/clk-rk3568.c +++ b/drivers/clk/rockchip/clk-rk3568.c @@ -1602,6 +1602,7 @@ static const char *const rk3568_cru_critical_clocks[] __initconst = { "pclk_php", "hclk_usb", "pclk_usb", + "hclk_vi", "hclk_vo", }; diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index 9b37d44b9e5d..df2b2d706450 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -207,6 +207,65 @@ struct clk; #define RK3399_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x100) #define RK3399_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x110) +#define RK3528_PMU_CRU_BASE 0x10000 +#define RK3528_PCIE_CRU_BASE 0x20000 +#define RK3528_DDRPHY_CRU_BASE 0x28000 +#define RK3528_PLL_CON(x) RK2928_PLL_CON(x) +#define RK3528_PCIE_PLL_CON(x) ((x) * 0x4 + RK3528_PCIE_CRU_BASE) +#define RK3528_DDRPHY_PLL_CON(x) ((x) * 0x4 + RK3528_DDRPHY_CRU_BASE) +#define RK3528_MODE_CON 0x280 +#define RK3528_CLKSEL_CON(x) ((x) * 0x4 + 0x300) +#define RK3528_CLKGATE_CON(x) ((x) * 0x4 + 0x800) +#define RK3528_SOFTRST_CON(x) ((x) * 0x4 + 0xa00) +#define RK3528_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PMU_CRU_BASE) +#define RK3528_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RK3528_PMU_CRU_BASE) +#define RK3528_PCIE_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PCIE_CRU_BASE) +#define RK3528_PCIE_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RK3528_PCIE_CRU_BASE) +#define RK3528_DDRPHY_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RK3528_DDRPHY_CRU_BASE) +#define RK3528_DDRPHY_MODE_CON (0x280 + RK3528_DDRPHY_CRU_BASE) +#define RK3528_GLB_CNT_TH 0xc00 +#define RK3528_GLB_SRST_FST 0xc08 +#define RK3528_GLB_SRST_SND 0xc0c + +#define RK3562_PMU0_CRU_BASE 0x10000 +#define RK3562_PMU1_CRU_BASE 0x18000 +#define RK3562_DDR_CRU_BASE 0x20000 +#define RK3562_SUBDDR_CRU_BASE 0x28000 +#define RK3562_PERI_CRU_BASE 0x30000 + +#define RK3562_PLL_CON(x) RK2928_PLL_CON(x) +#define RK3562_PMU1_PLL_CON(x) ((x) * 0x4 + RK3562_PMU1_CRU_BASE + 0x40) +#define RK3562_SUBDDR_PLL_CON(x) ((x) * 0x4 + RK3562_SUBDDR_CRU_BASE + 0x20) +#define RK3562_MODE_CON 0x600 +#define RK3562_PMU1_MODE_CON (RK3562_PMU1_CRU_BASE + 0x380) +#define RK3562_SUBDDR_MODE_CON (RK3562_SUBDDR_CRU_BASE + 0x380) +#define RK3562_CLKSEL_CON(x) ((x) * 0x4 + 0x100) +#define RK3562_CLKGATE_CON(x) ((x) * 0x4 + 0x300) +#define RK3562_SOFTRST_CON(x) ((x) * 0x4 + 0x400) +#define RK3562_DDR_CLKSEL_CON(x) ((x) * 0x4 + RK3562_DDR_CRU_BASE + 0x100) +#define RK3562_DDR_CLKGATE_CON(x) ((x) * 0x4 + RK3562_DDR_CRU_BASE + 0x180) +#define RK3562_DDR_SOFTRST_CON(x) ((x) * 0x4 + RK3562_DDR_CRU_BASE + 0x200) +#define RK3562_SUBDDR_CLKSEL_CON(x) ((x) * 0x4 + RK3562_SUBDDR_CRU_BASE + 0x100) +#define RK3562_SUBDDR_CLKGATE_CON(x) ((x) * 0x4 + RK3562_SUBDDR_CRU_BASE + 0x180) +#define RK3562_SUBDDR_SOFTRST_CON(x) ((x) * 0x4 + RK3562_SUBDDR_CRU_BASE + 0x200) +#define RK3562_PERI_CLKSEL_CON(x) ((x) * 0x4 + RK3562_PERI_CRU_BASE + 0x100) +#define RK3562_PERI_CLKGATE_CON(x) ((x) * 0x4 + RK3562_PERI_CRU_BASE + 0x300) +#define RK3562_PERI_SOFTRST_CON(x) ((x) * 0x4 + RK3562_PERI_CRU_BASE + 0x400) +#define RK3562_PMU0_CLKSEL_CON(x) ((x) * 0x4 + RK3562_PMU0_CRU_BASE + 0x100) +#define RK3562_PMU0_CLKGATE_CON(x) ((x) * 0x4 + RK3562_PMU0_CRU_BASE + 0x180) +#define RK3562_PMU0_SOFTRST_CON(x) ((x) * 0x4 + RK3562_PMU0_CRU_BASE + 0x200) +#define RK3562_PMU1_CLKSEL_CON(x) ((x) * 0x4 + RK3562_PMU1_CRU_BASE + 0x100) +#define RK3562_PMU1_CLKGATE_CON(x) ((x) * 0x4 + RK3562_PMU1_CRU_BASE + 0x180) +#define RK3562_PMU1_SOFTRST_CON(x) ((x) * 0x4 + RK3562_PMU1_CRU_BASE + 0x200) +#define RK3562_GLB_SRST_FST 0x614 +#define RK3562_GLB_SRST_SND 0x618 +#define RK3562_GLB_RST_CON 0x61c +#define RK3562_GLB_RST_ST 0x620 +#define RK3562_SDMMC0_CON0 0x624 +#define RK3562_SDMMC0_CON1 0x628 +#define RK3562_SDMMC1_CON0 0x62c +#define RK3562_SDMMC1_CON1 0x630 + #define RK3568_PLL_CON(x) RK2928_PLL_CON(x) #define RK3568_MODE_CON0 0xc0 #define RK3568_MISC_CON0 0xc4 @@ -444,6 +503,7 @@ struct rockchip_pll_rate_table { * Flags: * ROCKCHIP_PLL_SYNC_RATE - check rate parameters to match against the * rate_table parameters and ajust them if necessary. + * ROCKCHIP_PLL_FIXED_MODE - the pll operates in normal mode only */ struct rockchip_pll_clock { unsigned int id; @@ -461,6 +521,7 @@ struct rockchip_pll_clock { }; #define ROCKCHIP_PLL_SYNC_RATE BIT(0) +#define ROCKCHIP_PLL_FIXED_MODE BIT(1) #define PLL(_type, _id, _name, _pnames, _flags, _con, _mode, _mshift, \ _lshift, _pflags, _rtable) \ @@ -1118,6 +1179,8 @@ static inline void rockchip_register_softrst(struct device_node *np, return rockchip_register_softrst_lut(np, NULL, num_regs, base, flags); } +void rk3528_rst_init(struct device_node *np, void __iomem *reg_base); +void rk3562_rst_init(struct device_node *np, void __iomem *reg_base); void rk3576_rst_init(struct device_node *np, void __iomem *reg_base); void rk3588_rst_init(struct device_node *np, void __iomem *reg_base); diff --git a/drivers/clk/rockchip/rst-rk3528.c b/drivers/clk/rockchip/rst-rk3528.c new file mode 100644 index 000000000000..b24f2c367929 --- /dev/null +++ b/drivers/clk/rockchip/rst-rk3528.c @@ -0,0 +1,306 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * Based on Sebastian Reichel's implementation for RK3588 + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <dt-bindings/reset/rockchip,rk3528-cru.h> +#include "clk.h" + +/* 0xFF4A0000 + 0x0A00 */ +#define RK3528_CRU_RESET_OFFSET(id, reg, bit) [id] = (0 + reg * 16 + bit) + +/* mapping table for reset ID to register offset */ +static const int rk3528_register_offset[] = { + /* CRU_SOFTRST_CON03 */ + RK3528_CRU_RESET_OFFSET(SRST_CORE0_PO, 3, 0), + RK3528_CRU_RESET_OFFSET(SRST_CORE1_PO, 3, 1), + RK3528_CRU_RESET_OFFSET(SRST_CORE2_PO, 3, 2), + RK3528_CRU_RESET_OFFSET(SRST_CORE3_PO, 3, 3), + RK3528_CRU_RESET_OFFSET(SRST_CORE0, 3, 4), + RK3528_CRU_RESET_OFFSET(SRST_CORE1, 3, 5), + RK3528_CRU_RESET_OFFSET(SRST_CORE2, 3, 6), + RK3528_CRU_RESET_OFFSET(SRST_CORE3, 3, 7), + RK3528_CRU_RESET_OFFSET(SRST_NL2, 3, 8), + RK3528_CRU_RESET_OFFSET(SRST_CORE_BIU, 3, 9), + RK3528_CRU_RESET_OFFSET(SRST_CORE_CRYPTO, 3, 10), + + /* CRU_SOFTRST_CON05 */ + RK3528_CRU_RESET_OFFSET(SRST_P_DBG, 5, 13), + RK3528_CRU_RESET_OFFSET(SRST_POT_DBG, 5, 14), + RK3528_CRU_RESET_OFFSET(SRST_NT_DBG, 5, 15), + + /* CRU_SOFTRST_CON06 */ + RK3528_CRU_RESET_OFFSET(SRST_P_CORE_GRF, 6, 2), + RK3528_CRU_RESET_OFFSET(SRST_P_DAPLITE_BIU, 6, 3), + RK3528_CRU_RESET_OFFSET(SRST_P_CPU_BIU, 6, 4), + RK3528_CRU_RESET_OFFSET(SRST_REF_PVTPLL_CORE, 6, 7), + + /* CRU_SOFTRST_CON08 */ + RK3528_CRU_RESET_OFFSET(SRST_A_BUS_VOPGL_BIU, 8, 1), + RK3528_CRU_RESET_OFFSET(SRST_A_BUS_H_BIU, 8, 3), + RK3528_CRU_RESET_OFFSET(SRST_A_SYSMEM_BIU, 8, 8), + RK3528_CRU_RESET_OFFSET(SRST_A_BUS_BIU, 8, 10), + RK3528_CRU_RESET_OFFSET(SRST_H_BUS_BIU, 8, 11), + RK3528_CRU_RESET_OFFSET(SRST_P_BUS_BIU, 8, 12), + RK3528_CRU_RESET_OFFSET(SRST_P_DFT2APB, 8, 13), + RK3528_CRU_RESET_OFFSET(SRST_P_BUS_GRF, 8, 15), + + /* CRU_SOFTRST_CON09 */ + RK3528_CRU_RESET_OFFSET(SRST_A_BUS_M_BIU, 9, 0), + RK3528_CRU_RESET_OFFSET(SRST_A_GIC, 9, 1), + RK3528_CRU_RESET_OFFSET(SRST_A_SPINLOCK, 9, 2), + RK3528_CRU_RESET_OFFSET(SRST_A_DMAC, 9, 4), + RK3528_CRU_RESET_OFFSET(SRST_P_TIMER, 9, 5), + RK3528_CRU_RESET_OFFSET(SRST_TIMER0, 9, 6), + RK3528_CRU_RESET_OFFSET(SRST_TIMER1, 9, 7), + RK3528_CRU_RESET_OFFSET(SRST_TIMER2, 9, 8), + RK3528_CRU_RESET_OFFSET(SRST_TIMER3, 9, 9), + RK3528_CRU_RESET_OFFSET(SRST_TIMER4, 9, 10), + RK3528_CRU_RESET_OFFSET(SRST_TIMER5, 9, 11), + RK3528_CRU_RESET_OFFSET(SRST_P_JDBCK_DAP, 9, 12), + RK3528_CRU_RESET_OFFSET(SRST_JDBCK_DAP, 9, 13), + RK3528_CRU_RESET_OFFSET(SRST_P_WDT_NS, 9, 15), + + /* CRU_SOFTRST_CON10 */ + RK3528_CRU_RESET_OFFSET(SRST_T_WDT_NS, 10, 0), + RK3528_CRU_RESET_OFFSET(SRST_H_TRNG_NS, 10, 3), + RK3528_CRU_RESET_OFFSET(SRST_P_UART0, 10, 7), + RK3528_CRU_RESET_OFFSET(SRST_S_UART0, 10, 8), + RK3528_CRU_RESET_OFFSET(SRST_PKA_CRYPTO, 10, 10), + RK3528_CRU_RESET_OFFSET(SRST_A_CRYPTO, 10, 11), + RK3528_CRU_RESET_OFFSET(SRST_H_CRYPTO, 10, 12), + RK3528_CRU_RESET_OFFSET(SRST_P_DMA2DDR, 10, 13), + RK3528_CRU_RESET_OFFSET(SRST_A_DMA2DDR, 10, 14), + + /* CRU_SOFTRST_CON11 */ + RK3528_CRU_RESET_OFFSET(SRST_P_PWM0, 11, 4), + RK3528_CRU_RESET_OFFSET(SRST_PWM0, 11, 5), + RK3528_CRU_RESET_OFFSET(SRST_P_PWM1, 11, 7), + RK3528_CRU_RESET_OFFSET(SRST_PWM1, 11, 8), + RK3528_CRU_RESET_OFFSET(SRST_P_SCR, 11, 10), + RK3528_CRU_RESET_OFFSET(SRST_A_DCF, 11, 11), + RK3528_CRU_RESET_OFFSET(SRST_P_INTMUX, 11, 12), + + /* CRU_SOFTRST_CON25 */ + RK3528_CRU_RESET_OFFSET(SRST_A_VPU_BIU, 25, 6), + RK3528_CRU_RESET_OFFSET(SRST_H_VPU_BIU, 25, 7), + RK3528_CRU_RESET_OFFSET(SRST_P_VPU_BIU, 25, 8), + RK3528_CRU_RESET_OFFSET(SRST_A_VPU, 25, 9), + RK3528_CRU_RESET_OFFSET(SRST_H_VPU, 25, 10), + RK3528_CRU_RESET_OFFSET(SRST_P_CRU_PCIE, 25, 11), + RK3528_CRU_RESET_OFFSET(SRST_P_VPU_GRF, 25, 12), + RK3528_CRU_RESET_OFFSET(SRST_H_SFC, 25, 13), + RK3528_CRU_RESET_OFFSET(SRST_S_SFC, 25, 14), + RK3528_CRU_RESET_OFFSET(SRST_C_EMMC, 25, 15), + + /* CRU_SOFTRST_CON26 */ + RK3528_CRU_RESET_OFFSET(SRST_H_EMMC, 26, 0), + RK3528_CRU_RESET_OFFSET(SRST_A_EMMC, 26, 1), + RK3528_CRU_RESET_OFFSET(SRST_B_EMMC, 26, 2), + RK3528_CRU_RESET_OFFSET(SRST_T_EMMC, 26, 3), + RK3528_CRU_RESET_OFFSET(SRST_P_GPIO1, 26, 4), + RK3528_CRU_RESET_OFFSET(SRST_DB_GPIO1, 26, 5), + RK3528_CRU_RESET_OFFSET(SRST_A_VPU_L_BIU, 26, 6), + RK3528_CRU_RESET_OFFSET(SRST_P_VPU_IOC, 26, 8), + RK3528_CRU_RESET_OFFSET(SRST_H_SAI_I2S0, 26, 9), + RK3528_CRU_RESET_OFFSET(SRST_M_SAI_I2S0, 26, 10), + RK3528_CRU_RESET_OFFSET(SRST_H_SAI_I2S2, 26, 11), + RK3528_CRU_RESET_OFFSET(SRST_M_SAI_I2S2, 26, 12), + RK3528_CRU_RESET_OFFSET(SRST_P_ACODEC, 26, 13), + + /* CRU_SOFTRST_CON27 */ + RK3528_CRU_RESET_OFFSET(SRST_P_GPIO3, 27, 0), + RK3528_CRU_RESET_OFFSET(SRST_DB_GPIO3, 27, 1), + RK3528_CRU_RESET_OFFSET(SRST_P_SPI1, 27, 4), + RK3528_CRU_RESET_OFFSET(SRST_SPI1, 27, 5), + RK3528_CRU_RESET_OFFSET(SRST_P_UART2, 27, 7), + RK3528_CRU_RESET_OFFSET(SRST_S_UART2, 27, 8), + RK3528_CRU_RESET_OFFSET(SRST_P_UART5, 27, 9), + RK3528_CRU_RESET_OFFSET(SRST_S_UART5, 27, 10), + RK3528_CRU_RESET_OFFSET(SRST_P_UART6, 27, 11), + RK3528_CRU_RESET_OFFSET(SRST_S_UART6, 27, 12), + RK3528_CRU_RESET_OFFSET(SRST_P_UART7, 27, 13), + RK3528_CRU_RESET_OFFSET(SRST_S_UART7, 27, 14), + RK3528_CRU_RESET_OFFSET(SRST_P_I2C3, 27, 15), + + /* CRU_SOFTRST_CON28 */ + RK3528_CRU_RESET_OFFSET(SRST_I2C3, 28, 0), + RK3528_CRU_RESET_OFFSET(SRST_P_I2C5, 28, 1), + RK3528_CRU_RESET_OFFSET(SRST_I2C5, 28, 2), + RK3528_CRU_RESET_OFFSET(SRST_P_I2C6, 28, 3), + RK3528_CRU_RESET_OFFSET(SRST_I2C6, 28, 4), + RK3528_CRU_RESET_OFFSET(SRST_A_MAC, 28, 5), + + /* CRU_SOFTRST_CON30 */ + RK3528_CRU_RESET_OFFSET(SRST_P_PCIE, 30, 1), + RK3528_CRU_RESET_OFFSET(SRST_PCIE_PIPE_PHY, 30, 2), + RK3528_CRU_RESET_OFFSET(SRST_PCIE_POWER_UP, 30, 3), + RK3528_CRU_RESET_OFFSET(SRST_P_PCIE_PHY, 30, 6), + RK3528_CRU_RESET_OFFSET(SRST_P_PIPE_GRF, 30, 7), + + /* CRU_SOFTRST_CON32 */ + RK3528_CRU_RESET_OFFSET(SRST_H_SDIO0, 32, 2), + RK3528_CRU_RESET_OFFSET(SRST_H_SDIO1, 32, 4), + RK3528_CRU_RESET_OFFSET(SRST_TS_0, 32, 5), + RK3528_CRU_RESET_OFFSET(SRST_TS_1, 32, 6), + RK3528_CRU_RESET_OFFSET(SRST_P_CAN2, 32, 7), + RK3528_CRU_RESET_OFFSET(SRST_CAN2, 32, 8), + RK3528_CRU_RESET_OFFSET(SRST_P_CAN3, 32, 9), + RK3528_CRU_RESET_OFFSET(SRST_CAN3, 32, 10), + RK3528_CRU_RESET_OFFSET(SRST_P_SARADC, 32, 11), + RK3528_CRU_RESET_OFFSET(SRST_SARADC, 32, 12), + RK3528_CRU_RESET_OFFSET(SRST_SARADC_PHY, 32, 13), + RK3528_CRU_RESET_OFFSET(SRST_P_TSADC, 32, 14), + RK3528_CRU_RESET_OFFSET(SRST_TSADC, 32, 15), + + /* CRU_SOFTRST_CON33 */ + RK3528_CRU_RESET_OFFSET(SRST_A_USB3OTG, 33, 1), + + /* CRU_SOFTRST_CON34 */ + RK3528_CRU_RESET_OFFSET(SRST_A_GPU_BIU, 34, 3), + RK3528_CRU_RESET_OFFSET(SRST_P_GPU_BIU, 34, 5), + RK3528_CRU_RESET_OFFSET(SRST_A_GPU, 34, 8), + RK3528_CRU_RESET_OFFSET(SRST_REF_PVTPLL_GPU, 34, 9), + + /* CRU_SOFTRST_CON36 */ + RK3528_CRU_RESET_OFFSET(SRST_H_RKVENC_BIU, 36, 3), + RK3528_CRU_RESET_OFFSET(SRST_A_RKVENC_BIU, 36, 4), + RK3528_CRU_RESET_OFFSET(SRST_P_RKVENC_BIU, 36, 5), + RK3528_CRU_RESET_OFFSET(SRST_H_RKVENC, 36, 6), + RK3528_CRU_RESET_OFFSET(SRST_A_RKVENC, 36, 7), + RK3528_CRU_RESET_OFFSET(SRST_CORE_RKVENC, 36, 8), + RK3528_CRU_RESET_OFFSET(SRST_H_SAI_I2S1, 36, 9), + RK3528_CRU_RESET_OFFSET(SRST_M_SAI_I2S1, 36, 10), + RK3528_CRU_RESET_OFFSET(SRST_P_I2C1, 36, 11), + RK3528_CRU_RESET_OFFSET(SRST_I2C1, 36, 12), + RK3528_CRU_RESET_OFFSET(SRST_P_I2C0, 36, 13), + RK3528_CRU_RESET_OFFSET(SRST_I2C0, 36, 14), + + /* CRU_SOFTRST_CON37 */ + RK3528_CRU_RESET_OFFSET(SRST_P_SPI0, 37, 2), + RK3528_CRU_RESET_OFFSET(SRST_SPI0, 37, 3), + RK3528_CRU_RESET_OFFSET(SRST_P_GPIO4, 37, 8), + RK3528_CRU_RESET_OFFSET(SRST_DB_GPIO4, 37, 9), + RK3528_CRU_RESET_OFFSET(SRST_P_RKVENC_IOC, 37, 10), + RK3528_CRU_RESET_OFFSET(SRST_H_SPDIF, 37, 14), + RK3528_CRU_RESET_OFFSET(SRST_M_SPDIF, 37, 15), + + /* CRU_SOFTRST_CON38 */ + RK3528_CRU_RESET_OFFSET(SRST_H_PDM, 38, 0), + RK3528_CRU_RESET_OFFSET(SRST_M_PDM, 38, 1), + RK3528_CRU_RESET_OFFSET(SRST_P_UART1, 38, 2), + RK3528_CRU_RESET_OFFSET(SRST_S_UART1, 38, 3), + RK3528_CRU_RESET_OFFSET(SRST_P_UART3, 38, 4), + RK3528_CRU_RESET_OFFSET(SRST_S_UART3, 38, 5), + RK3528_CRU_RESET_OFFSET(SRST_P_RKVENC_GRF, 38, 6), + RK3528_CRU_RESET_OFFSET(SRST_P_CAN0, 38, 7), + RK3528_CRU_RESET_OFFSET(SRST_CAN0, 38, 8), + RK3528_CRU_RESET_OFFSET(SRST_P_CAN1, 38, 9), + RK3528_CRU_RESET_OFFSET(SRST_CAN1, 38, 10), + + /* CRU_SOFTRST_CON39 */ + RK3528_CRU_RESET_OFFSET(SRST_A_VO_BIU, 39, 3), + RK3528_CRU_RESET_OFFSET(SRST_H_VO_BIU, 39, 4), + RK3528_CRU_RESET_OFFSET(SRST_P_VO_BIU, 39, 5), + RK3528_CRU_RESET_OFFSET(SRST_H_RGA2E, 39, 7), + RK3528_CRU_RESET_OFFSET(SRST_A_RGA2E, 39, 8), + RK3528_CRU_RESET_OFFSET(SRST_CORE_RGA2E, 39, 9), + RK3528_CRU_RESET_OFFSET(SRST_H_VDPP, 39, 10), + RK3528_CRU_RESET_OFFSET(SRST_A_VDPP, 39, 11), + RK3528_CRU_RESET_OFFSET(SRST_CORE_VDPP, 39, 12), + RK3528_CRU_RESET_OFFSET(SRST_P_VO_GRF, 39, 13), + RK3528_CRU_RESET_OFFSET(SRST_P_CRU, 39, 15), + + /* CRU_SOFTRST_CON40 */ + RK3528_CRU_RESET_OFFSET(SRST_A_VOP_BIU, 40, 1), + RK3528_CRU_RESET_OFFSET(SRST_H_VOP, 40, 2), + RK3528_CRU_RESET_OFFSET(SRST_D_VOP0, 40, 3), + RK3528_CRU_RESET_OFFSET(SRST_D_VOP1, 40, 4), + RK3528_CRU_RESET_OFFSET(SRST_A_VOP, 40, 5), + RK3528_CRU_RESET_OFFSET(SRST_P_HDMI, 40, 6), + RK3528_CRU_RESET_OFFSET(SRST_HDMI, 40, 7), + RK3528_CRU_RESET_OFFSET(SRST_P_HDMIPHY, 40, 14), + RK3528_CRU_RESET_OFFSET(SRST_H_HDCP_KEY, 40, 15), + + /* CRU_SOFTRST_CON41 */ + RK3528_CRU_RESET_OFFSET(SRST_A_HDCP, 41, 0), + RK3528_CRU_RESET_OFFSET(SRST_H_HDCP, 41, 1), + RK3528_CRU_RESET_OFFSET(SRST_P_HDCP, 41, 2), + RK3528_CRU_RESET_OFFSET(SRST_H_CVBS, 41, 3), + RK3528_CRU_RESET_OFFSET(SRST_D_CVBS_VOP, 41, 4), + RK3528_CRU_RESET_OFFSET(SRST_D_4X_CVBS_VOP, 41, 5), + RK3528_CRU_RESET_OFFSET(SRST_A_JPEG_DECODER, 41, 6), + RK3528_CRU_RESET_OFFSET(SRST_H_JPEG_DECODER, 41, 7), + RK3528_CRU_RESET_OFFSET(SRST_A_VO_L_BIU, 41, 9), + RK3528_CRU_RESET_OFFSET(SRST_A_MAC_VO, 41, 10), + + /* CRU_SOFTRST_CON42 */ + RK3528_CRU_RESET_OFFSET(SRST_A_JPEG_BIU, 42, 0), + RK3528_CRU_RESET_OFFSET(SRST_H_SAI_I2S3, 42, 1), + RK3528_CRU_RESET_OFFSET(SRST_M_SAI_I2S3, 42, 2), + RK3528_CRU_RESET_OFFSET(SRST_MACPHY, 42, 3), + RK3528_CRU_RESET_OFFSET(SRST_P_VCDCPHY, 42, 4), + RK3528_CRU_RESET_OFFSET(SRST_P_GPIO2, 42, 5), + RK3528_CRU_RESET_OFFSET(SRST_DB_GPIO2, 42, 6), + RK3528_CRU_RESET_OFFSET(SRST_P_VO_IOC, 42, 7), + RK3528_CRU_RESET_OFFSET(SRST_H_SDMMC0, 42, 9), + RK3528_CRU_RESET_OFFSET(SRST_P_OTPC_NS, 42, 11), + RK3528_CRU_RESET_OFFSET(SRST_SBPI_OTPC_NS, 42, 12), + RK3528_CRU_RESET_OFFSET(SRST_USER_OTPC_NS, 42, 13), + + /* CRU_SOFTRST_CON43 */ + RK3528_CRU_RESET_OFFSET(SRST_HDMIHDP0, 43, 2), + RK3528_CRU_RESET_OFFSET(SRST_H_USBHOST, 43, 3), + RK3528_CRU_RESET_OFFSET(SRST_H_USBHOST_ARB, 43, 4), + RK3528_CRU_RESET_OFFSET(SRST_HOST_UTMI, 43, 6), + RK3528_CRU_RESET_OFFSET(SRST_P_UART4, 43, 7), + RK3528_CRU_RESET_OFFSET(SRST_S_UART4, 43, 8), + RK3528_CRU_RESET_OFFSET(SRST_P_I2C4, 43, 9), + RK3528_CRU_RESET_OFFSET(SRST_I2C4, 43, 10), + RK3528_CRU_RESET_OFFSET(SRST_P_I2C7, 43, 11), + RK3528_CRU_RESET_OFFSET(SRST_I2C7, 43, 12), + RK3528_CRU_RESET_OFFSET(SRST_P_USBPHY, 43, 13), + RK3528_CRU_RESET_OFFSET(SRST_USBPHY_POR, 43, 14), + RK3528_CRU_RESET_OFFSET(SRST_USBPHY_OTG, 43, 15), + + /* CRU_SOFTRST_CON44 */ + RK3528_CRU_RESET_OFFSET(SRST_USBPHY_HOST, 44, 0), + RK3528_CRU_RESET_OFFSET(SRST_P_DDRPHY_CRU, 44, 4), + RK3528_CRU_RESET_OFFSET(SRST_H_RKVDEC_BIU, 44, 6), + RK3528_CRU_RESET_OFFSET(SRST_A_RKVDEC_BIU, 44, 7), + RK3528_CRU_RESET_OFFSET(SRST_A_RKVDEC, 44, 8), + RK3528_CRU_RESET_OFFSET(SRST_H_RKVDEC, 44, 9), + RK3528_CRU_RESET_OFFSET(SRST_HEVC_CA_RKVDEC, 44, 11), + RK3528_CRU_RESET_OFFSET(SRST_REF_PVTPLL_RKVDEC, 44, 12), + + /* CRU_SOFTRST_CON45 */ + RK3528_CRU_RESET_OFFSET(SRST_P_DDR_BIU, 45, 1), + RK3528_CRU_RESET_OFFSET(SRST_P_DDRC, 45, 2), + RK3528_CRU_RESET_OFFSET(SRST_P_DDRMON, 45, 3), + RK3528_CRU_RESET_OFFSET(SRST_TIMER_DDRMON, 45, 4), + RK3528_CRU_RESET_OFFSET(SRST_P_MSCH_BIU, 45, 5), + RK3528_CRU_RESET_OFFSET(SRST_P_DDR_GRF, 45, 6), + RK3528_CRU_RESET_OFFSET(SRST_P_DDR_HWLP, 45, 8), + RK3528_CRU_RESET_OFFSET(SRST_P_DDRPHY, 45, 9), + RK3528_CRU_RESET_OFFSET(SRST_MSCH_BIU, 45, 10), + RK3528_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL, 45, 11), + RK3528_CRU_RESET_OFFSET(SRST_DDR_UPCTL, 45, 12), + RK3528_CRU_RESET_OFFSET(SRST_DDRMON, 45, 13), + RK3528_CRU_RESET_OFFSET(SRST_A_DDR_SCRAMBLE, 45, 14), + RK3528_CRU_RESET_OFFSET(SRST_A_SPLIT, 45, 15), + + /* CRU_SOFTRST_CON46 */ + RK3528_CRU_RESET_OFFSET(SRST_DDR_PHY, 46, 0), +}; + +void rk3528_rst_init(struct device_node *np, void __iomem *reg_base) +{ + rockchip_register_softrst_lut(np, + rk3528_register_offset, + ARRAY_SIZE(rk3528_register_offset), + reg_base + RK3528_SOFTRST_CON(0), + ROCKCHIP_SOFTRST_HIWORD_MASK); +} diff --git a/drivers/clk/rockchip/rst-rk3562.c b/drivers/clk/rockchip/rst-rk3562.c new file mode 100644 index 000000000000..a3854eaef3be --- /dev/null +++ b/drivers/clk/rockchip/rst-rk3562.c @@ -0,0 +1,429 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + * Copyright (c) 2024 Collabora Ltd. + * Author: Detlev Casanova <detlev.casanova@collabora.com> + * Based on Sebastien Reichel's implementation for RK3588 + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <dt-bindings/reset/rockchip,rk3562-cru.h> +#include "clk.h" + +/* 0xff100000 + 0x0A00 */ +#define RK3562_CRU_RESET_OFFSET(id, reg, bit) [id] = (0 + reg * 16 + bit) +/* 0xff110000 + 0x0A00 */ +#define RK3562_PMU0CRU_RESET_OFFSET(id, reg, bit) [id] = (0x10000*4 + reg * 16 + bit) +/* 0xff118000 + 0x0A00 */ +#define RK3562_PMU1CRU_RESET_OFFSET(id, reg, bit) [id] = (0x18000*4 + reg * 16 + bit) +/* 0xff120000 + 0x0A00 */ +#define RK3562_DDRCRU_RESET_OFFSET(id, reg, bit) [id] = (0x20000*4 + reg * 16 + bit) +/* 0xff128000 + 0x0A00 */ +#define RK3562_SUBDDRCRU_RESET_OFFSET(id, reg, bit) [id] = (0x28000*4 + reg * 16 + bit) +/* 0xff130000 + 0x0A00 */ +#define RK3562_PERICRU_RESET_OFFSET(id, reg, bit) [id] = (0x30000*4 + reg * 16 + bit) + +/* mapping table for reset ID to register offset */ +static const int rk3562_register_offset[] = { + /* SOFTRST_CON01 */ + RK3562_CRU_RESET_OFFSET(SRST_A_TOP_BIU, 1, 0), + RK3562_CRU_RESET_OFFSET(SRST_A_TOP_VIO_BIU, 1, 1), + RK3562_CRU_RESET_OFFSET(SRST_REF_PVTPLL_LOGIC, 1, 2), + + /* SOFTRST_CON03 */ + RK3562_CRU_RESET_OFFSET(SRST_NCOREPORESET0, 3, 0), + RK3562_CRU_RESET_OFFSET(SRST_NCOREPORESET1, 3, 1), + RK3562_CRU_RESET_OFFSET(SRST_NCOREPORESET2, 3, 2), + RK3562_CRU_RESET_OFFSET(SRST_NCOREPORESET3, 3, 3), + RK3562_CRU_RESET_OFFSET(SRST_NCORESET0, 3, 4), + RK3562_CRU_RESET_OFFSET(SRST_NCORESET1, 3, 5), + RK3562_CRU_RESET_OFFSET(SRST_NCORESET2, 3, 6), + RK3562_CRU_RESET_OFFSET(SRST_NCORESET3, 3, 7), + RK3562_CRU_RESET_OFFSET(SRST_NL2RESET, 3, 8), + + /* SOFTRST_CON04 */ + RK3562_CRU_RESET_OFFSET(SRST_DAP, 4, 9), + RK3562_CRU_RESET_OFFSET(SRST_P_DBG_DAPLITE, 4, 10), + RK3562_CRU_RESET_OFFSET(SRST_REF_PVTPLL_CORE, 4, 13), + + /* SOFTRST_CON05 */ + RK3562_CRU_RESET_OFFSET(SRST_A_CORE_BIU, 5, 0), + RK3562_CRU_RESET_OFFSET(SRST_P_CORE_BIU, 5, 1), + RK3562_CRU_RESET_OFFSET(SRST_H_CORE_BIU, 5, 2), + + /* SOFTRST_CON06 */ + RK3562_CRU_RESET_OFFSET(SRST_A_NPU_BIU, 6, 2), + RK3562_CRU_RESET_OFFSET(SRST_H_NPU_BIU, 6, 3), + RK3562_CRU_RESET_OFFSET(SRST_A_RKNN, 6, 4), + RK3562_CRU_RESET_OFFSET(SRST_H_RKNN, 6, 5), + RK3562_CRU_RESET_OFFSET(SRST_REF_PVTPLL_NPU, 6, 6), + + /* SOFTRST_CON08 */ + RK3562_CRU_RESET_OFFSET(SRST_A_GPU_BIU, 8, 3), + RK3562_CRU_RESET_OFFSET(SRST_GPU, 8, 4), + RK3562_CRU_RESET_OFFSET(SRST_REF_PVTPLL_GPU, 8, 5), + RK3562_CRU_RESET_OFFSET(SRST_GPU_BRG_BIU, 8, 8), + + /* SOFTRST_CON09 */ + RK3562_CRU_RESET_OFFSET(SRST_RKVENC_CORE, 9, 0), + RK3562_CRU_RESET_OFFSET(SRST_A_VEPU_BIU, 9, 3), + RK3562_CRU_RESET_OFFSET(SRST_H_VEPU_BIU, 9, 4), + RK3562_CRU_RESET_OFFSET(SRST_A_RKVENC, 9, 5), + RK3562_CRU_RESET_OFFSET(SRST_H_RKVENC, 9, 6), + + /* SOFTRST_CON10 */ + RK3562_CRU_RESET_OFFSET(SRST_RKVDEC_HEVC_CA, 10, 2), + RK3562_CRU_RESET_OFFSET(SRST_A_VDPU_BIU, 10, 5), + RK3562_CRU_RESET_OFFSET(SRST_H_VDPU_BIU, 10, 6), + RK3562_CRU_RESET_OFFSET(SRST_A_RKVDEC, 10, 7), + RK3562_CRU_RESET_OFFSET(SRST_H_RKVDEC, 10, 8), + + /* SOFTRST_CON11 */ + RK3562_CRU_RESET_OFFSET(SRST_A_VI_BIU, 11, 3), + RK3562_CRU_RESET_OFFSET(SRST_H_VI_BIU, 11, 4), + RK3562_CRU_RESET_OFFSET(SRST_P_VI_BIU, 11, 5), + RK3562_CRU_RESET_OFFSET(SRST_ISP, 11, 8), + RK3562_CRU_RESET_OFFSET(SRST_A_VICAP, 11, 9), + RK3562_CRU_RESET_OFFSET(SRST_H_VICAP, 11, 10), + RK3562_CRU_RESET_OFFSET(SRST_D_VICAP, 11, 11), + RK3562_CRU_RESET_OFFSET(SRST_I0_VICAP, 11, 12), + RK3562_CRU_RESET_OFFSET(SRST_I1_VICAP, 11, 13), + RK3562_CRU_RESET_OFFSET(SRST_I2_VICAP, 11, 14), + RK3562_CRU_RESET_OFFSET(SRST_I3_VICAP, 11, 15), + + /* SOFTRST_CON12 */ + RK3562_CRU_RESET_OFFSET(SRST_P_CSIHOST0, 12, 0), + RK3562_CRU_RESET_OFFSET(SRST_P_CSIHOST1, 12, 1), + RK3562_CRU_RESET_OFFSET(SRST_P_CSIHOST2, 12, 2), + RK3562_CRU_RESET_OFFSET(SRST_P_CSIHOST3, 12, 3), + RK3562_CRU_RESET_OFFSET(SRST_P_CSIPHY0, 12, 4), + RK3562_CRU_RESET_OFFSET(SRST_P_CSIPHY1, 12, 5), + + /* SOFTRST_CON13 */ + RK3562_CRU_RESET_OFFSET(SRST_A_VO_BIU, 13, 3), + RK3562_CRU_RESET_OFFSET(SRST_H_VO_BIU, 13, 4), + RK3562_CRU_RESET_OFFSET(SRST_A_VOP, 13, 6), + RK3562_CRU_RESET_OFFSET(SRST_H_VOP, 13, 7), + RK3562_CRU_RESET_OFFSET(SRST_D_VOP, 13, 8), + RK3562_CRU_RESET_OFFSET(SRST_D_VOP1, 13, 9), + + /* SOFTRST_CON14 */ + RK3562_CRU_RESET_OFFSET(SRST_A_RGA_BIU, 14, 3), + RK3562_CRU_RESET_OFFSET(SRST_H_RGA_BIU, 14, 4), + RK3562_CRU_RESET_OFFSET(SRST_A_RGA, 14, 6), + RK3562_CRU_RESET_OFFSET(SRST_H_RGA, 14, 7), + RK3562_CRU_RESET_OFFSET(SRST_RGA_CORE, 14, 8), + RK3562_CRU_RESET_OFFSET(SRST_A_JDEC, 14, 9), + RK3562_CRU_RESET_OFFSET(SRST_H_JDEC, 14, 10), + + /* SOFTRST_CON15 */ + RK3562_CRU_RESET_OFFSET(SRST_B_EBK_BIU, 15, 2), + RK3562_CRU_RESET_OFFSET(SRST_P_EBK_BIU, 15, 3), + RK3562_CRU_RESET_OFFSET(SRST_AHB2AXI_EBC, 15, 4), + RK3562_CRU_RESET_OFFSET(SRST_H_EBC, 15, 5), + RK3562_CRU_RESET_OFFSET(SRST_D_EBC, 15, 6), + RK3562_CRU_RESET_OFFSET(SRST_H_EINK, 15, 7), + RK3562_CRU_RESET_OFFSET(SRST_P_EINK, 15, 8), + + /* SOFTRST_CON16 */ + RK3562_CRU_RESET_OFFSET(SRST_P_PHP_BIU, 16, 2), + RK3562_CRU_RESET_OFFSET(SRST_A_PHP_BIU, 16, 3), + RK3562_CRU_RESET_OFFSET(SRST_P_PCIE20, 16, 7), + RK3562_CRU_RESET_OFFSET(SRST_PCIE20_POWERUP, 16, 8), + RK3562_CRU_RESET_OFFSET(SRST_USB3OTG, 16, 10), + + /* SOFTRST_CON17 */ + RK3562_CRU_RESET_OFFSET(SRST_PIPEPHY, 17, 3), + + /* SOFTRST_CON18 */ + RK3562_CRU_RESET_OFFSET(SRST_A_BUS_BIU, 18, 3), + RK3562_CRU_RESET_OFFSET(SRST_H_BUS_BIU, 18, 4), + RK3562_CRU_RESET_OFFSET(SRST_P_BUS_BIU, 18, 5), + + /* SOFTRST_CON19 */ + RK3562_CRU_RESET_OFFSET(SRST_P_I2C1, 19, 0), + RK3562_CRU_RESET_OFFSET(SRST_P_I2C2, 19, 1), + RK3562_CRU_RESET_OFFSET(SRST_P_I2C3, 19, 2), + RK3562_CRU_RESET_OFFSET(SRST_P_I2C4, 19, 3), + RK3562_CRU_RESET_OFFSET(SRST_P_I2C5, 19, 4), + RK3562_CRU_RESET_OFFSET(SRST_I2C1, 19, 6), + RK3562_CRU_RESET_OFFSET(SRST_I2C2, 19, 7), + RK3562_CRU_RESET_OFFSET(SRST_I2C3, 19, 8), + RK3562_CRU_RESET_OFFSET(SRST_I2C4, 19, 9), + RK3562_CRU_RESET_OFFSET(SRST_I2C5, 19, 10), + + /* SOFTRST_CON20 */ + RK3562_CRU_RESET_OFFSET(SRST_BUS_GPIO3, 20, 5), + RK3562_CRU_RESET_OFFSET(SRST_BUS_GPIO4, 20, 6), + + /* SOFTRST_CON21 */ + RK3562_CRU_RESET_OFFSET(SRST_P_TIMER, 21, 0), + RK3562_CRU_RESET_OFFSET(SRST_TIMER0, 21, 1), + RK3562_CRU_RESET_OFFSET(SRST_TIMER1, 21, 2), + RK3562_CRU_RESET_OFFSET(SRST_TIMER2, 21, 3), + RK3562_CRU_RESET_OFFSET(SRST_TIMER3, 21, 4), + RK3562_CRU_RESET_OFFSET(SRST_TIMER4, 21, 5), + RK3562_CRU_RESET_OFFSET(SRST_TIMER5, 21, 6), + RK3562_CRU_RESET_OFFSET(SRST_P_STIMER, 21, 7), + RK3562_CRU_RESET_OFFSET(SRST_STIMER0, 21, 8), + RK3562_CRU_RESET_OFFSET(SRST_STIMER1, 21, 9), + + /* SOFTRST_CON22 */ + RK3562_CRU_RESET_OFFSET(SRST_P_WDTNS, 22, 0), + RK3562_CRU_RESET_OFFSET(SRST_WDTNS, 22, 1), + RK3562_CRU_RESET_OFFSET(SRST_P_GRF, 22, 2), + RK3562_CRU_RESET_OFFSET(SRST_P_SGRF, 22, 3), + RK3562_CRU_RESET_OFFSET(SRST_P_MAILBOX, 22, 4), + RK3562_CRU_RESET_OFFSET(SRST_P_INTC, 22, 5), + RK3562_CRU_RESET_OFFSET(SRST_A_BUS_GIC400, 22, 6), + RK3562_CRU_RESET_OFFSET(SRST_A_BUS_GIC400_DEBUG, 22, 7), + + /* SOFTRST_CON23 */ + RK3562_CRU_RESET_OFFSET(SRST_A_BUS_SPINLOCK, 23, 0), + RK3562_CRU_RESET_OFFSET(SRST_A_DCF, 23, 1), + RK3562_CRU_RESET_OFFSET(SRST_P_DCF, 23, 2), + RK3562_CRU_RESET_OFFSET(SRST_F_BUS_CM0_CORE, 23, 3), + RK3562_CRU_RESET_OFFSET(SRST_T_BUS_CM0_JTAG, 23, 5), + RK3562_CRU_RESET_OFFSET(SRST_H_ICACHE, 23, 8), + RK3562_CRU_RESET_OFFSET(SRST_H_DCACHE, 23, 9), + + /* SOFTRST_CON24 */ + RK3562_CRU_RESET_OFFSET(SRST_P_TSADC, 24, 0), + RK3562_CRU_RESET_OFFSET(SRST_TSADC, 24, 1), + RK3562_CRU_RESET_OFFSET(SRST_TSADCPHY, 24, 2), + RK3562_CRU_RESET_OFFSET(SRST_P_DFT2APB, 24, 4), + + /* SOFTRST_CON25 */ + RK3562_CRU_RESET_OFFSET(SRST_A_GMAC, 25, 0), + RK3562_CRU_RESET_OFFSET(SRST_P_APB2ASB_VCCIO156, 25, 1), + RK3562_CRU_RESET_OFFSET(SRST_P_DSIPHY, 25, 5), + RK3562_CRU_RESET_OFFSET(SRST_P_DSITX, 25, 8), + RK3562_CRU_RESET_OFFSET(SRST_P_CPU_EMA_DET, 25, 9), + RK3562_CRU_RESET_OFFSET(SRST_P_HASH, 25, 10), + RK3562_CRU_RESET_OFFSET(SRST_P_TOPCRU, 25, 11), + + /* SOFTRST_CON26 */ + RK3562_CRU_RESET_OFFSET(SRST_P_ASB2APB_VCCIO156, 26, 0), + RK3562_CRU_RESET_OFFSET(SRST_P_IOC_VCCIO156, 26, 1), + RK3562_CRU_RESET_OFFSET(SRST_P_GPIO3_VCCIO156, 26, 2), + RK3562_CRU_RESET_OFFSET(SRST_P_GPIO4_VCCIO156, 26, 3), + RK3562_CRU_RESET_OFFSET(SRST_P_SARADC_VCCIO156, 26, 4), + RK3562_CRU_RESET_OFFSET(SRST_SARADC_VCCIO156, 26, 5), + RK3562_CRU_RESET_OFFSET(SRST_SARADC_VCCIO156_PHY, 26, 6), + + /* SOFTRST_CON27 */ + RK3562_CRU_RESET_OFFSET(SRST_A_MAC100, 27, 1), + + /* PMU0_SOFTRST_CON00 */ + RK3562_PMU0CRU_RESET_OFFSET(SRST_P_PMU0_CRU, 0, 0), + RK3562_PMU0CRU_RESET_OFFSET(SRST_P_PMU0_PMU, 0, 1), + RK3562_PMU0CRU_RESET_OFFSET(SRST_PMU0_PMU, 0, 2), + RK3562_PMU0CRU_RESET_OFFSET(SRST_P_PMU0_HP_TIMER, 0, 3), + RK3562_PMU0CRU_RESET_OFFSET(SRST_PMU0_HP_TIMER, 0, 4), + RK3562_PMU0CRU_RESET_OFFSET(SRST_PMU0_32K_HP_TIMER, 0, 5), + RK3562_PMU0CRU_RESET_OFFSET(SRST_P_PMU0_PVTM, 0, 6), + RK3562_PMU0CRU_RESET_OFFSET(SRST_PMU0_PVTM, 0, 7), + RK3562_PMU0CRU_RESET_OFFSET(SRST_P_IOC_PMUIO, 0, 8), + RK3562_PMU0CRU_RESET_OFFSET(SRST_P_PMU0_GPIO0, 0, 9), + RK3562_PMU0CRU_RESET_OFFSET(SRST_PMU0_GPIO0, 0, 10), + RK3562_PMU0CRU_RESET_OFFSET(SRST_P_PMU0_GRF, 0, 11), + RK3562_PMU0CRU_RESET_OFFSET(SRST_P_PMU0_SGRF, 0, 12), + + /* PMU0_SOFTRST_CON01 */ + RK3562_PMU0CRU_RESET_OFFSET(SRST_DDR_FAIL_SAFE, 1, 0), + RK3562_PMU0CRU_RESET_OFFSET(SRST_P_PMU0_SCRKEYGEN, 1, 1), + + /* PMU0_SOFTRST_CON02 */ + RK3562_PMU0CRU_RESET_OFFSET(SRST_P_PMU0_I2C0, 2, 8), + RK3562_PMU0CRU_RESET_OFFSET(SRST_PMU0_I2C0, 2, 9), + + /* PMU1_SOFTRST_CON00 */ + RK3562_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_CRU, 0, 0), + RK3562_PMU1CRU_RESET_OFFSET(SRST_H_PMU1_MEM, 0, 2), + RK3562_PMU1CRU_RESET_OFFSET(SRST_H_PMU1_BIU, 0, 3), + RK3562_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_BIU, 0, 4), + RK3562_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_UART0, 0, 7), + RK3562_PMU1CRU_RESET_OFFSET(SRST_S_PMU1_UART0, 0, 10), + + /* PMU1_SOFTRST_CON01 */ + RK3562_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_SPI0, 1, 0), + RK3562_PMU1CRU_RESET_OFFSET(SRST_PMU1_SPI0, 1, 1), + RK3562_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_PWM0, 1, 3), + RK3562_PMU1CRU_RESET_OFFSET(SRST_PMU1_PWM0, 1, 4), + + /* PMU1_SOFTRST_CON02 */ + RK3562_PMU1CRU_RESET_OFFSET(SRST_F_PMU1_CM0_CORE, 2, 0), + RK3562_PMU1CRU_RESET_OFFSET(SRST_T_PMU1_CM0_JTAG, 2, 2), + RK3562_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_WDTNS, 2, 3), + RK3562_PMU1CRU_RESET_OFFSET(SRST_PMU1_WDTNS, 2, 4), + RK3562_PMU1CRU_RESET_OFFSET(SRST_PMU1_MAILBOX, 2, 8), + + /* DDR_SOFTRST_CON00 */ + RK3562_DDRCRU_RESET_OFFSET(SRST_MSCH_BRG_BIU, 0, 4), + RK3562_DDRCRU_RESET_OFFSET(SRST_P_MSCH_BIU, 0, 5), + RK3562_DDRCRU_RESET_OFFSET(SRST_P_DDR_HWLP, 0, 6), + RK3562_DDRCRU_RESET_OFFSET(SRST_P_DDR_PHY, 0, 8), + RK3562_DDRCRU_RESET_OFFSET(SRST_P_DDR_DFICTL, 0, 9), + RK3562_DDRCRU_RESET_OFFSET(SRST_P_DDR_DMA2DDR, 0, 10), + + /* DDR_SOFTRST_CON01 */ + RK3562_DDRCRU_RESET_OFFSET(SRST_P_DDR_MON, 1, 0), + RK3562_DDRCRU_RESET_OFFSET(SRST_TM_DDR_MON, 1, 1), + RK3562_DDRCRU_RESET_OFFSET(SRST_P_DDR_GRF, 1, 2), + RK3562_DDRCRU_RESET_OFFSET(SRST_P_DDR_CRU, 1, 3), + RK3562_DDRCRU_RESET_OFFSET(SRST_P_SUBDDR_CRU, 1, 4), + + /* SUBDDR_SOFTRST_CON00 */ + RK3562_SUBDDRCRU_RESET_OFFSET(SRST_MSCH_BIU, 0, 1), + RK3562_SUBDDRCRU_RESET_OFFSET(SRST_DDR_PHY, 0, 4), + RK3562_SUBDDRCRU_RESET_OFFSET(SRST_DDR_DFICTL, 0, 5), + RK3562_SUBDDRCRU_RESET_OFFSET(SRST_DDR_SCRAMBLE, 0, 6), + RK3562_SUBDDRCRU_RESET_OFFSET(SRST_DDR_MON, 0, 7), + RK3562_SUBDDRCRU_RESET_OFFSET(SRST_A_DDR_SPLIT, 0, 8), + RK3562_SUBDDRCRU_RESET_OFFSET(SRST_DDR_DMA2DDR, 0, 9), + + /* PERI_SOFTRST_CON01 */ + RK3562_PERICRU_RESET_OFFSET(SRST_A_PERI_BIU, 1, 3), + RK3562_PERICRU_RESET_OFFSET(SRST_H_PERI_BIU, 1, 4), + RK3562_PERICRU_RESET_OFFSET(SRST_P_PERI_BIU, 1, 5), + RK3562_PERICRU_RESET_OFFSET(SRST_P_PERICRU, 1, 6), + + /* PERI_SOFTRST_CON02 */ + RK3562_PERICRU_RESET_OFFSET(SRST_H_SAI0_8CH, 2, 0), + RK3562_PERICRU_RESET_OFFSET(SRST_M_SAI0_8CH, 2, 3), + RK3562_PERICRU_RESET_OFFSET(SRST_H_SAI1_8CH, 2, 5), + RK3562_PERICRU_RESET_OFFSET(SRST_M_SAI1_8CH, 2, 8), + RK3562_PERICRU_RESET_OFFSET(SRST_H_SAI2_2CH, 2, 10), + RK3562_PERICRU_RESET_OFFSET(SRST_M_SAI2_2CH, 2, 13), + + /* PERI_SOFTRST_CON03 */ + RK3562_PERICRU_RESET_OFFSET(SRST_H_DSM, 3, 1), + RK3562_PERICRU_RESET_OFFSET(SRST_DSM, 3, 2), + RK3562_PERICRU_RESET_OFFSET(SRST_H_PDM, 3, 4), + RK3562_PERICRU_RESET_OFFSET(SRST_M_PDM, 3, 5), + RK3562_PERICRU_RESET_OFFSET(SRST_H_SPDIF, 3, 8), + RK3562_PERICRU_RESET_OFFSET(SRST_M_SPDIF, 3, 11), + + /* PERI_SOFTRST_CON04 */ + RK3562_PERICRU_RESET_OFFSET(SRST_H_SDMMC0, 4, 0), + RK3562_PERICRU_RESET_OFFSET(SRST_H_SDMMC1, 4, 2), + RK3562_PERICRU_RESET_OFFSET(SRST_H_EMMC, 4, 8), + RK3562_PERICRU_RESET_OFFSET(SRST_A_EMMC, 4, 9), + RK3562_PERICRU_RESET_OFFSET(SRST_C_EMMC, 4, 10), + RK3562_PERICRU_RESET_OFFSET(SRST_B_EMMC, 4, 11), + RK3562_PERICRU_RESET_OFFSET(SRST_T_EMMC, 4, 12), + RK3562_PERICRU_RESET_OFFSET(SRST_S_SFC, 4, 13), + RK3562_PERICRU_RESET_OFFSET(SRST_H_SFC, 4, 14), + + /* PERI_SOFTRST_CON05 */ + RK3562_PERICRU_RESET_OFFSET(SRST_H_USB2HOST, 5, 0), + RK3562_PERICRU_RESET_OFFSET(SRST_H_USB2HOST_ARB, 5, 1), + RK3562_PERICRU_RESET_OFFSET(SRST_USB2HOST_UTMI, 5, 2), + + /* PERI_SOFTRST_CON06 */ + RK3562_PERICRU_RESET_OFFSET(SRST_P_SPI1, 6, 0), + RK3562_PERICRU_RESET_OFFSET(SRST_SPI1, 6, 1), + RK3562_PERICRU_RESET_OFFSET(SRST_P_SPI2, 6, 3), + RK3562_PERICRU_RESET_OFFSET(SRST_SPI2, 6, 4), + + /* PERI_SOFTRST_CON07 */ + RK3562_PERICRU_RESET_OFFSET(SRST_P_UART1, 7, 0), + RK3562_PERICRU_RESET_OFFSET(SRST_P_UART2, 7, 1), + RK3562_PERICRU_RESET_OFFSET(SRST_P_UART3, 7, 2), + RK3562_PERICRU_RESET_OFFSET(SRST_P_UART4, 7, 3), + RK3562_PERICRU_RESET_OFFSET(SRST_P_UART5, 7, 4), + RK3562_PERICRU_RESET_OFFSET(SRST_P_UART6, 7, 5), + RK3562_PERICRU_RESET_OFFSET(SRST_P_UART7, 7, 6), + RK3562_PERICRU_RESET_OFFSET(SRST_P_UART8, 7, 7), + RK3562_PERICRU_RESET_OFFSET(SRST_P_UART9, 7, 8), + RK3562_PERICRU_RESET_OFFSET(SRST_S_UART1, 7, 11), + RK3562_PERICRU_RESET_OFFSET(SRST_S_UART2, 7, 14), + + /* PERI_SOFTRST_CON08 */ + RK3562_PERICRU_RESET_OFFSET(SRST_S_UART3, 8, 1), + RK3562_PERICRU_RESET_OFFSET(SRST_S_UART4, 8, 4), + RK3562_PERICRU_RESET_OFFSET(SRST_S_UART5, 8, 7), + RK3562_PERICRU_RESET_OFFSET(SRST_S_UART6, 8, 10), + RK3562_PERICRU_RESET_OFFSET(SRST_S_UART7, 8, 13), + + /* PERI_SOFTRST_CON09 */ + RK3562_PERICRU_RESET_OFFSET(SRST_S_UART8, 9, 0), + RK3562_PERICRU_RESET_OFFSET(SRST_S_UART9, 9, 3), + + /* PERI_SOFTRST_CON10 */ + RK3562_PERICRU_RESET_OFFSET(SRST_P_PWM1_PERI, 10, 0), + RK3562_PERICRU_RESET_OFFSET(SRST_PWM1_PERI, 10, 1), + RK3562_PERICRU_RESET_OFFSET(SRST_P_PWM2_PERI, 10, 3), + RK3562_PERICRU_RESET_OFFSET(SRST_PWM2_PERI, 10, 4), + RK3562_PERICRU_RESET_OFFSET(SRST_P_PWM3_PERI, 10, 6), + RK3562_PERICRU_RESET_OFFSET(SRST_PWM3_PERI, 10, 7), + + /* PERI_SOFTRST_CON11 */ + RK3562_PERICRU_RESET_OFFSET(SRST_P_CAN0, 11, 0), + RK3562_PERICRU_RESET_OFFSET(SRST_CAN0, 11, 1), + RK3562_PERICRU_RESET_OFFSET(SRST_P_CAN1, 11, 2), + RK3562_PERICRU_RESET_OFFSET(SRST_CAN1, 11, 3), + + /* PERI_SOFTRST_CON12 */ + RK3562_PERICRU_RESET_OFFSET(SRST_A_CRYPTO, 12, 0), + RK3562_PERICRU_RESET_OFFSET(SRST_H_CRYPTO, 12, 1), + RK3562_PERICRU_RESET_OFFSET(SRST_P_CRYPTO, 12, 2), + RK3562_PERICRU_RESET_OFFSET(SRST_CORE_CRYPTO, 12, 3), + RK3562_PERICRU_RESET_OFFSET(SRST_PKA_CRYPTO, 12, 4), + RK3562_PERICRU_RESET_OFFSET(SRST_H_KLAD, 12, 5), + RK3562_PERICRU_RESET_OFFSET(SRST_P_KEY_READER, 12, 6), + RK3562_PERICRU_RESET_OFFSET(SRST_H_RK_RNG_NS, 12, 7), + RK3562_PERICRU_RESET_OFFSET(SRST_H_RK_RNG_S, 12, 8), + RK3562_PERICRU_RESET_OFFSET(SRST_H_TRNG_NS, 12, 9), + RK3562_PERICRU_RESET_OFFSET(SRST_H_TRNG_S, 12, 10), + RK3562_PERICRU_RESET_OFFSET(SRST_H_CRYPTO_S, 12, 11), + + /* PERI_SOFTRST_CON13 */ + RK3562_PERICRU_RESET_OFFSET(SRST_P_PERI_WDT, 13, 0), + RK3562_PERICRU_RESET_OFFSET(SRST_T_PERI_WDT, 13, 1), + RK3562_PERICRU_RESET_OFFSET(SRST_A_SYSMEM, 13, 2), + RK3562_PERICRU_RESET_OFFSET(SRST_H_BOOTROM, 13, 3), + RK3562_PERICRU_RESET_OFFSET(SRST_P_PERI_GRF, 13, 4), + RK3562_PERICRU_RESET_OFFSET(SRST_A_DMAC, 13, 5), + RK3562_PERICRU_RESET_OFFSET(SRST_A_RKDMAC, 13, 6), + + /* PERI_SOFTRST_CON14 */ + RK3562_PERICRU_RESET_OFFSET(SRST_P_OTPC_NS, 14, 0), + RK3562_PERICRU_RESET_OFFSET(SRST_SBPI_OTPC_NS, 14, 1), + RK3562_PERICRU_RESET_OFFSET(SRST_USER_OTPC_NS, 14, 2), + RK3562_PERICRU_RESET_OFFSET(SRST_P_OTPC_S, 14, 3), + RK3562_PERICRU_RESET_OFFSET(SRST_SBPI_OTPC_S, 14, 4), + RK3562_PERICRU_RESET_OFFSET(SRST_USER_OTPC_S, 14, 5), + RK3562_PERICRU_RESET_OFFSET(SRST_OTPC_ARB, 14, 6), + RK3562_PERICRU_RESET_OFFSET(SRST_P_OTPPHY, 14, 7), + RK3562_PERICRU_RESET_OFFSET(SRST_OTP_NPOR, 14, 8), + + /* PERI_SOFTRST_CON15 */ + RK3562_PERICRU_RESET_OFFSET(SRST_P_USB2PHY, 15, 0), + RK3562_PERICRU_RESET_OFFSET(SRST_USB2PHY_POR, 15, 4), + RK3562_PERICRU_RESET_OFFSET(SRST_USB2PHY_OTG, 15, 5), + RK3562_PERICRU_RESET_OFFSET(SRST_USB2PHY_HOST, 15, 6), + RK3562_PERICRU_RESET_OFFSET(SRST_P_PIPEPHY, 15, 7), + + /* PERI_SOFTRST_CON16 */ + RK3562_PERICRU_RESET_OFFSET(SRST_P_SARADC, 16, 4), + RK3562_PERICRU_RESET_OFFSET(SRST_SARADC, 16, 5), + RK3562_PERICRU_RESET_OFFSET(SRST_SARADC_PHY, 16, 6), + RK3562_PERICRU_RESET_OFFSET(SRST_P_IOC_VCCIO234, 16, 12), + + /* PERI_SOFTRST_CON17 */ + RK3562_PERICRU_RESET_OFFSET(SRST_P_PERI_GPIO1, 17, 0), + RK3562_PERICRU_RESET_OFFSET(SRST_P_PERI_GPIO2, 17, 1), + RK3562_PERICRU_RESET_OFFSET(SRST_PERI_GPIO1, 17, 2), + RK3562_PERICRU_RESET_OFFSET(SRST_PERI_GPIO2, 17, 3), +}; + +void rk3562_rst_init(struct device_node *np, void __iomem *reg_base) +{ + rockchip_register_softrst_lut(np, + rk3562_register_offset, + ARRAY_SIZE(rk3562_register_offset), + reg_base + RK3562_SOFTRST_CON(0), + ROCKCHIP_SOFTRST_HIWORD_MASK); +} diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile index 90e5b114872c..b77fe288e4bb 100644 --- a/drivers/clk/samsung/Makefile +++ b/drivers/clk/samsung/Makefile @@ -17,7 +17,9 @@ obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos5433.o obj-$(CONFIG_EXYNOS_AUDSS_CLK_CON) += clk-exynos-audss.o obj-$(CONFIG_EXYNOS_CLKOUT) += clk-exynos-clkout.o obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos-arm64.o +obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos2200.o obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7.o +obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7870.o obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7885.o obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos850.o obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos8895.o diff --git a/drivers/clk/samsung/clk-cpu.c b/drivers/clk/samsung/clk-cpu.c index dfa149e648aa..97982662e1a6 100644 --- a/drivers/clk/samsung/clk-cpu.c +++ b/drivers/clk/samsung/clk-cpu.c @@ -133,7 +133,7 @@ static void wait_until_divider_stable(void __iomem *div_reg, unsigned long mask) if (!(readl(div_reg) & mask)) return; - pr_err("%s: timeout in divider stablization\n", __func__); + pr_err("%s: timeout in divider stabilization\n", __func__); } /* diff --git a/drivers/clk/samsung/clk-exynos-audss.c b/drivers/clk/samsung/clk-exynos-audss.c index e11ac67819ef..0f5ae3e8d000 100644 --- a/drivers/clk/samsung/clk-exynos-audss.c +++ b/drivers/clk/samsung/clk-exynos-audss.c @@ -11,6 +11,7 @@ #include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/of.h> +#include <linux/mod_devicetable.h> #include <linux/module.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> diff --git a/drivers/clk/samsung/clk-exynos-clkout.c b/drivers/clk/samsung/clk-exynos-clkout.c index 2ef5748c139b..5f1a4f5e2e59 100644 --- a/drivers/clk/samsung/clk-exynos-clkout.c +++ b/drivers/clk/samsung/clk-exynos-clkout.c @@ -10,6 +10,7 @@ #include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/module.h> +#include <linux/mod_devicetable.h> #include <linux/io.h> #include <linux/of.h> #include <linux/of_address.h> diff --git a/drivers/clk/samsung/clk-exynos2200.c b/drivers/clk/samsung/clk-exynos2200.c new file mode 100644 index 000000000000..eab9f5eecfa3 --- /dev/null +++ b/drivers/clk/samsung/clk-exynos2200.c @@ -0,0 +1,3928 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2025 Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> + * Author: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> + * + * Common Clock Framework support for Exynos2200 SoC. + */ + +#include <linux/clk-provider.h> +#include <linux/mod_devicetable.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include <dt-bindings/clock/samsung,exynos2200-cmu.h> + +#include "clk.h" +#include "clk-exynos-arm64.h" + +/* NOTE: Must be equal to the last clock ID increased by one */ +#define CLKS_NR_TOP (CLK_DOUT_TCXO_DIV4 + 1) +#define CLKS_NR_ALIVE (CLK_DOUT_ALIVE_DSP_NOC + 1) +#define CLKS_NR_PERIS (CLK_DOUT_PERIS_DDD_CTRL + 1) +#define CLKS_NR_CMGP (CLK_DOUT_CMGP_USI6 + 1) +#define CLKS_NR_HSI0 (CLK_DOUT_DIV_CLK_HSI0_EUSB + 1) +#define CLKS_NR_PERIC0 (CLK_DOUT_PERIC0_USI04 + 1) +#define CLKS_NR_PERIC1 (CLK_DOUT_PERIC1_USI10 + 1) +#define CLKS_NR_PERIC2 (CLK_DOUT_PERIC2_USI11 + 1) +#define CLKS_NR_UFS (CLK_MOUT_UFS_UFS_EMBD_USER + 1) +#define CLKS_NR_VTS (CLK_DOUT_CLKVTS_SERIAL_LIF_CORE + 1) + +/* ---- CMU_TOP ------------------------------------------------------------ */ + +/* Register Offset definitions for CMU_TOP (0x1a320000) */ +#define PLL_LOCKTIME_PLL_MMC 0x0 +#define PLL_LOCKTIME_PLL_SHARED0 0x4 +#define PLL_LOCKTIME_PLL_SHARED1 0x8 +#define PLL_LOCKTIME_PLL_SHARED2 0xc +#define PLL_LOCKTIME_PLL_SHARED3 0x10 +#define PLL_LOCKTIME_PLL_SHARED4 0x14 +#define PLL_LOCKTIME_PLL_SHARED_MIF 0x18 +#define PLL_CON3_PLL_MMC 0x10c +#define PLL_CON8_PLL_MMC 0x120 +#define PLL_CON3_PLL_SHARED0 0x14c +#define PLL_CON8_PLL_SHARED0 0x160 +#define PLL_CON3_PLL_SHARED1 0x18c +#define PLL_CON8_PLL_SHARED1 0x1a0 +#define PLL_CON3_PLL_SHARED2 0x1cc +#define PLL_CON8_PLL_SHARED2 0x1e0 +#define PLL_CON3_PLL_SHARED3 0x20c +#define PLL_CON8_PLL_SHARED3 0x220 +#define PLL_CON3_PLL_SHARED4 0x24c +#define PLL_CON8_PLL_SHARED4 0x260 +#define PLL_CON3_PLL_SHARED_MIF 0x28c +#define PLL_CON8_PLL_SHARED_MIF 0x2a0 +#define PLL_CON0_MUX_CP_MPLL_CLK_D2_USER 0x600 +#define PLL_CON1_MUX_CP_MPLL_CLK_D2_USER 0x604 +#define PLL_CON0_MUX_CP_MPLL_CLK_USER 0x610 +#define PLL_CON1_MUX_CP_MPLL_CLK_USER 0x614 +#define CLK_CON_MUX_CLKCMU_AUD_AUDIF0 0x1000 +#define CLK_CON_MUX_CLKCMU_AUD_AUDIF1 0x1004 +#define CLK_CON_MUX_CLKCMU_AUD_CPU 0x1008 +#define CLK_CON_MUX_CLKCMU_CPUCL0_DBG_NOC 0x100c +#define CLK_CON_MUX_CLKCMU_CPUCL0_SWITCH 0x1010 +#define CLK_CON_MUX_CLKCMU_CPUCL1_SWITCH 0x1014 +#define CLK_CON_MUX_CLKCMU_CPUCL2_SWITCH 0x1018 +#define CLK_CON_MUX_CLKCMU_DNC_NOC 0x101c +#define CLK_CON_MUX_CLKCMU_DPUB_NOC 0x1020 +#define CLK_CON_MUX_CLKCMU_DPUF_NOC 0x1024 +#define CLK_CON_MUX_CLKCMU_DSP_NOC 0x102c +#define CLK_CON_MUX_CLKCMU_DSU_SWITCH 0x1030 +#define CLK_CON_MUX_CLKCMU_G3D_SWITCH 0x1034 +#define CLK_CON_MUX_CLKCMU_GNPU_NOC 0x103c +#define CLK_CON_MUX_CLKCMU_UFS_MMC_CARD 0x1040 +#define CLK_CON_MUX_CLKCMU_M2M_NOC 0x1044 +#define CLK_CON_MUX_CLKCMU_NOCL0_NOC 0x1048 +#define CLK_CON_MUX_CLKCMU_NOCL1A_NOC 0x104c +#define CLK_CON_MUX_CLKCMU_NOCL1B_NOC0 0x1050 +#define CLK_CON_MUX_CLKCMU_NOCL1C_NOC 0x1054 +#define CLK_CON_MUX_CLKCMU_SDMA_NOC 0x1058 +#define CLK_CON_MUX_CP_HISPEEDY_CLK 0x105c +#define CLK_CON_MUX_CP_SHARED0_CLK 0x1060 +#define CLK_CON_MUX_CP_SHARED2_CLK 0x1064 +#define CLK_CON_MUX_MUX_CLKCMU_ALIVE_NOC 0x1068 +#define CLK_CON_MUX_MUX_CLKCMU_AUD_AUDIF0 0x106c +#define CLK_CON_MUX_MUX_CLKCMU_AUD_AUDIF1 0x1070 +#define CLK_CON_MUX_MUX_CLKCMU_AUD_CPU 0x1074 +#define CLK_CON_MUX_MUX_CLKCMU_AUD_NOC 0x1078 +#define CLK_CON_MUX_MUX_CLKCMU_BRP_NOC 0x107c +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0 0x1080 +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1 0x1084 +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2 0x1088 +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3 0x108c +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4 0x1090 +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5 0x1094 +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6 0x1098 +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7 0x109c +#define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST 0x10a0 +#define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_CAM 0x10a4 +#define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_CPU 0x10a8 +#define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_MIF 0x10ac +#define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_NOC 0x10b0 +#define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_NOCP 0x10b4 +#define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH 0x10b8 +#define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH 0x10bc +#define CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH 0x10c0 +#define CLK_CON_MUX_MUX_CLKCMU_CSIS_DCPHY 0x10c4 +#define CLK_CON_MUX_MUX_CLKCMU_CSIS_NOC 0x10c8 +#define CLK_CON_MUX_MUX_CLKCMU_CSIS_OIS_MCU 0x10cc +#define CLK_CON_MUX_MUX_CLKCMU_CSTAT_NOC 0x10d0 +#define CLK_CON_MUX_MUX_CLKCMU_DNC_NOC 0x10d4 +#define CLK_CON_MUX_MUX_CLKCMU_DPUB 0x10d8 +#define CLK_CON_MUX_MUX_CLKCMU_DPUB_ALT 0x10dc +#define CLK_CON_MUX_MUX_CLKCMU_DPUB_DSIM 0x10e0 +#define CLK_CON_MUX_MUX_CLKCMU_DPUF 0x10e4 +#define CLK_CON_MUX_MUX_CLKCMU_DPUF_ALT 0x10e8 +#define CLK_CON_MUX_MUX_CLKCMU_DSP_NOC 0x10f8 +#define CLK_CON_MUX_MUX_CLKCMU_DSU_SWITCH 0x10fc +#define CLK_CON_MUX_MUX_CLKCMU_G3D_NOCP 0x1100 +#define CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH 0x1104 +#define CLK_CON_MUX_MUX_CLKCMU_GNPU_NOC 0x110c +#define CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC 0x1114 +#define CLK_CON_MUX_MUX_CLKCMU_HSI0_DPOSC 0x1118 +#define CLK_CON_MUX_MUX_CLKCMU_HSI0_NOC 0x111c +#define CLK_CON_MUX_MUX_CLKCMU_HSI0_USB32DRD 0x1120 +#define CLK_CON_MUX_MUX_CLKCMU_UFS_MMC_CARD 0x1124 +#define CLK_CON_MUX_MUX_CLKCMU_HSI1_NOC 0x1128 +#define CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE 0x112c +#define CLK_CON_MUX_MUX_CLKCMU_UFS_UFS_EMBD 0x1130 +#define CLK_CON_MUX_MUX_CLKCMU_LME_LME 0x1134 +#define CLK_CON_MUX_MUX_CLKCMU_LME_NOC 0x1138 +#define CLK_CON_MUX_MUX_CLKCMU_M2M_NOC 0x1140 +#define CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC 0x1148 +#define CLK_CON_MUX_MUX_CLKCMU_MCSC_NOC 0x114c +#define CLK_CON_MUX_MUX_CLKCMU_MFC0_MFC0 0x1150 +#define CLK_CON_MUX_MUX_CLKCMU_MFC0_WFD 0x1154 +#define CLK_CON_MUX_MUX_CLKCMU_MFC1_MFC1 0x1158 +#define CLK_CON_MUX_MUX_CLKCMU_MIF_NOCP 0x115c +#define CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH 0x1160 +#define CLK_CON_MUX_MUX_CLKCMU_NOCL0_NOC 0x1164 +#define CLK_CON_MUX_MUX_CLKCMU_NOCL1A_NOC 0x1168 +#define CLK_CON_MUX_MUX_CLKCMU_NOCL1B_NOC0 0x116c +#define CLK_CON_MUX_MUX_CLKCMU_NOCL1B_NOC1 0x1170 +#define CLK_CON_MUX_MUX_CLKCMU_NOCL1C_NOC 0x1174 +#define CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP0 0x1178 +#define CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP1 0x117c +#define CLK_CON_MUX_MUX_CLKCMU_PERIC0_NOC 0x1180 +#define CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP0 0x1184 +#define CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP1 0x1188 +#define CLK_CON_MUX_MUX_CLKCMU_PERIC1_NOC 0x118c +#define CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP0 0x1190 +#define CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP1 0x1194 +#define CLK_CON_MUX_MUX_CLKCMU_PERIC2_NOC 0x1198 +#define CLK_CON_MUX_MUX_CLKCMU_PERIS_GIC 0x119c +#define CLK_CON_MUX_MUX_CLKCMU_PERIS_NOC 0x11a0 +#define CLK_CON_MUX_MUX_CLKCMU_SDMA_NOC 0x11a8 +#define CLK_CON_MUX_MUX_CLKCMU_SSP_NOC 0x11ac +#define CLK_CON_MUX_MUX_CLKCMU_VTS_DMIC 0x11b0 +#define CLK_CON_MUX_MUX_CLKCMU_YUVP_NOC 0x11b4 +#define CLK_CON_MUX_MUX_CMU_CMUREF 0x11b8 +#define CLK_CON_MUX_MUX_CP_HISPEEDY_CLK 0x11bc +#define CLK_CON_MUX_MUX_CP_SHARED0_CLK 0x11c0 +#define CLK_CON_MUX_MUX_CP_SHARED1_CLK 0x11c4 +#define CLK_CON_MUX_MUX_CP_SHARED2_CLK 0x11c8 +#define CLK_CON_MUX_CLKCMU_M2M_FRC 0x11cc +#define CLK_CON_MUX_CLKCMU_MCSC_MCSC 0x11d0 +#define CLK_CON_MUX_CLKCMU_MCSC_NOC 0x11d4 +#define CLK_CON_MUX_MUX_CLKCMU_M2M_FRC 0x11d8 +#define CLK_CON_MUX_MUX_CLKCMU_UFS_NOC 0x11dc +#define CLK_CON_DIV_CLKCMU_ALIVE_NOC 0x1800 +#define CLK_CON_DIV_CLKCMU_AUD_NOC 0x1804 +#define CLK_CON_DIV_CLKCMU_BRP_NOC 0x1808 +#define CLK_CON_DIV_CLKCMU_CMU_BOOST 0x180c +#define CLK_CON_DIV_CLKCMU_CMU_BOOST_CAM 0x1810 +#define CLK_CON_DIV_CLKCMU_CMU_BOOST_CPU 0x1814 +#define CLK_CON_DIV_CLKCMU_CMU_BOOST_MIF 0x1818 +#define CLK_CON_DIV_CLKCMU_CPUCL0_NOCP 0x181c +#define CLK_CON_DIV_CLKCMU_CSIS_DCPHY 0x1820 +#define CLK_CON_DIV_CLKCMU_CSIS_NOC 0x1824 +#define CLK_CON_DIV_CLKCMU_CSIS_OIS_MCU 0x1828 +#define CLK_CON_DIV_CLKCMU_CSTAT_NOC 0x182c +#define CLK_CON_DIV_CLKCMU_DPUB_DSIM 0x1830 +#define CLK_CON_DIV_CLKCMU_LME_LME 0x1834 +#define CLK_CON_DIV_CLKCMU_G3D_NOCP 0x1838 +#define CLK_CON_DIV_CLKCMU_HSI0_DPGTC 0x1840 +#define CLK_CON_DIV_CLKCMU_HSI0_DPOSC 0x1844 +#define CLK_CON_DIV_CLKCMU_HSI0_NOC 0x1848 +#define CLK_CON_DIV_CLKCMU_HSI0_USB32DRD 0x184c +#define CLK_CON_DIV_CLKCMU_HSI1_NOC 0x1850 +#define CLK_CON_DIV_CLKCMU_HSI1_PCIE 0x1854 +#define CLK_CON_DIV_CLKCMU_UFS_UFS_EMBD 0x1858 +#define CLK_CON_DIV_CLKCMU_LME_NOC 0x1860 +#define CLK_CON_DIV_CLKCMU_MFC0_MFC0 0x1874 +#define CLK_CON_DIV_CLKCMU_MFC0_WFD 0x1878 +#define CLK_CON_DIV_CLKCMU_MFC1_MFC1 0x187c +#define CLK_CON_DIV_CLKCMU_MIF_NOCP 0x1880 +#define CLK_CON_DIV_CLKCMU_NOCL1B_NOC1 0x1884 +#define CLK_CON_DIV_CLKCMU_PERIC0_IP0 0x1888 +#define CLK_CON_DIV_CLKCMU_PERIC0_IP1 0x188c +#define CLK_CON_DIV_CLKCMU_PERIC0_NOC 0x1890 +#define CLK_CON_DIV_CLKCMU_PERIC1_IP0 0x1894 +#define CLK_CON_DIV_CLKCMU_PERIC1_IP1 0x1898 +#define CLK_CON_DIV_CLKCMU_PERIC1_NOC 0x189c +#define CLK_CON_DIV_CLKCMU_PERIC2_IP0 0x18a0 +#define CLK_CON_DIV_CLKCMU_PERIC2_IP1 0x18a4 +#define CLK_CON_DIV_CLKCMU_PERIC2_NOC 0x18a8 +#define CLK_CON_DIV_CLKCMU_PERIS_GIC 0x18ac +#define CLK_CON_DIV_CLKCMU_PERIS_NOC 0x18b0 +#define CLK_CON_DIV_CLKCMU_SSP_NOC 0x18b8 +#define CLK_CON_DIV_CLKCMU_VTS_DMIC 0x18bc +#define CLK_CON_DIV_CLKCMU_YUVP_NOC 0x18c0 +#define CLK_CON_DIV_CP_SHARED1_CLK 0x18c4 +#define CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF0 0x18c8 +#define CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF0_SM 0x18cc +#define CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF1 0x18d0 +#define CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF1_SM 0x18d4 +#define CLK_CON_DIV_DIV_CLKCMU_AUD_CPU 0x18d8 +#define CLK_CON_DIV_DIV_CLKCMU_AUD_CPU_SM 0x18dc +#define CLK_CON_DIV_DIV_CLKCMU_CIS_CLK0 0x18e0 +#define CLK_CON_DIV_DIV_CLKCMU_CIS_CLK1 0x18e4 +#define CLK_CON_DIV_DIV_CLKCMU_CIS_CLK2 0x18e8 +#define CLK_CON_DIV_DIV_CLKCMU_CIS_CLK3 0x18ec +#define CLK_CON_DIV_DIV_CLKCMU_CIS_CLK4 0x18f0 +#define CLK_CON_DIV_DIV_CLKCMU_CIS_CLK5 0x18f4 +#define CLK_CON_DIV_DIV_CLKCMU_CIS_CLK6 0x18f8 +#define CLK_CON_DIV_DIV_CLKCMU_CIS_CLK7 0x18fc +#define CLK_CON_DIV_DIV_CLKCMU_CPUCL0_DBG_NOC 0x1900 +#define CLK_CON_DIV_DIV_CLKCMU_CPUCL0_DBG_NOC_SM 0x1904 +#define CLK_CON_DIV_DIV_CLKCMU_CPUCL0_SWITCH 0x1908 +#define CLK_CON_DIV_DIV_CLKCMU_CPUCL0_SWITCH_SM 0x190c +#define CLK_CON_DIV_DIV_CLKCMU_CPUCL1_SWITCH 0x1910 +#define CLK_CON_DIV_DIV_CLKCMU_CPUCL1_SWITCH_SM 0x1914 +#define CLK_CON_DIV_DIV_CLKCMU_CPUCL2_SWITCH 0x1918 +#define CLK_CON_DIV_DIV_CLKCMU_CPUCL2_SWITCH_SM 0x191c +#define CLK_CON_DIV_DIV_CLKCMU_DNC_NOC 0x1920 +#define CLK_CON_DIV_DIV_CLKCMU_DNC_NOC_SM 0x1924 +#define CLK_CON_DIV_DIV_CLKCMU_DPUB 0x1928 +#define CLK_CON_DIV_DIV_CLKCMU_DPUB_ALT 0x192c +#define CLK_CON_DIV_DIV_CLKCMU_DPUF 0x1930 +#define CLK_CON_DIV_DIV_CLKCMU_DPUF_ALT 0x1934 +#define CLK_CON_DIV_DIV_CLKCMU_DSP_NOC 0x1940 +#define CLK_CON_DIV_DIV_CLKCMU_DSP_NOC_SM 0x1944 +#define CLK_CON_DIV_DIV_CLKCMU_DSU_SWITCH 0x1948 +#define CLK_CON_DIV_DIV_CLKCMU_DSU_SWITCH_SM 0x194c +#define CLK_CON_DIV_DIV_CLKCMU_G3D_SWITCH 0x1950 +#define CLK_CON_DIV_DIV_CLKCMU_G3D_SWITCH_SM 0x1954 +#define CLK_CON_DIV_DIV_CLKCMU_GNPU_NOC 0x1960 +#define CLK_CON_DIV_DIV_CLKCMU_GNPU_NOC_SM 0x1964 +#define CLK_CON_DIV_DIV_CLKCMU_UFS_MMC_CARD 0x1968 +#define CLK_CON_DIV_DIV_CLKCMU_UFS_MMC_CARD_SM 0x196c +#define CLK_CON_DIV_DIV_CLKCMU_M2M_NOC 0x1970 +#define CLK_CON_DIV_DIV_CLKCMU_M2M_NOC_SM 0x1974 +#define CLK_CON_DIV_DIV_CLKCMU_NOCL0_NOC 0x1978 +#define CLK_CON_DIV_DIV_CLKCMU_NOCL0_NOC_SM 0x197c +#define CLK_CON_DIV_DIV_CLKCMU_NOCL1A_NOC 0x1980 +#define CLK_CON_DIV_DIV_CLKCMU_NOCL1A_NOC_SM 0x1984 +#define CLK_CON_DIV_DIV_CLKCMU_NOCL1B_NOC0 0x1988 +#define CLK_CON_DIV_DIV_CLKCMU_NOCL1B_NOC0_SM 0x198c +#define CLK_CON_DIV_DIV_CLKCMU_NOCL1C_NOC 0x1990 +#define CLK_CON_DIV_DIV_CLKCMU_NOCL1C_NOC_SM 0x1994 +#define CLK_CON_DIV_DIV_CLKCMU_SDMA_NOC 0x1998 +#define CLK_CON_DIV_DIV_CLKCMU_SDMA_NOC_SM 0x199c +#define CLK_CON_DIV_DIV_CP_HISPEEDY_CLK 0x19a0 +#define CLK_CON_DIV_DIV_CP_HISPEEDY_CLK_SM 0x19a4 +#define CLK_CON_DIV_DIV_CP_SHARED0_CLK 0x19a8 +#define CLK_CON_DIV_DIV_CP_SHARED0_CLK_SM 0x19ac +#define CLK_CON_DIV_DIV_CP_SHARED2_CLK 0x19b0 +#define CLK_CON_DIV_DIV_CP_SHARED2_CLK_SM 0x19b4 +#define CLK_CON_DIV_CLKCMU_UFS_NOC 0x19b8 +#define CLK_CON_DIV_DIV_CLKCMU_M2M_FRC 0x19bc +#define CLK_CON_DIV_DIV_CLKCMU_M2M_FRC_SM 0x19c0 +#define CLK_CON_DIV_DIV_CLKCMU_MCSC_MCSC 0x19c4 +#define CLK_CON_DIV_DIV_CLKCMU_MCSC_MCSC_SM 0x19c8 +#define CLK_CON_DIV_DIV_CLKCMU_MCSC_NOC 0x19cc +#define CLK_CON_DIV_DIV_CLKCMU_MCSC_NOC_SM 0x19d0 +#define CLK_CON_GAT_CLKCMU_MIF01_SWITCH 0x2000 +#define CLK_CON_GAT_CLKCMU_MIF23_SWITCH 0x2004 +#define CLK_CON_GAT_GATE_CLKCMU_ALIVE_NOC 0x200c +#define CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF0 0x2010 +#define CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF0_SM 0x2014 +#define CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF1 0x2018 +#define CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF1_SM 0x201c +#define CLK_CON_GAT_GATE_CLKCMU_AUD_CPU 0x2020 +#define CLK_CON_GAT_GATE_CLKCMU_AUD_CPU_SM 0x2024 +#define CLK_CON_GAT_GATE_CLKCMU_AUD_NOC 0x2028 +#define CLK_CON_GAT_GATE_CLKCMU_BRP_NOC 0x202c +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0 0x2030 +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1 0x2034 +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2 0x2038 +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3 0x203c +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4 0x2040 +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5 0x2044 +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6 0x2048 +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7 0x204c +#define CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST 0x2050 +#define CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_CAM 0x2054 +#define CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_CPU 0x2058 +#define CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_CPU_MIF 0x205c +#define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_NOC 0x2060 +#define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_NOC_SM 0x2064 +#define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_NOCP 0x2068 +#define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH 0x206c +#define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_SM 0x2070 +#define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH 0x2074 +#define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_SM 0x2078 +#define CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH 0x207c +#define CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH_SM 0x2080 +#define CLK_CON_GAT_GATE_CLKCMU_CSIS_DCPHY 0x2084 +#define CLK_CON_GAT_GATE_CLKCMU_CSIS_NOC 0x2088 +#define CLK_CON_GAT_GATE_CLKCMU_CSIS_OIS_MCU 0x208c +#define CLK_CON_GAT_GATE_CLKCMU_CSTAT_NOC 0x2090 +#define CLK_CON_GAT_GATE_CLKCMU_DNC_NOC 0x2094 +#define CLK_CON_GAT_GATE_CLKCMU_DNC_NOC_SM 0x2098 +#define CLK_CON_GAT_GATE_CLKCMU_DPUB 0x209c +#define CLK_CON_GAT_GATE_CLKCMU_DPUB_ALT 0x20a0 +#define CLK_CON_GAT_GATE_CLKCMU_DPUB_DSIM 0x20a4 +#define CLK_CON_GAT_GATE_CLKCMU_DPUF 0x20a8 +#define CLK_CON_GAT_GATE_CLKCMU_DPUF_ALT 0x20ac +#define CLK_CON_GAT_GATE_CLKCMU_DSP_NOC 0x20bc +#define CLK_CON_GAT_GATE_CLKCMU_DSP_NOC_SM 0x20c0 +#define CLK_CON_GAT_GATE_CLKCMU_DSU_SWITCH 0x20c4 +#define CLK_CON_GAT_GATE_CLKCMU_DSU_SWITCH_SM 0x20c8 +#define CLK_CON_GAT_GATE_CLKCMU_G3D_NOCP 0x20cc +#define CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH 0x20d0 +#define CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_SM 0x20d4 +#define CLK_CON_GAT_GATE_CLKCMU_GNPU_NOC 0x20e0 +#define CLK_CON_GAT_GATE_CLKCMU_GNPU_NOC_SM 0x20e4 +#define CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC 0x20ec +#define CLK_CON_GAT_GATE_CLKCMU_HSI0_DPOSC 0x20f0 +#define CLK_CON_GAT_GATE_CLKCMU_HSI0_NOC 0x20f4 +#define CLK_CON_GAT_GATE_CLKCMU_HSI0_USB32DRD 0x20f8 +#define CLK_CON_GAT_GATE_CLKCMU_UFS_MMC_CARD 0x20fc +#define CLK_CON_GAT_GATE_CLKCMU_UFS_MMC_CARD_SM 0x2100 +#define CLK_CON_GAT_GATE_CLKCMU_HSI1_NOC 0x2104 +#define CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE 0x2108 +#define CLK_CON_GAT_GATE_CLKCMU_UFS_UFS_EMBD 0x210c +#define CLK_CON_GAT_GATE_CLKCMU_LME_LME 0x2110 +#define CLK_CON_GAT_GATE_CLKCMU_LME_NOC 0x2114 +#define CLK_CON_GAT_GATE_CLKCMU_M2M_NOC 0x2118 +#define CLK_CON_GAT_GATE_CLKCMU_M2M_NOC_SM 0x211c +#define CLK_CON_GAT_GATE_CLKCMU_MFC0_MFC0 0x212c +#define CLK_CON_GAT_GATE_CLKCMU_MFC0_WFD 0x2130 +#define CLK_CON_GAT_GATE_CLKCMU_MFC1_MFC1 0x2134 +#define CLK_CON_GAT_GATE_CLKCMU_MIF_NOCP 0x2138 +#define CLK_CON_GAT_GATE_CLKCMU_NOCL0_NOC 0x213c +#define CLK_CON_GAT_GATE_CLKCMU_NOCL0_NOC_SM 0x2140 +#define CLK_CON_GAT_GATE_CLKCMU_NOCL1A_NOC 0x2144 +#define CLK_CON_GAT_GATE_CLKCMU_NOCL1A_NOC_SM 0x2148 +#define CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC0 0x214c +#define CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC0_SM 0x2150 +#define CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC1 0x2154 +#define CLK_CON_GAT_GATE_CLKCMU_NOCL1C_NOC 0x2158 +#define CLK_CON_GAT_GATE_CLKCMU_NOCL1C_NOC_SM 0x215c +#define CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP0 0x2160 +#define CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP1 0x2164 +#define CLK_CON_GAT_GATE_CLKCMU_PERIC0_NOC 0x2168 +#define CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP0 0x216c +#define CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP1 0x2170 +#define CLK_CON_GAT_GATE_CLKCMU_PERIC1_NOC 0x2174 +#define CLK_CON_GAT_GATE_CLKCMU_PERIC2_IP0 0x2178 +#define CLK_CON_GAT_GATE_CLKCMU_PERIC2_IP1 0x217c +#define CLK_CON_GAT_GATE_CLKCMU_PERIC2_NOC 0x2180 +#define CLK_CON_GAT_GATE_CLKCMU_PERIS_GIC 0x2184 +#define CLK_CON_GAT_GATE_CLKCMU_PERIS_NOC 0x2188 +#define CLK_CON_GAT_GATE_CLKCMU_SDMA_NOC 0x2190 +#define CLK_CON_GAT_GATE_CLKCMU_SDMA_NOC_SM 0x2194 +#define CLK_CON_GAT_GATE_CLKCMU_SSP_NOC 0x2198 +#define CLK_CON_GAT_GATE_CLKCMU_VTS_DMIC 0x219c +#define CLK_CON_GAT_GATE_CLKCMU_YUVP_NOC 0x21a0 +#define CLK_CON_GAT_GATE_CP_HISPEEDY_CLK 0x21a4 +#define CLK_CON_GAT_GATE_CP_HISPEEDY_CLK_SM 0x21a8 +#define CLK_CON_GAT_GATE_CP_SHARED0_CLK 0x21ac +#define CLK_CON_GAT_GATE_CP_SHARED0_CLK_SM 0x21b0 +#define CLK_CON_GAT_GATE_CP_SHARED1_CLK 0x21b4 +#define CLK_CON_GAT_GATE_CP_SHARED2_CLK 0x21b8 +#define CLK_CON_GAT_GATE_CP_SHARED2_CLK_SM 0x21bc +#define CLK_CON_GAT_GATE_CLKCMU_UFS_NOC 0x21c0 +#define CLK_CON_GAT_GATE_CLKCMU_M2M_FRC 0x21c4 +#define CLK_CON_GAT_GATE_CLKCMU_M2M_FRC_SM 0x21c8 +#define CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC 0x21cc +#define CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC_SM 0x21d0 +#define CLK_CON_GAT_GATE_CLKCMU_MCSC_NOC 0x21d4 +#define CLK_CON_GAT_GATE_CLKCMU_MCSC_NOC_SM 0x21d8 + +static const unsigned long top_clk_regs[] __initconst = { + PLL_LOCKTIME_PLL_MMC, + PLL_LOCKTIME_PLL_SHARED0, + PLL_LOCKTIME_PLL_SHARED1, + PLL_LOCKTIME_PLL_SHARED2, + PLL_LOCKTIME_PLL_SHARED3, + PLL_LOCKTIME_PLL_SHARED4, + PLL_LOCKTIME_PLL_SHARED_MIF, + PLL_CON3_PLL_MMC, + PLL_CON8_PLL_MMC, + PLL_CON3_PLL_SHARED0, + PLL_CON8_PLL_SHARED0, + PLL_CON3_PLL_SHARED1, + PLL_CON8_PLL_SHARED1, + PLL_CON3_PLL_SHARED2, + PLL_CON8_PLL_SHARED2, + PLL_CON3_PLL_SHARED3, + PLL_CON8_PLL_SHARED3, + PLL_CON3_PLL_SHARED4, + PLL_CON8_PLL_SHARED4, + PLL_CON3_PLL_SHARED_MIF, + PLL_CON8_PLL_SHARED_MIF, + PLL_CON0_MUX_CP_MPLL_CLK_D2_USER, + PLL_CON1_MUX_CP_MPLL_CLK_D2_USER, + PLL_CON0_MUX_CP_MPLL_CLK_USER, + PLL_CON1_MUX_CP_MPLL_CLK_USER, + CLK_CON_MUX_CLKCMU_AUD_AUDIF0, + CLK_CON_MUX_CLKCMU_AUD_AUDIF1, + CLK_CON_MUX_CLKCMU_AUD_CPU, + CLK_CON_MUX_CLKCMU_CPUCL0_DBG_NOC, + CLK_CON_MUX_CLKCMU_CPUCL0_SWITCH, + CLK_CON_MUX_CLKCMU_CPUCL1_SWITCH, + CLK_CON_MUX_CLKCMU_CPUCL2_SWITCH, + CLK_CON_MUX_CLKCMU_DNC_NOC, + CLK_CON_MUX_CLKCMU_DPUB_NOC, + CLK_CON_MUX_CLKCMU_DPUF_NOC, + CLK_CON_MUX_CLKCMU_DSP_NOC, + CLK_CON_MUX_CLKCMU_DSU_SWITCH, + CLK_CON_MUX_CLKCMU_G3D_SWITCH, + CLK_CON_MUX_CLKCMU_GNPU_NOC, + CLK_CON_MUX_CLKCMU_UFS_MMC_CARD, + CLK_CON_MUX_CLKCMU_M2M_NOC, + CLK_CON_MUX_CLKCMU_NOCL0_NOC, + CLK_CON_MUX_CLKCMU_NOCL1A_NOC, + CLK_CON_MUX_CLKCMU_NOCL1B_NOC0, + CLK_CON_MUX_CLKCMU_NOCL1C_NOC, + CLK_CON_MUX_CLKCMU_SDMA_NOC, + CLK_CON_MUX_CP_HISPEEDY_CLK, + CLK_CON_MUX_CP_SHARED0_CLK, + CLK_CON_MUX_CP_SHARED2_CLK, + CLK_CON_MUX_MUX_CLKCMU_ALIVE_NOC, + CLK_CON_MUX_MUX_CLKCMU_AUD_AUDIF0, + CLK_CON_MUX_MUX_CLKCMU_AUD_AUDIF1, + CLK_CON_MUX_MUX_CLKCMU_AUD_CPU, + CLK_CON_MUX_MUX_CLKCMU_AUD_NOC, + CLK_CON_MUX_MUX_CLKCMU_BRP_NOC, + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0, + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1, + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2, + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3, + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4, + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5, + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6, + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7, + CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST, + CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_CAM, + CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_CPU, + CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_MIF, + CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_NOC, + CLK_CON_MUX_MUX_CLKCMU_CPUCL0_NOCP, + CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH, + CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH, + CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH, + CLK_CON_MUX_MUX_CLKCMU_CSIS_DCPHY, + CLK_CON_MUX_MUX_CLKCMU_CSIS_NOC, + CLK_CON_MUX_MUX_CLKCMU_CSIS_OIS_MCU, + CLK_CON_MUX_MUX_CLKCMU_CSTAT_NOC, + CLK_CON_MUX_MUX_CLKCMU_DNC_NOC, + CLK_CON_MUX_MUX_CLKCMU_DPUB, + CLK_CON_MUX_MUX_CLKCMU_DPUB_ALT, + CLK_CON_MUX_MUX_CLKCMU_DPUB_DSIM, + CLK_CON_MUX_MUX_CLKCMU_DPUF, + CLK_CON_MUX_MUX_CLKCMU_DPUF_ALT, + CLK_CON_MUX_MUX_CLKCMU_DSP_NOC, + CLK_CON_MUX_MUX_CLKCMU_DSU_SWITCH, + CLK_CON_MUX_MUX_CLKCMU_G3D_NOCP, + CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, + CLK_CON_MUX_MUX_CLKCMU_GNPU_NOC, + CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC, + CLK_CON_MUX_MUX_CLKCMU_HSI0_DPOSC, + CLK_CON_MUX_MUX_CLKCMU_HSI0_NOC, + CLK_CON_MUX_MUX_CLKCMU_HSI0_USB32DRD, + CLK_CON_MUX_MUX_CLKCMU_UFS_MMC_CARD, + CLK_CON_MUX_MUX_CLKCMU_HSI1_NOC, + CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE, + CLK_CON_MUX_MUX_CLKCMU_UFS_UFS_EMBD, + CLK_CON_MUX_MUX_CLKCMU_LME_LME, + CLK_CON_MUX_MUX_CLKCMU_LME_NOC, + CLK_CON_MUX_MUX_CLKCMU_M2M_NOC, + CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC, + CLK_CON_MUX_MUX_CLKCMU_MCSC_NOC, + CLK_CON_MUX_MUX_CLKCMU_MFC0_MFC0, + CLK_CON_MUX_MUX_CLKCMU_MFC0_WFD, + CLK_CON_MUX_MUX_CLKCMU_MFC1_MFC1, + CLK_CON_MUX_MUX_CLKCMU_MIF_NOCP, + CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, + CLK_CON_MUX_MUX_CLKCMU_NOCL0_NOC, + CLK_CON_MUX_MUX_CLKCMU_NOCL1A_NOC, + CLK_CON_MUX_MUX_CLKCMU_NOCL1B_NOC0, + CLK_CON_MUX_MUX_CLKCMU_NOCL1B_NOC1, + CLK_CON_MUX_MUX_CLKCMU_NOCL1C_NOC, + CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP0, + CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP1, + CLK_CON_MUX_MUX_CLKCMU_PERIC0_NOC, + CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP0, + CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP1, + CLK_CON_MUX_MUX_CLKCMU_PERIC1_NOC, + CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP0, + CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP1, + CLK_CON_MUX_MUX_CLKCMU_PERIC2_NOC, + CLK_CON_MUX_MUX_CLKCMU_PERIS_GIC, + CLK_CON_MUX_MUX_CLKCMU_PERIS_NOC, + CLK_CON_MUX_MUX_CLKCMU_SDMA_NOC, + CLK_CON_MUX_MUX_CLKCMU_SSP_NOC, + CLK_CON_MUX_MUX_CLKCMU_VTS_DMIC, + CLK_CON_MUX_MUX_CLKCMU_YUVP_NOC, + CLK_CON_MUX_MUX_CMU_CMUREF, + CLK_CON_MUX_MUX_CP_HISPEEDY_CLK, + CLK_CON_MUX_MUX_CP_SHARED0_CLK, + CLK_CON_MUX_MUX_CP_SHARED1_CLK, + CLK_CON_MUX_MUX_CP_SHARED2_CLK, + CLK_CON_MUX_CLKCMU_M2M_FRC, + CLK_CON_MUX_CLKCMU_MCSC_MCSC, + CLK_CON_MUX_CLKCMU_MCSC_NOC, + CLK_CON_MUX_MUX_CLKCMU_M2M_FRC, + CLK_CON_MUX_MUX_CLKCMU_UFS_NOC, + CLK_CON_DIV_CLKCMU_ALIVE_NOC, + CLK_CON_DIV_CLKCMU_AUD_NOC, + CLK_CON_DIV_CLKCMU_BRP_NOC, + CLK_CON_DIV_CLKCMU_CMU_BOOST, + CLK_CON_DIV_CLKCMU_CMU_BOOST_CAM, + CLK_CON_DIV_CLKCMU_CMU_BOOST_CPU, + CLK_CON_DIV_CLKCMU_CMU_BOOST_MIF, + CLK_CON_DIV_CLKCMU_CPUCL0_NOCP, + CLK_CON_DIV_CLKCMU_CSIS_DCPHY, + CLK_CON_DIV_CLKCMU_CSIS_NOC, + CLK_CON_DIV_CLKCMU_CSIS_OIS_MCU, + CLK_CON_DIV_CLKCMU_CSTAT_NOC, + CLK_CON_DIV_CLKCMU_DPUB_DSIM, + CLK_CON_DIV_CLKCMU_LME_LME, + CLK_CON_DIV_CLKCMU_G3D_NOCP, + CLK_CON_DIV_CLKCMU_HSI0_DPGTC, + CLK_CON_DIV_CLKCMU_HSI0_DPOSC, + CLK_CON_DIV_CLKCMU_HSI0_NOC, + CLK_CON_DIV_CLKCMU_HSI0_USB32DRD, + CLK_CON_DIV_CLKCMU_HSI1_NOC, + CLK_CON_DIV_CLKCMU_HSI1_PCIE, + CLK_CON_DIV_CLKCMU_UFS_UFS_EMBD, + CLK_CON_DIV_CLKCMU_LME_NOC, + CLK_CON_DIV_CLKCMU_MFC0_MFC0, + CLK_CON_DIV_CLKCMU_MFC0_WFD, + CLK_CON_DIV_CLKCMU_MFC1_MFC1, + CLK_CON_DIV_CLKCMU_MIF_NOCP, + CLK_CON_DIV_CLKCMU_NOCL1B_NOC1, + CLK_CON_DIV_CLKCMU_PERIC0_IP0, + CLK_CON_DIV_CLKCMU_PERIC0_IP1, + CLK_CON_DIV_CLKCMU_PERIC0_NOC, + CLK_CON_DIV_CLKCMU_PERIC1_IP0, + CLK_CON_DIV_CLKCMU_PERIC1_IP1, + CLK_CON_DIV_CLKCMU_PERIC1_NOC, + CLK_CON_DIV_CLKCMU_PERIC2_IP0, + CLK_CON_DIV_CLKCMU_PERIC2_IP1, + CLK_CON_DIV_CLKCMU_PERIC2_NOC, + CLK_CON_DIV_CLKCMU_PERIS_GIC, + CLK_CON_DIV_CLKCMU_PERIS_NOC, + CLK_CON_DIV_CLKCMU_SSP_NOC, + CLK_CON_DIV_CLKCMU_VTS_DMIC, + CLK_CON_DIV_CLKCMU_YUVP_NOC, + CLK_CON_DIV_CP_SHARED1_CLK, + CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF0, + CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF0_SM, + CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF1, + CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF1_SM, + CLK_CON_DIV_DIV_CLKCMU_AUD_CPU, + CLK_CON_DIV_DIV_CLKCMU_AUD_CPU_SM, + CLK_CON_DIV_DIV_CLKCMU_CIS_CLK0, + CLK_CON_DIV_DIV_CLKCMU_CIS_CLK1, + CLK_CON_DIV_DIV_CLKCMU_CIS_CLK2, + CLK_CON_DIV_DIV_CLKCMU_CIS_CLK3, + CLK_CON_DIV_DIV_CLKCMU_CIS_CLK4, + CLK_CON_DIV_DIV_CLKCMU_CIS_CLK5, + CLK_CON_DIV_DIV_CLKCMU_CIS_CLK6, + CLK_CON_DIV_DIV_CLKCMU_CIS_CLK7, + CLK_CON_DIV_DIV_CLKCMU_CPUCL0_DBG_NOC, + CLK_CON_DIV_DIV_CLKCMU_CPUCL0_DBG_NOC_SM, + CLK_CON_DIV_DIV_CLKCMU_CPUCL0_SWITCH, + CLK_CON_DIV_DIV_CLKCMU_CPUCL0_SWITCH_SM, + CLK_CON_DIV_DIV_CLKCMU_CPUCL1_SWITCH, + CLK_CON_DIV_DIV_CLKCMU_CPUCL1_SWITCH_SM, + CLK_CON_DIV_DIV_CLKCMU_CPUCL2_SWITCH, + CLK_CON_DIV_DIV_CLKCMU_CPUCL2_SWITCH_SM, + CLK_CON_DIV_DIV_CLKCMU_DNC_NOC, + CLK_CON_DIV_DIV_CLKCMU_DNC_NOC_SM, + CLK_CON_DIV_DIV_CLKCMU_DPUB, + CLK_CON_DIV_DIV_CLKCMU_DPUB_ALT, + CLK_CON_DIV_DIV_CLKCMU_DPUF, + CLK_CON_DIV_DIV_CLKCMU_DPUF_ALT, + CLK_CON_DIV_DIV_CLKCMU_DSP_NOC, + CLK_CON_DIV_DIV_CLKCMU_DSP_NOC_SM, + CLK_CON_DIV_DIV_CLKCMU_DSU_SWITCH, + CLK_CON_DIV_DIV_CLKCMU_DSU_SWITCH_SM, + CLK_CON_DIV_DIV_CLKCMU_G3D_SWITCH, + CLK_CON_DIV_DIV_CLKCMU_G3D_SWITCH_SM, + CLK_CON_DIV_DIV_CLKCMU_GNPU_NOC, + CLK_CON_DIV_DIV_CLKCMU_GNPU_NOC_SM, + CLK_CON_DIV_DIV_CLKCMU_UFS_MMC_CARD, + CLK_CON_DIV_DIV_CLKCMU_UFS_MMC_CARD_SM, + CLK_CON_DIV_DIV_CLKCMU_M2M_NOC, + CLK_CON_DIV_DIV_CLKCMU_M2M_NOC_SM, + CLK_CON_DIV_DIV_CLKCMU_NOCL0_NOC, + CLK_CON_DIV_DIV_CLKCMU_NOCL0_NOC_SM, + CLK_CON_DIV_DIV_CLKCMU_NOCL1A_NOC, + CLK_CON_DIV_DIV_CLKCMU_NOCL1A_NOC_SM, + CLK_CON_DIV_DIV_CLKCMU_NOCL1B_NOC0, + CLK_CON_DIV_DIV_CLKCMU_NOCL1B_NOC0_SM, + CLK_CON_DIV_DIV_CLKCMU_NOCL1C_NOC, + CLK_CON_DIV_DIV_CLKCMU_NOCL1C_NOC_SM, + CLK_CON_DIV_DIV_CLKCMU_SDMA_NOC, + CLK_CON_DIV_DIV_CLKCMU_SDMA_NOC_SM, + CLK_CON_DIV_DIV_CP_HISPEEDY_CLK, + CLK_CON_DIV_DIV_CP_HISPEEDY_CLK_SM, + CLK_CON_DIV_DIV_CP_SHARED0_CLK, + CLK_CON_DIV_DIV_CP_SHARED0_CLK_SM, + CLK_CON_DIV_DIV_CP_SHARED2_CLK, + CLK_CON_DIV_DIV_CP_SHARED2_CLK_SM, + CLK_CON_DIV_CLKCMU_UFS_NOC, + CLK_CON_DIV_DIV_CLKCMU_M2M_FRC, + CLK_CON_DIV_DIV_CLKCMU_M2M_FRC_SM, + CLK_CON_DIV_DIV_CLKCMU_MCSC_MCSC, + CLK_CON_DIV_DIV_CLKCMU_MCSC_MCSC_SM, + CLK_CON_DIV_DIV_CLKCMU_MCSC_NOC, + CLK_CON_DIV_DIV_CLKCMU_MCSC_NOC_SM, + CLK_CON_GAT_CLKCMU_MIF01_SWITCH, + CLK_CON_GAT_CLKCMU_MIF23_SWITCH, + CLK_CON_GAT_GATE_CLKCMU_ALIVE_NOC, + CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF0, + CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF0_SM, + CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF1, + CLK_CON_GAT_GATE_CLKCMU_AUD_AUDIF1_SM, + CLK_CON_GAT_GATE_CLKCMU_AUD_CPU, + CLK_CON_GAT_GATE_CLKCMU_AUD_CPU_SM, + CLK_CON_GAT_GATE_CLKCMU_AUD_NOC, + CLK_CON_GAT_GATE_CLKCMU_BRP_NOC, + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0, + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1, + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2, + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3, + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4, + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5, + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6, + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7, + CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST, + CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_CAM, + CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_CPU, + CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_CPU_MIF, + CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_NOC, + CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_NOC_SM, + CLK_CON_GAT_GATE_CLKCMU_CPUCL0_NOCP, + CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH, + CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_SM, + CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH, + CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_SM, + CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH, + CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH_SM, + CLK_CON_GAT_GATE_CLKCMU_CSIS_DCPHY, + CLK_CON_GAT_GATE_CLKCMU_CSIS_NOC, + CLK_CON_GAT_GATE_CLKCMU_CSIS_OIS_MCU, + CLK_CON_GAT_GATE_CLKCMU_CSTAT_NOC, + CLK_CON_GAT_GATE_CLKCMU_DNC_NOC, + CLK_CON_GAT_GATE_CLKCMU_DNC_NOC_SM, + CLK_CON_GAT_GATE_CLKCMU_DPUB, + CLK_CON_GAT_GATE_CLKCMU_DPUB_ALT, + CLK_CON_GAT_GATE_CLKCMU_DPUB_DSIM, + CLK_CON_GAT_GATE_CLKCMU_DPUF, + CLK_CON_GAT_GATE_CLKCMU_DPUF_ALT, + CLK_CON_GAT_GATE_CLKCMU_DSP_NOC, + CLK_CON_GAT_GATE_CLKCMU_DSP_NOC_SM, + CLK_CON_GAT_GATE_CLKCMU_DSU_SWITCH, + CLK_CON_GAT_GATE_CLKCMU_DSU_SWITCH_SM, + CLK_CON_GAT_GATE_CLKCMU_G3D_NOCP, + CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH, + CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_SM, + CLK_CON_GAT_GATE_CLKCMU_GNPU_NOC, + CLK_CON_GAT_GATE_CLKCMU_GNPU_NOC_SM, + CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC, + CLK_CON_GAT_GATE_CLKCMU_HSI0_DPOSC, + CLK_CON_GAT_GATE_CLKCMU_HSI0_NOC, + CLK_CON_GAT_GATE_CLKCMU_HSI0_USB32DRD, + CLK_CON_GAT_GATE_CLKCMU_UFS_MMC_CARD, + CLK_CON_GAT_GATE_CLKCMU_UFS_MMC_CARD_SM, + CLK_CON_GAT_GATE_CLKCMU_HSI1_NOC, + CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE, + CLK_CON_GAT_GATE_CLKCMU_UFS_UFS_EMBD, + CLK_CON_GAT_GATE_CLKCMU_LME_LME, + CLK_CON_GAT_GATE_CLKCMU_LME_NOC, + CLK_CON_GAT_GATE_CLKCMU_M2M_NOC, + CLK_CON_GAT_GATE_CLKCMU_M2M_NOC_SM, + CLK_CON_GAT_GATE_CLKCMU_MFC0_MFC0, + CLK_CON_GAT_GATE_CLKCMU_MFC0_WFD, + CLK_CON_GAT_GATE_CLKCMU_MFC1_MFC1, + CLK_CON_GAT_GATE_CLKCMU_MIF_NOCP, + CLK_CON_GAT_GATE_CLKCMU_NOCL0_NOC, + CLK_CON_GAT_GATE_CLKCMU_NOCL0_NOC_SM, + CLK_CON_GAT_GATE_CLKCMU_NOCL1A_NOC, + CLK_CON_GAT_GATE_CLKCMU_NOCL1A_NOC_SM, + CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC0, + CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC0_SM, + CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC1, + CLK_CON_GAT_GATE_CLKCMU_NOCL1C_NOC, + CLK_CON_GAT_GATE_CLKCMU_NOCL1C_NOC_SM, + CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP0, + CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP1, + CLK_CON_GAT_GATE_CLKCMU_PERIC0_NOC, + CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP0, + CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP1, + CLK_CON_GAT_GATE_CLKCMU_PERIC1_NOC, + CLK_CON_GAT_GATE_CLKCMU_PERIC2_IP0, + CLK_CON_GAT_GATE_CLKCMU_PERIC2_IP1, + CLK_CON_GAT_GATE_CLKCMU_PERIC2_NOC, + CLK_CON_GAT_GATE_CLKCMU_PERIS_GIC, + CLK_CON_GAT_GATE_CLKCMU_PERIS_NOC, + CLK_CON_GAT_GATE_CLKCMU_SDMA_NOC, + CLK_CON_GAT_GATE_CLKCMU_SDMA_NOC_SM, + CLK_CON_GAT_GATE_CLKCMU_SSP_NOC, + CLK_CON_GAT_GATE_CLKCMU_VTS_DMIC, + CLK_CON_GAT_GATE_CLKCMU_YUVP_NOC, + CLK_CON_GAT_GATE_CP_HISPEEDY_CLK, + CLK_CON_GAT_GATE_CP_HISPEEDY_CLK_SM, + CLK_CON_GAT_GATE_CP_SHARED0_CLK, + CLK_CON_GAT_GATE_CP_SHARED0_CLK_SM, + CLK_CON_GAT_GATE_CP_SHARED1_CLK, + CLK_CON_GAT_GATE_CP_SHARED2_CLK, + CLK_CON_GAT_GATE_CP_SHARED2_CLK_SM, + CLK_CON_GAT_GATE_CLKCMU_UFS_NOC, + CLK_CON_GAT_GATE_CLKCMU_M2M_FRC, + CLK_CON_GAT_GATE_CLKCMU_M2M_FRC_SM, + CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC, + CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC_SM, + CLK_CON_GAT_GATE_CLKCMU_MCSC_NOC, + CLK_CON_GAT_GATE_CLKCMU_MCSC_NOC_SM, +}; + +/* List of parent clocks for Muxes in CMU_TOP */ +PNAME(mout_cmu_cp_mpll_clk_d2_user_parents) = { "oscclk" }; +PNAME(mout_cmu_cp_mpll_clk_user_parents) = { "oscclk" }; +PNAME(mout_cmu_aud_audif0_p) = { "dout_shared0_div1", + "dout_shared1_div1", + "dout_shared3_div1", + "dout_shared4_div1", + "mout_cmu_cp_mpll_clk_d2_user", + "oscclk", "oscclk", + "oscclk" }; +PNAME(mout_cmu_aud_audif1_p) = { "dout_shared0_div1", + "dout_shared1_div1", + "dout_shared3_div1", + "dout_shared4_div1", + "mout_cmu_cp_mpll_clk_d2_user", + "oscclk", "oscclk", + "oscclk" }; +PNAME(mout_cmu_aud_cpu_p) = { "dout_shared0_div1", + "dout_shared1_div1", + "dout_shared2_div1", + "dout_shared3_div1", + "dout_shared4_div1", + "dout_shared0_div2", + "dout_shared1_div2", + "mout_cmu_cp_mpll_clk_d2_user" }; +PNAME(mout_cmu_cpucl0_dbg_noc_p) = { "dout_shared2_div1", + "dout_shared4_div1", + "dout_shared0_div2", + "dout_shared1_div2" }; +PNAME(mout_cmu_cpucl0_switch_p) = { "dout_shared0_div1", + "dout_shared1_div1", + "dout_shared2_div1", + "dout_shared3_div1", + "dout_shared4_div1", + "dout_shared0_div2", + "oscclk", "oscclk" }; +PNAME(mout_cmu_cpucl1_switch_p) = { "dout_shared0_div1", + "dout_shared1_div1", + "dout_shared2_div1", + "dout_shared3_div1", + "dout_shared4_div1", + "dout_shared0_div2", + "oscclk", "oscclk" }; +PNAME(mout_cmu_cpucl2_switch_p) = { "dout_shared0_div1", + "dout_shared1_div1", + "dout_shared2_div1", + "dout_shared3_div1", + "dout_shared4_div1", + "dout_shared0_div2", + "oscclk", "oscclk" }; +PNAME(mout_cmu_dnc_noc_p) = { "dout_shared0_div1", + "dout_shared1_div1", + "dout_shared2_div1", + "dout_shared3_div1", + "dout_shared4_div1", + "dout_shared0_div2", + "dout_shared1_div2", + "oscclk" }; +PNAME(mout_cmu_dpub_noc_p) = { "dout_cmu_div_dpub", + "dout_cmu_div_dpub_alt"}; +PNAME(mout_cmu_dpuf_noc_p) = { "dout_cmu_div_dpuf", + "dout_cmu_div_dpuf_alt" }; +PNAME(mout_cmu_dsp_noc_p) = { "dout_shared0_div1", + "dout_shared1_div1", + "dout_shared2_div1", + "dout_shared3_div1", + "dout_shared4_div1", + "dout_shared0_div2", + "dout_shared1_div2", + "oscclk" }; +PNAME(mout_cmu_dsu_switch_p) = { "dout_shared0_div1", + "dout_shared1_div1", + "dout_shared2_div1", + "dout_shared3_div1", + "dout_shared4_div1", + "dout_shared0_div2", + "oscclk", "oscclk" }; +PNAME(mout_cmu_g3d_switch_p) = { "dout_shared0_div1", + "dout_shared1_div1", + "dout_shared2_div1", + "dout_shared3_div1", + "dout_shared4_div1", + "dout_shared0_div2", + "dout_shared1_div2", + "dout_shared2_div2" }; +PNAME(mout_cmu_gnpu_noc_p) = { "dout_shared0_div1", + "dout_shared1_div1", + "dout_shared2_div1", + "dout_shared3_div1", + "dout_shared4_div1", + "dout_shared0_div2", + "dout_shared1_div2", + "oscclk" }; +PNAME(mout_cmu_ufs_mmc_card_p) = { "oscclk", + "dout_shared2_div1", + "dout_mmc_div1", + "dout_shared0_div2" }; +PNAME(mout_cmu_m2m_noc_p) = { "dout_shared2_div1", + "dout_shared3_div1", + "dout_shared4_div1", + "dout_shared0_div2", + "dout_shared1_div2", + "dout_shared2_div2", + "dout_shared3_div2", + "oscclk" }; +PNAME(mout_cmu_nocl0_noc_p) = { "dout_shared0_div1", + "dout_shared1_div1", + "dout_shared2_div1", + "dout_shared3_div1", + "dout_shared4_div1", + "dout_shared0_div2", + "mout_cmu_cp_mpll_clk_d2_user", + "dout_shared_mif_div2" }; +PNAME(mout_cmu_nocl1a_noc_p) = { "dout_shared2_div1", + "dout_shared3_div1", + "dout_shared4_div1", + "dout_shared0_div2", + "dout_shared1_div2", + "dout_shared2_div2", + "dout_shared3_div2", + "dout_shared4_div2" }; +PNAME(mout_cmu_nocl1b_noc0_p) = { "dout_shared2_div1", + "dout_shared3_div1", + "dout_shared4_div1", + "dout_shared0_div2", + "dout_shared1_div2", + "dout_shared2_div2", + "dout_shared3_div2", + "dout_shared4_div2" }; +PNAME(mout_cmu_nocl1c_noc_p) = { "dout_shared2_div1", + "dout_shared3_div1", + "dout_shared4_div1", + "dout_shared0_div2", + "dout_shared1_div2", + "dout_shared2_div2", + "dout_shared3_div2", + "dout_shared4_div2" }; +PNAME(mout_cmu_sdma_noc_p) = { "dout_shared0_div1", + "dout_shared1_div1", + "dout_shared2_div1", + "dout_shared3_div1", + "dout_shared4_div1", + "dout_shared0_div2", + "dout_shared1_div2", + "oscclk" }; +PNAME(mout_cmu_cp_hispeedy_clk_p) = { "dout_shared2_div1", + "dout_shared3_div1" }; +PNAME(mout_cmu_cp_shared0_clk_p) = { "dout_shared0_div1", + "dout_shared1_div1", + "dout_shared2_div1", + "dout_shared3_div1" }; +PNAME(mout_cmu_cp_shared2_clk_p) = { "dout_shared2_div1", + "dout_shared3_div1", + "dout_shared4_div1", + "dout_shared1_div2" }; +PNAME(mout_cmu_mux_alive_noc_p) = { "dout_shared0_div2", + "dout_shared2_div2" }; +PNAME(mout_cmu_mux_aud_audif0_p) = { "dout_shared0_div1", + "dout_shared1_div1", + "dout_shared3_div1", + "dout_shared4_div1", + "mout_cmu_cp_mpll_clk_d2_user", + "oscclk", "oscclk", + "oscclk" }; +PNAME(mout_cmu_mux_aud_audif1_p) = { "dout_shared0_div1", + "dout_shared1_div1", + "dout_shared3_div1", + "dout_shared4_div1", + "mout_cmu_cp_mpll_clk_d2_user", + "oscclk", "oscclk", + "oscclk" }; +PNAME(mout_cmu_mux_aud_cpu_p) = { "dout_shared0_div1", + "dout_shared1_div1", + "dout_shared2_div1", + "dout_shared3_div1", + "dout_shared4_div1", + "dout_shared0_div2", + "dout_shared1_div2", + "mout_cmu_cp_mpll_clk_d2_user" }; +PNAME(mout_cmu_mux_aud_noc_p) = { "dout_shared4_div1", + "dout_shared0_div2", + "dout_shared1_div2", + "dout_shared2_div2", + "dout_shared3_div2", + "mout_cmu_cp_mpll_clk_d2_user", + "oscclk", "oscclk" }; +PNAME(mout_cmu_mux_brp_noc_p) = { "dout_shared2_div1", + "dout_shared3_div1", + "dout_shared4_div1", + "dout_shared0_div2", + "dout_shared1_div2", + "dout_shared2_div2", + "dout_shared3_div2", + "oscclk" }; +PNAME(mout_cmu_mux_cis_clk0_p) = { "oscclk", + "dout_shared2_div2" }; +PNAME(mout_cmu_mux_cis_clk1_p) = { "oscclk", + "dout_shared2_div2" }; +PNAME(mout_cmu_mux_cis_clk2_p) = { "oscclk", + "dout_shared2_div2" }; +PNAME(mout_cmu_mux_cis_clk3_p) = { "oscclk", + "dout_shared2_div2" }; +PNAME(mout_cmu_mux_cis_clk4_p) = { "oscclk", + "dout_shared2_div2" }; +PNAME(mout_cmu_mux_cis_clk5_p) = { "oscclk", + "dout_shared2_div2" }; +PNAME(mout_cmu_mux_cis_clk6_p) = { "oscclk", + "dout_shared2_div2" }; +PNAME(mout_cmu_mux_cis_clk7_p) = { "oscclk", + "dout_shared2_div2" }; +PNAME(mout_cmu_mux_cmu_boost_p) = { "dout_shared0_div2", + "dout_shared1_div2", + "dout_shared2_div2", + "dout_shared4_div2" }; +PNAME(mout_cmu_mux_cmu_boost_cam_p) = { "dout_shared0_div2", + "dout_shared1_div2", + "dout_shared2_div2", + "dout_shared4_div2" }; +PNAME(mout_cmu_mux_cmu_boost_cpu_p) = { "dout_shared0_div2", + "dout_shared1_div2", + "dout_shared2_div2", + "dout_shared4_div2" }; +PNAME(mout_cmu_mux_cmu_boost_mif_p) = { "dout_shared0_div2", + "dout_shared1_div2", + "dout_shared2_div2", + "dout_shared4_div2" }; +PNAME(mout_cmu_mux_cpucl0_dbg_noc_p) = { "dout_shared2_div1", + "dout_shared4_div1", + "dout_shared0_div2", + "dout_shared1_div2" }; +PNAME(mout_cmu_mux_cpucl0_nocp_p) = { "dout_shared0_div2", + "dout_shared1_div2", + "dout_shared2_div2", + "dout_shared4_div2" }; +PNAME(mout_cmu_mux_cpucl0_switch_p) = { "dout_shared0_div1", + "dout_shared1_div1", + "dout_shared2_div1", + "dout_shared3_div1", + "dout_shared4_div1", + "dout_shared0_div2", + "oscclk", "oscclk" }; +PNAME(mout_cmu_mux_cpucl1_switch_p) = { "dout_shared0_div1", + "dout_shared1_div1", + "dout_shared2_div1", + "dout_shared3_div1", + "dout_shared4_div1", + "dout_shared0_div2", + "oscclk", "oscclk" }; +PNAME(mout_cmu_mux_cpucl2_switch_p) = { "dout_shared0_div1", + "dout_shared1_div1", + "dout_shared2_div1", + "dout_shared3_div1", + "dout_shared4_div1", + "dout_shared0_div2", + "oscclk", "oscclk" }; +PNAME(mout_cmu_mux_csis_dcphy_p) = { "dout_shared0_div2", + "dout_shared1_div2", + "dout_shared2_div2", + "dout_shared4_div2" }; +PNAME(mout_cmu_mux_csis_noc_p) = { "dout_shared2_div1", + "dout_shared3_div1", + "dout_shared4_div1", + "dout_shared0_div2", + "dout_shared1_div2", + "dout_shared2_div2", + "dout_shared3_div2", + "oscclk" }; +PNAME(mout_cmu_mux_csis_ois_mcu_p) = { "dout_shared0_div2", + "dout_shared2_div2" }; +PNAME(mout_cmu_mux_cstat_noc_p) = { "dout_shared2_div1", + "dout_shared3_div1", + "dout_shared4_div1", + "dout_shared0_div2", + "dout_shared1_div2", + "dout_shared2_div2", + "dout_shared3_div2", + "oscclk" }; +PNAME(mout_cmu_mux_dnc_noc_p) = { "dout_shared0_div1", + "dout_shared1_div1", + "dout_shared2_div1", + "dout_shared3_div1", + "dout_shared4_div1", + "dout_shared0_div2", + "dout_shared1_div2", + "oscclk" }; +PNAME(mout_cmu_mux_dpub_p) = { "dout_shared2_div1", + "dout_shared3_div1", + "dout_shared4_div1", + "dout_shared0_div2", + "dout_shared1_div2", + "dout_shared2_div2", + "oscclk", "oscclk" }; +PNAME(mout_cmu_mux_dpub_alt_p) = { "dout_shared2_div1", + "dout_shared3_div1", + "dout_shared4_div1", + "dout_shared0_div2", + "dout_shared1_div2", + "dout_shared2_div2", + "oscclk", "oscclk" }; +PNAME(mout_cmu_mux_dpub_dsim_p) = { "dout_shared0_div2", + "dout_shared1_div2", + "dout_shared2_div2", + "dout_shared3_div2" }; +PNAME(mout_cmu_mux_dpuf_p) = { "dout_shared2_div1", + "dout_shared3_div1", + "dout_shared4_div1", + "dout_shared0_div2", + "dout_shared1_div2", + "dout_shared2_div2", + "oscclk", "oscclk" }; +PNAME(mout_cmu_mux_dpuf_alt_p) = { "dout_shared2_div1", + "dout_shared3_div1", + "dout_shared4_div1", + "dout_shared0_div2", + "dout_shared1_div2", + "dout_shared2_div2", + "oscclk", "oscclk" }; +PNAME(mout_cmu_mux_dsp_noc_p) = { "dout_shared0_div1", + "dout_shared1_div1", + "dout_shared2_div1", + "dout_shared3_div1", + "dout_shared4_div1", + "dout_shared0_div2", + "dout_shared1_div2", + "oscclk" }; +PNAME(mout_cmu_mux_dsu_switch_p) = { "dout_shared0_div1", + "dout_shared1_div1", + "dout_shared2_div1", + "dout_shared3_div1", + "dout_shared4_div1", + "dout_shared0_div2", + "oscclk", "oscclk" }; +PNAME(mout_cmu_mux_g3d_nocp_p) = { "dout_shared0_div2", + "dout_shared1_div2", + "dout_shared2_div2", + "dout_shared4_div2" }; +PNAME(mout_cmu_mux_g3d_switch_p) = { "dout_shared0_div1", + "dout_shared1_div1", + "dout_shared2_div1", + "dout_shared3_div1", + "dout_shared4_div1", + "dout_shared0_div2", + "dout_shared1_div2", + "dout_shared2_div2" }; +PNAME(mout_cmu_mux_gnpu_noc_p) = { "dout_shared0_div1", + "dout_shared1_div1", + "dout_shared2_div1", + "dout_shared3_div1", + "dout_shared4_div1", + "dout_shared0_div2", + "dout_shared1_div2", + "oscclk" }; +PNAME(mout_cmu_mux_hsi0_dpgtc_p) = { "oscclk", + "dout_shared0_div2", + "dout_shared2_div2", + "dout_shared4_div2" }; +PNAME(mout_cmu_mux_hsi0_dposc_p) = { "oscclk", + "dout_shared2_div1" }; +PNAME(mout_cmu_mux_hsi0_noc_p) = { "dout_shared0_div2", + "dout_shared2_div2", + "dout_shared3_div2", + "dout_shared4_div2" }; +PNAME(mout_cmu_mux_hsi0_usb32drd_p) = { "oscclk", + "dout_shared0_div2", + "dout_shared2_div2", + "dout_shared4_div2" }; +PNAME(mout_cmu_mux_ufs_mmc_card_p) = { "oscclk", + "dout_shared2_div1", + "dout_mmc_div1", + "dout_shared0_div2" }; +PNAME(mout_cmu_mux_hsi1_noc_p) = { "dout_shared0_div2", + "dout_shared1_div2", + "dout_shared2_div2", + "dout_shared4_div2" }; +PNAME(mout_cmu_mux_hsi1_pcie_p) = { "oscclk", + "dout_shared2_div1" }; +PNAME(mout_cmu_mux_ufs_ufs_embd_p) = { "oscclk", + "dout_shared0_div2", + "dout_shared2_div2", + "dout_shared4_div2" }; +PNAME(mout_cmu_mux_lme_lme_p) = { "dout_shared2_div1", + "dout_shared3_div1", + "dout_shared4_div1", + "dout_shared0_div2", + "dout_shared1_div2", + "dout_shared2_div2", + "dout_shared3_div2", + "oscclk" }; +PNAME(mout_cmu_mux_lme_noc_p) = { "dout_shared2_div1", + "dout_shared3_div1", + "dout_shared4_div1", + "dout_shared0_div2", + "dout_shared1_div2", + "dout_shared2_div2", + "dout_shared3_div2", + "oscclk" }; +PNAME(mout_cmu_mux_m2m_noc_p) = { "dout_shared2_div1", + "dout_shared3_div1", + "dout_shared4_div1", + "dout_shared0_div2", + "dout_shared1_div2", + "dout_shared2_div2", + "dout_shared3_div2", + "oscclk" }; +PNAME(mout_cmu_mux_mcsc_mcsc_p) = { "dout_shared2_div1", + "dout_shared3_div1", + "dout_shared4_div1", + "dout_shared0_div2", + "dout_shared1_div2", + "dout_shared2_div2", + "dout_shared3_div2", + "oscclk" }; +PNAME(mout_cmu_mux_mcsc_noc_p) = { "dout_shared2_div1", + "dout_shared3_div1", + "dout_shared4_div1", + "dout_shared0_div2", + "dout_shared1_div2", + "dout_shared2_div2", + "dout_shared3_div2", + "oscclk" }; +PNAME(mout_cmu_mux_mfc0_mfc0_p) = { "dout_shared2_div1", + "dout_shared3_div1", + "dout_shared4_div1", + "dout_shared0_div2", + "dout_shared1_div2", + "dout_shared2_div2", + "dout_shared3_div2", + "oscclk" }; +PNAME(mout_cmu_mux_mfc0_wfd_p) = { "dout_shared0_div2", + "dout_shared1_div2", + "dout_shared2_div2", + "dout_shared3_div2", + "dout_shared4_div2", + "oscclk", "oscclk", + "oscclk" }; +PNAME(mout_cmu_mux_mfc1_mfc1_p) = { "dout_shared2_div1", + "dout_shared3_div1", + "dout_shared4_div1", + "dout_shared0_div2", + "dout_shared1_div2", + "dout_shared2_div2", + "dout_shared3_div2", + "oscclk" }; +PNAME(mout_cmu_mux_mif_nocp_p) = { "dout_shared0_div2", + "dout_shared1_div2", + "dout_shared2_div2", + "dout_shared4_div2" }; +PNAME(mout_cmu_mux_mif_switch_p) = { "dout_shared0_div1", + "dout_shared1_div1", + "dout_shared2_div1", + "dout_shared3_div1", + "dout_shared4_div1", + "dout_shared0_div2", + "mout_cmu_cp_mpll_clk_user", + "dout_shared_mif_div1" }; +PNAME(mout_cmu_mux_nocl0_noc_p) = { "dout_shared0_div1", + "dout_shared1_div1", + "dout_shared2_div1", + "dout_shared3_div1", + "dout_shared4_div1", + "dout_shared0_div2", + "mout_cmu_cp_mpll_clk_d2_user", + "dout_shared_mif_div2" }; +PNAME(mout_cmu_mux_nocl1a_noc_p) = { "dout_shared2_div1", + "dout_shared3_div1", + "dout_shared4_div1", + "dout_shared0_div2", + "dout_shared1_div2", + "dout_shared2_div2", + "dout_shared3_div2", + "dout_shared4_div2" }; +PNAME(mout_cmu_mux_nocl1b_noc0_p) = { "dout_shared2_div1", + "dout_shared3_div1", + "dout_shared4_div1", + "dout_shared0_div2", + "dout_shared1_div2", + "dout_shared2_div2", + "dout_shared3_div2", + "dout_shared4_div2" }; +PNAME(mout_cmu_mux_nocl1b_noc1_p) = { "dout_shared4_div1", + "dout_shared0_div2", + "dout_shared1_div2", + "dout_shared2_div2" }; +PNAME(mout_cmu_mux_nocl1c_noc_p) = { "dout_shared2_div1", + "dout_shared3_div1", + "dout_shared4_div1", + "dout_shared0_div2", + "dout_shared1_div2", + "dout_shared2_div2", + "dout_shared3_div2", + "dout_shared4_div2" }; +PNAME(mout_cmu_mux_peric0_ip0_p) = { "dout_shared0_div2", + "dout_shared1_div2", + "dout_shared2_div2", + "dout_shared4_div2" }; +PNAME(mout_cmu_mux_peric0_ip1_p) = { "dout_shared0_div2", + "dout_shared1_div2", + "dout_shared2_div2", + "dout_shared4_div2" }; +PNAME(mout_cmu_mux_peric0_noc_p) = { "dout_shared0_div2", + "dout_shared2_div2" }; +PNAME(mout_cmu_mux_peric1_ip0_p) = { "dout_shared0_div2", + "dout_shared1_div2", + "dout_shared2_div2", + "dout_shared4_div2" }; +PNAME(mout_cmu_mux_peric1_ip1_p) = { "dout_shared0_div2", + "dout_shared1_div2", + "dout_shared2_div2", + "dout_shared4_div2" }; +PNAME(mout_cmu_mux_peric1_noc_p) = { "dout_shared0_div2", + "dout_shared2_div2" }; +PNAME(mout_cmu_mux_peric2_ip0_p) = { "dout_shared0_div2", + "dout_shared1_div2", + "dout_shared2_div2", + "dout_shared4_div2" }; +PNAME(mout_cmu_mux_peric2_ip1_p) = { "dout_shared0_div2", + "dout_shared1_div2", + "dout_shared2_div2", + "dout_shared4_div2" }; +PNAME(mout_cmu_mux_peric2_noc_p) = { "dout_shared0_div2", + "dout_shared2_div2" }; +PNAME(mout_cmu_mux_peris_gic_p) = { "dout_shared0_div2", + "dout_shared2_div2" }; +PNAME(mout_cmu_mux_peris_noc_p) = { "dout_shared0_div2", + "dout_shared2_div2" }; +PNAME(mout_cmu_mux_sdma_noc_p) = { "dout_shared0_div1", + "dout_shared1_div1", + "dout_shared2_div1", + "dout_shared3_div1", + "dout_shared4_div1", + "dout_shared0_div2", + "dout_shared1_div2", + "oscclk" }; +PNAME(mout_cmu_mux_ssp_noc_p) = { "dout_shared0_div2", + "dout_shared1_div2", + "dout_shared2_div2", + "dout_shared4_div2" }; +PNAME(mout_cmu_mux_vts_dmic_p) = { "dout_shared3_div1", + "dout_shared4_div1", + "dout_shared0_div2", + "dout_shared1_div2" }; +PNAME(mout_cmu_mux_yuvp_noc_p) = { "dout_shared2_div1", + "dout_shared3_div1", + "dout_shared4_div1", + "dout_shared0_div2", + "dout_shared1_div2", + "dout_shared2_div2", + "dout_shared3_div2", + "oscclk" }; +PNAME(mout_cmu_mux_cmu_cmuref_p) = { "oscclk", + "dout_cmu_boost" }; +PNAME(mout_cmu_mux_cp_hispeedy_clk_p) = { "dout_shared2_div1", + "dout_shared3_div1" }; +PNAME(mout_cmu_mux_cp_shared0_clk_p) = { "dout_shared0_div1", + "dout_shared1_div1", + "dout_shared2_div1", + "dout_shared3_div1" }; +PNAME(mout_cmu_mux_cp_shared1_clk_p) = { "dout_shared4_div1", + "dout_shared0_div2", + "dout_shared1_div2", + "dout_shared2_div2" }; +PNAME(mout_cmu_mux_cp_shared2_clk_p) = { "dout_shared2_div1", + "dout_shared3_div1", + "dout_shared4_div1", + "dout_shared1_div2" }; +PNAME(mout_cmu_m2m_frc_p) = { "dout_shared2_div1", + "dout_shared3_div1", + "dout_shared4_div1", + "dout_shared0_div2", + "dout_shared1_div2", + "dout_shared2_div2", + "dout_shared3_div2", + "oscclk" }; +PNAME(mout_cmu_mcsc_mcsc_p) = { "dout_shared2_div1", + "dout_shared3_div1", + "dout_shared4_div1", + "dout_shared0_div2", + "dout_shared1_div2", + "dout_shared2_div2", + "dout_shared3_div2", + "oscclk" }; +PNAME(mout_cmu_mcsc_noc_p) = { "dout_shared2_div1", + "dout_shared3_div1", + "dout_shared4_div1", + "dout_shared0_div2", + "dout_shared1_div2", + "dout_shared2_div2", + "dout_shared3_div2", + "oscclk" }; +PNAME(mout_cmu_mux_m2m_frc_p) = { "dout_shared2_div1", + "dout_shared3_div1", + "dout_shared4_div1", + "dout_shared0_div2", + "dout_shared1_div2", + "dout_shared2_div2", + "dout_shared3_div2", + "oscclk" }; +PNAME(mout_cmu_mux_ufs_noc_p) = { "dout_shared0_div2", + "dout_shared1_div2", + "dout_shared2_div2", + "dout_shared4_div2" }; + +static const struct samsung_pll_clock top_pll_clks[] __initconst = { + PLL(pll_4311, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk", + PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0, NULL), + PLL(pll_4311, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk", + PLL_LOCKTIME_PLL_SHARED1, PLL_CON3_PLL_SHARED1, NULL), + PLL(pll_4311, CLK_FOUT_SHARED2_PLL, "fout_shared2_pll", "oscclk", + PLL_LOCKTIME_PLL_SHARED2, PLL_CON3_PLL_SHARED2, NULL), + PLL(pll_4311, CLK_FOUT_SHARED3_PLL, "fout_shared3_pll", "oscclk", + PLL_LOCKTIME_PLL_SHARED3, PLL_CON3_PLL_SHARED3, NULL), + PLL(pll_4311, CLK_FOUT_SHARED4_PLL, "fout_shared4_pll", "oscclk", + PLL_LOCKTIME_PLL_SHARED4, PLL_CON3_PLL_SHARED4, NULL), + PLL(pll_4311, CLK_FOUT_MMC_PLL, "fout_mmc_pll", "oscclk", + PLL_LOCKTIME_PLL_MMC, PLL_CON3_PLL_MMC, NULL), + PLL(pll_4311, CLK_FOUT_SHARED_MIF_PLL, "fout_shared_mif_pll", "oscclk", + PLL_LOCKTIME_PLL_SHARED_MIF, PLL_CON3_PLL_SHARED_MIF, NULL), +}; + +static const struct samsung_mux_clock top_mux_clks[] __initconst = { + MUX(CLK_MOUT_CMU_CP_MPLL_CLK_D2_USER, "mout_cmu_cp_mpll_clk_d2_user", + mout_cmu_cp_mpll_clk_d2_user_parents, + PLL_CON0_MUX_CP_MPLL_CLK_D2_USER, 4, 1), + MUX(CLK_MOUT_CMU_CP_MPLL_CLK_USER, "mout_cmu_cp_mpll_clk_user", + mout_cmu_cp_mpll_clk_user_parents, PLL_CON0_MUX_CP_MPLL_CLK_USER, + 4, 1), + MUX(CLK_MOUT_CMU_AUD_AUDIF0, "mout_cmu_aud_audif0", + mout_cmu_aud_audif0_p, CLK_CON_MUX_CLKCMU_AUD_AUDIF0, 0, 3), + MUX(CLK_MOUT_CMU_AUD_AUDIF1, "mout_cmu_aud_audif1", + mout_cmu_aud_audif1_p, CLK_CON_MUX_CLKCMU_AUD_AUDIF1, 0, 3), + MUX(CLK_MOUT_CMU_AUD_CPU, "mout_cmu_aud_cpu", mout_cmu_aud_cpu_p, + CLK_CON_MUX_CLKCMU_AUD_CPU, 0, 3), + MUX(CLK_MOUT_CMU_CPUCL0_DBG_NOC, "mout_cmu_cpucl0_dbg_noc", + mout_cmu_cpucl0_dbg_noc_p, CLK_CON_MUX_CLKCMU_CPUCL0_DBG_NOC, + 0, 2), + MUX(CLK_MOUT_CMU_CPUCL0_SWITCH, "mout_cmu_cpucl0_switch", + mout_cmu_cpucl0_switch_p, CLK_CON_MUX_CLKCMU_CPUCL0_SWITCH, 0, 3), + MUX(CLK_MOUT_CMU_CPUCL1_SWITCH, "mout_cmu_cpucl1_switch", + mout_cmu_cpucl1_switch_p, CLK_CON_MUX_CLKCMU_CPUCL1_SWITCH, 0, 3), + MUX(CLK_MOUT_CMU_CPUCL2_SWITCH, "mout_cmu_cpucl2_switch", + mout_cmu_cpucl2_switch_p, CLK_CON_MUX_CLKCMU_CPUCL2_SWITCH, 0, 3), + MUX(CLK_MOUT_CMU_DNC_NOC, "mout_cmu_dnc_noc", mout_cmu_dnc_noc_p, + CLK_CON_MUX_CLKCMU_DNC_NOC, 0, 3), + MUX(CLK_MOUT_CMU_DPUB_NOC, "mout_cmu_dpub_noc", mout_cmu_dpub_noc_p, + CLK_CON_MUX_CLKCMU_DPUB_NOC, 0, 1), + MUX(CLK_MOUT_CMU_DPUF_NOC, "mout_cmu_dpuf_noc", mout_cmu_dpuf_noc_p, + CLK_CON_MUX_CLKCMU_DPUF_NOC, 0, 1), + MUX(CLK_MOUT_CMU_DSP_NOC, "mout_cmu_dsp_noc", mout_cmu_dsp_noc_p, + CLK_CON_MUX_CLKCMU_DSP_NOC, 0, 3), + MUX(CLK_MOUT_CMU_DSU_SWITCH, "mout_cmu_dsu_switch", + mout_cmu_dsu_switch_p, CLK_CON_MUX_CLKCMU_DSU_SWITCH, 0, 3), + MUX(CLK_MOUT_CMU_G3D_SWITCH, "mout_cmu_g3d_switch", + mout_cmu_g3d_switch_p, CLK_CON_MUX_CLKCMU_G3D_SWITCH, 0, 3), + MUX(CLK_MOUT_CMU_GNPU_NOC, "mout_cmu_gnpu_noc", mout_cmu_gnpu_noc_p, + CLK_CON_MUX_CLKCMU_GNPU_NOC, 0, 3), + MUX(CLK_MOUT_CMU_UFS_MMC_CARD, "mout_cmu_ufs_mmc_card", + mout_cmu_ufs_mmc_card_p, CLK_CON_MUX_CLKCMU_UFS_MMC_CARD, 0, 2), + MUX(CLK_MOUT_CMU_M2M_NOC, "mout_cmu_m2m_noc", mout_cmu_m2m_noc_p, + CLK_CON_MUX_CLKCMU_M2M_NOC, 0, 3), + MUX(CLK_MOUT_CMU_NOCL0_NOC, "mout_cmu_nocl0_noc", mout_cmu_nocl0_noc_p, + CLK_CON_MUX_CLKCMU_NOCL0_NOC, 0, 3), + MUX(CLK_MOUT_CMU_NOCL1A_NOC, "mout_cmu_nocl1a_noc", + mout_cmu_nocl1a_noc_p, CLK_CON_MUX_CLKCMU_NOCL1A_NOC, 0, 3), + MUX(CLK_MOUT_CMU_NOCL1B_NOC0, "mout_cmu_nocl1b_noc0", + mout_cmu_nocl1b_noc0_p, CLK_CON_MUX_CLKCMU_NOCL1B_NOC0, 0, 3), + MUX(CLK_MOUT_CMU_NOCL1C_NOC, "mout_cmu_nocl1c_noc", + mout_cmu_nocl1c_noc_p, CLK_CON_MUX_CLKCMU_NOCL1C_NOC, 0, 3), + MUX(CLK_MOUT_CMU_SDMA_NOC, "mout_cmu_sdma_noc", mout_cmu_sdma_noc_p, + CLK_CON_MUX_CLKCMU_SDMA_NOC, 0, 3), + MUX(CLK_MOUT_CMU_CP_HISPEEDY_CLK, "mout_cmu_cp_hispeedy_clk", + mout_cmu_cp_hispeedy_clk_p, CLK_CON_MUX_CP_HISPEEDY_CLK, 0, 1), + MUX(CLK_MOUT_CMU_CP_SHARED0_CLK, "mout_cmu_cp_shared0_clk", + mout_cmu_cp_shared0_clk_p, CLK_CON_MUX_CP_SHARED0_CLK, 0, 2), + MUX(CLK_MOUT_CMU_CP_SHARED2_CLK, "mout_cmu_cp_shared2_clk", + mout_cmu_cp_shared2_clk_p, CLK_CON_MUX_CP_SHARED2_CLK, 0, 2), + MUX(CLK_MOUT_CMU_MUX_ALIVE_NOC, "mout_cmu_mux_alive_noc", + mout_cmu_mux_alive_noc_p, CLK_CON_MUX_MUX_CLKCMU_ALIVE_NOC, 0, 1), + MUX(CLK_MOUT_CMU_MUX_AUD_AUDIF0, "mout_cmu_mux_aud_audif0", + mout_cmu_mux_aud_audif0_p, CLK_CON_MUX_MUX_CLKCMU_AUD_AUDIF0, + 0, 3), + MUX(CLK_MOUT_CMU_MUX_AUD_AUDIF1, "mout_cmu_mux_aud_audif1", + mout_cmu_mux_aud_audif1_p, CLK_CON_MUX_MUX_CLKCMU_AUD_AUDIF1, + 0, 3), + MUX(CLK_MOUT_CMU_MUX_AUD_CPU, "mout_cmu_mux_aud_cpu", + mout_cmu_mux_aud_cpu_p, CLK_CON_MUX_MUX_CLKCMU_AUD_CPU, 0, 3), + MUX(CLK_MOUT_CMU_MUX_AUD_NOC, "mout_cmu_mux_aud_noc", + mout_cmu_mux_aud_noc_p, CLK_CON_MUX_MUX_CLKCMU_AUD_NOC, 0, 3), + MUX(CLK_MOUT_CMU_MUX_BRP_NOC, "mout_cmu_mux_brp_noc", + mout_cmu_mux_brp_noc_p, CLK_CON_MUX_MUX_CLKCMU_BRP_NOC, 0, 3), + MUX(CLK_MOUT_CMU_MUX_CIS_CLK0, "mout_cmu_mux_cis_clk0", + mout_cmu_mux_cis_clk0_p, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0, 0, 1), + MUX(CLK_MOUT_CMU_MUX_CIS_CLK1, "mout_cmu_mux_cis_clk1", + mout_cmu_mux_cis_clk1_p, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1, 0, 1), + MUX(CLK_MOUT_CMU_MUX_CIS_CLK2, "mout_cmu_mux_cis_clk2", + mout_cmu_mux_cis_clk2_p, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2, 0, 1), + MUX(CLK_MOUT_CMU_MUX_CIS_CLK3, "mout_cmu_mux_cis_clk3", + mout_cmu_mux_cis_clk3_p, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3, 0, 1), + MUX(CLK_MOUT_CMU_MUX_CIS_CLK4, "mout_cmu_mux_cis_clk4", + mout_cmu_mux_cis_clk4_p, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4, 0, 1), + MUX(CLK_MOUT_CMU_MUX_CIS_CLK5, "mout_cmu_mux_cis_clk5", + mout_cmu_mux_cis_clk5_p, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5, 0, 1), + MUX(CLK_MOUT_CMU_MUX_CIS_CLK6, "mout_cmu_mux_cis_clk6", + mout_cmu_mux_cis_clk6_p, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6, 0, 1), + MUX(CLK_MOUT_CMU_MUX_CIS_CLK7, "mout_cmu_mux_cis_clk7", + mout_cmu_mux_cis_clk7_p, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7, 0, 1), + MUX(CLK_MOUT_CMU_MUX_CMU_BOOST, "mout_cmu_mux_cmu_boost", + mout_cmu_mux_cmu_boost_p, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST, 0, 2), + MUX(CLK_MOUT_CMU_MUX_CMU_BOOST_CAM, "mout_cmu_mux_cmu_boost_cam", + mout_cmu_mux_cmu_boost_cam_p, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_CAM, + 0, 2), + MUX(CLK_MOUT_CMU_MUX_CMU_BOOST_CPU, "mout_cmu_mux_cmu_boost_cpu", + mout_cmu_mux_cmu_boost_cpu_p, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_CPU, + 0, 2), + MUX(CLK_MOUT_CMU_MUX_CMU_BOOST_MIF, "mout_cmu_mux_cmu_boost_mif", + mout_cmu_mux_cmu_boost_mif_p, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_MIF, + 0, 2), + MUX(CLK_MOUT_CMU_MUX_CPUCL0_DBG_NOC, "mout_cmu_mux_cpucl0_dbg_noc", + mout_cmu_mux_cpucl0_dbg_noc_p, + CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_NOC, 0, 2), + MUX(CLK_MOUT_CMU_MUX_CPUCL0_NOCP, "mout_cmu_mux_cpucl0_nocp", + mout_cmu_mux_cpucl0_nocp_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_NOCP, + 0, 2), + MUX(CLK_MOUT_CMU_MUX_CPUCL0_SWITCH, "mout_cmu_mux_cpucl0_switch", + mout_cmu_mux_cpucl0_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH, + 0, 3), + MUX(CLK_MOUT_CMU_MUX_CPUCL1_SWITCH, "mout_cmu_mux_cpucl1_switch", + mout_cmu_mux_cpucl1_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH, + 0, 3), + MUX(CLK_MOUT_CMU_MUX_CPUCL2_SWITCH, "mout_cmu_mux_cpucl2_switch", + mout_cmu_mux_cpucl2_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH, + 0, 3), + MUX(CLK_MOUT_CMU_MUX_CSIS_DCPHY, "mout_cmu_mux_csis_dcphy", + mout_cmu_mux_csis_dcphy_p, CLK_CON_MUX_MUX_CLKCMU_CSIS_DCPHY, + 0, 2), + MUX(CLK_MOUT_CMU_MUX_CSIS_NOC, "mout_cmu_mux_csis_noc", + mout_cmu_mux_csis_noc_p, CLK_CON_MUX_MUX_CLKCMU_CSIS_NOC, 0, 3), + MUX(CLK_MOUT_CMU_MUX_CSIS_OIS_MCU, "mout_cmu_mux_csis_ois_mcu", + mout_cmu_mux_csis_ois_mcu_p, CLK_CON_MUX_MUX_CLKCMU_CSIS_OIS_MCU, + 0, 1), + MUX(CLK_MOUT_CMU_MUX_CSTAT_NOC, "mout_cmu_mux_cstat_noc", + mout_cmu_mux_cstat_noc_p, CLK_CON_MUX_MUX_CLKCMU_CSTAT_NOC, 0, 3), + MUX(CLK_MOUT_CMU_MUX_DNC_NOC, "mout_cmu_mux_dnc_noc", + mout_cmu_mux_dnc_noc_p, CLK_CON_MUX_MUX_CLKCMU_DNC_NOC, 0, 3), + MUX(CLK_MOUT_CMU_MUX_DPUB, "mout_cmu_mux_dpub", mout_cmu_mux_dpub_p, + CLK_CON_MUX_MUX_CLKCMU_DPUB, 0, 3), + MUX(CLK_MOUT_CMU_MUX_DPUB_ALT, "mout_cmu_mux_dpub_alt", + mout_cmu_mux_dpub_alt_p, CLK_CON_MUX_MUX_CLKCMU_DPUB_ALT, 0, 3), + MUX(CLK_MOUT_CMU_MUX_DPUB_DSIM, "mout_cmu_mux_dpub_dsim", + mout_cmu_mux_dpub_dsim_p, CLK_CON_MUX_MUX_CLKCMU_DPUB_DSIM, 0, 2), + MUX(CLK_MOUT_CMU_MUX_DPUF, "mout_cmu_mux_dpuf", mout_cmu_mux_dpuf_p, + CLK_CON_MUX_MUX_CLKCMU_DPUF, 0, 3), + MUX(CLK_MOUT_CMU_MUX_DPUF_ALT, "mout_cmu_mux_dpuf_alt", + mout_cmu_mux_dpuf_alt_p, CLK_CON_MUX_MUX_CLKCMU_DPUF_ALT, 0, 3), + MUX(CLK_MOUT_CMU_MUX_DSP_NOC, "mout_cmu_mux_dsp_noc", + mout_cmu_mux_dsp_noc_p, CLK_CON_MUX_MUX_CLKCMU_DSP_NOC, 0, 3), + MUX(CLK_MOUT_CMU_MUX_DSU_SWITCH, "mout_cmu_mux_dsu_switch", + mout_cmu_mux_dsu_switch_p, CLK_CON_MUX_MUX_CLKCMU_DSU_SWITCH, + 0, 3), + MUX(CLK_MOUT_CMU_MUX_G3D_NOCP, "mout_cmu_mux_g3d_nocp", + mout_cmu_mux_g3d_nocp_p, CLK_CON_MUX_MUX_CLKCMU_G3D_NOCP, 0, 2), + MUX(CLK_MOUT_CMU_MUX_G3D_SWITCH, "mout_cmu_mux_g3d_switch", + mout_cmu_mux_g3d_switch_p, CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, + 0, 3), + MUX(CLK_MOUT_CMU_MUX_GNPU_NOC, "mout_cmu_mux_gnpu_noc", + mout_cmu_mux_gnpu_noc_p, CLK_CON_MUX_MUX_CLKCMU_GNPU_NOC, 0, 3), + MUX(CLK_MOUT_CMU_MUX_HSI0_DPGTC, "mout_cmu_mux_hsi0_dpgtc", + mout_cmu_mux_hsi0_dpgtc_p, CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC, + 0, 2), + MUX(CLK_MOUT_CMU_MUX_HSI0_DPOSC, "mout_cmu_mux_hsi0_dposc", + mout_cmu_mux_hsi0_dposc_p, CLK_CON_MUX_MUX_CLKCMU_HSI0_DPOSC, + 0, 1), + MUX(CLK_MOUT_CMU_MUX_HSI0_NOC, "mout_cmu_mux_hsi0_noc", + mout_cmu_mux_hsi0_noc_p, CLK_CON_MUX_MUX_CLKCMU_HSI0_NOC, 0, 2), + MUX(CLK_MOUT_CMU_MUX_HSI0_USB32DRD, "mout_cmu_mux_hsi0_usb32drd", + mout_cmu_mux_hsi0_usb32drd_p, CLK_CON_MUX_MUX_CLKCMU_HSI0_USB32DRD, + 0, 2), + MUX(CLK_MOUT_CMU_MUX_UFS_MMC_CARD, "mout_cmu_mux_ufs_mmc_card", + mout_cmu_mux_ufs_mmc_card_p, CLK_CON_MUX_MUX_CLKCMU_UFS_MMC_CARD, + 0, 2), + MUX(CLK_MOUT_CMU_MUX_HSI1_NOC, "mout_cmu_mux_hsi1_noc", + mout_cmu_mux_hsi1_noc_p, CLK_CON_MUX_MUX_CLKCMU_HSI1_NOC, 0, 2), + MUX(CLK_MOUT_CMU_MUX_HSI1_PCIE, "mout_cmu_mux_hsi1_pcie", + mout_cmu_mux_hsi1_pcie_p, CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE, 0, 1), + MUX(CLK_MOUT_CMU_MUX_UFS_UFS_EMBD, "mout_cmu_mux_ufs_ufs_embd", + mout_cmu_mux_ufs_ufs_embd_p, CLK_CON_MUX_MUX_CLKCMU_UFS_UFS_EMBD, + 0, 2), + MUX(CLK_MOUT_CMU_MUX_LME_LME, "mout_cmu_mux_lme_lme", + mout_cmu_mux_lme_lme_p, CLK_CON_MUX_MUX_CLKCMU_LME_LME, 0, 3), + MUX(CLK_MOUT_CMU_MUX_LME_NOC, "mout_cmu_mux_lme_noc", + mout_cmu_mux_lme_noc_p, CLK_CON_MUX_MUX_CLKCMU_LME_NOC, 0, 3), + MUX(CLK_MOUT_CMU_MUX_M2M_NOC, "mout_cmu_mux_m2m_noc", + mout_cmu_mux_m2m_noc_p, CLK_CON_MUX_MUX_CLKCMU_M2M_NOC, 0, 3), + MUX(CLK_MOUT_CMU_MUX_MCSC_MCSC, "mout_cmu_mux_mcsc_mcsc", + mout_cmu_mux_mcsc_mcsc_p, CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC, 0, 3), + MUX(CLK_MOUT_CMU_MUX_MCSC_NOC, "mout_cmu_mux_mcsc_noc", + mout_cmu_mux_mcsc_noc_p, CLK_CON_MUX_MUX_CLKCMU_MCSC_NOC, 0, 3), + MUX(CLK_MOUT_CMU_MUX_MFC0_MFC0, "mout_cmu_mux_mfc0_mfc0", + mout_cmu_mux_mfc0_mfc0_p, CLK_CON_MUX_MUX_CLKCMU_MFC0_MFC0, 0, 3), + MUX(CLK_MOUT_CMU_MUX_MFC0_WFD, "mout_cmu_mux_mfc0_wfd", + mout_cmu_mux_mfc0_wfd_p, CLK_CON_MUX_MUX_CLKCMU_MFC0_WFD, 0, 3), + MUX(CLK_MOUT_CMU_MUX_MFC1_MFC1, "mout_cmu_mux_mfc1_mfc1", + mout_cmu_mux_mfc1_mfc1_p, CLK_CON_MUX_MUX_CLKCMU_MFC1_MFC1, 0, 3), + MUX(CLK_MOUT_CMU_MUX_MIF_NOCP, "mout_cmu_mux_mif_nocp", + mout_cmu_mux_mif_nocp_p, CLK_CON_MUX_MUX_CLKCMU_MIF_NOCP, 0, 2), + MUX(CLK_MOUT_CMU_MUX_MIF_SWITCH, "mout_cmu_mux_mif_switch", + mout_cmu_mux_mif_switch_p, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, + 0, 3), + MUX(CLK_MOUT_CMU_MUX_NOCL0_NOC, "mout_cmu_mux_nocl0_noc", + mout_cmu_mux_nocl0_noc_p, CLK_CON_MUX_MUX_CLKCMU_NOCL0_NOC, 0, 3), + MUX(CLK_MOUT_CMU_MUX_NOCL1A_NOC, "mout_cmu_mux_nocl1a_noc", + mout_cmu_mux_nocl1a_noc_p, CLK_CON_MUX_MUX_CLKCMU_NOCL1A_NOC, + 0, 3), + MUX(CLK_MOUT_CMU_MUX_NOCL1B_NOC0, "mout_cmu_mux_nocl1b_noc0", + mout_cmu_mux_nocl1b_noc0_p, CLK_CON_MUX_MUX_CLKCMU_NOCL1B_NOC0, + 0, 3), + MUX(CLK_MOUT_CMU_MUX_NOCL1B_NOC1, "mout_cmu_mux_nocl1b_noc1", + mout_cmu_mux_nocl1b_noc1_p, CLK_CON_MUX_MUX_CLKCMU_NOCL1B_NOC1, + 0, 2), + MUX(CLK_MOUT_CMU_MUX_NOCL1C_NOC, "mout_cmu_mux_nocl1c_noc", + mout_cmu_mux_nocl1c_noc_p, CLK_CON_MUX_MUX_CLKCMU_NOCL1C_NOC, + 0, 3), + MUX(CLK_MOUT_CMU_MUX_PERIC0_IP0, "mout_cmu_mux_peric0_ip0", + mout_cmu_mux_peric0_ip0_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP0, + 0, 2), + MUX(CLK_MOUT_CMU_MUX_PERIC0_IP1, "mout_cmu_mux_peric0_ip1", + mout_cmu_mux_peric0_ip1_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP1, + 0, 2), + MUX(CLK_MOUT_CMU_MUX_PERIC0_NOC, "mout_cmu_mux_peric0_noc", + mout_cmu_mux_peric0_noc_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_NOC, + 0, 1), + MUX(CLK_MOUT_CMU_MUX_PERIC1_IP0, "mout_cmu_mux_peric1_ip0", + mout_cmu_mux_peric1_ip0_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP0, + 0, 2), + MUX(CLK_MOUT_CMU_MUX_PERIC1_IP1, "mout_cmu_mux_peric1_ip1", + mout_cmu_mux_peric1_ip1_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP1, + 0, 2), + MUX(CLK_MOUT_CMU_MUX_PERIC1_NOC, "mout_cmu_mux_peric1_noc", + mout_cmu_mux_peric1_noc_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_NOC, + 0, 1), + MUX(CLK_MOUT_CMU_MUX_PERIC2_IP0, "mout_cmu_mux_peric2_ip0", + mout_cmu_mux_peric2_ip0_p, CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP0, + 0, 2), + MUX(CLK_MOUT_CMU_MUX_PERIC2_IP1, "mout_cmu_mux_peric2_ip1", + mout_cmu_mux_peric2_ip1_p, CLK_CON_MUX_MUX_CLKCMU_PERIC2_IP1, + 0, 2), + MUX(CLK_MOUT_CMU_MUX_PERIC2_NOC, "mout_cmu_mux_peric2_noc", + mout_cmu_mux_peric2_noc_p, CLK_CON_MUX_MUX_CLKCMU_PERIC2_NOC, + 0, 1), + MUX(CLK_MOUT_CMU_MUX_PERIS_GIC, "mout_cmu_mux_peris_gic", + mout_cmu_mux_peris_gic_p, CLK_CON_MUX_MUX_CLKCMU_PERIS_GIC, 0, 1), + MUX(CLK_MOUT_CMU_MUX_PERIS_NOC, "mout_cmu_mux_peris_noc", + mout_cmu_mux_peris_noc_p, CLK_CON_MUX_MUX_CLKCMU_PERIS_NOC, 0, 1), + MUX(CLK_MOUT_CMU_MUX_SDMA_NOC, "mout_cmu_mux_sdma_noc", + mout_cmu_mux_sdma_noc_p, CLK_CON_MUX_MUX_CLKCMU_SDMA_NOC, 0, 3), + MUX(CLK_MOUT_CMU_MUX_SSP_NOC, "mout_cmu_mux_ssp_noc", + mout_cmu_mux_ssp_noc_p, CLK_CON_MUX_MUX_CLKCMU_SSP_NOC, 0, 2), + MUX(CLK_MOUT_CMU_MUX_VTS_DMIC, "mout_cmu_mux_vts_dmic", + mout_cmu_mux_vts_dmic_p, CLK_CON_MUX_MUX_CLKCMU_VTS_DMIC, 0, 2), + MUX(CLK_MOUT_CMU_MUX_YUVP_NOC, "mout_cmu_mux_yuvp_noc", + mout_cmu_mux_yuvp_noc_p, CLK_CON_MUX_MUX_CLKCMU_YUVP_NOC, 0, 3), + MUX(CLK_MOUT_CMU_MUX_CMU_CMUREF, "mout_cmu_mux_cmu_cmuref", + mout_cmu_mux_cmu_cmuref_p, CLK_CON_MUX_MUX_CMU_CMUREF, 0, 1), + MUX(CLK_MOUT_CMU_MUX_CP_HISPEEDY_CLK, "mout_cmu_mux_cp_hispeedy_clk", + mout_cmu_mux_cp_hispeedy_clk_p, CLK_CON_MUX_MUX_CP_HISPEEDY_CLK, + 0, 1), + MUX(CLK_MOUT_CMU_MUX_CP_SHARED0_CLK, "mout_cmu_mux_cp_shared0_clk", + mout_cmu_mux_cp_shared0_clk_p, CLK_CON_MUX_MUX_CP_SHARED0_CLK, + 0, 2), + MUX(CLK_MOUT_CMU_MUX_CP_SHARED1_CLK, "mout_cmu_mux_cp_shared1_clk", + mout_cmu_mux_cp_shared1_clk_p, CLK_CON_MUX_MUX_CP_SHARED1_CLK, + 0, 2), + MUX(CLK_MOUT_CMU_MUX_CP_SHARED2_CLK, "mout_cmu_mux_cp_shared2_clk", + mout_cmu_mux_cp_shared2_clk_p, CLK_CON_MUX_MUX_CP_SHARED2_CLK, + 0, 2), + MUX(CLK_MOUT_CMU_M2M_FRC, "mout_cmu_m2m_frc", mout_cmu_m2m_frc_p, + CLK_CON_MUX_CLKCMU_M2M_FRC, 0, 3), + MUX(CLK_MOUT_CMU_MCSC_MCSC, "mout_cmu_mcsc_mcsc", mout_cmu_mcsc_mcsc_p, + CLK_CON_MUX_CLKCMU_MCSC_MCSC, 0, 3), + MUX(CLK_MOUT_CMU_MCSC_NOC, "mout_cmu_mcsc_noc", mout_cmu_mcsc_noc_p, + CLK_CON_MUX_CLKCMU_MCSC_NOC, 0, 3), + MUX(CLK_MOUT_CMU_MUX_M2M_FRC, "mout_cmu_mux_m2m_frc", + mout_cmu_mux_m2m_frc_p, CLK_CON_MUX_MUX_CLKCMU_M2M_FRC, 0, 3), + MUX(CLK_MOUT_CMU_MUX_UFS_NOC, "mout_cmu_mux_ufs_noc", + mout_cmu_mux_ufs_noc_p, CLK_CON_MUX_MUX_CLKCMU_UFS_NOC, 0, 2), +}; + +static const struct samsung_div_clock top_div_clks[] __initconst = { + DIV(CLK_DOUT_CMU_ALIVE_NOC, "dout_cmu_alive_noc", + "mout_cmu_mux_alive_noc", CLK_CON_DIV_CLKCMU_ALIVE_NOC, 0, 2), + DIV(CLK_DOUT_CMU_AUD_NOC, "dout_cmu_aud_noc", "mout_cmu_mux_aud_noc", + CLK_CON_DIV_CLKCMU_AUD_NOC, 0, 4), + DIV(CLK_DOUT_CMU_BRP_NOC, "dout_cmu_brp_noc", "mout_cmu_mux_brp_noc", + CLK_CON_DIV_CLKCMU_BRP_NOC, 0, 4), + DIV(CLK_DOUT_CMU_CMU_BOOST, "dout_cmu_cmu_boost", + "mout_cmu_mux_cmu_boost", CLK_CON_DIV_CLKCMU_CMU_BOOST, 0, 3), + DIV(CLK_DOUT_CMU_CMU_BOOST_CAM, "dout_cmu_cmu_boost_cam", + "mout_cmu_mux_cmu_boost_cam", CLK_CON_DIV_CLKCMU_CMU_BOOST_CAM, + 0, 3), + DIV(CLK_DOUT_CMU_CMU_BOOST_CPU, "dout_cmu_cmu_boost_cpu", + "mout_cmu_mux_cmu_boost_cpu", CLK_CON_DIV_CLKCMU_CMU_BOOST_CPU, + 0, 3), + DIV(CLK_DOUT_CMU_CMU_BOOST_MIF, "dout_cmu_cmu_boost_mif", + "mout_cmu_mux_cmu_boost_mif", CLK_CON_DIV_CLKCMU_CMU_BOOST_MIF, + 0, 3), + DIV(CLK_DOUT_CMU_CPUCL0_NOCP, "dout_cmu_cpucl0_nocp", + "mout_cmu_mux_cpucl0_nocp", CLK_CON_DIV_CLKCMU_CPUCL0_NOCP, 0, 4), + DIV(CLK_DOUT_CMU_CSIS_DCPHY, "dout_cmu_csis_dcphy", + "mout_cmu_mux_csis_dcphy", CLK_CON_DIV_CLKCMU_CSIS_DCPHY, 0, 4), + DIV(CLK_DOUT_CMU_CSIS_NOC, "dout_cmu_csis_noc", + "mout_cmu_mux_csis_noc", CLK_CON_DIV_CLKCMU_CSIS_NOC, 0, 4), + DIV(CLK_DOUT_CMU_CSIS_OIS_MCU, "dout_cmu_csis_ois_mcu", + "mout_cmu_mux_csis_ois_mcu", CLK_CON_DIV_CLKCMU_CSIS_OIS_MCU, + 0, 4), + DIV(CLK_DOUT_CMU_CSTAT_NOC, "dout_cmu_cstat_noc", + "mout_cmu_mux_cstat_noc", CLK_CON_DIV_CLKCMU_CSTAT_NOC, 0, 4), + DIV(CLK_DOUT_CMU_DPUB_DSIM, "dout_cmu_dpub_dsim", + "mout_cmu_mux_dpub_dsim", CLK_CON_DIV_CLKCMU_DPUB_DSIM, 0, 4), + DIV(CLK_DOUT_CMU_LME_LME, "dout_cmu_lme_lme", "mout_cmu_mux_lme_lme", + CLK_CON_DIV_CLKCMU_LME_LME, 0, 4), + DIV(CLK_DOUT_CMU_G3D_NOCP, "dout_cmu_g3d_nocp", + "mout_cmu_mux_g3d_nocp", CLK_CON_DIV_CLKCMU_G3D_NOCP, 0, 3), + DIV(CLK_DOUT_CMU_HSI0_DPGTC, "dout_cmu_hsi0_dpgtc", + "mout_cmu_mux_hsi0_dpgtc", CLK_CON_DIV_CLKCMU_HSI0_DPGTC, 0, 3), + DIV(CLK_DOUT_CMU_HSI0_DPOSC, "dout_cmu_hsi0_dposc", + "mout_cmu_mux_hsi0_dposc", CLK_CON_DIV_CLKCMU_HSI0_DPOSC, 0, 5), + DIV(CLK_DOUT_CMU_HSI0_NOC, "dout_cmu_hsi0_noc", + "mout_cmu_mux_hsi0_noc", CLK_CON_DIV_CLKCMU_HSI0_NOC, 0, 4), + DIV(CLK_DOUT_CMU_HSI0_USB32DRD, "dout_cmu_hsi0_usb32drd", + "mout_cmu_mux_hsi0_usb32drd", CLK_CON_DIV_CLKCMU_HSI0_USB32DRD, + 0, 5), + DIV(CLK_DOUT_CMU_HSI1_NOC, "dout_cmu_hsi1_noc", + "mout_cmu_mux_hsi1_noc", CLK_CON_DIV_CLKCMU_HSI1_NOC, 0, 4), + DIV(CLK_DOUT_CMU_HSI1_PCIE, "dout_cmu_hsi1_pcie", + "mout_cmu_mux_hsi1_pcie", CLK_CON_DIV_CLKCMU_HSI1_PCIE, 0, 8), + DIV(CLK_DOUT_CMU_UFS_UFS_EMBD, "dout_cmu_ufs_ufs_embd", + "mout_cmu_mux_ufs_ufs_embd", CLK_CON_DIV_CLKCMU_UFS_UFS_EMBD, + 0, 4), + DIV(CLK_DOUT_CMU_LME_NOC, "dout_cmu_lme_noc", "mout_cmu_mux_lme_noc", + CLK_CON_DIV_CLKCMU_LME_NOC, 0, 4), + DIV(CLK_DOUT_CMU_MFC0_MFC0, "dout_cmu_mfc0_mfc0", + "mout_cmu_mux_mfc0_mfc0", CLK_CON_DIV_CLKCMU_MFC0_MFC0, 0, 4), + DIV(CLK_DOUT_CMU_MFC0_WFD, "dout_cmu_mfc0_wfd", + "mout_cmu_mux_mfc0_wfd", CLK_CON_DIV_CLKCMU_MFC0_WFD, 0, 4), + DIV(CLK_DOUT_CMU_MFC1_MFC1, "dout_cmu_mfc1_mfc1", + "mout_cmu_mux_mfc1_mfc1", CLK_CON_DIV_CLKCMU_MFC1_MFC1, 0, 4), + DIV(CLK_DOUT_CMU_MIF_NOCP, "dout_cmu_mif_nocp", + "mout_cmu_mux_mif_nocp", CLK_CON_DIV_CLKCMU_MIF_NOCP, 0, 4), + DIV(CLK_DOUT_CMU_NOCL1B_NOC1, "dout_cmu_nocl1b_noc1", + "mout_cmu_mux_nocl1b_noc1", CLK_CON_DIV_CLKCMU_NOCL1B_NOC1, 0, 4), + DIV(CLK_DOUT_CMU_PERIC0_IP0, "dout_cmu_peric0_ip0", + "mout_cmu_mux_peric0_ip0", CLK_CON_DIV_CLKCMU_PERIC0_IP0, 0, 4), + DIV(CLK_DOUT_CMU_PERIC0_IP1, "dout_cmu_peric0_ip1", + "mout_cmu_mux_peric0_ip1", CLK_CON_DIV_CLKCMU_PERIC0_IP1, 0, 4), + DIV(CLK_DOUT_CMU_PERIC0_NOC, "dout_cmu_peric0_noc", + "mout_cmu_mux_peric0_noc", CLK_CON_DIV_CLKCMU_PERIC0_NOC, 0, 4), + DIV(CLK_DOUT_CMU_PERIC1_IP0, "dout_cmu_peric1_ip0", + "mout_cmu_mux_peric1_ip0", CLK_CON_DIV_CLKCMU_PERIC1_IP0, 0, 4), + DIV(CLK_DOUT_CMU_PERIC1_IP1, "dout_cmu_peric1_ip1", + "mout_cmu_mux_peric1_ip1", CLK_CON_DIV_CLKCMU_PERIC1_IP1, 0, 4), + DIV(CLK_DOUT_CMU_PERIC1_NOC, "dout_cmu_peric1_noc", + "mout_cmu_mux_peric1_noc", CLK_CON_DIV_CLKCMU_PERIC1_NOC, 0, 4), + DIV(CLK_DOUT_CMU_PERIC2_IP0, "dout_cmu_peric2_ip0", + "mout_cmu_mux_peric2_ip0", CLK_CON_DIV_CLKCMU_PERIC2_IP0, 0, 4), + DIV(CLK_DOUT_CMU_PERIC2_IP1, "dout_cmu_peric2_ip1", + "mout_cmu_mux_peric2_ip1", CLK_CON_DIV_CLKCMU_PERIC2_IP1, 0, 4), + DIV(CLK_DOUT_CMU_PERIC2_NOC, "dout_cmu_peric2_noc", + "mout_cmu_mux_peric2_noc", CLK_CON_DIV_CLKCMU_PERIC2_NOC, 0, 4), + DIV(CLK_DOUT_CMU_PERIS_GIC, "dout_cmu_peris_gic", + "mout_cmu_mux_peris_gic", CLK_CON_DIV_CLKCMU_PERIS_GIC, 0, 4), + DIV(CLK_DOUT_CMU_PERIS_NOC, "dout_cmu_peris_noc", + "mout_cmu_mux_peris_noc", CLK_CON_DIV_CLKCMU_PERIS_NOC, 0, 4), + DIV(CLK_DOUT_CMU_SSP_NOC, "dout_cmu_ssp_noc", "mout_cmu_mux_ssp_noc", + CLK_CON_DIV_CLKCMU_SSP_NOC, 0, 4), + DIV(CLK_DOUT_CMU_VTS_DMIC, "dout_cmu_vts_dmic", + "mout_cmu_mux_vts_dmic", CLK_CON_DIV_CLKCMU_VTS_DMIC, 0, 6), + DIV(CLK_DOUT_CMU_YUVP_NOC, "dout_cmu_yuvp_noc", + "mout_cmu_mux_yuvp_noc", CLK_CON_DIV_CLKCMU_YUVP_NOC, 0, 4), + DIV(CLK_DOUT_CMU_CP_SHARED1_CLK, "dout_cmu_cp_shared1_clk", + "mout_cmu_mux_cp_shared1_clk", CLK_CON_DIV_CP_SHARED1_CLK, 0, 3), + DIV(CLK_DOUT_CMU_DIV_AUD_AUDIF0, "dout_cmu_div_aud_audif0", + "mout_cmu_mux_aud_audif0", CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF0, + 0, 6), + DIV(CLK_DOUT_CMU_DIV_AUD_AUDIF0_SM, "dout_cmu_div_aud_audif0_sm", + "mout_cmu_aud_audif0", CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF0_SM, 0, 6), + DIV(CLK_DOUT_CMU_DIV_AUD_AUDIF1, "dout_cmu_div_aud_audif1", + "mout_cmu_mux_aud_audif1", CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF1, + 0, 6), + DIV(CLK_DOUT_CMU_DIV_AUD_AUDIF1_SM, "dout_cmu_div_aud_audif1_sm", + "mout_cmu_aud_audif1", CLK_CON_DIV_DIV_CLKCMU_AUD_AUDIF1_SM, 0, 6), + DIV(CLK_DOUT_CMU_DIV_AUD_CPU, "dout_cmu_div_aud_cpu", + "mout_cmu_mux_aud_cpu", CLK_CON_DIV_DIV_CLKCMU_AUD_CPU, 0, 3), + DIV(CLK_DOUT_CMU_DIV_AUD_CPU_SM, "dout_cmu_div_aud_cpu_sm", + "mout_cmu_aud_cpu", CLK_CON_DIV_DIV_CLKCMU_AUD_CPU_SM, 0, 3), + DIV(CLK_DOUT_CMU_DIV_CIS_CLK0, "dout_cmu_div_cis_clk0", + "mout_cmu_mux_cis_clk0", CLK_CON_DIV_DIV_CLKCMU_CIS_CLK0, 0, 5), + DIV(CLK_DOUT_CMU_DIV_CIS_CLK1, "dout_cmu_div_cis_clk1", + "mout_cmu_mux_cis_clk1", CLK_CON_DIV_DIV_CLKCMU_CIS_CLK1, 0, 5), + DIV(CLK_DOUT_CMU_DIV_CIS_CLK2, "dout_cmu_div_cis_clk2", + "mout_cmu_mux_cis_clk2", CLK_CON_DIV_DIV_CLKCMU_CIS_CLK2, 0, 5), + DIV(CLK_DOUT_CMU_DIV_CIS_CLK3, "dout_cmu_div_cis_clk3", + "mout_cmu_mux_cis_clk3", CLK_CON_DIV_DIV_CLKCMU_CIS_CLK3, 0, 5), + DIV(CLK_DOUT_CMU_DIV_CIS_CLK4, "dout_cmu_div_cis_clk4", + "mout_cmu_mux_cis_clk4", CLK_CON_DIV_DIV_CLKCMU_CIS_CLK4, 0, 5), + DIV(CLK_DOUT_CMU_DIV_CIS_CLK5, "dout_cmu_div_cis_clk5", + "mout_cmu_mux_cis_clk5", CLK_CON_DIV_DIV_CLKCMU_CIS_CLK5, 0, 5), + DIV(CLK_DOUT_CMU_DIV_CIS_CLK6, "dout_cmu_div_cis_clk6", + "mout_cmu_mux_cis_clk6", CLK_CON_DIV_DIV_CLKCMU_CIS_CLK6, 0, 5), + DIV(CLK_DOUT_CMU_DIV_CIS_CLK7, "dout_cmu_div_cis_clk7", + "mout_cmu_mux_cis_clk7", CLK_CON_DIV_DIV_CLKCMU_CIS_CLK7, 0, 5), + DIV(CLK_DOUT_CMU_DIV_CPUCL0_DBG_NOC, "dout_cmu_div_cpucl0_dbg_noc", + "mout_cmu_mux_cpucl0_dbg_noc", + CLK_CON_DIV_DIV_CLKCMU_CPUCL0_DBG_NOC, 0, 4), + DIV(CLK_DOUT_CMU_DIV_CPUCL0_DBG_NOC_SM, + "dout_cmu_div_cpucl0_dbg_noc_sm", "mout_cmu_cpucl0_dbg_noc", + CLK_CON_DIV_DIV_CLKCMU_CPUCL0_DBG_NOC_SM, 0, 4), + DIV(CLK_DOUT_CMU_DIV_CPUCL0_SWITCH, "dout_cmu_div_cpucl0_switch", + "mout_cmu_mux_cpucl0_switch", CLK_CON_DIV_DIV_CLKCMU_CPUCL0_SWITCH, + 0, 3), + DIV(CLK_DOUT_CMU_DIV_CPUCL0_SWITCH_SM, "dout_cmu_div_cpucl0_switch_sm", + "mout_cmu_cpucl0_switch", CLK_CON_DIV_DIV_CLKCMU_CPUCL0_SWITCH_SM, + 0, 3), + DIV(CLK_DOUT_CMU_DIV_CPUCL1_SWITCH, "dout_cmu_div_cpucl1_switch", + "mout_cmu_mux_cpucl1_switch", CLK_CON_DIV_DIV_CLKCMU_CPUCL1_SWITCH, + 0, 3), + DIV(CLK_DOUT_CMU_DIV_CPUCL1_SWITCH_SM, "dout_cmu_div_cpucl1_switch_sm", + "mout_cmu_cpucl1_switch", CLK_CON_DIV_DIV_CLKCMU_CPUCL1_SWITCH_SM, + 0, 3), + DIV(CLK_DOUT_CMU_DIV_CPUCL2_SWITCH, "dout_cmu_div_cpucl2_switch", + "mout_cmu_mux_cpucl2_switch", CLK_CON_DIV_DIV_CLKCMU_CPUCL2_SWITCH, + 0, 3), + DIV(CLK_DOUT_CMU_DIV_CPUCL2_SWITCH_SM, "dout_cmu_div_cpucl2_switch_sm", + "mout_cmu_cpucl2_switch", CLK_CON_DIV_DIV_CLKCMU_CPUCL2_SWITCH_SM, + 0, 3), + DIV(CLK_DOUT_CMU_DIV_DNC_NOC, "dout_cmu_div_dnc_noc", + "mout_cmu_mux_dnc_noc", CLK_CON_DIV_DIV_CLKCMU_DNC_NOC, 0, 4), + DIV(CLK_DOUT_CMU_DIV_DNC_NOC_SM, "dout_cmu_div_dnc_noc_sm", + "mout_cmu_dnc_noc", CLK_CON_DIV_DIV_CLKCMU_DNC_NOC_SM, 0, 4), + DIV(CLK_DOUT_CMU_DIV_DPUB, "dout_cmu_div_dpub", "mout_cmu_mux_dpub", + CLK_CON_DIV_DIV_CLKCMU_DPUB, 0, 4), + DIV(CLK_DOUT_CMU_DIV_DPUB_ALT, "dout_cmu_div_dpub_alt", + "mout_cmu_mux_dpub_alt", CLK_CON_DIV_DIV_CLKCMU_DPUB_ALT, 0, 4), + DIV(CLK_DOUT_CMU_DIV_DPUF, "dout_cmu_div_dpuf", "mout_cmu_mux_dpuf", + CLK_CON_DIV_DIV_CLKCMU_DPUF, 0, 4), + DIV(CLK_DOUT_CMU_DIV_DPUF_ALT, "dout_cmu_div_dpuf_alt", + "mout_cmu_mux_dpuf_alt", CLK_CON_DIV_DIV_CLKCMU_DPUF_ALT, 0, 4), + DIV(CLK_DOUT_CMU_DIV_DSP_NOC, "dout_cmu_div_dsp_noc", + "mout_cmu_mux_dsp_noc", CLK_CON_DIV_DIV_CLKCMU_DSP_NOC, 0, 4), + DIV(CLK_DOUT_CMU_DIV_DSP_NOC_SM, "dout_cmu_div_dsp_noc_sm", + "mout_cmu_dsp_noc", CLK_CON_DIV_DIV_CLKCMU_DSP_NOC_SM, 0, 4), + DIV(CLK_DOUT_CMU_DIV_DSU_SWITCH, "dout_cmu_div_dsu_switch", + "mout_cmu_mux_dsu_switch", CLK_CON_DIV_DIV_CLKCMU_DSU_SWITCH, + 0, 3), + DIV(CLK_DOUT_CMU_DIV_DSU_SWITCH_SM, "dout_cmu_div_dsu_switch_sm", + "mout_cmu_dsu_switch", CLK_CON_DIV_DIV_CLKCMU_DSU_SWITCH_SM, 0, 3), + DIV(CLK_DOUT_CMU_DIV_G3D_SWITCH, "dout_cmu_div_g3d_switch", + "mout_cmu_mux_g3d_switch", CLK_CON_DIV_DIV_CLKCMU_G3D_SWITCH, + 0, 3), + DIV(CLK_DOUT_CMU_DIV_G3D_SWITCH_SM, "dout_cmu_div_g3d_switch_sm", + "mout_cmu_g3d_switch", CLK_CON_DIV_DIV_CLKCMU_G3D_SWITCH_SM, 0, 3), + DIV(CLK_DOUT_CMU_DIV_GNPU_NOC, "dout_cmu_div_gnpu_noc", + "mout_cmu_mux_gnpu_noc", CLK_CON_DIV_DIV_CLKCMU_GNPU_NOC, 0, 4), + DIV(CLK_DOUT_CMU_DIV_GNPU_NOC_SM, "dout_cmu_div_gnpu_noc_sm", + "mout_cmu_gnpu_noc", CLK_CON_DIV_DIV_CLKCMU_GNPU_NOC_SM, 0, 4), + DIV(CLK_DOUT_CMU_DIV_UFS_MMC_CARD, "dout_cmu_div_ufs_mmc_card", + "mout_cmu_mux_ufs_mmc_card", CLK_CON_DIV_DIV_CLKCMU_UFS_MMC_CARD, + 0, 9), + DIV(CLK_DOUT_CMU_DIV_UFS_MMC_CARD_SM, "dout_cmu_div_ufs_mmc_card_sm", + "mout_cmu_ufs_mmc_card", CLK_CON_DIV_DIV_CLKCMU_UFS_MMC_CARD_SM, + 0, 9), + DIV(CLK_DOUT_CMU_DIV_M2M_NOC, "dout_cmu_div_m2m_noc", + "mout_cmu_mux_m2m_noc", CLK_CON_DIV_DIV_CLKCMU_M2M_NOC, 0, 4), + DIV(CLK_DOUT_CMU_DIV_M2M_NOC_SM, "dout_cmu_div_m2m_noc_sm", + "mout_cmu_m2m_noc", CLK_CON_DIV_DIV_CLKCMU_M2M_NOC_SM, 0, 4), + DIV(CLK_DOUT_CMU_DIV_NOCL0_NOC, "dout_cmu_div_nocl0_noc", + "mout_cmu_mux_nocl0_noc", CLK_CON_DIV_DIV_CLKCMU_NOCL0_NOC, + 0, 4), + DIV(CLK_DOUT_CMU_DIV_NOCL0_NOC_SM, "dout_cmu_div_nocl0_noc_sm", + "mout_cmu_nocl0_noc", CLK_CON_DIV_DIV_CLKCMU_NOCL0_NOC_SM, 0, 4), + DIV(CLK_DOUT_CMU_DIV_NOCL1A_NOC, "dout_cmu_div_nocl1a_noc", + "mout_cmu_mux_nocl1a_noc", CLK_CON_DIV_DIV_CLKCMU_NOCL1A_NOC, + 0, 4), + DIV(CLK_DOUT_CMU_DIV_NOCL1A_NOC_SM, "dout_cmu_div_nocl1a_noc_sm", + "mout_cmu_nocl1a_noc", CLK_CON_DIV_DIV_CLKCMU_NOCL1A_NOC_SM, 0, 4), + DIV(CLK_DOUT_CMU_DIV_NOCL1B_NOC0, "dout_cmu_div_nocl1b_noc0", + "mout_cmu_mux_nocl1b_noc0", CLK_CON_DIV_DIV_CLKCMU_NOCL1B_NOC0, + 0, 4), + DIV(CLK_DOUT_CMU_DIV_NOCL1B_NOC0_SM, "dout_cmu_div_nocl1b_noc0_sm", + "mout_cmu_nocl1b_noc0", CLK_CON_DIV_DIV_CLKCMU_NOCL1B_NOC0_SM, + 0, 4), + DIV(CLK_DOUT_CMU_DIV_NOCL1C_NOC, "dout_cmu_div_nocl1c_noc", + "mout_cmu_mux_nocl1c_noc", CLK_CON_DIV_DIV_CLKCMU_NOCL1C_NOC, + 0, 4), + DIV(CLK_DOUT_CMU_DIV_NOCL1C_NOC_SM, "dout_cmu_div_nocl1c_noc_sm", + "mout_cmu_nocl1c_noc", CLK_CON_DIV_DIV_CLKCMU_NOCL1C_NOC_SM, 0, 4), + DIV(CLK_DOUT_CMU_DIV_SDMA_NOC, "dout_cmu_div_sdma_noc", + "mout_cmu_mux_sdma_noc", CLK_CON_DIV_DIV_CLKCMU_SDMA_NOC, 0, 4), + DIV(CLK_DOUT_CMU_DIV_SDMA_NOC_SM, "dout_cmu_div_sdma_noc_sm", + "mout_cmu_sdma_noc", CLK_CON_DIV_DIV_CLKCMU_SDMA_NOC_SM, 0, 4), + DIV(CLK_DOUT_CMU_DIV_CP_HISPEEDY_CLK, "dout_cmu_div_cp_hispeedy_clk", + "mout_cmu_mux_cp_hispeedy_clk", CLK_CON_DIV_DIV_CP_HISPEEDY_CLK, + 0, 4), + DIV(CLK_DOUT_CMU_DIV_CP_HISPEEDY_CLK_SM, + "dout_cmu_div_cp_hispeedy_clk_sm", "mout_cmu_mux_cp_hispeedy_clk", + CLK_CON_DIV_DIV_CP_HISPEEDY_CLK_SM, 0, 4), + DIV(CLK_DOUT_CMU_DIV_CP_SHARED0_CLK, "dout_cmu_div_cp_shared0_clk", + "mout_cmu_mux_cp_shared0_clk", CLK_CON_DIV_DIV_CP_SHARED0_CLK, + 0, 3), + DIV(CLK_DOUT_CMU_DIV_CP_SHARED0_CLK_SM, + "dout_cmu_div_cp_shared0_clk_sm", "mout_cmu_cp_shared0_clk", + CLK_CON_DIV_DIV_CP_SHARED0_CLK_SM, 0, 3), + DIV(CLK_DOUT_CMU_DIV_CP_SHARED2_CLK, "dout_cmu_div_cp_shared2_clk", + "mout_cmu_mux_cp_shared2_clk", CLK_CON_DIV_DIV_CP_SHARED2_CLK, + 0, 3), + DIV(CLK_DOUT_CMU_DIV_CP_SHARED2_CLK_SM, + "dout_cmu_div_cp_shared2_clk_sm", "mout_cmu_cp_shared2_clk", + CLK_CON_DIV_DIV_CP_SHARED2_CLK_SM, 0, 3), + DIV(CLK_DOUT_CMU_UFS_NOC, "dout_cmu_ufs_noc", "mout_cmu_mux_ufs_noc", + CLK_CON_DIV_CLKCMU_UFS_NOC, 0, 4), + DIV(CLK_DOUT_CMU_DIV_M2M_FRC, "dout_cmu_div_m2m_frc", + "mout_cmu_mux_m2m_frc", CLK_CON_DIV_DIV_CLKCMU_M2M_FRC, 0, 4), + DIV(CLK_DOUT_CMU_DIV_M2M_FRC_SM, "dout_cmu_div_m2m_frc_sm", + "mout_cmu_m2m_frc", CLK_CON_DIV_DIV_CLKCMU_M2M_FRC_SM, 0, 4), + DIV(CLK_DOUT_CMU_DIV_MCSC_MCSC, "dout_cmu_div_mcsc_mcsc", + "mout_cmu_mux_mcsc_mcsc", CLK_CON_DIV_DIV_CLKCMU_MCSC_MCSC, 0, 4), + DIV(CLK_DOUT_CMU_DIV_MCSC_MCSC_SM, "dout_cmu_div_mcsc_mcsc_sm", + "mout_cmu_mcsc_mcsc", CLK_CON_DIV_DIV_CLKCMU_MCSC_MCSC_SM, 0, 4), + DIV(CLK_DOUT_CMU_DIV_MCSC_NOC, "dout_cmu_div_mcsc_noc", + "mout_cmu_mux_mcsc_noc", CLK_CON_DIV_DIV_CLKCMU_MCSC_NOC, 0, 4), + DIV(CLK_DOUT_CMU_DIV_MCSC_NOC_SM, "dout_cmu_div_mcsc_noc_sm", + "mout_cmu_mcsc_noc", CLK_CON_DIV_DIV_CLKCMU_MCSC_NOC_SM, 0, 4), +}; + +static const struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initconst = { + FFACTOR(CLK_DOUT_SHARED0_DIV1, "dout_shared0_div1", + "fout_shared0_pll", 1, 1, 0), + FFACTOR(CLK_DOUT_SHARED0_DIV2, "dout_shared0_div2", + "fout_shared0_pll", 1, 2, 0), + FFACTOR(CLK_DOUT_SHARED0_DIV4, "dout_shared0_div4", + "fout_shared0_pll", 1, 4, 0), + FFACTOR(CLK_DOUT_SHARED1_DIV1, "dout_shared1_div1", + "fout_shared1_pll", 1, 1, 0), + FFACTOR(CLK_DOUT_SHARED1_DIV2, "dout_shared1_div2", + "fout_shared1_pll", 1, 2, 0), + FFACTOR(CLK_DOUT_SHARED1_DIV4, "dout_shared1_div4", + "fout_shared1_pll", 1, 4, 0), + FFACTOR(CLK_DOUT_SHARED2_DIV1, "dout_shared2_div1", + "fout_shared2_pll", 1, 1, 0), + FFACTOR(CLK_DOUT_SHARED2_DIV2, "dout_shared2_div2", + "fout_shared2_pll", 1, 2, 0), + FFACTOR(CLK_DOUT_SHARED2_DIV4, "dout_shared2_div4", + "fout_shared2_pll", 1, 4, 0), + FFACTOR(CLK_DOUT_SHARED3_DIV1, "dout_shared3_div1", + "fout_shared3_pll", 1, 1, 0), + FFACTOR(CLK_DOUT_SHARED3_DIV2, "dout_shared3_div2", + "fout_shared3_pll", 1, 2, 0), + FFACTOR(CLK_DOUT_SHARED3_DIV4, "dout_shared3_div4", + "fout_shared3_pll", 1, 4, 0), + FFACTOR(CLK_DOUT_SHARED4_DIV1, "dout_shared4_div1", + "fout_shared4_pll", 1, 1, 0), + FFACTOR(CLK_DOUT_SHARED4_DIV2, "dout_shared4_div2", + "fout_shared4_pll", 1, 2, 0), + FFACTOR(CLK_DOUT_SHARED4_DIV4, "dout_shared4_div4", + "fout_shared4_pll", 1, 4, 0), + FFACTOR(CLK_DOUT_SHARED_MIF_DIV1, "dout_shared_mif_div1", + "fout_shared_mif_pll", 1, 1, 0), + FFACTOR(CLK_DOUT_SHARED_MIF_DIV2, "dout_shared_mif_div2", + "fout_shared_mif_pll", 1, 2, 0), + FFACTOR(CLK_DOUT_SHARED_MIF_DIV4, "dout_shared_mif_div4", + "fout_shared_mif_pll", 1, 4, 0), + FFACTOR(CLK_DOUT_SHARED_MIF_DIV4, "dout_mmc_div1", + "fout_mmc_pll", 1, 1, 0), + FFACTOR(CLK_DOUT_SHARED_MIF_DIV4, "dout_mmc_div2", + "fout_mmc_pll", 1, 2, 0), + FFACTOR(CLK_DOUT_SHARED_MIF_DIV4, "dout_mmc_div4", + "fout_mmc_pll", 1, 4, 0), + FFACTOR(CLK_DOUT_TCXO_DIV3, "dout_tcxo_div3", + "oscclk", 1, 3, 0), + FFACTOR(CLK_DOUT_TCXO_DIV4, "dout_tcxo_div4", + "oscclk", 1, 4, 0), +}; + +static const struct samsung_cmu_info top_cmu_info __initconst = { + .pll_clks = top_pll_clks, + .nr_pll_clks = ARRAY_SIZE(top_pll_clks), + .mux_clks = top_mux_clks, + .nr_mux_clks = ARRAY_SIZE(top_mux_clks), + .div_clks = top_div_clks, + .nr_div_clks = ARRAY_SIZE(top_div_clks), + .fixed_factor_clks = top_fixed_factor_clks, + .nr_fixed_factor_clks = ARRAY_SIZE(top_fixed_factor_clks), + .nr_clk_ids = CLKS_NR_TOP, + .clk_regs = top_clk_regs, + .nr_clk_regs = ARRAY_SIZE(top_clk_regs), +}; + +static void __init exynos2200_cmu_top_init(struct device_node *np) +{ + exynos_arm64_register_cmu(NULL, np, &top_cmu_info); +} + +/* Register CMU_TOP early, as it's a dependency for other early domains */ +CLK_OF_DECLARE(exynos2200_cmu_top, "samsung,exynos2200-cmu-top", + exynos2200_cmu_top_init); + +/* ---- CMU_ALIVE ---------------------------------------------------------- */ + +/* Register Offset definitions for CMU_ALIVE (0x15800000) */ +#define PLL_CON0_MUX_CLKCMU_ALIVE_NOC_USER 0x600 +#define PLL_CON1_MUX_CLKCMU_ALIVE_NOC_USER 0x604 +#define PLL_CON0_MUX_CLKMUX_ALIVE_RCO_SPMI_USER 0x610 +#define PLL_CON1_MUX_CLKMUX_ALIVE_RCO_SPMI_USER 0x614 +#define PLL_CON0_MUX_CLK_RCO_ALIVE_USER 0x620 +#define PLL_CON1_MUX_CLK_RCO_ALIVE_USER 0x624 +#define CLK_CON_MUX_MUX_CLKALIVE_CHUB_PERI 0x1004 +#define CLK_CON_MUX_MUX_CLKALIVE_CMGP_NOC 0x1008 +#define CLK_CON_MUX_MUX_CLKALIVE_CMGP_PERI 0x100c +#define CLK_CON_MUX_MUX_CLKALIVE_DBGCORE_NOC 0x1010 +#define CLK_CON_MUX_MUX_CLKALIVE_DNC_NOC 0x1014 +#define CLK_CON_MUX_MUX_CLKALIVE_CHUBVTS_NOC 0x1018 +#define CLK_CON_MUX_MUX_CLKALIVE_GNPU_NOC 0x101c +#define CLK_CON_MUX_MUX_CLKALIVE_GNSS_NOC 0x1020 +#define CLK_CON_MUX_MUX_CLKALIVE_SDMA_NOC 0x1024 +#define CLK_CON_MUX_MUX_CLKALIVE_UFD_NOC 0x1028 +#define CLK_CON_MUX_MUX_CLK_ALIVE_DBGCORE_UART 0x1030 +#define CLK_CON_MUX_MUX_CLK_ALIVE_NOC 0x1034 +#define CLK_CON_MUX_MUX_CLK_ALIVE_PMU_SUB 0x1038 +#define CLK_CON_MUX_MUX_CLK_ALIVE_SPMI 0x103c +#define CLK_CON_MUX_MUX_CLK_ALIVE_TIMER 0x1040 +#define CLK_CON_MUX_MUX_CLKALIVE_CSIS_NOC 0x1044 +#define CLK_CON_MUX_MUX_CLKALIVE_DSP_NOC 0x1048 +#define CLK_CON_DIV_CLKALIVE_CHUB_PERI 0x1804 +#define CLK_CON_DIV_CLKALIVE_CMGP_NOC 0x1808 +#define CLK_CON_DIV_CLKALIVE_CMGP_PERI 0x180c +#define CLK_CON_DIV_CLKALIVE_DBGCORE_NOC 0x1810 +#define CLK_CON_DIV_CLKALIVE_DNC_NOC 0x1814 +#define CLK_CON_DIV_CLKALIVE_CHUBVTS_NOC 0x1818 +#define CLK_CON_DIV_CLKALIVE_GNPU_NOC 0x181c +#define CLK_CON_DIV_CLKALIVE_SDMA_NOC 0x1820 +#define CLK_CON_DIV_CLKALIVE_UFD_NOC 0x1824 +#define CLK_CON_DIV_DIV_CLK_ALIVE_DBGCORE_UART 0x182c +#define CLK_CON_DIV_DIV_CLK_ALIVE_NOC 0x1830 +#define CLK_CON_DIV_DIV_CLK_ALIVE_PMU_SUB 0x1834 +#define CLK_CON_DIV_DIV_CLK_ALIVE_SPMI 0x1838 +#define CLK_CON_DIV_CLKALIVE_CSIS_NOC 0x183c +#define CLK_CON_DIV_CLKALIVE_DSP_NOC 0x1840 +#define CLK_CON_GAT_CLKALIVE_CHUBVTS_RCO 0x2000 +#define CLK_CON_GAT_CLKALIVE_DNC_RCO 0x2004 +#define CLK_CON_GAT_CLKALIVE_CSIS_RCO 0x2008 +#define CLK_CON_GAT_CLKALIVE_GNPU_RCO 0x200c +#define CLK_CON_GAT_CLKALIVE_GNSS_NOC 0x2010 +#define CLK_CON_GAT_CLKALIVE_SDMA_RCO 0x2014 +#define CLK_CON_GAT_CLKALIVE_UFD_RCO 0x2018 +#define CLK_CON_GAT_CLKALIVE_DSP_RCO 0x201c +#define CLK_CON_GAT_CLK_BLK_ALIVE_UID_ALIVE_CMU_ALIVE_IPCLKPORT_PCLK 0x2020 +#define CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK 0x2024 +#define CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_INTCOMB_VGPIO2APM_IPCLKPORT_PCLK 0x2028 +#define CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_INTCOMB_VGPIO2AP_IPCLKPORT_PCLK 0x202c +#define CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_INTCOMB_VGPIO2PMU_IPCLKPORT_PCLK 0x2030 +#define CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK 0x2034 +#define CLK_CON_GAT_CLK_BLK_ALIVE_UID_APM_DMA_IPCLKPORT_PCLK 0x2038 +#define CLK_CON_GAT_CLK_BLK_ALIVE_UID_CHUB_RTC_IPCLKPORT_OSCCLK 0x203c +#define CLK_CON_GAT_CLK_BLK_ALIVE_UID_CHUB_RTC_IPCLKPORT_PCLK 0x2040 +#define CLK_CON_GAT_CLK_BLK_ALIVE_UID_CLKMON_IPCLKPORT_PCLK 0x2044 +#define CLK_CON_GAT_CLK_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_IPCLK 0x2048 +#define CLK_CON_GAT_CLK_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_PCLK 0x204c +#define CLK_CON_GAT_CLK_BLK_ALIVE_UID_BLK_ALIVE_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK 0x2050 +#define CLK_CON_GAT_CLK_BLK_ALIVE_UID_DTZPC_ALIVE_IPCLKPORT_PCLK 0x2054 +#define CLK_CON_GAT_CLK_BLK_ALIVE_UID_GREBEINTEGRATION_IPCLKPORT_HCLK 0x2058 +#define CLK_CON_GAT_CLK_BLK_ALIVE_UID_HW_SCANDUMP_CLKSTOP_CTRL_IPCLKPORT_ACLK 0x205c +#define CLK_CON_GAT_CLK_BLK_ALIVE_UID_INTMEM_IPCLKPORT_I_ACLK 0x2060 +#define CLK_CON_GAT_CLK_BLK_ALIVE_UID_INTMEM_IPCLKPORT_I_PCLK 0x2064 +#define CLK_CON_GAT_CLK_BLK_ALIVE_UID_LH_AXI_SI_D_APM_IPCLKPORT_I_CLK 0x2068 +#define CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK 0x206c +#define CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_CHUB_IPCLKPORT_PCLK 0x2070 +#define CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_CP_IPCLKPORT_PCLK 0x2074 +#define CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_GNSS_IPCLKPORT_PCLK 0x2078 +#define CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_VTS_IPCLKPORT_PCLK 0x207c +#define CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_CHUB_IPCLKPORT_PCLK 0x2080 +#define CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_CP_IPCLKPORT_PCLK 0x2084 +#define CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_CP_S_IPCLKPORT_PCLK 0x2088 +#define CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK 0x208c +#define CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_GNSS_IPCLKPORT_PCLK 0x2090 +#define CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_CP_CHUB_IPCLKPORT_PCLK 0x2094 +#define CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_CP_GNSS_IPCLKPORT_PCLK 0x2098 +#define CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_GNSS_CHUB_IPCLKPORT_PCLK 0x209c +#define CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_SHARED_SRAM_IPCLKPORT_PCLK 0x20a0 +#define CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_AUD_IPCLKPORT_PCLK 0x20a4 +#define CLK_CON_GAT_CLK_BLK_ALIVE_UID_MCT_ALIVE_IPCLKPORT_I_PCLK 0x20a8 +#define CLK_CON_GAT_CLK_BLK_ALIVE_UID_PMU_INTR_GEN_IPCLKPORT_PCLK 0x20ac +#define CLK_CON_GAT_CLK_BLK_ALIVE_UID_PMU_IPCLKPORT_ACLK 0x20b0 +#define CLK_CON_GAT_CLK_BLK_ALIVE_UID_PMU_IPCLKPORT_CLKIN_PMU_SUB 0x20b4 +#define CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_CP_1_IPCLKPORT_PCLK 0x20b8 +#define CLK_CON_GAT_CLK_BLK_ALIVE_UID_OTP_DESERIAL_ALIVE_IPCLKPORT_I_CLK 0x20bc +#define CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_DBGCORE_UART_IPCLKPORT_CLK 0x20c0 +#define CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_FREE_OSCCLK_IPCLKPORT_CLK 0x20c4 +#define CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_IPCLKPORT_CLK 0x20c8 +#define CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_NOC_IPCLKPORT_CLK 0x20cc +#define CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_OSCCLK_RCO_IPCLKPORT_CLK 0x20d0 +#define CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_SPMI_IPCLKPORT_CLK 0x20d4 +#define CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_TIMER_IPCLKPORT_CLK 0x20d8 +#define CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_NOC_IPCLKPORT_CLK 0x20dc +#define CLK_CON_GAT_CLK_BLK_ALIVE_UID_RTC_IPCLKPORT_PCLK 0x20e0 +#define CLK_CON_GAT_CLK_BLK_ALIVE_UID_OTP_HCU_DESERIAL_IPCLKPORT_I_CLK 0x20e4 +#define CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_LD_GNSS_IPCLKPORT_I_CLK 0x20e8 +#define CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_LP_MODEM_IPCLKPORT_I_CLK 0x20ec +#define CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_LD_CHUBVTS_IPCLKPORT_I_CLK 0x20f0 +#define CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_ID_DBGCORE_IPCLKPORT_I_CLK 0x20f4 +#define CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_P_APM_IPCLKPORT_I_CLK 0x20f8 +#define CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_CMGP_IPCLKPORT_I_CLK 0x20fc +#define CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_IP_APM_IPCLKPORT_I_CLK 0x2100 +#define CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_FREE_OSCCLK_IPCLKPORT_CLK 0x2104 +#define CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_CHUBVTS_IPCLKPORT_I_CLK 0x2108 +#define CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_PPU_IPCLKPORT_I_CLK 0x210c +#define CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_ALIVEDNC_IPCLKPORT_I_CLK 0x2110 +#define CLK_CON_GAT_CLK_BLK_ALIVE_UID_SPC_ALIVE_IPCLKPORT_PCLK 0x2114 +#define CLK_CON_GAT_CLK_BLK_ALIVE_UID_SPMI_MASTER_PMIC_IPCLKPORT_I_IPCLK 0x2118 +#define CLK_CON_GAT_CLK_BLK_ALIVE_UID_SPMI_MASTER_PMIC_IPCLKPORT_I_PCLK 0x211c +#define CLK_CON_GAT_CLK_BLK_ALIVE_UID_SWEEPER_P_ALIVE_IPCLKPORT_ACLK 0x2120 +#define CLK_CON_GAT_CLK_BLK_ALIVE_UID_SYSREG_ALIVE_IPCLKPORT_PCLK 0x2124 +#define CLK_CON_GAT_CLK_BLK_ALIVE_UID_TOP_RTC_IPCLKPORT_OSCCLK 0x2128 +#define CLK_CON_GAT_CLK_BLK_ALIVE_UID_TOP_RTC_IPCLKPORT_PCLK 0x212c +#define CLK_CON_GAT_CLK_BLK_ALIVE_UID_VGEN_LITE_ALIVE_IPCLKPORT_CLK 0x2130 +#define CLK_CON_GAT_CLK_BLK_ALIVE_UID_WDT_ALIVE_IPCLKPORT_PCLK 0x2134 +#define CLK_CON_GAT_CLK_BLK_ALIVE_UID_XIU_DP_ALIVE_IPCLKPORT_ACLK 0x2138 +#define CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_OSCCLK_RCO_IPCLKPORT_CLK 0x213c +#define CLK_CON_GAT_GATE_CLKALIVE_CHUB_PERI 0x2140 +#define CLK_CON_GAT_GATE_CLKALIVE_CMGP_NOC 0x2144 +#define CLK_CON_GAT_GATE_CLKALIVE_CMGP_PERI 0x2148 +#define CLK_CON_GAT_GATE_CLKALIVE_DBGCORE_NOC 0x214c +#define CLK_CON_GAT_GATE_CLKALIVE_DNC_NOC 0x2150 +#define CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_SPMI_IPCLKPORT_CLK 0x2154 +#define CLK_CON_GAT_GATE_CLKALIVE_GNPU_NOC 0x2158 +#define CLK_CON_GAT_GATE_CLKALIVE_SDMA_NOC 0x215c +#define CLK_CON_GAT_GATE_CLKALIVE_UFD_NOC 0x2160 +#define CLK_CON_GAT_GATE_CLKALIVE_CHUBVTS_NOC 0x2164 +#define CLK_CON_GAT_GATE_CLKALIVE_CSIS_NOC 0x2168 +#define CLK_CON_GAT_GATE_CLKALIVE_DSP_NOC 0x216c + +static const unsigned long alive_clk_regs[] __initconst = { + PLL_CON0_MUX_CLKCMU_ALIVE_NOC_USER, + PLL_CON1_MUX_CLKCMU_ALIVE_NOC_USER, + PLL_CON0_MUX_CLKMUX_ALIVE_RCO_SPMI_USER, + PLL_CON1_MUX_CLKMUX_ALIVE_RCO_SPMI_USER, + PLL_CON0_MUX_CLK_RCO_ALIVE_USER, + PLL_CON1_MUX_CLK_RCO_ALIVE_USER, + CLK_CON_MUX_MUX_CLKALIVE_CHUB_PERI, + CLK_CON_MUX_MUX_CLKALIVE_CMGP_NOC, + CLK_CON_MUX_MUX_CLKALIVE_CMGP_PERI, + CLK_CON_MUX_MUX_CLKALIVE_DBGCORE_NOC, + CLK_CON_MUX_MUX_CLKALIVE_DNC_NOC, + CLK_CON_MUX_MUX_CLKALIVE_CHUBVTS_NOC, + CLK_CON_MUX_MUX_CLKALIVE_GNPU_NOC, + CLK_CON_MUX_MUX_CLKALIVE_GNSS_NOC, + CLK_CON_MUX_MUX_CLKALIVE_SDMA_NOC, + CLK_CON_MUX_MUX_CLKALIVE_UFD_NOC, + CLK_CON_MUX_MUX_CLK_ALIVE_DBGCORE_UART, + CLK_CON_MUX_MUX_CLK_ALIVE_NOC, + CLK_CON_MUX_MUX_CLK_ALIVE_PMU_SUB, + CLK_CON_MUX_MUX_CLK_ALIVE_SPMI, + CLK_CON_MUX_MUX_CLK_ALIVE_TIMER, + CLK_CON_MUX_MUX_CLKALIVE_CSIS_NOC, + CLK_CON_MUX_MUX_CLKALIVE_DSP_NOC, + CLK_CON_DIV_CLKALIVE_CHUB_PERI, + CLK_CON_DIV_CLKALIVE_CMGP_NOC, + CLK_CON_DIV_CLKALIVE_CMGP_PERI, + CLK_CON_DIV_CLKALIVE_DBGCORE_NOC, + CLK_CON_DIV_CLKALIVE_DNC_NOC, + CLK_CON_DIV_CLKALIVE_CHUBVTS_NOC, + CLK_CON_DIV_CLKALIVE_GNPU_NOC, + CLK_CON_DIV_CLKALIVE_SDMA_NOC, + CLK_CON_DIV_CLKALIVE_UFD_NOC, + CLK_CON_DIV_DIV_CLK_ALIVE_DBGCORE_UART, + CLK_CON_DIV_DIV_CLK_ALIVE_NOC, + CLK_CON_DIV_DIV_CLK_ALIVE_PMU_SUB, + CLK_CON_DIV_DIV_CLK_ALIVE_SPMI, + CLK_CON_DIV_CLKALIVE_CSIS_NOC, + CLK_CON_DIV_CLKALIVE_DSP_NOC, + CLK_CON_GAT_CLKALIVE_CHUBVTS_RCO, + CLK_CON_GAT_CLKALIVE_DNC_RCO, + CLK_CON_GAT_CLKALIVE_CSIS_RCO, + CLK_CON_GAT_CLKALIVE_GNPU_RCO, + CLK_CON_GAT_CLKALIVE_GNSS_NOC, + CLK_CON_GAT_CLKALIVE_SDMA_RCO, + CLK_CON_GAT_CLKALIVE_UFD_RCO, + CLK_CON_GAT_CLKALIVE_DSP_RCO, + CLK_CON_GAT_CLK_BLK_ALIVE_UID_ALIVE_CMU_ALIVE_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_INTCOMB_VGPIO2APM_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_INTCOMB_VGPIO2AP_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_INTCOMB_VGPIO2PMU_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_ALIVE_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_ALIVE_UID_APM_DMA_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_ALIVE_UID_CHUB_RTC_IPCLKPORT_OSCCLK, + CLK_CON_GAT_CLK_BLK_ALIVE_UID_CHUB_RTC_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_ALIVE_UID_CLKMON_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_IPCLK, + CLK_CON_GAT_CLK_BLK_ALIVE_UID_DBGCORE_UART_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_ALIVE_UID_BLK_ALIVE_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_ALIVE_UID_DTZPC_ALIVE_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_ALIVE_UID_GREBEINTEGRATION_IPCLKPORT_HCLK, + CLK_CON_GAT_CLK_BLK_ALIVE_UID_HW_SCANDUMP_CLKSTOP_CTRL_IPCLKPORT_ACLK, + CLK_CON_GAT_CLK_BLK_ALIVE_UID_INTMEM_IPCLKPORT_I_ACLK, + CLK_CON_GAT_CLK_BLK_ALIVE_UID_INTMEM_IPCLKPORT_I_PCLK, + CLK_CON_GAT_CLK_BLK_ALIVE_UID_LH_AXI_SI_D_APM_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_CHUB_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_CP_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_GNSS_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_VTS_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_CHUB_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_CP_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_CP_S_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_AP_GNSS_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_CP_CHUB_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_CP_GNSS_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_GNSS_CHUB_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_SHARED_SRAM_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_AUD_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_ALIVE_UID_MCT_ALIVE_IPCLKPORT_I_PCLK, + CLK_CON_GAT_CLK_BLK_ALIVE_UID_PMU_INTR_GEN_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_ALIVE_UID_PMU_IPCLKPORT_ACLK, + CLK_CON_GAT_CLK_BLK_ALIVE_UID_PMU_IPCLKPORT_CLKIN_PMU_SUB, + CLK_CON_GAT_CLK_BLK_ALIVE_UID_MAILBOX_APM_CP_1_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_ALIVE_UID_OTP_DESERIAL_ALIVE_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_DBGCORE_UART_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_FREE_OSCCLK_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_GREBE_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_NOC_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_OSCCLK_RCO_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_SPMI_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_CLK_ALIVE_TIMER_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_NOC_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_ALIVE_UID_RTC_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_ALIVE_UID_OTP_HCU_DESERIAL_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_LD_GNSS_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_LP_MODEM_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_LD_CHUBVTS_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_ID_DBGCORE_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_MI_P_APM_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_CMGP_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_IP_APM_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_FREE_OSCCLK_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_CHUBVTS_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_PPU_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_ALIVE_UID_SLH_AXI_SI_LP_ALIVEDNC_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_ALIVE_UID_SPC_ALIVE_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_ALIVE_UID_SPMI_MASTER_PMIC_IPCLKPORT_I_IPCLK, + CLK_CON_GAT_CLK_BLK_ALIVE_UID_SPMI_MASTER_PMIC_IPCLKPORT_I_PCLK, + CLK_CON_GAT_CLK_BLK_ALIVE_UID_SWEEPER_P_ALIVE_IPCLKPORT_ACLK, + CLK_CON_GAT_CLK_BLK_ALIVE_UID_SYSREG_ALIVE_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_ALIVE_UID_TOP_RTC_IPCLKPORT_OSCCLK, + CLK_CON_GAT_CLK_BLK_ALIVE_UID_TOP_RTC_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_ALIVE_UID_VGEN_LITE_ALIVE_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_ALIVE_UID_WDT_ALIVE_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_ALIVE_UID_XIU_DP_ALIVE_IPCLKPORT_ACLK, + CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_OSCCLK_RCO_IPCLKPORT_CLK, + CLK_CON_GAT_GATE_CLKALIVE_CHUB_PERI, + CLK_CON_GAT_GATE_CLKALIVE_CMGP_NOC, + CLK_CON_GAT_GATE_CLKALIVE_CMGP_PERI, + CLK_CON_GAT_GATE_CLKALIVE_DBGCORE_NOC, + CLK_CON_GAT_GATE_CLKALIVE_DNC_NOC, + CLK_CON_GAT_CLK_BLK_ALIVE_UID_RSTNSYNC_SR_CLK_ALIVE_SPMI_IPCLKPORT_CLK, + CLK_CON_GAT_GATE_CLKALIVE_GNPU_NOC, + CLK_CON_GAT_GATE_CLKALIVE_SDMA_NOC, + CLK_CON_GAT_GATE_CLKALIVE_UFD_NOC, + CLK_CON_GAT_GATE_CLKALIVE_CHUBVTS_NOC, + CLK_CON_GAT_GATE_CLKALIVE_CSIS_NOC, + CLK_CON_GAT_GATE_CLKALIVE_DSP_NOC, +}; + +PNAME(mout_alive_noc_user_p) = { "oscclk", "dout_cmu_alive_noc" }; +PNAME(mout_alive_rco_spmi_user_p) = { "oscclk", "rco_i3c_pmic" }; +PNAME(mout_rco_alive_user_p) = { "oscclk", "rco_alive" }; +PNAME(mout_alive_chub_peri_p) = { "mout_rco_alive_user", "rco_400", + "mout_alive_noc_user", "oscclk" }; +PNAME(mout_alive_cmgp_noc_p) = { "mout_rco_alive_user", "rco_400", + "mout_alive_noc_user", "oscclk" }; +PNAME(mout_alive_cmgp_peri_p) = { "mout_rco_alive_user", "rco_400", + "mout_alive_noc_user", "oscclk" }; +PNAME(mout_alive_dbgcore_noc_p) = { "mout_rco_alive_user", "rco_400", + "mout_alive_noc_user", "oscclk" }; +PNAME(mout_alive_dnc_noc_p) = { "mout_rco_alive_user", "rco_400", + "mout_alive_noc_user", "oscclk" }; +PNAME(mout_alive_chubvts_noc_p) = { "mout_rco_alive_user", "rco_400", + "mout_alive_noc_user", "oscclk" }; +PNAME(mout_alive_gnpu_noc_p) = { "mout_rco_alive_user", "rco_400", + "mout_alive_noc_user", "oscclk" }; +PNAME(mout_alive_gnss_noc_p) = { "rco_400", "mout_alive_noc_user" }; +PNAME(mout_alive_sdma_noc_p) = { "mout_rco_alive_user", "rco_400", + "mout_alive_noc_user", "oscclk" }; +PNAME(mout_alive_ufd_noc_p) = { "mout_rco_alive_user", + "rco_400", + "mout_alive_noc_user", + "oscclk" }; +PNAME(mout_alive_dbgcore_uart_p) = { "mout_rco_alive_user", "rco_400", + "mout_alive_noc_user", "oscclk" }; +PNAME(mout_alive_noc_p) = { "mout_rco_alive_user", "rco_400", + "mout_alive_noc_user", "oscclk" }; +PNAME(mout_alive_pmu_sub_p) = { "mout_rco_alive_user", "rco_400", + "mout_alive_noc_user", "oscclk" }; +PNAME(mout_alive_spmi_p) = { "mout_rco_alive_user", "rco_400", + "mout_alive_rco_spmi_user", + "oscclk" }; +PNAME(mout_alive_timer_p) = { "oscclk", "oscclk" }; +PNAME(mout_alive_csis_noc_p) = { "mout_rco_alive_user", "rco_400", + "mout_alive_noc_user", "oscclk" }; +PNAME(mout_alive_dsp_noc_p) = { "mout_rco_alive_user", "rco_400", + "mout_alive_noc_user", "oscclk" }; + +static const struct samsung_mux_clock alive_mux_clks[] __initconst = { + MUX(CLK_MOUT_ALIVE_NOC_USER, "mout_alive_noc_user", + mout_alive_noc_user_p, PLL_CON0_MUX_CLKCMU_ALIVE_NOC_USER, 4, 1), + MUX(CLK_MOUT_ALIVE_RCO_SPMI_USER, "mout_alive_rco_spmi_user", + mout_alive_rco_spmi_user_p, + PLL_CON0_MUX_CLKMUX_ALIVE_RCO_SPMI_USER, 4, 1), + MUX(CLK_MOUT_RCO_ALIVE_USER, "mout_rco_alive_user", + mout_rco_alive_user_p, PLL_CON0_MUX_CLK_RCO_ALIVE_USER, 4, 1), + MUX(CLK_MOUT_ALIVE_CHUB_PERI, "mout_alive_chub_peri", + mout_alive_chub_peri_p, CLK_CON_MUX_MUX_CLKALIVE_CHUB_PERI, 0, 2), + MUX(CLK_MOUT_ALIVE_CMGP_NOC, "mout_alive_cmgp_noc", + mout_alive_cmgp_noc_p, CLK_CON_MUX_MUX_CLKALIVE_CMGP_NOC, 0, 2), + MUX(CLK_MOUT_ALIVE_CMGP_PERI, "mout_alive_cmgp_peri", + mout_alive_cmgp_peri_p, CLK_CON_MUX_MUX_CLKALIVE_CMGP_PERI, 0, 2), + MUX(CLK_MOUT_ALIVE_DBGCORE_NOC, "mout_alive_dbgcore_noc", + mout_alive_dbgcore_noc_p, CLK_CON_MUX_MUX_CLKALIVE_DBGCORE_NOC, + 0, 2), + MUX(CLK_MOUT_ALIVE_DNC_NOC, "mout_alive_dnc_noc", mout_alive_dnc_noc_p, + CLK_CON_MUX_MUX_CLKALIVE_DNC_NOC, 0, 2), + MUX(CLK_MOUT_ALIVE_CHUBVTS_NOC, "mout_alive_chubvts_noc", + mout_alive_chubvts_noc_p, CLK_CON_MUX_MUX_CLKALIVE_CHUBVTS_NOC, + 0, 2), + MUX(CLK_MOUT_ALIVE_GNPU_NOC, "mout_alive_gnpu_noc", + mout_alive_gnpu_noc_p, CLK_CON_MUX_MUX_CLKALIVE_GNPU_NOC, 0, 2), + MUX(CLK_MOUT_ALIVE_GNSS_NOC, "mout_alive_gnss_noc", + mout_alive_gnss_noc_p, CLK_CON_MUX_MUX_CLKALIVE_GNSS_NOC, 0, 1), + MUX(CLK_MOUT_ALIVE_SDMA_NOC, "mout_alive_sdma_noc", + mout_alive_sdma_noc_p, CLK_CON_MUX_MUX_CLKALIVE_SDMA_NOC, 0, 2), + MUX(CLK_MOUT_ALIVE_UFD_NOC, "mout_alive_ufd_noc", mout_alive_ufd_noc_p, + CLK_CON_MUX_MUX_CLKALIVE_UFD_NOC, 0, 2), + MUX(CLK_MOUT_ALIVE_DBGCORE_UART, "mout_alive_dbgcore_uart", + mout_alive_dbgcore_uart_p, CLK_CON_MUX_MUX_CLK_ALIVE_DBGCORE_UART, + 0, 2), + MUX(CLK_MOUT_ALIVE_NOC, "mout_alive_noc", mout_alive_noc_p, + CLK_CON_MUX_MUX_CLK_ALIVE_NOC, 0, 2), + MUX(CLK_MOUT_ALIVE_PMU_SUB, "mout_alive_pmu_sub", mout_alive_pmu_sub_p, + CLK_CON_MUX_MUX_CLK_ALIVE_PMU_SUB, 0, 2), + MUX(CLK_MOUT_ALIVE_SPMI, "mout_alive_spmi", mout_alive_spmi_p, + CLK_CON_MUX_MUX_CLK_ALIVE_SPMI, 0, 2), + MUX(CLK_MOUT_ALIVE_TIMER, "mout_alive_timer", mout_alive_timer_p, + CLK_CON_MUX_MUX_CLK_ALIVE_TIMER, 0, 1), + MUX(CLK_MOUT_ALIVE_CSIS_NOC, "mout_alive_csis_noc", + mout_alive_csis_noc_p, CLK_CON_MUX_MUX_CLKALIVE_CSIS_NOC, 0, 2), + MUX(CLK_MOUT_ALIVE_DSP_NOC, "mout_alive_dsp_noc", mout_alive_dsp_noc_p, + CLK_CON_MUX_MUX_CLKALIVE_DSP_NOC, 0, 2), +}; + +static const struct samsung_div_clock alive_div_clks[] __initconst = { + DIV(CLK_DOUT_ALIVE_CHUB_PERI, "dout_alive_chub_peri", + "mout_alive_chub_peri", CLK_CON_DIV_CLKALIVE_CHUB_PERI, 0, 3), + DIV(CLK_DOUT_ALIVE_CMGP_NOC, "dout_alive_cmgp_noc", + "mout_alive_cmgp_noc", CLK_CON_DIV_CLKALIVE_CMGP_NOC, 0, 3), + DIV(CLK_DOUT_ALIVE_CMGP_PERI, "dout_alive_cmgp_peri", + "mout_alive_cmgp_peri", CLK_CON_DIV_CLKALIVE_CMGP_PERI, 0, 3), + DIV(CLK_DOUT_ALIVE_DBGCORE_NOC, "dout_alive_dbgcore_noc", + "mout_alive_dbgcore_noc", CLK_CON_DIV_CLKALIVE_DBGCORE_NOC, 0, 3), + DIV(CLK_DOUT_ALIVE_DNC_NOC, "dout_alive_dnc_noc", "mout_alive_dnc_noc", + CLK_CON_DIV_CLKALIVE_DNC_NOC, 0, 3), + DIV(CLK_DOUT_ALIVE_CHUBVTS_NOC, "dout_alive_chubvts_noc", + "mout_alive_chubvts_noc", CLK_CON_DIV_CLKALIVE_CHUBVTS_NOC, 0, 3), + DIV(CLK_DOUT_ALIVE_GNPU_NOC, "dout_alive_gnpu_noc", + "mout_alive_gnpu_noc", CLK_CON_DIV_CLKALIVE_GNPU_NOC, 0, 3), + DIV(CLK_DOUT_ALIVE_SDMA_NOC, "dout_alive_sdma_noc", + "mout_alive_sdma_noc", CLK_CON_DIV_CLKALIVE_SDMA_NOC, 0, 3), + DIV(CLK_DOUT_ALIVE_UFD_NOC, "dout_alive_ufd_noc", "mout_alive_ufd_noc", + CLK_CON_DIV_CLKALIVE_UFD_NOC, 0, 3), + DIV(CLK_DOUT_ALIVE_DBGCORE_UART, "dout_alive_dbgcore_uart", + "mout_alive_dbgcore_uart", CLK_CON_DIV_DIV_CLK_ALIVE_DBGCORE_UART, + 0, 4), + DIV(CLK_DOUT_ALIVE_NOC, "dout_alive_noc", "mout_alive_noc", + CLK_CON_DIV_DIV_CLK_ALIVE_NOC, 0, 3), + DIV(CLK_DOUT_ALIVE_PMU_SUB, "dout_alive_pmu_sub", "mout_alive_pmu_sub", + CLK_CON_DIV_DIV_CLK_ALIVE_PMU_SUB, 0, 3), + DIV(CLK_DOUT_ALIVE_SPMI, "dout_alive_spmi", "mout_alive_spmi", + CLK_CON_DIV_DIV_CLK_ALIVE_SPMI, 0, 5), + DIV(CLK_DOUT_ALIVE_CSIS_NOC, "dout_alive_csis_noc", + "mout_alive_csis_noc", CLK_CON_DIV_CLKALIVE_CSIS_NOC, 0, 3), + DIV(CLK_DOUT_ALIVE_DSP_NOC, "dout_alive_dsp_noc", + "mout_alive_dsp_noc", CLK_CON_DIV_CLKALIVE_DSP_NOC, 0, 3), +}; + +static const struct samsung_fixed_rate_clock alive_fixed_clks[] __initconst = { + FRATE(0, "rco_i3c_pmic", NULL, 0, 49152000), + FRATE(0, "rco_alive", NULL, 0, 49152000), + FRATE(0, "rco_400", NULL, 0, 393216000), +}; + +static const struct samsung_cmu_info alive_cmu_info __initconst = { + .mux_clks = alive_mux_clks, + .nr_mux_clks = ARRAY_SIZE(alive_mux_clks), + .div_clks = alive_div_clks, + .nr_div_clks = ARRAY_SIZE(alive_div_clks), + .fixed_clks = alive_fixed_clks, + .nr_fixed_clks = ARRAY_SIZE(alive_fixed_clks), + .nr_clk_ids = CLKS_NR_ALIVE, + .clk_regs = alive_clk_regs, + .nr_clk_regs = ARRAY_SIZE(alive_clk_regs), + .clk_name = "noc", +}; + +static void __init exynos2200_cmu_alive_init(struct device_node *np) +{ + exynos_arm64_register_cmu(NULL, np, &alive_cmu_info); +} + +/* Register CMU_ALIVE early, as it's a dependency for other early domains */ +CLK_OF_DECLARE(exynos2200_cmu_alive, "samsung,exynos2200-cmu-alive", + exynos2200_cmu_alive_init); + +/* ---- CMU_PERIS ---------------------------------------------------------- */ + +/* Register Offset definitions for CMU_PERIS (0x10020000) */ +#define PLL_CON0_MUX_CLKCMU_PERIS_GIC_USER 0x600 +#define PLL_CON1_MUX_CLKCMU_PERIS_GIC_USER 0x604 +#define PLL_CON0_MUX_CLKCMU_PERIS_NOC_USER 0x610 +#define PLL_CON1_MUX_CLKCMU_PERIS_NOC_USER 0x614 +#define CLK_CON_MUX_MUX_CLK_PERIS_GIC 0x1000 +#define CLK_CON_DIV_CLKCMU_OTP 0x1800 +#define CLK_CON_DIV_DIV_CLK_PERIS_DDD_CTRL 0x1804 +#define CLK_CON_GAT_CLK_BLK_PERIS_UID_BUSIF_DDD_PERIS_IPCLKPORT_ATCLK 0x2000 +#define CLK_CON_GAT_CLK_BLK_PERIS_UID_BUSIF_DDD_PERIS_IPCLKPORT_PCLK 0x2004 +#define CLK_CON_GAT_CLK_BLK_PERIS_UID_DDD_PERIS_IPCLKPORT_CK_IN 0x2008 +#define CLK_CON_GAT_CLK_BLK_PERIS_UID_D_TZPC_PERIS_IPCLKPORT_PCLK 0x200c +#define CLK_CON_GAT_CLK_BLK_PERIS_UID_GIC_IPCLKPORT_GICCLK 0x2010 +#define CLK_CON_GAT_CLK_BLK_PERIS_UID_LH_AST_MI_LD_ICC_CPUGIC_CLUSTER0_IPCLKPORT_I_CLK 0x2014 +#define CLK_CON_GAT_CLK_BLK_PERIS_UID_LH_AST_SI_LD_IRI_GICCPU_CLUSTER0_IPCLKPORT_I_CLK 0x2018 +#define CLK_CON_GAT_CLK_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK 0x201c +#define CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK 0x2020 +#define CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK 0x2024 +#define CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK 0x2028 +#define CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK 0x202c +#define CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK 0x2030 +#define CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_FREE_OSCCLK_IPCLKPORT_CLK 0x2038 +#define CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK 0x203c +#define CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_NOCP_IPCLKPORT_CLK 0x2040 +#define CLK_CON_GAT_CLK_BLK_PERIS_UID_SLH_AXI_MI_P_PERISGIC_IPCLKPORT_I_CLK 0x2044 +#define CLK_CON_GAT_CLK_BLK_PERIS_UID_SLH_AXI_MI_P_PERIS_IPCLKPORT_I_CLK 0x2048 +#define CLK_CON_GAT_CLK_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK 0x204c +#define CLK_CON_GAT_CLK_BLK_PERIS_UID_TMU_SUB_IPCLKPORT_PCLK 0x2050 +#define CLK_CON_GAT_CLK_BLK_PERIS_UID_TMU_TOP_IPCLKPORT_PCLK 0x2054 +#define CLK_CON_GAT_CLK_BLK_PERIS_UID_WDT0_IPCLKPORT_PCLK 0x2058 +#define CLK_CON_GAT_CLK_BLK_PERIS_UID_WDT1_IPCLKPORT_PCLK 0x205c +#define CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_DDD_CTRL_IPCLKPORT_CLK 0x2060 +#define CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_FREE_OSCCLK_IPCLKPORT_CLK 0x2064 +#define CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_GIC_IPCLKPORT_CLK 0x2068 +#define CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_NOCP_IPCLKPORT_CLK 0x206c + +static const unsigned long peris_clk_regs[] __initconst = { + PLL_CON0_MUX_CLKCMU_PERIS_GIC_USER, + PLL_CON1_MUX_CLKCMU_PERIS_GIC_USER, + PLL_CON0_MUX_CLKCMU_PERIS_NOC_USER, + PLL_CON1_MUX_CLKCMU_PERIS_NOC_USER, + CLK_CON_MUX_MUX_CLK_PERIS_GIC, + CLK_CON_DIV_CLKCMU_OTP, + CLK_CON_DIV_DIV_CLK_PERIS_DDD_CTRL, + CLK_CON_GAT_CLK_BLK_PERIS_UID_BUSIF_DDD_PERIS_IPCLKPORT_ATCLK, + CLK_CON_GAT_CLK_BLK_PERIS_UID_BUSIF_DDD_PERIS_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIS_UID_DDD_PERIS_IPCLKPORT_CK_IN, + CLK_CON_GAT_CLK_BLK_PERIS_UID_D_TZPC_PERIS_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIS_UID_GIC_IPCLKPORT_GICCLK, + CLK_CON_GAT_CLK_BLK_PERIS_UID_LH_AST_MI_LD_ICC_CPUGIC_CLUSTER0_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_PERIS_UID_LH_AST_SI_LD_IRI_GICCPU_CLUSTER0_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK, + CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK, + CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_FREE_OSCCLK_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_NOCP_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_PERIS_UID_SLH_AXI_MI_P_PERISGIC_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_PERIS_UID_SLH_AXI_MI_P_PERIS_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIS_UID_TMU_SUB_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIS_UID_TMU_TOP_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIS_UID_WDT0_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIS_UID_WDT1_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_DDD_CTRL_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_FREE_OSCCLK_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_GIC_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_SR_CLK_PERIS_NOCP_IPCLKPORT_CLK, +}; + +PNAME(mout_peris_gic_user_p) = { "dout_tcxo_div3", + "dout_cmu_peris_gic" }; +PNAME(mout_peris_noc_user_p) = { "dout_tcxo_div3", + "dout_cmu_peris_noc" }; +PNAME(mout_peris_gic_p) = { "mout_peris_gic_user", "dout_tcxo_div3" }; + +static const struct samsung_mux_clock peris_mux_clks[] __initconst = { + MUX(CLK_MOUT_PERIS_GIC_USER, "mout_peris_gic_user", + mout_peris_gic_user_p, PLL_CON0_MUX_CLKCMU_PERIS_GIC_USER, 4, 1), + MUX(CLK_MOUT_PERIS_NOC_USER, "mout_peris_noc_user", + mout_peris_noc_user_p, PLL_CON0_MUX_CLKCMU_PERIS_NOC_USER, 4, 1), + MUX(CLK_MOUT_PERIS_GIC, "mout_peris_gic", mout_peris_gic_p, + CLK_CON_MUX_MUX_CLK_PERIS_GIC, 0, 0), +}; + +static const struct samsung_fixed_factor_clock peris_fixed_factor_clks[] __initconst = { + FFACTOR(CLK_DOUT_PERIS_OTP, "dout_peris_otp", + "dout_tcxo_div3", 1, 8, 0), + FFACTOR(CLK_DOUT_PERIS_DDD_CTRL, "dout_peris_ddd_ctrl", + "mout_peris_gic", 1, 4, 0), +}; + +static const struct samsung_cmu_info peris_cmu_info __initconst = { + .mux_clks = peris_mux_clks, + .nr_mux_clks = ARRAY_SIZE(peris_mux_clks), + .fixed_factor_clks = peris_fixed_factor_clks, + .nr_fixed_factor_clks = ARRAY_SIZE(peris_fixed_factor_clks), + .nr_clk_ids = CLKS_NR_PERIS, + .clk_regs = peris_clk_regs, + .nr_clk_regs = ARRAY_SIZE(peris_clk_regs), + .clk_name = "noc", +}; + +static void __init exynos2200_cmu_peris_init(struct device_node *np) +{ + exynos_arm64_register_cmu(NULL, np, &peris_cmu_info); +} + +/* Register CMU_PERIS early, as it's a dependency for GIC and MCT */ +CLK_OF_DECLARE(exynos2200_cmu_peris, "samsung,exynos2200-cmu-peris", + exynos2200_cmu_peris_init); + +/* ---- CMU_CMGP ----------------------------------------------------------- */ + +/* Register Offset definitions for CMU_CMGP (0x14e00000) */ +#define PLL_CON0_MUX_CLKALIVE_CMGP_NOC_USER 0x610 +#define PLL_CON1_MUX_CLKALIVE_CMGP_NOC_USER 0x614 +#define PLL_CON0_MUX_CLKALIVE_CMGP_PERI_USER 0x620 +#define PLL_CON1_MUX_CLKALIVE_CMGP_PERI_USER 0x624 +#define CLK_CON_MUX_MUX_CLK_CMGP_I2C 0x1000 +#define CLK_CON_MUX_MUX_CLK_CMGP_SPI_I2C0 0x1008 +#define CLK_CON_MUX_MUX_CLK_CMGP_SPI_I2C1 0x100c +#define CLK_CON_MUX_MUX_CLK_CMGP_SPI_MS_CTRL 0x1010 +#define CLK_CON_MUX_MUX_CLK_CMGP_USI0 0x1014 +#define CLK_CON_MUX_MUX_CLK_CMGP_USI1 0x1018 +#define CLK_CON_MUX_MUX_CLK_CMGP_USI2 0x101c +#define CLK_CON_MUX_MUX_CLK_CMGP_USI3 0x1020 +#define CLK_CON_MUX_MUX_CLK_CMGP_USI4 0x1024 +#define CLK_CON_MUX_MUX_CLK_CMGP_USI5 0x1028 +#define CLK_CON_MUX_MUX_CLK_CMGP_USI6 0x102c +#define CLK_CON_DIV_DIV_CLK_CMGP_I2C 0x1800 +#define CLK_CON_DIV_DIV_CLK_CMGP_SPI_I2C0 0x1808 +#define CLK_CON_DIV_DIV_CLK_CMGP_SPI_I2C1 0x180c +#define CLK_CON_DIV_DIV_CLK_CMGP_SPI_MS_CTRL 0x1810 +#define CLK_CON_DIV_DIV_CLK_CMGP_USI0 0x1814 +#define CLK_CON_DIV_DIV_CLK_CMGP_USI1 0x1818 +#define CLK_CON_DIV_DIV_CLK_CMGP_USI2 0x181c +#define CLK_CON_DIV_DIV_CLK_CMGP_USI3 0x1820 +#define CLK_CON_DIV_DIV_CLK_CMGP_USI4 0x1824 +#define CLK_CON_DIV_DIV_CLK_CMGP_USI5 0x1828 +#define CLK_CON_DIV_DIV_CLK_CMGP_USI6 0x182c +#define CLK_CON_GAT_CLK_BLK_CMGP_UID_APBIF_GPIO_CMGP_IPCLKPORT_PCLK 0x2000 +#define CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK 0x2004 +#define CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_I2C_IPCLKPORT_IPCLK 0x2008 +#define CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_I2C_IPCLKPORT_PCLK 0x200c +#define CLK_CON_GAT_CLK_BLK_CMGP_UID_D_TZPC_CMGP_IPCLKPORT_PCLK 0x2010 +#define CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_IPCLK 0x2014 +#define CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_PCLK 0x2018 +#define CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_IPCLK 0x201c +#define CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_PCLK 0x2020 +#define CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP4_IPCLKPORT_IPCLK 0x2024 +#define CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP4_IPCLKPORT_PCLK 0x2028 +#define CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP5_IPCLKPORT_IPCLK 0x202c +#define CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP5_IPCLKPORT_PCLK 0x2030 +#define CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP6_IPCLKPORT_IPCLK 0x2034 +#define CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP6_IPCLKPORT_PCLK 0x2038 +#define CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_NOC_IPCLKPORT_CLK 0x2040 +#define CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_FREE_OSCCLK_IPCLKPORT_CLK 0x2044 +#define CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_I2C_IPCLKPORT_CLK 0x2048 +#define CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_NOC_IPCLKPORT_CLK 0x2050 +#define CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_SPI_I2C0_IPCLKPORT_CLK 0x2054 +#define CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_SPI_I2C1_IPCLKPORT_CLK 0x2058 +#define CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI0_IPCLKPORT_CLK 0x205c +#define CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI1_IPCLKPORT_CLK 0x2060 +#define CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI2_IPCLKPORT_CLK 0x2064 +#define CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI3_IPCLKPORT_CLK 0x2068 +#define CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI4_IPCLKPORT_CLK 0x206c +#define CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI5_IPCLKPORT_CLK 0x2070 +#define CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI6_IPCLKPORT_CLK 0x2074 +#define CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_SPI_MS_CTRL_IPCLKPORT_CLK 0x2078 +#define CLK_CON_GAT_CLK_BLK_CMGP_UID_SLH_AXI_MI_LP_CMGP_IPCLKPORT_I_CLK 0x207c +#define CLK_CON_GAT_CLK_BLK_CMGP_UID_SLH_AXI_SI_LP_CMGPUFD_IPCLKPORT_I_CLK 0x2080 +#define CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_I2C_CMGP0_IPCLKPORT_IPCLK 0x2084 +#define CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_I2C_CMGP0_IPCLKPORT_PCLK 0x2088 +#define CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_I2C_CMGP1_IPCLKPORT_IPCLK 0x208c +#define CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_I2C_CMGP1_IPCLKPORT_PCLK 0x2090 +#define CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_MULTI_SLV_Q_CTRL_CMGP_IPCLKPORT_CLK 0x2094 +#define CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2APM_IPCLKPORT_PCLK 0x2098 +#define CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2CHUB_IPCLKPORT_PCLK 0x209c +#define CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK 0x20a0 +#define CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK 0x20a4 +#define CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK 0x20a8 +#define CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK 0x20ac +#define CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_IPCLK 0x20b0 +#define CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_PCLK 0x20b4 +#define CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_IPCLK 0x20b8 +#define CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_PCLK 0x20bc +#define CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_IPCLK 0x20c0 +#define CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_PCLK 0x20c4 +#define CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_IPCLK 0x20c8 +#define CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_PCLK 0x20cc +#define CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP4_IPCLKPORT_IPCLK 0x20d0 +#define CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP4_IPCLKPORT_PCLK 0x20d4 +#define CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP5_IPCLKPORT_IPCLK 0x20d8 +#define CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP5_IPCLKPORT_PCLK 0x20dc +#define CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP6_IPCLKPORT_IPCLK 0x20e0 +#define CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP6_IPCLKPORT_PCLK 0x20e4 + +static const unsigned long cmgp_clk_regs[] __initconst = { + PLL_CON0_MUX_CLKALIVE_CMGP_NOC_USER, + PLL_CON1_MUX_CLKALIVE_CMGP_NOC_USER, + PLL_CON0_MUX_CLKALIVE_CMGP_PERI_USER, + PLL_CON1_MUX_CLKALIVE_CMGP_PERI_USER, + CLK_CON_MUX_MUX_CLK_CMGP_I2C, + CLK_CON_MUX_MUX_CLK_CMGP_SPI_I2C0, + CLK_CON_MUX_MUX_CLK_CMGP_SPI_I2C1, + CLK_CON_MUX_MUX_CLK_CMGP_SPI_MS_CTRL, + CLK_CON_MUX_MUX_CLK_CMGP_USI0, + CLK_CON_MUX_MUX_CLK_CMGP_USI1, + CLK_CON_MUX_MUX_CLK_CMGP_USI2, + CLK_CON_MUX_MUX_CLK_CMGP_USI3, + CLK_CON_MUX_MUX_CLK_CMGP_USI4, + CLK_CON_MUX_MUX_CLK_CMGP_USI5, + CLK_CON_MUX_MUX_CLK_CMGP_USI6, + CLK_CON_DIV_DIV_CLK_CMGP_I2C, + CLK_CON_DIV_DIV_CLK_CMGP_SPI_I2C0, + CLK_CON_DIV_DIV_CLK_CMGP_SPI_I2C1, + CLK_CON_DIV_DIV_CLK_CMGP_SPI_MS_CTRL, + CLK_CON_DIV_DIV_CLK_CMGP_USI0, + CLK_CON_DIV_DIV_CLK_CMGP_USI1, + CLK_CON_DIV_DIV_CLK_CMGP_USI2, + CLK_CON_DIV_DIV_CLK_CMGP_USI3, + CLK_CON_DIV_DIV_CLK_CMGP_USI4, + CLK_CON_DIV_DIV_CLK_CMGP_USI5, + CLK_CON_DIV_DIV_CLK_CMGP_USI6, + CLK_CON_GAT_CLK_BLK_CMGP_UID_APBIF_GPIO_CMGP_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_I2C_IPCLKPORT_IPCLK, + CLK_CON_GAT_CLK_BLK_CMGP_UID_CMGP_I2C_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_CMGP_UID_D_TZPC_CMGP_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_IPCLK, + CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_IPCLK, + CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP4_IPCLKPORT_IPCLK, + CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP4_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP5_IPCLKPORT_IPCLK, + CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP5_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP6_IPCLKPORT_IPCLK, + CLK_CON_GAT_CLK_BLK_CMGP_UID_I2C_CMGP6_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_NOC_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_FREE_OSCCLK_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_I2C_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_NOC_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_SPI_I2C0_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_SPI_I2C1_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI0_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI1_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI2_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI3_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI4_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI5_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_USI6_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_CMGP_UID_RSTNSYNC_SR_CLK_CMGP_SPI_MS_CTRL_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_CMGP_UID_SLH_AXI_MI_LP_CMGP_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_CMGP_UID_SLH_AXI_SI_LP_CMGPUFD_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_I2C_CMGP0_IPCLKPORT_IPCLK, + CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_I2C_CMGP0_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_I2C_CMGP1_IPCLKPORT_IPCLK, + CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_I2C_CMGP1_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_CMGP_UID_SPI_MULTI_SLV_Q_CTRL_CMGP_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2APM_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2CHUB_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2GNSS_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_IPCLK, + CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_IPCLK, + CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_IPCLK, + CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_IPCLK, + CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP4_IPCLKPORT_IPCLK, + CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP4_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP5_IPCLKPORT_IPCLK, + CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP5_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP6_IPCLKPORT_IPCLK, + CLK_CON_GAT_CLK_BLK_CMGP_UID_USI_CMGP6_IPCLKPORT_PCLK, +}; + +PNAME(mout_cmgp_clkalive_noc_user_p) = { "oscclk", "dout_alive_cmgp_noc" }; +PNAME(mout_cmgp_clkalive_peri_user_p) = { "oscclk", "dout_alive_cmgp_peri" }; +PNAME(mout_cmgp_i2c_p) = { "oscclk", + "mout_cmgp_clkalive_peri_user" }; +PNAME(mout_cmgp_spi_i2c0_p) = { "oscclk", + "mout_cmgp_clkalive_peri_user" }; +PNAME(mout_cmgp_spi_i2c1_p) = { "oscclk", + "mout_cmgp_clkalive_peri_user" }; +PNAME(mout_cmgp_spi_ms_ctrl_p) = { "oscclk", + "mout_cmgp_clkalive_peri_user" }; +PNAME(mout_cmgp_usi0_p) = { "oscclk", + "mout_cmgp_clkalive_peri_user" }; +PNAME(mout_cmgp_usi1_p) = { "oscclk", + "mout_cmgp_clkalive_peri_user" }; +PNAME(mout_cmgp_usi2_p) = { "oscclk", + "mout_cmgp_clkalive_peri_user" }; +PNAME(mout_cmgp_usi3_p) = { "oscclk", + "mout_cmgp_clkalive_peri_user" }; +PNAME(mout_cmgp_usi4_p) = { "oscclk", + "mout_cmgp_clkalive_peri_user" }; +PNAME(mout_cmgp_usi5_p) = { "oscclk", + "mout_cmgp_clkalive_peri_user" }; +PNAME(mout_cmgp_usi6_p) = { "oscclk", + "mout_cmgp_clkalive_peri_user" }; + +static const struct samsung_mux_clock cmgp_mux_clks[] __initconst = { + MUX(CLK_MOUT_CMGP_CLKALIVE_NOC_USER, "mout_cmgp_clkalive_noc_user", + mout_cmgp_clkalive_noc_user_p, PLL_CON0_MUX_CLKALIVE_CMGP_NOC_USER, + 4, 1), + MUX(CLK_MOUT_CMGP_CLKALIVE_PERI_USER, "mout_cmgp_clkalive_peri_user", + mout_cmgp_clkalive_peri_user_p, + PLL_CON0_MUX_CLKALIVE_CMGP_PERI_USER, 4, 1), + MUX(CLK_MOUT_CMGP_I2C, "mout_cmgp_i2c", mout_cmgp_i2c_p, + CLK_CON_MUX_MUX_CLK_CMGP_I2C, 0, 1), + MUX(CLK_MOUT_CMGP_SPI_I2C0, "mout_cmgp_spi_i2c0", mout_cmgp_spi_i2c0_p, + CLK_CON_MUX_MUX_CLK_CMGP_SPI_I2C0, 0, 1), + MUX(CLK_MOUT_CMGP_SPI_I2C1, "mout_cmgp_spi_i2c1", mout_cmgp_spi_i2c1_p, + CLK_CON_MUX_MUX_CLK_CMGP_SPI_I2C1, 0, 1), + MUX(CLK_MOUT_CMGP_SPI_MS_CTRL, "mout_cmgp_spi_ms_ctrl", + mout_cmgp_spi_ms_ctrl_p, CLK_CON_MUX_MUX_CLK_CMGP_SPI_MS_CTRL, + 0, 1), + MUX(CLK_MOUT_CMGP_USI0, "mout_cmgp_usi0", mout_cmgp_usi0_p, + CLK_CON_MUX_MUX_CLK_CMGP_USI0, 0, 1), + MUX(CLK_MOUT_CMGP_USI1, "mout_cmgp_usi1", mout_cmgp_usi1_p, + CLK_CON_MUX_MUX_CLK_CMGP_USI1, 0, 1), + MUX(CLK_MOUT_CMGP_USI2, "mout_cmgp_usi2", mout_cmgp_usi2_p, + CLK_CON_MUX_MUX_CLK_CMGP_USI2, 0, 1), + MUX(CLK_MOUT_CMGP_USI3, "mout_cmgp_usi3", mout_cmgp_usi3_p, + CLK_CON_MUX_MUX_CLK_CMGP_USI3, 0, 1), + MUX(CLK_MOUT_CMGP_USI4, "mout_cmgp_usi4", mout_cmgp_usi4_p, + CLK_CON_MUX_MUX_CLK_CMGP_USI4, 0, 1), + MUX(CLK_MOUT_CMGP_USI5, "mout_cmgp_usi5", mout_cmgp_usi5_p, + CLK_CON_MUX_MUX_CLK_CMGP_USI5, 0, 1), + MUX(CLK_MOUT_CMGP_USI6, "mout_cmgp_usi6", mout_cmgp_usi6_p, + CLK_CON_MUX_MUX_CLK_CMGP_USI6, 0, 1), +}; + +static const struct samsung_div_clock cmgp_div_clks[] __initconst = { + DIV(CLK_DOUT_CMGP_I2C, "dout_cmgp_i2c", "mout_cmgp_i2c", + CLK_CON_DIV_DIV_CLK_CMGP_I2C, 0, 4), + DIV(CLK_DOUT_CMGP_SPI_I2C0, "dout_cmgp_spi_i2c0", "mout_cmgp_spi_i2c0", + CLK_CON_DIV_DIV_CLK_CMGP_SPI_I2C0, 0, 4), + DIV(CLK_DOUT_CMGP_SPI_I2C1, "dout_cmgp_spi_i2c1", "mout_cmgp_spi_i2c1", + CLK_CON_DIV_DIV_CLK_CMGP_SPI_I2C1, 0, 4), + DIV(CLK_DOUT_CMGP_SPI_MS_CTRL, "dout_cmgp_spi_ms_ctrl", + "mout_cmgp_spi_ms_ctrl", CLK_CON_DIV_DIV_CLK_CMGP_SPI_MS_CTRL, + 0, 4), + DIV(CLK_DOUT_CMGP_USI0, "dout_cmgp_usi0", "mout_cmgp_usi0", + CLK_CON_DIV_DIV_CLK_CMGP_USI0, 0, 4), + DIV(CLK_DOUT_CMGP_USI1, "dout_cmgp_usi1", "mout_cmgp_usi1", + CLK_CON_DIV_DIV_CLK_CMGP_USI1, 0, 4), + DIV(CLK_DOUT_CMGP_USI2, "dout_cmgp_usi2", "mout_cmgp_usi2", + CLK_CON_DIV_DIV_CLK_CMGP_USI2, 0, 4), + DIV(CLK_DOUT_CMGP_USI3, "dout_cmgp_usi3", "mout_cmgp_usi3", + CLK_CON_DIV_DIV_CLK_CMGP_USI3, 0, 4), + DIV(CLK_DOUT_CMGP_USI4, "dout_cmgp_usi4", "mout_cmgp_usi4", + CLK_CON_DIV_DIV_CLK_CMGP_USI4, 0, 4), + DIV(CLK_DOUT_CMGP_USI5, "dout_cmgp_usi5", "mout_cmgp_usi5", + CLK_CON_DIV_DIV_CLK_CMGP_USI5, 0, 4), + DIV(CLK_DOUT_CMGP_USI6, "dout_cmgp_usi6", "mout_cmgp_usi6", + CLK_CON_DIV_DIV_CLK_CMGP_USI6, 0, 4), +}; + +static const struct samsung_cmu_info cmgp_cmu_info __initconst = { + .mux_clks = cmgp_mux_clks, + .nr_mux_clks = ARRAY_SIZE(cmgp_mux_clks), + .div_clks = cmgp_div_clks, + .nr_div_clks = ARRAY_SIZE(cmgp_div_clks), + .nr_clk_ids = CLKS_NR_CMGP, + .clk_regs = cmgp_clk_regs, + .nr_clk_regs = ARRAY_SIZE(cmgp_clk_regs), + .clk_name = "noc", +}; + +/* ---- CMU_HSI0 ----------------------------------------------------------- */ + +/* Register Offset definitions for CMU_HSI0 (0x10a00000) */ +#define PLL_CON0_MUX_CLKAUD_HSI0_NOC_USER 0x600 +#define PLL_CON1_MUX_CLKAUD_HSI0_NOC_USER 0x604 +#define PLL_CON0_MUX_CLKCMU_HSI0_DPGTC_USER 0x610 +#define PLL_CON1_MUX_CLKCMU_HSI0_DPGTC_USER 0x614 +#define PLL_CON0_MUX_CLKCMU_HSI0_DPOSC_USER 0x620 +#define PLL_CON1_MUX_CLKCMU_HSI0_DPOSC_USER 0x624 +#define PLL_CON0_MUX_CLKCMU_HSI0_NOC_USER 0x630 +#define PLL_CON1_MUX_CLKCMU_HSI0_NOC_USER 0x634 +#define PLL_CON0_MUX_CLKCMU_HSI0_USB32DRD_USER 0x640 +#define PLL_CON1_MUX_CLKCMU_HSI0_USB32DRD_USER 0x644 +#define CLK_CON_MUX_MUX_CLK_HSI0_NOC 0x1000 +#define CLK_CON_MUX_MUX_CLK_HSI0_RTCCLK 0x1004 +#define CLK_CON_MUX_MUX_CLK_HSI0_USB32DRD 0x1008 +#define CLK_CON_DIV_DIV_CLK_HSI0_EUSB 0x1800 +#define CLK_CON_GAT_CLK_BLK_HSI0_UID_AS_APB_EUSBPHY_HSI0_IPCLKPORT_PCLKM 0x2000 +#define CLK_CON_GAT_CLK_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK 0x2004 +#define CLK_CON_GAT_CLK_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_OSC_CLK 0x2008 +#define CLK_CON_GAT_CLK_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK 0x200c +#define CLK_CON_GAT_CLK_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK 0x2010 +#define CLK_CON_GAT_CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK 0x2014 +#define CLK_CON_GAT_CLK_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_ACLK 0x2018 +#define CLK_CON_GAT_CLK_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_PCLK 0x201c +#define CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_EUSB_IPCLKPORT_CLK 0x2020 +#define CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_NOC_IPCLKPORT_CLK 0x2024 +#define CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_ACEL_SI_D_HSI0_IPCLKPORT_I_CLK 0x2028 +#define CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AST_SI_G_PPMU_HSI0_IPCLKPORT_I_CLK 0x202c +#define CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_LD_AUDHSI0_IPCLKPORT_I_CLK 0x2030 +#define CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_P_HSI0_IPCLKPORT_I_CLK 0x2034 +#define CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_SI_LD_HSI0AUD_IPCLKPORT_I_CLK 0x2038 +#define CLK_CON_GAT_CLK_BLK_HSI0_UID_BLK_HSI0_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK 0x203c +#define CLK_CON_GAT_CLK_BLK_HSI0_UID_SYSMMU_D_HSI0_IPCLKPORT_CLK_S2 0x2040 +#define CLK_CON_GAT_CLK_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK 0x2044 +#define CLK_CON_GAT_CLK_BLK_HSI0_UID_URAM_IPCLKPORT_ACLK 0x2048 +#define CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_EUSB_APB_CLK 0x204c +#define CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_EUSB_CTRL_PCLK 0x2050 +#define CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USB32DRD_REF_CLK_40 0x2054 +#define CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBDPPHY_CTRL_PCLK 0x2058 +#define CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBDPPHY_TCA_APB_CLK 0x205c +#define CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBLINK_ACLK 0x2060 +#define CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBSUBCTL_APB_PCLK 0x2064 +#define CLK_CON_GAT_CLK_BLK_HSI0_UID_VGEN_LITE_HSI0_IPCLKPORT_CLK 0x2068 +#define CLK_CON_GAT_CLK_BLK_HSI0_UID_XIU_D_HSI0_IPCLKPORT_ACLK 0x206c +#define CLK_CON_GAT_CLK_BLK_HSI0_UID_XIU_P0_HSI0_IPCLKPORT_ACLK 0x2070 +#define CLK_CON_GAT_CLK_BLK_HSI0_UID_OTP_DESERIAL_DPLINK_HDCP_IPCLKPORT_I_CLK 0x2074 +#define CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_SR_CLK_HSI0_FREE_OSCCLK_IPCLKPORT_CLK 0x2078 +#define CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_SR_CLK_HSI0_NOC_IPCLKPORT_CLK 0x207c +#define CLK_CON_GAT_CLK_BLK_HSI0_UID_SPC_HSI0_IPCLKPORT_PCLK 0x2080 + +static const unsigned long hsi0_clk_regs[] __initconst = { + PLL_CON0_MUX_CLKAUD_HSI0_NOC_USER, + PLL_CON1_MUX_CLKAUD_HSI0_NOC_USER, + PLL_CON0_MUX_CLKCMU_HSI0_DPGTC_USER, + PLL_CON1_MUX_CLKCMU_HSI0_DPGTC_USER, + PLL_CON0_MUX_CLKCMU_HSI0_DPOSC_USER, + PLL_CON1_MUX_CLKCMU_HSI0_DPOSC_USER, + PLL_CON0_MUX_CLKCMU_HSI0_NOC_USER, + PLL_CON1_MUX_CLKCMU_HSI0_NOC_USER, + PLL_CON0_MUX_CLKCMU_HSI0_USB32DRD_USER, + PLL_CON1_MUX_CLKCMU_HSI0_USB32DRD_USER, + CLK_CON_MUX_MUX_CLK_HSI0_NOC, + CLK_CON_MUX_MUX_CLK_HSI0_RTCCLK, + CLK_CON_MUX_MUX_CLK_HSI0_USB32DRD, + CLK_CON_DIV_DIV_CLK_HSI0_EUSB, + CLK_CON_GAT_CLK_BLK_HSI0_UID_AS_APB_EUSBPHY_HSI0_IPCLKPORT_PCLKM, + CLK_CON_GAT_CLK_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK, + CLK_CON_GAT_CLK_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_OSC_CLK, + CLK_CON_GAT_CLK_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK, + CLK_CON_GAT_CLK_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_ACLK, + CLK_CON_GAT_CLK_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_EUSB_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_NOC_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_ACEL_SI_D_HSI0_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AST_SI_G_PPMU_HSI0_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_LD_AUDHSI0_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_P_HSI0_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_SI_LD_HSI0AUD_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_HSI0_UID_BLK_HSI0_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_HSI0_UID_SYSMMU_D_HSI0_IPCLKPORT_CLK_S2, + CLK_CON_GAT_CLK_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_HSI0_UID_URAM_IPCLKPORT_ACLK, + CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_EUSB_APB_CLK, + CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_EUSB_CTRL_PCLK, + CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USB32DRD_REF_CLK_40, + CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBDPPHY_CTRL_PCLK, + CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBDPPHY_TCA_APB_CLK, + CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBLINK_ACLK, + CLK_CON_GAT_CLK_BLK_HSI0_UID_USB32DRD_IPCLKPORT_I_USBSUBCTL_APB_PCLK, + CLK_CON_GAT_CLK_BLK_HSI0_UID_VGEN_LITE_HSI0_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_HSI0_UID_XIU_D_HSI0_IPCLKPORT_ACLK, + CLK_CON_GAT_CLK_BLK_HSI0_UID_XIU_P0_HSI0_IPCLKPORT_ACLK, + CLK_CON_GAT_CLK_BLK_HSI0_UID_OTP_DESERIAL_DPLINK_HDCP_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_SR_CLK_HSI0_FREE_OSCCLK_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_SR_CLK_HSI0_NOC_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_HSI0_UID_SPC_HSI0_IPCLKPORT_PCLK, +}; + +PNAME(mout_clkcmu_hsi0_dpgtc_user_p) = { "oscclk", "dout_cmu_hsi0_dpgtc" }; +PNAME(mout_clkcmu_hsi0_dposc_user_p) = { "oscclk", "dout_cmu_hsi0_dposc" }; +PNAME(mout_clkcmu_hsi0_noc_user_p) = { "oscclk", "dout_cmu_hsi0_noc" }; +PNAME(mout_clkcmu_hsi0_usb32drd_user_p) = { "oscclk", + "dout_cmu_hsi0_usb32drd" }; +PNAME(mout_mux_clk_hsi0_noc_p) = { "mout_clkcmu_hsi0_noc_user" }; +PNAME(mout_mux_clk_hsi0_rtcclk_p) = { "rtcclk", "oscclk" }; +PNAME(mout_mux_clk_hsi0_usb32drd_p) = { "dout_tcxo_div4", + "mout_clkcmu_hsi0_usb32drd_user" }; + +static const struct samsung_mux_clock hsi0_mux_clks[] __initconst = { + MUX(CLK_MOUT_CLKCMU_HSI0_DPGTC_USER, "mout_clkcmu_hsi0_dpgtc_user", + mout_clkcmu_hsi0_dpgtc_user_p, PLL_CON0_MUX_CLKCMU_HSI0_DPGTC_USER, + 4, 1), + MUX(CLK_MOUT_CLKCMU_HSI0_DPOSC_USER, "mout_clkcmu_hsi0_dposc_user", + mout_clkcmu_hsi0_dposc_user_p, PLL_CON0_MUX_CLKCMU_HSI0_DPOSC_USER, + 4, 1), + MUX(CLK_MOUT_CLKCMU_HSI0_NOC_USER, "mout_clkcmu_hsi0_noc_user", + mout_clkcmu_hsi0_noc_user_p, PLL_CON0_MUX_CLKCMU_HSI0_NOC_USER, + 4, 1), + MUX(CLK_MOUT_CLKCMU_HSI0_USB32DRD_USER, + "mout_clkcmu_hsi0_usb32drd_user", mout_clkcmu_hsi0_usb32drd_user_p, + PLL_CON0_MUX_CLKCMU_HSI0_USB32DRD_USER, 4, 1), + MUX(CLK_MOUT_HSI0_NOC, "mout_hsi0_noc", mout_mux_clk_hsi0_noc_p, + CLK_CON_MUX_MUX_CLK_HSI0_NOC, 0, 1), + MUX(CLK_MOUT_HSI0_RTCCLK, "mout_hsi0_rtcclk", + mout_mux_clk_hsi0_rtcclk_p, CLK_CON_MUX_MUX_CLK_HSI0_RTCCLK, 0, 1), + MUX(CLK_MOUT_HSI0_USB32DRD, "mout_hsi0_usb32drd", + mout_mux_clk_hsi0_usb32drd_p, CLK_CON_MUX_MUX_CLK_HSI0_USB32DRD, + 0, 1), +}; + +static const struct samsung_div_clock hsi0_div_clks[] __initconst = { + DIV(CLK_DOUT_DIV_CLK_HSI0_EUSB, "dout_div_clk_hsi0_eusb", + "mout_hsi0_noc", CLK_CON_DIV_DIV_CLK_HSI0_EUSB, 0, 2), +}; + +static const struct samsung_cmu_info hsi0_cmu_info __initconst = { + .mux_clks = hsi0_mux_clks, + .nr_mux_clks = ARRAY_SIZE(hsi0_mux_clks), + .div_clks = hsi0_div_clks, + .nr_div_clks = ARRAY_SIZE(hsi0_div_clks), + .nr_clk_ids = CLKS_NR_HSI0, + .clk_regs = hsi0_clk_regs, + .nr_clk_regs = ARRAY_SIZE(hsi0_clk_regs), + .clk_name = "noc", +}; + +/* ---- CMU_PERIC0 --------------------------------------------------------- */ + +/* Register Offset definitions for CMU_PERIC0 (0x10400000) */ +#define PLL_CON0_MUX_CLKCMU_PERIC0_IP0_USER 0x600 +#define PLL_CON1_MUX_CLKCMU_PERIC0_IP0_USER 0x604 +#define PLL_CON0_MUX_CLKCMU_PERIC0_IP1_USER 0x610 +#define PLL_CON1_MUX_CLKCMU_PERIC0_IP1_USER 0x614 +#define PLL_CON0_MUX_CLKCMU_PERIC0_NOC_USER 0x620 +#define PLL_CON1_MUX_CLKCMU_PERIC0_NOC_USER 0x624 +#define CLK_CON_MUX_MUX_CLK_PERIC0_I2C 0x1000 +#define CLK_CON_MUX_MUX_CLK_PERIC0_USI04 0x1010 +#define CLK_CON_DIV_DIV_CLK_PERIC0_I2C 0x1800 +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI04 0x1810 +#define CLK_CON_GAT_CLK_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK 0x2000 +#define CLK_CON_GAT_CLK_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK 0x2004 +#define CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK 0x2008 +#define CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_FREE_OSCCLK_IPCLKPORT_CLK 0x200c +#define CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I2C_IPCLKPORT_CLK 0x2010 +#define CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_NOCP_IPCLKPORT_CLK 0x2014 +#define CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_SR_CLK_PERIC0_USI04_IPCLKPORT_CLK 0x2018 +#define CLK_CON_GAT_CLK_BLK_PERIC0_UID_SLH_AXI_MI_P_PERIC0_IPCLKPORT_I_CLK 0x201c +#define CLK_CON_GAT_CLK_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK 0x2020 +#define CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_IPCLK 0x2024 +#define CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_PCLK 0x2028 +#define CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_IPCLK 0x202c +#define CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_PCLK 0x2030 +#define CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C00_IPCLKPORT_I_PCLK 0x2034 +#define CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C00_IPCLKPORT_I_SCLK 0x2038 +#define CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C01_IPCLKPORT_I_PCLK 0x203c +#define CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C01_IPCLKPORT_I_SCLK 0x2040 +#define CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C02_IPCLKPORT_I_PCLK 0x2044 +#define CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C02_IPCLKPORT_I_SCLK 0x2048 +#define CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_SR_CLK_PERIC0_I2C_IPCLKPORT_CLK 0x204c +#define CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_SR_CLK_PERIC0_NOCP_IPCLKPORT_CLK 0x2050 + +static const unsigned long peric0_clk_regs[] __initconst = { + PLL_CON0_MUX_CLKCMU_PERIC0_IP0_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_IP0_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_IP1_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_IP1_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_NOC_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_NOC_USER, + CLK_CON_MUX_MUX_CLK_PERIC0_I2C, + CLK_CON_MUX_MUX_CLK_PERIC0_USI04, + CLK_CON_DIV_DIV_CLK_PERIC0_I2C, + CLK_CON_DIV_DIV_CLK_PERIC0_USI04, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_FREE_OSCCLK_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I2C_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_NOCP_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_SR_CLK_PERIC0_USI04_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_SLH_AXI_MI_P_PERIC0_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_IPCLK, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_IPCLK, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C00_IPCLKPORT_I_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C00_IPCLKPORT_I_SCLK, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C01_IPCLKPORT_I_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C01_IPCLKPORT_I_SCLK, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C02_IPCLKPORT_I_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C02_IPCLKPORT_I_SCLK, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_SR_CLK_PERIC0_I2C_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_SR_CLK_PERIC0_NOCP_IPCLKPORT_CLK, +}; + +PNAME(mout_peric0_ip0_user_p) = { "oscclk", "dout_cmu_peric0_ip0" }; +PNAME(mout_peric0_ip1_user_p) = { "oscclk", "dout_cmu_peric0_ip1" }; +PNAME(mout_peric0_noc_user_p) = { "oscclk", "dout_cmu_peric0_noc" }; +PNAME(mout_peric0_i2c_p) = { "oscclk", "mout_peric0_ip0_user", + "mout_peric0_ip0_user", "oscclk" }; +PNAME(mout_peric0_usi04_p) = { "oscclk", "mout_peric0_ip0_user", + "mout_peric0_ip0_user", "oscclk" }; + +static const struct samsung_mux_clock peric0_mux_clks[] __initconst = { + MUX(CLK_MOUT_PERIC0_IP0_USER, "mout_peric0_ip0_user", + mout_peric0_ip0_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_IP0_USER, 4, 1), + MUX(CLK_MOUT_PERIC0_IP1_USER, "mout_peric0_ip1_user", + mout_peric0_ip1_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_IP1_USER, 4, 1), + MUX(CLK_MOUT_PERIC0_NOC_USER, "mout_peric0_noc_user", + mout_peric0_noc_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_NOC_USER, 4, 1), + MUX(CLK_MOUT_PERIC0_I2C, "mout_peric0_i2c", mout_peric0_i2c_p, + CLK_CON_MUX_MUX_CLK_PERIC0_I2C, 0, 2), + MUX(CLK_MOUT_PERIC0_USI04, "mout_peric0_usi04", mout_peric0_usi04_p, + CLK_CON_MUX_MUX_CLK_PERIC0_USI04, 0, 2), +}; + +static const struct samsung_div_clock peric0_div_clks[] __initconst = { + DIV(CLK_DOUT_PERIC0_I2C, "dout_peric0_i2c", "mout_peric0_i2c", + CLK_CON_DIV_DIV_CLK_PERIC0_I2C, 0, 4), + DIV(CLK_DOUT_PERIC0_USI04, "dout_peric0_usi04", "mout_peric0_usi04", + CLK_CON_DIV_DIV_CLK_PERIC0_USI04, 0, 7), +}; + +static const struct samsung_cmu_info peric0_cmu_info __initconst = { + .mux_clks = peric0_mux_clks, + .nr_mux_clks = ARRAY_SIZE(peric0_mux_clks), + .div_clks = peric0_div_clks, + .nr_div_clks = ARRAY_SIZE(peric0_div_clks), + .nr_clk_ids = CLKS_NR_PERIC0, + .clk_regs = peric0_clk_regs, + .nr_clk_regs = ARRAY_SIZE(peric0_clk_regs), + .clk_name = "noc", +}; + +/* ---- CMU_PERIC1 --------------------------------------------------------- */ + +/* Register Offset definitions for CMU_PERIC1 (0x10700000) */ +#define PLL_CON0_MUX_CLKCMU_PERIC1_IP0_USER 0x600 +#define PLL_CON1_MUX_CLKCMU_PERIC1_IP0_USER 0x604 +#define PLL_CON0_MUX_CLKCMU_PERIC1_IP1_USER 0x610 +#define PLL_CON1_MUX_CLKCMU_PERIC1_IP1_USER 0x614 +#define PLL_CON0_MUX_CLKCMU_PERIC1_NOC_USER 0x620 +#define PLL_CON1_MUX_CLKCMU_PERIC1_NOC_USER 0x624 +#define CLK_CON_MUX_MUX_CLK_PERIC1_I2C 0x1000 +#define CLK_CON_MUX_MUX_CLK_PERIC1_SPI_MS_CTRL 0x1004 +#define CLK_CON_MUX_MUX_CLK_PERIC1_UART_BT 0x1008 +#define CLK_CON_MUX_MUX_CLK_PERIC1_USI07 0x100c +#define CLK_CON_MUX_MUX_CLK_PERIC1_USI07_SPI_I2C 0x1010 +#define CLK_CON_MUX_MUX_CLK_PERIC1_USI08 0x1014 +#define CLK_CON_MUX_MUX_CLK_PERIC1_USI08_SPI_I2C 0x1018 +#define CLK_CON_MUX_MUX_CLK_PERIC1_USI09 0x101c +#define CLK_CON_MUX_MUX_CLK_PERIC1_USI10 0x1020 +#define CLK_CON_DIV_DIV_CLK_PERIC1_I2C 0x1800 +#define CLK_CON_DIV_DIV_CLK_PERIC1_SPI_MS_CTRL 0x1804 +#define CLK_CON_DIV_DIV_CLK_PERIC1_UART_BT 0x1808 +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI07 0x180c +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI07_SPI_I2C 0x1810 +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI08 0x1814 +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI08_SPI_I2C 0x1818 +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI09 0x181c +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI10 0x1820 +#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_BT_UART_IPCLKPORT_IPCLK 0x2000 +#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_BT_UART_IPCLKPORT_PCLK 0x2004 +#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK 0x2008 +#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK 0x200c +#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_I2C_IPCLKPORT_CLK 0x2010 +#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_NOCP_IPCLKPORT_CLK 0x2014 +#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK 0x2028 +#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_FREE_OSCCLK_IPCLKPORT_CLK 0x202c +#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_NOCP_IPCLKPORT_CLK 0x2034 +#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_UART_BT_IPCLKPORT_CLK 0x2038 +#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI07_IPCLKPORT_CLK 0x203c +#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI07_SPI_I2C_IPCLKPORT_CLK 0x2040 +#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI08_IPCLKPORT_CLK 0x2044 +#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI08_SPI_I2C_IPCLKPORT_CLK 0x2048 +#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI09_IPCLKPORT_CLK 0x204c +#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI10_IPCLKPORT_CLK 0x2050 +#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_SPI_MS_CTRL_IPCLKPORT_CLK 0x2054 +#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_SLH_AXI_MI_P_PERIC1_IPCLKPORT_I_CLK 0x205c +#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_SPI_MULTI_SLV_Q_CTRL_PERIC1_IPCLKPORT_CLK 0x2060 +#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK 0x2064 +#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI07_SPI_I2C_IPCLKPORT_IPCLK 0x2068 +#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI07_SPI_I2C_IPCLKPORT_PCLK 0x206c +#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_IPCLK 0x2070 +#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_PCLK 0x2074 +#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI08_SPI_I2C_IPCLKPORT_IPCLK 0x2078 +#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI08_SPI_I2C_IPCLKPORT_PCLK 0x207c +#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_IPCLK 0x2080 +#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_PCLK 0x2084 +#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_IPCLK 0x2088 +#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_PCLK 0x208c +#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_IPCLK 0x2090 +#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_PCLK 0x2094 +#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_IPCLK 0x2098 +#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_PCLK 0x209c +#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_IPCLK 0x20a0 +#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_PCLK 0x20a4 +#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK 0x20a8 + +static const unsigned long peric1_clk_regs[] __initconst = { + PLL_CON0_MUX_CLKCMU_PERIC1_IP0_USER, + PLL_CON1_MUX_CLKCMU_PERIC1_IP0_USER, + PLL_CON0_MUX_CLKCMU_PERIC1_IP1_USER, + PLL_CON1_MUX_CLKCMU_PERIC1_IP1_USER, + PLL_CON0_MUX_CLKCMU_PERIC1_NOC_USER, + PLL_CON1_MUX_CLKCMU_PERIC1_NOC_USER, + CLK_CON_MUX_MUX_CLK_PERIC1_I2C, + CLK_CON_MUX_MUX_CLK_PERIC1_SPI_MS_CTRL, + CLK_CON_MUX_MUX_CLK_PERIC1_UART_BT, + CLK_CON_MUX_MUX_CLK_PERIC1_USI07, + CLK_CON_MUX_MUX_CLK_PERIC1_USI07_SPI_I2C, + CLK_CON_MUX_MUX_CLK_PERIC1_USI08, + CLK_CON_MUX_MUX_CLK_PERIC1_USI08_SPI_I2C, + CLK_CON_MUX_MUX_CLK_PERIC1_USI09, + CLK_CON_MUX_MUX_CLK_PERIC1_USI10, + CLK_CON_DIV_DIV_CLK_PERIC1_I2C, + CLK_CON_DIV_DIV_CLK_PERIC1_SPI_MS_CTRL, + CLK_CON_DIV_DIV_CLK_PERIC1_UART_BT, + CLK_CON_DIV_DIV_CLK_PERIC1_USI07, + CLK_CON_DIV_DIV_CLK_PERIC1_USI07_SPI_I2C, + CLK_CON_DIV_DIV_CLK_PERIC1_USI08, + CLK_CON_DIV_DIV_CLK_PERIC1_USI08_SPI_I2C, + CLK_CON_DIV_DIV_CLK_PERIC1_USI09, + CLK_CON_DIV_DIV_CLK_PERIC1_USI10, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_BT_UART_IPCLKPORT_IPCLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_BT_UART_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_I2C_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_NOCP_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_FREE_OSCCLK_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_NOCP_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_UART_BT_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI07_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI07_SPI_I2C_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI08_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI08_SPI_I2C_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI09_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_USI10_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_SR_CLK_PERIC1_SPI_MS_CTRL_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_SLH_AXI_MI_P_PERIC1_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_SPI_MULTI_SLV_Q_CTRL_PERIC1_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI07_SPI_I2C_IPCLKPORT_IPCLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI07_SPI_I2C_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_IPCLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI08_SPI_I2C_IPCLKPORT_IPCLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI08_SPI_I2C_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_IPCLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_IPCLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_IPCLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_IPCLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_IPCLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK, +}; + +PNAME(mout_peric1_ip0_user_p) = { "oscclk", "dout_cmu_peric1_ip0" }; +PNAME(mout_peric1_ip1_user_p) = { "oscclk", "dout_cmu_peric1_ip1" }; +PNAME(mout_peric1_noc_user_p) = { "oscclk", "dout_cmu_peric1_noc" }; +PNAME(mout_peric1_i2c_p) = { "oscclk", "mout_peric1_ip0_user", + "mout_peric1_ip1_user", "oscclk" }; +PNAME(mout_peric1_spi_ms_ctrl_p) = { "oscclk", "mout_peric1_ip0_user", + "mout_peric1_ip1_user", "oscclk" }; +PNAME(mout_peric1_uart_bt_p) = { "oscclk", "mout_peric1_ip0_user", + "mout_peric1_ip1_user", "oscclk" }; +PNAME(mout_peric1_usi07_p) = { "oscclk", "mout_peric1_ip0_user", + "mout_peric1_ip1_user", "oscclk" }; +PNAME(mout_peric1_usi07_spi_i2c_p) = { "oscclk", "mout_peric1_ip0_user", + "mout_peric1_ip1_user", "oscclk" }; +PNAME(mout_peric1_usi08_p) = { "oscclk", "mout_peric1_ip0_user", + "mout_peric1_ip1_user", "oscclk" }; +PNAME(mout_peric1_usi08_spi_i2c_p) = { "oscclk", "mout_peric1_ip0_user", + "mout_peric1_ip1_user", "oscclk" }; +PNAME(mout_peric1_usi09_p) = { "oscclk", "mout_peric1_ip0_user", + "mout_peric1_ip1_user", "oscclk" }; +PNAME(mout_peric1_usi10_p) = { "oscclk", "mout_peric1_ip0_user", + "mout_peric1_ip1_user", "oscclk" }; + +static const struct samsung_mux_clock peric1_mux_clks[] __initconst = { + MUX(CLK_MOUT_PERIC1_IP0_USER, "mout_peric1_ip0_user", + mout_peric1_ip0_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_IP0_USER, 4, 1), + MUX(CLK_MOUT_PERIC1_IP1_USER, "mout_peric1_ip1_user", + mout_peric1_ip1_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_IP1_USER, 4, 1), + MUX(CLK_MOUT_PERIC1_NOC_USER, "mout_peric1_noc_user", + mout_peric1_noc_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_NOC_USER, 4, 1), + MUX(CLK_MOUT_PERIC1_I2C, "mout_peric1_i2c", mout_peric1_i2c_p, + CLK_CON_MUX_MUX_CLK_PERIC1_I2C, 0, 2), + MUX(CLK_MOUT_PERIC1_SPI_MS_CTRL, "mout_peric1_spi_ms_ctrl", + mout_peric1_spi_ms_ctrl_p, CLK_CON_MUX_MUX_CLK_PERIC1_SPI_MS_CTRL, + 0, 2), + MUX(CLK_MOUT_PERIC1_UART_BT, "mout_peric1_uart_bt", + mout_peric1_uart_bt_p, CLK_CON_MUX_MUX_CLK_PERIC1_UART_BT, 0, 2), + MUX(CLK_MOUT_PERIC1_USI07, "mout_peric1_usi07", mout_peric1_usi07_p, + CLK_CON_MUX_MUX_CLK_PERIC1_USI07, 0, 2), + MUX(CLK_MOUT_PERIC1_USI07_SPI_I2C, "mout_peric1_usi07_spi_i2c", + mout_peric1_usi07_spi_i2c_p, + CLK_CON_MUX_MUX_CLK_PERIC1_USI07_SPI_I2C, 0, 2), + MUX(CLK_MOUT_PERIC1_USI08, "mout_peric1_usi08", mout_peric1_usi08_p, + CLK_CON_MUX_MUX_CLK_PERIC1_USI08, 0, 2), + MUX(CLK_MOUT_PERIC1_USI08_SPI_I2C, "mout_peric1_usi08_spi_i2c", + mout_peric1_usi08_spi_i2c_p, + CLK_CON_MUX_MUX_CLK_PERIC1_USI08_SPI_I2C, 0, 2), + MUX(CLK_MOUT_PERIC1_USI09, "mout_peric1_usi09", mout_peric1_usi09_p, + CLK_CON_MUX_MUX_CLK_PERIC1_USI09, 0, 2), + MUX(CLK_MOUT_PERIC1_USI10, "mout_peric1_usi10", mout_peric1_usi10_p, + CLK_CON_MUX_MUX_CLK_PERIC1_USI10, 0, 2), +}; + +static const struct samsung_div_clock peric1_div_clks[] __initconst = { + DIV(CLK_DOUT_PERIC1_I2C, "dout_peric1_i2c", "mout_peric1_i2c", + CLK_CON_DIV_DIV_CLK_PERIC1_I2C, 0, 4), + DIV(CLK_DOUT_PERIC1_SPI_MS_CTRL, "dout_peric1_spi_ms_ctrl", + "mout_peric1_spi_ms_ctrl", CLK_CON_DIV_DIV_CLK_PERIC1_SPI_MS_CTRL, + 0, 7), + DIV(CLK_DOUT_PERIC1_UART_BT, "dout_peric1_uart_bt", + "mout_peric1_uart_bt", CLK_CON_DIV_DIV_CLK_PERIC1_UART_BT, 0, 4), + DIV(CLK_DOUT_PERIC1_USI07, "dout_peric1_usi07", "mout_peric1_usi07", + CLK_CON_DIV_DIV_CLK_PERIC1_USI07, 0, 7), + DIV(CLK_DOUT_PERIC1_USI07_SPI_I2C, "dout_peric1_usi07_spi_i2c", + "mout_peric1_usi07_spi_i2c", + CLK_CON_DIV_DIV_CLK_PERIC1_USI07_SPI_I2C, 0, 4), + DIV(CLK_DOUT_PERIC1_USI08, "dout_peric1_usi08", "mout_peric1_usi08", + CLK_CON_DIV_DIV_CLK_PERIC1_USI08, 0, 7), + DIV(CLK_DOUT_PERIC1_USI08_SPI_I2C, "dout_peric1_usi08_spi_i2c", + "mout_peric1_usi08_spi_i2c", + CLK_CON_DIV_DIV_CLK_PERIC1_USI08_SPI_I2C, 0, 4), + DIV(CLK_DOUT_PERIC1_USI09, "dout_peric1_usi09", "mout_peric1_usi09", + CLK_CON_DIV_DIV_CLK_PERIC1_USI09, 0, 7), + DIV(CLK_DOUT_PERIC1_USI10, "dout_peric1_usi10", "mout_peric1_usi10", + CLK_CON_DIV_DIV_CLK_PERIC1_USI10, 0, 7), +}; + +static const struct samsung_cmu_info peric1_cmu_info __initconst = { + .mux_clks = peric1_mux_clks, + .nr_mux_clks = ARRAY_SIZE(peric1_mux_clks), + .div_clks = peric1_div_clks, + .nr_div_clks = ARRAY_SIZE(peric1_div_clks), + .nr_clk_ids = CLKS_NR_PERIC1, + .clk_regs = peric1_clk_regs, + .nr_clk_regs = ARRAY_SIZE(peric1_clk_regs), + .clk_name = "noc", +}; + +/* ---- CMU_PERIC2 --------------------------------------------------------- */ + +/* Register Offset definitions for CMU_PERIC2 (0x11c00000) */ +#define PLL_CON0_MUX_CLKCMU_PERIC2_IP0_USER 0x600 +#define PLL_CON1_MUX_CLKCMU_PERIC2_IP0_USER 0x604 +#define PLL_CON0_MUX_CLKCMU_PERIC2_IP1_USER 0x610 +#define PLL_CON1_MUX_CLKCMU_PERIC2_IP1_USER 0x614 +#define PLL_CON0_MUX_CLKCMU_PERIC2_NOC_USER 0x620 +#define PLL_CON1_MUX_CLKCMU_PERIC2_NOC_USER 0x624 +#define CLK_CON_MUX_MUX_CLK_PERIC2_I2C 0x1000 +#define CLK_CON_MUX_MUX_CLK_PERIC2_SPI_MS_CTRL 0x1004 +#define CLK_CON_MUX_MUX_CLK_PERIC2_UART_DBG 0x1008 +#define CLK_CON_MUX_MUX_CLK_PERIC2_USI00 0x100c +#define CLK_CON_MUX_MUX_CLK_PERIC2_USI00_SPI_I2C 0x1010 +#define CLK_CON_MUX_MUX_CLK_PERIC2_USI01 0x1014 +#define CLK_CON_MUX_MUX_CLK_PERIC2_USI01_SPI_I2C 0x1018 +#define CLK_CON_MUX_MUX_CLK_PERIC2_USI02 0x101c +#define CLK_CON_MUX_MUX_CLK_PERIC2_USI03 0x1020 +#define CLK_CON_MUX_MUX_CLK_PERIC2_USI05 0x1024 +#define CLK_CON_MUX_MUX_CLK_PERIC2_USI06 0x1028 +#define CLK_CON_MUX_MUX_CLK_PERIC2_USI11 0x102c +#define CLK_CON_DIV_DIV_CLK_PERIC2_I2C 0x1800 +#define CLK_CON_DIV_DIV_CLK_PERIC2_SPI_MS_CTRL 0x1804 +#define CLK_CON_DIV_DIV_CLK_PERIC2_UART_DBG 0x1808 +#define CLK_CON_DIV_DIV_CLK_PERIC2_USI00 0x180c +#define CLK_CON_DIV_DIV_CLK_PERIC2_USI00_SPI_I2C 0x1810 +#define CLK_CON_DIV_DIV_CLK_PERIC2_USI01 0x1814 +#define CLK_CON_DIV_DIV_CLK_PERIC2_USI01_SPI_I2C 0x1818 +#define CLK_CON_DIV_DIV_CLK_PERIC2_USI02 0x181c +#define CLK_CON_DIV_DIV_CLK_PERIC2_USI03 0x1820 +#define CLK_CON_DIV_DIV_CLK_PERIC2_USI05 0x1824 +#define CLK_CON_DIV_DIV_CLK_PERIC2_USI06 0x1828 +#define CLK_CON_DIV_DIV_CLK_PERIC2_USI11 0x182c +#define CLK_CON_GAT_CLK_BLK_PERIC2_UID_DBG_UART_IPCLKPORT_IPCLK 0x2000 +#define CLK_CON_GAT_CLK_BLK_PERIC2_UID_DBG_UART_IPCLKPORT_PCLK 0x2004 +#define CLK_CON_GAT_CLK_BLK_PERIC2_UID_D_TZPC_PERIC2_IPCLKPORT_PCLK 0x2008 +#define CLK_CON_GAT_CLK_BLK_PERIC2_UID_GPIO_PERIC2_IPCLKPORT_PCLK 0x200c +#define CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C03_OIS_IPCLKPORT_I_PCLK 0x2010 +#define CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C03_OIS_IPCLKPORT_I_SCLK 0x2014 +#define CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C04_IPCLKPORT_I_PCLK 0x2018 +#define CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C04_IPCLKPORT_I_SCLK 0x201c +#define CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C05_IPCLKPORT_I_PCLK 0x2020 +#define CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C05_IPCLKPORT_I_SCLK 0x2024 +#define CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C06_IPCLKPORT_I_PCLK 0x2028 +#define CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C06_IPCLKPORT_I_SCLK 0x202c +#define CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C07_IPCLKPORT_I_PCLK 0x2030 +#define CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C07_IPCLKPORT_I_SCLK 0x2034 +#define CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C08_IPCLKPORT_I_PCLK 0x2038 +#define CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C08_IPCLKPORT_I_SCLK 0x203c +#define CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C09_IPCLKPORT_I_PCLK 0x2040 +#define CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C09_IPCLKPORT_I_SCLK 0x2044 +#define CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C10_IPCLKPORT_I_PCLK 0x2048 +#define CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C10_IPCLKPORT_I_SCLK 0x204c +#define CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C11_IPCLKPORT_I_PCLK 0x2050 +#define CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C11_IPCLKPORT_I_SCLK 0x2054 +#define CLK_CON_GAT_CLK_BLK_PERIC2_UID_PERIC2_CMU_PERIC2_IPCLKPORT_PCLK 0x2058 +#define CLK_CON_GAT_CLK_BLK_PERIC2_UID_PWM_IPCLKPORT_I_PCLK_S0 0x205c +#define CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_FREE_OSCCLK_IPCLKPORT_CLK 0x2060 +#define CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_I2C_IPCLKPORT_CLK 0x2064 +#define CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_NOCP_IPCLKPORT_CLK 0x2068 +#define CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_UART_DBG_IPCLKPORT_CLK 0x206c +#define CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI00_IPCLKPORT_CLK 0x2070 +#define CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI00_SPI_I2C_IPCLKPORT_CLK 0x2074 +#define CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI01_IPCLKPORT_CLK 0x2078 +#define CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI01_SPI_I2C_IPCLKPORT_CLK 0x207c +#define CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI02_IPCLKPORT_CLK 0x2080 +#define CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI03_IPCLKPORT_CLK 0x2084 +#define CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI05_IPCLKPORT_CLK 0x2088 +#define CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI06_IPCLKPORT_CLK 0x208c +#define CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI11_IPCLKPORT_CLK 0x2090 +#define CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_SPI_MS_CTRL_IPCLKPORT_CLK 0x2094 +#define CLK_CON_GAT_CLK_BLK_PERIC2_UID_SLH_AXI_MI_P_PERIC2_IPCLKPORT_I_CLK 0x2098 +#define CLK_CON_GAT_CLK_BLK_PERIC2_UID_SPI_MULTI_SLV_Q_CTRL_PERIC2_IPCLKPORT_CLK 0x209c +#define CLK_CON_GAT_CLK_BLK_PERIC2_UID_SYSREG_PERIC2_IPCLKPORT_PCLK 0x20a0 +#define CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI00_SPI_I2C_IPCLKPORT_IPCLK 0x20a4 +#define CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI00_SPI_I2C_IPCLKPORT_PCLK 0x20a8 +#define CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI00_USI_IPCLKPORT_IPCLK 0x20ac +#define CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI00_USI_IPCLKPORT_PCLK 0x20b0 +#define CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI01_SPI_I2C_IPCLKPORT_IPCLK 0x20b4 +#define CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI01_SPI_I2C_IPCLKPORT_PCLK 0x20b8 +#define CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI01_USI_IPCLKPORT_IPCLK 0x20bc +#define CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI01_USI_IPCLKPORT_PCLK 0x20c0 +#define CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI02_I2C_IPCLKPORT_IPCLK 0x20c4 +#define CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI02_I2C_IPCLKPORT_PCLK 0x20c8 +#define CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI02_USI_IPCLKPORT_IPCLK 0x20cc +#define CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI02_USI_IPCLKPORT_PCLK 0x20d0 +#define CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI03_I2C_IPCLKPORT_IPCLK 0x20d4 +#define CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI03_I2C_IPCLKPORT_PCLK 0x20d8 +#define CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI03_USI_IPCLKPORT_IPCLK 0x20dc +#define CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI03_USI_IPCLKPORT_PCLK 0x20e0 +#define CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI05_I2C_IPCLKPORT_IPCLK 0x20e4 +#define CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI05_I2C_IPCLKPORT_PCLK 0x20e8 +#define CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI05_USI_OIS_IPCLKPORT_IPCLK 0x20ec +#define CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI05_USI_OIS_IPCLKPORT_PCLK 0x20f0 +#define CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI06_I2C_IPCLKPORT_IPCLK 0x20f4 +#define CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI06_I2C_IPCLKPORT_PCLK 0x20f8 +#define CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI06_USI_OIS_IPCLKPORT_IPCLK 0x20fc +#define CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI06_USI_OIS_IPCLKPORT_PCLK 0x2100 +#define CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI11_I2C_IPCLKPORT_IPCLK 0x2104 +#define CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI11_I2C_IPCLKPORT_PCLK 0x2108 +#define CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI11_USI_IPCLKPORT_IPCLK 0x210c +#define CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI11_USI_IPCLKPORT_PCLK 0x2110 +#define CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_I2C_IPCLKPORT_CLK 0x2114 +#define CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_NOCP_IPCLKPORT_CLK 0x2118 +#define CLK_CON_GAT_CLK_BLK_PERIC2_UID_SLH_AXI_MI_LP_CSISPERIC2_IPCLKPORT_I_CLK 0x211c +#define CLK_CON_GAT_CLK_BLK_PERIC2_UID_XIU_P_PERIC2_IPCLKPORT_ACLK 0x2120 + +static const unsigned long peric2_clk_regs[] __initconst = { + PLL_CON0_MUX_CLKCMU_PERIC2_IP0_USER, + PLL_CON1_MUX_CLKCMU_PERIC2_IP0_USER, + PLL_CON0_MUX_CLKCMU_PERIC2_IP1_USER, + PLL_CON1_MUX_CLKCMU_PERIC2_IP1_USER, + PLL_CON0_MUX_CLKCMU_PERIC2_NOC_USER, + PLL_CON1_MUX_CLKCMU_PERIC2_NOC_USER, + CLK_CON_MUX_MUX_CLK_PERIC2_I2C, + CLK_CON_MUX_MUX_CLK_PERIC2_SPI_MS_CTRL, + CLK_CON_MUX_MUX_CLK_PERIC2_UART_DBG, + CLK_CON_MUX_MUX_CLK_PERIC2_USI00, + CLK_CON_MUX_MUX_CLK_PERIC2_USI00_SPI_I2C, + CLK_CON_MUX_MUX_CLK_PERIC2_USI01, + CLK_CON_MUX_MUX_CLK_PERIC2_USI01_SPI_I2C, + CLK_CON_MUX_MUX_CLK_PERIC2_USI02, + CLK_CON_MUX_MUX_CLK_PERIC2_USI03, + CLK_CON_MUX_MUX_CLK_PERIC2_USI05, + CLK_CON_MUX_MUX_CLK_PERIC2_USI06, + CLK_CON_MUX_MUX_CLK_PERIC2_USI11, + CLK_CON_DIV_DIV_CLK_PERIC2_I2C, + CLK_CON_DIV_DIV_CLK_PERIC2_SPI_MS_CTRL, + CLK_CON_DIV_DIV_CLK_PERIC2_UART_DBG, + CLK_CON_DIV_DIV_CLK_PERIC2_USI00, + CLK_CON_DIV_DIV_CLK_PERIC2_USI00_SPI_I2C, + CLK_CON_DIV_DIV_CLK_PERIC2_USI01, + CLK_CON_DIV_DIV_CLK_PERIC2_USI01_SPI_I2C, + CLK_CON_DIV_DIV_CLK_PERIC2_USI02, + CLK_CON_DIV_DIV_CLK_PERIC2_USI03, + CLK_CON_DIV_DIV_CLK_PERIC2_USI05, + CLK_CON_DIV_DIV_CLK_PERIC2_USI06, + CLK_CON_DIV_DIV_CLK_PERIC2_USI11, + CLK_CON_GAT_CLK_BLK_PERIC2_UID_DBG_UART_IPCLKPORT_IPCLK, + CLK_CON_GAT_CLK_BLK_PERIC2_UID_DBG_UART_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC2_UID_D_TZPC_PERIC2_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC2_UID_GPIO_PERIC2_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C03_OIS_IPCLKPORT_I_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C03_OIS_IPCLKPORT_I_SCLK, + CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C04_IPCLKPORT_I_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C04_IPCLKPORT_I_SCLK, + CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C05_IPCLKPORT_I_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C05_IPCLKPORT_I_SCLK, + CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C06_IPCLKPORT_I_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C06_IPCLKPORT_I_SCLK, + CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C07_IPCLKPORT_I_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C07_IPCLKPORT_I_SCLK, + CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C08_IPCLKPORT_I_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C08_IPCLKPORT_I_SCLK, + CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C09_IPCLKPORT_I_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C09_IPCLKPORT_I_SCLK, + CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C10_IPCLKPORT_I_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C10_IPCLKPORT_I_SCLK, + CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C11_IPCLKPORT_I_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC2_UID_I3C11_IPCLKPORT_I_SCLK, + CLK_CON_GAT_CLK_BLK_PERIC2_UID_PERIC2_CMU_PERIC2_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC2_UID_PWM_IPCLKPORT_I_PCLK_S0, + CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_FREE_OSCCLK_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_I2C_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_CLK_PERIC2_NOCP_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_UART_DBG_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI00_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI00_SPI_I2C_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI01_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI01_SPI_I2C_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI02_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI03_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI05_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI06_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_USI11_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_SPI_MS_CTRL_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_PERIC2_UID_SLH_AXI_MI_P_PERIC2_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_PERIC2_UID_SPI_MULTI_SLV_Q_CTRL_PERIC2_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_PERIC2_UID_SYSREG_PERIC2_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI00_SPI_I2C_IPCLKPORT_IPCLK, + CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI00_SPI_I2C_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI00_USI_IPCLKPORT_IPCLK, + CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI00_USI_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI01_SPI_I2C_IPCLKPORT_IPCLK, + CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI01_SPI_I2C_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI01_USI_IPCLKPORT_IPCLK, + CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI01_USI_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI02_I2C_IPCLKPORT_IPCLK, + CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI02_I2C_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI02_USI_IPCLKPORT_IPCLK, + CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI02_USI_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI03_I2C_IPCLKPORT_IPCLK, + CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI03_I2C_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI03_USI_IPCLKPORT_IPCLK, + CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI03_USI_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI05_I2C_IPCLKPORT_IPCLK, + CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI05_I2C_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI05_USI_OIS_IPCLKPORT_IPCLK, + CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI05_USI_OIS_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI06_I2C_IPCLKPORT_IPCLK, + CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI06_I2C_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI06_USI_OIS_IPCLKPORT_IPCLK, + CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI06_USI_OIS_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI11_I2C_IPCLKPORT_IPCLK, + CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI11_I2C_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI11_USI_IPCLKPORT_IPCLK, + CLK_CON_GAT_CLK_BLK_PERIC2_UID_USI11_USI_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_I2C_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_PERIC2_UID_RSTNSYNC_SR_CLK_PERIC2_NOCP_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_PERIC2_UID_SLH_AXI_MI_LP_CSISPERIC2_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_PERIC2_UID_XIU_P_PERIC2_IPCLKPORT_ACLK, +}; + +PNAME(mout_peric2_ip0_user_p) = { "oscclk", + "dout_cmu_peric2_ip0" }; +PNAME(mout_peric2_ip1_user_p) = { "oscclk", + "dout_cmu_peric2_ip1" }; +PNAME(mout_peric2_noc_user_p) = { "oscclk", + "dout_cmu_peric2_noc" }; +PNAME(mout_peric2_i2c_p) = { "oscclk", + "mout_peric2_ip0_user", + "mout_peric2_ip1_user", + "oscclk" }; +PNAME(mout_peric2_spi_ms_ctrl_p) = { "oscclk", + "mout_peric2_ip0_user", + "mout_peric2_ip1_user", + "oscclk" }; +PNAME(mout_peric2_uart_dbg_p) = { "oscclk", + "mout_peric2_ip0_user", + "mout_peric2_ip1_user", + "oscclk" }; +PNAME(mout_peric2_usi00_p) = { "oscclk", + "mout_peric2_ip0_user", + "mout_peric2_ip1_user", + "oscclk" }; +PNAME(mout_peric2_usi00_spi_i2c_p) = { "oscclk", + "mout_peric2_ip0_user", + "mout_peric2_ip1_user", + "oscclk" }; +PNAME(mout_peric2_usi01_p) = { "oscclk", + "mout_peric2_ip0_user", + "mout_peric2_ip1_user", + "oscclk" }; +PNAME(mout_peric2_usi01_spi_i2c_p) = { "oscclk", + "mout_peric2_ip0_user", + "mout_peric2_ip1_user", + "oscclk" }; +PNAME(mout_peric2_usi02_p) = { "oscclk", + "mout_peric2_ip0_user", + "mout_peric2_ip1_user", + "oscclk" }; +PNAME(mout_peric2_usi03_p) = { "oscclk", + "mout_peric2_ip0_user", + "mout_peric2_ip1_user", + "oscclk" }; +PNAME(mout_peric2_usi05_p) = { "oscclk", + "mout_peric2_ip0_user", + "mout_peric2_ip1_user", + "oscclk" }; +PNAME(mout_peric2_usi06_p) = { "oscclk", + "mout_peric2_ip0_user", + "mout_peric2_ip1_user", + "oscclk" }; +PNAME(mout_peric2_usi11_p) = { "oscclk", + "mout_peric2_ip0_user", + "mout_peric2_ip1_user", + "oscclk" }; + +static const struct samsung_mux_clock peric2_mux_clks[] __initconst = { + MUX(CLK_MOUT_PERIC2_IP0_USER, "mout_peric2_ip0_user", + mout_peric2_ip0_user_p, PLL_CON0_MUX_CLKCMU_PERIC2_IP0_USER, 4, 1), + MUX(CLK_MOUT_PERIC2_IP1_USER, "mout_peric2_ip1_user", + mout_peric2_ip1_user_p, PLL_CON0_MUX_CLKCMU_PERIC2_IP1_USER, 4, 1), + MUX(CLK_MOUT_PERIC2_NOC_USER, "mout_peric2_noc_user", + mout_peric2_noc_user_p, PLL_CON0_MUX_CLKCMU_PERIC2_NOC_USER, 4, 1), + MUX(CLK_MOUT_PERIC2_I2C, "mout_peric2_i2c", mout_peric2_i2c_p, + CLK_CON_MUX_MUX_CLK_PERIC2_I2C, 0, 2), + MUX(CLK_MOUT_PERIC2_SPI_MS_CTRL, "mout_peric2_spi_ms_ctrl", + mout_peric2_spi_ms_ctrl_p, + CLK_CON_MUX_MUX_CLK_PERIC2_SPI_MS_CTRL, 0, 2), + MUX(CLK_MOUT_PERIC2_UART_DBG, "mout_peric2_uart_dbg", + mout_peric2_uart_dbg_p, CLK_CON_MUX_MUX_CLK_PERIC2_UART_DBG, 0, 2), + MUX(CLK_MOUT_PERIC2_USI00, "mout_peric2_usi00", mout_peric2_usi00_p, + CLK_CON_MUX_MUX_CLK_PERIC2_USI00, 0, 2), + MUX(CLK_MOUT_PERIC2_USI00_SPI_I2C, "mout_peric2_usi00_spi_i2c", + mout_peric2_usi00_spi_i2c_p, CLK_CON_MUX_MUX_CLK_PERIC2_USI00_SPI_I2C, + 0, 2), + MUX(CLK_MOUT_PERIC2_USI01, "mout_peric2_usi01", mout_peric2_usi01_p, + CLK_CON_MUX_MUX_CLK_PERIC2_USI01, 0, 2), + MUX(CLK_MOUT_PERIC2_USI01_SPI_I2C, "mout_peric2_usi01_spi_i2c", + mout_peric2_usi01_spi_i2c_p, + CLK_CON_MUX_MUX_CLK_PERIC2_USI01_SPI_I2C, 0, 2), + MUX(CLK_MOUT_PERIC2_USI02, "mout_peric2_usi02", mout_peric2_usi02_p, + CLK_CON_MUX_MUX_CLK_PERIC2_USI02, 0, 2), + MUX(CLK_MOUT_PERIC2_USI03, "mout_peric2_usi03", mout_peric2_usi03_p, + CLK_CON_MUX_MUX_CLK_PERIC2_USI03, 0, 2), + MUX(CLK_MOUT_PERIC2_USI05, "mout_peric2_usi05", mout_peric2_usi05_p, + CLK_CON_MUX_MUX_CLK_PERIC2_USI05, 0, 2), + MUX(CLK_MOUT_PERIC2_USI06, "mout_peric2_usi06", mout_peric2_usi06_p, + CLK_CON_MUX_MUX_CLK_PERIC2_USI06, 0, 2), + MUX(CLK_MOUT_PERIC2_USI11, "mout_peric2_usi11", mout_peric2_usi11_p, + CLK_CON_MUX_MUX_CLK_PERIC2_USI11, 0, 2), +}; + +static const struct samsung_div_clock peric2_div_clks[] __initconst = { + DIV(CLK_DOUT_PERIC2_I2C, "dout_peric2_i2c", "mout_peric2_i2c", + CLK_CON_DIV_DIV_CLK_PERIC2_I2C, 0, 4), + DIV(CLK_DOUT_PERIC2_SPI_MS_CTRL, "dout_peric2_spi_ms_ctrl", + "mout_peric2_spi_ms_ctrl", CLK_CON_DIV_DIV_CLK_PERIC2_SPI_MS_CTRL, + 0, 7), + DIV(CLK_DOUT_PERIC2_UART_DBG, "dout_peric2_uart_dbg", + "mout_peric2_uart_dbg", CLK_CON_DIV_DIV_CLK_PERIC2_UART_DBG, 0, 4), + DIV(CLK_DOUT_PERIC2_USI00, "dout_peric2_usi00", "mout_peric2_usi00", + CLK_CON_DIV_DIV_CLK_PERIC2_USI00, 0, 7), + DIV(CLK_DOUT_PERIC2_USI00_SPI_I2C, "dout_peric2_usi00_spi_i2c", + "mout_peric2_usi00_spi_i2c", + CLK_CON_DIV_DIV_CLK_PERIC2_USI00_SPI_I2C, 0, 4), + DIV(CLK_DOUT_PERIC2_USI01, "dout_peric2_usi01", "mout_peric2_usi01", + CLK_CON_DIV_DIV_CLK_PERIC2_USI01, 0, 7), + DIV(CLK_DOUT_PERIC2_USI01_SPI_I2C, "dout_peric2_usi01_spi_i2c", + "mout_peric2_usi01_spi_i2c", + CLK_CON_DIV_DIV_CLK_PERIC2_USI01_SPI_I2C, 0, 4), + DIV(CLK_DOUT_PERIC2_USI02, "dout_peric2_usi02", "mout_peric2_usi02", + CLK_CON_DIV_DIV_CLK_PERIC2_USI02, 0, 7), + DIV(CLK_DOUT_PERIC2_USI03, "dout_peric2_usi03", "mout_peric2_usi03", + CLK_CON_DIV_DIV_CLK_PERIC2_USI03, 0, 7), + DIV(CLK_DOUT_PERIC2_USI05, "dout_peric2_usi05", "mout_peric2_usi05", + CLK_CON_DIV_DIV_CLK_PERIC2_USI05, 0, 7), + DIV(CLK_DOUT_PERIC2_USI06, "dout_peric2_usi06", "mout_peric2_usi06", + CLK_CON_DIV_DIV_CLK_PERIC2_USI06, 0, 7), + DIV(CLK_DOUT_PERIC2_USI11, "dout_peric2_usi11", "mout_peric2_usi11", + CLK_CON_DIV_DIV_CLK_PERIC2_USI11, 0, 7), +}; + +static const struct samsung_cmu_info peric2_cmu_info __initconst = { + .mux_clks = peric2_mux_clks, + .nr_mux_clks = ARRAY_SIZE(peric2_mux_clks), + .div_clks = peric2_div_clks, + .nr_div_clks = ARRAY_SIZE(peric2_div_clks), + .nr_clk_ids = CLKS_NR_PERIC2, + .clk_regs = peric2_clk_regs, + .nr_clk_regs = ARRAY_SIZE(peric2_clk_regs), + .clk_name = "noc", +}; + +/* ---- CMU_UFS ------------------------------------------------------------ */ + +/* Register Offset definitions for CMU_UFS(0x11000000) */ +#define PLL_CON0_MUX_CLKCMU_UFS_MMC_CARD_USER 0x600 +#define PLL_CON1_MUX_CLKCMU_UFS_MMC_CARD_USER 0x604 +#define PLL_CON0_MUX_CLKCMU_UFS_NOC_USER 0x610 +#define PLL_CON1_MUX_CLKCMU_UFS_NOC_USER 0x614 +#define PLL_CON0_MUX_CLKCMU_UFS_UFS_EMBD_USER 0x620 +#define PLL_CON1_MUX_CLKCMU_UFS_UFS_EMBD_USER 0x624 +#define CLK_CON_GAT_CLK_BLK_UFS_UID_BLK_UFS_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK 0x2000 +#define CLK_CON_GAT_CLK_BLK_UFS_UID_D_TZPC_UFS_IPCLKPORT_PCLK 0x2004 +#define CLK_CON_GAT_CLK_BLK_UFS_UID_GPIO_HSI1UFS_IPCLKPORT_PCLK 0x2008 +#define CLK_CON_GAT_CLK_BLK_UFS_UID_GPIO_UFS_IPCLKPORT_PCLK 0x200c +#define CLK_CON_GAT_CLK_BLK_UFS_UID_LH_ACEL_SI_D_UFS_IPCLKPORT_I_CLK 0x2010 +#define CLK_CON_GAT_CLK_BLK_UFS_UID_MMC_CARD_IPCLKPORT_I_ACLK 0x2014 +#define CLK_CON_GAT_CLK_BLK_UFS_UID_MMC_CARD_IPCLKPORT_SDCLKIN 0x2018 +#define CLK_CON_GAT_CLK_BLK_UFS_UID_OTP_DESERIAL_UFS_EMBD_FMP_IPCLKPORT_I_CLK 0x201c +#define CLK_CON_GAT_CLK_BLK_UFS_UID_PPMU_UFS_IPCLKPORT_ACLK 0x2024 +#define CLK_CON_GAT_CLK_BLK_UFS_UID_PPMU_UFS_IPCLKPORT_PCLK 0x2028 +#define CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_FREE_OSCCLK_IPCLKPORT_CLK 0x202c +#define CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_MMC_CARD_IPCLKPORT_CLK 0x2030 +#define CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_NOC_IPCLKPORT_CLK 0x2034 +#define CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_UFS_EMBD_IPCLKPORT_CLK 0x2038 +#define CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_SR_CLK_UFS_FREE_OSCCLK_IPCLKPORT_CLK 0x203c +#define CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_SR_CLK_UFS_NOC_IPCLKPORT_CLK 0x2040 +#define CLK_CON_GAT_CLK_BLK_UFS_UID_SLH_AST_SI_G_PPMU_UFS_IPCLKPORT_I_CLK 0x2044 +#define CLK_CON_GAT_CLK_BLK_UFS_UID_SLH_AXI_MI_P_UFS_IPCLKPORT_I_CLK 0x2048 +#define CLK_CON_GAT_CLK_BLK_UFS_UID_SPC_UFS_IPCLKPORT_PCLK 0x204c +#define CLK_CON_GAT_CLK_BLK_UFS_UID_SYSMMU_UFS_IPCLKPORT_CLK_S2 0x2050 +#define CLK_CON_GAT_CLK_BLK_UFS_UID_SYSREG_UFS_IPCLKPORT_PCLK 0x2054 +#define CLK_CON_GAT_CLK_BLK_UFS_UID_UFS_CMU_UFS_IPCLKPORT_PCLK 0x2058 +#define CLK_CON_GAT_CLK_BLK_UFS_UID_UFS_EMBD_IPCLKPORT_I_ACLK 0x205c +#define CLK_CON_GAT_CLK_BLK_UFS_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO 0x2060 +#define CLK_CON_GAT_CLK_BLK_UFS_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK 0x2064 +#define CLK_CON_GAT_CLK_BLK_UFS_UID_VGEN_LITE_UFS_IPCLKPORT_CLK 0x2068 +#define CLK_CON_GAT_CLK_BLK_UFS_UID_XIU_D_UFS_IPCLKPORT_ACLK 0x206c +#define CLK_CON_GAT_CLK_BLK_UFS_UID_XIU_P_UFS_IPCLKPORT_ACLK 0x2070 + +static const unsigned long ufs_clk_regs[] __initconst = { + PLL_CON0_MUX_CLKCMU_UFS_MMC_CARD_USER, + PLL_CON1_MUX_CLKCMU_UFS_MMC_CARD_USER, + PLL_CON0_MUX_CLKCMU_UFS_NOC_USER, + PLL_CON1_MUX_CLKCMU_UFS_NOC_USER, + PLL_CON0_MUX_CLKCMU_UFS_UFS_EMBD_USER, + PLL_CON1_MUX_CLKCMU_UFS_UFS_EMBD_USER, + CLK_CON_GAT_CLK_BLK_UFS_UID_BLK_UFS_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_UFS_UID_D_TZPC_UFS_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_UFS_UID_GPIO_HSI1UFS_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_UFS_UID_GPIO_UFS_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_UFS_UID_LH_ACEL_SI_D_UFS_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_UFS_UID_MMC_CARD_IPCLKPORT_I_ACLK, + CLK_CON_GAT_CLK_BLK_UFS_UID_MMC_CARD_IPCLKPORT_SDCLKIN, + CLK_CON_GAT_CLK_BLK_UFS_UID_OTP_DESERIAL_UFS_EMBD_FMP_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_UFS_UID_PPMU_UFS_IPCLKPORT_ACLK, + CLK_CON_GAT_CLK_BLK_UFS_UID_PPMU_UFS_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_FREE_OSCCLK_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_MMC_CARD_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_NOC_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_CLK_UFS_UFS_EMBD_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_SR_CLK_UFS_FREE_OSCCLK_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_UFS_UID_RSTNSYNC_SR_CLK_UFS_NOC_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_UFS_UID_SLH_AST_SI_G_PPMU_UFS_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_UFS_UID_SLH_AXI_MI_P_UFS_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_UFS_UID_SPC_UFS_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_UFS_UID_SYSMMU_UFS_IPCLKPORT_CLK_S2, + CLK_CON_GAT_CLK_BLK_UFS_UID_SYSREG_UFS_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_UFS_UID_UFS_CMU_UFS_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_UFS_UID_UFS_EMBD_IPCLKPORT_I_ACLK, + CLK_CON_GAT_CLK_BLK_UFS_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO, + CLK_CON_GAT_CLK_BLK_UFS_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK, + CLK_CON_GAT_CLK_BLK_UFS_UID_VGEN_LITE_UFS_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_UFS_UID_XIU_D_UFS_IPCLKPORT_ACLK, + CLK_CON_GAT_CLK_BLK_UFS_UID_XIU_P_UFS_IPCLKPORT_ACLK, +}; + +PNAME(mout_clkcmu_ufs_mmc_card_user_p) = { "oscclk", + "mout_cmu_ufs_mmc_card" }; +PNAME(mout_clkcmu_ufs_noc_user_p) = { "oscclk", "dout_cmu_ufs_noc" }; +PNAME(mout_clkcmu_ufs_ufs_embd_user_p) = { "oscclk", + "dout_cmu_ufs_ufs_embd" }; + +static const struct samsung_mux_clock ufs_mux_clks[] __initconst = { + MUX(CLK_MOUT_UFS_MMC_CARD_USER, "mout_ufs_mmc_card_user", + mout_clkcmu_ufs_mmc_card_user_p, + PLL_CON0_MUX_CLKCMU_UFS_MMC_CARD_USER, 4, 1), + MUX(CLK_MOUT_UFS_NOC_USER, "mout_ufs_noc_user", + mout_clkcmu_ufs_noc_user_p, + PLL_CON0_MUX_CLKCMU_UFS_NOC_USER, 4, 1), + MUX(CLK_MOUT_UFS_UFS_EMBD_USER, "mout_ufs_ufs_embd_user", + mout_clkcmu_ufs_ufs_embd_user_p, + PLL_CON0_MUX_CLKCMU_UFS_UFS_EMBD_USER, 4, 1), +}; + +static const struct samsung_cmu_info ufs_cmu_info __initconst = { + .mux_clks = ufs_mux_clks, + .nr_mux_clks = ARRAY_SIZE(ufs_mux_clks), + .nr_clk_ids = CLKS_NR_UFS, + .clk_regs = ufs_clk_regs, + .nr_clk_regs = ARRAY_SIZE(ufs_clk_regs), + .clk_name = "noc", +}; + +/* ---- CMU_VTS ------------------------------------------------------------ */ + +/* Register Offset definitions for CMU_VTS (0x15300000) */ +#define PLL_CON0_MUX_CLKALIVE_VTS_NOC_USER 0x600 +#define PLL_CON1_MUX_CLKALIVE_VTS_NOC_USER 0x604 +#define PLL_CON0_MUX_CLKALIVE_VTS_RCO_USER 0x610 +#define PLL_CON1_MUX_CLKALIVE_VTS_RCO_USER 0x614 +#define PLL_CON0_MUX_CLKCMU_VTS_DMIC_USER 0x620 +#define PLL_CON1_MUX_CLKCMU_VTS_DMIC_USER 0x624 +#define CLK_CON_MUX_MUX_CLKVTS_AUD_DMIC1 0x1000 +#define CLK_CON_MUX_MUX_CLK_VTS_NOC 0x1004 +#define CLK_CON_MUX_MUX_CLK_VTS_DMIC_PAD 0x100c +#define CLK_CON_DIV_DIV_CLKVTS_AUD_DMIC0 0x1800 +#define CLK_CON_DIV_DIV_CLKVTS_AUD_DMIC1 0x1804 +#define CLK_CON_DIV_DIV_CLK_VTS_CPU 0x1808 +#define CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF 0x1814 +#define CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_DIV2 0x1818 +#define CLK_CON_DIV_DIV_CLK_VTS_NOC 0x181c +#define CLK_CON_DIV_DIV_CLK_VTS_SERIAL_LIF 0x1820 +#define CLK_CON_DIV_DIV_CLK_VTS_SERIAL_LIF_CORE 0x1824 +#define CLK_CON_GAT_CLKVTS_AUD_DMIC0 0x2000 +#define CLK_CON_GAT_CLKVTS_AUD_DMIC1 0x2004 +#define CLK_CON_GAT_CLK_BLK_VTS_UID_BAAW_VTS_IPCLKPORT_I_PCLK 0x2008 +#define CLK_CON_GAT_CLK_BLK_VTS_UID_LH_AXI_MI_IP_VC2VTS_IPCLKPORT_I_CLK 0x200c +#define CLK_CON_GAT_CLK_BLK_VTS_UID_LH_AXI_SI_ID_VTS2VC_IPCLKPORT_I_CLK 0x2010 +#define CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_FREE_OSCCLK_IPCLKPORT_CLK 0x2014 +#define CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_DMIC_IF_IPCLKPORT_CLK 0x2018 +#define CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_SERIAL_LIF_CORE_IPCLKPORT_CLK 0x2020 +#define CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_SERIAL_LIF_IPCLKPORT_CLK 0x2024 +#define CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_YAMIN_IPCLKPORT_CLK 0x2028 +#define CLK_CON_GAT_CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_ACLK 0x202c +#define CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK 0x2030 +#define CLK_CON_GAT_CLK_BLK_VTS_UID_ASYNCINTERRUPT_VTS_IPCLKPORT_CLK 0x2034 +#define CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_CLK 0x2068 +#define CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_DIV2_CLK 0x206c +#define CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_PCLK 0x2070 +#define CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_CLK 0x2074 +#define CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_DIV2_CLK 0x2078 +#define CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_PCLK 0x207c +#define CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_DMIC_IF_CLK 0x2080 +#define CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_DMIC_IF_DIV2_CLK 0x2084 +#define CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_PCLK 0x2088 +#define CLK_CON_GAT_CLK_BLK_VTS_UID_GPIO_VTS_IPCLKPORT_PCLK 0x2090 +#define CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_CODE_IPCLKPORT_I_ACLK 0x20ac +#define CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_CODE_IPCLKPORT_I_PCLK 0x20b0 +#define CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_DATA0_IPCLKPORT_I_ACLK 0x20b4 +#define CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_DATA0_IPCLKPORT_I_PCLK 0x20b8 +#define CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_DATA1_IPCLKPORT_I_ACLK 0x20bc +#define CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_DATA1_IPCLKPORT_I_PCLK 0x20c0 +#define CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_PCM_IPCLKPORT_I_ACLK 0x20c4 +#define CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_PCM_IPCLKPORT_I_PCLK 0x20c8 +#define CLK_CON_GAT_CLK_BLK_VTS_UID_MAILBOX_ABOX_VTS_IPCLKPORT_PCLK 0x20cc +#define CLK_CON_GAT_CLK_BLK_VTS_UID_MAILBOX_AP_VTS_IPCLKPORT_PCLK 0x20d0 +#define CLK_CON_GAT_CLK_BLK_VTS_UID_MAILBOX_DNC_VTS_IPCLKPORT_PCLK 0x20d4 +#define CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_NOC_IPCLKPORT_CLK 0x20ec +#define CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_YAMIN_IPCLKPORT_CLK 0x20f8 +#define CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_NOC_IPCLKPORT_CLK 0x20fc +#define CLK_CON_GAT_CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_BCLK 0x2104 +#define CLK_CON_GAT_CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_CCLK 0x2108 +#define CLK_CON_GAT_CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_PCLK 0x210c +#define CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_ACLK_CPU 0x2124 +#define CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_DIV2_CLK 0x2128 +#define CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK0 0x212c +#define CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK1 0x2130 +#define CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK2 0x2134 +#define CLK_CON_GAT_CLK_BLK_VTS_UID_SYSREG_VTS_IPCLKPORT_PCLK 0x213c +#define CLK_CON_GAT_CLK_BLK_VTS_UID_TIMER1_IPCLKPORT_PCLK 0x2140 +#define CLK_CON_GAT_CLK_BLK_VTS_UID_TIMER2_IPCLKPORT_PCLK 0x2144 +#define CLK_CON_GAT_CLK_BLK_VTS_UID_TIMER_IPCLKPORT_PCLK 0x2148 +#define CLK_CON_GAT_CLK_BLK_VTS_UID_VTS_CMU_VTS_IPCLKPORT_PCLK 0x2150 +#define CLK_CON_GAT_CLK_BLK_VTS_UID_WDT_VTS_IPCLKPORT_PCLK 0x2154 +#define CLK_CON_GAT_CLK_BLK_VTS_UID_XIU_DP0_VTS_IPCLKPORT_ACLK 0x2158 +#define CLK_CON_GAT_CLK_BLK_VTS_UID_YAMIN_MCU_VTS_IPCLKPORT_CLKIN 0x215c +#define CLK_CON_GAT_CLK_BLK_VTS_UID_YAMIN_MCU_VTS_IPCLKPORT_DBGCLK 0x2160 +#define CLK_CON_GAT_CLK_BLK_VTS_UID_YAMIN_MCU_VTS_IPCLKPORT_IWICCLK 0x2164 + +static const unsigned long vts_clk_regs[] __initconst = { + PLL_CON0_MUX_CLKALIVE_VTS_NOC_USER, + PLL_CON1_MUX_CLKALIVE_VTS_NOC_USER, + PLL_CON0_MUX_CLKALIVE_VTS_RCO_USER, + PLL_CON1_MUX_CLKALIVE_VTS_RCO_USER, + PLL_CON0_MUX_CLKCMU_VTS_DMIC_USER, + PLL_CON1_MUX_CLKCMU_VTS_DMIC_USER, + CLK_CON_MUX_MUX_CLKVTS_AUD_DMIC1, + CLK_CON_MUX_MUX_CLK_VTS_NOC, + CLK_CON_MUX_MUX_CLK_VTS_DMIC_PAD, + CLK_CON_DIV_DIV_CLKVTS_AUD_DMIC0, + CLK_CON_DIV_DIV_CLKVTS_AUD_DMIC1, + CLK_CON_DIV_DIV_CLK_VTS_CPU, + CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF, + CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_DIV2, + CLK_CON_DIV_DIV_CLK_VTS_NOC, + CLK_CON_DIV_DIV_CLK_VTS_SERIAL_LIF, + CLK_CON_DIV_DIV_CLK_VTS_SERIAL_LIF_CORE, + CLK_CON_GAT_CLKVTS_AUD_DMIC0, + CLK_CON_GAT_CLKVTS_AUD_DMIC1, + CLK_CON_GAT_CLK_BLK_VTS_UID_BAAW_VTS_IPCLKPORT_I_PCLK, + CLK_CON_GAT_CLK_BLK_VTS_UID_LH_AXI_MI_IP_VC2VTS_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_VTS_UID_LH_AXI_SI_ID_VTS2VC_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_FREE_OSCCLK_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_DMIC_IF_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_SERIAL_LIF_CORE_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_SERIAL_LIF_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_YAMIN_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_ACLK, + CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_FRC_OTP_DESERIAL_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_VTS_UID_ASYNCINTERRUPT_VTS_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_CLK, + CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_DMIC_IF_DIV2_CLK, + CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF0_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_CLK, + CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_DMIC_IF_DIV2_CLK, + CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF1_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_DMIC_IF_CLK, + CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_DMIC_IF_DIV2_CLK, + CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF2_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_VTS_UID_GPIO_VTS_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_CODE_IPCLKPORT_I_ACLK, + CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_CODE_IPCLKPORT_I_PCLK, + CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_DATA0_IPCLKPORT_I_ACLK, + CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_DATA0_IPCLKPORT_I_PCLK, + CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_DATA1_IPCLKPORT_I_ACLK, + CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_DATA1_IPCLKPORT_I_PCLK, + CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_PCM_IPCLKPORT_I_ACLK, + CLK_CON_GAT_CLK_BLK_VTS_UID_INTMEM_PCM_IPCLKPORT_I_PCLK, + CLK_CON_GAT_CLK_BLK_VTS_UID_MAILBOX_ABOX_VTS_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_VTS_UID_MAILBOX_AP_VTS_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_VTS_UID_MAILBOX_DNC_VTS_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_NOC_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_YAMIN_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_VTS_UID_RSTNSYNC_SR_CLK_VTS_NOC_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_BCLK, + CLK_CON_GAT_CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_CCLK, + CLK_CON_GAT_CLK_BLK_VTS_UID_SERIAL_LIF_VT_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_ACLK_CPU, + CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_AUD_DIV2_CLK, + CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK0, + CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK1, + CLK_CON_GAT_CLK_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_DMIC_IF_PAD_CLK2, + CLK_CON_GAT_CLK_BLK_VTS_UID_SYSREG_VTS_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_VTS_UID_TIMER1_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_VTS_UID_TIMER2_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_VTS_UID_TIMER_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_VTS_UID_VTS_CMU_VTS_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_VTS_UID_WDT_VTS_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_VTS_UID_XIU_DP0_VTS_IPCLKPORT_ACLK, + CLK_CON_GAT_CLK_BLK_VTS_UID_YAMIN_MCU_VTS_IPCLKPORT_CLKIN, + CLK_CON_GAT_CLK_BLK_VTS_UID_YAMIN_MCU_VTS_IPCLKPORT_DBGCLK, + CLK_CON_GAT_CLK_BLK_VTS_UID_YAMIN_MCU_VTS_IPCLKPORT_IWICCLK, +}; + +PNAME(mout_clkalive_vts_noc_user_p) = { "oscclk" }; +PNAME(mout_clkalive_vts_rco_user_p) = { "oscclk" }; +PNAME(mout_clkcmu_vts_dmic_user_p) = { "oscclk", "dout_cmu_vts_dmic" }; +PNAME(mout_clkvts_aud_dmic1_p) = { "dout_clkvts_aud_dmic1", + "dout_clkvts_dmic_if_div2", + "dmic_clk0_in", "dmic_clk1_in", + "dmic_clk2_in", "oscclk", "oscclk", + "oscclk" }; +PNAME(mout_clkvts_noc_p) = { "mout_clkalive_vts_noc_user", + "mout_clkalive_vts_rco_user" }; +PNAME(mout_clkvts_dmic_pad_p) = { "mout_clkalive_vts_rco_user", + "mout_clkcmu_vts_dmic_user" }; + +static const struct samsung_mux_clock vts_mux_clks[] __initconst = { + MUX(CLK_MOUT_CLKALIVE_VTS_NOC_USER, "mout_clkalive_vts_noc_user", + mout_clkalive_vts_noc_user_p, PLL_CON0_MUX_CLKALIVE_VTS_NOC_USER, + 4, 1), + MUX(CLK_MOUT_CLKALIVE_VTS_RCO_USER, "mout_clkalive_vts_rco_user", + mout_clkalive_vts_rco_user_p, PLL_CON0_MUX_CLKALIVE_VTS_RCO_USER, + 4, 1), + MUX(CLK_MOUT_CLKCMU_VTS_DMIC_USER, "mout_clkcmu_vts_dmic_user", + mout_clkcmu_vts_dmic_user_p, PLL_CON0_MUX_CLKCMU_VTS_DMIC_USER, + 4, 1), + MUX(CLK_MOUT_CLKVTS_AUD_DMIC1, "mout_clkvts_aud_dmic1", + mout_clkvts_aud_dmic1_p, CLK_CON_MUX_MUX_CLKVTS_AUD_DMIC1, 0, 3), + MUX(CLK_MOUT_CLKVTS_NOC, "mout_clkvts_noc", mout_clkvts_noc_p, + CLK_CON_MUX_MUX_CLK_VTS_NOC, 0, 1), + MUX(CLK_MOUT_CLKVTS_DMIC_PAD, "mout_clkvts_dmic_pad", + mout_clkvts_dmic_pad_p, CLK_CON_MUX_MUX_CLK_VTS_DMIC_PAD, 0, 1), +}; + +static const struct samsung_div_clock vts_div_clks[] __initconst = { + DIV(CLK_DOUT_CLKVTS_AUD_DMIC0, "dout_clkvts_aud_dmic0", + "mout_clkvts_dmic_pad", CLK_CON_DIV_DIV_CLKVTS_AUD_DMIC0, 0, 5), + DIV(CLK_DOUT_CLKVTS_AUD_DMIC1, "dout_clkvts_aud_dmic1", + "dout_clkvts_aud_dmic0", CLK_CON_DIV_DIV_CLKVTS_AUD_DMIC1, 0, 4), + DIV(CLK_DOUT_CLKVTS_CPU, "dout_clkvts_cpu", "mout_clkvts_noc", + CLK_CON_DIV_DIV_CLK_VTS_CPU, 0, 3), + DIV(CLK_DOUT_CLKVTS_DMIC_IF, "dout_clkvts_dmic_if", + "dout_clkvts_aud_dmic0", CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF, 0, 7), + DIV(CLK_DOUT_CLKVTS_DMIC_IF_DIV2, "dout_clkvts_dmic_if_div2", + "dout_clkvts_dmic_if", CLK_CON_DIV_DIV_CLK_VTS_DMIC_IF_DIV2, 0, 4), + DIV(CLK_DOUT_CLKVTS_NOC, "dout_clkvts_noc", "dout_clkvts_cpu", + CLK_CON_DIV_DIV_CLK_VTS_NOC, 0, 3), + DIV(CLK_DOUT_CLKVTS_SERIAL_LIF, "dout_clkvts_serial_lif", + "mout_clkalive_vts_rco_user", CLK_CON_DIV_DIV_CLK_VTS_SERIAL_LIF, + 0, 7), + DIV(CLK_DOUT_CLKVTS_SERIAL_LIF_CORE, "dout_clkvts_serial_lif_core", + "mout_clkalive_vts_rco_user", + CLK_CON_DIV_DIV_CLK_VTS_SERIAL_LIF_CORE, 0, 7), +}; + +static const struct samsung_fixed_rate_clock vts_fixed_clks[] __initconst = { + FRATE(0, "dmic_clk0_in", NULL, 0, 100000000), + FRATE(0, "dmic_clk1_in", NULL, 0, 100000000), + FRATE(0, "dmic_clk2_in", NULL, 0, 100000000), +}; + +static const struct samsung_cmu_info vts_cmu_info __initconst = { + .mux_clks = vts_mux_clks, + .nr_mux_clks = ARRAY_SIZE(vts_mux_clks), + .div_clks = vts_div_clks, + .nr_div_clks = ARRAY_SIZE(vts_div_clks), + .fixed_clks = vts_fixed_clks, + .nr_fixed_clks = ARRAY_SIZE(vts_fixed_clks), + .nr_clk_ids = CLKS_NR_VTS, + .clk_regs = vts_clk_regs, + .nr_clk_regs = ARRAY_SIZE(vts_clk_regs), + .clk_name = "dmic", +}; + +static int __init exynos2200_cmu_probe(struct platform_device *pdev) +{ + const struct samsung_cmu_info *info; + struct device *dev = &pdev->dev; + + info = of_device_get_match_data(dev); + exynos_arm64_register_cmu(dev, dev->of_node, info); + + return 0; +} + +static const struct of_device_id exynos2200_cmu_of_match[] = { + { + .compatible = "samsung,exynos2200-cmu-cmgp", + .data = &cmgp_cmu_info, + }, { + .compatible = "samsung,exynos2200-cmu-hsi0", + .data = &hsi0_cmu_info, + }, { + .compatible = "samsung,exynos2200-cmu-peric0", + .data = &peric0_cmu_info, + }, { + .compatible = "samsung,exynos2200-cmu-peric1", + .data = &peric1_cmu_info, + }, { + .compatible = "samsung,exynos2200-cmu-peric2", + .data = &peric2_cmu_info, + }, { + .compatible = "samsung,exynos2200-cmu-ufs", + .data = &ufs_cmu_info, + }, { + .compatible = "samsung,exynos2200-cmu-vts", + .data = &vts_cmu_info, + }, { } +}; + +static struct platform_driver exynos2200_cmu_driver __refdata = { + .driver = { + .name = "exynos2200-cmu", + .of_match_table = exynos2200_cmu_of_match, + .suppress_bind_attrs = true, + }, + .probe = exynos2200_cmu_probe, +}; + +static int __init exynos2200_cmu_init(void) +{ + return platform_driver_register(&exynos2200_cmu_driver); +} +core_initcall(exynos2200_cmu_init); diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c index aec4d18c1f9e..84564ec4c8ec 100644 --- a/drivers/clk/samsung/clk-exynos3250.c +++ b/drivers/clk/samsung/clk-exynos3250.c @@ -7,10 +7,8 @@ #include <linux/clk-provider.h> #include <linux/io.h> -#include <linux/of.h> -#include <linux/of_address.h> +#include <linux/mod_devicetable.h> #include <linux/platform_device.h> - #include <dt-bindings/clock/exynos3250.h> #include "clk.h" diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index 16be0c53903c..374c26e5d9fd 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -9,9 +9,9 @@ #include <dt-bindings/clock/exynos4.h> #include <linux/slab.h> -#include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/io.h> +#include <linux/mod_devicetable.h> #include <linux/of.h> #include <linux/of_address.h> diff --git a/drivers/clk/samsung/clk-exynos4412-isp.c b/drivers/clk/samsung/clk-exynos4412-isp.c index 29c5644f0593..fa915057e109 100644 --- a/drivers/clk/samsung/clk-exynos4412-isp.c +++ b/drivers/clk/samsung/clk-exynos4412-isp.c @@ -8,8 +8,8 @@ #include <dt-bindings/clock/exynos4.h> #include <linux/slab.h> -#include <linux/clk.h> #include <linux/clk-provider.h> +#include <linux/mod_devicetable.h> #include <linux/of.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> diff --git a/drivers/clk/samsung/clk-exynos5-subcmu.c b/drivers/clk/samsung/clk-exynos5-subcmu.c index 373129847301..03bbde76e3ce 100644 --- a/drivers/clk/samsung/clk-exynos5-subcmu.c +++ b/drivers/clk/samsung/clk-exynos5-subcmu.c @@ -5,6 +5,7 @@ // Common Clock Framework support for Exynos5 power-domain dependent clocks #include <linux/io.h> +#include <linux/mod_devicetable.h> #include <linux/of.h> #include <linux/platform_device.h> #include <linux/pm_domain.h> diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index 47e9ac2275ee..e90d3a0848cb 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c @@ -10,6 +10,7 @@ #include <dt-bindings/clock/exynos5250.h> #include <linux/clk-provider.h> #include <linux/io.h> +#include <linux/mod_devicetable.h> #include <linux/of.h> #include <linux/of_address.h> diff --git a/drivers/clk/samsung/clk-exynos5260.c b/drivers/clk/samsung/clk-exynos5260.c index fd0520d204dc..0a5959823370 100644 --- a/drivers/clk/samsung/clk-exynos5260.c +++ b/drivers/clk/samsung/clk-exynos5260.c @@ -6,9 +6,6 @@ * Common Clock Framework support for Exynos5260 SoC. */ -#include <linux/of.h> -#include <linux/of_address.h> - #include "clk-exynos5260.h" #include "clk.h" #include "clk-pll.h" diff --git a/drivers/clk/samsung/clk-exynos5410.c b/drivers/clk/samsung/clk-exynos5410.c index 99b1bb4539fd..baa9988c7bb7 100644 --- a/drivers/clk/samsung/clk-exynos5410.c +++ b/drivers/clk/samsung/clk-exynos5410.c @@ -9,8 +9,6 @@ #include <dt-bindings/clock/exynos5410.h> #include <linux/clk-provider.h> -#include <linux/of.h> -#include <linux/of_address.h> #include <linux/clk.h> #include "clk.h" diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 333c52fda17f..a9df4e6db82f 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -10,6 +10,7 @@ #include <dt-bindings/clock/exynos5420.h> #include <linux/slab.h> #include <linux/clk-provider.h> +#include <linux/mod_devicetable.h> #include <linux/of.h> #include <linux/of_address.h> #include <linux/clk.h> diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c index 609d31a7aa52..4b2a861e7d57 100644 --- a/drivers/clk/samsung/clk-exynos5433.c +++ b/drivers/clk/samsung/clk-exynos5433.c @@ -6,10 +6,8 @@ * Common Clock Framework support for Exynos5433 SoC. */ -#include <linux/clk.h> #include <linux/clk-provider.h> -#include <linux/of.h> -#include <linux/of_address.h> +#include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> #include <linux/slab.h> diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c index e6c938effa29..fe0fa5bdbd4b 100644 --- a/drivers/clk/samsung/clk-exynos7.c +++ b/drivers/clk/samsung/clk-exynos7.c @@ -5,7 +5,6 @@ */ #include <linux/clk-provider.h> -#include <linux/of.h> #include "clk.h" #include <dt-bindings/clock/exynos7-clk.h> diff --git a/drivers/clk/samsung/clk-exynos7870.c b/drivers/clk/samsung/clk-exynos7870.c new file mode 100644 index 000000000000..b3bcf3a1d0b7 --- /dev/null +++ b/drivers/clk/samsung/clk-exynos7870.c @@ -0,0 +1,1829 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2015 Samsung Electronics Co., Ltd. + * Author: Kaustabh Chakraborty <kauschluss@disroot.org> + * + * Common Clock Framework support for Exynos7870. + */ + +#include <linux/clk-provider.h> +#include <linux/mod_devicetable.h> +#include <linux/of.h> +#include <linux/platform_device.h> + +#include <dt-bindings/clock/samsung,exynos7870-cmu.h> + +#include "clk.h" +#include "clk-exynos-arm64.h" + +/* + * Register offsets for CMU_MIF (0x10460000) + */ +#define PLL_LOCKTIME_MIF_MEM_PLL 0x0000 +#define PLL_LOCKTIME_MIF_MEDIA_PLL 0x0020 +#define PLL_LOCKTIME_MIF_BUS_PLL 0x0040 +#define PLL_CON0_MIF_MEM_PLL 0x0100 +#define PLL_CON0_MIF_MEDIA_PLL 0x0120 +#define PLL_CON0_MIF_BUS_PLL 0x0140 +#define CLK_CON_GAT_MIF_MUX_MEM_PLL 0x0200 +#define CLK_CON_GAT_MIF_MUX_MEM_PLL_CON 0x0200 +#define CLK_CON_GAT_MIF_MUX_MEDIA_PLL 0x0204 +#define CLK_CON_GAT_MIF_MUX_MEDIA_PLL_CON 0x0204 +#define CLK_CON_GAT_MIF_MUX_BUS_PLL 0x0208 +#define CLK_CON_GAT_MIF_MUX_BUS_PLL_CON 0x0208 +#define CLK_CON_GAT_MIF_MUX_BUSD 0x0220 +#define CLK_CON_MUX_MIF_BUSD 0x0220 +#define CLK_CON_GAT_MIF_MUX_CMU_ISP_VRA 0x0264 +#define CLK_CON_MUX_MIF_CMU_ISP_VRA 0x0264 +#define CLK_CON_GAT_MIF_MUX_CMU_ISP_CAM 0x0268 +#define CLK_CON_MUX_MIF_CMU_ISP_CAM 0x0268 +#define CLK_CON_GAT_MIF_MUX_CMU_ISP_ISP 0x026c +#define CLK_CON_MUX_MIF_CMU_ISP_ISP 0x026c +#define CLK_CON_GAT_MIF_MUX_CMU_DISPAUD_BUS 0x0270 +#define CLK_CON_MUX_MIF_CMU_DISPAUD_BUS 0x0270 +#define CLK_CON_GAT_MIF_MUX_CMU_DISPAUD_DECON_VCLK 0x0274 +#define CLK_CON_MUX_MIF_CMU_DISPAUD_DECON_VCLK 0x0274 +#define CLK_CON_GAT_MIF_MUX_CMU_DISPAUD_DECON_ECLK 0x0278 +#define CLK_CON_MUX_MIF_CMU_DISPAUD_DECON_ECLK 0x0278 +#define CLK_CON_GAT_MIF_MUX_CMU_MFCMSCL_MSCL 0x027c +#define CLK_CON_MUX_MIF_CMU_MFCMSCL_MSCL 0x027c +#define CLK_CON_GAT_MIF_MUX_CMU_MFCMSCL_MFC 0x0280 +#define CLK_CON_MUX_MIF_CMU_MFCMSCL_MFC 0x0280 +#define CLK_CON_GAT_MIF_MUX_CMU_FSYS_BUS 0x0284 +#define CLK_CON_MUX_MIF_CMU_FSYS_BUS 0x0284 +#define CLK_CON_GAT_MIF_MUX_CMU_FSYS_MMC0 0x0288 +#define CLK_CON_MUX_MIF_CMU_FSYS_MMC0 0x0288 +#define CLK_CON_GAT_MIF_MUX_CMU_FSYS_MMC1 0x028c +#define CLK_CON_MUX_MIF_CMU_FSYS_MMC1 0x028c +#define CLK_CON_GAT_MIF_MUX_CMU_FSYS_MMC2 0x0290 +#define CLK_CON_MUX_MIF_CMU_FSYS_MMC2 0x0290 +#define CLK_CON_GAT_MIF_MUX_CMU_FSYS_USB20DRD_REFCLK 0x029c +#define CLK_CON_MUX_MIF_CMU_FSYS_USB20DRD_REFCLK 0x029c +#define CLK_CON_GAT_MIF_MUX_CMU_PERI_BUS 0x02a0 +#define CLK_CON_MUX_MIF_CMU_PERI_BUS 0x02a0 +#define CLK_CON_GAT_MIF_MUX_CMU_PERI_UART1 0x02a4 +#define CLK_CON_MUX_MIF_CMU_PERI_UART1 0x02a4 +#define CLK_CON_GAT_MIF_MUX_CMU_PERI_UART2 0x02a8 +#define CLK_CON_MUX_MIF_CMU_PERI_UART2 0x02a8 +#define CLK_CON_GAT_MIF_MUX_CMU_PERI_UART0 0x02ac +#define CLK_CON_MUX_MIF_CMU_PERI_UART0 0x02ac +#define CLK_CON_GAT_MIF_MUX_CMU_PERI_SPI2 0x02b0 +#define CLK_CON_MUX_MIF_CMU_PERI_SPI2 0x02b0 +#define CLK_CON_GAT_MIF_MUX_CMU_PERI_SPI1 0x02b4 +#define CLK_CON_MUX_MIF_CMU_PERI_SPI1 0x02b4 +#define CLK_CON_GAT_MIF_MUX_CMU_PERI_SPI0 0x02b8 +#define CLK_CON_MUX_MIF_CMU_PERI_SPI0 0x02b8 +#define CLK_CON_GAT_MIF_MUX_CMU_PERI_SPI3 0x02bc +#define CLK_CON_MUX_MIF_CMU_PERI_SPI3 0x02bc +#define CLK_CON_GAT_MIF_MUX_CMU_PERI_SPI4 0x02c0 +#define CLK_CON_MUX_MIF_CMU_PERI_SPI4 0x02c0 +#define CLK_CON_GAT_MIF_MUX_CMU_ISP_SENSOR0 0x02c4 +#define CLK_CON_MUX_MIF_CMU_ISP_SENSOR0 0x02c4 +#define CLK_CON_GAT_MIF_MUX_CMU_ISP_SENSOR1 0x02c8 +#define CLK_CON_MUX_MIF_CMU_ISP_SENSOR1 0x02c8 +#define CLK_CON_GAT_MIF_MUX_CMU_ISP_SENSOR2 0x02cc +#define CLK_CON_MUX_MIF_CMU_ISP_SENSOR2 0x02cc +#define CLK_CON_DIV_MIF_BUSD 0x0420 +#define CLK_CON_DIV_MIF_APB 0x0424 +#define CLK_CON_DIV_MIF_HSI2C 0x0430 +#define CLK_CON_DIV_MIF_CMU_G3D_SWITCH 0x0460 +#define CLK_CON_DIV_MIF_CMU_ISP_VRA 0x0464 +#define CLK_CON_DIV_MIF_CMU_ISP_CAM 0x0468 +#define CLK_CON_DIV_MIF_CMU_ISP_ISP 0x046c +#define CLK_CON_DIV_MIF_CMU_DISPAUD_BUS 0x0470 +#define CLK_CON_DIV_MIF_CMU_DISPAUD_DECON_VCLK 0x0474 +#define CLK_CON_DIV_MIF_CMU_DISPAUD_DECON_ECLK 0x0478 +#define CLK_CON_DIV_MIF_CMU_MFCMSCL_MSCL 0x047c +#define CLK_CON_DIV_MIF_CMU_MFCMSCL_MFC 0x0480 +#define CLK_CON_DIV_MIF_CMU_FSYS_BUS 0x0484 +#define CLK_CON_DIV_MIF_CMU_FSYS_MMC0 0x0488 +#define CLK_CON_DIV_MIF_CMU_FSYS_MMC1 0x048c +#define CLK_CON_DIV_MIF_CMU_FSYS_MMC2 0x0490 +#define CLK_CON_DIV_MIF_CMU_FSYS_USB20DRD_REFCLK 0x049c +#define CLK_CON_DIV_MIF_CMU_PERI_BUS 0x04a0 +#define CLK_CON_DIV_MIF_CMU_PERI_UART1 0x04a4 +#define CLK_CON_DIV_MIF_CMU_PERI_UART2 0x04a8 +#define CLK_CON_DIV_MIF_CMU_PERI_UART0 0x04ac +#define CLK_CON_DIV_MIF_CMU_PERI_SPI2 0x04b0 +#define CLK_CON_DIV_MIF_CMU_PERI_SPI1 0x04b4 +#define CLK_CON_DIV_MIF_CMU_PERI_SPI0 0x04b8 +#define CLK_CON_DIV_MIF_CMU_PERI_SPI3 0x04bc +#define CLK_CON_DIV_MIF_CMU_PERI_SPI4 0x04c0 +#define CLK_CON_DIV_MIF_CMU_ISP_SENSOR0 0x04c4 +#define CLK_CON_DIV_MIF_CMU_ISP_SENSOR1 0x04c8 +#define CLK_CON_DIV_MIF_CMU_ISP_SENSOR2 0x04cc +#define CLK_CON_GAT_MIF_WRAP_ADC_IF_OSC_SYS 0x080c +#define CLK_CON_GAT_MIF_HSI2C_AP_PCLKS 0x0828 +#define CLK_CON_GAT_MIF_HSI2C_CP_PCLKS 0x0828 +#define CLK_CON_GAT_MIF_WRAP_ADC_IF_PCLK_S0 0x0828 +#define CLK_CON_GAT_MIF_WRAP_ADC_IF_PCLK_S1 0x0828 +#define CLK_CON_GAT_MIF_HSI2C_AP_PCLKM 0x0840 +#define CLK_CON_GAT_MIF_HSI2C_CP_PCLKM 0x0840 +#define CLK_CON_GAT_MIF_HSI2C_IPCLK 0x0840 +#define CLK_CON_GAT_MIF_HSI2C_ITCLK 0x0840 +#define CLK_CON_GAT_MIF_CP_PCLK_HSI2C 0x0840 +#define CLK_CON_GAT_MIF_CP_PCLK_HSI2C_BAT_0 0x0840 +#define CLK_CON_GAT_MIF_CP_PCLK_HSI2C_BAT_1 0x0840 +#define CLK_CON_GAT_MIF_CMU_G3D_SWITCH 0x0860 +#define CLK_CON_GAT_MIF_CMU_ISP_VRA 0x0864 +#define CLK_CON_GAT_MIF_CMU_ISP_CAM 0x0868 +#define CLK_CON_GAT_MIF_CMU_ISP_ISP 0x086c +#define CLK_CON_GAT_MIF_CMU_DISPAUD_BUS 0x0870 +#define CLK_CON_GAT_MIF_CMU_DISPAUD_DECON_VCLK 0x0874 +#define CLK_CON_GAT_MIF_CMU_DISPAUD_DECON_ECLK 0x0878 +#define CLK_CON_GAT_MIF_CMU_MFCMSCL_MSCL 0x087c +#define CLK_CON_GAT_MIF_CMU_MFCMSCL_MFC 0x0880 +#define CLK_CON_GAT_MIF_CMU_FSYS_BUS 0x0884 +#define CLK_CON_GAT_MIF_CMU_FSYS_MMC0 0x0888 +#define CLK_CON_GAT_MIF_CMU_FSYS_MMC1 0x088c +#define CLK_CON_GAT_MIF_CMU_FSYS_MMC2 0x0890 +#define CLK_CON_GAT_MIF_CMU_FSYS_USB20DRD_REFCLK 0x089c +#define CLK_CON_GAT_MIF_CMU_PERI_BUS 0x08a0 +#define CLK_CON_GAT_MIF_CMU_PERI_UART1 0x08a4 +#define CLK_CON_GAT_MIF_CMU_PERI_UART2 0x08a8 +#define CLK_CON_GAT_MIF_CMU_PERI_UART0 0x08ac +#define CLK_CON_GAT_MIF_CMU_PERI_SPI2 0x08b0 +#define CLK_CON_GAT_MIF_CMU_PERI_SPI1 0x08b4 +#define CLK_CON_GAT_MIF_CMU_PERI_SPI0 0x08b8 +#define CLK_CON_GAT_MIF_CMU_PERI_SPI3 0x08bc +#define CLK_CON_GAT_MIF_CMU_PERI_SPI4 0x08c0 +#define CLK_CON_GAT_MIF_CMU_ISP_SENSOR0 0x08c4 +#define CLK_CON_GAT_MIF_CMU_ISP_SENSOR1 0x08c8 +#define CLK_CON_GAT_MIF_CMU_ISP_SENSOR2 0x08cc + +static const unsigned long mif_clk_regs[] __initconst = { + PLL_LOCKTIME_MIF_MEM_PLL, + PLL_LOCKTIME_MIF_MEDIA_PLL, + PLL_LOCKTIME_MIF_BUS_PLL, + PLL_CON0_MIF_MEM_PLL, + PLL_CON0_MIF_MEDIA_PLL, + PLL_CON0_MIF_BUS_PLL, + CLK_CON_GAT_MIF_MUX_MEM_PLL, + CLK_CON_GAT_MIF_MUX_MEM_PLL_CON, + CLK_CON_GAT_MIF_MUX_MEDIA_PLL, + CLK_CON_GAT_MIF_MUX_MEDIA_PLL_CON, + CLK_CON_GAT_MIF_MUX_BUS_PLL, + CLK_CON_GAT_MIF_MUX_BUS_PLL_CON, + CLK_CON_GAT_MIF_MUX_BUSD, + CLK_CON_MUX_MIF_BUSD, + CLK_CON_GAT_MIF_MUX_CMU_ISP_VRA, + CLK_CON_MUX_MIF_CMU_ISP_VRA, + CLK_CON_GAT_MIF_MUX_CMU_ISP_CAM, + CLK_CON_MUX_MIF_CMU_ISP_CAM, + CLK_CON_GAT_MIF_MUX_CMU_ISP_ISP, + CLK_CON_MUX_MIF_CMU_ISP_ISP, + CLK_CON_GAT_MIF_MUX_CMU_DISPAUD_BUS, + CLK_CON_MUX_MIF_CMU_DISPAUD_BUS, + CLK_CON_GAT_MIF_MUX_CMU_DISPAUD_DECON_VCLK, + CLK_CON_MUX_MIF_CMU_DISPAUD_DECON_VCLK, + CLK_CON_GAT_MIF_MUX_CMU_DISPAUD_DECON_ECLK, + CLK_CON_MUX_MIF_CMU_DISPAUD_DECON_ECLK, + CLK_CON_GAT_MIF_MUX_CMU_MFCMSCL_MSCL, + CLK_CON_MUX_MIF_CMU_MFCMSCL_MSCL, + CLK_CON_GAT_MIF_MUX_CMU_MFCMSCL_MFC, + CLK_CON_MUX_MIF_CMU_MFCMSCL_MFC, + CLK_CON_GAT_MIF_MUX_CMU_FSYS_BUS, + CLK_CON_MUX_MIF_CMU_FSYS_BUS, + CLK_CON_GAT_MIF_MUX_CMU_FSYS_MMC0, + CLK_CON_MUX_MIF_CMU_FSYS_MMC0, + CLK_CON_GAT_MIF_MUX_CMU_FSYS_MMC1, + CLK_CON_MUX_MIF_CMU_FSYS_MMC1, + CLK_CON_GAT_MIF_MUX_CMU_FSYS_MMC2, + CLK_CON_MUX_MIF_CMU_FSYS_MMC2, + CLK_CON_GAT_MIF_MUX_CMU_FSYS_USB20DRD_REFCLK, + CLK_CON_MUX_MIF_CMU_FSYS_USB20DRD_REFCLK, + CLK_CON_GAT_MIF_MUX_CMU_PERI_BUS, + CLK_CON_MUX_MIF_CMU_PERI_BUS, + CLK_CON_GAT_MIF_MUX_CMU_PERI_UART1, + CLK_CON_MUX_MIF_CMU_PERI_UART1, + CLK_CON_GAT_MIF_MUX_CMU_PERI_UART2, + CLK_CON_MUX_MIF_CMU_PERI_UART2, + CLK_CON_GAT_MIF_MUX_CMU_PERI_UART0, + CLK_CON_MUX_MIF_CMU_PERI_UART0, + CLK_CON_GAT_MIF_MUX_CMU_PERI_SPI2, + CLK_CON_MUX_MIF_CMU_PERI_SPI2, + CLK_CON_GAT_MIF_MUX_CMU_PERI_SPI1, + CLK_CON_MUX_MIF_CMU_PERI_SPI1, + CLK_CON_GAT_MIF_MUX_CMU_PERI_SPI0, + CLK_CON_MUX_MIF_CMU_PERI_SPI0, + CLK_CON_GAT_MIF_MUX_CMU_PERI_SPI3, + CLK_CON_MUX_MIF_CMU_PERI_SPI3, + CLK_CON_GAT_MIF_MUX_CMU_PERI_SPI4, + CLK_CON_MUX_MIF_CMU_PERI_SPI4, + CLK_CON_GAT_MIF_MUX_CMU_ISP_SENSOR0, + CLK_CON_MUX_MIF_CMU_ISP_SENSOR0, + CLK_CON_GAT_MIF_MUX_CMU_ISP_SENSOR1, + CLK_CON_MUX_MIF_CMU_ISP_SENSOR1, + CLK_CON_GAT_MIF_MUX_CMU_ISP_SENSOR2, + CLK_CON_MUX_MIF_CMU_ISP_SENSOR2, + CLK_CON_DIV_MIF_BUSD, + CLK_CON_DIV_MIF_APB, + CLK_CON_DIV_MIF_HSI2C, + CLK_CON_DIV_MIF_CMU_G3D_SWITCH, + CLK_CON_DIV_MIF_CMU_ISP_VRA, + CLK_CON_DIV_MIF_CMU_ISP_CAM, + CLK_CON_DIV_MIF_CMU_ISP_ISP, + CLK_CON_DIV_MIF_CMU_DISPAUD_BUS, + CLK_CON_DIV_MIF_CMU_DISPAUD_DECON_VCLK, + CLK_CON_DIV_MIF_CMU_DISPAUD_DECON_ECLK, + CLK_CON_DIV_MIF_CMU_MFCMSCL_MSCL, + CLK_CON_DIV_MIF_CMU_MFCMSCL_MFC, + CLK_CON_DIV_MIF_CMU_FSYS_BUS, + CLK_CON_DIV_MIF_CMU_FSYS_MMC0, + CLK_CON_DIV_MIF_CMU_FSYS_MMC1, + CLK_CON_DIV_MIF_CMU_FSYS_MMC2, + CLK_CON_DIV_MIF_CMU_FSYS_USB20DRD_REFCLK, + CLK_CON_DIV_MIF_CMU_PERI_BUS, + CLK_CON_DIV_MIF_CMU_PERI_UART1, + CLK_CON_DIV_MIF_CMU_PERI_UART2, + CLK_CON_DIV_MIF_CMU_PERI_UART0, + CLK_CON_DIV_MIF_CMU_PERI_SPI2, + CLK_CON_DIV_MIF_CMU_PERI_SPI1, + CLK_CON_DIV_MIF_CMU_PERI_SPI0, + CLK_CON_DIV_MIF_CMU_PERI_SPI3, + CLK_CON_DIV_MIF_CMU_PERI_SPI4, + CLK_CON_DIV_MIF_CMU_ISP_SENSOR0, + CLK_CON_DIV_MIF_CMU_ISP_SENSOR1, + CLK_CON_DIV_MIF_CMU_ISP_SENSOR2, + CLK_CON_GAT_MIF_WRAP_ADC_IF_OSC_SYS, + CLK_CON_GAT_MIF_HSI2C_AP_PCLKS, + CLK_CON_GAT_MIF_HSI2C_CP_PCLKS, + CLK_CON_GAT_MIF_WRAP_ADC_IF_PCLK_S0, + CLK_CON_GAT_MIF_WRAP_ADC_IF_PCLK_S1, + CLK_CON_GAT_MIF_HSI2C_AP_PCLKM, + CLK_CON_GAT_MIF_HSI2C_CP_PCLKM, + CLK_CON_GAT_MIF_HSI2C_IPCLK, + CLK_CON_GAT_MIF_HSI2C_ITCLK, + CLK_CON_GAT_MIF_CP_PCLK_HSI2C, + CLK_CON_GAT_MIF_CP_PCLK_HSI2C_BAT_0, + CLK_CON_GAT_MIF_CP_PCLK_HSI2C_BAT_1, + CLK_CON_GAT_MIF_CMU_G3D_SWITCH, + CLK_CON_GAT_MIF_CMU_ISP_VRA, + CLK_CON_GAT_MIF_CMU_ISP_CAM, + CLK_CON_GAT_MIF_CMU_ISP_ISP, + CLK_CON_GAT_MIF_CMU_DISPAUD_BUS, + CLK_CON_GAT_MIF_CMU_DISPAUD_DECON_VCLK, + CLK_CON_GAT_MIF_CMU_DISPAUD_DECON_ECLK, + CLK_CON_GAT_MIF_CMU_MFCMSCL_MSCL, + CLK_CON_GAT_MIF_CMU_MFCMSCL_MFC, + CLK_CON_GAT_MIF_CMU_FSYS_BUS, + CLK_CON_GAT_MIF_CMU_FSYS_MMC0, + CLK_CON_GAT_MIF_CMU_FSYS_MMC1, + CLK_CON_GAT_MIF_CMU_FSYS_MMC2, + CLK_CON_GAT_MIF_CMU_FSYS_USB20DRD_REFCLK, + CLK_CON_GAT_MIF_CMU_PERI_BUS, + CLK_CON_GAT_MIF_CMU_PERI_UART1, + CLK_CON_GAT_MIF_CMU_PERI_UART2, + CLK_CON_GAT_MIF_CMU_PERI_UART0, + CLK_CON_GAT_MIF_CMU_PERI_SPI2, + CLK_CON_GAT_MIF_CMU_PERI_SPI1, + CLK_CON_GAT_MIF_CMU_PERI_SPI0, + CLK_CON_GAT_MIF_CMU_PERI_SPI3, + CLK_CON_GAT_MIF_CMU_PERI_SPI4, + CLK_CON_GAT_MIF_CMU_ISP_SENSOR0, + CLK_CON_GAT_MIF_CMU_ISP_SENSOR1, + CLK_CON_GAT_MIF_CMU_ISP_SENSOR2, +}; + +static const struct samsung_fixed_factor_clock mif_fixed_factor_clks[] __initconst = { + FFACTOR(0, "ffac_mif_mux_bus_pll_div2", "gout_mif_mux_bus_pll_con", 1, 2, + 0), + FFACTOR(0, "ffac_mif_mux_media_pll_div2", "gout_mif_mux_media_pll_con", + 1, 2, 0), + FFACTOR(0, "ffac_mif_mux_mem_pll_div2", "gout_mif_mux_mem_pll_con", 1, 2, + 0), +}; + +static const struct samsung_pll_clock mif_pll_clks[] __initconst = { + PLL(pll_1417x, CLK_FOUT_MIF_BUS_PLL, "fout_mif_bus_pll", "oscclk", + PLL_LOCKTIME_MIF_BUS_PLL, PLL_CON0_MIF_BUS_PLL, NULL), + PLL(pll_1417x, CLK_FOUT_MIF_MEDIA_PLL, "fout_mif_media_pll", "oscclk", + PLL_LOCKTIME_MIF_MEDIA_PLL, PLL_CON0_MIF_MEDIA_PLL, NULL), + PLL(pll_1417x, CLK_FOUT_MIF_MEM_PLL, "fout_mif_mem_pll", "oscclk", + PLL_LOCKTIME_MIF_MEM_PLL, PLL_CON0_MIF_MEM_PLL, NULL), +}; + +/* List of parent clocks for muxes in CMU_MIF */ +PNAME(mout_mif_cmu_dispaud_bus_p) = { "ffac_mif_mux_bus_pll_div2", + "ffac_mif_mux_media_pll_div2" }; +PNAME(mout_mif_cmu_dispaud_decon_eclk_p) = { "ffac_mif_mux_bus_pll_div2", + "ffac_mif_mux_media_pll_div2" }; +PNAME(mout_mif_cmu_dispaud_decon_vclk_p) = { "ffac_mif_mux_bus_pll_div2", + "ffac_mif_mux_media_pll_div2" }; +PNAME(mout_mif_cmu_fsys_bus_p) = { "ffac_mif_mux_bus_pll_div2", + "ffac_mif_mux_media_pll_div2" }; +PNAME(mout_mif_cmu_fsys_mmc0_p) = { "ffac_mif_mux_bus_pll_div2", + "ffac_mif_mux_media_pll_div2" }; +PNAME(mout_mif_cmu_fsys_mmc1_p) = { "ffac_mif_mux_bus_pll_div2", + "ffac_mif_mux_media_pll_div2" }; +PNAME(mout_mif_cmu_fsys_mmc2_p) = { "ffac_mif_mux_bus_pll_div2", + "ffac_mif_mux_media_pll_div2" }; +PNAME(mout_mif_cmu_fsys_usb20drd_refclk_p) = { "ffac_mif_mux_bus_pll_div2", + "ffac_mif_mux_media_pll_div2" }; +PNAME(mout_mif_cmu_isp_cam_p) = { "ffac_mif_mux_bus_pll_div2", + "ffac_mif_mux_media_pll_div2" }; +PNAME(mout_mif_cmu_isp_isp_p) = { "ffac_mif_mux_bus_pll_div2", + "ffac_mif_mux_media_pll_div2" }; +PNAME(mout_mif_cmu_isp_sensor0_p) = { "ffac_mif_mux_bus_pll_div2", + "oscclk" }; +PNAME(mout_mif_cmu_isp_sensor1_p) = { "ffac_mif_mux_bus_pll_div2", + "oscclk" }; +PNAME(mout_mif_cmu_isp_sensor2_p) = { "ffac_mif_mux_bus_pll_div2", + "oscclk" }; +PNAME(mout_mif_cmu_isp_vra_p) = { "ffac_mif_mux_bus_pll_div2", + "ffac_mif_mux_media_pll_div2", + "gout_mif_mux_bus_pll_con" }; +PNAME(mout_mif_cmu_mfcmscl_mfc_p) = { "ffac_mif_mux_bus_pll_div2", + "ffac_mif_mux_media_pll_div2", + "gout_mif_mux_bus_pll_con" }; +PNAME(mout_mif_cmu_mfcmscl_mscl_p) = { "ffac_mif_mux_bus_pll_div2", + "ffac_mif_mux_media_pll_div2", + "gout_mif_mux_bus_pll_con" }; +PNAME(mout_mif_cmu_peri_bus_p) = { "ffac_mif_mux_bus_pll_div2", + "ffac_mif_mux_media_pll_div2" }; +PNAME(mout_mif_cmu_peri_spi0_p) = { "ffac_mif_mux_bus_pll_div2", + "oscclk" }; +PNAME(mout_mif_cmu_peri_spi2_p) = { "ffac_mif_mux_bus_pll_div2", + "oscclk" }; +PNAME(mout_mif_cmu_peri_spi1_p) = { "ffac_mif_mux_bus_pll_div2", + "oscclk" }; +PNAME(mout_mif_cmu_peri_spi4_p) = { "ffac_mif_mux_bus_pll_div2", + "oscclk" }; +PNAME(mout_mif_cmu_peri_spi3_p) = { "ffac_mif_mux_bus_pll_div2", + "oscclk" }; +PNAME(mout_mif_cmu_peri_uart1_p) = { "ffac_mif_mux_bus_pll_div2", + "ffac_mif_mux_media_pll_div2" }; +PNAME(mout_mif_cmu_peri_uart2_p) = { "ffac_mif_mux_bus_pll_div2", + "ffac_mif_mux_media_pll_div2" }; +PNAME(mout_mif_cmu_peri_uart0_p) = { "ffac_mif_mux_bus_pll_div2", + "ffac_mif_mux_media_pll_div2" }; +PNAME(mout_mif_busd_p) = { "ffac_mif_mux_bus_pll_div2", + "ffac_mif_mux_media_pll_div2", + "ffac_mif_mux_mem_pll_div2" }; + +static const struct samsung_mux_clock mif_mux_clks[] __initconst = { + MUX(CLK_MOUT_MIF_CMU_DISPAUD_BUS, "mout_mif_cmu_dispaud_bus", + mout_mif_cmu_dispaud_bus_p, CLK_CON_MUX_MIF_CMU_DISPAUD_BUS, 12, 1), + MUX(CLK_MOUT_MIF_CMU_DISPAUD_DECON_ECLK, + "mout_mif_cmu_dispaud_decon_eclk", + mout_mif_cmu_dispaud_decon_eclk_p, + CLK_CON_MUX_MIF_CMU_DISPAUD_DECON_ECLK, 12, 1), + MUX(CLK_MOUT_MIF_CMU_DISPAUD_DECON_VCLK, + "mout_mif_cmu_dispaud_decon_vclk", + mout_mif_cmu_dispaud_decon_vclk_p, + CLK_CON_MUX_MIF_CMU_DISPAUD_DECON_VCLK, 12, 1), + MUX(CLK_MOUT_MIF_CMU_FSYS_BUS, "mout_mif_cmu_fsys_bus", + mout_mif_cmu_fsys_bus_p, CLK_CON_MUX_MIF_CMU_FSYS_BUS, 12, 1), + MUX(CLK_MOUT_MIF_CMU_FSYS_MMC0, "mout_mif_cmu_fsys_mmc0", + mout_mif_cmu_fsys_mmc0_p, CLK_CON_MUX_MIF_CMU_FSYS_MMC0, 12, 1), + MUX(CLK_MOUT_MIF_CMU_FSYS_MMC1, "mout_mif_cmu_fsys_mmc1", + mout_mif_cmu_fsys_mmc1_p, CLK_CON_MUX_MIF_CMU_FSYS_MMC1, 12, 1), + MUX(CLK_MOUT_MIF_CMU_FSYS_MMC2, "mout_mif_cmu_fsys_mmc2", + mout_mif_cmu_fsys_mmc2_p, CLK_CON_MUX_MIF_CMU_FSYS_MMC2, 12, 1), + MUX(CLK_MOUT_MIF_CMU_FSYS_USB20DRD_REFCLK, + "mout_mif_cmu_fsys_usb20drd_refclk", + mout_mif_cmu_fsys_usb20drd_refclk_p, + CLK_CON_MUX_MIF_CMU_FSYS_USB20DRD_REFCLK, 12, 1), + MUX(CLK_MOUT_MIF_CMU_ISP_CAM, "mout_mif_cmu_isp_cam", + mout_mif_cmu_isp_cam_p, CLK_CON_MUX_MIF_CMU_ISP_CAM, 12, 1), + MUX(CLK_MOUT_MIF_CMU_ISP_ISP, "mout_mif_cmu_isp_isp", + mout_mif_cmu_isp_isp_p, CLK_CON_MUX_MIF_CMU_ISP_ISP, 12, 1), + MUX(CLK_MOUT_MIF_CMU_ISP_SENSOR0, "mout_mif_cmu_isp_sensor0", + mout_mif_cmu_isp_sensor0_p, CLK_CON_MUX_MIF_CMU_ISP_SENSOR0, 12, 1), + MUX(CLK_MOUT_MIF_CMU_ISP_SENSOR1, "mout_mif_cmu_isp_sensor1", + mout_mif_cmu_isp_sensor1_p, CLK_CON_MUX_MIF_CMU_ISP_SENSOR1, 12, 1), + MUX(CLK_MOUT_MIF_CMU_ISP_SENSOR2, "mout_mif_cmu_isp_sensor2", + mout_mif_cmu_isp_sensor2_p, CLK_CON_MUX_MIF_CMU_ISP_SENSOR2, 12, 1), + MUX(CLK_MOUT_MIF_CMU_ISP_VRA, "mout_mif_cmu_isp_vra", + mout_mif_cmu_isp_vra_p, CLK_CON_MUX_MIF_CMU_ISP_VRA, 12, 2), + MUX(CLK_MOUT_MIF_CMU_MFCMSCL_MFC, "mout_mif_cmu_mfcmscl_mfc", + mout_mif_cmu_mfcmscl_mfc_p, CLK_CON_MUX_MIF_CMU_MFCMSCL_MFC, 12, 2), + MUX(CLK_MOUT_MIF_CMU_MFCMSCL_MSCL, "mout_mif_cmu_mfcmscl_mscl", + mout_mif_cmu_mfcmscl_mscl_p, CLK_CON_MUX_MIF_CMU_MFCMSCL_MSCL, 12, + 2), + MUX(CLK_MOUT_MIF_CMU_PERI_BUS, "mout_mif_cmu_peri_bus", + mout_mif_cmu_peri_bus_p, CLK_CON_MUX_MIF_CMU_PERI_BUS, 12, 1), + MUX(CLK_MOUT_MIF_CMU_PERI_SPI0, "mout_mif_cmu_peri_spi0", + mout_mif_cmu_peri_spi0_p, CLK_CON_MUX_MIF_CMU_PERI_SPI0, 12, 1), + MUX(CLK_MOUT_MIF_CMU_PERI_SPI2, "mout_mif_cmu_peri_spi2", + mout_mif_cmu_peri_spi2_p, CLK_CON_MUX_MIF_CMU_PERI_SPI2, 12, 1), + MUX(CLK_MOUT_MIF_CMU_PERI_SPI1, "mout_mif_cmu_peri_spi1", + mout_mif_cmu_peri_spi1_p, CLK_CON_MUX_MIF_CMU_PERI_SPI1, 12, 1), + MUX(CLK_MOUT_MIF_CMU_PERI_SPI4, "mout_mif_cmu_peri_spi4", + mout_mif_cmu_peri_spi4_p, CLK_CON_MUX_MIF_CMU_PERI_SPI4, 12, 1), + MUX(CLK_MOUT_MIF_CMU_PERI_SPI3, "mout_mif_cmu_peri_spi3", + mout_mif_cmu_peri_spi3_p, CLK_CON_MUX_MIF_CMU_PERI_SPI3, 12, 1), + MUX(CLK_MOUT_MIF_CMU_PERI_UART1, "mout_mif_cmu_peri_uart1", + mout_mif_cmu_peri_uart1_p, CLK_CON_MUX_MIF_CMU_PERI_UART1, 12, 1), + MUX(CLK_MOUT_MIF_CMU_PERI_UART2, "mout_mif_cmu_peri_uart2", + mout_mif_cmu_peri_uart2_p, CLK_CON_MUX_MIF_CMU_PERI_UART2, 12, 1), + MUX(CLK_MOUT_MIF_CMU_PERI_UART0, "mout_mif_cmu_peri_uart0", + mout_mif_cmu_peri_uart0_p, CLK_CON_MUX_MIF_CMU_PERI_UART0, 12, 1), + MUX(CLK_MOUT_MIF_BUSD, "mout_mif_busd", mout_mif_busd_p, + CLK_CON_MUX_MIF_BUSD, 12, 2), +}; + +static const struct samsung_div_clock mif_div_clks[] __initconst = { + DIV(CLK_DOUT_MIF_CMU_DISPAUD_BUS, "dout_mif_cmu_dispaud_bus", + "gout_mif_mux_cmu_dispaud_bus", CLK_CON_DIV_MIF_CMU_DISPAUD_BUS, 0, + 4), + DIV(CLK_DOUT_MIF_CMU_DISPAUD_DECON_ECLK, + "dout_mif_cmu_dispaud_decon_eclk", + "gout_mif_mux_cmu_dispaud_decon_eclk", + CLK_CON_DIV_MIF_CMU_DISPAUD_DECON_ECLK, 0, 4), + DIV(CLK_DOUT_MIF_CMU_DISPAUD_DECON_VCLK, + "dout_mif_cmu_dispaud_decon_vclk", + "gout_mif_mux_cmu_dispaud_decon_vclk", + CLK_CON_DIV_MIF_CMU_DISPAUD_DECON_VCLK, 0, 4), + DIV(CLK_DOUT_MIF_CMU_FSYS_BUS, "dout_mif_cmu_fsys_bus", + "gout_mif_mux_cmu_fsys_bus", CLK_CON_DIV_MIF_CMU_FSYS_BUS, 0, 4), + DIV(CLK_DOUT_MIF_CMU_FSYS_MMC0, "dout_mif_cmu_fsys_mmc0", + "gout_mif_mux_cmu_fsys_mmc0", CLK_CON_DIV_MIF_CMU_FSYS_MMC0, 0, 10), + DIV(CLK_DOUT_MIF_CMU_FSYS_MMC1, "dout_mif_cmu_fsys_mmc1", + "gout_mif_mux_cmu_fsys_mmc1", CLK_CON_DIV_MIF_CMU_FSYS_MMC1, 0, 10), + DIV(CLK_DOUT_MIF_CMU_FSYS_MMC2, "dout_mif_cmu_fsys_mmc2", + "gout_mif_mux_cmu_fsys_mmc2", CLK_CON_DIV_MIF_CMU_FSYS_MMC2, 0, 10), + DIV(CLK_DOUT_MIF_CMU_FSYS_USB20DRD_REFCLK, + "dout_mif_cmu_fsys_usb20drd_refclk", + "gout_mif_mux_cmu_fsys_usb20drd_refclk", + CLK_CON_DIV_MIF_CMU_FSYS_USB20DRD_REFCLK, 0, 4), + DIV(CLK_DOUT_MIF_CMU_G3D_SWITCH, "dout_mif_cmu_g3d_switch", + "ffac_mif_mux_bus_pll_div2", CLK_CON_DIV_MIF_CMU_G3D_SWITCH, 0, 2), + DIV(CLK_DOUT_MIF_CMU_ISP_CAM, "dout_mif_cmu_isp_cam", + "gout_mif_mux_cmu_isp_cam", CLK_CON_DIV_MIF_CMU_ISP_CAM, 0, 4), + DIV(CLK_DOUT_MIF_CMU_ISP_ISP, "dout_mif_cmu_isp_isp", + "gout_mif_mux_cmu_isp_isp", CLK_CON_DIV_MIF_CMU_ISP_ISP, 0, 4), + DIV(CLK_DOUT_MIF_CMU_ISP_SENSOR0, "dout_mif_cmu_isp_sensor0", + "gout_mif_mux_cmu_isp_sensor0", CLK_CON_DIV_MIF_CMU_ISP_SENSOR0, 0, + 6), + DIV(CLK_DOUT_MIF_CMU_ISP_SENSOR1, "dout_mif_cmu_isp_sensor1", + "gout_mif_mux_cmu_isp_sensor1", CLK_CON_DIV_MIF_CMU_ISP_SENSOR1, 0, + 6), + DIV(CLK_DOUT_MIF_CMU_ISP_SENSOR2, "dout_mif_cmu_isp_sensor2", + "gout_mif_mux_cmu_isp_sensor2", CLK_CON_DIV_MIF_CMU_ISP_SENSOR2, 0, + 6), + DIV(CLK_DOUT_MIF_CMU_ISP_VRA, "dout_mif_cmu_isp_vra", + "gout_mif_mux_cmu_isp_vra", CLK_CON_DIV_MIF_CMU_ISP_VRA, 0, 4), + DIV(CLK_DOUT_MIF_CMU_MFCMSCL_MFC, "dout_mif_cmu_mfcmscl_mfc", + "gout_mif_mux_cmu_mfcmscl_mfc", CLK_CON_DIV_MIF_CMU_MFCMSCL_MFC, 0, + 4), + DIV(CLK_DOUT_MIF_CMU_MFCMSCL_MSCL, "dout_mif_cmu_mfcmscl_mscl", + "gout_mif_mux_cmu_mfcmscl_mscl", CLK_CON_DIV_MIF_CMU_MFCMSCL_MSCL, + 0, 4), + DIV(CLK_DOUT_MIF_CMU_PERI_BUS, "dout_mif_cmu_peri_bus", + "gout_mif_mux_cmu_peri_bus", CLK_CON_DIV_MIF_CMU_PERI_BUS, 0, 4), + DIV(CLK_DOUT_MIF_CMU_PERI_SPI0, "dout_mif_cmu_peri_spi0", + "gout_mif_mux_cmu_peri_spi0", CLK_CON_DIV_MIF_CMU_PERI_SPI0, 0, 6), + DIV(CLK_DOUT_MIF_CMU_PERI_SPI2, "dout_mif_cmu_peri_spi2", + "gout_mif_mux_cmu_peri_spi2", CLK_CON_DIV_MIF_CMU_PERI_SPI2, 0, 6), + DIV(CLK_DOUT_MIF_CMU_PERI_SPI1, "dout_mif_cmu_peri_spi1", + "gout_mif_mux_cmu_peri_spi1", CLK_CON_DIV_MIF_CMU_PERI_SPI1, 0, 6), + DIV(CLK_DOUT_MIF_CMU_PERI_SPI4, "dout_mif_cmu_peri_spi4", + "gout_mif_mux_cmu_peri_spi4", CLK_CON_DIV_MIF_CMU_PERI_SPI4, 0, 6), + DIV(CLK_DOUT_MIF_CMU_PERI_SPI3, "dout_mif_cmu_peri_spi3", + "gout_mif_mux_cmu_peri_spi3", CLK_CON_DIV_MIF_CMU_PERI_SPI3, 0, 6), + DIV(CLK_DOUT_MIF_CMU_PERI_UART1, "dout_mif_cmu_peri_uart1", + "gout_mif_mux_cmu_peri_uart1", CLK_CON_DIV_MIF_CMU_PERI_UART1, 0, 4), + DIV(CLK_DOUT_MIF_CMU_PERI_UART2, "dout_mif_cmu_peri_uart2", + "gout_mif_mux_cmu_peri_uart2", CLK_CON_DIV_MIF_CMU_PERI_UART2, 0, 4), + DIV(CLK_DOUT_MIF_CMU_PERI_UART0, "dout_mif_cmu_peri_uart0", + "gout_mif_mux_cmu_peri_uart0", CLK_CON_DIV_MIF_CMU_PERI_UART0, 0, 4), + DIV(CLK_DOUT_MIF_APB, "dout_mif_apb", "dout_mif_busd", + CLK_CON_DIV_MIF_APB, 0, 2), + DIV(CLK_DOUT_MIF_BUSD, "dout_mif_busd", "gout_mif_mux_busd", + CLK_CON_DIV_MIF_BUSD, 0, 4), + DIV(CLK_DOUT_MIF_HSI2C, "dout_mif_hsi2c", "ffac_mif_mux_media_pll_div2", + CLK_CON_DIV_MIF_HSI2C, 0, 4), +}; + +static const struct samsung_gate_clock mif_gate_clks[] __initconst = { + GATE(CLK_GOUT_MIF_CMU_DISPAUD_BUS, "gout_mif_cmu_dispaud_bus", + "dout_mif_cmu_dispaud_bus", CLK_CON_GAT_MIF_CMU_DISPAUD_BUS, 0, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MIF_CMU_DISPAUD_DECON_ECLK, + "gout_mif_cmu_dispaud_decon_eclk", + "dout_mif_cmu_dispaud_decon_eclk", + CLK_CON_GAT_MIF_CMU_DISPAUD_DECON_ECLK, 0, CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MIF_CMU_DISPAUD_DECON_VCLK, + "gout_mif_cmu_dispaud_decon_vclk", + "dout_mif_cmu_dispaud_decon_vclk", + CLK_CON_GAT_MIF_CMU_DISPAUD_DECON_VCLK, 0, CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MIF_CMU_FSYS_BUS, "gout_mif_cmu_fsys_bus", + "dout_mif_cmu_fsys_bus", CLK_CON_GAT_MIF_CMU_FSYS_BUS, 0, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MIF_CMU_FSYS_MMC0, "gout_mif_cmu_fsys_mmc0", + "dout_mif_cmu_fsys_mmc0", CLK_CON_GAT_MIF_CMU_FSYS_MMC0, 0, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MIF_CMU_FSYS_MMC1, "gout_mif_cmu_fsys_mmc1", + "dout_mif_cmu_fsys_mmc1", CLK_CON_GAT_MIF_CMU_FSYS_MMC1, 0, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MIF_CMU_FSYS_MMC2, "gout_mif_cmu_fsys_mmc2", + "dout_mif_cmu_fsys_mmc2", CLK_CON_GAT_MIF_CMU_FSYS_MMC2, 0, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MIF_CMU_FSYS_USB20DRD_REFCLK, + "gout_mif_cmu_fsys_usb20drd_refclk", + "dout_mif_cmu_fsys_usb20drd_refclk", + CLK_CON_GAT_MIF_CMU_FSYS_USB20DRD_REFCLK, 0, CLK_SET_RATE_PARENT, + 0), + GATE(CLK_GOUT_MIF_CMU_G3D_SWITCH, "gout_mif_cmu_g3d_switch", + "dout_mif_cmu_g3d_switch", CLK_CON_GAT_MIF_CMU_G3D_SWITCH, 0, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MIF_CMU_ISP_CAM, "gout_mif_cmu_isp_cam", + "dout_mif_cmu_isp_cam", CLK_CON_GAT_MIF_CMU_ISP_CAM, 0, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MIF_CMU_ISP_ISP, "gout_mif_cmu_isp_isp", + "dout_mif_cmu_isp_isp", CLK_CON_GAT_MIF_CMU_ISP_ISP, 0, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MIF_CMU_ISP_SENSOR0, "gout_mif_cmu_isp_sensor0", + "dout_mif_cmu_isp_sensor0", CLK_CON_GAT_MIF_CMU_ISP_SENSOR0, 0, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MIF_CMU_ISP_SENSOR1, "gout_mif_cmu_isp_sensor1", + "dout_mif_cmu_isp_sensor1", CLK_CON_GAT_MIF_CMU_ISP_SENSOR1, 0, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MIF_CMU_ISP_SENSOR2, "gout_mif_cmu_isp_sensor2", + "dout_mif_cmu_isp_sensor2", CLK_CON_GAT_MIF_CMU_ISP_SENSOR2, 0, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MIF_CMU_ISP_VRA, "gout_mif_cmu_isp_vra", + "dout_mif_cmu_isp_vra", CLK_CON_GAT_MIF_CMU_ISP_VRA, 0, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MIF_CMU_MFCMSCL_MFC, "gout_mif_cmu_mfcmscl_mfc", + "dout_mif_cmu_mfcmscl_mfc", CLK_CON_GAT_MIF_CMU_MFCMSCL_MFC, 0, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MIF_CMU_MFCMSCL_MSCL, "gout_mif_cmu_mfcmscl_mscl", + "dout_mif_cmu_mfcmscl_mscl", CLK_CON_GAT_MIF_CMU_MFCMSCL_MSCL, 0, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MIF_CMU_PERI_BUS, "gout_mif_cmu_peri_bus", + "dout_mif_cmu_peri_bus", CLK_CON_GAT_MIF_CMU_PERI_BUS, 0, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MIF_CMU_PERI_SPI0, "gout_mif_cmu_peri_spi0", + "dout_mif_cmu_peri_spi0", CLK_CON_GAT_MIF_CMU_PERI_SPI0, 0, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MIF_CMU_PERI_SPI2, "gout_mif_cmu_peri_spi2", + "dout_mif_cmu_peri_spi2", CLK_CON_GAT_MIF_CMU_PERI_SPI2, 0, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MIF_CMU_PERI_SPI1, "gout_mif_cmu_peri_spi1", + "dout_mif_cmu_peri_spi1", CLK_CON_GAT_MIF_CMU_PERI_SPI1, 0, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MIF_CMU_PERI_SPI4, "gout_mif_cmu_peri_spi4", + "dout_mif_cmu_peri_spi4", CLK_CON_GAT_MIF_CMU_PERI_SPI4, 0, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MIF_CMU_PERI_SPI3, "gout_mif_cmu_peri_spi3", + "dout_mif_cmu_peri_spi3", CLK_CON_GAT_MIF_CMU_PERI_SPI3, 0, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MIF_CMU_PERI_UART1, "gout_mif_cmu_peri_uart1", + "dout_mif_cmu_peri_uart1", CLK_CON_GAT_MIF_CMU_PERI_UART1, 0, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MIF_CMU_PERI_UART2, "gout_mif_cmu_peri_uart2", + "dout_mif_cmu_peri_uart2", CLK_CON_GAT_MIF_CMU_PERI_UART2, 0, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MIF_CMU_PERI_UART0, "gout_mif_cmu_peri_uart0", + "dout_mif_cmu_peri_uart0", CLK_CON_GAT_MIF_CMU_PERI_UART0, 0, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MIF_HSI2C_AP_PCLKM, "gout_mif_hsi2c_ap_pclkm", + "dout_mif_hsi2c", CLK_CON_GAT_MIF_HSI2C_AP_PCLKM, 0, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MIF_HSI2C_AP_PCLKS, "gout_mif_hsi2c_ap_pclks", + "dout_mif_apb", CLK_CON_GAT_MIF_HSI2C_AP_PCLKS, 14, CLK_IS_CRITICAL + | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MIF_HSI2C_CP_PCLKM, "gout_mif_hsi2c_cp_pclkm", + "dout_mif_hsi2c", CLK_CON_GAT_MIF_HSI2C_CP_PCLKM, 1, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MIF_HSI2C_CP_PCLKS, "gout_mif_hsi2c_cp_pclks", + "dout_mif_apb", CLK_CON_GAT_MIF_HSI2C_CP_PCLKS, 15, CLK_IS_CRITICAL + | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MIF_HSI2C_IPCLK, "gout_mif_hsi2c_ipclk", "dout_mif_hsi2c", + CLK_CON_GAT_MIF_HSI2C_IPCLK, 2, CLK_IS_CRITICAL | + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MIF_HSI2C_ITCLK, "gout_mif_hsi2c_itclk", "dout_mif_hsi2c", + CLK_CON_GAT_MIF_HSI2C_ITCLK, 3, CLK_IS_CRITICAL | + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MIF_CP_PCLK_HSI2C, "gout_mif_cp_pclk_hsi2c", + "dout_mif_hsi2c", CLK_CON_GAT_MIF_CP_PCLK_HSI2C, 6, CLK_IS_CRITICAL + | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MIF_CP_PCLK_HSI2C_BAT_0, "gout_mif_cp_pclk_hsi2c_bat_0", + "dout_mif_hsi2c", CLK_CON_GAT_MIF_CP_PCLK_HSI2C_BAT_0, 4, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MIF_CP_PCLK_HSI2C_BAT_1, "gout_mif_cp_pclk_hsi2c_bat_1", + "dout_mif_hsi2c", CLK_CON_GAT_MIF_CP_PCLK_HSI2C_BAT_1, 5, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MIF_WRAP_ADC_IF_OSC_SYS, "gout_mif_wrap_adc_if_osc_sys", + "oscclk", CLK_CON_GAT_MIF_WRAP_ADC_IF_OSC_SYS, 3, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MIF_WRAP_ADC_IF_PCLK_S0, "gout_mif_wrap_adc_if_pclk_s0", + "dout_mif_apb", CLK_CON_GAT_MIF_WRAP_ADC_IF_PCLK_S0, 20, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MIF_WRAP_ADC_IF_PCLK_S1, "gout_mif_wrap_adc_if_pclk_s1", + "dout_mif_apb", CLK_CON_GAT_MIF_WRAP_ADC_IF_PCLK_S1, 21, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MIF_MUX_BUS_PLL, "gout_mif_mux_bus_pll", + "gout_mif_mux_bus_pll_con", CLK_CON_GAT_MIF_MUX_BUS_PLL, 21, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MIF_MUX_BUS_PLL_CON, "gout_mif_mux_bus_pll_con", + "fout_mif_bus_pll", CLK_CON_GAT_MIF_MUX_BUS_PLL_CON, 12, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MIF_MUX_CMU_DISPAUD_BUS, "gout_mif_mux_cmu_dispaud_bus", + "mout_mif_cmu_dispaud_bus", CLK_CON_GAT_MIF_MUX_CMU_DISPAUD_BUS, + 21, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MIF_MUX_CMU_DISPAUD_DECON_ECLK, + "gout_mif_mux_cmu_dispaud_decon_eclk", + "mout_mif_cmu_dispaud_decon_eclk", + CLK_CON_GAT_MIF_MUX_CMU_DISPAUD_DECON_ECLK, 21, CLK_IS_CRITICAL | + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MIF_MUX_CMU_DISPAUD_DECON_VCLK, + "gout_mif_mux_cmu_dispaud_decon_vclk", + "mout_mif_cmu_dispaud_decon_vclk", + CLK_CON_GAT_MIF_MUX_CMU_DISPAUD_DECON_VCLK, 21, CLK_IS_CRITICAL | + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MIF_MUX_CMU_FSYS_BUS, "gout_mif_mux_cmu_fsys_bus", + "mout_mif_cmu_fsys_bus", CLK_CON_GAT_MIF_MUX_CMU_FSYS_BUS, 21, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MIF_MUX_CMU_FSYS_MMC0, "gout_mif_mux_cmu_fsys_mmc0", + "mout_mif_cmu_fsys_mmc0", CLK_CON_GAT_MIF_MUX_CMU_FSYS_MMC0, 21, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MIF_MUX_CMU_FSYS_MMC1, "gout_mif_mux_cmu_fsys_mmc1", + "mout_mif_cmu_fsys_mmc1", CLK_CON_GAT_MIF_MUX_CMU_FSYS_MMC1, 21, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MIF_MUX_CMU_FSYS_MMC2, "gout_mif_mux_cmu_fsys_mmc2", + "mout_mif_cmu_fsys_mmc2", CLK_CON_GAT_MIF_MUX_CMU_FSYS_MMC2, 21, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MIF_MUX_CMU_FSYS_USB20DRD_REFCLK, + "gout_mif_mux_cmu_fsys_usb20drd_refclk", + "mout_mif_cmu_fsys_usb20drd_refclk", + CLK_CON_GAT_MIF_MUX_CMU_FSYS_USB20DRD_REFCLK, 21, CLK_IS_CRITICAL | + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MIF_MUX_CMU_ISP_CAM, "gout_mif_mux_cmu_isp_cam", + "mout_mif_cmu_isp_cam", CLK_CON_GAT_MIF_MUX_CMU_ISP_CAM, 21, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MIF_MUX_CMU_ISP_ISP, "gout_mif_mux_cmu_isp_isp", + "mout_mif_cmu_isp_isp", CLK_CON_GAT_MIF_MUX_CMU_ISP_ISP, 21, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MIF_MUX_CMU_ISP_SENSOR0, "gout_mif_mux_cmu_isp_sensor0", + "mout_mif_cmu_isp_sensor0", CLK_CON_GAT_MIF_MUX_CMU_ISP_SENSOR0, + 21, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MIF_MUX_CMU_ISP_SENSOR1, "gout_mif_mux_cmu_isp_sensor1", + "mout_mif_cmu_isp_sensor1", CLK_CON_GAT_MIF_MUX_CMU_ISP_SENSOR1, + 21, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MIF_MUX_CMU_ISP_SENSOR2, "gout_mif_mux_cmu_isp_sensor2", + "mout_mif_cmu_isp_sensor2", CLK_CON_GAT_MIF_MUX_CMU_ISP_SENSOR2, + 21, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MIF_MUX_CMU_ISP_VRA, "gout_mif_mux_cmu_isp_vra", + "mout_mif_cmu_isp_vra", CLK_CON_GAT_MIF_MUX_CMU_ISP_VRA, 21, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MIF_MUX_CMU_MFCMSCL_MFC, "gout_mif_mux_cmu_mfcmscl_mfc", + "mout_mif_cmu_mfcmscl_mfc", CLK_CON_GAT_MIF_MUX_CMU_MFCMSCL_MFC, + 21, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MIF_MUX_CMU_MFCMSCL_MSCL, "gout_mif_mux_cmu_mfcmscl_mscl", + "mout_mif_cmu_mfcmscl_mscl", CLK_CON_GAT_MIF_MUX_CMU_MFCMSCL_MSCL, + 21, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MIF_MUX_CMU_PERI_BUS, "gout_mif_mux_cmu_peri_bus", + "mout_mif_cmu_peri_bus", CLK_CON_GAT_MIF_MUX_CMU_PERI_BUS, 21, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MIF_MUX_CMU_PERI_SPI0, "gout_mif_mux_cmu_peri_spi0", + "mout_mif_cmu_peri_spi0", CLK_CON_GAT_MIF_MUX_CMU_PERI_SPI0, 21, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MIF_MUX_CMU_PERI_SPI2, "gout_mif_mux_cmu_peri_spi2", + "mout_mif_cmu_peri_spi2", CLK_CON_GAT_MIF_MUX_CMU_PERI_SPI2, 21, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MIF_MUX_CMU_PERI_SPI1, "gout_mif_mux_cmu_peri_spi1", + "mout_mif_cmu_peri_spi1", CLK_CON_GAT_MIF_MUX_CMU_PERI_SPI1, 21, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MIF_MUX_CMU_PERI_SPI4, "gout_mif_mux_cmu_peri_spi4", + "mout_mif_cmu_peri_spi4", CLK_CON_GAT_MIF_MUX_CMU_PERI_SPI4, 21, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MIF_MUX_CMU_PERI_SPI3, "gout_mif_mux_cmu_peri_spi3", + "mout_mif_cmu_peri_spi3", CLK_CON_GAT_MIF_MUX_CMU_PERI_SPI3, 21, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MIF_MUX_CMU_PERI_UART1, "gout_mif_mux_cmu_peri_uart1", + "mout_mif_cmu_peri_uart1", CLK_CON_GAT_MIF_MUX_CMU_PERI_UART1, 21, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MIF_MUX_CMU_PERI_UART2, "gout_mif_mux_cmu_peri_uart2", + "mout_mif_cmu_peri_uart2", CLK_CON_GAT_MIF_MUX_CMU_PERI_UART2, 21, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MIF_MUX_CMU_PERI_UART0, "gout_mif_mux_cmu_peri_uart0", + "mout_mif_cmu_peri_uart0", CLK_CON_GAT_MIF_MUX_CMU_PERI_UART0, 21, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MIF_MUX_BUSD, "gout_mif_mux_busd", "mout_mif_busd", + CLK_CON_GAT_MIF_MUX_BUSD, 21, CLK_IS_CRITICAL | + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MIF_MUX_MEDIA_PLL, "gout_mif_mux_media_pll", + "gout_mif_mux_media_pll_con", CLK_CON_GAT_MIF_MUX_MEDIA_PLL, 21, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MIF_MUX_MEDIA_PLL_CON, "gout_mif_mux_media_pll_con", + "fout_mif_media_pll", CLK_CON_GAT_MIF_MUX_MEDIA_PLL_CON, 12, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MIF_MUX_MEM_PLL, "gout_mif_mux_mem_pll", + "gout_mif_mux_mem_pll_con", CLK_CON_GAT_MIF_MUX_MEM_PLL, 21, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MIF_MUX_MEM_PLL_CON, "gout_mif_mux_mem_pll_con", + "fout_mif_mem_pll", CLK_CON_GAT_MIF_MUX_MEM_PLL_CON, 12, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), +}; + +static const struct samsung_cmu_info mif_cmu_info __initconst = { + .fixed_factor_clks = mif_fixed_factor_clks, + .nr_fixed_factor_clks = ARRAY_SIZE(mif_fixed_factor_clks), + .pll_clks = mif_pll_clks, + .nr_pll_clks = ARRAY_SIZE(mif_pll_clks), + .mux_clks = mif_mux_clks, + .nr_mux_clks = ARRAY_SIZE(mif_mux_clks), + .div_clks = mif_div_clks, + .nr_div_clks = ARRAY_SIZE(mif_div_clks), + .gate_clks = mif_gate_clks, + .nr_gate_clks = ARRAY_SIZE(mif_gate_clks), + .clk_regs = mif_clk_regs, + .nr_clk_regs = ARRAY_SIZE(mif_clk_regs), + .nr_clk_ids = MIF_NR_CLK, +}; + +/* + * Register offsets for CMU_DISPAUD (0x148d0000) + */ +#define PLL_LOCKTIME_DISPAUD_PLL 0x0000 +#define PLL_LOCKTIME_DISPAUD_AUD_PLL 0x00c0 +#define PLL_CON0_DISPAUD_PLL 0x0100 +#define PLL_CON0_DISPAUD_AUD_PLL 0x01c0 +#define CLK_CON_GAT_DISPAUD_MUX_PLL 0x0200 +#define CLK_CON_GAT_DISPAUD_MUX_PLL_CON 0x0200 +#define CLK_CON_GAT_DISPAUD_MUX_AUD_PLL 0x0204 +#define CLK_CON_GAT_DISPAUD_MUX_AUD_PLL_CON 0x0204 +#define CLK_CON_GAT_DISPAUD_MUX_BUS_USER 0x0210 +#define CLK_CON_MUX_DISPAUD_BUS_USER 0x0210 +#define CLK_CON_GAT_DISPAUD_MUX_DECON_VCLK_USER 0x0214 +#define CLK_CON_MUX_DISPAUD_DECON_VCLK_USER 0x0214 +#define CLK_CON_GAT_DISPAUD_MUX_DECON_ECLK_USER 0x0218 +#define CLK_CON_MUX_DISPAUD_DECON_ECLK_USER 0x0218 +#define CLK_CON_GAT_DISPAUD_MUX_DECON_VCLK 0x021c +#define CLK_CON_MUX_DISPAUD_DECON_VCLK 0x021c +#define CLK_CON_GAT_DISPAUD_MUX_DECON_ECLK 0x0220 +#define CLK_CON_MUX_DISPAUD_DECON_ECLK 0x0220 +#define CLK_CON_GAT_DISPAUD_MUX_MIPIPHY_TXBYTECLKHS_USER 0x0224 +#define CLK_CON_GAT_DISPAUD_MUX_MIPIPHY_TXBYTECLKHS_USER_CON 0x0224 +#define CLK_CON_GAT_DISPAUD_MUX_MIPIPHY_RXCLKESC0_USER 0x0228 +#define CLK_CON_GAT_DISPAUD_MUX_MIPIPHY_RXCLKESC0_USER_CON 0x0228 +#define CLK_CON_GAT_DISPAUD_MUX_MI2S 0x022c +#define CLK_CON_MUX_DISPAUD_MI2S 0x022c +#define CLK_CON_DIV_DISPAUD_APB 0x0400 +#define CLK_CON_DIV_DISPAUD_DECON_VCLK 0x0404 +#define CLK_CON_DIV_DISPAUD_DECON_ECLK 0x0408 +#define CLK_CON_DIV_DISPAUD_MI2S 0x040c +#define CLK_CON_DIV_DISPAUD_MIXER 0x0410 +#define CLK_CON_GAT_DISPAUD_BUS 0x0810 +#define CLK_CON_GAT_DISPAUD_BUS_DISP 0x0810 +#define CLK_CON_GAT_DISPAUD_BUS_PPMU 0x0810 +#define CLK_CON_GAT_DISPAUD_APB_AUD 0x0814 +#define CLK_CON_GAT_DISPAUD_APB_AUD_AMP 0x0814 +#define CLK_CON_GAT_DISPAUD_APB_DISP 0x0814 +#define CLK_CON_GAT_DISPAUD_DECON_VCLK 0x081c +#define CLK_CON_GAT_DISPAUD_DECON_ECLK 0x0820 +#define CLK_CON_GAT_DISPAUD_MI2S_AMP_I2SCODCLKI 0x082c +#define CLK_CON_GAT_DISPAUD_MI2S_AUD_I2SCODCLKI 0x082c +#define CLK_CON_GAT_DISPAUD_MIXER_AUD_SYSCLK 0x0830 +#define CLK_CON_GAT_DISPAUD_CON_EXT2AUD_BCK_GPIO_I2S 0x0834 +#define CLK_CON_GAT_DISPAUD_CON_AUD_I2S_BCLK_BT_IN 0x0838 +#define CLK_CON_GAT_DISPAUD_CON_CP2AUD_BCK 0x083c +#define CLK_CON_GAT_DISPAUD_CON_AUD_I2S_BCLK_FM_IN 0x0840 + +static const unsigned long dispaud_clk_regs[] __initconst = { + PLL_LOCKTIME_DISPAUD_PLL, + PLL_LOCKTIME_DISPAUD_AUD_PLL, + PLL_CON0_DISPAUD_PLL, + PLL_CON0_DISPAUD_AUD_PLL, + CLK_CON_GAT_DISPAUD_MUX_PLL, + CLK_CON_GAT_DISPAUD_MUX_PLL_CON, + CLK_CON_GAT_DISPAUD_MUX_AUD_PLL, + CLK_CON_GAT_DISPAUD_MUX_AUD_PLL_CON, + CLK_CON_GAT_DISPAUD_MUX_BUS_USER, + CLK_CON_MUX_DISPAUD_BUS_USER, + CLK_CON_GAT_DISPAUD_MUX_DECON_VCLK_USER, + CLK_CON_MUX_DISPAUD_DECON_VCLK_USER, + CLK_CON_GAT_DISPAUD_MUX_DECON_ECLK_USER, + CLK_CON_MUX_DISPAUD_DECON_ECLK_USER, + CLK_CON_GAT_DISPAUD_MUX_DECON_VCLK, + CLK_CON_MUX_DISPAUD_DECON_VCLK, + CLK_CON_GAT_DISPAUD_MUX_DECON_ECLK, + CLK_CON_MUX_DISPAUD_DECON_ECLK, + CLK_CON_GAT_DISPAUD_MUX_MIPIPHY_TXBYTECLKHS_USER, + CLK_CON_GAT_DISPAUD_MUX_MIPIPHY_TXBYTECLKHS_USER_CON, + CLK_CON_GAT_DISPAUD_MUX_MIPIPHY_RXCLKESC0_USER, + CLK_CON_GAT_DISPAUD_MUX_MIPIPHY_RXCLKESC0_USER_CON, + CLK_CON_GAT_DISPAUD_MUX_MI2S, + CLK_CON_MUX_DISPAUD_MI2S, + CLK_CON_DIV_DISPAUD_APB, + CLK_CON_DIV_DISPAUD_DECON_VCLK, + CLK_CON_DIV_DISPAUD_DECON_ECLK, + CLK_CON_DIV_DISPAUD_MI2S, + CLK_CON_DIV_DISPAUD_MIXER, + CLK_CON_GAT_DISPAUD_BUS, + CLK_CON_GAT_DISPAUD_BUS_DISP, + CLK_CON_GAT_DISPAUD_BUS_PPMU, + CLK_CON_GAT_DISPAUD_APB_AUD, + CLK_CON_GAT_DISPAUD_APB_AUD_AMP, + CLK_CON_GAT_DISPAUD_APB_DISP, + CLK_CON_GAT_DISPAUD_DECON_VCLK, + CLK_CON_GAT_DISPAUD_DECON_ECLK, + CLK_CON_GAT_DISPAUD_MI2S_AMP_I2SCODCLKI, + CLK_CON_GAT_DISPAUD_MI2S_AUD_I2SCODCLKI, + CLK_CON_GAT_DISPAUD_MIXER_AUD_SYSCLK, + CLK_CON_GAT_DISPAUD_CON_EXT2AUD_BCK_GPIO_I2S, + CLK_CON_GAT_DISPAUD_CON_AUD_I2S_BCLK_BT_IN, + CLK_CON_GAT_DISPAUD_CON_CP2AUD_BCK, + CLK_CON_GAT_DISPAUD_CON_AUD_I2S_BCLK_FM_IN, +}; + +static const struct samsung_fixed_rate_clock dispaud_fixed_clks[] __initconst = { + FRATE(0, "frat_dispaud_audiocdclk0", NULL, 0, 100000000), + FRATE(0, "frat_dispaud_mixer_bclk_bt", NULL, 0, 12500000), + FRATE(0, "frat_dispaud_mixer_bclk_cp", NULL, 0, 12500000), + FRATE(0, "frat_dispaud_mixer_bclk_fm", NULL, 0, 12500000), + FRATE(0, "frat_dispaud_mixer_sclk_ap", NULL, 0, 12500000), + FRATE(0, "frat_dispaud_mipiphy_rxclkesc0", NULL, 0, 188000000), + FRATE(0, "frat_dispaud_mipiphy_txbyteclkhs", NULL, 0, 188000000), +}; + +static const struct samsung_pll_clock dispaud_pll_clks[] __initconst = { + PLL(pll_1417x, CLK_FOUT_DISPAUD_AUD_PLL, "fout_dispaud_aud_pll", + "oscclk", PLL_LOCKTIME_DISPAUD_AUD_PLL, PLL_CON0_DISPAUD_AUD_PLL, + NULL), + PLL(pll_1417x, CLK_FOUT_DISPAUD_PLL, "fout_dispaud_pll", "oscclk", + PLL_LOCKTIME_DISPAUD_PLL, PLL_CON0_DISPAUD_PLL, NULL), +}; + +/* List of parent clocks for muxes in CMU_DISPAUD */ +PNAME(mout_dispaud_bus_user_p) = { "oscclk", "gout_mif_cmu_dispaud_bus" }; +PNAME(mout_dispaud_decon_eclk_user_p) = { "oscclk", + "gout_mif_cmu_dispaud_decon_eclk" }; +PNAME(mout_dispaud_decon_vclk_user_p) = { "oscclk", + "gout_mif_cmu_dispaud_decon_vclk" }; +PNAME(mout_dispaud_decon_eclk_p) = { "gout_dispaud_mux_decon_eclk_user", + "gout_dispaud_mux_pll_con" }; +PNAME(mout_dispaud_decon_vclk_p) = { "gout_dispaud_mux_decon_vclk_user", + "gout_dispaud_mux_pll_con" }; +PNAME(mout_dispaud_mi2s_p) = { "gout_dispaud_mux_aud_pll_con", + "frat_dispaud_audiocdclk0" }; + +static const struct samsung_mux_clock dispaud_mux_clks[] __initconst = { + MUX(CLK_MOUT_DISPAUD_BUS_USER, "mout_dispaud_bus_user", + mout_dispaud_bus_user_p, CLK_CON_MUX_DISPAUD_BUS_USER, 12, 1), + MUX(CLK_MOUT_DISPAUD_DECON_ECLK_USER, "mout_dispaud_decon_eclk_user", + mout_dispaud_decon_eclk_user_p, CLK_CON_MUX_DISPAUD_DECON_ECLK_USER, + 12, 1), + MUX(CLK_MOUT_DISPAUD_DECON_VCLK_USER, "mout_dispaud_decon_vclk_user", + mout_dispaud_decon_vclk_user_p, CLK_CON_MUX_DISPAUD_DECON_VCLK_USER, + 12, 1), + MUX(CLK_MOUT_DISPAUD_DECON_ECLK, "mout_dispaud_decon_eclk", + mout_dispaud_decon_eclk_p, CLK_CON_MUX_DISPAUD_DECON_ECLK, 12, 1), + MUX(CLK_MOUT_DISPAUD_DECON_VCLK, "mout_dispaud_decon_vclk", + mout_dispaud_decon_vclk_p, CLK_CON_MUX_DISPAUD_DECON_VCLK, 12, 1), + MUX(CLK_MOUT_DISPAUD_MI2S, "mout_dispaud_mi2s", mout_dispaud_mi2s_p, + CLK_CON_MUX_DISPAUD_MI2S, 12, 1), +}; + +static const struct samsung_div_clock dispaud_div_clks[] __initconst = { + DIV(CLK_DOUT_DISPAUD_APB, "dout_dispaud_apb", + "gout_dispaud_mux_bus_user", CLK_CON_DIV_DISPAUD_APB, 0, 2), + DIV(CLK_DOUT_DISPAUD_DECON_ECLK, "dout_dispaud_decon_eclk", + "gout_dispaud_mux_decon_eclk", CLK_CON_DIV_DISPAUD_DECON_ECLK, 0, 3), + DIV(CLK_DOUT_DISPAUD_DECON_VCLK, "dout_dispaud_decon_vclk", + "gout_dispaud_mux_decon_vclk", CLK_CON_DIV_DISPAUD_DECON_VCLK, 0, 3), + DIV(CLK_DOUT_DISPAUD_MI2S, "dout_dispaud_mi2s", "gout_dispaud_mux_mi2s", + CLK_CON_DIV_DISPAUD_MI2S, 0, 4), + DIV(CLK_DOUT_DISPAUD_MIXER, "dout_dispaud_mixer", + "gout_dispaud_mux_aud_pll_con", CLK_CON_DIV_DISPAUD_MIXER, 0, 4), +}; + +static const struct samsung_gate_clock dispaud_gate_clks[] __initconst = { + GATE(CLK_GOUT_DISPAUD_BUS, "gout_dispaud_bus", + "gout_dispaud_mux_bus_user", CLK_CON_GAT_DISPAUD_BUS, 0, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_DISPAUD_BUS_DISP, "gout_dispaud_bus_disp", + "gout_dispaud_mux_bus_user", CLK_CON_GAT_DISPAUD_BUS_DISP, 2, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_DISPAUD_BUS_PPMU, "gout_dispaud_bus_ppmu", + "gout_dispaud_mux_bus_user", CLK_CON_GAT_DISPAUD_BUS_PPMU, 3, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_DISPAUD_APB_AUD, "gout_dispaud_apb_aud", + "dout_dispaud_apb", CLK_CON_GAT_DISPAUD_APB_AUD, 2, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_DISPAUD_APB_AUD_AMP, "gout_dispaud_apb_aud_amp", + "dout_dispaud_apb", CLK_CON_GAT_DISPAUD_APB_AUD_AMP, 3, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_DISPAUD_APB_DISP, "gout_dispaud_apb_disp", + "dout_dispaud_apb", CLK_CON_GAT_DISPAUD_APB_DISP, 1, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_DISPAUD_CON_AUD_I2S_BCLK_BT_IN, + "gout_dispaud_con_aud_i2s_bclk_bt_in", + "frat_dispaud_mixer_bclk_bt", + CLK_CON_GAT_DISPAUD_CON_AUD_I2S_BCLK_BT_IN, 0, CLK_SET_RATE_PARENT, + 0), + GATE(CLK_GOUT_DISPAUD_CON_AUD_I2S_BCLK_FM_IN, + "gout_dispaud_con_aud_i2s_bclk_fm_in", + "frat_dispaud_mixer_bclk_fm", + CLK_CON_GAT_DISPAUD_CON_AUD_I2S_BCLK_FM_IN, 0, CLK_SET_RATE_PARENT, + 0), + GATE(CLK_GOUT_DISPAUD_CON_CP2AUD_BCK, "gout_dispaud_con_cp2aud_bck", + "frat_dispaud_mixer_bclk_cp", CLK_CON_GAT_DISPAUD_CON_CP2AUD_BCK, + 0, CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_DISPAUD_CON_EXT2AUD_BCK_GPIO_I2S, + "gout_dispaud_con_ext2aud_bck_gpio_i2s", + "frat_dispaud_mixer_sclk_ap", + CLK_CON_GAT_DISPAUD_CON_EXT2AUD_BCK_GPIO_I2S, 0, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_DISPAUD_DECON_ECLK, "gout_dispaud_decon_eclk", + "dout_dispaud_decon_eclk", CLK_CON_GAT_DISPAUD_DECON_ECLK, 0, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_DISPAUD_DECON_VCLK, "gout_dispaud_decon_vclk", + "dout_dispaud_decon_vclk", CLK_CON_GAT_DISPAUD_DECON_VCLK, 0, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_DISPAUD_MI2S_AMP_I2SCODCLKI, + "gout_dispaud_mi2s_amp_i2scodclki", "dout_dispaud_mi2s", + CLK_CON_GAT_DISPAUD_MI2S_AMP_I2SCODCLKI, 1, CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_DISPAUD_MI2S_AUD_I2SCODCLKI, + "gout_dispaud_mi2s_aud_i2scodclki", "dout_dispaud_mi2s", + CLK_CON_GAT_DISPAUD_MI2S_AUD_I2SCODCLKI, 0, CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_DISPAUD_MIXER_AUD_SYSCLK, "gout_dispaud_mixer_aud_sysclk", + "dout_dispaud_mixer", CLK_CON_GAT_DISPAUD_MIXER_AUD_SYSCLK, 0, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_DISPAUD_MUX_AUD_PLL, "gout_dispaud_mux_aud_pll", + "gout_dispaud_mux_aud_pll_con", CLK_CON_GAT_DISPAUD_MUX_AUD_PLL, + 21, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_DISPAUD_MUX_AUD_PLL_CON, "gout_dispaud_mux_aud_pll_con", + "fout_dispaud_aud_pll", CLK_CON_GAT_DISPAUD_MUX_AUD_PLL_CON, 12, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_DISPAUD_MUX_BUS_USER, "gout_dispaud_mux_bus_user", + "mout_dispaud_bus_user", CLK_CON_GAT_DISPAUD_MUX_BUS_USER, 21, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_DISPAUD_MUX_DECON_ECLK_USER, + "gout_dispaud_mux_decon_eclk_user", "mout_dispaud_decon_eclk_user", + CLK_CON_GAT_DISPAUD_MUX_DECON_ECLK_USER, 21, CLK_IS_CRITICAL | + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_DISPAUD_MUX_DECON_VCLK_USER, + "gout_dispaud_mux_decon_vclk_user", "mout_dispaud_decon_vclk_user", + CLK_CON_GAT_DISPAUD_MUX_DECON_VCLK_USER, 21, CLK_IS_CRITICAL | + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_DISPAUD_MUX_MIPIPHY_RXCLKESC0_USER, + "gout_dispaud_mux_mipiphy_rxclkesc0_user", + "gout_dispaud_mux_mipiphy_rxclkesc0_user_con", + CLK_CON_GAT_DISPAUD_MUX_MIPIPHY_RXCLKESC0_USER, 21, CLK_IS_CRITICAL + | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_DISPAUD_MUX_MIPIPHY_RXCLKESC0_USER_CON, + "gout_dispaud_mux_mipiphy_rxclkesc0_user_con", + "frat_dispaud_mipiphy_rxclkesc0", + CLK_CON_GAT_DISPAUD_MUX_MIPIPHY_RXCLKESC0_USER_CON, 12, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_DISPAUD_MUX_MIPIPHY_TXBYTECLKHS_USER, + "gout_dispaud_mux_mipiphy_txbyteclkhs_user", + "gout_dispaud_mux_mipiphy_txbyteclkhs_user_con", + CLK_CON_GAT_DISPAUD_MUX_MIPIPHY_TXBYTECLKHS_USER, 21, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_DISPAUD_MUX_MIPIPHY_TXBYTECLKHS_USER_CON, + "gout_dispaud_mux_mipiphy_txbyteclkhs_user_con", + "frat_dispaud_mipiphy_txbyteclkhs", + CLK_CON_GAT_DISPAUD_MUX_MIPIPHY_TXBYTECLKHS_USER_CON, 12, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_DISPAUD_MUX_DECON_ECLK, "gout_dispaud_mux_decon_eclk", + "mout_dispaud_decon_eclk", CLK_CON_GAT_DISPAUD_MUX_DECON_ECLK, 21, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_DISPAUD_MUX_DECON_VCLK, "gout_dispaud_mux_decon_vclk", + "mout_dispaud_decon_vclk", CLK_CON_GAT_DISPAUD_MUX_DECON_VCLK, 21, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_DISPAUD_MUX_MI2S, "gout_dispaud_mux_mi2s", + "mout_dispaud_mi2s", CLK_CON_GAT_DISPAUD_MUX_MI2S, 21, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_DISPAUD_MUX_PLL, "gout_dispaud_mux_pll", + "gout_dispaud_mux_pll_con", CLK_CON_GAT_DISPAUD_MUX_PLL, 21, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_DISPAUD_MUX_PLL_CON, "gout_dispaud_mux_pll_con", + "fout_dispaud_pll", CLK_CON_GAT_DISPAUD_MUX_PLL_CON, 12, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), +}; + +static const struct samsung_cmu_info dispaud_cmu_info __initconst = { + .fixed_clks = dispaud_fixed_clks, + .nr_fixed_clks = ARRAY_SIZE(dispaud_fixed_clks), + .pll_clks = dispaud_pll_clks, + .nr_pll_clks = ARRAY_SIZE(dispaud_pll_clks), + .mux_clks = dispaud_mux_clks, + .nr_mux_clks = ARRAY_SIZE(dispaud_mux_clks), + .div_clks = dispaud_div_clks, + .nr_div_clks = ARRAY_SIZE(dispaud_div_clks), + .gate_clks = dispaud_gate_clks, + .nr_gate_clks = ARRAY_SIZE(dispaud_gate_clks), + .clk_regs = dispaud_clk_regs, + .nr_clk_regs = ARRAY_SIZE(dispaud_clk_regs), + .nr_clk_ids = DISPAUD_NR_CLK, +}; + +/* + * Register offsets for CMU_FSYS (0x13730000) + */ +#define PLL_LOCKTIME_FSYS_USB_PLL 0x0000 +#define PLL_CON0_FSYS_USB_PLL 0x0100 +#define CLK_CON_GAT_FSYS_MUX_USB_PLL 0x0200 +#define CLK_CON_GAT_FSYS_MUX_USB_PLL_CON 0x0200 +#define CLK_CON_GAT_FSYS_MUX_USB20DRD_PHYCLOCK_USER 0x0230 +#define CLK_CON_GAT_FSYS_MUX_USB20DRD_PHYCLOCK_USER_CON 0x0230 +#define CLK_CON_GAT_FSYS_BUSP3_HCLK 0x0804 +#define CLK_CON_GAT_FSYS_MMC0_ACLK 0x0804 +#define CLK_CON_GAT_FSYS_MMC1_ACLK 0x0804 +#define CLK_CON_GAT_FSYS_MMC2_ACLK 0x0804 +#define CLK_CON_GAT_FSYS_PDMA0_ACLK_PDMA0 0x0804 +#define CLK_CON_GAT_FSYS_PPMU_ACLK 0x0804 +#define CLK_CON_GAT_FSYS_PPMU_PCLK 0x0804 +#define CLK_CON_GAT_FSYS_SROMC_HCLK 0x0804 +#define CLK_CON_GAT_FSYS_UPSIZER_BUS1_ACLK 0x0804 +#define CLK_CON_GAT_FSYS_USB20DRD_ACLK_HSDRD 0x0804 +#define CLK_CON_GAT_FSYS_USB20DRD_HCLK_USB20_CTRL 0x0804 +#define CLK_CON_GAT_FSYS_USB20DRD_HSDRD_REF_CLK 0x0828 + +static const unsigned long fsys_clk_regs[] __initconst = { + PLL_LOCKTIME_FSYS_USB_PLL, + PLL_CON0_FSYS_USB_PLL, + CLK_CON_GAT_FSYS_MUX_USB_PLL, + CLK_CON_GAT_FSYS_MUX_USB_PLL_CON, + CLK_CON_GAT_FSYS_MUX_USB20DRD_PHYCLOCK_USER, + CLK_CON_GAT_FSYS_MUX_USB20DRD_PHYCLOCK_USER_CON, + CLK_CON_GAT_FSYS_BUSP3_HCLK, + CLK_CON_GAT_FSYS_MMC0_ACLK, + CLK_CON_GAT_FSYS_MMC1_ACLK, + CLK_CON_GAT_FSYS_MMC2_ACLK, + CLK_CON_GAT_FSYS_PDMA0_ACLK_PDMA0, + CLK_CON_GAT_FSYS_PPMU_ACLK, + CLK_CON_GAT_FSYS_PPMU_PCLK, + CLK_CON_GAT_FSYS_SROMC_HCLK, + CLK_CON_GAT_FSYS_UPSIZER_BUS1_ACLK, + CLK_CON_GAT_FSYS_USB20DRD_ACLK_HSDRD, + CLK_CON_GAT_FSYS_USB20DRD_HCLK_USB20_CTRL, + CLK_CON_GAT_FSYS_USB20DRD_HSDRD_REF_CLK, +}; + +static const struct samsung_fixed_rate_clock fsys_fixed_clks[] __initconst = { + FRATE(0, "frat_fsys_usb20drd_phyclock", NULL, 0, 60000000), +}; + +static const struct samsung_pll_clock fsys_pll_clks[] __initconst = { + PLL(pll_1417x, CLK_FOUT_FSYS_USB_PLL, "fout_fsys_usb_pll", "oscclk", + PLL_LOCKTIME_FSYS_USB_PLL, PLL_CON0_FSYS_USB_PLL, NULL), +}; + +static const struct samsung_gate_clock fsys_gate_clks[] __initconst = { + GATE(CLK_GOUT_FSYS_BUSP3_HCLK, "gout_fsys_busp3_hclk", + "gout_mif_cmu_fsys_bus", CLK_CON_GAT_FSYS_BUSP3_HCLK, 2, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_FSYS_MMC0_ACLK, "gout_fsys_mmc0_aclk", + "gout_fsys_busp3_hclk", CLK_CON_GAT_FSYS_MMC0_ACLK, 8, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_FSYS_MMC1_ACLK, "gout_fsys_mmc1_aclk", + "gout_fsys_busp3_hclk", CLK_CON_GAT_FSYS_MMC1_ACLK, 9, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_FSYS_MMC2_ACLK, "gout_fsys_mmc2_aclk", + "gout_fsys_busp3_hclk", CLK_CON_GAT_FSYS_MMC2_ACLK, 10, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_FSYS_PDMA0_ACLK_PDMA0, "gout_fsys_pdma0_aclk_pdma0", + "gout_fsys_upsizer_bus1_aclk", CLK_CON_GAT_FSYS_PDMA0_ACLK_PDMA0, + 7, CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_FSYS_PPMU_ACLK, "gout_fsys_ppmu_aclk", + "gout_mif_cmu_fsys_bus", CLK_CON_GAT_FSYS_PPMU_ACLK, 17, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_FSYS_PPMU_PCLK, "gout_fsys_ppmu_pclk", + "gout_mif_cmu_fsys_bus", CLK_CON_GAT_FSYS_PPMU_PCLK, 18, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_FSYS_SROMC_HCLK, "gout_fsys_sromc_hclk", + "gout_fsys_busp3_hclk", CLK_CON_GAT_FSYS_SROMC_HCLK, 6, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_FSYS_UPSIZER_BUS1_ACLK, "gout_fsys_upsizer_bus1_aclk", + "gout_mif_cmu_fsys_bus", CLK_CON_GAT_FSYS_UPSIZER_BUS1_ACLK, 12, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_FSYS_USB20DRD_ACLK_HSDRD, "gout_fsys_usb20drd_aclk_hsdrd", + "gout_fsys_busp3_hclk", CLK_CON_GAT_FSYS_USB20DRD_ACLK_HSDRD, 20, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_FSYS_USB20DRD_HCLK_USB20_CTRL, + "gout_fsys_usb20drd_hclk_usb20_ctrl", "gout_fsys_busp3_hclk", + CLK_CON_GAT_FSYS_USB20DRD_HCLK_USB20_CTRL, 21, CLK_IS_CRITICAL | + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_FSYS_USB20DRD_HSDRD_REF_CLK, + "gout_fsys_usb20drd_hsdrd_ref_clk", + "gout_mif_cmu_fsys_usb20drd_refclk", + CLK_CON_GAT_FSYS_USB20DRD_HSDRD_REF_CLK, 0, CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_FSYS_MUX_USB20DRD_PHYCLOCK_USER, + "gout_fsys_mux_usb20drd_phyclock_user", + "gout_fsys_mux_usb20drd_phyclock_user_con", + CLK_CON_GAT_FSYS_MUX_USB20DRD_PHYCLOCK_USER, 21, CLK_IS_CRITICAL | + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_FSYS_MUX_USB20DRD_PHYCLOCK_USER_CON, + "gout_fsys_mux_usb20drd_phyclock_user_con", + "frat_fsys_usb20drd_phyclock", + CLK_CON_GAT_FSYS_MUX_USB20DRD_PHYCLOCK_USER_CON, 12, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_FSYS_MUX_USB_PLL, "gout_fsys_mux_usb_pll", + "gout_fsys_mux_usb_pll_con", CLK_CON_GAT_FSYS_MUX_USB_PLL, 21, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_FSYS_MUX_USB_PLL_CON, "gout_fsys_mux_usb_pll_con", + "fout_fsys_usb_pll", CLK_CON_GAT_FSYS_MUX_USB_PLL_CON, 12, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), +}; + +static const struct samsung_cmu_info fsys_cmu_info __initconst = { + .fixed_clks = fsys_fixed_clks, + .nr_fixed_clks = ARRAY_SIZE(fsys_fixed_clks), + .pll_clks = fsys_pll_clks, + .nr_pll_clks = ARRAY_SIZE(fsys_pll_clks), + .gate_clks = fsys_gate_clks, + .nr_gate_clks = ARRAY_SIZE(fsys_gate_clks), + .clk_regs = fsys_clk_regs, + .nr_clk_regs = ARRAY_SIZE(fsys_clk_regs), + .nr_clk_ids = FSYS_NR_CLK, +}; + +/* + * Register offsets for CMU_G3D (0x11460000) + */ +#define PLL_LOCKTIME_G3D_PLL 0x0000 +#define PLL_CON0_G3D_PLL 0x0100 +#define CLK_CON_GAT_G3D_MUX_PLL 0x0200 +#define CLK_CON_GAT_G3D_MUX_PLL_CON 0x0200 +#define CLK_CON_GAT_G3D_MUX_SWITCH_USER 0x0204 +#define CLK_CON_MUX_G3D_SWITCH_USER 0x0204 +#define CLK_CON_GAT_G3D_MUX 0x0208 +#define CLK_CON_MUX_G3D 0x0208 +#define CLK_CON_DIV_G3D_BUS 0x0400 +#define CLK_CON_DIV_G3D_APB 0x0404 +#define CLK_CON_GAT_G3D_ASYNCS_D0_CLK 0x0804 +#define CLK_CON_GAT_G3D_ASYNC_PCLKM 0x0804 +#define CLK_CON_GAT_G3D_CLK 0x0804 +#define CLK_CON_GAT_G3D_PPMU_ACLK 0x0804 +#define CLK_CON_GAT_G3D_QE_ACLK 0x0804 +#define CLK_CON_GAT_G3D_PPMU_PCLK 0x0808 +#define CLK_CON_GAT_G3D_QE_PCLK 0x0808 +#define CLK_CON_GAT_G3D_SYSREG_PCLK 0x0808 + +static const unsigned long g3d_clk_regs[] __initconst = { + PLL_LOCKTIME_G3D_PLL, + PLL_CON0_G3D_PLL, + CLK_CON_GAT_G3D_MUX_PLL, + CLK_CON_GAT_G3D_MUX_PLL_CON, + CLK_CON_GAT_G3D_MUX_SWITCH_USER, + CLK_CON_MUX_G3D_SWITCH_USER, + CLK_CON_GAT_G3D_MUX, + CLK_CON_MUX_G3D, + CLK_CON_DIV_G3D_BUS, + CLK_CON_DIV_G3D_APB, + CLK_CON_GAT_G3D_ASYNCS_D0_CLK, + CLK_CON_GAT_G3D_ASYNC_PCLKM, + CLK_CON_GAT_G3D_CLK, + CLK_CON_GAT_G3D_PPMU_ACLK, + CLK_CON_GAT_G3D_QE_ACLK, + CLK_CON_GAT_G3D_PPMU_PCLK, + CLK_CON_GAT_G3D_QE_PCLK, + CLK_CON_GAT_G3D_SYSREG_PCLK, +}; + +static const struct samsung_pll_clock g3d_pll_clks[] __initconst = { + PLL(pll_1417x, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "oscclk", + PLL_LOCKTIME_G3D_PLL, PLL_CON0_G3D_PLL, NULL), +}; + +/* List of parent clocks for muxes in CMU_G3D */ +PNAME(mout_g3d_switch_user_p) = { "oscclk", "gout_mif_cmu_g3d_switch" }; +PNAME(mout_g3d_p) = { "gout_g3d_mux_pll_con", + "gout_g3d_mux_switch_user" }; + +static const struct samsung_mux_clock g3d_mux_clks[] __initconst = { + MUX(CLK_MOUT_G3D_SWITCH_USER, "mout_g3d_switch_user", + mout_g3d_switch_user_p, CLK_CON_MUX_G3D_SWITCH_USER, 12, 1), + MUX(CLK_MOUT_G3D, "mout_g3d", mout_g3d_p, CLK_CON_MUX_G3D, 12, 1), +}; + +static const struct samsung_div_clock g3d_div_clks[] __initconst = { + DIV(CLK_DOUT_G3D_APB, "dout_g3d_apb", "dout_g3d_bus", + CLK_CON_DIV_G3D_APB, 0, 3), + DIV(CLK_DOUT_G3D_BUS, "dout_g3d_bus", "gout_g3d_mux", + CLK_CON_DIV_G3D_BUS, 0, 3), +}; + +static const struct samsung_gate_clock g3d_gate_clks[] __initconst = { + GATE(CLK_GOUT_G3D_ASYNCS_D0_CLK, "gout_g3d_asyncs_d0_clk", + "dout_g3d_bus", CLK_CON_GAT_G3D_ASYNCS_D0_CLK, 1, CLK_IS_CRITICAL | + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_G3D_ASYNC_PCLKM, "gout_g3d_async_pclkm", "dout_g3d_bus", + CLK_CON_GAT_G3D_ASYNC_PCLKM, 0, CLK_IS_CRITICAL | + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_G3D_CLK, "gout_g3d_clk", "dout_g3d_bus", + CLK_CON_GAT_G3D_CLK, 6, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_G3D_PPMU_ACLK, "gout_g3d_ppmu_aclk", "dout_g3d_bus", + CLK_CON_GAT_G3D_PPMU_ACLK, 7, CLK_IS_CRITICAL | + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_G3D_PPMU_PCLK, "gout_g3d_ppmu_pclk", "dout_g3d_apb", + CLK_CON_GAT_G3D_PPMU_PCLK, 4, CLK_IS_CRITICAL | + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_G3D_QE_ACLK, "gout_g3d_qe_aclk", "dout_g3d_bus", + CLK_CON_GAT_G3D_QE_ACLK, 8, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, + 0), + GATE(CLK_GOUT_G3D_QE_PCLK, "gout_g3d_qe_pclk", "dout_g3d_apb", + CLK_CON_GAT_G3D_QE_PCLK, 5, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, + 0), + GATE(CLK_GOUT_G3D_SYSREG_PCLK, "gout_g3d_sysreg_pclk", "dout_g3d_apb", + CLK_CON_GAT_G3D_SYSREG_PCLK, 6, CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_G3D_MUX_SWITCH_USER, "gout_g3d_mux_switch_user", + "mout_g3d_switch_user", CLK_CON_GAT_G3D_MUX_SWITCH_USER, 21, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_G3D_MUX, "gout_g3d_mux", "mout_g3d", CLK_CON_GAT_G3D_MUX, + 21, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_G3D_MUX_PLL, "gout_g3d_mux_pll", "gout_g3d_mux_pll_con", + CLK_CON_GAT_G3D_MUX_PLL, 21, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, + 0), + GATE(CLK_GOUT_G3D_MUX_PLL_CON, "gout_g3d_mux_pll_con", "fout_g3d_pll", + CLK_CON_GAT_G3D_MUX_PLL_CON, 12, CLK_IS_CRITICAL | + CLK_SET_RATE_PARENT, 0), +}; + +static const struct samsung_cmu_info g3d_cmu_info __initconst = { + .pll_clks = g3d_pll_clks, + .nr_pll_clks = ARRAY_SIZE(g3d_pll_clks), + .mux_clks = g3d_mux_clks, + .nr_mux_clks = ARRAY_SIZE(g3d_mux_clks), + .div_clks = g3d_div_clks, + .nr_div_clks = ARRAY_SIZE(g3d_div_clks), + .gate_clks = g3d_gate_clks, + .nr_gate_clks = ARRAY_SIZE(g3d_gate_clks), + .clk_regs = g3d_clk_regs, + .nr_clk_regs = ARRAY_SIZE(g3d_clk_regs), + .nr_clk_ids = G3D_NR_CLK, +}; + +/* + * Register offsets for CMU_ISP (0x144d0000) + */ +#define PLL_LOCKTIME_ISP_PLL 0x0000 +#define PLL_CON0_ISP_PLL 0x0100 +#define CLK_CON_GAT_ISP_MUX_PLL 0x0200 +#define CLK_CON_GAT_ISP_MUX_PLL_CON 0x0200 +#define CLK_CON_GAT_ISP_MUX_VRA_USER 0x0210 +#define CLK_CON_MUX_ISP_VRA_USER 0x0210 +#define CLK_CON_GAT_ISP_MUX_CAM_USER 0x0214 +#define CLK_CON_MUX_ISP_CAM_USER 0x0214 +#define CLK_CON_GAT_ISP_MUX_USER 0x0218 +#define CLK_CON_MUX_ISP_USER 0x0218 +#define CLK_CON_GAT_ISP_MUX_VRA 0x0220 +#define CLK_CON_MUX_ISP_VRA 0x0220 +#define CLK_CON_GAT_ISP_MUX_CAM 0x0224 +#define CLK_CON_MUX_ISP_CAM 0x0224 +#define CLK_CON_GAT_ISP_MUX_ISP 0x0228 +#define CLK_CON_MUX_ISP_ISP 0x0228 +#define CLK_CON_GAT_ISP_MUX_ISPD 0x022c +#define CLK_CON_MUX_ISP_ISPD 0x022c +#define CLK_CON_GAT_ISP_MUX_RXBYTECLKHS0_SENSOR0_USER 0x0230 +#define CLK_CON_GAT_ISP_MUX_RXBYTECLKHS0_SENSOR0_USER_CON 0x0230 +#define CLK_CON_GAT_ISP_MUX_RXBYTECLKHS0_SENSOR1_USER 0x0234 +#define CLK_CON_GAT_ISP_MUX_RXBYTECLKHS0_SENSOR1_USER_CON 0x0234 +#define CLK_CON_DIV_ISP_APB 0x0400 +#define CLK_CON_DIV_ISP_CAM_HALF 0x0404 +#define CLK_CON_GAT_ISP_VRA 0x0810 +#define CLK_CON_GAT_ISP_ISPD 0x0818 +#define CLK_CON_GAT_ISP_ISPD_PPMU 0x0818 +#define CLK_CON_GAT_ISP_CAM 0x081c +#define CLK_CON_GAT_ISP_CAM_HALF 0x0820 + +static const unsigned long isp_clk_regs[] __initconst = { + PLL_LOCKTIME_ISP_PLL, + PLL_CON0_ISP_PLL, + CLK_CON_GAT_ISP_MUX_PLL, + CLK_CON_GAT_ISP_MUX_PLL_CON, + CLK_CON_GAT_ISP_MUX_VRA_USER, + CLK_CON_MUX_ISP_VRA_USER, + CLK_CON_GAT_ISP_MUX_CAM_USER, + CLK_CON_MUX_ISP_CAM_USER, + CLK_CON_GAT_ISP_MUX_USER, + CLK_CON_MUX_ISP_USER, + CLK_CON_GAT_ISP_MUX_VRA, + CLK_CON_MUX_ISP_VRA, + CLK_CON_GAT_ISP_MUX_CAM, + CLK_CON_MUX_ISP_CAM, + CLK_CON_GAT_ISP_MUX_ISP, + CLK_CON_MUX_ISP_ISP, + CLK_CON_GAT_ISP_MUX_ISPD, + CLK_CON_MUX_ISP_ISPD, + CLK_CON_GAT_ISP_MUX_RXBYTECLKHS0_SENSOR0_USER, + CLK_CON_GAT_ISP_MUX_RXBYTECLKHS0_SENSOR0_USER_CON, + CLK_CON_GAT_ISP_MUX_RXBYTECLKHS0_SENSOR1_USER, + CLK_CON_GAT_ISP_MUX_RXBYTECLKHS0_SENSOR1_USER_CON, + CLK_CON_DIV_ISP_APB, + CLK_CON_DIV_ISP_CAM_HALF, + CLK_CON_GAT_ISP_VRA, + CLK_CON_GAT_ISP_ISPD, + CLK_CON_GAT_ISP_ISPD_PPMU, + CLK_CON_GAT_ISP_CAM, + CLK_CON_GAT_ISP_CAM_HALF, +}; + +static const struct samsung_fixed_rate_clock isp_fixed_clks[] __initconst = { + FRATE(0, "frat_isp_rxbyteclkhs0_sensor0", NULL, 0, 188000000), + FRATE(0, "frat_isp_rxbyteclkhs0_sensor1", NULL, 0, 188000000), +}; + +static const struct samsung_pll_clock isp_pll_clks[] __initconst = { + PLL(pll_1417x, CLK_FOUT_ISP_PLL, "fout_isp_pll", "oscclk", + PLL_LOCKTIME_ISP_PLL, PLL_CON0_ISP_PLL, NULL), +}; + +/* List of parent clocks for muxes in CMU_ISP */ +PNAME(mout_isp_cam_user_p) = { "oscclk", "gout_mif_cmu_isp_cam" }; +PNAME(mout_isp_user_p) = { "oscclk", "gout_mif_cmu_isp_isp" }; +PNAME(mout_isp_vra_user_p) = { "oscclk", "gout_mif_cmu_isp_vra" }; +PNAME(mout_isp_cam_p) = { "gout_isp_mux_cam_user", + "gout_isp_mux_pll_con" }; +PNAME(mout_isp_isp_p) = { "gout_isp_mux_user", "gout_isp_mux_pll_con" }; +PNAME(mout_isp_ispd_p) = { "gout_isp_mux_vra", "gout_isp_mux_cam" }; +PNAME(mout_isp_vra_p) = { "gout_isp_mux_vra_user", + "gout_isp_mux_pll_con" }; + +static const struct samsung_mux_clock isp_mux_clks[] __initconst = { + MUX(CLK_MOUT_ISP_CAM_USER, "mout_isp_cam_user", mout_isp_cam_user_p, + CLK_CON_MUX_ISP_CAM_USER, 12, 1), + MUX(CLK_MOUT_ISP_USER, "mout_isp_user", mout_isp_user_p, + CLK_CON_MUX_ISP_USER, 12, 1), + MUX(CLK_MOUT_ISP_VRA_USER, "mout_isp_vra_user", mout_isp_vra_user_p, + CLK_CON_MUX_ISP_VRA_USER, 12, 1), + MUX(CLK_MOUT_ISP_CAM, "mout_isp_cam", mout_isp_cam_p, + CLK_CON_MUX_ISP_CAM, 12, 1), + MUX(CLK_MOUT_ISP_ISP, "mout_isp_isp", mout_isp_isp_p, + CLK_CON_MUX_ISP_ISP, 12, 1), + MUX(CLK_MOUT_ISP_ISPD, "mout_isp_ispd", mout_isp_ispd_p, + CLK_CON_MUX_ISP_ISPD, 12, 1), + MUX(CLK_MOUT_ISP_VRA, "mout_isp_vra", mout_isp_vra_p, + CLK_CON_MUX_ISP_VRA, 12, 1), +}; + +static const struct samsung_div_clock isp_div_clks[] __initconst = { + DIV(CLK_DOUT_ISP_APB, "dout_isp_apb", "gout_isp_mux_vra", + CLK_CON_DIV_ISP_APB, 0, 2), + DIV(CLK_DOUT_ISP_CAM_HALF, "dout_isp_cam_half", "gout_isp_mux_cam", + CLK_CON_DIV_ISP_CAM_HALF, 0, 2), +}; + +static const struct samsung_gate_clock isp_gate_clks[] __initconst = { + GATE(CLK_GOUT_ISP_CAM, "gout_isp_cam", "gout_isp_mux_cam", + CLK_CON_GAT_ISP_CAM, 0, CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_ISP_CAM_HALF, "gout_isp_cam_half", "dout_isp_cam_half", + CLK_CON_GAT_ISP_CAM_HALF, 0, CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_ISP_ISPD, "gout_isp_ispd", "gout_isp_mux_ispd", + CLK_CON_GAT_ISP_ISPD, 0, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_ISP_ISPD_PPMU, "gout_isp_ispd_ppmu", "gout_isp_mux_ispd", + CLK_CON_GAT_ISP_ISPD_PPMU, 1, CLK_IS_CRITICAL | + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_ISP_VRA, "gout_isp_vra", "gout_isp_mux_vra", + CLK_CON_GAT_ISP_VRA, 0, CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_ISP_MUX_CAM_USER, "gout_isp_mux_cam_user", + "mout_isp_cam_user", CLK_CON_GAT_ISP_MUX_CAM_USER, 21, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_ISP_MUX_USER, "gout_isp_mux_user", "mout_isp_user", + CLK_CON_GAT_ISP_MUX_USER, 21, CLK_IS_CRITICAL | + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_ISP_MUX_VRA_USER, "gout_isp_mux_vra_user", + "mout_isp_vra_user", CLK_CON_GAT_ISP_MUX_VRA_USER, 21, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_ISP_MUX_RXBYTECLKHS0_SENSOR1_USER, + "gout_isp_mux_rxbyteclkhs0_sensor1_user", + "gout_isp_mux_rxbyteclkhs0_sensor1_user_con", + CLK_CON_GAT_ISP_MUX_RXBYTECLKHS0_SENSOR1_USER, 21, CLK_IS_CRITICAL + | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_ISP_MUX_RXBYTECLKHS0_SENSOR1_USER_CON, + "gout_isp_mux_rxbyteclkhs0_sensor1_user_con", + "frat_isp_rxbyteclkhs0_sensor1", + CLK_CON_GAT_ISP_MUX_RXBYTECLKHS0_SENSOR1_USER_CON, 12, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_ISP_MUX_RXBYTECLKHS0_SENSOR0_USER, + "gout_isp_mux_rxbyteclkhs0_sensor0_user", + "gout_isp_mux_rxbyteclkhs0_sensor0_user_con", + CLK_CON_GAT_ISP_MUX_RXBYTECLKHS0_SENSOR0_USER, 21, CLK_IS_CRITICAL + | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_ISP_MUX_RXBYTECLKHS0_SENSOR0_USER_CON, + "gout_isp_mux_rxbyteclkhs0_sensor0_user_con", + "frat_isp_rxbyteclkhs0_sensor0", + CLK_CON_GAT_ISP_MUX_RXBYTECLKHS0_SENSOR0_USER_CON, 12, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_ISP_MUX_CAM, "gout_isp_mux_cam", "mout_isp_cam", + CLK_CON_GAT_ISP_MUX_CAM, 21, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, + 0), + GATE(CLK_GOUT_ISP_MUX_ISP, "gout_isp_mux_isp", "mout_isp_isp", + CLK_CON_GAT_ISP_MUX_ISP, 21, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, + 0), + GATE(CLK_GOUT_ISP_MUX_ISPD, "gout_isp_mux_ispd", "mout_isp_ispd", + CLK_CON_GAT_ISP_MUX_ISPD, 21, CLK_IS_CRITICAL | + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_ISP_MUX_VRA, "gout_isp_mux_vra", "mout_isp_vra", + CLK_CON_GAT_ISP_MUX_VRA, 21, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, + 0), + GATE(CLK_GOUT_ISP_MUX_PLL, "gout_isp_mux_pll", "gout_isp_mux_pll_con", + CLK_CON_GAT_ISP_MUX_PLL, 21, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, + 0), + GATE(CLK_GOUT_ISP_MUX_PLL_CON, "gout_isp_mux_pll_con", "fout_isp_pll", + CLK_CON_GAT_ISP_MUX_PLL_CON, 12, CLK_IS_CRITICAL | + CLK_SET_RATE_PARENT, 0), +}; + +static const struct samsung_cmu_info isp_cmu_info __initconst = { + .fixed_clks = isp_fixed_clks, + .nr_fixed_clks = ARRAY_SIZE(isp_fixed_clks), + .pll_clks = isp_pll_clks, + .nr_pll_clks = ARRAY_SIZE(isp_pll_clks), + .mux_clks = isp_mux_clks, + .nr_mux_clks = ARRAY_SIZE(isp_mux_clks), + .div_clks = isp_div_clks, + .nr_div_clks = ARRAY_SIZE(isp_div_clks), + .gate_clks = isp_gate_clks, + .nr_gate_clks = ARRAY_SIZE(isp_gate_clks), + .clk_regs = isp_clk_regs, + .nr_clk_regs = ARRAY_SIZE(isp_clk_regs), + .nr_clk_ids = ISP_NR_CLK, +}; + +/* + * Register offsets for CMU_MFCMSCL (0x12cb0000) + */ +#define CLK_CON_GAT_MFCMSCL_MUX_MSCL_USER 0x0200 +#define CLK_CON_MUX_MFCMSCL_MSCL_USER 0x0200 +#define CLK_CON_GAT_MFCMSCL_MUX_MFC_USER 0x0204 +#define CLK_CON_MUX_MFCMSCL_MFC_USER 0x0204 +#define CLK_CON_DIV_MFCMSCL_APB 0x0400 +#define CLK_CON_GAT_MFCMSCL_MSCL 0x0804 +#define CLK_CON_GAT_MFCMSCL_MSCL_BI 0x0804 +#define CLK_CON_GAT_MFCMSCL_MSCL_D 0x0804 +#define CLK_CON_GAT_MFCMSCL_MSCL_JPEG 0x0804 +#define CLK_CON_GAT_MFCMSCL_MSCL_POLY 0x0804 +#define CLK_CON_GAT_MFCMSCL_MSCL_PPMU 0x0804 +#define CLK_CON_GAT_MFCMSCL_MFC 0x0808 + +static const unsigned long mfcmscl_clk_regs[] __initconst = { + CLK_CON_GAT_MFCMSCL_MUX_MSCL_USER, + CLK_CON_MUX_MFCMSCL_MSCL_USER, + CLK_CON_GAT_MFCMSCL_MUX_MFC_USER, + CLK_CON_MUX_MFCMSCL_MFC_USER, + CLK_CON_DIV_MFCMSCL_APB, + CLK_CON_GAT_MFCMSCL_MSCL, + CLK_CON_GAT_MFCMSCL_MSCL_BI, + CLK_CON_GAT_MFCMSCL_MSCL_D, + CLK_CON_GAT_MFCMSCL_MSCL_JPEG, + CLK_CON_GAT_MFCMSCL_MSCL_POLY, + CLK_CON_GAT_MFCMSCL_MSCL_PPMU, + CLK_CON_GAT_MFCMSCL_MFC, +}; + +/* List of parent clocks for muxes in CMU_MFCMSCL */ +PNAME(mout_mfcmscl_mfc_user_p) = { "oscclk", "gout_mif_cmu_mfcmscl_mfc" }; +PNAME(mout_mfcmscl_mscl_user_p) = { "oscclk", "gout_mif_cmu_mfcmscl_mscl" }; + +static const struct samsung_mux_clock mfcmscl_mux_clks[] __initconst = { + MUX(CLK_MOUT_MFCMSCL_MFC_USER, "mout_mfcmscl_mfc_user", + mout_mfcmscl_mfc_user_p, CLK_CON_MUX_MFCMSCL_MFC_USER, 12, 1), + MUX(CLK_MOUT_MFCMSCL_MSCL_USER, "mout_mfcmscl_mscl_user", + mout_mfcmscl_mscl_user_p, CLK_CON_MUX_MFCMSCL_MSCL_USER, 12, 1), +}; + +static const struct samsung_div_clock mfcmscl_div_clks[] __initconst = { + DIV(CLK_DOUT_MFCMSCL_APB, "dout_mfcmscl_apb", + "gout_mfcmscl_mux_mscl_user", CLK_CON_DIV_MFCMSCL_APB, 0, 2), +}; + +static const struct samsung_gate_clock mfcmscl_gate_clks[] __initconst = { + GATE(CLK_GOUT_MFCMSCL_MFC, "gout_mfcmscl_mfc", + "gout_mfcmscl_mux_mfc_user", CLK_CON_GAT_MFCMSCL_MFC, 0, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MFCMSCL_MSCL, "gout_mfcmscl_mscl", + "gout_mfcmscl_mux_mscl_user", CLK_CON_GAT_MFCMSCL_MSCL, 0, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MFCMSCL_MSCL_BI, "gout_mfcmscl_mscl_bi", + "gout_mfcmscl_mscl_d", CLK_CON_GAT_MFCMSCL_MSCL_BI, 4, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MFCMSCL_MSCL_D, "gout_mfcmscl_mscl_d", + "gout_mfcmscl_mux_mscl_user", CLK_CON_GAT_MFCMSCL_MSCL_D, 1, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MFCMSCL_MSCL_JPEG, "gout_mfcmscl_mscl_jpeg", + "gout_mfcmscl_mscl_d", CLK_CON_GAT_MFCMSCL_MSCL_JPEG, 2, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MFCMSCL_MSCL_POLY, "gout_mfcmscl_mscl_poly", + "gout_mfcmscl_mscl_d", CLK_CON_GAT_MFCMSCL_MSCL_POLY, 3, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MFCMSCL_MSCL_PPMU, "gout_mfcmscl_mscl_ppmu", + "gout_mfcmscl_mux_mscl_user", CLK_CON_GAT_MFCMSCL_MSCL_PPMU, 5, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MFCMSCL_MUX_MFC_USER, "gout_mfcmscl_mux_mfc_user", + "mout_mfcmscl_mfc_user", CLK_CON_GAT_MFCMSCL_MUX_MFC_USER, 21, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_MFCMSCL_MUX_MSCL_USER, "gout_mfcmscl_mux_mscl_user", + "mout_mfcmscl_mscl_user", CLK_CON_GAT_MFCMSCL_MUX_MSCL_USER, 21, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), +}; + +static const struct samsung_cmu_info mfcmscl_cmu_info __initconst = { + .mux_clks = mfcmscl_mux_clks, + .nr_mux_clks = ARRAY_SIZE(mfcmscl_mux_clks), + .div_clks = mfcmscl_div_clks, + .nr_div_clks = ARRAY_SIZE(mfcmscl_div_clks), + .gate_clks = mfcmscl_gate_clks, + .nr_gate_clks = ARRAY_SIZE(mfcmscl_gate_clks), + .clk_regs = mfcmscl_clk_regs, + .nr_clk_regs = ARRAY_SIZE(mfcmscl_clk_regs), + .nr_clk_ids = MFCMSCL_NR_CLK, +}; + +/* + * Register offsets for CMU_PERI (0x101f0000) + */ +#define CLK_CON_GAT_PERI_PWM_MOTOR_OSCCLK 0x0800 +#define CLK_CON_GAT_PERI_TMU_CPUCL0_CLK 0x0800 +#define CLK_CON_GAT_PERI_TMU_CPUCL1_CLK 0x0800 +#define CLK_CON_GAT_PERI_TMU_CLK 0x0800 +#define CLK_CON_GAT_PERI_BUSP1_PERIC0_HCLK 0x0810 +#define CLK_CON_GAT_PERI_GPIO2_PCLK 0x0810 +#define CLK_CON_GAT_PERI_GPIO5_PCLK 0x0810 +#define CLK_CON_GAT_PERI_GPIO6_PCLK 0x0810 +#define CLK_CON_GAT_PERI_GPIO7_PCLK 0x0810 +#define CLK_CON_GAT_PERI_HSI2C4_IPCLK 0x0810 +#define CLK_CON_GAT_PERI_HSI2C6_IPCLK 0x0810 +#define CLK_CON_GAT_PERI_HSI2C3_IPCLK 0x0810 +#define CLK_CON_GAT_PERI_HSI2C5_IPCLK 0x0810 +#define CLK_CON_GAT_PERI_HSI2C2_IPCLK 0x0810 +#define CLK_CON_GAT_PERI_HSI2C1_IPCLK 0x0810 +#define CLK_CON_GAT_PERI_I2C0_PCLK 0x0810 +#define CLK_CON_GAT_PERI_I2C4_PCLK 0x0810 +#define CLK_CON_GAT_PERI_I2C5_PCLK 0x0810 +#define CLK_CON_GAT_PERI_I2C6_PCLK 0x0810 +#define CLK_CON_GAT_PERI_I2C7_PCLK 0x0810 +#define CLK_CON_GAT_PERI_I2C8_PCLK 0x0810 +#define CLK_CON_GAT_PERI_I2C3_PCLK 0x0810 +#define CLK_CON_GAT_PERI_I2C2_PCLK 0x0810 +#define CLK_CON_GAT_PERI_I2C1_PCLK 0x0810 +#define CLK_CON_GAT_PERI_MCT_PCLK 0x0810 +#define CLK_CON_GAT_PERI_PWM_MOTOR_PCLK_S0 0x0810 +#define CLK_CON_GAT_PERI_SFRIF_TMU_CPUCL0_PCLK 0x0814 +#define CLK_CON_GAT_PERI_SFRIF_TMU_CPUCL1_PCLK 0x0814 +#define CLK_CON_GAT_PERI_SFRIF_TMU_PCLK 0x0814 +#define CLK_CON_GAT_PERI_SPI0_PCLK 0x0814 +#define CLK_CON_GAT_PERI_SPI2_PCLK 0x0814 +#define CLK_CON_GAT_PERI_SPI1_PCLK 0x0814 +#define CLK_CON_GAT_PERI_SPI4_PCLK 0x0814 +#define CLK_CON_GAT_PERI_SPI3_PCLK 0x0814 +#define CLK_CON_GAT_PERI_UART1_PCLK 0x0814 +#define CLK_CON_GAT_PERI_UART2_PCLK 0x0814 +#define CLK_CON_GAT_PERI_UART0_PCLK 0x0814 +#define CLK_CON_GAT_PERI_WDT_CPUCL0_PCLK 0x0814 +#define CLK_CON_GAT_PERI_WDT_CPUCL1_PCLK 0x0814 +#define CLK_CON_GAT_PERI_UART1_EXT_UCLK 0x0830 +#define CLK_CON_GAT_PERI_UART2_EXT_UCLK 0x0834 +#define CLK_CON_GAT_PERI_UART0_EXT_UCLK 0x0838 +#define CLK_CON_GAT_PERI_SPI2_SPI_EXT_CLK 0x083c +#define CLK_CON_GAT_PERI_SPI1_SPI_EXT_CLK 0x0840 +#define CLK_CON_GAT_PERI_SPI0_SPI_EXT_CLK 0x0844 +#define CLK_CON_GAT_PERI_SPI3_SPI_EXT_CLK 0x0848 +#define CLK_CON_GAT_PERI_SPI4_SPI_EXT_CLK 0x084c + +static const unsigned long peri_clk_regs[] __initconst = { + CLK_CON_GAT_PERI_PWM_MOTOR_OSCCLK, + CLK_CON_GAT_PERI_TMU_CPUCL0_CLK, + CLK_CON_GAT_PERI_TMU_CPUCL1_CLK, + CLK_CON_GAT_PERI_TMU_CLK, + CLK_CON_GAT_PERI_BUSP1_PERIC0_HCLK, + CLK_CON_GAT_PERI_GPIO2_PCLK, + CLK_CON_GAT_PERI_GPIO5_PCLK, + CLK_CON_GAT_PERI_GPIO6_PCLK, + CLK_CON_GAT_PERI_GPIO7_PCLK, + CLK_CON_GAT_PERI_HSI2C4_IPCLK, + CLK_CON_GAT_PERI_HSI2C6_IPCLK, + CLK_CON_GAT_PERI_HSI2C3_IPCLK, + CLK_CON_GAT_PERI_HSI2C5_IPCLK, + CLK_CON_GAT_PERI_HSI2C2_IPCLK, + CLK_CON_GAT_PERI_HSI2C1_IPCLK, + CLK_CON_GAT_PERI_I2C0_PCLK, + CLK_CON_GAT_PERI_I2C4_PCLK, + CLK_CON_GAT_PERI_I2C5_PCLK, + CLK_CON_GAT_PERI_I2C6_PCLK, + CLK_CON_GAT_PERI_I2C7_PCLK, + CLK_CON_GAT_PERI_I2C8_PCLK, + CLK_CON_GAT_PERI_I2C3_PCLK, + CLK_CON_GAT_PERI_I2C2_PCLK, + CLK_CON_GAT_PERI_I2C1_PCLK, + CLK_CON_GAT_PERI_MCT_PCLK, + CLK_CON_GAT_PERI_PWM_MOTOR_PCLK_S0, + CLK_CON_GAT_PERI_SFRIF_TMU_CPUCL0_PCLK, + CLK_CON_GAT_PERI_SFRIF_TMU_CPUCL1_PCLK, + CLK_CON_GAT_PERI_SFRIF_TMU_PCLK, + CLK_CON_GAT_PERI_SPI0_PCLK, + CLK_CON_GAT_PERI_SPI2_PCLK, + CLK_CON_GAT_PERI_SPI1_PCLK, + CLK_CON_GAT_PERI_SPI4_PCLK, + CLK_CON_GAT_PERI_SPI3_PCLK, + CLK_CON_GAT_PERI_UART1_PCLK, + CLK_CON_GAT_PERI_UART2_PCLK, + CLK_CON_GAT_PERI_UART0_PCLK, + CLK_CON_GAT_PERI_WDT_CPUCL0_PCLK, + CLK_CON_GAT_PERI_WDT_CPUCL1_PCLK, + CLK_CON_GAT_PERI_UART1_EXT_UCLK, + CLK_CON_GAT_PERI_UART2_EXT_UCLK, + CLK_CON_GAT_PERI_UART0_EXT_UCLK, + CLK_CON_GAT_PERI_SPI2_SPI_EXT_CLK, + CLK_CON_GAT_PERI_SPI1_SPI_EXT_CLK, + CLK_CON_GAT_PERI_SPI0_SPI_EXT_CLK, + CLK_CON_GAT_PERI_SPI3_SPI_EXT_CLK, + CLK_CON_GAT_PERI_SPI4_SPI_EXT_CLK, +}; + +static const struct samsung_gate_clock peri_gate_clks[] __initconst = { + GATE(CLK_GOUT_PERI_BUSP1_PERIC0_HCLK, "gout_peri_busp1_peric0_hclk", + "gout_mif_cmu_peri_bus", CLK_CON_GAT_PERI_BUSP1_PERIC0_HCLK, 3, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_PERI_GPIO2_PCLK, "gout_peri_gpio2_pclk", + "gout_mif_cmu_peri_bus", CLK_CON_GAT_PERI_GPIO2_PCLK, 7, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_PERI_GPIO5_PCLK, "gout_peri_gpio5_pclk", + "gout_mif_cmu_peri_bus", CLK_CON_GAT_PERI_GPIO5_PCLK, 8, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_PERI_GPIO6_PCLK, "gout_peri_gpio6_pclk", + "gout_mif_cmu_peri_bus", CLK_CON_GAT_PERI_GPIO6_PCLK, 9, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_PERI_GPIO7_PCLK, "gout_peri_gpio7_pclk", + "gout_mif_cmu_peri_bus", CLK_CON_GAT_PERI_GPIO7_PCLK, 10, + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_PERI_HSI2C4_IPCLK, "gout_peri_hsi2c4_ipclk", + "gout_peri_busp1_peric0_hclk", CLK_CON_GAT_PERI_HSI2C4_IPCLK, 14, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_PERI_HSI2C6_IPCLK, "gout_peri_hsi2c6_ipclk", + "gout_mif_cmu_peri_bus", CLK_CON_GAT_PERI_HSI2C6_IPCLK, 16, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_PERI_HSI2C3_IPCLK, "gout_peri_hsi2c3_ipclk", + "gout_peri_busp1_peric0_hclk", CLK_CON_GAT_PERI_HSI2C3_IPCLK, 13, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_PERI_HSI2C5_IPCLK, "gout_peri_hsi2c5_ipclk", + "gout_mif_cmu_peri_bus", CLK_CON_GAT_PERI_HSI2C5_IPCLK, 15, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_PERI_HSI2C2_IPCLK, "gout_peri_hsi2c2_ipclk", + "gout_peri_busp1_peric0_hclk", CLK_CON_GAT_PERI_HSI2C2_IPCLK, 12, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_PERI_HSI2C1_IPCLK, "gout_peri_hsi2c1_ipclk", + "gout_peri_busp1_peric0_hclk", CLK_CON_GAT_PERI_HSI2C1_IPCLK, 11, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_PERI_I2C0_PCLK, "gout_peri_i2c0_pclk", + "gout_peri_busp1_peric0_hclk", CLK_CON_GAT_PERI_I2C0_PCLK, 21, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_PERI_I2C4_PCLK, "gout_peri_i2c4_pclk", + "gout_peri_busp1_peric0_hclk", CLK_CON_GAT_PERI_I2C4_PCLK, 17, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_PERI_I2C5_PCLK, "gout_peri_i2c5_pclk", + "gout_peri_busp1_peric0_hclk", CLK_CON_GAT_PERI_I2C5_PCLK, 18, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_PERI_I2C6_PCLK, "gout_peri_i2c6_pclk", + "gout_peri_busp1_peric0_hclk", CLK_CON_GAT_PERI_I2C6_PCLK, 19, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_PERI_I2C7_PCLK, "gout_peri_i2c7_pclk", + "gout_peri_busp1_peric0_hclk", CLK_CON_GAT_PERI_I2C7_PCLK, 24, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_PERI_I2C8_PCLK, "gout_peri_i2c8_pclk", + "gout_peri_busp1_peric0_hclk", CLK_CON_GAT_PERI_I2C8_PCLK, 25, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_PERI_I2C3_PCLK, "gout_peri_i2c3_pclk", + "gout_peri_busp1_peric0_hclk", CLK_CON_GAT_PERI_I2C3_PCLK, 20, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_PERI_I2C2_PCLK, "gout_peri_i2c2_pclk", + "gout_peri_busp1_peric0_hclk", CLK_CON_GAT_PERI_I2C2_PCLK, 22, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_PERI_I2C1_PCLK, "gout_peri_i2c1_pclk", + "gout_peri_busp1_peric0_hclk", CLK_CON_GAT_PERI_I2C1_PCLK, 23, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_PERI_MCT_PCLK, "gout_peri_mct_pclk", + "gout_mif_cmu_peri_bus", CLK_CON_GAT_PERI_MCT_PCLK, 26, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_PERI_PWM_MOTOR_OSCCLK, "gout_peri_pwm_motor_oscclk", + "oscclk", CLK_CON_GAT_PERI_PWM_MOTOR_OSCCLK, 2, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_PERI_PWM_MOTOR_PCLK_S0, "gout_peri_pwm_motor_pclk_s0", + "gout_mif_cmu_peri_bus", CLK_CON_GAT_PERI_PWM_MOTOR_PCLK_S0, 29, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_PERI_SFRIF_TMU_CPUCL0_PCLK, + "gout_peri_sfrif_tmu_cpucl0_pclk", "gout_mif_cmu_peri_bus", + CLK_CON_GAT_PERI_SFRIF_TMU_CPUCL0_PCLK, 1, CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_PERI_SFRIF_TMU_CPUCL1_PCLK, + "gout_peri_sfrif_tmu_cpucl1_pclk", "gout_mif_cmu_peri_bus", + CLK_CON_GAT_PERI_SFRIF_TMU_CPUCL1_PCLK, 2, CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_PERI_SFRIF_TMU_PCLK, "gout_peri_sfrif_tmu_pclk", + "gout_mif_cmu_peri_bus", CLK_CON_GAT_PERI_SFRIF_TMU_PCLK, 3, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_PERI_SPI0_PCLK, "gout_peri_spi0_pclk", + "gout_mif_cmu_peri_bus", CLK_CON_GAT_PERI_SPI0_PCLK, 6, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_PERI_SPI0_SPI_EXT_CLK, "gout_peri_spi0_spi_ext_clk", + "gout_mif_cmu_peri_spi0", CLK_CON_GAT_PERI_SPI0_SPI_EXT_CLK, 0, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_PERI_SPI2_PCLK, "gout_peri_spi2_pclk", + "gout_mif_cmu_peri_bus", CLK_CON_GAT_PERI_SPI2_PCLK, 4, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_PERI_SPI2_SPI_EXT_CLK, "gout_peri_spi2_spi_ext_clk", + "gout_mif_cmu_peri_spi2", CLK_CON_GAT_PERI_SPI2_SPI_EXT_CLK, 0, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_PERI_SPI1_PCLK, "gout_peri_spi1_pclk", + "gout_mif_cmu_peri_bus", CLK_CON_GAT_PERI_SPI1_PCLK, 5, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_PERI_SPI1_SPI_EXT_CLK, "gout_peri_spi1_spi_ext_clk", + "gout_mif_cmu_peri_spi1", CLK_CON_GAT_PERI_SPI1_SPI_EXT_CLK, 0, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_PERI_SPI4_PCLK, "gout_peri_spi4_pclk", + "gout_mif_cmu_peri_bus", CLK_CON_GAT_PERI_SPI4_PCLK, 8, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_PERI_SPI4_SPI_EXT_CLK, "gout_peri_spi4_spi_ext_clk", + "gout_mif_cmu_peri_spi4", CLK_CON_GAT_PERI_SPI4_SPI_EXT_CLK, 0, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_PERI_SPI3_PCLK, "gout_peri_spi3_pclk", + "gout_mif_cmu_peri_bus", CLK_CON_GAT_PERI_SPI3_PCLK, 7, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_PERI_SPI3_SPI_EXT_CLK, "gout_peri_spi3_spi_ext_clk", + "gout_mif_cmu_peri_spi3", CLK_CON_GAT_PERI_SPI3_SPI_EXT_CLK, 0, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_PERI_TMU_CPUCL0_CLK, "gout_peri_tmu_cpucl0_clk", "oscclk", + CLK_CON_GAT_PERI_TMU_CPUCL0_CLK, 4, CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_PERI_TMU_CPUCL1_CLK, "gout_peri_tmu_cpucl1_clk", "oscclk", + CLK_CON_GAT_PERI_TMU_CPUCL1_CLK, 5, CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_PERI_TMU_CLK, "gout_peri_tmu_clk", "oscclk", + CLK_CON_GAT_PERI_TMU_CLK, 6, CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_PERI_UART1_EXT_UCLK, "gout_peri_uart1_ext_uclk", + "gout_mif_cmu_peri_uart1", CLK_CON_GAT_PERI_UART1_EXT_UCLK, 0, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_PERI_UART1_PCLK, "gout_peri_uart1_pclk", + "gout_peri_busp1_peric0_hclk", CLK_CON_GAT_PERI_UART1_PCLK, 11, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_PERI_UART2_EXT_UCLK, "gout_peri_uart2_ext_uclk", + "gout_mif_cmu_peri_uart2", CLK_CON_GAT_PERI_UART2_EXT_UCLK, 0, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_PERI_UART2_PCLK, "gout_peri_uart2_pclk", + "gout_peri_busp1_peric0_hclk", CLK_CON_GAT_PERI_UART2_PCLK, 12, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_PERI_UART0_EXT_UCLK, "gout_peri_uart0_ext_uclk", + "gout_mif_cmu_peri_uart0", CLK_CON_GAT_PERI_UART0_EXT_UCLK, 0, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_PERI_UART0_PCLK, "gout_peri_uart0_pclk", + "gout_peri_busp1_peric0_hclk", CLK_CON_GAT_PERI_UART0_PCLK, 10, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_PERI_WDT_CPUCL0_PCLK, "gout_peri_wdt_cpucl0_pclk", + "gout_mif_cmu_peri_bus", CLK_CON_GAT_PERI_WDT_CPUCL0_PCLK, 13, + CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_PERI_WDT_CPUCL1_PCLK, "gout_peri_wdt_cpucl1_pclk", + "gout_mif_cmu_peri_bus", CLK_CON_GAT_PERI_WDT_CPUCL1_PCLK, 14, + CLK_SET_RATE_PARENT, 0), +}; + +static const struct samsung_cmu_info peri_cmu_info __initconst = { + .gate_clks = peri_gate_clks, + .nr_gate_clks = ARRAY_SIZE(peri_gate_clks), + .clk_regs = peri_clk_regs, + .nr_clk_regs = ARRAY_SIZE(peri_clk_regs), + .nr_clk_ids = PERI_NR_CLK, +}; + +static int __init exynos7870_cmu_probe(struct platform_device *pdev) +{ + const struct samsung_cmu_info *info; + struct device *dev = &pdev->dev; + + info = of_device_get_match_data(dev); + exynos_arm64_register_cmu(dev, dev->of_node, info); + + return 0; +} + +static const struct of_device_id exynos7870_cmu_of_match[] = { + { + .compatible = "samsung,exynos7870-cmu-mif", + .data = &mif_cmu_info, + }, { + .compatible = "samsung,exynos7870-cmu-dispaud", + .data = &dispaud_cmu_info, + }, { + .compatible = "samsung,exynos7870-cmu-fsys", + .data = &fsys_cmu_info, + }, { + .compatible = "samsung,exynos7870-cmu-g3d", + .data = &g3d_cmu_info, + }, { + .compatible = "samsung,exynos7870-cmu-isp", + .data = &isp_cmu_info, + }, { + .compatible = "samsung,exynos7870-cmu-mfcmscl", + .data = &mfcmscl_cmu_info, + }, { + .compatible = "samsung,exynos7870-cmu-peri", + .data = &peri_cmu_info, + }, { + }, +}; + +static struct platform_driver exynos7870_cmu_driver __refdata = { + .driver = { + .name = "exynos7870-cmu", + .of_match_table = exynos7870_cmu_of_match, + .suppress_bind_attrs = true, + }, + .probe = exynos7870_cmu_probe, +}; + +static int __init exynos7870_cmu_init(void) +{ + return platform_driver_register(&exynos7870_cmu_driver); +} +core_initcall(exynos7870_cmu_init); diff --git a/drivers/clk/samsung/clk-exynos7885.c b/drivers/clk/samsung/clk-exynos7885.c index fc42251731ed..ba7cf79bc300 100644 --- a/drivers/clk/samsung/clk-exynos7885.c +++ b/drivers/clk/samsung/clk-exynos7885.c @@ -6,8 +6,8 @@ * Common Clock Framework support for Exynos7885 SoC. */ -#include <linux/clk.h> #include <linux/clk-provider.h> +#include <linux/mod_devicetable.h> #include <linux/of.h> #include <linux/platform_device.h> diff --git a/drivers/clk/samsung/clk-exynos850.c b/drivers/clk/samsung/clk-exynos850.c index e00e213b1201..cf7e08cca78e 100644 --- a/drivers/clk/samsung/clk-exynos850.c +++ b/drivers/clk/samsung/clk-exynos850.c @@ -6,8 +6,8 @@ * Common Clock Framework support for Exynos850 SoC. */ -#include <linux/clk.h> #include <linux/clk-provider.h> +#include <linux/mod_devicetable.h> #include <linux/of.h> #include <linux/platform_device.h> diff --git a/drivers/clk/samsung/clk-exynos8895.c b/drivers/clk/samsung/clk-exynos8895.c index 29ec0c4a8635..e6980a8f026f 100644 --- a/drivers/clk/samsung/clk-exynos8895.c +++ b/drivers/clk/samsung/clk-exynos8895.c @@ -6,8 +6,8 @@ * Common Clock Framework support for Exynos8895 SoC. */ -#include <linux/clk.h> #include <linux/clk-provider.h> +#include <linux/mod_devicetable.h> #include <linux/of.h> #include <linux/platform_device.h> diff --git a/drivers/clk/samsung/clk-exynos990.c b/drivers/clk/samsung/clk-exynos990.c index 8e2a2e8eccee..8d3f193d2b4d 100644 --- a/drivers/clk/samsung/clk-exynos990.c +++ b/drivers/clk/samsung/clk-exynos990.c @@ -5,8 +5,8 @@ * Common Clock Framework support for Exynos990. */ -#include <linux/clk.h> #include <linux/clk-provider.h> +#include <linux/mod_devicetable.h> #include <linux/of.h> #include <linux/platform_device.h> @@ -19,6 +19,7 @@ /* NOTE: Must be equal to the last clock ID increased by one */ #define CLKS_NR_TOP (CLK_GOUT_CMU_VRA_BUS + 1) #define CLKS_NR_HSI0 (CLK_GOUT_HSI0_XIU_D_HSI0_ACLK + 1) +#define CLKS_NR_PERIS (CLK_GOUT_PERIS_OTP_CON_TOP_OSCCLK + 1) /* ---- CMU_TOP ------------------------------------------------------------- */ @@ -449,7 +450,7 @@ static const struct samsung_pll_clock top_pll_clks[] __initconst = { PLL_LOCKTIME_PLL_G3D, PLL_CON3_PLL_G3D, NULL), }; -/* Parent clock list for CMU_TOP muxes*/ +/* Parent clock list for CMU_TOP muxes */ PNAME(mout_pll_shared0_p) = { "oscclk", "fout_shared0_pll" }; PNAME(mout_pll_shared1_p) = { "oscclk", "fout_shared1_pll" }; PNAME(mout_pll_shared2_p) = { "oscclk", "fout_shared2_pll" }; @@ -1192,6 +1193,7 @@ static const unsigned long hsi0_clk_regs[] __initconst = { CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D_HSI0_IPCLKPORT_ACLK, }; +/* Parent clock list for CMU_HSI0 muxes */ PNAME(mout_hsi0_bus_user_p) = { "oscclk", "dout_cmu_hsi0_bus" }; PNAME(mout_hsi0_usb31drd_user_p) = { "oscclk", "dout_cmu_hsi0_usb31drd" }; PNAME(mout_hsi0_usbdp_debug_user_p) = { "oscclk", @@ -1305,6 +1307,182 @@ static const struct samsung_cmu_info hsi0_cmu_info __initconst = { .clk_name = "bus", }; +/* ---- CMU_PERIS ----------------------------------------------------------- */ + +/* Register Offset definitions for CMU_PERIS (0x10020000) */ +#define PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER 0x0600 +#define PLL_CON1_MUX_CLKCMU_PERIS_BUS_USER 0x0604 +#define CLK_CON_MUX_MUX_CLK_PERIS_GIC 0x1000 +#define CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK 0x203c +#define CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER2_IPCLKPORT_PCLK 0x204c +#define CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK 0x2048 +#define CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK 0x200c +#define CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_BUSP_IPCLKPORT_CLK 0x2034 +#define CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_OSCCLK_IPCLKPORT_CLK 0x2010 +#define CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK 0x2038 +#define CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKM 0x2014 +#define CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK 0x2028 +#define CLK_CON_GAT_GOUT_BLK_PERIS_UID_GIC_IPCLKPORT_CLK 0x201c +#define CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERIS_IPCLKPORT_I_CLK 0x2020 +#define CLK_CON_GAT_GOUT_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK 0x2024 +#define CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK 0x2030 +#define CLK_CON_GAT_GOUT_BLK_PERIS_UID_D_TZPC_PERIS_IPCLKPORT_PCLK 0x2018 +#define CLK_CON_GAT_GOUT_BLK_PERIS_UID_TMU_SUB_IPCLKPORT_PCLK 0x2040 +#define CLK_CON_GAT_GOUT_BLK_PERIS_UID_TMU_TOP_IPCLKPORT_PCLK 0x2044 +#define CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK 0x2000 +#define CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK 0x2008 +#define QCH_CON_D_TZPC_PERIS_QCH 0x3004 +#define QCH_CON_GIC_QCH 0x3008 +#define QCH_CON_LHM_AXI_P_PERIS_QCH 0x300c +#define QCH_CON_MCT_QCH 0x3010 +#define QCH_CON_OTP_CON_BIRA_QCH 0x3014 +#define QCH_CON_OTP_CON_TOP_QCH 0x301c +#define QCH_CON_PERIS_CMU_PERIS_QCH 0x3020 +#define QCH_CON_SYSREG_PERIS_QCH 0x3024 +#define QCH_CON_TMU_SUB_QCH 0x3028 +#define QCH_CON_TMU_TOP_QCH 0x302c +#define QCH_CON_WDT_CLUSTER0_QCH 0x3030 +#define QCH_CON_WDT_CLUSTER2_QCH 0x3034 + +static const unsigned long peris_clk_regs[] __initconst = { + PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER, + PLL_CON1_MUX_CLKCMU_PERIS_BUS_USER, + CLK_CON_MUX_MUX_CLK_PERIS_GIC, + CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER2_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_BUSP_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_OSCCLK_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKM, + CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_PERIS_UID_GIC_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERIS_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_PERIS_UID_D_TZPC_PERIS_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_PERIS_UID_TMU_SUB_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_PERIS_UID_TMU_TOP_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK, + CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK, + QCH_CON_D_TZPC_PERIS_QCH, + QCH_CON_GIC_QCH, + QCH_CON_LHM_AXI_P_PERIS_QCH, + QCH_CON_MCT_QCH, + QCH_CON_OTP_CON_BIRA_QCH, + QCH_CON_OTP_CON_TOP_QCH, + QCH_CON_PERIS_CMU_PERIS_QCH, + QCH_CON_SYSREG_PERIS_QCH, + QCH_CON_TMU_SUB_QCH, + QCH_CON_TMU_TOP_QCH, + QCH_CON_WDT_CLUSTER0_QCH, + QCH_CON_WDT_CLUSTER2_QCH, +}; + +/* Parent clock list for CMU_PERIS muxes */ +PNAME(mout_peris_bus_user_p) = { "oscclk", "mout_cmu_peris_bus" }; +PNAME(mout_peris_clk_peris_gic_p) = { "oscclk", "mout_peris_bus_user" }; + +static const struct samsung_mux_clock peris_mux_clks[] __initconst = { + MUX(CLK_MOUT_PERIS_BUS_USER, "mout_peris_bus_user", + mout_peris_bus_user_p, PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER, + 4, 1), + MUX(CLK_MOUT_PERIS_CLK_PERIS_GIC, "mout_peris_clk_peris_gic", + mout_peris_clk_peris_gic_p, CLK_CON_MUX_MUX_CLK_PERIS_GIC, + 4, 1), +}; + +static const struct samsung_gate_clock peris_gate_clks[] __initconst = { + GATE(CLK_GOUT_PERIS_SYSREG_PERIS_PCLK, + "gout_peris_sysreg_peris_pclk", "mout_peris_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIS_WDT_CLUSTER2_PCLK, + "gout_peris_wdt_cluster2_pclk", "mout_peris_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER2_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIS_WDT_CLUSTER0_PCLK, + "gout_peris_wdt_cluster0_pclk", "mout_peris_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_CLK_PERIS_PERIS_CMU_PERIS_PCLK, + "clk_peris_peris_cmu_peris_pclk", "mout_peris_bus_user", + CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_PERIS_CLK_PERIS_BUSP_CLK, + "gout_peris_clk_peris_busp_clk", "mout_peris_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_BUSP_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIS_CLK_PERIS_OSCCLK_CLK, + "gout_peris_clk_peris_oscclk_clk", "mout_peris_bus_user", + CLK_CON_GAT_CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_OSCCLK_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIS_CLK_PERIS_GIC_CLK, + "gout_peris_clk_peris_gic_clk", "mout_peris_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIS_AD_AXI_P_PERIS_ACLKM, + "gout_peris_ad_axi_p_peris_aclkm", "mout_peris_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKM, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_PERIS_OTP_CON_BIRA_PCLK, + "gout_peris_otp_con_bira_pclk", "mout_peris_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIS_GIC_CLK, + "gout_peris_gic_clk", "mout_peris_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIS_UID_GIC_IPCLKPORT_CLK, + 21, CLK_IS_CRITICAL, 0), + GATE(CLK_GOUT_PERIS_LHM_AXI_P_PERIS_CLK, + "gout_peris_lhm_axi_p_peris_clk", "oscclk", + CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERIS_IPCLKPORT_I_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_PERIS_MCT_PCLK, + "gout_peris_mct_pclk", "mout_peris_clk_peris_gic", + CLK_CON_GAT_GOUT_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIS_OTP_CON_TOP_PCLK, + "gout_peris_otp_con_top_pclk", "mout_peris_clk_peris_gic", + CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIS_D_TZPC_PERIS_PCLK, + "gout_peris_d_tzpc_peris_pclk", "mout_peris_bus_user", + CLK_CON_GAT_GOUT_BLK_PERIS_UID_D_TZPC_PERIS_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIS_TMU_TOP_PCLK, + "gout_peris_tmu_top_pclk", "mout_peris_clk_peris_gic", + CLK_CON_GAT_GOUT_BLK_PERIS_UID_TMU_TOP_IPCLKPORT_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIS_OTP_CON_BIRA_OSCCLK, + "gout_peris_otp_con_bira_oscclk", "oscclk", + CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK, + 21, 0, 0), + GATE(CLK_GOUT_PERIS_OTP_CON_TOP_OSCCLK, + "gout_peris_otp_con_top_oscclk", "oscclk", + CLK_CON_GAT_CLK_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK, + 21, 0, 0), +}; + +static const struct samsung_cmu_info peris_cmu_info __initconst = { + .mux_clks = peris_mux_clks, + .nr_mux_clks = ARRAY_SIZE(peris_mux_clks), + .gate_clks = peris_gate_clks, + .nr_gate_clks = ARRAY_SIZE(peris_gate_clks), + .nr_clk_ids = CLKS_NR_PERIS, + .clk_regs = peris_clk_regs, + .nr_clk_regs = ARRAY_SIZE(peris_clk_regs), +}; + +static void __init exynos990_cmu_peris_init(struct device_node *np) +{ + exynos_arm64_register_cmu(NULL, np, &peris_cmu_info); +} + +/* Register CMU_PERIS early, as it's a dependency for the MCT. */ +CLK_OF_DECLARE(exynos990_cmu_peris, "samsung,exynos990-cmu-peris", + exynos990_cmu_peris_init); + /* ----- platform_driver ----- */ static int __init exynos990_cmu_probe(struct platform_device *pdev) diff --git a/drivers/clk/samsung/clk-exynosautov9.c b/drivers/clk/samsung/clk-exynosautov9.c index 5971e680e566..e4d7c7b96aa8 100644 --- a/drivers/clk/samsung/clk-exynosautov9.c +++ b/drivers/clk/samsung/clk-exynosautov9.c @@ -6,8 +6,8 @@ * Common Clock Framework support for ExynosAuto V9 SoC. */ -#include <linux/clk.h> #include <linux/clk-provider.h> +#include <linux/mod_devicetable.h> #include <linux/of.h> #include <linux/platform_device.h> diff --git a/drivers/clk/samsung/clk-exynosautov920.c b/drivers/clk/samsung/clk-exynosautov920.c index 2a8bfd5d9abc..dc8d4240f6de 100644 --- a/drivers/clk/samsung/clk-exynosautov920.c +++ b/drivers/clk/samsung/clk-exynosautov920.c @@ -6,8 +6,8 @@ * Common Clock Framework support for ExynosAuto v920 SoC. */ -#include <linux/clk.h> #include <linux/clk-provider.h> +#include <linux/mod_devicetable.h> #include <linux/of.h> #include <linux/platform_device.h> diff --git a/drivers/clk/samsung/clk-fsd.c b/drivers/clk/samsung/clk-fsd.c index 9a6006c298c2..594931334574 100644 --- a/drivers/clk/samsung/clk-fsd.c +++ b/drivers/clk/samsung/clk-fsd.c @@ -8,10 +8,10 @@ * Common Clock Framework support for FSD SoC. */ -#include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/init.h> #include <linux/kernel.h> +#include <linux/mod_devicetable.h> #include <linux/of.h> #include <linux/platform_device.h> diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c index 86b39edba122..b58b8e1c272d 100644 --- a/drivers/clk/samsung/clk-gs101.c +++ b/drivers/clk/samsung/clk-gs101.c @@ -6,8 +6,8 @@ * Common Clock Framework support for GS101. */ -#include <linux/clk.h> #include <linux/clk-provider.h> +#include <linux/mod_devicetable.h> #include <linux/of.h> #include <linux/platform_device.h> diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index 2e94bba6c396..d2b5b525c560 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -1460,6 +1460,7 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, init.ops = &samsung_pll2650xx_clk_ops; break; case pll_531x: + case pll_4311: init.ops = &samsung_pll531x_clk_ops; break; default: diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h index 6ddc54d173a0..e9a5f8e0e0a3 100644 --- a/drivers/clk/samsung/clk-pll.h +++ b/drivers/clk/samsung/clk-pll.h @@ -48,6 +48,7 @@ enum samsung_pll_type { pll_0717x, pll_0718x, pll_0732x, + pll_4311, }; #define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \ diff --git a/drivers/clk/samsung/clk-s3c64xx.c b/drivers/clk/samsung/clk-s3c64xx.c index e2ec8fe32e39..397a057af5d1 100644 --- a/drivers/clk/samsung/clk-s3c64xx.c +++ b/drivers/clk/samsung/clk-s3c64xx.c @@ -8,7 +8,6 @@ #include <linux/slab.h> #include <linux/clk-provider.h> #include <linux/clk/samsung.h> -#include <linux/of.h> #include <linux/of_address.h> #include <dt-bindings/clock/samsung,s3c64xx-clock.h> diff --git a/drivers/clk/samsung/clk-s5pv210-audss.c b/drivers/clk/samsung/clk-s5pv210-audss.c index d19a3d9fd452..b1fd8fac3a4c 100644 --- a/drivers/clk/samsung/clk-s5pv210-audss.c +++ b/drivers/clk/samsung/clk-s5pv210-audss.c @@ -13,6 +13,7 @@ #include <linux/io.h> #include <linux/clk.h> #include <linux/clk-provider.h> +#include <linux/mod_devicetable.h> #include <linux/of_address.h> #include <linux/syscore_ops.h> #include <linux/init.h> diff --git a/drivers/clk/samsung/clk-s5pv210.c b/drivers/clk/samsung/clk-s5pv210.c index cd85342e4ddb..9a4217cc1908 100644 --- a/drivers/clk/samsung/clk-s5pv210.c +++ b/drivers/clk/samsung/clk-s5pv210.c @@ -9,7 +9,6 @@ */ #include <linux/clk-provider.h> -#include <linux/of.h> #include <linux/of_address.h> #include "clk.h" diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c index 283c523763e6..dbc9925ca8f4 100644 --- a/drivers/clk/samsung/clk.c +++ b/drivers/clk/samsung/clk.c @@ -10,9 +10,9 @@ #include <linux/slab.h> #include <linux/clkdev.h> -#include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/io.h> +#include <linux/mod_devicetable.h> #include <linux/of_address.h> #include <linux/syscore_ops.h> @@ -74,12 +74,12 @@ struct samsung_clk_provider * __init samsung_clk_init(struct device *dev, if (!ctx) panic("could not allocate clock provider context.\n"); + ctx->clk_data.num = nr_clks; for (i = 0; i < nr_clks; ++i) ctx->clk_data.hws[i] = ERR_PTR(-ENOENT); ctx->dev = dev; ctx->reg_base = base; - ctx->clk_data.num = nr_clks; spin_lock_init(&ctx->lock); return ctx; diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h index fb06caa71f0a..18660c1ac6f0 100644 --- a/drivers/clk/samsung/clk.h +++ b/drivers/clk/samsung/clk.h @@ -11,6 +11,7 @@ #define __SAMSUNG_CLK_H #include <linux/clk-provider.h> +#include <linux/mod_devicetable.h> #include "clk-pll.h" #include "clk-cpu.h" diff --git a/include/dt-bindings/clock/mediatek,mt8188-clk.h b/include/dt-bindings/clock/mediatek,mt8188-clk.h index bd5cd100b796..0e87f61c90f4 100644 --- a/include/dt-bindings/clock/mediatek,mt8188-clk.h +++ b/include/dt-bindings/clock/mediatek,mt8188-clk.h @@ -721,6 +721,6 @@ #define CLK_VDO1_DPINTF 58 #define CLK_VDO1_DISP_MONITOR_DPINTF 59 #define CLK_VDO1_26M_SLOW 60 -#define CLK_VDO1_NR_CLK 61 +#define CLK_VDO1_DPI1_HDMI 61 #endif /* _DT_BINDINGS_CLK_MT8188_H */ diff --git a/include/dt-bindings/clock/rk3188-cru-common.h b/include/dt-bindings/clock/rk3188-cru-common.h index 01e14ab252a7..dd988cc9d582 100644 --- a/include/dt-bindings/clock/rk3188-cru-common.h +++ b/include/dt-bindings/clock/rk3188-cru-common.h @@ -103,6 +103,8 @@ #define PCLK_PERI 351 #define PCLK_DDRUPCTL 352 #define PCLK_PUBL 353 +#define PCLK_CIF0 354 +#define PCLK_CIF1 355 /* hclk gates */ #define HCLK_SDMMC 448 diff --git a/include/dt-bindings/clock/rockchip,rk3528-cru.h b/include/dt-bindings/clock/rockchip,rk3528-cru.h new file mode 100644 index 000000000000..55a448f5ed6d --- /dev/null +++ b/include/dt-bindings/clock/rockchip,rk3528-cru.h @@ -0,0 +1,453 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (c) 2022 Rockchip Electronics Co. Ltd. + * Copyright (c) 2024 Yao Zi <ziyao@disroot.org> + * Author: Joseph Chen <chenjh@rock-chips.com> + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3528_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3528_H + +/* cru-clocks indices */ +#define PLL_APLL 0 +#define PLL_CPLL 1 +#define PLL_GPLL 2 +#define PLL_PPLL 3 +#define PLL_DPLL 4 +#define ARMCLK 5 +#define XIN_OSC0_HALF 6 +#define CLK_MATRIX_50M_SRC 7 +#define CLK_MATRIX_100M_SRC 8 +#define CLK_MATRIX_150M_SRC 9 +#define CLK_MATRIX_200M_SRC 10 +#define CLK_MATRIX_250M_SRC 11 +#define CLK_MATRIX_300M_SRC 12 +#define CLK_MATRIX_339M_SRC 13 +#define CLK_MATRIX_400M_SRC 14 +#define CLK_MATRIX_500M_SRC 15 +#define CLK_MATRIX_600M_SRC 16 +#define CLK_UART0_SRC 17 +#define CLK_UART0_FRAC 18 +#define SCLK_UART0 19 +#define CLK_UART1_SRC 20 +#define CLK_UART1_FRAC 21 +#define SCLK_UART1 22 +#define CLK_UART2_SRC 23 +#define CLK_UART2_FRAC 24 +#define SCLK_UART2 25 +#define CLK_UART3_SRC 26 +#define CLK_UART3_FRAC 27 +#define SCLK_UART3 28 +#define CLK_UART4_SRC 29 +#define CLK_UART4_FRAC 30 +#define SCLK_UART4 31 +#define CLK_UART5_SRC 32 +#define CLK_UART5_FRAC 33 +#define SCLK_UART5 34 +#define CLK_UART6_SRC 35 +#define CLK_UART6_FRAC 36 +#define SCLK_UART6 37 +#define CLK_UART7_SRC 38 +#define CLK_UART7_FRAC 39 +#define SCLK_UART7 40 +#define CLK_I2S0_2CH_SRC 41 +#define CLK_I2S0_2CH_FRAC 42 +#define MCLK_I2S0_2CH_SAI_SRC 43 +#define CLK_I2S3_8CH_SRC 44 +#define CLK_I2S3_8CH_FRAC 45 +#define MCLK_I2S3_8CH_SAI_SRC 46 +#define CLK_I2S1_8CH_SRC 47 +#define CLK_I2S1_8CH_FRAC 48 +#define MCLK_I2S1_8CH_SAI_SRC 49 +#define CLK_I2S2_2CH_SRC 50 +#define CLK_I2S2_2CH_FRAC 51 +#define MCLK_I2S2_2CH_SAI_SRC 52 +#define CLK_SPDIF_SRC 53 +#define CLK_SPDIF_FRAC 54 +#define MCLK_SPDIF_SRC 55 +#define DCLK_VOP_SRC0 56 +#define DCLK_VOP_SRC1 57 +#define CLK_HSM 58 +#define CLK_CORE_SRC_ACS 59 +#define CLK_CORE_SRC_PVTMUX 60 +#define CLK_CORE_SRC 61 +#define CLK_CORE 62 +#define ACLK_M_CORE_BIU 63 +#define CLK_CORE_PVTPLL_SRC 64 +#define PCLK_DBG 65 +#define SWCLKTCK 66 +#define CLK_SCANHS_CORE 67 +#define CLK_SCANHS_ACLKM_CORE 68 +#define CLK_SCANHS_PCLK_DBG 69 +#define CLK_SCANHS_PCLK_CPU_BIU 70 +#define PCLK_CPU_ROOT 71 +#define PCLK_CORE_GRF 72 +#define PCLK_DAPLITE_BIU 73 +#define PCLK_CPU_BIU 74 +#define CLK_REF_PVTPLL_CORE 75 +#define ACLK_BUS_VOPGL_ROOT 76 +#define ACLK_BUS_VOPGL_BIU 77 +#define ACLK_BUS_H_ROOT 78 +#define ACLK_BUS_H_BIU 79 +#define ACLK_BUS_ROOT 80 +#define HCLK_BUS_ROOT 81 +#define PCLK_BUS_ROOT 82 +#define ACLK_BUS_M_ROOT 83 +#define ACLK_SYSMEM_BIU 84 +#define CLK_TIMER_ROOT 85 +#define ACLK_BUS_BIU 86 +#define HCLK_BUS_BIU 87 +#define PCLK_BUS_BIU 88 +#define PCLK_DFT2APB 89 +#define PCLK_BUS_GRF 90 +#define ACLK_BUS_M_BIU 91 +#define ACLK_GIC 92 +#define ACLK_SPINLOCK 93 +#define ACLK_DMAC 94 +#define PCLK_TIMER 95 +#define CLK_TIMER0 96 +#define CLK_TIMER1 97 +#define CLK_TIMER2 98 +#define CLK_TIMER3 99 +#define CLK_TIMER4 100 +#define CLK_TIMER5 101 +#define PCLK_JDBCK_DAP 102 +#define CLK_JDBCK_DAP 103 +#define PCLK_WDT_NS 104 +#define TCLK_WDT_NS 105 +#define HCLK_TRNG_NS 106 +#define PCLK_UART0 107 +#define PCLK_DMA2DDR 108 +#define ACLK_DMA2DDR 109 +#define PCLK_PWM0 110 +#define CLK_PWM0 111 +#define CLK_CAPTURE_PWM0 112 +#define PCLK_PWM1 113 +#define CLK_PWM1 114 +#define CLK_CAPTURE_PWM1 115 +#define PCLK_SCR 116 +#define ACLK_DCF 117 +#define PCLK_INTMUX 118 +#define CLK_PPLL_I 119 +#define CLK_PPLL_MUX 120 +#define CLK_PPLL_100M_MATRIX 121 +#define CLK_PPLL_50M_MATRIX 122 +#define CLK_REF_PCIE_INNER_PHY 123 +#define CLK_REF_PCIE_100M_PHY 124 +#define ACLK_VPU_L_ROOT 125 +#define CLK_GMAC1_VPU_25M 126 +#define CLK_PPLL_125M_MATRIX 127 +#define ACLK_VPU_ROOT 128 +#define HCLK_VPU_ROOT 129 +#define PCLK_VPU_ROOT 130 +#define ACLK_VPU_BIU 131 +#define HCLK_VPU_BIU 132 +#define PCLK_VPU_BIU 133 +#define ACLK_VPU 134 +#define HCLK_VPU 135 +#define PCLK_CRU_PCIE 136 +#define PCLK_VPU_GRF 137 +#define HCLK_SFC 138 +#define SCLK_SFC 139 +#define CCLK_SRC_EMMC 140 +#define HCLK_EMMC 141 +#define ACLK_EMMC 142 +#define BCLK_EMMC 143 +#define TCLK_EMMC 144 +#define PCLK_GPIO1 145 +#define DBCLK_GPIO1 146 +#define ACLK_VPU_L_BIU 147 +#define PCLK_VPU_IOC 148 +#define HCLK_SAI_I2S0 149 +#define MCLK_SAI_I2S0 150 +#define HCLK_SAI_I2S2 151 +#define MCLK_SAI_I2S2 152 +#define PCLK_ACODEC 153 +#define MCLK_ACODEC_TX 154 +#define PCLK_GPIO3 155 +#define DBCLK_GPIO3 156 +#define PCLK_SPI1 157 +#define CLK_SPI1 158 +#define SCLK_IN_SPI1 159 +#define PCLK_UART2 160 +#define PCLK_UART5 161 +#define PCLK_UART6 162 +#define PCLK_UART7 163 +#define PCLK_I2C3 164 +#define CLK_I2C3 165 +#define PCLK_I2C5 166 +#define CLK_I2C5 167 +#define PCLK_I2C6 168 +#define CLK_I2C6 169 +#define ACLK_MAC_VPU 170 +#define PCLK_MAC_VPU 171 +#define CLK_GMAC1_RMII_VPU 172 +#define CLK_GMAC1_SRC_VPU 173 +#define PCLK_PCIE 174 +#define CLK_PCIE_AUX 175 +#define ACLK_PCIE 176 +#define HCLK_PCIE_SLV 177 +#define HCLK_PCIE_DBI 178 +#define PCLK_PCIE_PHY 179 +#define PCLK_PIPE_GRF 180 +#define CLK_PIPE_USB3OTG_COMBO 181 +#define CLK_UTMI_USB3OTG 182 +#define CLK_PCIE_PIPE_PHY 183 +#define CCLK_SRC_SDIO0 184 +#define HCLK_SDIO0 185 +#define CCLK_SRC_SDIO1 186 +#define HCLK_SDIO1 187 +#define CLK_TS_0 188 +#define CLK_TS_1 189 +#define PCLK_CAN2 190 +#define CLK_CAN2 191 +#define PCLK_CAN3 192 +#define CLK_CAN3 193 +#define PCLK_SARADC 194 +#define CLK_SARADC 195 +#define PCLK_TSADC 196 +#define CLK_TSADC 197 +#define CLK_TSADC_TSEN 198 +#define ACLK_USB3OTG 199 +#define CLK_REF_USB3OTG 200 +#define CLK_SUSPEND_USB3OTG 201 +#define ACLK_GPU_ROOT 202 +#define PCLK_GPU_ROOT 203 +#define ACLK_GPU_BIU 204 +#define PCLK_GPU_BIU 205 +#define ACLK_GPU 206 +#define CLK_GPU_PVTPLL_SRC 207 +#define ACLK_GPU_MALI 208 +#define HCLK_RKVENC_ROOT 209 +#define ACLK_RKVENC_ROOT 210 +#define PCLK_RKVENC_ROOT 211 +#define HCLK_RKVENC_BIU 212 +#define ACLK_RKVENC_BIU 213 +#define PCLK_RKVENC_BIU 214 +#define HCLK_RKVENC 215 +#define ACLK_RKVENC 216 +#define CLK_CORE_RKVENC 217 +#define HCLK_SAI_I2S1 218 +#define MCLK_SAI_I2S1 219 +#define PCLK_I2C1 220 +#define CLK_I2C1 221 +#define PCLK_I2C0 222 +#define CLK_I2C0 223 +#define CLK_UART_JTAG 224 +#define PCLK_SPI0 225 +#define CLK_SPI0 226 +#define SCLK_IN_SPI0 227 +#define PCLK_GPIO4 228 +#define DBCLK_GPIO4 229 +#define PCLK_RKVENC_IOC 230 +#define HCLK_SPDIF 231 +#define MCLK_SPDIF 232 +#define HCLK_PDM 233 +#define MCLK_PDM 234 +#define PCLK_UART1 235 +#define PCLK_UART3 236 +#define PCLK_RKVENC_GRF 237 +#define PCLK_CAN0 238 +#define CLK_CAN0 239 +#define PCLK_CAN1 240 +#define CLK_CAN1 241 +#define ACLK_VO_ROOT 242 +#define HCLK_VO_ROOT 243 +#define PCLK_VO_ROOT 244 +#define ACLK_VO_BIU 245 +#define HCLK_VO_BIU 246 +#define PCLK_VO_BIU 247 +#define HCLK_RGA2E 248 +#define ACLK_RGA2E 249 +#define CLK_CORE_RGA2E 250 +#define HCLK_VDPP 251 +#define ACLK_VDPP 252 +#define CLK_CORE_VDPP 253 +#define PCLK_VO_GRF 254 +#define PCLK_CRU 255 +#define ACLK_VOP_ROOT 256 +#define ACLK_VOP_BIU 257 +#define HCLK_VOP 258 +#define DCLK_VOP0 259 +#define DCLK_VOP1 260 +#define ACLK_VOP 261 +#define PCLK_HDMI 262 +#define CLK_SFR_HDMI 263 +#define CLK_CEC_HDMI 264 +#define CLK_SPDIF_HDMI 265 +#define CLK_HDMIPHY_TMDSSRC 266 +#define CLK_HDMIPHY_PREP 267 +#define PCLK_HDMIPHY 268 +#define HCLK_HDCP_KEY 269 +#define ACLK_HDCP 270 +#define HCLK_HDCP 271 +#define PCLK_HDCP 272 +#define HCLK_CVBS 273 +#define DCLK_CVBS 274 +#define DCLK_4X_CVBS 275 +#define ACLK_JPEG_DECODER 276 +#define HCLK_JPEG_DECODER 277 +#define ACLK_VO_L_ROOT 278 +#define ACLK_VO_L_BIU 279 +#define ACLK_MAC_VO 280 +#define PCLK_MAC_VO 281 +#define CLK_GMAC0_SRC 282 +#define CLK_GMAC0_RMII_50M 283 +#define CLK_GMAC0_TX 284 +#define CLK_GMAC0_RX 285 +#define ACLK_JPEG_ROOT 286 +#define ACLK_JPEG_BIU 287 +#define HCLK_SAI_I2S3 288 +#define MCLK_SAI_I2S3 289 +#define CLK_MACPHY 290 +#define PCLK_VCDCPHY 291 +#define PCLK_GPIO2 292 +#define DBCLK_GPIO2 293 +#define PCLK_VO_IOC 294 +#define CCLK_SRC_SDMMC0 295 +#define HCLK_SDMMC0 296 +#define PCLK_OTPC_NS 297 +#define CLK_SBPI_OTPC_NS 298 +#define CLK_USER_OTPC_NS 299 +#define CLK_HDMIHDP0 300 +#define HCLK_USBHOST 301 +#define HCLK_USBHOST_ARB 302 +#define CLK_USBHOST_OHCI 303 +#define CLK_USBHOST_UTMI 304 +#define PCLK_UART4 305 +#define PCLK_I2C4 306 +#define CLK_I2C4 307 +#define PCLK_I2C7 308 +#define CLK_I2C7 309 +#define PCLK_USBPHY 310 +#define CLK_REF_USBPHY 311 +#define HCLK_RKVDEC_ROOT 312 +#define ACLK_RKVDEC_ROOT_NDFT 313 +#define PCLK_DDRPHY_CRU 314 +#define HCLK_RKVDEC_BIU 315 +#define ACLK_RKVDEC_BIU 316 +#define ACLK_RKVDEC 317 +#define HCLK_RKVDEC 318 +#define CLK_HEVC_CA_RKVDEC 319 +#define ACLK_RKVDEC_PVTMUX_ROOT 320 +#define CLK_RKVDEC_PVTPLL_SRC 321 +#define PCLK_DDR_ROOT 322 +#define PCLK_DDR_BIU 323 +#define PCLK_DDRC 324 +#define PCLK_DDRMON 325 +#define CLK_TIMER_DDRMON 326 +#define PCLK_MSCH_BIU 327 +#define PCLK_DDR_GRF 328 +#define PCLK_DDR_HWLP 329 +#define PCLK_DDRPHY 330 +#define CLK_MSCH_BIU 331 +#define ACLK_DDR_UPCTL 332 +#define CLK_DDR_UPCTL 333 +#define CLK_DDRMON 334 +#define ACLK_DDR_SCRAMBLE 335 +#define ACLK_SPLIT 336 +#define CLK_DDRC_SRC 337 +#define CLK_DDR_PHY 338 +#define PCLK_OTPC_S 339 +#define CLK_SBPI_OTPC_S 340 +#define CLK_USER_OTPC_S 341 +#define PCLK_KEYREADER 342 +#define PCLK_BUS_SGRF 343 +#define PCLK_STIMER 344 +#define CLK_STIMER0 345 +#define CLK_STIMER1 346 +#define PCLK_WDT_S 347 +#define TCLK_WDT_S 348 +#define HCLK_TRNG_S 349 +#define HCLK_BOOTROM 350 +#define PCLK_DCF 351 +#define ACLK_SYSMEM 352 +#define HCLK_TSP 353 +#define ACLK_TSP 354 +#define CLK_CORE_TSP 355 +#define CLK_OTPC_ARB 356 +#define PCLK_OTP_MASK 357 +#define CLK_PMC_OTP 358 +#define PCLK_PMU_ROOT 359 +#define HCLK_PMU_ROOT 360 +#define PCLK_I2C2 361 +#define CLK_I2C2 362 +#define HCLK_PMU_BIU 363 +#define PCLK_PMU_BIU 364 +#define FCLK_MCU 365 +#define RTC_CLK_MCU 366 +#define PCLK_OSCCHK 367 +#define CLK_PMU_MCU_JTAG 368 +#define PCLK_PMU 369 +#define PCLK_GPIO0 370 +#define DBCLK_GPIO0 371 +#define XIN_OSC0_DIV 372 +#define CLK_DEEPSLOW 373 +#define CLK_DDR_FAIL_SAFE 374 +#define PCLK_PMU_HP_TIMER 375 +#define CLK_PMU_HP_TIMER 376 +#define CLK_PMU_32K_HP_TIMER 377 +#define PCLK_PMU_IOC 378 +#define PCLK_PMU_CRU 379 +#define PCLK_PMU_GRF 380 +#define PCLK_PMU_WDT 381 +#define TCLK_PMU_WDT 382 +#define PCLK_PMU_MAILBOX 383 +#define PCLK_SCRKEYGEN 384 +#define CLK_SCRKEYGEN 385 +#define CLK_PVTM_OSCCHK 386 +#define CLK_REFOUT 387 +#define CLK_PVTM_PMU 388 +#define PCLK_PVTM_PMU 389 +#define PCLK_PMU_SGRF 390 +#define HCLK_PMU_SRAM 391 +#define CLK_UART0 392 +#define CLK_UART1 393 +#define CLK_UART2 394 +#define CLK_UART3 395 +#define CLK_UART4 396 +#define CLK_UART5 397 +#define CLK_UART6 398 +#define CLK_UART7 399 +#define MCLK_I2S0_2CH_SAI_SRC_PRE 400 +#define MCLK_I2S1_8CH_SAI_SRC_PRE 401 +#define MCLK_I2S2_2CH_SAI_SRC_PRE 402 +#define MCLK_I2S3_8CH_SAI_SRC_PRE 403 +#define MCLK_SDPDIF_SRC_PRE 404 + +/* scmi-clocks indices */ +#define SCMI_PCLK_KEYREADER 0 +#define SCMI_HCLK_KLAD 1 +#define SCMI_PCLK_KLAD 2 +#define SCMI_HCLK_TRNG_S 3 +#define SCMI_HCLK_CRYPTO_S 4 +#define SCMI_PCLK_WDT_S 5 +#define SCMI_TCLK_WDT_S 6 +#define SCMI_PCLK_STIMER 7 +#define SCMI_CLK_STIMER0 8 +#define SCMI_CLK_STIMER1 9 +#define SCMI_PCLK_OTP_MASK 10 +#define SCMI_PCLK_OTPC_S 11 +#define SCMI_CLK_SBPI_OTPC_S 12 +#define SCMI_CLK_USER_OTPC_S 13 +#define SCMI_CLK_PMC_OTP 14 +#define SCMI_CLK_OTPC_ARB 15 +#define SCMI_CLK_CORE_TSP 16 +#define SCMI_ACLK_TSP 17 +#define SCMI_HCLK_TSP 18 +#define SCMI_PCLK_DCF 19 +#define SCMI_CLK_DDR 20 +#define SCMI_CLK_CPU 21 +#define SCMI_CLK_GPU 22 +#define SCMI_CORE_CRYPTO 23 +#define SCMI_ACLK_CRYPTO 24 +#define SCMI_PKA_CRYPTO 25 +#define SCMI_HCLK_CRYPTO 26 +#define SCMI_CORE_CRYPTO_S 27 +#define SCMI_ACLK_CRYPTO_S 28 +#define SCMI_PKA_CRYPTO_S 29 +#define SCMI_CORE_KLAD 30 +#define SCMI_ACLK_KLAD 31 +#define SCMI_HCLK_TRNG 32 + +#endif // _DT_BINDINGS_CLK_ROCKCHIP_RK3528_H diff --git a/include/dt-bindings/clock/rockchip,rk3562-cru.h b/include/dt-bindings/clock/rockchip,rk3562-cru.h new file mode 100644 index 000000000000..a5b0b153209c --- /dev/null +++ b/include/dt-bindings/clock/rockchip,rk3562-cru.h @@ -0,0 +1,379 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2022-2025 Rockchip Electronics Co., Ltd. + * Author: Finley Xiao <finley.xiao@rock-chips.com> + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3562_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3562_H + +/* cru-clocks indices */ + +/* cru plls */ +#define PLL_DMPLL0 0 +#define PLL_APLL 1 +#define PLL_GPLL 2 +#define PLL_VPLL 3 +#define PLL_HPLL 4 +#define PLL_CPLL 5 +#define PLL_DPLL 6 +#define PLL_DMPLL1 7 + +/* cru clocks */ +#define ARMCLK 8 +#define CLK_GPU 9 +#define ACLK_RKNN 10 +#define CLK_DDR 11 +#define CLK_MATRIX_50M_SRC 12 +#define CLK_MATRIX_100M_SRC 13 +#define CLK_MATRIX_125M_SRC 14 +#define CLK_MATRIX_200M_SRC 15 +#define CLK_MATRIX_300M_SRC 16 +#define ACLK_TOP 17 +#define ACLK_TOP_VIO 18 +#define CLK_CAM0_OUT2IO 19 +#define CLK_CAM1_OUT2IO 20 +#define CLK_CAM2_OUT2IO 21 +#define CLK_CAM3_OUT2IO 22 +#define ACLK_BUS 23 +#define HCLK_BUS 24 +#define PCLK_BUS 25 +#define PCLK_I2C1 26 +#define PCLK_I2C2 27 +#define PCLK_I2C3 28 +#define PCLK_I2C4 29 +#define PCLK_I2C5 30 +#define CLK_I2C 31 +#define CLK_I2C1 32 +#define CLK_I2C2 33 +#define CLK_I2C3 34 +#define CLK_I2C4 35 +#define CLK_I2C5 36 +#define DCLK_BUS_GPIO 37 +#define DCLK_BUS_GPIO3 38 +#define DCLK_BUS_GPIO4 39 +#define PCLK_TIMER 40 +#define CLK_TIMER0 41 +#define CLK_TIMER1 42 +#define CLK_TIMER2 43 +#define CLK_TIMER3 44 +#define CLK_TIMER4 45 +#define CLK_TIMER5 46 +#define PCLK_STIMER 47 +#define CLK_STIMER0 48 +#define CLK_STIMER1 49 +#define PCLK_WDTNS 50 +#define CLK_WDTNS 51 +#define PCLK_GRF 52 +#define PCLK_SGRF 53 +#define PCLK_MAILBOX 54 +#define PCLK_INTC 55 +#define ACLK_BUS_GIC400 56 +#define ACLK_BUS_SPINLOCK 57 +#define ACLK_DCF 58 +#define PCLK_DCF 59 +#define FCLK_BUS_CM0_CORE 60 +#define CLK_BUS_CM0_RTC 61 +#define HCLK_ICACHE 62 +#define HCLK_DCACHE 63 +#define PCLK_TSADC 64 +#define CLK_TSADC 65 +#define CLK_TSADC_TSEN 66 +#define PCLK_DFT2APB 67 +#define CLK_SARADC_VCCIO156 68 +#define PCLK_GMAC 69 +#define ACLK_GMAC 70 +#define CLK_GMAC_125M_CRU_I 71 +#define CLK_GMAC_50M_CRU_I 72 +#define CLK_GMAC_50M_O 73 +#define CLK_GMAC_ETH_OUT2IO 74 +#define PCLK_APB2ASB_VCCIO156 75 +#define PCLK_TO_VCCIO156 76 +#define PCLK_DSIPHY 77 +#define PCLK_DSITX 78 +#define PCLK_CPU_EMA_DET 79 +#define PCLK_HASH 80 +#define PCLK_TOPCRU 81 +#define PCLK_ASB2APB_VCCIO156 82 +#define PCLK_IOC_VCCIO156 83 +#define PCLK_GPIO3_VCCIO156 84 +#define PCLK_GPIO4_VCCIO156 85 +#define PCLK_SARADC_VCCIO156 86 +#define PCLK_MAC100 87 +#define ACLK_MAC100 89 +#define CLK_MAC100_50M_MATRIX 90 +#define HCLK_CORE 91 +#define PCLK_DDR 92 +#define CLK_MSCH_BRG_BIU 93 +#define PCLK_DDR_HWLP 94 +#define PCLK_DDR_UPCTL 95 +#define PCLK_DDR_PHY 96 +#define PCLK_DDR_DFICTL 97 +#define PCLK_DDR_DMA2DDR 98 +#define PCLK_DDR_MON 99 +#define TMCLK_DDR_MON 100 +#define PCLK_DDR_GRF 101 +#define PCLK_DDR_CRU 102 +#define PCLK_SUBDDR_CRU 103 +#define CLK_GPU_PRE 104 +#define ACLK_GPU_PRE 105 +#define CLK_GPU_BRG 107 +#define CLK_NPU_PRE 108 +#define HCLK_NPU_PRE 109 +#define HCLK_RKNN 111 +#define ACLK_PERI 112 +#define HCLK_PERI 113 +#define PCLK_PERI 114 +#define PCLK_PERICRU 115 +#define HCLK_SAI0 116 +#define CLK_SAI0_SRC 117 +#define CLK_SAI0_FRAC 118 +#define CLK_SAI0 119 +#define MCLK_SAI0 120 +#define MCLK_SAI0_OUT2IO 121 +#define HCLK_SAI1 122 +#define CLK_SAI1_SRC 123 +#define CLK_SAI1_FRAC 124 +#define CLK_SAI1 125 +#define MCLK_SAI1 126 +#define MCLK_SAI1_OUT2IO 127 +#define HCLK_SAI2 128 +#define CLK_SAI2_SRC 129 +#define CLK_SAI2_FRAC 130 +#define CLK_SAI2 131 +#define MCLK_SAI2 132 +#define MCLK_SAI2_OUT2IO 133 +#define HCLK_DSM 134 +#define CLK_DSM 135 +#define HCLK_PDM 136 +#define MCLK_PDM 137 +#define HCLK_SPDIF 138 +#define CLK_SPDIF_SRC 139 +#define CLK_SPDIF_FRAC 140 +#define CLK_SPDIF 141 +#define MCLK_SPDIF 142 +#define HCLK_SDMMC0 143 +#define CCLK_SDMMC0 144 +#define HCLK_SDMMC1 145 +#define CCLK_SDMMC1 146 +#define SCLK_SDMMC0_DRV 147 +#define SCLK_SDMMC0_SAMPLE 148 +#define SCLK_SDMMC1_DRV 149 +#define SCLK_SDMMC1_SAMPLE 150 +#define HCLK_EMMC 151 +#define ACLK_EMMC 152 +#define CCLK_EMMC 153 +#define BCLK_EMMC 154 +#define TMCLK_EMMC 155 +#define SCLK_SFC 156 +#define HCLK_SFC 157 +#define HCLK_USB2HOST 158 +#define HCLK_USB2HOST_ARB 159 +#define PCLK_SPI1 160 +#define CLK_SPI1 161 +#define SCLK_IN_SPI1 162 +#define PCLK_SPI2 163 +#define CLK_SPI2 164 +#define SCLK_IN_SPI2 165 +#define PCLK_UART1 166 +#define PCLK_UART2 167 +#define PCLK_UART3 168 +#define PCLK_UART4 169 +#define PCLK_UART5 170 +#define PCLK_UART6 171 +#define PCLK_UART7 172 +#define PCLK_UART8 173 +#define PCLK_UART9 174 +#define CLK_UART1_SRC 175 +#define CLK_UART1_FRAC 176 +#define CLK_UART1 177 +#define SCLK_UART1 178 +#define CLK_UART2_SRC 179 +#define CLK_UART2_FRAC 180 +#define CLK_UART2 181 +#define SCLK_UART2 182 +#define CLK_UART3_SRC 183 +#define CLK_UART3_FRAC 184 +#define CLK_UART3 185 +#define SCLK_UART3 186 +#define CLK_UART4_SRC 187 +#define CLK_UART4_FRAC 188 +#define CLK_UART4 189 +#define SCLK_UART4 190 +#define CLK_UART5_SRC 191 +#define CLK_UART5_FRAC 192 +#define CLK_UART5 193 +#define SCLK_UART5 194 +#define CLK_UART6_SRC 195 +#define CLK_UART6_FRAC 196 +#define CLK_UART6 197 +#define SCLK_UART6 198 +#define CLK_UART7_SRC 199 +#define CLK_UART7_FRAC 200 +#define CLK_UART7 201 +#define SCLK_UART7 202 +#define CLK_UART8_SRC 203 +#define CLK_UART8_FRAC 204 +#define CLK_UART8 205 +#define SCLK_UART8 206 +#define CLK_UART9_SRC 207 +#define CLK_UART9_FRAC 208 +#define CLK_UART9 209 +#define SCLK_UART9 210 +#define PCLK_PWM1_PERI 211 +#define CLK_PWM1_PERI 212 +#define CLK_CAPTURE_PWM1_PERI 213 +#define PCLK_PWM2_PERI 214 +#define CLK_PWM2_PERI 215 +#define CLK_CAPTURE_PWM2_PERI 216 +#define PCLK_PWM3_PERI 217 +#define CLK_PWM3_PERI 218 +#define CLK_CAPTURE_PWM3_PERI 219 +#define PCLK_CAN0 220 +#define CLK_CAN0 221 +#define PCLK_CAN1 222 +#define CLK_CAN1 223 +#define ACLK_CRYPTO 224 +#define HCLK_CRYPTO 225 +#define PCLK_CRYPTO 226 +#define CLK_CORE_CRYPTO 227 +#define CLK_PKA_CRYPTO 228 +#define HCLK_KLAD 229 +#define PCLK_KEY_READER 230 +#define HCLK_RK_RNG_NS 231 +#define HCLK_RK_RNG_S 232 +#define HCLK_TRNG_NS 233 +#define HCLK_TRNG_S 234 +#define HCLK_CRYPTO_S 235 +#define PCLK_PERI_WDT 236 +#define TCLK_PERI_WDT 237 +#define ACLK_SYSMEM 238 +#define HCLK_BOOTROM 239 +#define PCLK_PERI_GRF 240 +#define ACLK_DMAC 241 +#define ACLK_RKDMAC 242 +#define PCLK_OTPC_NS 243 +#define CLK_SBPI_OTPC_NS 244 +#define CLK_USER_OTPC_NS 245 +#define PCLK_OTPC_S 246 +#define CLK_SBPI_OTPC_S 247 +#define CLK_USER_OTPC_S 248 +#define CLK_OTPC_ARB 249 +#define PCLK_OTPPHY 250 +#define PCLK_USB2PHY 251 +#define PCLK_PIPEPHY 252 +#define PCLK_SARADC 253 +#define CLK_SARADC 254 +#define PCLK_IOC_VCCIO234 255 +#define PCLK_PERI_GPIO1 256 +#define PCLK_PERI_GPIO2 257 +#define DCLK_PERI_GPIO 258 +#define DCLK_PERI_GPIO1 259 +#define DCLK_PERI_GPIO2 260 +#define ACLK_PHP 261 +#define PCLK_PHP 262 +#define ACLK_PCIE20_MST 263 +#define ACLK_PCIE20_SLV 264 +#define ACLK_PCIE20_DBI 265 +#define PCLK_PCIE20 266 +#define CLK_PCIE20_AUX 267 +#define ACLK_USB3OTG 268 +#define CLK_USB3OTG_SUSPEND 269 +#define CLK_USB3OTG_REF 270 +#define CLK_PIPEPHY_REF_FUNC 271 +#define CLK_200M_PMU 272 +#define CLK_RTC_32K 273 +#define CLK_RTC32K_FRAC 274 +#define BUSCLK_PDPMU0 275 +#define PCLK_PMU0_CRU 276 +#define PCLK_PMU0_PMU 277 +#define CLK_PMU0_PMU 278 +#define PCLK_PMU0_HP_TIMER 279 +#define CLK_PMU0_HP_TIMER 280 +#define CLK_PMU0_32K_HP_TIMER 281 +#define PCLK_PMU0_PVTM 282 +#define CLK_PMU0_PVTM 283 +#define PCLK_IOC_PMUIO 284 +#define PCLK_PMU0_GPIO0 285 +#define DBCLK_PMU0_GPIO0 286 +#define PCLK_PMU0_GRF 287 +#define PCLK_PMU0_SGRF 288 +#define CLK_DDR_FAIL_SAFE 289 +#define PCLK_PMU0_SCRKEYGEN 290 +#define PCLK_PMU1_CRU 291 +#define HCLK_PMU1_MEM 292 +#define PCLK_PMU0_I2C0 293 +#define CLK_PMU0_I2C0 294 +#define PCLK_PMU1_UART0 295 +#define CLK_PMU1_UART0_SRC 296 +#define CLK_PMU1_UART0_FRAC 297 +#define CLK_PMU1_UART0 298 +#define SCLK_PMU1_UART0 299 +#define PCLK_PMU1_SPI0 300 +#define CLK_PMU1_SPI0 301 +#define SCLK_IN_PMU1_SPI0 302 +#define PCLK_PMU1_PWM0 303 +#define CLK_PMU1_PWM0 304 +#define CLK_CAPTURE_PMU1_PWM0 305 +#define CLK_PMU1_WIFI 306 +#define FCLK_PMU1_CM0_CORE 307 +#define CLK_PMU1_CM0_RTC 308 +#define PCLK_PMU1_WDTNS 309 +#define CLK_PMU1_WDTNS 310 +#define PCLK_PMU1_MAILBOX 311 +#define CLK_PIPEPHY_DIV 312 +#define CLK_PIPEPHY_XIN24M 313 +#define CLK_PIPEPHY_REF 314 +#define CLK_24M_SSCSRC 315 +#define CLK_USB2PHY_XIN24M 316 +#define CLK_USB2PHY_REF 317 +#define CLK_MIPIDSIPHY_XIN24M 318 +#define CLK_MIPIDSIPHY_REF 319 +#define ACLK_RGA_PRE 320 +#define HCLK_RGA_PRE 321 +#define ACLK_RGA 322 +#define HCLK_RGA 323 +#define CLK_RGA_CORE 324 +#define ACLK_JDEC 325 +#define HCLK_JDEC 326 +#define ACLK_VDPU_PRE 327 +#define CLK_RKVDEC_HEVC_CA 328 +#define HCLK_VDPU_PRE 329 +#define ACLK_RKVDEC 330 +#define HCLK_RKVDEC 331 +#define CLK_RKVENC_CORE 332 +#define ACLK_VEPU_PRE 333 +#define HCLK_VEPU_PRE 334 +#define ACLK_RKVENC 335 +#define HCLK_RKVENC 336 +#define ACLK_VI 337 +#define HCLK_VI 338 +#define PCLK_VI 339 +#define ACLK_ISP 340 +#define HCLK_ISP 341 +#define CLK_ISP 342 +#define ACLK_VICAP 343 +#define HCLK_VICAP 344 +#define DCLK_VICAP 345 +#define CSIRX0_CLK_DATA 346 +#define CSIRX1_CLK_DATA 347 +#define CSIRX2_CLK_DATA 348 +#define CSIRX3_CLK_DATA 349 +#define PCLK_CSIHOST0 350 +#define PCLK_CSIHOST1 351 +#define PCLK_CSIHOST2 352 +#define PCLK_CSIHOST3 353 +#define PCLK_CSIPHY0 354 +#define PCLK_CSIPHY1 355 +#define ACLK_VO_PRE 356 +#define HCLK_VO_PRE 357 +#define ACLK_VOP 358 +#define HCLK_VOP 359 +#define DCLK_VOP 360 +#define DCLK_VOP1 361 +#define ACLK_CRYPTO_S 362 +#define PCLK_CRYPTO_S 363 +#define CLK_CORE_CRYPTO_S 364 +#define CLK_PKA_CRYPTO_S 365 + +#endif diff --git a/include/dt-bindings/clock/samsung,exynos2200-cmu.h b/include/dt-bindings/clock/samsung,exynos2200-cmu.h new file mode 100644 index 000000000000..310552be0c8c --- /dev/null +++ b/include/dt-bindings/clock/samsung,exynos2200-cmu.h @@ -0,0 +1,431 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2025 Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> + * Author: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> + * + * Device Tree binding constants for Exynos2200 clock controller. + */ + +#ifndef _DT_BINDINGS_CLOCK_EXYNOS2200_H +#define _DT_BINDINGS_CLOCK_EXYNOS2200_H + +/* CMU_TOP */ +#define CLK_FOUT_SHARED0_PLL 1 +#define CLK_FOUT_SHARED1_PLL 2 +#define CLK_FOUT_SHARED2_PLL 3 +#define CLK_FOUT_SHARED3_PLL 4 +#define CLK_FOUT_SHARED4_PLL 5 +#define CLK_FOUT_MMC_PLL 6 +#define CLK_FOUT_SHARED_MIF_PLL 7 + +#define CLK_MOUT_CMU_CP_MPLL_CLK_D2_USER 8 +#define CLK_MOUT_CMU_CP_MPLL_CLK_USER 9 +#define CLK_MOUT_CMU_AUD_AUDIF0 10 +#define CLK_MOUT_CMU_AUD_AUDIF1 11 +#define CLK_MOUT_CMU_AUD_CPU 12 +#define CLK_MOUT_CMU_CPUCL0_DBG_NOC 13 +#define CLK_MOUT_CMU_CPUCL0_SWITCH 14 +#define CLK_MOUT_CMU_CPUCL1_SWITCH 15 +#define CLK_MOUT_CMU_CPUCL2_SWITCH 16 +#define CLK_MOUT_CMU_DNC_NOC 17 +#define CLK_MOUT_CMU_DPUB_NOC 18 +#define CLK_MOUT_CMU_DPUF_NOC 19 +#define CLK_MOUT_CMU_DSP_NOC 20 +#define CLK_MOUT_CMU_DSU_SWITCH 21 +#define CLK_MOUT_CMU_G3D_SWITCH 22 +#define CLK_MOUT_CMU_GNPU_NOC 23 +#define CLK_MOUT_CMU_UFS_MMC_CARD 24 +#define CLK_MOUT_CMU_M2M_NOC 25 +#define CLK_MOUT_CMU_NOCL0_NOC 26 +#define CLK_MOUT_CMU_NOCL1A_NOC 27 +#define CLK_MOUT_CMU_NOCL1B_NOC0 28 +#define CLK_MOUT_CMU_NOCL1C_NOC 29 +#define CLK_MOUT_CMU_SDMA_NOC 30 +#define CLK_MOUT_CMU_CP_HISPEEDY_CLK 31 +#define CLK_MOUT_CMU_CP_SHARED0_CLK 32 +#define CLK_MOUT_CMU_CP_SHARED2_CLK 33 +#define CLK_MOUT_CMU_MUX_ALIVE_NOC 34 +#define CLK_MOUT_CMU_MUX_AUD_AUDIF0 35 +#define CLK_MOUT_CMU_MUX_AUD_AUDIF1 36 +#define CLK_MOUT_CMU_MUX_AUD_CPU 37 +#define CLK_MOUT_CMU_MUX_AUD_NOC 38 +#define CLK_MOUT_CMU_MUX_BRP_NOC 39 +#define CLK_MOUT_CMU_MUX_CIS_CLK0 40 +#define CLK_MOUT_CMU_MUX_CIS_CLK1 41 +#define CLK_MOUT_CMU_MUX_CIS_CLK2 42 +#define CLK_MOUT_CMU_MUX_CIS_CLK3 43 +#define CLK_MOUT_CMU_MUX_CIS_CLK4 44 +#define CLK_MOUT_CMU_MUX_CIS_CLK5 45 +#define CLK_MOUT_CMU_MUX_CIS_CLK6 46 +#define CLK_MOUT_CMU_MUX_CIS_CLK7 47 +#define CLK_MOUT_CMU_MUX_CMU_BOOST 48 +#define CLK_MOUT_CMU_MUX_CMU_BOOST_CAM 49 +#define CLK_MOUT_CMU_MUX_CMU_BOOST_CPU 50 +#define CLK_MOUT_CMU_MUX_CMU_BOOST_MIF 51 +#define CLK_MOUT_CMU_MUX_CPUCL0_DBG_NOC 52 +#define CLK_MOUT_CMU_MUX_CPUCL0_NOCP 53 +#define CLK_MOUT_CMU_MUX_CPUCL0_SWITCH 54 +#define CLK_MOUT_CMU_MUX_CPUCL1_SWITCH 55 +#define CLK_MOUT_CMU_MUX_CPUCL2_SWITCH 56 +#define CLK_MOUT_CMU_MUX_CSIS_DCPHY 57 +#define CLK_MOUT_CMU_MUX_CSIS_NOC 58 +#define CLK_MOUT_CMU_MUX_CSIS_OIS_MCU 59 +#define CLK_MOUT_CMU_MUX_CSTAT_NOC 60 +#define CLK_MOUT_CMU_MUX_DNC_NOC 61 +#define CLK_MOUT_CMU_MUX_DPUB 62 +#define CLK_MOUT_CMU_MUX_DPUB_ALT 63 +#define CLK_MOUT_CMU_MUX_DPUB_DSIM 64 +#define CLK_MOUT_CMU_MUX_DPUF 65 +#define CLK_MOUT_CMU_MUX_DPUF_ALT 66 +#define CLK_MOUT_CMU_MUX_DSP_NOC 67 +#define CLK_MOUT_CMU_MUX_DSU_SWITCH 68 +#define CLK_MOUT_CMU_MUX_G3D_NOCP 69 +#define CLK_MOUT_CMU_MUX_G3D_SWITCH 70 +#define CLK_MOUT_CMU_MUX_GNPU_NOC 71 +#define CLK_MOUT_CMU_MUX_HSI0_DPGTC 72 +#define CLK_MOUT_CMU_MUX_HSI0_DPOSC 73 +#define CLK_MOUT_CMU_MUX_HSI0_NOC 74 +#define CLK_MOUT_CMU_MUX_HSI0_USB32DRD 75 +#define CLK_MOUT_CMU_MUX_UFS_MMC_CARD 76 +#define CLK_MOUT_CMU_MUX_HSI1_NOC 77 +#define CLK_MOUT_CMU_MUX_HSI1_PCIE 78 +#define CLK_MOUT_CMU_MUX_UFS_UFS_EMBD 79 +#define CLK_MOUT_CMU_MUX_LME_LME 80 +#define CLK_MOUT_CMU_MUX_LME_NOC 81 +#define CLK_MOUT_CMU_MUX_M2M_NOC 82 +#define CLK_MOUT_CMU_MUX_MCSC_MCSC 83 +#define CLK_MOUT_CMU_MUX_MCSC_NOC 84 +#define CLK_MOUT_CMU_MUX_MFC0_MFC0 85 +#define CLK_MOUT_CMU_MUX_MFC0_WFD 86 +#define CLK_MOUT_CMU_MUX_MFC1_MFC1 87 +#define CLK_MOUT_CMU_MUX_MIF_NOCP 88 +#define CLK_MOUT_CMU_MUX_MIF_SWITCH 89 +#define CLK_MOUT_CMU_MUX_NOCL0_NOC 90 +#define CLK_MOUT_CMU_MUX_NOCL1A_NOC 91 +#define CLK_MOUT_CMU_MUX_NOCL1B_NOC0 92 +#define CLK_MOUT_CMU_MUX_NOCL1B_NOC1 93 +#define CLK_MOUT_CMU_MUX_NOCL1C_NOC 94 +#define CLK_MOUT_CMU_MUX_PERIC0_IP0 95 +#define CLK_MOUT_CMU_MUX_PERIC0_IP1 96 +#define CLK_MOUT_CMU_MUX_PERIC0_NOC 97 +#define CLK_MOUT_CMU_MUX_PERIC1_IP0 98 +#define CLK_MOUT_CMU_MUX_PERIC1_IP1 99 +#define CLK_MOUT_CMU_MUX_PERIC1_NOC 100 +#define CLK_MOUT_CMU_MUX_PERIC2_IP0 101 +#define CLK_MOUT_CMU_MUX_PERIC2_IP1 102 +#define CLK_MOUT_CMU_MUX_PERIC2_NOC 103 +#define CLK_MOUT_CMU_MUX_PERIS_GIC 104 +#define CLK_MOUT_CMU_MUX_PERIS_NOC 105 +#define CLK_MOUT_CMU_MUX_SDMA_NOC 106 +#define CLK_MOUT_CMU_MUX_SSP_NOC 107 +#define CLK_MOUT_CMU_MUX_VTS_DMIC 108 +#define CLK_MOUT_CMU_MUX_YUVP_NOC 109 +#define CLK_MOUT_CMU_MUX_CMU_CMUREF 110 +#define CLK_MOUT_CMU_MUX_CP_HISPEEDY_CLK 111 +#define CLK_MOUT_CMU_MUX_CP_SHARED0_CLK 112 +#define CLK_MOUT_CMU_MUX_CP_SHARED1_CLK 113 +#define CLK_MOUT_CMU_MUX_CP_SHARED2_CLK 114 +#define CLK_MOUT_CMU_M2M_FRC 115 +#define CLK_MOUT_CMU_MCSC_MCSC 116 +#define CLK_MOUT_CMU_MCSC_NOC 117 +#define CLK_MOUT_CMU_MUX_M2M_FRC 118 +#define CLK_MOUT_CMU_MUX_UFS_NOC 119 + +#define CLK_DOUT_CMU_ALIVE_NOC 120 +#define CLK_DOUT_CMU_AUD_NOC 121 +#define CLK_DOUT_CMU_BRP_NOC 122 +#define CLK_DOUT_CMU_CMU_BOOST 123 +#define CLK_DOUT_CMU_CMU_BOOST_CAM 124 +#define CLK_DOUT_CMU_CMU_BOOST_CPU 125 +#define CLK_DOUT_CMU_CMU_BOOST_MIF 126 +#define CLK_DOUT_CMU_CPUCL0_NOCP 127 +#define CLK_DOUT_CMU_CSIS_DCPHY 128 +#define CLK_DOUT_CMU_CSIS_NOC 129 +#define CLK_DOUT_CMU_CSIS_OIS_MCU 130 +#define CLK_DOUT_CMU_CSTAT_NOC 131 +#define CLK_DOUT_CMU_DPUB_DSIM 132 +#define CLK_DOUT_CMU_LME_LME 133 +#define CLK_DOUT_CMU_G3D_NOCP 134 +#define CLK_DOUT_CMU_HSI0_DPGTC 135 +#define CLK_DOUT_CMU_HSI0_DPOSC 136 +#define CLK_DOUT_CMU_HSI0_NOC 137 +#define CLK_DOUT_CMU_HSI0_USB32DRD 138 +#define CLK_DOUT_CMU_HSI1_NOC 139 +#define CLK_DOUT_CMU_HSI1_PCIE 140 +#define CLK_DOUT_CMU_UFS_UFS_EMBD 141 +#define CLK_DOUT_CMU_LME_NOC 142 +#define CLK_DOUT_CMU_MFC0_MFC0 143 +#define CLK_DOUT_CMU_MFC0_WFD 144 +#define CLK_DOUT_CMU_MFC1_MFC1 145 +#define CLK_DOUT_CMU_MIF_NOCP 146 +#define CLK_DOUT_CMU_NOCL1B_NOC1 147 +#define CLK_DOUT_CMU_PERIC0_IP0 148 +#define CLK_DOUT_CMU_PERIC0_IP1 149 +#define CLK_DOUT_CMU_PERIC0_NOC 150 +#define CLK_DOUT_CMU_PERIC1_IP0 151 +#define CLK_DOUT_CMU_PERIC1_IP1 152 +#define CLK_DOUT_CMU_PERIC1_NOC 153 +#define CLK_DOUT_CMU_PERIC2_IP0 154 +#define CLK_DOUT_CMU_PERIC2_IP1 155 +#define CLK_DOUT_CMU_PERIC2_NOC 156 +#define CLK_DOUT_CMU_PERIS_GIC 157 +#define CLK_DOUT_CMU_PERIS_NOC 158 +#define CLK_DOUT_CMU_SSP_NOC 159 +#define CLK_DOUT_CMU_VTS_DMIC 160 +#define CLK_DOUT_CMU_YUVP_NOC 161 +#define CLK_DOUT_CMU_CP_SHARED1_CLK 162 +#define CLK_DOUT_CMU_DIV_AUD_AUDIF0 163 +#define CLK_DOUT_CMU_DIV_AUD_AUDIF0_SM 164 +#define CLK_DOUT_CMU_DIV_AUD_AUDIF1 165 +#define CLK_DOUT_CMU_DIV_AUD_AUDIF1_SM 166 +#define CLK_DOUT_CMU_DIV_AUD_CPU 167 +#define CLK_DOUT_CMU_DIV_AUD_CPU_SM 168 +#define CLK_DOUT_CMU_DIV_CIS_CLK0 169 +#define CLK_DOUT_CMU_DIV_CIS_CLK1 170 +#define CLK_DOUT_CMU_DIV_CIS_CLK2 171 +#define CLK_DOUT_CMU_DIV_CIS_CLK3 172 +#define CLK_DOUT_CMU_DIV_CIS_CLK4 173 +#define CLK_DOUT_CMU_DIV_CIS_CLK5 174 +#define CLK_DOUT_CMU_DIV_CIS_CLK6 175 +#define CLK_DOUT_CMU_DIV_CIS_CLK7 176 +#define CLK_DOUT_CMU_DIV_CPUCL0_DBG_NOC 177 +#define CLK_DOUT_CMU_DIV_CPUCL0_DBG_NOC_SM 178 +#define CLK_DOUT_CMU_DIV_CPUCL0_SWITCH 179 +#define CLK_DOUT_CMU_DIV_CPUCL0_SWITCH_SM 180 +#define CLK_DOUT_CMU_DIV_CPUCL1_SWITCH 181 +#define CLK_DOUT_CMU_DIV_CPUCL1_SWITCH_SM 182 +#define CLK_DOUT_CMU_DIV_CPUCL2_SWITCH 183 +#define CLK_DOUT_CMU_DIV_CPUCL2_SWITCH_SM 184 +#define CLK_DOUT_CMU_DIV_DNC_NOC 185 +#define CLK_DOUT_CMU_DIV_DNC_NOC_SM 186 +#define CLK_DOUT_CMU_DIV_DPUB 187 +#define CLK_DOUT_CMU_DIV_DPUB_ALT 188 +#define CLK_DOUT_CMU_DIV_DPUF 189 +#define CLK_DOUT_CMU_DIV_DPUF_ALT 190 +#define CLK_DOUT_CMU_DIV_DSP_NOC 191 +#define CLK_DOUT_CMU_DIV_DSP_NOC_SM 192 +#define CLK_DOUT_CMU_DIV_DSU_SWITCH 193 +#define CLK_DOUT_CMU_DIV_DSU_SWITCH_SM 194 +#define CLK_DOUT_CMU_DIV_G3D_SWITCH 195 +#define CLK_DOUT_CMU_DIV_G3D_SWITCH_SM 196 +#define CLK_DOUT_CMU_DIV_GNPU_NOC 197 +#define CLK_DOUT_CMU_DIV_GNPU_NOC_SM 198 +#define CLK_DOUT_CMU_DIV_UFS_MMC_CARD 199 +#define CLK_DOUT_CMU_DIV_UFS_MMC_CARD_SM 200 +#define CLK_DOUT_CMU_DIV_M2M_NOC 201 +#define CLK_DOUT_CMU_DIV_M2M_NOC_SM 202 +#define CLK_DOUT_CMU_DIV_NOCL0_NOC 203 +#define CLK_DOUT_CMU_DIV_NOCL0_NOC_SM 204 +#define CLK_DOUT_CMU_DIV_NOCL1A_NOC 205 +#define CLK_DOUT_CMU_DIV_NOCL1A_NOC_SM 206 +#define CLK_DOUT_CMU_DIV_NOCL1B_NOC0 207 +#define CLK_DOUT_CMU_DIV_NOCL1B_NOC0_SM 208 +#define CLK_DOUT_CMU_DIV_NOCL1C_NOC 209 +#define CLK_DOUT_CMU_DIV_NOCL1C_NOC_SM 210 +#define CLK_DOUT_CMU_DIV_SDMA_NOC 211 +#define CLK_DOUT_CMU_DIV_SDMA_NOC_SM 212 +#define CLK_DOUT_CMU_DIV_CP_HISPEEDY_CLK 213 +#define CLK_DOUT_CMU_DIV_CP_HISPEEDY_CLK_SM 214 +#define CLK_DOUT_CMU_DIV_CP_SHARED0_CLK 215 +#define CLK_DOUT_CMU_DIV_CP_SHARED0_CLK_SM 216 +#define CLK_DOUT_CMU_DIV_CP_SHARED2_CLK 217 +#define CLK_DOUT_CMU_DIV_CP_SHARED2_CLK_SM 218 +#define CLK_DOUT_CMU_UFS_NOC 219 +#define CLK_DOUT_CMU_DIV_M2M_FRC 220 +#define CLK_DOUT_CMU_DIV_M2M_FRC_SM 221 +#define CLK_DOUT_CMU_DIV_MCSC_MCSC 222 +#define CLK_DOUT_CMU_DIV_MCSC_MCSC_SM 223 +#define CLK_DOUT_CMU_DIV_MCSC_NOC 224 +#define CLK_DOUT_CMU_DIV_MCSC_NOC_SM 225 +#define CLK_DOUT_SHARED0_DIV1 226 +#define CLK_DOUT_SHARED0_DIV2 227 +#define CLK_DOUT_SHARED0_DIV4 228 +#define CLK_DOUT_SHARED1_DIV1 229 +#define CLK_DOUT_SHARED1_DIV2 230 +#define CLK_DOUT_SHARED1_DIV4 231 +#define CLK_DOUT_SHARED2_DIV1 232 +#define CLK_DOUT_SHARED2_DIV2 233 +#define CLK_DOUT_SHARED2_DIV4 234 +#define CLK_DOUT_SHARED3_DIV1 235 +#define CLK_DOUT_SHARED3_DIV2 236 +#define CLK_DOUT_SHARED3_DIV4 237 +#define CLK_DOUT_SHARED4_DIV1 238 +#define CLK_DOUT_SHARED4_DIV2 239 +#define CLK_DOUT_SHARED4_DIV4 240 +#define CLK_DOUT_SHARED_MIF_DIV1 241 +#define CLK_DOUT_SHARED_MIF_DIV2 242 +#define CLK_DOUT_SHARED_MIF_DIV4 243 +#define CLK_DOUT_TCXO_DIV3 244 +#define CLK_DOUT_TCXO_DIV4 245 + +/* CMU_ALIVE */ +#define CLK_MOUT_ALIVE_NOC_USER 1 +#define CLK_MOUT_ALIVE_RCO_SPMI_USER 2 +#define CLK_MOUT_RCO_ALIVE_USER 3 +#define CLK_MOUT_ALIVE_CHUB_PERI 4 +#define CLK_MOUT_ALIVE_CMGP_NOC 5 +#define CLK_MOUT_ALIVE_CMGP_PERI 6 +#define CLK_MOUT_ALIVE_DBGCORE_NOC 7 +#define CLK_MOUT_ALIVE_DNC_NOC 8 +#define CLK_MOUT_ALIVE_CHUBVTS_NOC 9 +#define CLK_MOUT_ALIVE_GNPU_NOC 10 +#define CLK_MOUT_ALIVE_GNSS_NOC 11 +#define CLK_MOUT_ALIVE_SDMA_NOC 12 +#define CLK_MOUT_ALIVE_UFD_NOC 13 +#define CLK_MOUT_ALIVE_DBGCORE_UART 14 +#define CLK_MOUT_ALIVE_NOC 15 +#define CLK_MOUT_ALIVE_PMU_SUB 16 +#define CLK_MOUT_ALIVE_SPMI 17 +#define CLK_MOUT_ALIVE_TIMER 18 +#define CLK_MOUT_ALIVE_CSIS_NOC 19 +#define CLK_MOUT_ALIVE_DSP_NOC 20 + +#define CLK_DOUT_ALIVE_CHUB_PERI 21 +#define CLK_DOUT_ALIVE_CMGP_NOC 22 +#define CLK_DOUT_ALIVE_CMGP_PERI 23 +#define CLK_DOUT_ALIVE_DBGCORE_NOC 24 +#define CLK_DOUT_ALIVE_DNC_NOC 25 +#define CLK_DOUT_ALIVE_CHUBVTS_NOC 26 +#define CLK_DOUT_ALIVE_GNPU_NOC 27 +#define CLK_DOUT_ALIVE_SDMA_NOC 28 +#define CLK_DOUT_ALIVE_UFD_NOC 29 +#define CLK_DOUT_ALIVE_DBGCORE_UART 30 +#define CLK_DOUT_ALIVE_NOC 31 +#define CLK_DOUT_ALIVE_PMU_SUB 32 +#define CLK_DOUT_ALIVE_SPMI 33 +#define CLK_DOUT_ALIVE_CSIS_NOC 34 +#define CLK_DOUT_ALIVE_DSP_NOC 35 + +/* CMU_PERIS */ +#define CLK_MOUT_PERIS_GIC_USER 1 +#define CLK_MOUT_PERIS_NOC_USER 2 +#define CLK_MOUT_PERIS_GIC 3 + +#define CLK_DOUT_PERIS_OTP 4 +#define CLK_DOUT_PERIS_DDD_CTRL 5 + +/* CMU_CMGP */ +#define CLK_MOUT_CMGP_CLKALIVE_NOC_USER 1 +#define CLK_MOUT_CMGP_CLKALIVE_PERI_USER 2 +#define CLK_MOUT_CMGP_I2C 3 +#define CLK_MOUT_CMGP_SPI_I2C0 4 +#define CLK_MOUT_CMGP_SPI_I2C1 5 +#define CLK_MOUT_CMGP_SPI_MS_CTRL 6 +#define CLK_MOUT_CMGP_USI0 7 +#define CLK_MOUT_CMGP_USI1 8 +#define CLK_MOUT_CMGP_USI2 9 +#define CLK_MOUT_CMGP_USI3 10 +#define CLK_MOUT_CMGP_USI4 11 +#define CLK_MOUT_CMGP_USI5 12 +#define CLK_MOUT_CMGP_USI6 13 + +#define CLK_DOUT_CMGP_I2C 14 +#define CLK_DOUT_CMGP_SPI_I2C0 15 +#define CLK_DOUT_CMGP_SPI_I2C1 16 +#define CLK_DOUT_CMGP_SPI_MS_CTRL 17 +#define CLK_DOUT_CMGP_USI0 18 +#define CLK_DOUT_CMGP_USI1 19 +#define CLK_DOUT_CMGP_USI2 20 +#define CLK_DOUT_CMGP_USI3 21 +#define CLK_DOUT_CMGP_USI4 22 +#define CLK_DOUT_CMGP_USI5 23 +#define CLK_DOUT_CMGP_USI6 24 + +/* CMU_HSI0 */ +#define CLK_MOUT_CLKCMU_HSI0_DPGTC_USER 1 +#define CLK_MOUT_CLKCMU_HSI0_DPOSC_USER 2 +#define CLK_MOUT_CLKCMU_HSI0_NOC_USER 3 +#define CLK_MOUT_CLKCMU_HSI0_USB32DRD_USER 4 +#define CLK_MOUT_HSI0_NOC 5 +#define CLK_MOUT_HSI0_RTCCLK 6 +#define CLK_MOUT_HSI0_USB32DRD 7 + +#define CLK_DOUT_DIV_CLK_HSI0_EUSB 8 + +/* CMU_PERIC0 */ +#define CLK_MOUT_PERIC0_IP0_USER 1 +#define CLK_MOUT_PERIC0_IP1_USER 2 +#define CLK_MOUT_PERIC0_NOC_USER 3 +#define CLK_MOUT_PERIC0_I2C 4 +#define CLK_MOUT_PERIC0_USI04 5 + +#define CLK_DOUT_PERIC0_I2C 6 +#define CLK_DOUT_PERIC0_USI04 7 + +/* CMU_PERIC1 */ +#define CLK_MOUT_PERIC1_IP0_USER 1 +#define CLK_MOUT_PERIC1_IP1_USER 2 +#define CLK_MOUT_PERIC1_NOC_USER 3 +#define CLK_MOUT_PERIC1_I2C 4 +#define CLK_MOUT_PERIC1_SPI_MS_CTRL 5 +#define CLK_MOUT_PERIC1_UART_BT 6 +#define CLK_MOUT_PERIC1_USI07 7 +#define CLK_MOUT_PERIC1_USI07_SPI_I2C 8 +#define CLK_MOUT_PERIC1_USI08 9 +#define CLK_MOUT_PERIC1_USI08_SPI_I2C 10 +#define CLK_MOUT_PERIC1_USI09 11 +#define CLK_MOUT_PERIC1_USI10 12 + +#define CLK_DOUT_PERIC1_I2C 13 +#define CLK_DOUT_PERIC1_SPI_MS_CTRL 14 +#define CLK_DOUT_PERIC1_UART_BT 15 +#define CLK_DOUT_PERIC1_USI07 16 +#define CLK_DOUT_PERIC1_USI07_SPI_I2C 17 +#define CLK_DOUT_PERIC1_USI08 18 +#define CLK_DOUT_PERIC1_USI08_SPI_I2C 19 +#define CLK_DOUT_PERIC1_USI09 20 +#define CLK_DOUT_PERIC1_USI10 21 + +/* CMU_PERIC2 */ +#define CLK_MOUT_PERIC2_IP0_USER 1 +#define CLK_MOUT_PERIC2_IP1_USER 2 +#define CLK_MOUT_PERIC2_NOC_USER 3 +#define CLK_MOUT_PERIC2_I2C 4 +#define CLK_MOUT_PERIC2_SPI_MS_CTRL 5 +#define CLK_MOUT_PERIC2_UART_DBG 6 +#define CLK_MOUT_PERIC2_USI00 7 +#define CLK_MOUT_PERIC2_USI00_SPI_I2C 8 +#define CLK_MOUT_PERIC2_USI01 9 +#define CLK_MOUT_PERIC2_USI01_SPI_I2C 10 +#define CLK_MOUT_PERIC2_USI02 11 +#define CLK_MOUT_PERIC2_USI03 12 +#define CLK_MOUT_PERIC2_USI05 13 +#define CLK_MOUT_PERIC2_USI06 14 +#define CLK_MOUT_PERIC2_USI11 15 + +#define CLK_DOUT_PERIC2_I2C 16 +#define CLK_DOUT_PERIC2_SPI_MS_CTRL 17 +#define CLK_DOUT_PERIC2_UART_DBG 18 +#define CLK_DOUT_PERIC2_USI00 19 +#define CLK_DOUT_PERIC2_USI00_SPI_I2C 20 +#define CLK_DOUT_PERIC2_USI01 21 +#define CLK_DOUT_PERIC2_USI01_SPI_I2C 22 +#define CLK_DOUT_PERIC2_USI02 23 +#define CLK_DOUT_PERIC2_USI03 24 +#define CLK_DOUT_PERIC2_USI05 25 +#define CLK_DOUT_PERIC2_USI06 26 +#define CLK_DOUT_PERIC2_USI11 27 + +/* CMU_UFS */ +#define CLK_MOUT_UFS_MMC_CARD_USER 1 +#define CLK_MOUT_UFS_NOC_USER 2 +#define CLK_MOUT_UFS_UFS_EMBD_USER 3 + +/* CMU_VTS */ +#define CLK_MOUT_CLKALIVE_VTS_NOC_USER 1 +#define CLK_MOUT_CLKALIVE_VTS_RCO_USER 2 +#define CLK_MOUT_CLKCMU_VTS_DMIC_USER 3 +#define CLK_MOUT_CLKVTS_AUD_DMIC1 4 +#define CLK_MOUT_CLKVTS_NOC 5 +#define CLK_MOUT_CLKVTS_DMIC_PAD 6 + +#define CLK_DOUT_CLKVTS_AUD_DMIC0 7 +#define CLK_DOUT_CLKVTS_AUD_DMIC1 8 +#define CLK_DOUT_CLKVTS_CPU 9 +#define CLK_DOUT_CLKVTS_DMIC_IF 10 +#define CLK_DOUT_CLKVTS_DMIC_IF_DIV2 11 +#define CLK_DOUT_CLKVTS_NOC 12 +#define CLK_DOUT_CLKVTS_SERIAL_LIF 13 +#define CLK_DOUT_CLKVTS_SERIAL_LIF_CORE 14 + +#endif diff --git a/include/dt-bindings/clock/samsung,exynos7870-cmu.h b/include/dt-bindings/clock/samsung,exynos7870-cmu.h new file mode 100644 index 000000000000..57d04bbe342d --- /dev/null +++ b/include/dt-bindings/clock/samsung,exynos7870-cmu.h @@ -0,0 +1,324 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2015 Samsung Electronics Co., Ltd. + * Author: Kaustabh Chakraborty <kauschluss@disroot.org> + * + * Device Tree binding constants for Exynos7870 clock controller. + */ + +#ifndef _DT_BINDINGS_CLOCK_EXYNOS7870_H +#define _DT_BINDINGS_CLOCK_EXYNOS7870_H + +/* CMU_MIF */ +#define CLK_DOUT_MIF_APB 1 +#define CLK_DOUT_MIF_BUSD 2 +#define CLK_DOUT_MIF_CMU_DISPAUD_BUS 3 +#define CLK_DOUT_MIF_CMU_DISPAUD_DECON_ECLK 4 +#define CLK_DOUT_MIF_CMU_DISPAUD_DECON_VCLK 5 +#define CLK_DOUT_MIF_CMU_FSYS_BUS 6 +#define CLK_DOUT_MIF_CMU_FSYS_MMC0 7 +#define CLK_DOUT_MIF_CMU_FSYS_MMC1 8 +#define CLK_DOUT_MIF_CMU_FSYS_MMC2 9 +#define CLK_DOUT_MIF_CMU_FSYS_USB20DRD_REFCLK 10 +#define CLK_DOUT_MIF_CMU_G3D_SWITCH 11 +#define CLK_DOUT_MIF_CMU_ISP_CAM 12 +#define CLK_DOUT_MIF_CMU_ISP_ISP 13 +#define CLK_DOUT_MIF_CMU_ISP_SENSOR0 14 +#define CLK_DOUT_MIF_CMU_ISP_SENSOR1 15 +#define CLK_DOUT_MIF_CMU_ISP_SENSOR2 16 +#define CLK_DOUT_MIF_CMU_ISP_VRA 17 +#define CLK_DOUT_MIF_CMU_MFCMSCL_MFC 18 +#define CLK_DOUT_MIF_CMU_MFCMSCL_MSCL 19 +#define CLK_DOUT_MIF_CMU_PERI_BUS 20 +#define CLK_DOUT_MIF_CMU_PERI_SPI0 21 +#define CLK_DOUT_MIF_CMU_PERI_SPI1 22 +#define CLK_DOUT_MIF_CMU_PERI_SPI2 23 +#define CLK_DOUT_MIF_CMU_PERI_SPI3 24 +#define CLK_DOUT_MIF_CMU_PERI_SPI4 25 +#define CLK_DOUT_MIF_CMU_PERI_UART0 26 +#define CLK_DOUT_MIF_CMU_PERI_UART1 27 +#define CLK_DOUT_MIF_CMU_PERI_UART2 28 +#define CLK_DOUT_MIF_HSI2C 29 +#define CLK_FOUT_MIF_BUS_PLL 30 +#define CLK_FOUT_MIF_MEDIA_PLL 31 +#define CLK_FOUT_MIF_MEM_PLL 32 +#define CLK_GOUT_MIF_CMU_DISPAUD_BUS 33 +#define CLK_GOUT_MIF_CMU_DISPAUD_DECON_ECLK 34 +#define CLK_GOUT_MIF_CMU_DISPAUD_DECON_VCLK 35 +#define CLK_GOUT_MIF_CMU_FSYS_BUS 36 +#define CLK_GOUT_MIF_CMU_FSYS_MMC0 37 +#define CLK_GOUT_MIF_CMU_FSYS_MMC1 38 +#define CLK_GOUT_MIF_CMU_FSYS_MMC2 39 +#define CLK_GOUT_MIF_CMU_FSYS_USB20DRD_REFCLK 40 +#define CLK_GOUT_MIF_CMU_G3D_SWITCH 41 +#define CLK_GOUT_MIF_CMU_ISP_CAM 42 +#define CLK_GOUT_MIF_CMU_ISP_ISP 43 +#define CLK_GOUT_MIF_CMU_ISP_SENSOR0 44 +#define CLK_GOUT_MIF_CMU_ISP_SENSOR1 45 +#define CLK_GOUT_MIF_CMU_ISP_SENSOR2 46 +#define CLK_GOUT_MIF_CMU_ISP_VRA 47 +#define CLK_GOUT_MIF_CMU_MFCMSCL_MFC 48 +#define CLK_GOUT_MIF_CMU_MFCMSCL_MSCL 49 +#define CLK_GOUT_MIF_CMU_PERI_BUS 50 +#define CLK_GOUT_MIF_CMU_PERI_SPI0 51 +#define CLK_GOUT_MIF_CMU_PERI_SPI1 52 +#define CLK_GOUT_MIF_CMU_PERI_SPI2 53 +#define CLK_GOUT_MIF_CMU_PERI_SPI3 54 +#define CLK_GOUT_MIF_CMU_PERI_SPI4 55 +#define CLK_GOUT_MIF_CMU_PERI_UART0 56 +#define CLK_GOUT_MIF_CMU_PERI_UART1 57 +#define CLK_GOUT_MIF_CMU_PERI_UART2 58 +#define CLK_GOUT_MIF_CP_PCLK_HSI2C 59 +#define CLK_GOUT_MIF_CP_PCLK_HSI2C_BAT_0 60 +#define CLK_GOUT_MIF_CP_PCLK_HSI2C_BAT_1 61 +#define CLK_GOUT_MIF_HSI2C_AP_PCLKM 62 +#define CLK_GOUT_MIF_HSI2C_AP_PCLKS 63 +#define CLK_GOUT_MIF_HSI2C_CP_PCLKM 64 +#define CLK_GOUT_MIF_HSI2C_CP_PCLKS 65 +#define CLK_GOUT_MIF_HSI2C_IPCLK 66 +#define CLK_GOUT_MIF_HSI2C_ITCLK 67 +#define CLK_GOUT_MIF_MUX_BUSD 68 +#define CLK_GOUT_MIF_MUX_BUS_PLL 69 +#define CLK_GOUT_MIF_MUX_BUS_PLL_CON 70 +#define CLK_GOUT_MIF_MUX_CMU_DISPAUD_BUS 71 +#define CLK_GOUT_MIF_MUX_CMU_DISPAUD_DECON_ECLK 72 +#define CLK_GOUT_MIF_MUX_CMU_DISPAUD_DECON_VCLK 73 +#define CLK_GOUT_MIF_MUX_CMU_FSYS_BUS 74 +#define CLK_GOUT_MIF_MUX_CMU_FSYS_MMC0 75 +#define CLK_GOUT_MIF_MUX_CMU_FSYS_MMC1 76 +#define CLK_GOUT_MIF_MUX_CMU_FSYS_MMC2 77 +#define CLK_GOUT_MIF_MUX_CMU_FSYS_USB20DRD_REFCLK 78 +#define CLK_GOUT_MIF_MUX_CMU_ISP_CAM 79 +#define CLK_GOUT_MIF_MUX_CMU_ISP_ISP 80 +#define CLK_GOUT_MIF_MUX_CMU_ISP_SENSOR0 81 +#define CLK_GOUT_MIF_MUX_CMU_ISP_SENSOR1 82 +#define CLK_GOUT_MIF_MUX_CMU_ISP_SENSOR2 83 +#define CLK_GOUT_MIF_MUX_CMU_ISP_VRA 84 +#define CLK_GOUT_MIF_MUX_CMU_MFCMSCL_MFC 85 +#define CLK_GOUT_MIF_MUX_CMU_MFCMSCL_MSCL 86 +#define CLK_GOUT_MIF_MUX_CMU_PERI_BUS 87 +#define CLK_GOUT_MIF_MUX_CMU_PERI_SPI0 88 +#define CLK_GOUT_MIF_MUX_CMU_PERI_SPI1 89 +#define CLK_GOUT_MIF_MUX_CMU_PERI_SPI2 90 +#define CLK_GOUT_MIF_MUX_CMU_PERI_SPI3 91 +#define CLK_GOUT_MIF_MUX_CMU_PERI_SPI4 92 +#define CLK_GOUT_MIF_MUX_CMU_PERI_UART0 93 +#define CLK_GOUT_MIF_MUX_CMU_PERI_UART1 94 +#define CLK_GOUT_MIF_MUX_CMU_PERI_UART2 95 +#define CLK_GOUT_MIF_MUX_MEDIA_PLL 96 +#define CLK_GOUT_MIF_MUX_MEDIA_PLL_CON 97 +#define CLK_GOUT_MIF_MUX_MEM_PLL 98 +#define CLK_GOUT_MIF_MUX_MEM_PLL_CON 99 +#define CLK_GOUT_MIF_WRAP_ADC_IF_OSC_SYS 100 +#define CLK_GOUT_MIF_WRAP_ADC_IF_PCLK_S0 101 +#define CLK_GOUT_MIF_WRAP_ADC_IF_PCLK_S1 102 +#define CLK_MOUT_MIF_BUSD 103 +#define CLK_MOUT_MIF_CMU_DISPAUD_BUS 104 +#define CLK_MOUT_MIF_CMU_DISPAUD_DECON_ECLK 105 +#define CLK_MOUT_MIF_CMU_DISPAUD_DECON_VCLK 106 +#define CLK_MOUT_MIF_CMU_FSYS_BUS 107 +#define CLK_MOUT_MIF_CMU_FSYS_MMC0 108 +#define CLK_MOUT_MIF_CMU_FSYS_MMC1 109 +#define CLK_MOUT_MIF_CMU_FSYS_MMC2 110 +#define CLK_MOUT_MIF_CMU_FSYS_USB20DRD_REFCLK 111 +#define CLK_MOUT_MIF_CMU_ISP_CAM 112 +#define CLK_MOUT_MIF_CMU_ISP_ISP 113 +#define CLK_MOUT_MIF_CMU_ISP_SENSOR0 114 +#define CLK_MOUT_MIF_CMU_ISP_SENSOR1 115 +#define CLK_MOUT_MIF_CMU_ISP_SENSOR2 116 +#define CLK_MOUT_MIF_CMU_ISP_VRA 117 +#define CLK_MOUT_MIF_CMU_MFCMSCL_MFC 118 +#define CLK_MOUT_MIF_CMU_MFCMSCL_MSCL 119 +#define CLK_MOUT_MIF_CMU_PERI_BUS 120 +#define CLK_MOUT_MIF_CMU_PERI_SPI0 121 +#define CLK_MOUT_MIF_CMU_PERI_SPI1 122 +#define CLK_MOUT_MIF_CMU_PERI_SPI2 123 +#define CLK_MOUT_MIF_CMU_PERI_SPI3 124 +#define CLK_MOUT_MIF_CMU_PERI_SPI4 125 +#define CLK_MOUT_MIF_CMU_PERI_UART0 126 +#define CLK_MOUT_MIF_CMU_PERI_UART1 127 +#define CLK_MOUT_MIF_CMU_PERI_UART2 128 +#define MIF_NR_CLK 129 + +/* CMU_DISPAUD */ +#define CLK_DOUT_DISPAUD_APB 1 +#define CLK_DOUT_DISPAUD_DECON_ECLK 2 +#define CLK_DOUT_DISPAUD_DECON_VCLK 3 +#define CLK_DOUT_DISPAUD_MI2S 4 +#define CLK_DOUT_DISPAUD_MIXER 5 +#define CLK_FOUT_DISPAUD_AUD_PLL 6 +#define CLK_FOUT_DISPAUD_PLL 7 +#define CLK_GOUT_DISPAUD_APB_AUD 8 +#define CLK_GOUT_DISPAUD_APB_AUD_AMP 9 +#define CLK_GOUT_DISPAUD_APB_DISP 10 +#define CLK_GOUT_DISPAUD_BUS 11 +#define CLK_GOUT_DISPAUD_BUS_DISP 12 +#define CLK_GOUT_DISPAUD_BUS_PPMU 13 +#define CLK_GOUT_DISPAUD_CON_AUD_I2S_BCLK_BT_IN 14 +#define CLK_GOUT_DISPAUD_CON_AUD_I2S_BCLK_FM_IN 15 +#define CLK_GOUT_DISPAUD_CON_CP2AUD_BCK 16 +#define CLK_GOUT_DISPAUD_CON_EXT2AUD_BCK_GPIO_I2S 17 +#define CLK_GOUT_DISPAUD_DECON_ECLK 18 +#define CLK_GOUT_DISPAUD_DECON_VCLK 19 +#define CLK_GOUT_DISPAUD_MI2S_AMP_I2SCODCLKI 20 +#define CLK_GOUT_DISPAUD_MI2S_AUD_I2SCODCLKI 21 +#define CLK_GOUT_DISPAUD_MIXER_AUD_SYSCLK 22 +#define CLK_GOUT_DISPAUD_MUX_AUD_PLL 23 +#define CLK_GOUT_DISPAUD_MUX_AUD_PLL_CON 24 +#define CLK_GOUT_DISPAUD_MUX_BUS_USER 25 +#define CLK_GOUT_DISPAUD_MUX_DECON_ECLK 26 +#define CLK_GOUT_DISPAUD_MUX_DECON_ECLK_USER 27 +#define CLK_GOUT_DISPAUD_MUX_DECON_VCLK 28 +#define CLK_GOUT_DISPAUD_MUX_DECON_VCLK_USER 29 +#define CLK_GOUT_DISPAUD_MUX_MI2S 30 +#define CLK_GOUT_DISPAUD_MUX_MIPIPHY_RXCLKESC0_USER 31 +#define CLK_GOUT_DISPAUD_MUX_MIPIPHY_RXCLKESC0_USER_CON 32 +#define CLK_GOUT_DISPAUD_MUX_MIPIPHY_TXBYTECLKHS_USER 33 +#define CLK_GOUT_DISPAUD_MUX_MIPIPHY_TXBYTECLKHS_USER_CON 34 +#define CLK_GOUT_DISPAUD_MUX_PLL 35 +#define CLK_GOUT_DISPAUD_MUX_PLL_CON 36 +#define CLK_MOUT_DISPAUD_BUS_USER 37 +#define CLK_MOUT_DISPAUD_DECON_ECLK 38 +#define CLK_MOUT_DISPAUD_DECON_ECLK_USER 39 +#define CLK_MOUT_DISPAUD_DECON_VCLK 40 +#define CLK_MOUT_DISPAUD_DECON_VCLK_USER 41 +#define CLK_MOUT_DISPAUD_MI2S 42 +#define DISPAUD_NR_CLK 43 + +/* CMU_FSYS */ +#define CLK_FOUT_FSYS_USB_PLL 1 +#define CLK_GOUT_FSYS_BUSP3_HCLK 2 +#define CLK_GOUT_FSYS_MMC0_ACLK 3 +#define CLK_GOUT_FSYS_MMC1_ACLK 4 +#define CLK_GOUT_FSYS_MMC2_ACLK 5 +#define CLK_GOUT_FSYS_MUX_USB20DRD_PHYCLOCK_USER 6 +#define CLK_GOUT_FSYS_MUX_USB20DRD_PHYCLOCK_USER_CON 7 +#define CLK_GOUT_FSYS_MUX_USB_PLL 8 +#define CLK_GOUT_FSYS_MUX_USB_PLL_CON 9 +#define CLK_GOUT_FSYS_PDMA0_ACLK_PDMA0 10 +#define CLK_GOUT_FSYS_PPMU_ACLK 11 +#define CLK_GOUT_FSYS_PPMU_PCLK 12 +#define CLK_GOUT_FSYS_SROMC_HCLK 13 +#define CLK_GOUT_FSYS_UPSIZER_BUS1_ACLK 14 +#define CLK_GOUT_FSYS_USB20DRD_ACLK_HSDRD 15 +#define CLK_GOUT_FSYS_USB20DRD_HCLK_USB20_CTRL 16 +#define CLK_GOUT_FSYS_USB20DRD_HSDRD_REF_CLK 17 +#define FSYS_NR_CLK 18 + +/* CMU_G3D */ +#define CLK_DOUT_G3D_APB 1 +#define CLK_DOUT_G3D_BUS 2 +#define CLK_FOUT_G3D_PLL 3 +#define CLK_GOUT_G3D_ASYNCS_D0_CLK 4 +#define CLK_GOUT_G3D_ASYNC_PCLKM 5 +#define CLK_GOUT_G3D_CLK 6 +#define CLK_GOUT_G3D_MUX 7 +#define CLK_GOUT_G3D_MUX_PLL 8 +#define CLK_GOUT_G3D_MUX_PLL_CON 9 +#define CLK_GOUT_G3D_MUX_SWITCH_USER 10 +#define CLK_GOUT_G3D_PPMU_ACLK 11 +#define CLK_GOUT_G3D_PPMU_PCLK 12 +#define CLK_GOUT_G3D_QE_ACLK 13 +#define CLK_GOUT_G3D_QE_PCLK 14 +#define CLK_GOUT_G3D_SYSREG_PCLK 15 +#define CLK_MOUT_G3D 16 +#define CLK_MOUT_G3D_SWITCH_USER 17 +#define G3D_NR_CLK 18 + +/* CMU_ISP */ +#define CLK_DOUT_ISP_APB 1 +#define CLK_DOUT_ISP_CAM_HALF 2 +#define CLK_FOUT_ISP_PLL 3 +#define CLK_GOUT_ISP_CAM 4 +#define CLK_GOUT_ISP_CAM_HALF 5 +#define CLK_GOUT_ISP_ISPD 6 +#define CLK_GOUT_ISP_ISPD_PPMU 7 +#define CLK_GOUT_ISP_MUX_CAM 8 +#define CLK_GOUT_ISP_MUX_CAM_USER 9 +#define CLK_GOUT_ISP_MUX_ISP 10 +#define CLK_GOUT_ISP_MUX_ISPD 11 +#define CLK_GOUT_ISP_MUX_PLL 12 +#define CLK_GOUT_ISP_MUX_PLL_CON 13 +#define CLK_GOUT_ISP_MUX_RXBYTECLKHS0_SENSOR0_USER 14 +#define CLK_GOUT_ISP_MUX_RXBYTECLKHS0_SENSOR0_USER_CON 15 +#define CLK_GOUT_ISP_MUX_RXBYTECLKHS0_SENSOR1_USER 16 +#define CLK_GOUT_ISP_MUX_RXBYTECLKHS0_SENSOR1_USER_CON 17 +#define CLK_GOUT_ISP_MUX_USER 18 +#define CLK_GOUT_ISP_MUX_VRA 19 +#define CLK_GOUT_ISP_MUX_VRA_USER 20 +#define CLK_GOUT_ISP_VRA 21 +#define CLK_MOUT_ISP_CAM 22 +#define CLK_MOUT_ISP_CAM_USER 23 +#define CLK_MOUT_ISP_ISP 24 +#define CLK_MOUT_ISP_ISPD 25 +#define CLK_MOUT_ISP_USER 26 +#define CLK_MOUT_ISP_VRA 27 +#define CLK_MOUT_ISP_VRA_USER 28 +#define ISP_NR_CLK 29 + +/* CMU_MFCMSCL */ +#define CLK_DOUT_MFCMSCL_APB 1 +#define CLK_GOUT_MFCMSCL_MFC 2 +#define CLK_GOUT_MFCMSCL_MSCL 3 +#define CLK_GOUT_MFCMSCL_MSCL_BI 4 +#define CLK_GOUT_MFCMSCL_MSCL_D 5 +#define CLK_GOUT_MFCMSCL_MSCL_JPEG 6 +#define CLK_GOUT_MFCMSCL_MSCL_POLY 7 +#define CLK_GOUT_MFCMSCL_MSCL_PPMU 8 +#define CLK_GOUT_MFCMSCL_MUX_MFC_USER 9 +#define CLK_GOUT_MFCMSCL_MUX_MSCL_USER 10 +#define CLK_MOUT_MFCMSCL_MFC_USER 11 +#define CLK_MOUT_MFCMSCL_MSCL_USER 12 +#define MFCMSCL_NR_CLK 13 + +/* CMU_PERI */ +#define CLK_GOUT_PERI_BUSP1_PERIC0_HCLK 1 +#define CLK_GOUT_PERI_GPIO2_PCLK 2 +#define CLK_GOUT_PERI_GPIO5_PCLK 3 +#define CLK_GOUT_PERI_GPIO6_PCLK 4 +#define CLK_GOUT_PERI_GPIO7_PCLK 5 +#define CLK_GOUT_PERI_HSI2C1_IPCLK 6 +#define CLK_GOUT_PERI_HSI2C2_IPCLK 7 +#define CLK_GOUT_PERI_HSI2C3_IPCLK 8 +#define CLK_GOUT_PERI_HSI2C4_IPCLK 9 +#define CLK_GOUT_PERI_HSI2C5_IPCLK 10 +#define CLK_GOUT_PERI_HSI2C6_IPCLK 11 +#define CLK_GOUT_PERI_I2C0_PCLK 12 +#define CLK_GOUT_PERI_I2C1_PCLK 13 +#define CLK_GOUT_PERI_I2C2_PCLK 14 +#define CLK_GOUT_PERI_I2C3_PCLK 15 +#define CLK_GOUT_PERI_I2C4_PCLK 16 +#define CLK_GOUT_PERI_I2C5_PCLK 17 +#define CLK_GOUT_PERI_I2C6_PCLK 18 +#define CLK_GOUT_PERI_I2C7_PCLK 19 +#define CLK_GOUT_PERI_I2C8_PCLK 20 +#define CLK_GOUT_PERI_MCT_PCLK 21 +#define CLK_GOUT_PERI_PWM_MOTOR_OSCCLK 22 +#define CLK_GOUT_PERI_PWM_MOTOR_PCLK_S0 23 +#define CLK_GOUT_PERI_SFRIF_TMU_CPUCL0_PCLK 24 +#define CLK_GOUT_PERI_SFRIF_TMU_CPUCL1_PCLK 25 +#define CLK_GOUT_PERI_SFRIF_TMU_PCLK 26 +#define CLK_GOUT_PERI_SPI0_PCLK 27 +#define CLK_GOUT_PERI_SPI0_SPI_EXT_CLK 28 +#define CLK_GOUT_PERI_SPI1_PCLK 29 +#define CLK_GOUT_PERI_SPI1_SPI_EXT_CLK 30 +#define CLK_GOUT_PERI_SPI2_PCLK 31 +#define CLK_GOUT_PERI_SPI2_SPI_EXT_CLK 32 +#define CLK_GOUT_PERI_SPI3_PCLK 33 +#define CLK_GOUT_PERI_SPI3_SPI_EXT_CLK 34 +#define CLK_GOUT_PERI_SPI4_PCLK 35 +#define CLK_GOUT_PERI_SPI4_SPI_EXT_CLK 36 +#define CLK_GOUT_PERI_TMU_CLK 37 +#define CLK_GOUT_PERI_TMU_CPUCL0_CLK 38 +#define CLK_GOUT_PERI_TMU_CPUCL1_CLK 39 +#define CLK_GOUT_PERI_UART0_EXT_UCLK 40 +#define CLK_GOUT_PERI_UART0_PCLK 41 +#define CLK_GOUT_PERI_UART1_EXT_UCLK 42 +#define CLK_GOUT_PERI_UART1_PCLK 43 +#define CLK_GOUT_PERI_UART2_EXT_UCLK 44 +#define CLK_GOUT_PERI_UART2_PCLK 45 +#define CLK_GOUT_PERI_WDT_CPUCL0_PCLK 46 +#define CLK_GOUT_PERI_WDT_CPUCL1_PCLK 47 +#define PERI_NR_CLK 48 + +#endif /* _DT_BINDINGS_CLOCK_EXYNOS7870_H */ diff --git a/include/dt-bindings/clock/samsung,exynos990.h b/include/dt-bindings/clock/samsung,exynos990.h index 307215a3f3ed..6b9df09d2822 100644 --- a/include/dt-bindings/clock/samsung,exynos990.h +++ b/include/dt-bindings/clock/samsung,exynos990.h @@ -233,4 +233,25 @@ #define CLK_GOUT_HSI0_CMU_HSI0_PCLK 21 #define CLK_GOUT_HSI0_XIU_D_HSI0_ACLK 22 +/* CMU_PERIS */ +#define CLK_MOUT_PERIS_BUS_USER 1 +#define CLK_MOUT_PERIS_CLK_PERIS_GIC 2 +#define CLK_GOUT_PERIS_SYSREG_PERIS_PCLK 3 +#define CLK_GOUT_PERIS_WDT_CLUSTER2_PCLK 4 +#define CLK_GOUT_PERIS_WDT_CLUSTER0_PCLK 5 +#define CLK_CLK_PERIS_PERIS_CMU_PERIS_PCLK 6 +#define CLK_GOUT_PERIS_CLK_PERIS_BUSP_CLK 7 +#define CLK_GOUT_PERIS_CLK_PERIS_OSCCLK_CLK 8 +#define CLK_GOUT_PERIS_CLK_PERIS_GIC_CLK 9 +#define CLK_GOUT_PERIS_AD_AXI_P_PERIS_ACLKM 10 +#define CLK_GOUT_PERIS_OTP_CON_BIRA_PCLK 11 +#define CLK_GOUT_PERIS_GIC_CLK 12 +#define CLK_GOUT_PERIS_LHM_AXI_P_PERIS_CLK 13 +#define CLK_GOUT_PERIS_MCT_PCLK 14 +#define CLK_GOUT_PERIS_OTP_CON_TOP_PCLK 15 +#define CLK_GOUT_PERIS_D_TZPC_PERIS_PCLK 16 +#define CLK_GOUT_PERIS_TMU_TOP_PCLK 17 +#define CLK_GOUT_PERIS_OTP_CON_BIRA_OSCCLK 18 +#define CLK_GOUT_PERIS_OTP_CON_TOP_OSCCLK 19 + #endif diff --git a/include/dt-bindings/reset/rockchip,rk3528-cru.h b/include/dt-bindings/reset/rockchip,rk3528-cru.h new file mode 100644 index 000000000000..6b024c5f2e1c --- /dev/null +++ b/include/dt-bindings/reset/rockchip,rk3528-cru.h @@ -0,0 +1,241 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (c) 2022 Rockchip Electronics Co. Ltd. + * Copyright (c) 2024 Yao Zi <ziyao@disroot.org> + * Author: Joseph Chen <chenjh@rock-chips.com> + */ + +#ifndef _DT_BINDINGS_RESET_ROCKCHIP_RK3528_H +#define _DT_BINDINGS_RESET_ROCKCHIP_RK3528_H + +#define SRST_CORE0_PO 0 +#define SRST_CORE1_PO 1 +#define SRST_CORE2_PO 2 +#define SRST_CORE3_PO 3 +#define SRST_CORE0 4 +#define SRST_CORE1 5 +#define SRST_CORE2 6 +#define SRST_CORE3 7 +#define SRST_NL2 8 +#define SRST_CORE_BIU 9 +#define SRST_CORE_CRYPTO 10 +#define SRST_P_DBG 11 +#define SRST_POT_DBG 12 +#define SRST_NT_DBG 13 +#define SRST_P_CORE_GRF 14 +#define SRST_P_DAPLITE_BIU 15 +#define SRST_P_CPU_BIU 16 +#define SRST_REF_PVTPLL_CORE 17 +#define SRST_A_BUS_VOPGL_BIU 18 +#define SRST_A_BUS_H_BIU 19 +#define SRST_A_SYSMEM_BIU 20 +#define SRST_A_BUS_BIU 21 +#define SRST_H_BUS_BIU 22 +#define SRST_P_BUS_BIU 23 +#define SRST_P_DFT2APB 24 +#define SRST_P_BUS_GRF 25 +#define SRST_A_BUS_M_BIU 26 +#define SRST_A_GIC 27 +#define SRST_A_SPINLOCK 28 +#define SRST_A_DMAC 29 +#define SRST_P_TIMER 30 +#define SRST_TIMER0 31 +#define SRST_TIMER1 32 +#define SRST_TIMER2 33 +#define SRST_TIMER3 34 +#define SRST_TIMER4 35 +#define SRST_TIMER5 36 +#define SRST_P_JDBCK_DAP 37 +#define SRST_JDBCK_DAP 38 +#define SRST_P_WDT_NS 39 +#define SRST_T_WDT_NS 40 +#define SRST_H_TRNG_NS 41 +#define SRST_P_UART0 42 +#define SRST_S_UART0 43 +#define SRST_PKA_CRYPTO 44 +#define SRST_A_CRYPTO 45 +#define SRST_H_CRYPTO 46 +#define SRST_P_DMA2DDR 47 +#define SRST_A_DMA2DDR 48 +#define SRST_P_PWM0 49 +#define SRST_PWM0 50 +#define SRST_P_PWM1 51 +#define SRST_PWM1 52 +#define SRST_P_SCR 53 +#define SRST_A_DCF 54 +#define SRST_P_INTMUX 55 +#define SRST_A_VPU_BIU 56 +#define SRST_H_VPU_BIU 57 +#define SRST_P_VPU_BIU 58 +#define SRST_A_VPU 59 +#define SRST_H_VPU 60 +#define SRST_P_CRU_PCIE 61 +#define SRST_P_VPU_GRF 62 +#define SRST_H_SFC 63 +#define SRST_S_SFC 64 +#define SRST_C_EMMC 65 +#define SRST_H_EMMC 66 +#define SRST_A_EMMC 67 +#define SRST_B_EMMC 68 +#define SRST_T_EMMC 69 +#define SRST_P_GPIO1 70 +#define SRST_DB_GPIO1 71 +#define SRST_A_VPU_L_BIU 72 +#define SRST_P_VPU_IOC 73 +#define SRST_H_SAI_I2S0 74 +#define SRST_M_SAI_I2S0 75 +#define SRST_H_SAI_I2S2 76 +#define SRST_M_SAI_I2S2 77 +#define SRST_P_ACODEC 78 +#define SRST_P_GPIO3 79 +#define SRST_DB_GPIO3 80 +#define SRST_P_SPI1 81 +#define SRST_SPI1 82 +#define SRST_P_UART2 83 +#define SRST_S_UART2 84 +#define SRST_P_UART5 85 +#define SRST_S_UART5 86 +#define SRST_P_UART6 87 +#define SRST_S_UART6 88 +#define SRST_P_UART7 89 +#define SRST_S_UART7 90 +#define SRST_P_I2C3 91 +#define SRST_I2C3 92 +#define SRST_P_I2C5 93 +#define SRST_I2C5 94 +#define SRST_P_I2C6 95 +#define SRST_I2C6 96 +#define SRST_A_MAC 97 +#define SRST_P_PCIE 98 +#define SRST_PCIE_PIPE_PHY 99 +#define SRST_PCIE_POWER_UP 100 +#define SRST_P_PCIE_PHY 101 +#define SRST_P_PIPE_GRF 102 +#define SRST_H_SDIO0 103 +#define SRST_H_SDIO1 104 +#define SRST_TS_0 105 +#define SRST_TS_1 106 +#define SRST_P_CAN2 107 +#define SRST_CAN2 108 +#define SRST_P_CAN3 109 +#define SRST_CAN3 110 +#define SRST_P_SARADC 111 +#define SRST_SARADC 112 +#define SRST_SARADC_PHY 113 +#define SRST_P_TSADC 114 +#define SRST_TSADC 115 +#define SRST_A_USB3OTG 116 +#define SRST_A_GPU_BIU 117 +#define SRST_P_GPU_BIU 118 +#define SRST_A_GPU 119 +#define SRST_REF_PVTPLL_GPU 120 +#define SRST_H_RKVENC_BIU 121 +#define SRST_A_RKVENC_BIU 122 +#define SRST_P_RKVENC_BIU 123 +#define SRST_H_RKVENC 124 +#define SRST_A_RKVENC 125 +#define SRST_CORE_RKVENC 126 +#define SRST_H_SAI_I2S1 127 +#define SRST_M_SAI_I2S1 128 +#define SRST_P_I2C1 129 +#define SRST_I2C1 130 +#define SRST_P_I2C0 131 +#define SRST_I2C0 132 +#define SRST_P_SPI0 133 +#define SRST_SPI0 134 +#define SRST_P_GPIO4 135 +#define SRST_DB_GPIO4 136 +#define SRST_P_RKVENC_IOC 137 +#define SRST_H_SPDIF 138 +#define SRST_M_SPDIF 139 +#define SRST_H_PDM 140 +#define SRST_M_PDM 141 +#define SRST_P_UART1 142 +#define SRST_S_UART1 143 +#define SRST_P_UART3 144 +#define SRST_S_UART3 145 +#define SRST_P_RKVENC_GRF 146 +#define SRST_P_CAN0 147 +#define SRST_CAN0 148 +#define SRST_P_CAN1 149 +#define SRST_CAN1 150 +#define SRST_A_VO_BIU 151 +#define SRST_H_VO_BIU 152 +#define SRST_P_VO_BIU 153 +#define SRST_H_RGA2E 154 +#define SRST_A_RGA2E 155 +#define SRST_CORE_RGA2E 156 +#define SRST_H_VDPP 157 +#define SRST_A_VDPP 158 +#define SRST_CORE_VDPP 159 +#define SRST_P_VO_GRF 160 +#define SRST_P_CRU 161 +#define SRST_A_VOP_BIU 162 +#define SRST_H_VOP 163 +#define SRST_D_VOP0 164 +#define SRST_D_VOP1 165 +#define SRST_A_VOP 166 +#define SRST_P_HDMI 167 +#define SRST_HDMI 168 +#define SRST_P_HDMIPHY 169 +#define SRST_H_HDCP_KEY 170 +#define SRST_A_HDCP 171 +#define SRST_H_HDCP 172 +#define SRST_P_HDCP 173 +#define SRST_H_CVBS 174 +#define SRST_D_CVBS_VOP 175 +#define SRST_D_4X_CVBS_VOP 176 +#define SRST_A_JPEG_DECODER 177 +#define SRST_H_JPEG_DECODER 178 +#define SRST_A_VO_L_BIU 179 +#define SRST_A_MAC_VO 180 +#define SRST_A_JPEG_BIU 181 +#define SRST_H_SAI_I2S3 182 +#define SRST_M_SAI_I2S3 183 +#define SRST_MACPHY 184 +#define SRST_P_VCDCPHY 185 +#define SRST_P_GPIO2 186 +#define SRST_DB_GPIO2 187 +#define SRST_P_VO_IOC 188 +#define SRST_H_SDMMC0 189 +#define SRST_P_OTPC_NS 190 +#define SRST_SBPI_OTPC_NS 191 +#define SRST_USER_OTPC_NS 192 +#define SRST_HDMIHDP0 193 +#define SRST_H_USBHOST 194 +#define SRST_H_USBHOST_ARB 195 +#define SRST_HOST_UTMI 196 +#define SRST_P_UART4 197 +#define SRST_S_UART4 198 +#define SRST_P_I2C4 199 +#define SRST_I2C4 200 +#define SRST_P_I2C7 201 +#define SRST_I2C7 202 +#define SRST_P_USBPHY 203 +#define SRST_USBPHY_POR 204 +#define SRST_USBPHY_OTG 205 +#define SRST_USBPHY_HOST 206 +#define SRST_P_DDRPHY_CRU 207 +#define SRST_H_RKVDEC_BIU 208 +#define SRST_A_RKVDEC_BIU 209 +#define SRST_A_RKVDEC 210 +#define SRST_H_RKVDEC 211 +#define SRST_HEVC_CA_RKVDEC 212 +#define SRST_REF_PVTPLL_RKVDEC 213 +#define SRST_P_DDR_BIU 214 +#define SRST_P_DDRC 215 +#define SRST_P_DDRMON 216 +#define SRST_TIMER_DDRMON 217 +#define SRST_P_MSCH_BIU 218 +#define SRST_P_DDR_GRF 219 +#define SRST_P_DDR_HWLP 220 +#define SRST_P_DDRPHY 221 +#define SRST_MSCH_BIU 222 +#define SRST_A_DDR_UPCTL 223 +#define SRST_DDR_UPCTL 224 +#define SRST_DDRMON 225 +#define SRST_A_DDR_SCRAMBLE 226 +#define SRST_A_SPLIT 227 +#define SRST_DDR_PHY 228 + +#endif // _DT_BINDINGS_RESET_ROCKCHIP_RK3528_H diff --git a/include/dt-bindings/reset/rockchip,rk3562-cru.h b/include/dt-bindings/reset/rockchip,rk3562-cru.h new file mode 100644 index 000000000000..8df95113056e --- /dev/null +++ b/include/dt-bindings/reset/rockchip,rk3562-cru.h @@ -0,0 +1,358 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2024-2025 Rockchip Electronics Co. Ltd. + * + * Author: Elaine Zhang <zhangqing@rock-chips.com> + */ + +#ifndef _DT_BINDINGS_RESET_ROCKCHIP_RK3562_H +#define _DT_BINDINGS_RESET_ROCKCHIP_RK3562_H + +/********Name=SOFTRST_CON01,Offset=0x404********/ +#define SRST_A_TOP_BIU 0 +#define SRST_A_TOP_VIO_BIU 1 +#define SRST_REF_PVTPLL_LOGIC 2 +/********Name=SOFTRST_CON03,Offset=0x40C********/ +#define SRST_NCOREPORESET0 3 +#define SRST_NCOREPORESET1 4 +#define SRST_NCOREPORESET2 5 +#define SRST_NCOREPORESET3 6 +#define SRST_NCORESET0 7 +#define SRST_NCORESET1 8 +#define SRST_NCORESET2 9 +#define SRST_NCORESET3 10 +#define SRST_NL2RESET 11 +/********Name=SOFTRST_CON04,Offset=0x410********/ +#define SRST_DAP 12 +#define SRST_P_DBG_DAPLITE 13 +#define SRST_REF_PVTPLL_CORE 14 +/********Name=SOFTRST_CON05,Offset=0x414********/ +#define SRST_A_CORE_BIU 15 +#define SRST_P_CORE_BIU 16 +#define SRST_H_CORE_BIU 17 +/********Name=SOFTRST_CON06,Offset=0x418********/ +#define SRST_A_NPU_BIU 18 +#define SRST_H_NPU_BIU 19 +#define SRST_A_RKNN 20 +#define SRST_H_RKNN 21 +#define SRST_REF_PVTPLL_NPU 22 +/********Name=SOFTRST_CON08,Offset=0x420********/ +#define SRST_A_GPU_BIU 23 +#define SRST_GPU 24 +#define SRST_REF_PVTPLL_GPU 25 +#define SRST_GPU_BRG_BIU 26 +/********Name=SOFTRST_CON09,Offset=0x424********/ +#define SRST_RKVENC_CORE 27 +#define SRST_A_VEPU_BIU 28 +#define SRST_H_VEPU_BIU 29 +#define SRST_A_RKVENC 30 +#define SRST_H_RKVENC 31 +/********Name=SOFTRST_CON10,Offset=0x428********/ +#define SRST_RKVDEC_HEVC_CA 32 +#define SRST_A_VDPU_BIU 33 +#define SRST_H_VDPU_BIU 34 +#define SRST_A_RKVDEC 35 +#define SRST_H_RKVDEC 36 +/********Name=SOFTRST_CON11,Offset=0x42C********/ +#define SRST_A_VI_BIU 37 +#define SRST_H_VI_BIU 38 +#define SRST_P_VI_BIU 39 +#define SRST_ISP 40 +#define SRST_A_VICAP 41 +#define SRST_H_VICAP 42 +#define SRST_D_VICAP 43 +#define SRST_I0_VICAP 44 +#define SRST_I1_VICAP 45 +#define SRST_I2_VICAP 46 +#define SRST_I3_VICAP 47 +/********Name=SOFTRST_CON12,Offset=0x430********/ +#define SRST_P_CSIHOST0 48 +#define SRST_P_CSIHOST1 49 +#define SRST_P_CSIHOST2 50 +#define SRST_P_CSIHOST3 51 +#define SRST_P_CSIPHY0 52 +#define SRST_P_CSIPHY1 53 +/********Name=SOFTRST_CON13,Offset=0x434********/ +#define SRST_A_VO_BIU 54 +#define SRST_H_VO_BIU 55 +#define SRST_A_VOP 56 +#define SRST_H_VOP 57 +#define SRST_D_VOP 58 +#define SRST_D_VOP1 59 +/********Name=SOFTRST_CON14,Offset=0x438********/ +#define SRST_A_RGA_BIU 60 +#define SRST_H_RGA_BIU 61 +#define SRST_A_RGA 62 +#define SRST_H_RGA 63 +#define SRST_RGA_CORE 64 +#define SRST_A_JDEC 65 +#define SRST_H_JDEC 66 +/********Name=SOFTRST_CON15,Offset=0x43C********/ +#define SRST_B_EBK_BIU 67 +#define SRST_P_EBK_BIU 68 +#define SRST_AHB2AXI_EBC 69 +#define SRST_H_EBC 70 +#define SRST_D_EBC 71 +#define SRST_H_EINK 72 +#define SRST_P_EINK 73 +/********Name=SOFTRST_CON16,Offset=0x440********/ +#define SRST_P_PHP_BIU 74 +#define SRST_A_PHP_BIU 75 +#define SRST_P_PCIE20 76 +#define SRST_PCIE20_POWERUP 77 +#define SRST_USB3OTG 78 +/********Name=SOFTRST_CON17,Offset=0x444********/ +#define SRST_PIPEPHY 79 +/********Name=SOFTRST_CON18,Offset=0x448********/ +#define SRST_A_BUS_BIU 80 +#define SRST_H_BUS_BIU 81 +#define SRST_P_BUS_BIU 82 +/********Name=SOFTRST_CON19,Offset=0x44C********/ +#define SRST_P_I2C1 83 +#define SRST_P_I2C2 84 +#define SRST_P_I2C3 85 +#define SRST_P_I2C4 86 +#define SRST_P_I2C5 87 +#define SRST_I2C1 88 +#define SRST_I2C2 89 +#define SRST_I2C3 90 +#define SRST_I2C4 91 +#define SRST_I2C5 92 +/********Name=SOFTRST_CON20,Offset=0x450********/ +#define SRST_BUS_GPIO3 93 +#define SRST_BUS_GPIO4 94 +/********Name=SOFTRST_CON21,Offset=0x454********/ +#define SRST_P_TIMER 95 +#define SRST_TIMER0 96 +#define SRST_TIMER1 97 +#define SRST_TIMER2 98 +#define SRST_TIMER3 99 +#define SRST_TIMER4 100 +#define SRST_TIMER5 101 +#define SRST_P_STIMER 102 +#define SRST_STIMER0 103 +#define SRST_STIMER1 104 +/********Name=SOFTRST_CON22,Offset=0x458********/ +#define SRST_P_WDTNS 105 +#define SRST_WDTNS 106 +#define SRST_P_GRF 107 +#define SRST_P_SGRF 108 +#define SRST_P_MAILBOX 109 +#define SRST_P_INTC 110 +#define SRST_A_BUS_GIC400 111 +#define SRST_A_BUS_GIC400_DEBUG 112 +/********Name=SOFTRST_CON23,Offset=0x45C********/ +#define SRST_A_BUS_SPINLOCK 113 +#define SRST_A_DCF 114 +#define SRST_P_DCF 115 +#define SRST_F_BUS_CM0_CORE 116 +#define SRST_T_BUS_CM0_JTAG 117 +#define SRST_H_ICACHE 118 +#define SRST_H_DCACHE 119 +/********Name=SOFTRST_CON24,Offset=0x460********/ +#define SRST_P_TSADC 120 +#define SRST_TSADC 121 +#define SRST_TSADCPHY 122 +#define SRST_P_DFT2APB 123 +/********Name=SOFTRST_CON25,Offset=0x464********/ +#define SRST_A_GMAC 124 +#define SRST_P_APB2ASB_VCCIO156 125 +#define SRST_P_DSIPHY 126 +#define SRST_P_DSITX 127 +#define SRST_P_CPU_EMA_DET 128 +#define SRST_P_HASH 129 +#define SRST_P_TOPCRU 130 +/********Name=SOFTRST_CON26,Offset=0x468********/ +#define SRST_P_ASB2APB_VCCIO156 131 +#define SRST_P_IOC_VCCIO156 132 +#define SRST_P_GPIO3_VCCIO156 133 +#define SRST_P_GPIO4_VCCIO156 134 +#define SRST_P_SARADC_VCCIO156 135 +#define SRST_SARADC_VCCIO156 136 +#define SRST_SARADC_VCCIO156_PHY 137 +/********Name=SOFTRST_CON27,Offset=0x46c********/ +#define SRST_A_MAC100 138 + +/********Name=PMU0SOFTRST_CON00,Offset=0x10200********/ +#define SRST_P_PMU0_CRU 139 +#define SRST_P_PMU0_PMU 140 +#define SRST_PMU0_PMU 141 +#define SRST_P_PMU0_HP_TIMER 142 +#define SRST_PMU0_HP_TIMER 143 +#define SRST_PMU0_32K_HP_TIMER 144 +#define SRST_P_PMU0_PVTM 145 +#define SRST_PMU0_PVTM 146 +#define SRST_P_IOC_PMUIO 147 +#define SRST_P_PMU0_GPIO0 148 +#define SRST_PMU0_GPIO0 149 +#define SRST_P_PMU0_GRF 150 +#define SRST_P_PMU0_SGRF 151 +/********Name=PMU0SOFTRST_CON01,Offset=0x10204********/ +#define SRST_DDR_FAIL_SAFE 152 +#define SRST_P_PMU0_SCRKEYGEN 153 +/********Name=PMU0SOFTRST_CON02,Offset=0x10208********/ +#define SRST_P_PMU0_I2C0 154 +#define SRST_PMU0_I2C0 155 + +/********Name=PMU1SOFTRST_CON00,Offset=0x18200********/ +#define SRST_P_PMU1_CRU 156 +#define SRST_H_PMU1_MEM 157 +#define SRST_H_PMU1_BIU 158 +#define SRST_P_PMU1_BIU 159 +#define SRST_P_PMU1_UART0 160 +#define SRST_S_PMU1_UART0 161 +/********Name=PMU1SOFTRST_CON01,Offset=0x18204********/ +#define SRST_P_PMU1_SPI0 162 +#define SRST_PMU1_SPI0 163 +#define SRST_P_PMU1_PWM0 164 +#define SRST_PMU1_PWM0 165 +/********Name=PMU1SOFTRST_CON02,Offset=0x18208********/ +#define SRST_F_PMU1_CM0_CORE 166 +#define SRST_T_PMU1_CM0_JTAG 167 +#define SRST_P_PMU1_WDTNS 168 +#define SRST_PMU1_WDTNS 169 +#define SRST_PMU1_MAILBOX 170 + +/********Name=DDRSOFTRST_CON00,Offset=0x20200********/ +#define SRST_MSCH_BRG_BIU 171 +#define SRST_P_MSCH_BIU 172 +#define SRST_P_DDR_HWLP 173 +#define SRST_P_DDR_PHY 290 +#define SRST_P_DDR_DFICTL 174 +#define SRST_P_DDR_DMA2DDR 175 +/********Name=DDRSOFTRST_CON01,Offset=0x20204********/ +#define SRST_P_DDR_MON 176 +#define SRST_TM_DDR_MON 177 +#define SRST_P_DDR_GRF 178 +#define SRST_P_DDR_CRU 179 +#define SRST_P_SUBDDR_CRU 180 + +/********Name=SUBDDRSOFTRST_CON00,Offset=0x28200********/ +#define SRST_MSCH_BIU 181 +#define SRST_DDR_PHY 182 +#define SRST_DDR_DFICTL 183 +#define SRST_DDR_SCRAMBLE 184 +#define SRST_DDR_MON 185 +#define SRST_A_DDR_SPLIT 186 +#define SRST_DDR_DMA2DDR 187 + +/********Name=PERISOFTRST_CON01,Offset=0x30404********/ +#define SRST_A_PERI_BIU 188 +#define SRST_H_PERI_BIU 189 +#define SRST_P_PERI_BIU 190 +#define SRST_P_PERICRU 191 +/********Name=PERISOFTRST_CON02,Offset=0x30408********/ +#define SRST_H_SAI0_8CH 192 +#define SRST_M_SAI0_8CH 193 +#define SRST_H_SAI1_8CH 194 +#define SRST_M_SAI1_8CH 195 +#define SRST_H_SAI2_2CH 196 +#define SRST_M_SAI2_2CH 197 +/********Name=PERISOFTRST_CON03,Offset=0x3040C********/ +#define SRST_H_DSM 198 +#define SRST_DSM 199 +#define SRST_H_PDM 200 +#define SRST_M_PDM 201 +#define SRST_H_SPDIF 202 +#define SRST_M_SPDIF 203 +/********Name=PERISOFTRST_CON04,Offset=0x30410********/ +#define SRST_H_SDMMC0 204 +#define SRST_H_SDMMC1 205 +#define SRST_H_EMMC 206 +#define SRST_A_EMMC 207 +#define SRST_C_EMMC 208 +#define SRST_B_EMMC 209 +#define SRST_T_EMMC 210 +#define SRST_S_SFC 211 +#define SRST_H_SFC 212 +/********Name=PERISOFTRST_CON05,Offset=0x30414********/ +#define SRST_H_USB2HOST 213 +#define SRST_H_USB2HOST_ARB 214 +#define SRST_USB2HOST_UTMI 215 +/********Name=PERISOFTRST_CON06,Offset=0x30418********/ +#define SRST_P_SPI1 216 +#define SRST_SPI1 217 +#define SRST_P_SPI2 218 +#define SRST_SPI2 219 +/********Name=PERISOFTRST_CON07,Offset=0x3041C********/ +#define SRST_P_UART1 220 +#define SRST_P_UART2 221 +#define SRST_P_UART3 222 +#define SRST_P_UART4 223 +#define SRST_P_UART5 224 +#define SRST_P_UART6 225 +#define SRST_P_UART7 226 +#define SRST_P_UART8 227 +#define SRST_P_UART9 228 +#define SRST_S_UART1 229 +#define SRST_S_UART2 230 +/********Name=PERISOFTRST_CON08,Offset=0x30420********/ +#define SRST_S_UART3 231 +#define SRST_S_UART4 232 +#define SRST_S_UART5 233 +#define SRST_S_UART6 234 +#define SRST_S_UART7 235 +/********Name=PERISOFTRST_CON09,Offset=0x30424********/ +#define SRST_S_UART8 236 +#define SRST_S_UART9 237 +/********Name=PERISOFTRST_CON10,Offset=0x30428********/ +#define SRST_P_PWM1_PERI 238 +#define SRST_PWM1_PERI 239 +#define SRST_P_PWM2_PERI 240 +#define SRST_PWM2_PERI 241 +#define SRST_P_PWM3_PERI 242 +#define SRST_PWM3_PERI 243 +/********Name=PERISOFTRST_CON11,Offset=0x3042C********/ +#define SRST_P_CAN0 244 +#define SRST_CAN0 245 +#define SRST_P_CAN1 246 +#define SRST_CAN1 247 +/********Name=PERISOFTRST_CON12,Offset=0x30430********/ +#define SRST_A_CRYPTO 248 +#define SRST_H_CRYPTO 249 +#define SRST_P_CRYPTO 250 +#define SRST_CORE_CRYPTO 251 +#define SRST_PKA_CRYPTO 252 +#define SRST_H_KLAD 253 +#define SRST_P_KEY_READER 254 +#define SRST_H_RK_RNG_NS 255 +#define SRST_H_RK_RNG_S 256 +#define SRST_H_TRNG_NS 257 +#define SRST_H_TRNG_S 258 +#define SRST_H_CRYPTO_S 259 +/********Name=PERISOFTRST_CON13,Offset=0x30434********/ +#define SRST_P_PERI_WDT 260 +#define SRST_T_PERI_WDT 261 +#define SRST_A_SYSMEM 262 +#define SRST_H_BOOTROM 263 +#define SRST_P_PERI_GRF 264 +#define SRST_A_DMAC 265 +#define SRST_A_RKDMAC 267 +/********Name=PERISOFTRST_CON14,Offset=0x30438********/ +#define SRST_P_OTPC_NS 268 +#define SRST_SBPI_OTPC_NS 269 +#define SRST_USER_OTPC_NS 270 +#define SRST_P_OTPC_S 271 +#define SRST_SBPI_OTPC_S 272 +#define SRST_USER_OTPC_S 273 +#define SRST_OTPC_ARB 274 +#define SRST_P_OTPPHY 275 +#define SRST_OTP_NPOR 276 +/********Name=PERISOFTRST_CON15,Offset=0x3043C********/ +#define SRST_P_USB2PHY 277 +#define SRST_USB2PHY_POR 278 +#define SRST_USB2PHY_OTG 279 +#define SRST_USB2PHY_HOST 280 +#define SRST_P_PIPEPHY 281 +/********Name=PERISOFTRST_CON16,Offset=0x30440********/ +#define SRST_P_SARADC 282 +#define SRST_SARADC 283 +#define SRST_SARADC_PHY 284 +#define SRST_P_IOC_VCCIO234 285 +/********Name=PERISOFTRST_CON17,Offset=0x30444********/ +#define SRST_P_PERI_GPIO1 286 +#define SRST_P_PERI_GPIO2 287 +#define SRST_PERI_GPIO1 288 +#define SRST_PERI_GPIO2 289 + +#endif diff --git a/include/linux/clk/davinci.h b/include/linux/clk/davinci.h index e1d37451e03f..787a81116b00 100644 --- a/include/linux/clk/davinci.h +++ b/include/linux/clk/davinci.h @@ -12,12 +12,6 @@ #include <linux/regmap.h> /* function for registering clocks in early boot */ - -#ifdef CONFIG_ARCH_DAVINCI_DA830 -int da830_pll_init(struct device *dev, void __iomem *base, struct regmap *cfgchip); -#endif -#ifdef CONFIG_ARCH_DAVINCI_DA850 int da850_pll0_init(struct device *dev, void __iomem *base, struct regmap *cfgchip); -#endif #endif /* __LINUX_CLK_DAVINCI_PLL_H___ */ |