diff options
| -rw-r--r-- | arch/arm/mach-omap2/cm-regbits-44xx.h | 101 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/cm1_44xx.h | 174 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/cm2_44xx.h | 386 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/scrm44xx.h | 141 |
4 files changed, 0 insertions, 802 deletions
diff --git a/arch/arm/mach-omap2/cm-regbits-44xx.h b/arch/arm/mach-omap2/cm-regbits-44xx.h index 1e9c23c107b2..553a6267ed57 100644 --- a/arch/arm/mach-omap2/cm-regbits-44xx.h +++ b/arch/arm/mach-omap2/cm-regbits-44xx.h @@ -20,71 +20,11 @@ #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H #define OMAP4430_ABE_STATDEP_SHIFT 3 -#define OMAP4430_AUTO_DPLL_MODE_MASK (0x7 << 0) -#define OMAP4430_CLKSEL_SHIFT 24 -#define OMAP4430_CLKSEL_WIDTH 0x1 -#define OMAP4430_CLKSEL_MASK (1 << 24) -#define OMAP4430_CLKSEL_0_0_SHIFT 0 -#define OMAP4430_CLKSEL_0_0_WIDTH 0x1 -#define OMAP4430_CLKSEL_0_1_SHIFT 0 -#define OMAP4430_CLKSEL_0_1_WIDTH 0x2 -#define OMAP4430_CLKSEL_24_25_SHIFT 24 -#define OMAP4430_CLKSEL_24_25_WIDTH 0x2 -#define OMAP4430_CLKSEL_60M_SHIFT 24 -#define OMAP4430_CLKSEL_60M_WIDTH 0x1 -#define OMAP4430_CLKSEL_AESS_FCLK_SHIFT 24 -#define OMAP4430_CLKSEL_AESS_FCLK_WIDTH 0x1 -#define OMAP4430_CLKSEL_CORE_SHIFT 0 -#define OMAP4430_CLKSEL_CORE_WIDTH 0x1 -#define OMAP4430_CLKSEL_DIV_SHIFT 24 -#define OMAP4430_CLKSEL_DIV_WIDTH 0x1 -#define OMAP4430_CLKSEL_FCLK_SHIFT 24 -#define OMAP4430_CLKSEL_FCLK_WIDTH 0x2 -#define OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT 25 -#define OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH 0x1 -#define OMAP4430_CLKSEL_L3_SHIFT 4 -#define OMAP4430_CLKSEL_L3_WIDTH 0x1 -#define OMAP4430_CLKSEL_L4_SHIFT 8 -#define OMAP4430_CLKSEL_L4_WIDTH 0x1 -#define OMAP4430_CLKSEL_OPP_SHIFT 0 -#define OMAP4430_CLKSEL_OPP_WIDTH 0x2 -#define OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT 27 -#define OMAP4430_CLKSEL_PMD_STM_CLK_WIDTH 0x3 -#define OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK (0x7 << 24) -#define OMAP4430_CLKSEL_SGX_FCLK_MASK (1 << 24) -#define OMAP4430_CLKSEL_SOURCE_MASK (0x3 << 24) -#define OMAP4430_CLKSEL_SOURCE_24_24_MASK (1 << 24) -#define OMAP4430_CLKSEL_UTMI_P1_SHIFT 24 -#define OMAP4430_CLKSEL_UTMI_P1_WIDTH 0x1 -#define OMAP4430_CLKSEL_UTMI_P2_SHIFT 25 -#define OMAP4430_CLKSEL_UTMI_P2_WIDTH 0x1 #define OMAP4430_CLKTRCTRL_SHIFT 0 #define OMAP4430_CLKTRCTRL_MASK (0x3 << 0) -#define OMAP4430_DPLL_BYP_CLKSEL_SHIFT 23 -#define OMAP4430_DPLL_BYP_CLKSEL_WIDTH 0x1 -#define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK (0x1f << 0) -#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT 8 -#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK (1 << 10) -#define OMAP4430_DPLL_CLKOUT_DIV_SHIFT 0 -#define OMAP4430_DPLL_CLKOUT_DIV_WIDTH 0x5 -#define OMAP4430_DPLL_CLKOUT_DIV_MASK (0x1f << 0) -#define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK (0x7f << 0) -#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8) -#define OMAP4430_DPLL_DIV_MASK (0x7f << 0) -#define OMAP4430_DPLL_DIV_0_7_MASK (0xff << 0) -#define OMAP4430_DPLL_EN_MASK (0x7 << 0) -#define OMAP4430_DPLL_LPMODE_EN_MASK (1 << 10) -#define OMAP4430_DPLL_MULT_MASK (0x7ff << 8) -#define OMAP4430_DPLL_MULT_USB_MASK (0xfff << 8) -#define OMAP4430_DPLL_REGM4XEN_MASK (1 << 11) -#define OMAP4430_DPLL_SD_DIV_MASK (0xff << 24) #define OMAP4430_DSS_STATDEP_SHIFT 8 #define OMAP4430_DUCATI_STATDEP_SHIFT 0 #define OMAP4430_GFX_STATDEP_SHIFT 10 -#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK (0x1f << 0) -#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK (0x1f << 0) -#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK (0x1f << 0) -#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK (0x1f << 0) #define OMAP4430_IDLEST_SHIFT 16 #define OMAP4430_IDLEST_MASK (0x3 << 16) #define OMAP4430_IVAHD_STATDEP_SHIFT 2 @@ -98,46 +38,5 @@ #define OMAP4430_MEMIF_STATDEP_SHIFT 4 #define OMAP4430_MODULEMODE_SHIFT 0 #define OMAP4430_MODULEMODE_MASK (0x3 << 0) -#define OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT 9 -#define OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT 8 -#define OMAP4430_OPTFCLKEN_CLK32K_SHIFT 8 -#define OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_DBCLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_DSSCLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_FCLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_FCLK0_SHIFT 8 -#define OMAP4430_OPTFCLKEN_FCLK1_SHIFT 9 -#define OMAP4430_OPTFCLKEN_FCLK2_SHIFT 10 -#define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT 15 -#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT 13 -#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT 14 -#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT 11 -#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT 12 -#define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT 9 -#define OMAP4430_OPTFCLKEN_PHY_48M_SHIFT 8 -#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT 10 -#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT 11 -#define OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT 10 -#define OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_TV_CLK_SHIFT 11 -#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT 9 -#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT 10 -#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT 9 -#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT 10 -#define OMAP4430_OPTFCLKEN_XCLK_SHIFT 8 -#define OMAP4430_PAD_CLKS_GATE_SHIFT 8 -#define OMAP4430_PMD_STM_MUX_CTRL_SHIFT 20 -#define OMAP4430_PMD_STM_MUX_CTRL_WIDTH 0x2 -#define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT 22 -#define OMAP4430_PMD_TRACE_MUX_CTRL_WIDTH 0x2 -#define OMAP4430_SCALE_FCLK_SHIFT 0 -#define OMAP4430_SCALE_FCLK_WIDTH 0x1 -#define OMAP4430_SLIMBUS_CLK_GATE_SHIFT 10 -#define OMAP4430_ST_DPLL_CLK_MASK (1 << 0) -#define OMAP4430_SYS_CLKSEL_SHIFT 0 -#define OMAP4430_SYS_CLKSEL_WIDTH 0x3 #define OMAP4430_TESLA_STATDEP_SHIFT 1 #endif diff --git a/arch/arm/mach-omap2/cm1_44xx.h b/arch/arm/mach-omap2/cm1_44xx.h index 1a9725c7ad30..13710cefaf41 100644 --- a/arch/arm/mach-omap2/cm1_44xx.h +++ b/arch/arm/mach-omap2/cm1_44xx.h @@ -34,184 +34,10 @@ #define OMAP4430_CM1_MPU_INST 0x0300 #define OMAP4430_CM1_TESLA_INST 0x0400 #define OMAP4430_CM1_ABE_INST 0x0500 -#define OMAP4430_CM1_RESTORE_INST 0x0e00 -#define OMAP4430_CM1_INSTR_INST 0x0f00 /* CM1 clockdomain register offsets (from instance start) */ #define OMAP4430_CM1_MPU_MPU_CDOFFS 0x0000 #define OMAP4430_CM1_TESLA_TESLA_CDOFFS 0x0000 #define OMAP4430_CM1_ABE_ABE_CDOFFS 0x0000 -/* CM1 */ - -/* CM1.OCP_SOCKET_CM1 register offsets */ -#define OMAP4_REVISION_CM1_OFFSET 0x0000 -#define OMAP4430_REVISION_CM1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_INST, 0x0000) -#define OMAP4_CM_CM1_PROFILING_CLKCTRL_OFFSET 0x0040 -#define OMAP4430_CM_CM1_PROFILING_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_INST, 0x0040) - -/* CM1.CKGEN_CM1 register offsets */ -#define OMAP4_CM_CLKSEL_CORE_OFFSET 0x0000 -#define OMAP4430_CM_CLKSEL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0000) -#define OMAP4_CM_CLKSEL_ABE_OFFSET 0x0008 -#define OMAP4430_CM_CLKSEL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0008) -#define OMAP4_CM_DLL_CTRL_OFFSET 0x0010 -#define OMAP4430_CM_DLL_CTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0010) -#define OMAP4_CM_CLKMODE_DPLL_CORE_OFFSET 0x0020 -#define OMAP4430_CM_CLKMODE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0020) -#define OMAP4_CM_IDLEST_DPLL_CORE_OFFSET 0x0024 -#define OMAP4430_CM_IDLEST_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0024) -#define OMAP4_CM_AUTOIDLE_DPLL_CORE_OFFSET 0x0028 -#define OMAP4430_CM_AUTOIDLE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0028) -#define OMAP4_CM_CLKSEL_DPLL_CORE_OFFSET 0x002c -#define OMAP4430_CM_CLKSEL_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x002c) -#define OMAP4_CM_DIV_M2_DPLL_CORE_OFFSET 0x0030 -#define OMAP4430_CM_DIV_M2_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0030) -#define OMAP4_CM_DIV_M3_DPLL_CORE_OFFSET 0x0034 -#define OMAP4430_CM_DIV_M3_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0034) -#define OMAP4_CM_DIV_M4_DPLL_CORE_OFFSET 0x0038 -#define OMAP4430_CM_DIV_M4_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0038) -#define OMAP4_CM_DIV_M5_DPLL_CORE_OFFSET 0x003c -#define OMAP4430_CM_DIV_M5_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x003c) -#define OMAP4_CM_DIV_M6_DPLL_CORE_OFFSET 0x0040 -#define OMAP4430_CM_DIV_M6_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0040) -#define OMAP4_CM_DIV_M7_DPLL_CORE_OFFSET 0x0044 -#define OMAP4430_CM_DIV_M7_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0044) -#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0048 -#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0048) -#define OMAP4_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET 0x004c -#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x004c) -#define OMAP4_CM_EMU_OVERRIDE_DPLL_CORE_OFFSET 0x0050 -#define OMAP4430_CM_EMU_OVERRIDE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0050) -#define OMAP4_CM_CLKMODE_DPLL_MPU_OFFSET 0x0060 -#define OMAP4430_CM_CLKMODE_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0060) -#define OMAP4_CM_IDLEST_DPLL_MPU_OFFSET 0x0064 -#define OMAP4430_CM_IDLEST_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0064) -#define OMAP4_CM_AUTOIDLE_DPLL_MPU_OFFSET 0x0068 -#define OMAP4430_CM_AUTOIDLE_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0068) -#define OMAP4_CM_CLKSEL_DPLL_MPU_OFFSET 0x006c -#define OMAP4430_CM_CLKSEL_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x006c) -#define OMAP4_CM_DIV_M2_DPLL_MPU_OFFSET 0x0070 -#define OMAP4430_CM_DIV_M2_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0070) -#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0088 -#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0088) -#define OMAP4_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET 0x008c -#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x008c) -#define OMAP4_CM_BYPCLK_DPLL_MPU_OFFSET 0x009c -#define OMAP4430_CM_BYPCLK_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x009c) -#define OMAP4_CM_CLKMODE_DPLL_IVA_OFFSET 0x00a0 -#define OMAP4430_CM_CLKMODE_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a0) -#define OMAP4_CM_IDLEST_DPLL_IVA_OFFSET 0x00a4 -#define OMAP4430_CM_IDLEST_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a4) -#define OMAP4_CM_AUTOIDLE_DPLL_IVA_OFFSET 0x00a8 -#define OMAP4430_CM_AUTOIDLE_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a8) -#define OMAP4_CM_CLKSEL_DPLL_IVA_OFFSET 0x00ac -#define OMAP4430_CM_CLKSEL_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00ac) -#define OMAP4_CM_DIV_M4_DPLL_IVA_OFFSET 0x00b8 -#define OMAP4430_CM_DIV_M4_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00b8) -#define OMAP4_CM_DIV_M5_DPLL_IVA_OFFSET 0x00bc -#define OMAP4430_CM_DIV_M5_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00bc) -#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET 0x00c8 -#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00c8) -#define OMAP4_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET 0x00cc -#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00cc) -#define OMAP4_CM_BYPCLK_DPLL_IVA_OFFSET 0x00dc -#define OMAP4430_CM_BYPCLK_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00dc) -#define OMAP4_CM_CLKMODE_DPLL_ABE_OFFSET 0x00e0 -#define OMAP4430_CM_CLKMODE_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e0) -#define OMAP4_CM_IDLEST_DPLL_ABE_OFFSET 0x00e4 -#define OMAP4430_CM_IDLEST_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e4) -#define OMAP4_CM_AUTOIDLE_DPLL_ABE_OFFSET 0x00e8 -#define OMAP4430_CM_AUTOIDLE_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e8) -#define OMAP4_CM_CLKSEL_DPLL_ABE_OFFSET 0x00ec -#define OMAP4430_CM_CLKSEL_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00ec) -#define OMAP4_CM_DIV_M2_DPLL_ABE_OFFSET 0x00f0 -#define OMAP4430_CM_DIV_M2_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f0) -#define OMAP4_CM_DIV_M3_DPLL_ABE_OFFSET 0x00f4 -#define OMAP4430_CM_DIV_M3_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f4) -#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET 0x0108 -#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0108) -#define OMAP4_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET 0x010c -#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x010c) -#define OMAP4_CM_CLKMODE_DPLL_DDRPHY_OFFSET 0x0120 -#define OMAP4430_CM_CLKMODE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0120) -#define OMAP4_CM_IDLEST_DPLL_DDRPHY_OFFSET 0x0124 -#define OMAP4430_CM_IDLEST_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0124) -#define OMAP4_CM_AUTOIDLE_DPLL_DDRPHY_OFFSET 0x0128 -#define OMAP4430_CM_AUTOIDLE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0128) -#define OMAP4_CM_CLKSEL_DPLL_DDRPHY_OFFSET 0x012c -#define OMAP4430_CM_CLKSEL_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x012c) -#define OMAP4_CM_DIV_M2_DPLL_DDRPHY_OFFSET 0x0130 -#define OMAP4430_CM_DIV_M2_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0130) -#define OMAP4_CM_DIV_M4_DPLL_DDRPHY_OFFSET 0x0138 -#define OMAP4430_CM_DIV_M4_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0138) -#define OMAP4_CM_DIV_M5_DPLL_DDRPHY_OFFSET 0x013c -#define OMAP4430_CM_DIV_M5_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x013c) -#define OMAP4_CM_DIV_M6_DPLL_DDRPHY_OFFSET 0x0140 -#define OMAP4430_CM_DIV_M6_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0140) -#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_DDRPHY_OFFSET 0x0148 -#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0148) -#define OMAP4_CM_SSC_MODFREQDIV_DPLL_DDRPHY_OFFSET 0x014c -#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x014c) -#define OMAP4_CM_SHADOW_FREQ_CONFIG1_OFFSET 0x0160 -#define OMAP4430_CM_SHADOW_FREQ_CONFIG1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0160) -#define OMAP4_CM_SHADOW_FREQ_CONFIG2_OFFSET 0x0164 -#define OMAP4430_CM_SHADOW_FREQ_CONFIG2 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0164) -#define OMAP4_CM_DYN_DEP_PRESCAL_OFFSET 0x0170 -#define OMAP4430_CM_DYN_DEP_PRESCAL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0170) -#define OMAP4_CM_RESTORE_ST_OFFSET 0x0180 -#define OMAP4430_CM_RESTORE_ST OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0180) - -/* CM1.MPU_CM1 register offsets */ -#define OMAP4_CM_MPU_CLKSTCTRL_OFFSET 0x0000 -#define OMAP4430_CM_MPU_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0000) -#define OMAP4_CM_MPU_STATICDEP_OFFSET 0x0004 -#define OMAP4430_CM_MPU_STATICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0004) -#define OMAP4_CM_MPU_DYNAMICDEP_OFFSET 0x0008 -#define OMAP4430_CM_MPU_DYNAMICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0008) -#define OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET 0x0020 -#define OMAP4430_CM_MPU_MPU_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0020) - -/* CM1.TESLA_CM1 register offsets */ -#define OMAP4_CM_TESLA_CLKSTCTRL_OFFSET 0x0000 -#define OMAP4430_CM_TESLA_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0000) -#define OMAP4_CM_TESLA_STATICDEP_OFFSET 0x0004 -#define OMAP4430_CM_TESLA_STATICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0004) -#define OMAP4_CM_TESLA_DYNAMICDEP_OFFSET 0x0008 -#define OMAP4430_CM_TESLA_DYNAMICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0008) -#define OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET 0x0020 -#define OMAP4430_CM_TESLA_TESLA_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0020) - -/* CM1.ABE_CM1 register offsets */ -#define OMAP4_CM1_ABE_CLKSTCTRL_OFFSET 0x0000 -#define OMAP4430_CM1_ABE_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0000) -#define OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET 0x0020 -#define OMAP4430_CM1_ABE_L4ABE_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0020) -#define OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET 0x0028 -#define OMAP4430_CM1_ABE_AESS_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0028) -#define OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET 0x0030 -#define OMAP4430_CM1_ABE_PDM_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0030) -#define OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET 0x0038 -#define OMAP4430_CM1_ABE_DMIC_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0038) -#define OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET 0x0040 -#define OMAP4430_CM1_ABE_MCASP_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0040) -#define OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET 0x0048 -#define OMAP4430_CM1_ABE_MCBSP1_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0048) -#define OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET 0x0050 -#define OMAP4430_CM1_ABE_MCBSP2_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0050) -#define OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET 0x0058 -#define OMAP4430_CM1_ABE_MCBSP3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0058) -#define OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET 0x0060 -#define OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0060) -#define OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET 0x0068 -#define OMAP4430_CM1_ABE_TIMER5_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0068) -#define OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET 0x0070 -#define OMAP4430_CM1_ABE_TIMER6_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0070) -#define OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET 0x0078 -#define OMAP4430_CM1_ABE_TIMER7_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0078) -#define OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET 0x0080 -#define OMAP4430_CM1_ABE_TIMER8_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0080) -#define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET 0x0088 -#define OMAP4430_CM1_ABE_WDT3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0088) - #endif diff --git a/arch/arm/mach-omap2/cm2_44xx.h b/arch/arm/mach-omap2/cm2_44xx.h index 370d295446b6..7f9b7a81f153 100644 --- a/arch/arm/mach-omap2/cm2_44xx.h +++ b/arch/arm/mach-omap2/cm2_44xx.h @@ -40,8 +40,6 @@ #define OMAP4430_CM2_L3INIT_INST 0x1300 #define OMAP4430_CM2_L4PER_INST 0x1400 #define OMAP4430_CM2_CEFUSE_INST 0x1600 -#define OMAP4430_CM2_RESTORE_INST 0x1e00 -#define OMAP4430_CM2_INSTR_INST 0x1f00 /* CM2 clockdomain register offsets (from instance start) */ #define OMAP4430_CM2_ALWAYS_ON_ALWON_CDOFFS 0x0000 @@ -62,388 +60,4 @@ #define OMAP4430_CM2_L4PER_L4SEC_CDOFFS 0x0180 #define OMAP4430_CM2_CEFUSE_CEFUSE_CDOFFS 0x0000 -/* CM2 */ - -/* CM2.OCP_SOCKET_CM2 register offsets */ -#define OMAP4_REVISION_CM2_OFFSET 0x0000 -#define OMAP4430_REVISION_CM2 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_INST, 0x0000) -#define OMAP4_CM_CM2_PROFILING_CLKCTRL_OFFSET 0x0040 -#define OMAP4430_CM_CM2_PROFILING_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_INST, 0x0040) - -/* CM2.CKGEN_CM2 register offsets */ -#define OMAP4_CM_CLKSEL_DUCATI_ISS_ROOT_OFFSET 0x0000 -#define OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0000) -#define OMAP4_CM_CLKSEL_USB_60MHZ_OFFSET 0x0004 -#define OMAP4430_CM_CLKSEL_USB_60MHZ OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0004) -#define OMAP4_CM_SCALE_FCLK_OFFSET 0x0008 -#define OMAP4430_CM_SCALE_FCLK OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0008) -#define OMAP4_CM_CORE_DVFS_PERF1_OFFSET 0x0010 -#define OMAP4430_CM_CORE_DVFS_PERF1 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0010) -#define OMAP4_CM_CORE_DVFS_PERF2_OFFSET 0x0014 -#define OMAP4430_CM_CORE_DVFS_PERF2 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0014) -#define OMAP4_CM_CORE_DVFS_PERF3_OFFSET 0x0018 -#define OMAP4430_CM_CORE_DVFS_PERF3 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0018) -#define OMAP4_CM_CORE_DVFS_PERF4_OFFSET 0x001c -#define OMAP4430_CM_CORE_DVFS_PERF4 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x001c) -#define OMAP4_CM_CORE_DVFS_CURRENT_OFFSET 0x0024 -#define OMAP4430_CM_CORE_DVFS_CURRENT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0024) -#define OMAP4_CM_IVA_DVFS_PERF_TESLA_OFFSET 0x0028 -#define OMAP4430_CM_IVA_DVFS_PERF_TESLA OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0028) -#define OMAP4_CM_IVA_DVFS_PERF_IVAHD_OFFSET 0x002c -#define OMAP4430_CM_IVA_DVFS_PERF_IVAHD OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x002c) -#define OMAP4_CM_IVA_DVFS_PERF_ABE_OFFSET 0x0030 -#define OMAP4430_CM_IVA_DVFS_PERF_ABE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0030) -#define OMAP4_CM_IVA_DVFS_CURRENT_OFFSET 0x0038 -#define OMAP4430_CM_IVA_DVFS_CURRENT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0038) -#define OMAP4_CM_CLKMODE_DPLL_PER_OFFSET 0x0040 -#define OMAP4430_CM_CLKMODE_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0040) -#define OMAP4_CM_IDLEST_DPLL_PER_OFFSET 0x0044 -#define OMAP4430_CM_IDLEST_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0044) -#define OMAP4_CM_AUTOIDLE_DPLL_PER_OFFSET 0x0048 -#define OMAP4430_CM_AUTOIDLE_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0048) -#define OMAP4_CM_CLKSEL_DPLL_PER_OFFSET 0x004c -#define OMAP4430_CM_CLKSEL_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x004c) -#define OMAP4_CM_DIV_M2_DPLL_PER_OFFSET 0x0050 -#define OMAP4430_CM_DIV_M2_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0050) -#define OMAP4_CM_DIV_M3_DPLL_PER_OFFSET 0x0054 -#define OMAP4430_CM_DIV_M3_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0054) -#define OMAP4_CM_DIV_M4_DPLL_PER_OFFSET 0x0058 -#define OMAP4430_CM_DIV_M4_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0058) -#define OMAP4_CM_DIV_M5_DPLL_PER_OFFSET 0x005c -#define OMAP4430_CM_DIV_M5_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x005c) -#define OMAP4_CM_DIV_M6_DPLL_PER_OFFSET 0x0060 -#define OMAP4430_CM_DIV_M6_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0060) -#define OMAP4_CM_DIV_M7_DPLL_PER_OFFSET 0x0064 -#define OMAP4430_CM_DIV_M7_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0064) -#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET 0x0068 -#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0068) -#define OMAP4_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x006c -#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x006c) -#define OMAP4_CM_CLKMODE_DPLL_USB_OFFSET 0x0080 -#define OMAP4430_CM_CLKMODE_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0080) -#define OMAP4_CM_IDLEST_DPLL_USB_OFFSET 0x0084 -#define OMAP4430_CM_IDLEST_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0084) -#define OMAP4_CM_AUTOIDLE_DPLL_USB_OFFSET 0x0088 -#define OMAP4430_CM_AUTOIDLE_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0088) -#define OMAP4_CM_CLKSEL_DPLL_USB_OFFSET 0x008c -#define OMAP4430_CM_CLKSEL_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x008c) -#define OMAP4_CM_DIV_M2_DPLL_USB_OFFSET 0x0090 -#define OMAP4430_CM_DIV_M2_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0090) -#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET 0x00a8 -#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00a8) -#define OMAP4_CM_SSC_MODFREQDIV_DPLL_USB_OFFSET 0x00ac -#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ac) -#define OMAP4_CM_CLKDCOLDO_DPLL_USB_OFFSET 0x00b4 -#define OMAP4430_CM_CLKDCOLDO_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00b4) -#define OMAP4_CM_CLKMODE_DPLL_UNIPRO_OFFSET 0x00c0 -#define OMAP4430_CM_CLKMODE_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00c0) -#define OMAP4_CM_IDLEST_DPLL_UNIPRO_OFFSET 0x00c4 -#define OMAP4430_CM_IDLEST_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00c4) -#define OMAP4_CM_AUTOIDLE_DPLL_UNIPRO_OFFSET 0x00c8 -#define OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00c8) -#define OMAP4_CM_CLKSEL_DPLL_UNIPRO_OFFSET 0x00cc -#define OMAP4430_CM_CLKSEL_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00cc) -#define OMAP4_CM_DIV_M2_DPLL_UNIPRO_OFFSET 0x00d0 -#define OMAP4430_CM_DIV_M2_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00d0) -#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_UNIPRO_OFFSET 0x00e8 -#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00e8) -#define OMAP4_CM_SSC_MODFREQDIV_DPLL_UNIPRO_OFFSET 0x00ec -#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ec) - -/* CM2.ALWAYS_ON_CM2 register offsets */ -#define OMAP4_CM_ALWON_CLKSTCTRL_OFFSET 0x0000 -#define OMAP4430_CM_ALWON_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0000) -#define OMAP4_CM_ALWON_MDMINTC_CLKCTRL_OFFSET 0x0020 -#define OMAP4430_CM_ALWON_MDMINTC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0020) -#define OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET 0x0028 -#define OMAP4430_CM_ALWON_SR_MPU_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0028) -#define OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET 0x0030 -#define OMAP4430_CM_ALWON_SR_IVA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0030) -#define OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET 0x0038 -#define OMAP4430_CM_ALWON_SR_CORE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0038) -#define OMAP4_CM_ALWON_USBPHY_CLKCTRL_OFFSET 0x0040 -#define OMAP4430_CM_ALWON_USBPHY_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0040) - -/* CM2.CORE_CM2 register offsets */ -#define OMAP4_CM_L3_1_CLKSTCTRL_OFFSET 0x0000 -#define OMAP4430_CM_L3_1_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0000) -#define OMAP4_CM_L3_1_DYNAMICDEP_OFFSET 0x0008 -#define OMAP4430_CM_L3_1_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0008) -#define OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET 0x0020 -#define OMAP4430_CM_L3_1_L3_1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0020) -#define OMAP4_CM_L3_2_CLKSTCTRL_OFFSET 0x0100 -#define OMAP4430_CM_L3_2_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0100) -#define OMAP4_CM_L3_2_DYNAMICDEP_OFFSET 0x0108 -#define OMAP4430_CM_L3_2_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0108) -#define OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET 0x0120 -#define OMAP4430_CM_L3_2_L3_2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0120) -#define OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET 0x0128 -#define OMAP4430_CM_L3_2_GPMC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0128) -#define OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET 0x0130 -#define OMAP4430_CM_L3_2_OCMC_RAM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0130) -#define OMAP4_CM_DUCATI_CLKSTCTRL_OFFSET 0x0200 -#define OMAP4430_CM_DUCATI_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0200) -#define OMAP4_CM_DUCATI_STATICDEP_OFFSET 0x0204 -#define OMAP4430_CM_DUCATI_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0204) -#define OMAP4_CM_DUCATI_DYNAMICDEP_OFFSET 0x0208 -#define OMAP4430_CM_DUCATI_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0208) -#define OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET 0x0220 -#define OMAP4430_CM_DUCATI_DUCATI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0220) -#define OMAP4_CM_SDMA_CLKSTCTRL_OFFSET 0x0300 -#define OMAP4430_CM_SDMA_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0300) -#define OMAP4_CM_SDMA_STATICDEP_OFFSET 0x0304 -#define OMAP4430_CM_SDMA_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0304) -#define OMAP4_CM_SDMA_DYNAMICDEP_OFFSET 0x0308 -#define OMAP4430_CM_SDMA_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0308) -#define OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET 0x0320 -#define OMAP4430_CM_SDMA_SDMA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0320) -#define OMAP4_CM_MEMIF_CLKSTCTRL_OFFSET 0x0400 -#define OMAP4430_CM_MEMIF_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0400) -#define OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET 0x0420 -#define OMAP4430_CM_MEMIF_DMM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0420) -#define OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET 0x0428 -#define OMAP4430_CM_MEMIF_EMIF_FW_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0428) -#define OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET 0x0430 -#define OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0430) -#define OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET 0x0438 -#define OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0438) -#define OMAP4_CM_MEMIF_DLL_CLKCTRL_OFFSET 0x0440 -#define OMAP4430_CM_MEMIF_DLL_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0440) -#define OMAP4_CM_MEMIF_EMIF_H1_CLKCTRL_OFFSET 0x0450 -#define OMAP4430_CM_MEMIF_EMIF_H1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0450) -#define OMAP4_CM_MEMIF_EMIF_H2_CLKCTRL_OFFSET 0x0458 -#define OMAP4430_CM_MEMIF_EMIF_H2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0458) -#define OMAP4_CM_MEMIF_DLL_H_CLKCTRL_OFFSET 0x0460 -#define OMAP4430_CM_MEMIF_DLL_H_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0460) -#define OMAP4_CM_D2D_CLKSTCTRL_OFFSET 0x0500 -#define OMAP4430_CM_D2D_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0500) -#define OMAP4_CM_D2D_STATICDEP_OFFSET 0x0504 -#define OMAP4430_CM_D2D_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0504) -#define OMAP4_CM_D2D_DYNAMICDEP_OFFSET 0x0508 -#define OMAP4430_CM_D2D_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0508) -#define OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET 0x0520 -#define OMAP4430_CM_D2D_SAD2D_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0520) -#define OMAP4_CM_D2D_MODEM_ICR_CLKCTRL_OFFSET 0x0528 -#define OMAP4430_CM_D2D_MODEM_ICR_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0528) -#define OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET 0x0530 -#define OMAP4430_CM_D2D_SAD2D_FW_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0530) -#define OMAP4_CM_L4CFG_CLKSTCTRL_OFFSET 0x0600 -#define OMAP4430_CM_L4CFG_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0600) -#define OMAP4_CM_L4CFG_DYNAMICDEP_OFFSET 0x0608 -#define OMAP4430_CM_L4CFG_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0608) -#define OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET 0x0620 -#define OMAP4430_CM_L4CFG_L4_CFG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0620) -#define OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET 0x0628 -#define OMAP4430_CM_L4CFG_HW_SEM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0628) -#define OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET 0x0630 -#define OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0630) -#define OMAP4_CM_L4CFG_SAR_ROM_CLKCTRL_OFFSET 0x0638 -#define OMAP4430_CM_L4CFG_SAR_ROM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0638) -#define OMAP4_CM_L3INSTR_CLKSTCTRL_OFFSET 0x0700 -#define OMAP4430_CM_L3INSTR_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0700) -#define OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET 0x0720 -#define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0720) -#define OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET 0x0728 -#define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0728) -#define OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET 0x0740 -#define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0740) - -/* CM2.IVAHD_CM2 register offsets */ -#define OMAP4_CM_IVAHD_CLKSTCTRL_OFFSET 0x0000 -#define OMAP4430_CM_IVAHD_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0000) -#define OMAP4_CM_IVAHD_STATICDEP_OFFSET 0x0004 -#define OMAP4430_CM_IVAHD_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0004) -#define OMAP4_CM_IVAHD_DYNAMICDEP_OFFSET 0x0008 -#define OMAP4430_CM_IVAHD_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0008) -#define OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET 0x0020 -#define OMAP4430_CM_IVAHD_IVAHD_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0020) -#define OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET 0x0028 -#define OMAP4430_CM_IVAHD_SL2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0028) - -/* CM2.CAM_CM2 register offsets */ -#define OMAP4_CM_CAM_CLKSTCTRL_OFFSET 0x0000 -#define OMAP4430_CM_CAM_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0000) -#define OMAP4_CM_CAM_STATICDEP_OFFSET 0x0004 -#define OMAP4430_CM_CAM_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0004) -#define OMAP4_CM_CAM_DYNAMICDEP_OFFSET 0x0008 -#define OMAP4430_CM_CAM_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0008) -#define OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET 0x0020 -#define OMAP4430_CM_CAM_ISS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0020) -#define OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET 0x0028 -#define OMAP4430_CM_CAM_FDIF_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0028) - -/* CM2.DSS_CM2 register offsets */ -#define OMAP4_CM_DSS_CLKSTCTRL_OFFSET 0x0000 -#define OMAP4430_CM_DSS_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0000) -#define OMAP4_CM_DSS_STATICDEP_OFFSET 0x0004 -#define OMAP4430_CM_DSS_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0004) -#define OMAP4_CM_DSS_DYNAMICDEP_OFFSET 0x0008 -#define OMAP4430_CM_DSS_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0008) -#define OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET 0x0020 -#define OMAP4430_CM_DSS_DSS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0020) -#define OMAP4_CM_DSS_DEISS_CLKCTRL_OFFSET 0x0028 -#define OMAP4430_CM_DSS_DEISS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0028) - -/* CM2.GFX_CM2 register offsets */ -#define OMAP4_CM_GFX_CLKSTCTRL_OFFSET 0x0000 -#define OMAP4430_CM_GFX_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_INST, 0x0000) -#define OMAP4_CM_GFX_STATICDEP_OFFSET 0x0004 -#define OMAP4430_CM_GFX_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_INST, 0x0004) -#define OMAP4_CM_GFX_DYNAMICDEP_OFFSET 0x0008 -#define OMAP4430_CM_GFX_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_INST, 0x0008) -#define OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET 0x0020 -#define OMAP4430_CM_GFX_GFX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_INST, 0x0020) - -/* CM2.L3INIT_CM2 register offsets */ -#define OMAP4_CM_L3INIT_CLKSTCTRL_OFFSET 0x0000 -#define OMAP4430_CM_L3INIT_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0000) -#define OMAP4_CM_L3INIT_STATICDEP_OFFSET 0x0004 -#define OMAP4430_CM_L3INIT_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0004) -#define OMAP4_CM_L3INIT_DYNAMICDEP_OFFSET 0x0008 -#define OMAP4430_CM_L3INIT_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0008) -#define OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET 0x0028 -#define OMAP4430_CM_L3INIT_MMC1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0028) -#define OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET 0x0030 -#define OMAP4430_CM_L3INIT_MMC2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0030) -#define OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET 0x0038 -#define OMAP4430_CM_L3INIT_HSI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0038) -#define OMAP4_CM_L3INIT_UNIPRO1_CLKCTRL_OFFSET 0x0040 -#define OMAP4430_CM_L3INIT_UNIPRO1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0040) -#define OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET 0x0058 -#define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0058) -#define OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET 0x0060 -#define OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0060) -#define OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET 0x0068 -#define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0068) -#define OMAP4_CM_L3INIT_P1500_CLKCTRL_OFFSET 0x0078 -#define OMAP4430_CM_L3INIT_P1500_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0078) -#define OMAP4_CM_L3INIT_EMAC_CLKCTRL_OFFSET 0x0080 -#define OMAP4430_CM_L3INIT_EMAC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0080) -#define OMAP4_CM_L3INIT_SATA_CLKCTRL_OFFSET 0x0088 -#define OMAP4430_CM_L3INIT_SATA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0088) -#define OMAP4_CM_L3INIT_TPPSS_CLKCTRL_OFFSET 0x0090 -#define OMAP4430_CM_L3INIT_TPPSS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0090) -#define OMAP4_CM_L3INIT_PCIESS_CLKCTRL_OFFSET 0x0098 -#define OMAP4430_CM_L3INIT_PCIESS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0098) -#define OMAP4_CM_L3INIT_CCPTX_CLKCTRL_OFFSET 0x00a8 -#define OMAP4430_CM_L3INIT_CCPTX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00a8) -#define OMAP4_CM_L3INIT_XHPI_CLKCTRL_OFFSET 0x00c0 -#define OMAP4430_CM_L3INIT_XHPI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00c0) -#define OMAP4_CM_L3INIT_MMC6_CLKCTRL_OFFSET 0x00c8 -#define OMAP4430_CM_L3INIT_MMC6_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00c8) -#define OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET 0x00d0 -#define OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00d0) -#define OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET 0x00e0 -#define OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00e0) - -/* CM2.L4PER_CM2 register offsets */ -#define OMAP4_CM_L4PER_CLKSTCTRL_OFFSET 0x0000 -#define OMAP4430_CM_L4PER_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0000) -#define OMAP4_CM_L4PER_DYNAMICDEP_OFFSET 0x0008 -#define OMAP4430_CM_L4PER_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0008) -#define OMAP4_CM_L4PER_ADC_CLKCTRL_OFFSET 0x0020 -#define OMAP4430_CM_L4PER_ADC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0020) -#define OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET 0x0028 -#define OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0028) -#define OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET 0x0030 -#define OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0030) -#define OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET 0x0038 -#define OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0038) -#define OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET 0x0040 -#define OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0040) -#define OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET 0x0048 -#define OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0048) -#define OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET 0x0050 -#define OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0050) -#define OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET 0x0058 -#define OMAP4430_CM_L4PER_ELM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0058) -#define OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET 0x0060 -#define OMAP4430_CM_L4PER_GPIO2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0060) -#define OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET 0x0068 -#define OMAP4430_CM_L4PER_GPIO3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0068) -#define OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET 0x0070 -#define OMAP4430_CM_L4PER_GPIO4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0070) -#define OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET 0x0078 -#define OMAP4430_CM_L4PER_GPIO5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0078) -#define OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET 0x0080 -#define OMAP4430_CM_L4PER_GPIO6_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0080) -#define OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET 0x0088 -#define OMAP4430_CM_L4PER_HDQ1W_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0088) -#define OMAP4_CM_L4PER_HECC1_CLKCTRL_OFFSET 0x0090 -#define OMAP4430_CM_L4PER_HECC1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0090) -#define OMAP4_CM_L4PER_HECC2_CLKCTRL_OFFSET 0x0098 -#define OMAP4430_CM_L4PER_HECC2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0098) -#define OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET 0x00a0 -#define OMAP4430_CM_L4PER_I2C1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00a0) -#define OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET 0x00a8 -#define OMAP4430_CM_L4PER_I2C2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00a8) -#define OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET 0x00b0 -#define OMAP4430_CM_L4PER_I2C3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00b0) -#define OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET 0x00b8 -#define OMAP4430_CM_L4PER_I2C4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00b8) -#define OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET 0x00c0 -#define OMAP4430_CM_L4PER_L4PER_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00c0) -#define OMAP4_CM_L4PER_MCASP2_CLKCTRL_OFFSET 0x00d0 -#define OMAP4430_CM_L4PER_MCASP2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00d0) -#define OMAP4_CM_L4PER_MCASP3_CLKCTRL_OFFSET 0x00d8 -#define OMAP4430_CM_L4PER_MCASP3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00d8) -#define OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET 0x00e0 -#define OMAP4430_CM_L4PER_MCBSP4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00e0) -#define OMAP4_CM_L4PER_MGATE_CLKCTRL_OFFSET 0x00e8 -#define OMAP4430_CM_L4PER_MGATE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00e8) -#define OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET 0x00f0 -#define OMAP4430_CM_L4PER_MCSPI1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00f0) -#define OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET 0x00f8 -#define OMAP4430_CM_L4PER_MCSPI2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00f8) -#define OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET 0x0100 -#define OMAP4430_CM_L4PER_MCSPI3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0100) -#define OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET 0x0108 -#define OMAP4430_CM_L4PER_MCSPI4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0108) -#define OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET 0x0120 -#define OMAP4430_CM_L4PER_MMCSD3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0120) -#define OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET 0x0128 -#define OMAP4430_CM_L4PER_MMCSD4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0128) -#define OMAP4_CM_L4PER_MSPROHG_CLKCTRL_OFFSET 0x0130 -#define OMAP4430_CM_L4PER_MSPROHG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0130) -#define OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET 0x0138 -#define OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0138) -#define OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET 0x0140 -#define OMAP4430_CM_L4PER_UART1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0140) -#define OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET 0x0148 -#define OMAP4430_CM_L4PER_UART2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0148) -#define OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET 0x0150 -#define OMAP4430_CM_L4PER_UART3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0150) -#define OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET 0x0158 -#define OMAP4430_CM_L4PER_UART4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0158) -#define OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET 0x0160 -#define OMAP4430_CM_L4PER_MMCSD5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0160) -#define OMAP4_CM_L4PER_I2C5_CLKCTRL_OFFSET 0x0168 -#define OMAP4430_CM_L4PER_I2C5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0168) -#define OMAP4_CM_L4SEC_CLKSTCTRL_OFFSET 0x0180 -#define OMAP4430_CM_L4SEC_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0180) -#define OMAP4_CM_L4SEC_STATICDEP_OFFSET 0x0184 -#define OMAP4430_CM_L4SEC_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0184) -#define OMAP4_CM_L4SEC_DYNAMICDEP_OFFSET 0x0188 -#define OMAP4430_CM_L4SEC_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0188) -#define OMAP4_CM_L4SEC_AES1_CLKCTRL_OFFSET 0x01a0 -#define OMAP4430_CM_L4SEC_AES1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01a0) -#define OMAP4_CM_L4SEC_AES2_CLKCTRL_OFFSET 0x01a8 -#define OMAP4430_CM_L4SEC_AES2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01a8) -#define OMAP4_CM_L4SEC_DES3DES_CLKCTRL_OFFSET 0x01b0 -#define OMAP4430_CM_L4SEC_DES3DES_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01b0) -#define OMAP4_CM_L4SEC_PKAEIP29_CLKCTRL_OFFSET 0x01b8 -#define OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01b8) -#define OMAP4_CM_L4SEC_RNG_CLKCTRL_OFFSET 0x01c0 -#define OMAP4430_CM_L4SEC_RNG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01c0) -#define OMAP4_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET 0x01c8 -#define OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01c8) -#define OMAP4_CM_L4SEC_CRYPTODMA_CLKCTRL_OFFSET 0x01d8 -#define OMAP4430_CM_L4SEC_CRYPTODMA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01d8) - -/* CM2.CEFUSE_CM2 register offsets */ -#define OMAP4_CM_CEFUSE_CLKSTCTRL_OFFSET 0x0000 -#define OMAP4430_CM_CEFUSE_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_INST, 0x0000) -#define OMAP4_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET 0x0020 -#define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_INST, 0x0020) - #endif diff --git a/arch/arm/mach-omap2/scrm44xx.h b/arch/arm/mach-omap2/scrm44xx.h index 3f530b89e4c9..2e861aa951f0 100644 --- a/arch/arm/mach-omap2/scrm44xx.h +++ b/arch/arm/mach-omap2/scrm44xx.h @@ -22,72 +22,7 @@ OMAP2_L4_IO_ADDRESS(OMAP4_SCRM_BASE + (reg)) /* Registers offset */ -#define OMAP4_SCRM_REVISION_SCRM_OFFSET 0x0000 -#define OMAP4_SCRM_REVISION_SCRM OMAP44XX_SCRM_REGADDR(0x0000) -#define OMAP4_SCRM_CLKSETUPTIME_OFFSET 0x0100 #define OMAP4_SCRM_CLKSETUPTIME OMAP44XX_SCRM_REGADDR(0x0100) -#define OMAP4_SCRM_PMICSETUPTIME_OFFSET 0x0104 -#define OMAP4_SCRM_PMICSETUPTIME OMAP44XX_SCRM_REGADDR(0x0104) -#define OMAP4_SCRM_ALTCLKSRC_OFFSET 0x0110 -#define OMAP4_SCRM_ALTCLKSRC OMAP44XX_SCRM_REGADDR(0x0110) -#define OMAP4_SCRM_MODEMCLKM_OFFSET 0x0118 -#define OMAP4_SCRM_MODEMCLKM OMAP44XX_SCRM_REGADDR(0x0118) -#define OMAP4_SCRM_D2DCLKM_OFFSET 0x011c -#define OMAP4_SCRM_D2DCLKM OMAP44XX_SCRM_REGADDR(0x011c) -#define OMAP4_SCRM_EXTCLKREQ_OFFSET 0x0200 -#define OMAP4_SCRM_EXTCLKREQ OMAP44XX_SCRM_REGADDR(0x0200) -#define OMAP4_SCRM_ACCCLKREQ_OFFSET 0x0204 -#define OMAP4_SCRM_ACCCLKREQ OMAP44XX_SCRM_REGADDR(0x0204) -#define OMAP4_SCRM_PWRREQ_OFFSET 0x0208 -#define OMAP4_SCRM_PWRREQ OMAP44XX_SCRM_REGADDR(0x0208) -#define OMAP4_SCRM_AUXCLKREQ0_OFFSET 0x0210 -#define OMAP4_SCRM_AUXCLKREQ0 OMAP44XX_SCRM_REGADDR(0x0210) -#define OMAP4_SCRM_AUXCLKREQ1_OFFSET 0x0214 -#define OMAP4_SCRM_AUXCLKREQ1 OMAP44XX_SCRM_REGADDR(0x0214) -#define OMAP4_SCRM_AUXCLKREQ2_OFFSET 0x0218 -#define OMAP4_SCRM_AUXCLKREQ2 OMAP44XX_SCRM_REGADDR(0x0218) -#define OMAP4_SCRM_AUXCLKREQ3_OFFSET 0x021c -#define OMAP4_SCRM_AUXCLKREQ3 OMAP44XX_SCRM_REGADDR(0x021c) -#define OMAP4_SCRM_AUXCLKREQ4_OFFSET 0x0220 -#define OMAP4_SCRM_AUXCLKREQ4 OMAP44XX_SCRM_REGADDR(0x0220) -#define OMAP4_SCRM_AUXCLKREQ5_OFFSET 0x0224 -#define OMAP4_SCRM_AUXCLKREQ5 OMAP44XX_SCRM_REGADDR(0x0224) -#define OMAP4_SCRM_D2DCLKREQ_OFFSET 0x0234 -#define OMAP4_SCRM_D2DCLKREQ OMAP44XX_SCRM_REGADDR(0x0234) -#define OMAP4_SCRM_AUXCLK0_OFFSET 0x0310 -#define OMAP4_SCRM_AUXCLK0 OMAP44XX_SCRM_REGADDR(0x0310) -#define OMAP4_SCRM_AUXCLK1_OFFSET 0x0314 -#define OMAP4_SCRM_AUXCLK1 OMAP44XX_SCRM_REGADDR(0x0314) -#define OMAP4_SCRM_AUXCLK2_OFFSET 0x0318 -#define OMAP4_SCRM_AUXCLK2 OMAP44XX_SCRM_REGADDR(0x0318) -#define OMAP4_SCRM_AUXCLK3_OFFSET 0x031c -#define OMAP4_SCRM_AUXCLK3 OMAP44XX_SCRM_REGADDR(0x031c) -#define OMAP4_SCRM_AUXCLK4_OFFSET 0x0320 -#define OMAP4_SCRM_AUXCLK4 OMAP44XX_SCRM_REGADDR(0x0320) -#define OMAP4_SCRM_AUXCLK5_OFFSET 0x0324 -#define OMAP4_SCRM_AUXCLK5 OMAP44XX_SCRM_REGADDR(0x0324) -#define OMAP4_SCRM_RSTTIME_OFFSET 0x0400 -#define OMAP4_SCRM_RSTTIME OMAP44XX_SCRM_REGADDR(0x0400) -#define OMAP4_SCRM_MODEMRSTCTRL_OFFSET 0x0418 -#define OMAP4_SCRM_MODEMRSTCTRL OMAP44XX_SCRM_REGADDR(0x0418) -#define OMAP4_SCRM_D2DRSTCTRL_OFFSET 0x041c -#define OMAP4_SCRM_D2DRSTCTRL OMAP44XX_SCRM_REGADDR(0x041c) -#define OMAP4_SCRM_EXTPWRONRSTCTRL_OFFSET 0x0420 -#define OMAP4_SCRM_EXTPWRONRSTCTRL OMAP44XX_SCRM_REGADDR(0x0420) -#define OMAP4_SCRM_EXTWARMRSTST_OFFSET 0x0510 -#define OMAP4_SCRM_EXTWARMRSTST OMAP44XX_SCRM_REGADDR(0x0510) -#define OMAP4_SCRM_APEWARMRSTST_OFFSET 0x0514 -#define OMAP4_SCRM_APEWARMRSTST OMAP44XX_SCRM_REGADDR(0x0514) -#define OMAP4_SCRM_MODEMWARMRSTST_OFFSET 0x0518 -#define OMAP4_SCRM_MODEMWARMRSTST OMAP44XX_SCRM_REGADDR(0x0518) -#define OMAP4_SCRM_D2DWARMRSTST_OFFSET 0x051c -#define OMAP4_SCRM_D2DWARMRSTST OMAP44XX_SCRM_REGADDR(0x051c) - -/* Registers shifts and masks */ - -/* REVISION_SCRM */ -#define OMAP4_REV_SHIFT 0 -#define OMAP4_REV_MASK (0xff << 0) /* CLKSETUPTIME */ #define OMAP4_DOWNTIME_SHIFT 16 @@ -95,80 +30,4 @@ #define OMAP4_SETUPTIME_SHIFT 0 #define OMAP4_SETUPTIME_MASK (0xfff << 0) -/* PMICSETUPTIME */ -#define OMAP4_WAKEUPTIME_SHIFT 16 -#define OMAP4_WAKEUPTIME_MASK (0x3f << 16) -#define OMAP4_SLEEPTIME_SHIFT 0 -#define OMAP4_SLEEPTIME_MASK (0x3f << 0) - -/* ALTCLKSRC */ -#define OMAP4_ENABLE_EXT_SHIFT 3 -#define OMAP4_ENABLE_EXT_MASK (1 << 3) -#define OMAP4_ENABLE_INT_SHIFT 2 -#define OMAP4_ENABLE_INT_MASK (1 << 2) -#define OMAP4_ALTCLKSRC_MODE_SHIFT 0 -#define OMAP4_ALTCLKSRC_MODE_MASK (0x3 << 0) - -/* MODEMCLKM */ -#define OMAP4_CLK_32KHZ_SHIFT 0 -#define OMAP4_CLK_32KHZ_MASK (1 << 0) - -/* D2DCLKM */ -#define OMAP4_SYSCLK_SHIFT 1 -#define OMAP4_SYSCLK_MASK (1 << 1) - -/* EXTCLKREQ */ -#define OMAP4_POLARITY_SHIFT 0 -#define OMAP4_POLARITY_MASK (1 << 0) - -/* AUXCLKREQ0 */ -#define OMAP4_MAPPING_SHIFT 2 -#define OMAP4_MAPPING_MASK (0x7 << 2) -#define OMAP4_MAPPING_WIDTH 3 -#define OMAP4_ACCURACY_SHIFT 1 -#define OMAP4_ACCURACY_MASK (1 << 1) - -/* AUXCLK0 */ -#define OMAP4_CLKDIV_SHIFT 16 -#define OMAP4_CLKDIV_MASK (0xf << 16) -#define OMAP4_CLKDIV_WIDTH 4 -#define OMAP4_DISABLECLK_SHIFT 9 -#define OMAP4_DISABLECLK_MASK (1 << 9) -#define OMAP4_ENABLE_SHIFT 8 -#define OMAP4_ENABLE_MASK (1 << 8) -#define OMAP4_SRCSELECT_SHIFT 1 -#define OMAP4_SRCSELECT_MASK (0x3 << 1) - -/* RSTTIME */ -#define OMAP4_RSTTIME_SHIFT 0 -#define OMAP4_RSTTIME_MASK (0xf << 0) - -/* MODEMRSTCTRL */ -#define OMAP4_WARMRST_SHIFT 1 -#define OMAP4_WARMRST_MASK (1 << 1) -#define OMAP4_COLDRST_SHIFT 0 -#define OMAP4_COLDRST_MASK (1 << 0) - -/* EXTPWRONRSTCTRL */ -#define OMAP4_PWRONRST_SHIFT 1 -#define OMAP4_PWRONRST_MASK (1 << 1) -#define OMAP4_ENABLE_EXTPWRONRSTCTRL_SHIFT 0 -#define OMAP4_ENABLE_EXTPWRONRSTCTRL_MASK (1 << 0) - -/* EXTWARMRSTST */ -#define OMAP4_EXTWARMRSTST_SHIFT 0 -#define OMAP4_EXTWARMRSTST_MASK (1 << 0) - -/* APEWARMRSTST */ -#define OMAP4_APEWARMRSTST_SHIFT 1 -#define OMAP4_APEWARMRSTST_MASK (1 << 1) - -/* MODEMWARMRSTST */ -#define OMAP4_MODEMWARMRSTST_SHIFT 2 -#define OMAP4_MODEMWARMRSTST_MASK (1 << 2) - -/* D2DWARMRSTST */ -#define OMAP4_D2DWARMRSTST_SHIFT 3 -#define OMAP4_D2DWARMRSTST_MASK (1 << 3) - #endif |