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-rw-r--r--arch/riscv/boot/dts/starfive/jh7110.dtsi2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index a2831f719bca..e5d0445767f1 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -635,7 +635,7 @@
clocks = <&clkgen JH7110_DMA1P_CLK_AXI>,
<&clkgen JH7110_DMA1P_CLK_AHB>,
<&clkgen JH7110_NOC_BUS_CLK_STG_AXI>;
- clock-names = "core-clk", "cfgr-clk", "stg_clk";
+ clock-names = "core-clk", "cfgr-clk", "noc-clk";
resets = <&rstgen RSTN_U0_DW_DMA1P_AXI>,
<&rstgen RSTN_U0_DW_DMA1P_AHB>,
<&rstgen RSTN_U0_NOC_BUS_STG_AXI_N>;