diff options
| -rw-r--r-- | arch/arm/mach-imx/Makefile | 1 | ||||
| -rw-r--r-- | arch/arm/mach-imx/cache-l2x0.c | 56 | ||||
| -rw-r--r-- | arch/arm/mach-imx/mm-imx3.c | 38 |
3 files changed, 38 insertions, 57 deletions
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 8ec4a4ca1489..0aa86d22236b 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -10,7 +10,6 @@ obj-$(CONFIG_MACH_MX27) += clock-imx27.o mm-imx27.o ehci-imx27.o obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o clock-imx31.o iomux-imx31.o ehci-imx31.o obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clock-imx35.o ehci-imx35.o -obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o # Support for CMOS sensor interface obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o diff --git a/arch/arm/mach-imx/cache-l2x0.c b/arch/arm/mach-imx/cache-l2x0.c deleted file mode 100644 index 69d1322add3c..000000000000 --- a/arch/arm/mach-imx/cache-l2x0.c +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Copyright (C) 2009-2010 Pengutronix - * Sascha Hauer <s.hauer@pengutronix.de> - * Juergen Beisert <j.beisert@pengutronix.de> - * - * This program is free software; you can redistribute it and/or modify it under - * the terms of the GNU General Public License version 2 as published by the - * Free Software Foundation. - */ - -#include <linux/init.h> -#include <linux/err.h> -#include <linux/kernel.h> - -#include <asm/hardware/cache-l2x0.h> - -#include <mach/hardware.h> - -static int mxc_init_l2x0(void) -{ - void __iomem *l2x0_base; - void __iomem *clkctl_base; - - if (!cpu_is_mx31() && !cpu_is_mx35()) - return 0; - -/* - * First of all, we must repair broken chip settings. There are some - * i.MX35 CPUs in the wild, comming with bogus L2 cache settings. These - * misconfigured CPUs will run amok immediately when the L2 cache gets enabled. - * Workaraound is to setup the correct register setting prior enabling the - * L2 cache. This should not hurt already working CPUs, as they are using the - * same value. - */ -#define L2_MEM_VAL 0x10 - - clkctl_base = ioremap(MX35_CLKCTL_BASE_ADDR, 4096); - if (clkctl_base != NULL) { - writel(0x00000515, clkctl_base + L2_MEM_VAL); - iounmap(clkctl_base); - } else { - pr_err("L2 cache: Cannot fix timing. Trying to continue without\n"); - } - - l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096); - if (IS_ERR(l2x0_base)) { - printk(KERN_ERR "remapping L2 cache area failed with %ld\n", - PTR_ERR(l2x0_base)); - return 0; - } - - l2x0_init(l2x0_base, 0x00030024, 0x00000000); - - return 0; -} -arch_initcall(mxc_init_l2x0); diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c index e06eed12a7b0..ffa33b4dedde 100644 --- a/arch/arm/mach-imx/mm-imx3.c +++ b/arch/arm/mach-imx/mm-imx3.c @@ -21,6 +21,7 @@ #include <linux/err.h> #include <asm/pgtable.h> +#include <asm/hardware/cache-l2x0.h> #include <asm/mach/map.h> #include <mach/common.h> @@ -29,6 +30,39 @@ #include <mach/iomux-v3.h> #include <mach/irqs.h> +void imx3_init_l2x0(void) +{ + void __iomem *l2x0_base; + void __iomem *clkctl_base; + +/* + * First of all, we must repair broken chip settings. There are some + * i.MX35 CPUs in the wild, comming with bogus L2 cache settings. These + * misconfigured CPUs will run amok immediately when the L2 cache gets enabled. + * Workaraound is to setup the correct register setting prior enabling the + * L2 cache. This should not hurt already working CPUs, as they are using the + * same value. + */ +#define L2_MEM_VAL 0x10 + + clkctl_base = ioremap(MX35_CLKCTL_BASE_ADDR, 4096); + if (clkctl_base != NULL) { + writel(0x00000515, clkctl_base + L2_MEM_VAL); + iounmap(clkctl_base); + } else { + pr_err("L2 cache: Cannot fix timing. Trying to continue without\n"); + } + + l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096); + if (IS_ERR(l2x0_base)) { + printk(KERN_ERR "remapping L2 cache area failed with %ld\n", + PTR_ERR(l2x0_base)); + return; + } + + l2x0_init(l2x0_base, 0x00030024, 0x00000000); +} + static struct map_desc mx31_io_desc[] __initdata = { imx_map_entry(MX31, X_MEMC, MT_DEVICE), imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED), @@ -102,6 +136,8 @@ void __init imx31_soc_init(void) { int to_version = mx31_revision() >> 4; + imx3_init_l2x0(); + mxc_register_gpio("imx31-gpio", 0, MX31_GPIO1_BASE_ADDR, SZ_16K, MX31_INT_GPIO1, 0); mxc_register_gpio("imx31-gpio", 1, MX31_GPIO2_BASE_ADDR, SZ_16K, MX31_INT_GPIO2, 0); mxc_register_gpio("imx31-gpio", 2, MX31_GPIO3_BASE_ADDR, SZ_16K, MX31_INT_GPIO3, 0); @@ -154,6 +190,8 @@ void __init imx35_soc_init(void) { int to_version = mx35_revision() >> 4; + imx3_init_l2x0(); + /* i.mx35 has the i.mx31 type gpio */ mxc_register_gpio("imx31-gpio", 0, MX35_GPIO1_BASE_ADDR, SZ_16K, MX35_INT_GPIO1, 0); mxc_register_gpio("imx31-gpio", 1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0); |