diff options
31 files changed, 183 insertions, 695 deletions
diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt index 14510b215480..bdadc3da9556 100644 --- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt @@ -21,8 +21,6 @@ Required root node properties: - "samsung,smdk5420" - for Exynos5420-based Samsung SMDK5420 eval board. - "samsung,tm2" - for Exynos5433-based Samsung TM2 board. - "samsung,tm2e" - for Exynos5433-based Samsung TM2E board. - - "samsung,sd5v1" - for Exynos5440-based Samsung board. - - "samsung,ssdk5440" - for Exynos5440-based Samsung board. * Other companies Exynos SoC based * FriendlyARM diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 775fe23fe3b8..1b5d6d1a90f9 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -193,8 +193,6 @@ dtb-$(CONFIG_ARCH_EXYNOS5) += \ exynos5422-odroidxu3.dtb \ exynos5422-odroidxu3-lite.dtb \ exynos5422-odroidxu4.dtb \ - exynos5440-sd5v1.dtb \ - exynos5440-ssdk5440.dtb \ exynos5800-peach-pi.dtb dtb-$(CONFIG_ARCH_GEMINI) += \ gemini-dlink-dir-685.dtb \ diff --git a/arch/arm/boot/dts/exynos-syscon-restart.dtsi b/arch/arm/boot/dts/exynos-syscon-restart.dtsi index 4b3dd0549a54..ecf416690a15 100644 --- a/arch/arm/boot/dts/exynos-syscon-restart.dtsi +++ b/arch/arm/boot/dts/exynos-syscon-restart.dtsi @@ -3,22 +3,18 @@ * Samsung's Exynos SoC syscon reboot/poweroff nodes common definition. */ -/ { - soc { - compatible = "simple-bus"; - - poweroff: syscon-poweroff { - compatible = "syscon-poweroff"; - regmap = <&pmu_system_controller>; - offset = <0x330C>; /* PS_HOLD_CONTROL */ - mask = <0x5200>; /* reset value */ - }; +&pmu_system_controller { + poweroff: syscon-poweroff { + compatible = "syscon-poweroff"; + regmap = <&pmu_system_controller>; + offset = <0x330C>; /* PS_HOLD_CONTROL */ + mask = <0x5200>; /* reset value */ + }; - reboot: syscon-reboot { - compatible = "syscon-reboot"; - regmap = <&pmu_system_controller>; - offset = <0x0400>; /* SWRESET */ - mask = <0x1>; - }; + reboot: syscon-reboot { + compatible = "syscon-reboot"; + regmap = <&pmu_system_controller>; + offset = <0x0400>; /* SWRESET */ + mask = <0x1>; }; }; diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts b/arch/arm/boot/dts/exynos3250-rinato.dts index 2c3460781cc6..2a6b828c01b7 100644 --- a/arch/arm/boot/dts/exynos3250-rinato.dts +++ b/arch/arm/boot/dts/exynos3250-rinato.dts @@ -24,6 +24,10 @@ i2c7 = &i2c_max77836; }; + chosen { + stdout-path = &serial_1; + }; + memory@40000000 { device_type = "memory"; reg = <0x40000000 0x1ff00000>; diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi index 0a5f989d963b..962af97c1883 100644 --- a/arch/arm/boot/dts/exynos3250.dtsi +++ b/arch/arm/boot/dts/exynos3250.dtsi @@ -15,7 +15,6 @@ */ #include "exynos4-cpu-thermal.dtsi" -#include "exynos-syscon-restart.dtsi" #include <dt-bindings/clock/exynos3250.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> @@ -919,3 +918,4 @@ }; #include "exynos3250-pinctrl.dtsi" +#include "exynos-syscon-restart.dtsi" diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index 909a9f2bf5be..dfe41b698745 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi @@ -20,7 +20,6 @@ #include <dt-bindings/clock/exynos-audss-clk.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> -#include "exynos-syscon-restart.dtsi" / { interrupt-parent = <&gic>; @@ -1025,3 +1024,5 @@ }; }; }; + +#include "exynos-syscon-restart.dtsi" diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts index 9a310e841d5d..2ab99f9f3d0a 100644 --- a/arch/arm/boot/dts/exynos4210-origen.dts +++ b/arch/arm/boot/dts/exynos4210-origen.dts @@ -34,26 +34,17 @@ stdout-path = &serial_2; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - mmc_reg: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "VMEM_VDD_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpx1 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + mmc_reg: voltage-regulator { + compatible = "regulator-fixed"; + regulator-name = "VMEM_VDD_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpx1 1 GPIO_ACTIVE_HIGH>; + enable-active-high; }; gpio_keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; up { label = "Up"; @@ -131,12 +122,23 @@ cpu0-supply = <&buck1_reg>; }; +&exynos_usbphy { + status = "okay"; +}; + &fimd { pinctrl-0 = <&lcd_en &lcd_clk &lcd_data24 &pwm0_out>; pinctrl-names = "default"; status = "okay"; }; +&hsotg { + vusb_d-supply = <&ldo3_reg>; + vusb_a-supply = <&ldo8_reg>; + dr_mode = "peripheral"; + status = "okay"; +}; + &i2c_0 { status = "okay"; samsung,i2c-sda-delay = <100>; diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts index eaeeb4f6b84a..6f1d76cb7951 100644 --- a/arch/arm/boot/dts/exynos4210-trats.dts +++ b/arch/arm/boot/dts/exynos4210-trats.dts @@ -259,8 +259,8 @@ reg = <0x48>; interrupt-parent = <&gpx0>; interrupts = <4 IRQ_TYPE_EDGE_FALLING>; - x-size = <720>; - y-size = <1280>; + touchscreen-size-x = <720>; + touchscreen-size-y = <1280>; avdd-supply = <&tsp_reg>; vdd-supply = <&tsp_reg>; }; diff --git a/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi b/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi index ee8e1f445370..30eee5942eff 100644 --- a/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi +++ b/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi @@ -15,24 +15,22 @@ i2c10 = &i2c_cm36651; }; - regulators { - lcd_vdd3_reg: voltage-regulator-2 { - compatible = "regulator-fixed"; - regulator-name = "LCD_VDD_2.2V"; - regulator-min-microvolt = <2200000>; - regulator-max-microvolt = <2200000>; - gpio = <&gpc0 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + lcd_vdd3_reg: voltage-regulator-6 { + compatible = "regulator-fixed"; + regulator-name = "LCD_VDD_2.2V"; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2200000>; + gpio = <&gpc0 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; - ps_als_reg: voltage-regulator-5 { - compatible = "regulator-fixed"; - regulator-name = "LED_A_3.0V"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - gpio = <&gpj0 5 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + ps_als_reg: voltage-regulator-7 { + compatible = "regulator-fixed"; + regulator-name = "LED_A_3.0V"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpj0 5 GPIO_ACTIVE_HIGH>; + enable-active-high; }; i2c_ak8975: i2c-gpio-0 { @@ -120,8 +118,8 @@ reg = <0x48>; interrupt-parent = <&gpm2>; interrupts = <3 IRQ_TYPE_EDGE_FALLING>; - x-size = <720>; - y-size = <1280>; + touchscreen-size-x = <720>; + touchscreen-size-y = <1280>; avdd-supply = <&ldo23_reg>; vdd-supply = <&ldo24_reg>; }; diff --git a/arch/arm/boot/dts/exynos4412-midas.dtsi b/arch/arm/boot/dts/exynos4412-midas.dtsi index 76f2b30f1731..dc11ca1673e8 100644 --- a/arch/arm/boot/dts/exynos4412-midas.dtsi +++ b/arch/arm/boot/dts/exynos4412-midas.dtsi @@ -46,56 +46,50 @@ }; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - cam_io_reg: voltage-regulator-1 { - compatible = "regulator-fixed"; - regulator-name = "CAM_SENSOR_A"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - enable-active-high; - status = "disabled"; - }; + cam_io_reg: voltage-regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "CAM_SENSOR_A"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + enable-active-high; + status = "disabled"; + }; - cam_af_reg: voltage-regulator-3 { - compatible = "regulator-fixed"; - regulator-name = "CAM_AF"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - enable-active-high; - status = "disabled"; - }; + cam_af_reg: voltage-regulator-2 { + compatible = "regulator-fixed"; + regulator-name = "CAM_AF"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + enable-active-high; + status = "disabled"; + }; - vsil12: voltage-regulator-6 { - compatible = "regulator-fixed"; - regulator-name = "VSIL_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - gpio = <&gpl0 4 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&buck7_reg>; - }; + vsil12: voltage-regulator-3 { + compatible = "regulator-fixed"; + regulator-name = "VSIL_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + gpio = <&gpl0 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&buck7_reg>; + }; - vcc33mhl: voltage-regulator-7 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3.3_MHL"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpl0 4 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + vcc33mhl: voltage-regulator-4 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3.3_MHL"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpl0 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; - vcc18mhl: voltage-regulator-8 { - compatible = "regulator-fixed"; - regulator-name = "VCC_1.8_MHL"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpl0 4 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + vcc18mhl: voltage-regulator-5 { + compatible = "regulator-fixed"; + regulator-name = "VCC_1.8_MHL"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpl0 4 GPIO_ACTIVE_HIGH>; + enable-active-high; }; gpio-keys { diff --git a/arch/arm/boot/dts/exynos4412-n710x.dts b/arch/arm/boot/dts/exynos4412-n710x.dts index eb402a0d6651..fe2bfd76cc4e 100644 --- a/arch/arm/boot/dts/exynos4412-n710x.dts +++ b/arch/arm/boot/dts/exynos4412-n710x.dts @@ -13,15 +13,13 @@ /* bootargs are passed in by bootloader */ - regulators { - cam_vdda_reg: voltage-regulator-9 { - compatible = "regulator-fixed"; - regulator-name = "CAM_SENSOR_CORE_1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - gpio = <&gpm4 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + cam_vdda_reg: voltage-regulator-6 { + compatible = "regulator-fixed"; + regulator-name = "CAM_SENSOR_CORE_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + gpio = <&gpm4 1 GPIO_ACTIVE_HIGH>; + enable-active-high; }; }; diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts index 1514f0dbaff8..346f71932457 100644 --- a/arch/arm/boot/dts/exynos4412-origen.dts +++ b/arch/arm/boot/dts/exynos4412-origen.dts @@ -90,7 +90,7 @@ samsung,vbus-gpio = <&gpx3 5 1>; status = "okay"; - port@1{ + port@1 { status = "okay"; }; port@2 { diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi index 2ae1ab602f4b..7b43c10c510b 100644 --- a/arch/arm/boot/dts/exynos4412.dtsi +++ b/arch/arm/boot/dts/exynos4412.dtsi @@ -298,7 +298,7 @@ status = "disabled"; }; - sysmmu_g2d: sysmmu@10A40000{ + sysmmu_g2d: sysmmu@10a40000 { compatible = "samsung,exynos-sysmmu"; reg = <0x10A40000 0x1000>; interrupt-parent = <&combiner>; diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi index f8d7de1144f1..5d2f0a06fbef 100644 --- a/arch/arm/boot/dts/exynos5.dtsi +++ b/arch/arm/boot/dts/exynos5.dtsi @@ -12,7 +12,6 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> -#include "exynos-syscon-restart.dtsi" / { interrupt-parent = <&gic>; @@ -197,8 +196,6 @@ reg = <0x145B0000 0x1000>; interrupts = <10 3>; interrupt-parent = <&combiner>; - #address-cells = <1>; - #size-cells = <0>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 45283a6c5eee..2daf505b3d08 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -132,10 +132,6 @@ reg = <0x100440A0 0x20>; #power-domain-cells = <0>; label = "DISP1"; - clocks = <&clock CLK_FIN_PLL>, - <&clock CLK_MOUT_ACLK200_DISP1_SUB>, - <&clock CLK_MOUT_ACLK300_DISP1_SUB>; - clock-names = "oscclk", "clk0", "clk1"; }; pd_mau: power-domain@100440c0 { @@ -882,7 +878,7 @@ #iommu-cells = <0>; }; - sysmmu_fimc_dis1: sysmmu@132E0000{ + sysmmu_fimc_dis1: sysmmu@132e0000 { compatible = "samsung,exynos-sysmmu"; reg = <0x132E0000 0x1000>; interrupt-parent = <&combiner>; @@ -1117,3 +1113,4 @@ }; #include "exynos5250-pinctrl.dtsi" +#include "exynos-syscon-restart.dtsi" diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi index 55509c690328..20e789ea136f 100644 --- a/arch/arm/boot/dts/exynos5410.dtsi +++ b/arch/arm/boot/dts/exynos5410.dtsi @@ -439,3 +439,4 @@ }; #include "exynos5410-pinctrl.dtsi" +#include "exynos-syscon-restart.dtsi" diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts index 244f0091c21f..57c2332bf282 100644 --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts @@ -29,7 +29,7 @@ aliases { /* Assign 20 so we don't get confused w/ builtin ones */ - i2c20 = "/spi@12d40000/cros-ec@0/i2c-tunnel"; + i2c20 = &i2c_tunnel; }; backlight: backlight { @@ -970,7 +970,7 @@ samsung,spi-feedback-delay = <1>; }; - i2c-tunnel { + i2c_tunnel: i2c-tunnel { compatible = "google,cros-ec-i2c-tunnel"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 2f3cb2a97f71..f4e8c5823bc2 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -276,10 +276,6 @@ reg = <0x10044000 0x20>; #power-domain-cells = <0>; label = "GSC"; - clocks = <&clock CLK_FIN_PLL>, - <&clock CLK_MOUT_USER_ACLK300_GSCL>, - <&clock CLK_GSCL0>, <&clock CLK_GSCL1>; - clock-names = "oscclk", "clk0", "asb0", "asb1"; }; isp_pd: power-domain@10044020 { @@ -292,10 +288,6 @@ mfc_pd: power-domain@10044060 { compatible = "samsung,exynos4210-pd"; reg = <0x10044060 0x20>; - clocks = <&clock CLK_FIN_PLL>, - <&clock CLK_MOUT_USER_ACLK333>, - <&clock CLK_ACLK333>; - clock-names = "oscclk", "clk0","asb0"; #power-domain-cells = <0>; label = "MFC"; }; @@ -312,12 +304,6 @@ reg = <0x100440C0 0x20>; #power-domain-cells = <0>; label = "DISP"; - clocks = <&clock CLK_FIN_PLL>, - <&clock CLK_MOUT_USER_ACLK200_DISP1>, - <&clock CLK_MOUT_USER_ACLK300_DISP1>, - <&clock CLK_MOUT_USER_ACLK400_DISP1>, - <&clock CLK_FIMD1>, <&clock CLK_MIXER>; - clock-names = "oscclk", "clk0", "clk1", "clk2", "asb0", "asb1"; }; mau_pd: power-domain@100440e0 { @@ -687,6 +673,36 @@ iommus = <&sysmmu_gscl1>; }; + scaler_0: scaler@12800000 { + compatible = "samsung,exynos5420-scaler"; + reg = <0x12800000 0x1294>; + interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clock CLK_MSCL0>; + clock-names = "mscl"; + power-domains = <&msc_pd>; + iommus = <&sysmmu_scaler0r>, <&sysmmu_scaler0w>; + }; + + scaler_1: scaler@12810000 { + compatible = "samsung,exynos5420-scaler"; + reg = <0x12810000 0x1294>; + interrupts = <0 221 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clock CLK_MSCL1>; + clock-names = "mscl"; + power-domains = <&msc_pd>; + iommus = <&sysmmu_scaler1r>, <&sysmmu_scaler1w>; + }; + + scaler_2: scaler@12820000 { + compatible = "samsung,exynos5420-scaler"; + reg = <0x12820000 0x1294>; + interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clock CLK_MSCL2>; + clock-names = "mscl"; + power-domains = <&msc_pd>; + iommus = <&sysmmu_scaler2r>, <&sysmmu_scaler2w>; + }; + jpeg_0: jpeg@11f50000 { compatible = "samsung,exynos5420-jpeg"; reg = <0x11F50000 0x1000>; @@ -761,7 +777,7 @@ #include "exynos5420-tmu-sensor-conf.dtsi" }; - sysmmu_g2dr: sysmmu@0x10A60000 { + sysmmu_g2dr: sysmmu@10a60000 { compatible = "samsung,exynos-sysmmu"; reg = <0x10A60000 0x1000>; interrupt-parent = <&combiner>; @@ -771,7 +787,7 @@ #iommu-cells = <0>; }; - sysmmu_g2dw: sysmmu@0x10A70000 { + sysmmu_g2dw: sysmmu@10a70000 { compatible = "samsung,exynos-sysmmu"; reg = <0x10A70000 0x1000>; interrupt-parent = <&combiner>; @@ -781,7 +797,7 @@ #iommu-cells = <0>; }; - sysmmu_tv: sysmmu@0x14650000 { + sysmmu_tv: sysmmu@14650000 { compatible = "samsung,exynos-sysmmu"; reg = <0x14650000 0x1000>; interrupt-parent = <&combiner>; @@ -792,7 +808,7 @@ #iommu-cells = <0>; }; - sysmmu_gscl0: sysmmu@0x13E80000 { + sysmmu_gscl0: sysmmu@13e80000 { compatible = "samsung,exynos-sysmmu"; reg = <0x13E80000 0x1000>; interrupt-parent = <&combiner>; @@ -803,7 +819,7 @@ #iommu-cells = <0>; }; - sysmmu_gscl1: sysmmu@0x13E90000 { + sysmmu_gscl1: sysmmu@13e90000 { compatible = "samsung,exynos-sysmmu"; reg = <0x13E90000 0x1000>; interrupt-parent = <&combiner>; @@ -814,65 +830,71 @@ #iommu-cells = <0>; }; - sysmmu_scaler0r: sysmmu@0x12880000 { + sysmmu_scaler0r: sysmmu@12880000 { compatible = "samsung,exynos-sysmmu"; reg = <0x12880000 0x1000>; interrupt-parent = <&combiner>; interrupts = <22 4>; clock-names = "sysmmu", "master"; clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>; + power-domains = <&msc_pd>; #iommu-cells = <0>; }; - sysmmu_scaler1r: sysmmu@0x12890000 { + sysmmu_scaler1r: sysmmu@12890000 { compatible = "samsung,exynos-sysmmu"; reg = <0x12890000 0x1000>; interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; clock-names = "sysmmu", "master"; clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>; + power-domains = <&msc_pd>; #iommu-cells = <0>; }; - sysmmu_scaler2r: sysmmu@0x128A0000 { + sysmmu_scaler2r: sysmmu@128a0000 { compatible = "samsung,exynos-sysmmu"; reg = <0x128A0000 0x1000>; interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; clock-names = "sysmmu", "master"; clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>; + power-domains = <&msc_pd>; #iommu-cells = <0>; }; - sysmmu_scaler0w: sysmmu@0x128C0000 { + sysmmu_scaler0w: sysmmu@128c0000 { compatible = "samsung,exynos-sysmmu"; reg = <0x128C0000 0x1000>; interrupt-parent = <&combiner>; interrupts = <27 2>; clock-names = "sysmmu", "master"; clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>; + power-domains = <&msc_pd>; #iommu-cells = <0>; }; - sysmmu_scaler1w: sysmmu@0x128D0000 { + sysmmu_scaler1w: sysmmu@128d0000 { compatible = "samsung,exynos-sysmmu"; reg = <0x128D0000 0x1000>; interrupt-parent = <&combiner>; interrupts = <22 6>; clock-names = "sysmmu", "master"; clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>; + power-domains = <&msc_pd>; #iommu-cells = <0>; }; - sysmmu_scaler2w: sysmmu@0x128E0000 { + sysmmu_scaler2w: sysmmu@128e0000 { compatible = "samsung,exynos-sysmmu"; reg = <0x128E0000 0x1000>; interrupt-parent = <&combiner>; interrupts = <19 6>; clock-names = "sysmmu", "master"; clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>; + power-domains = <&msc_pd>; #iommu-cells = <0>; }; - sysmmu_rotator: sysmmu@0x11D40000 { + sysmmu_rotator: sysmmu@11d40000 { compatible = "samsung,exynos-sysmmu"; reg = <0x11D40000 0x1000>; interrupt-parent = <&combiner>; @@ -882,7 +904,7 @@ #iommu-cells = <0>; }; - sysmmu_jpeg0: sysmmu@0x11F10000 { + sysmmu_jpeg0: sysmmu@11f10000 { compatible = "samsung,exynos-sysmmu"; reg = <0x11F10000 0x1000>; interrupt-parent = <&combiner>; @@ -892,7 +914,7 @@ #iommu-cells = <0>; }; - sysmmu_jpeg1: sysmmu@0x11F20000 { + sysmmu_jpeg1: sysmmu@11f20000 { compatible = "samsung,exynos-sysmmu"; reg = <0x11F20000 0x1000>; interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; @@ -901,7 +923,7 @@ #iommu-cells = <0>; }; - sysmmu_mfc_l: sysmmu@0x11200000 { + sysmmu_mfc_l: sysmmu@11200000 { compatible = "samsung,exynos-sysmmu"; reg = <0x11200000 0x1000>; interrupt-parent = <&combiner>; @@ -912,7 +934,7 @@ #iommu-cells = <0>; }; - sysmmu_mfc_r: sysmmu@0x11210000 { + sysmmu_mfc_r: sysmmu@11210000 { compatible = "samsung,exynos-sysmmu"; reg = <0x11210000 0x1000>; interrupt-parent = <&combiner>; @@ -923,7 +945,7 @@ #iommu-cells = <0>; }; - sysmmu_fimd1_0: sysmmu@0x14640000 { + sysmmu_fimd1_0: sysmmu@14640000 { compatible = "samsung,exynos-sysmmu"; reg = <0x14640000 0x1000>; interrupt-parent = <&combiner>; @@ -934,7 +956,7 @@ #iommu-cells = <0>; }; - sysmmu_fimd1_1: sysmmu@0x14680000 { + sysmmu_fimd1_1: sysmmu@14680000 { compatible = "samsung,exynos-sysmmu"; reg = <0x14680000 0x1000>; interrupt-parent = <&combiner>; @@ -1531,3 +1553,4 @@ }; #include "exynos5420-pinctrl.dtsi" +#include "exynos-syscon-restart.dtsi" diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi index d31249f25ccf..2f4f40882dab 100644 --- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi @@ -23,7 +23,7 @@ stdout-path = "serial2:115200n8"; }; - firmware@02073000 { + firmware@2073000 { compatible = "samsung,secure-firmware"; reg = <0x02073000 0x1000>; }; diff --git a/arch/arm/boot/dts/exynos5440-sd5v1.dts b/arch/arm/boot/dts/exynos5440-sd5v1.dts deleted file mode 100644 index c4b8392d1ae1..000000000000 --- a/arch/arm/boot/dts/exynos5440-sd5v1.dts +++ /dev/null @@ -1,42 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * SAMSUNG SD5v1 board device tree source - * - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * http://www.samsung.com - */ - -/dts-v1/; -#include "exynos5440.dtsi" - -/ { - model = "SAMSUNG SD5v1 board based on EXYNOS5440"; - compatible = "samsung,sd5v1", "samsung,exynos5440", "samsung,exynos5"; - - chosen { - bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel earlyprintk no_console_suspend mem=2048M@0x80000000 mem=6144M@0x100000000 console=ttySAC0,115200"; - }; - - /* FIXME: set reg property with correct start address and size */ - memory@0 { - device_type = "memory"; - reg = <0 0>; - }; - - fixed-rate-clocks { - xtal { - compatible = "samsung,clock-xtal"; - clock-frequency = <50000000>; - }; - }; - - spi { - status = "disabled"; - }; - -}; - -&gmac { - fixed_phy; - phy_addr = <1>; -}; diff --git a/arch/arm/boot/dts/exynos5440-ssdk5440.dts b/arch/arm/boot/dts/exynos5440-ssdk5440.dts deleted file mode 100644 index a33c4fc29ae5..000000000000 --- a/arch/arm/boot/dts/exynos5440-ssdk5440.dts +++ /dev/null @@ -1,81 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * SAMSUNG SSDK5440 board device tree source - * - * Copyright (c) 2012 Samsung Electronics Co., Ltd. - * http://www.samsung.com - */ - -/dts-v1/; -#include "exynos5440.dtsi" -#include <dt-bindings/gpio/gpio.h> - -/ { - model = "SAMSUNG SSDK5440 board based on EXYNOS5440"; - compatible = "samsung,ssdk5440", "samsung,exynos5440", "samsung,exynos5"; - - chosen { - bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel earlyprintk no_console_suspend mem=2048M@0x80000000 mem=6144M@0x100000000 console=ttySAC0,115200"; - }; - - /* FIXME: set reg property with correct start address and size */ - memory@0 { - device_type = "memory"; - reg = <0 0>; - }; - - fixed-rate-clocks { - xtal { - compatible = "samsung,clock-xtal"; - clock-frequency = <50000000>; - }; - }; -}; - -&pcie_0 { - reset-gpio = <&pin_ctrl 5 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&pcie_1 { - reset-gpio = <&pin_ctrl 22 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&spi_0 { - flash: w25q128@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "winbond,w25q128"; - spi-max-frequency = <15625000>; - reg = <0>; - controller-data { - samsung,spi-feedback-delay = <0>; - }; - - partition@0 { - label = "BootLoader"; - reg = <0x60000 0x80000>; - read-only; - }; - - partition@e0000 { - label = "Recovery-Kernel"; - reg = <0xe0000 0x300000>; - read-only; - }; - - partition@3e0000 { - label = "CRAM-FS"; - reg = <0x3e0000 0x700000>; - read-only; - }; - - partition@ae0000 { - label = "User-Data"; - reg = <0xae0000 0x520000>; - }; - - }; - -}; diff --git a/arch/arm/boot/dts/exynos5440-tmu-sensor-conf.dtsi b/arch/arm/boot/dts/exynos5440-tmu-sensor-conf.dtsi deleted file mode 100644 index 0421c3d42905..000000000000 --- a/arch/arm/boot/dts/exynos5440-tmu-sensor-conf.dtsi +++ /dev/null @@ -1,20 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device tree sources for Exynos5440 TMU sensor configuration - * - * Copyright (c) 2014 Lukasz Majewski <l.majewski@samsung.com> - */ - -#include <dt-bindings/thermal/thermal_exynos.h> - -#thermal-sensor-cells = <0>; -samsung,tmu_gain = <5>; -samsung,tmu_reference_voltage = <16>; -samsung,tmu_noise_cancel_mode = <4>; -samsung,tmu_efuse_value = <0x5d2d>; -samsung,tmu_min_efuse_value = <16>; -samsung,tmu_max_efuse_value = <76>; -samsung,tmu_first_point_trim = <25>; -samsung,tmu_second_point_trim = <70>; -samsung,tmu_default_temp_offset = <25>; -samsung,tmu_cal_type = <TYPE_ONE_POINT_TRIMMING>; diff --git a/arch/arm/boot/dts/exynos5440-trip-points.dtsi b/arch/arm/boot/dts/exynos5440-trip-points.dtsi deleted file mode 100644 index a2b04fed7d0b..000000000000 --- a/arch/arm/boot/dts/exynos5440-trip-points.dtsi +++ /dev/null @@ -1,21 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device tree sources for default Exynos5440 thermal zone definition - * - * Copyright (c) 2014 Lukasz Majewski <l.majewski@samsung.com> - */ - -polling-delay-passive = <0>; -polling-delay = <0>; -trips { - cpu-alert-0 { - temperature = <100000>; /* millicelsius */ - hysteresis = <0>; /* millicelsius */ - type = "active"; - }; - cpu-crit-0 { - temperature = <105000>; /* millicelsius */ - hysteresis = <0>; /* millicelsius */ - type = "critical"; - }; -}; diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi deleted file mode 100644 index f3abecc44657..000000000000 --- a/arch/arm/boot/dts/exynos5440.dtsi +++ /dev/null @@ -1,355 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * SAMSUNG EXYNOS5440 SoC device tree source - * - * Copyright (c) 2012 Samsung Electronics Co., Ltd. - * http://www.samsung.com - */ - -#include <dt-bindings/clock/exynos5440.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/interrupt-controller/irq.h> - -/ { - compatible = "samsung,exynos5440", "samsung,exynos5"; - - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - aliases { - serial0 = &serial_0; - serial1 = &serial_1; - spi0 = &spi_0; - tmuctrl0 = &tmuctrl_0; - tmuctrl1 = &tmuctrl_1; - tmuctrl2 = &tmuctrl_2; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0>; - }; - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <1>; - }; - cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <2>; - }; - cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <3>; - }; - }; - - soc: soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - clock: clock-controller@160000 { - compatible = "samsung,exynos5440-clock"; - reg = <0x160000 0x1000>; - #clock-cells = <1>; - }; - - gic: interrupt-controller@2e0000 { - compatible = "arm,cortex-a15-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x2E1000 0x1000>, - <0x2E2000 0x2000>, - <0x2E4000 0x2000>, - <0x2E6000 0x2000>; - interrupts = <GIC_PPI 9 - (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; - }; - - - arm-pmu { - compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu"; - interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; - }; - - timer { - compatible = "arm,cortex-a15-timer", - "arm,armv7-timer"; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; - clock-frequency = <50000000>; - }; - - cpufreq@160000 { - compatible = "samsung,exynos5440-cpufreq"; - reg = <0x160000 0x1000>; - interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; - operating-points = < - /* KHz uV */ - 1500000 1100000 - 1400000 1075000 - 1300000 1050000 - 1200000 1025000 - 1100000 1000000 - 1000000 975000 - 900000 950000 - 800000 925000 - >; - }; - - serial_0: serial@b0000 { - compatible = "samsung,exynos4210-uart"; - reg = <0xB0000 0x1000>; - interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clock CLK_B_125>, <&clock CLK_B_125>; - clock-names = "uart", "clk_uart_baud0"; - }; - - serial_1: serial@c0000 { - compatible = "samsung,exynos4210-uart"; - reg = <0xC0000 0x1000>; - interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clock CLK_B_125>, <&clock CLK_B_125>; - clock-names = "uart", "clk_uart_baud0"; - }; - - spi_0: spi@d0000 { - compatible = "samsung,exynos5440-spi"; - reg = <0xD0000 0x100>; - interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - samsung,spi-src-clk = <0>; - num-cs = <1>; - clocks = <&clock CLK_B_125>, <&clock CLK_SPI_BAUD>; - clock-names = "spi", "spi_busclk0"; - }; - - pin_ctrl: pinctrl@e0000 { - compatible = "samsung,exynos5440-pinctrl"; - reg = <0xE0000 0x1000>; - interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <2>; - #gpio-cells = <2>; - - fan: fan { - samsung,exynos5440-pin-function = <1>; - }; - - hdd_led0: hdd_led0 { - samsung,exynos5440-pin-function = <2>; - }; - - hdd_led1: hdd_led1 { - samsung,exynos5440-pin-function = <3>; - }; - - uart1: uart1 { - samsung,exynos5440-pin-function = <4>; - }; - }; - - i2c@f0000 { - compatible = "samsung,exynos5440-i2c"; - reg = <0xF0000 0x1000>; - interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_B_125>; - clock-names = "i2c"; - }; - - i2c@100000 { - compatible = "samsung,exynos5440-i2c"; - reg = <0x100000 0x1000>; - interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&clock CLK_B_125>; - clock-names = "i2c"; - }; - - watchdog@110000 { - compatible = "samsung,s3c6410-wdt"; - reg = <0x110000 0x1000>; - interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clock CLK_B_125>; - clock-names = "watchdog"; - }; - - gmac: ethernet@230000 { - compatible = "snps,dwmac-3.70a", "snps,dwmac"; - reg = <0x00230000 0x8000>; - interrupt-parent = <&gic>; - interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq"; - phy-mode = "sgmii"; - clocks = <&clock CLK_GMAC0>; - clock-names = "stmmaceth"; - }; - - amba { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&gic>; - ranges; - }; - - rtc@130000 { - compatible = "samsung,s3c6410-rtc"; - reg = <0x130000 0x1000>; - interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clock CLK_B_125>; - clock-names = "rtc"; - }; - - tmuctrl_0: tmuctrl@160118 { - compatible = "samsung,exynos5440-tmu"; - reg = <0x160118 0x230>, <0x160368 0x10>; - interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clock CLK_B_125>; - clock-names = "tmu_apbif"; - #include "exynos5440-tmu-sensor-conf.dtsi" - }; - - tmuctrl_1: tmuctrl@16011c { - compatible = "samsung,exynos5440-tmu"; - reg = <0x16011C 0x230>, <0x160368 0x10>; - interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clock CLK_B_125>; - clock-names = "tmu_apbif"; - #include "exynos5440-tmu-sensor-conf.dtsi" - }; - - tmuctrl_2: tmuctrl@160120 { - compatible = "samsung,exynos5440-tmu"; - reg = <0x160120 0x230>, <0x160368 0x10>; - interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clock CLK_B_125>; - clock-names = "tmu_apbif"; - #include "exynos5440-tmu-sensor-conf.dtsi" - }; - - sata@210000 { - compatible = "snps,exynos5440-ahci"; - reg = <0x210000 0x10000>; - interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clock CLK_SATA>; - clock-names = "sata"; - }; - - ohci@220000 { - compatible = "samsung,exynos5440-ohci"; - reg = <0x220000 0x1000>; - interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clock CLK_USB>; - clock-names = "usbhost"; - }; - - ehci@221000 { - compatible = "samsung,exynos5440-ehci"; - reg = <0x221000 0x1000>; - interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clock CLK_USB>; - clock-names = "usbhost"; - }; - - pcie_phy0: pcie-phy@270000 { - #phy-cells = <0>; - compatible = "samsung,exynos5440-pcie-phy"; - reg = <0x270000 0x1000>, <0x271000 0x40>; - }; - - pcie_phy1: pcie-phy@272000 { - #phy-cells = <0>; - compatible = "samsung,exynos5440-pcie-phy"; - reg = <0x272000 0x1000>, <0x271040 0x40>; - }; - - pcie_0: pcie@290000 { - compatible = "samsung,exynos5440-pcie", "snps,dw-pcie"; - reg = <0x290000 0x1000>, <0x40000000 0x1000>; - reg-names = "elbi", "config"; - interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clock CLK_PR0_250_O>, <&clock CLK_PB0_250_O>; - clock-names = "pcie", "pcie_bus"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - phys = <&pcie_phy0>; - ranges = <0x81000000 0 0 0x40001000 0 0x00010000 /* downstream I/O */ - 0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */ - bus-range = <0x00 0xff>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0x0 0 &gic 53>; - num-lanes = <4>; - status = "disabled"; - }; - - pcie_1: pcie@2a0000 { - compatible = "samsung,exynos5440-pcie", "snps,dw-pcie"; - reg = <0x2a0000 0x1000>, <0x60000000 0x1000>; - reg-names = "elbi", "config"; - interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clock CLK_PR1_250_O>, <&clock CLK_PB0_250_O>; - clock-names = "pcie", "pcie_bus"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - phys = <&pcie_phy1>; - ranges = <0x81000000 0 0 0x60001000 0 0x00010000 /* downstream I/O */ - 0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */ - bus-range = <0x00 0xff>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0x0 0 &gic 56>; - num-lanes = <4>; - status = "disabled"; - }; - }; - - thermal-zones { - cpu0_thermal: cpu0-thermal { - thermal-sensors = <&tmuctrl_0>; - #include "exynos5440-trip-points.dtsi" - }; - cpu1_thermal: cpu1-thermal { - thermal-sensors = <&tmuctrl_1>; - #include "exynos5440-trip-points.dtsi" - }; - cpu2_thermal: cpu2-thermal { - thermal-sensors = <&tmuctrl_2>; - #include "exynos5440-trip-points.dtsi" - }; - }; -}; diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts index 2f8df9244f72..d80ab9085da1 100644 --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts @@ -27,7 +27,7 @@ aliases { /* Assign 20 so we don't get confused w/ builtin ones */ - i2c20 = "/spi@12d40000/cros-ec@0/i2c-tunnel"; + i2c20 = &i2c_tunnel; }; backlight: backlight { @@ -939,7 +939,7 @@ samsung,spi-feedback-delay = <1>; }; - i2c-tunnel { + i2c_tunnel: i2c-tunnel { compatible = "google,cros-ec-i2c-tunnel"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/s3c2416-smdk2416.dts b/arch/arm/boot/dts/s3c2416-smdk2416.dts index a1c9d8c695cc..5164386aff3a 100644 --- a/arch/arm/boot/dts/s3c2416-smdk2416.dts +++ b/arch/arm/boot/dts/s3c2416-smdk2416.dts @@ -12,14 +12,13 @@ model = "SMDK2416"; compatible = "samsung,s3c2416"; - memory { + memory@30000000 { + device_type = "memory"; reg = <0x30000000 0x4000000>; }; clocks { compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; xti: xti { compatible = "fixed-clock"; diff --git a/arch/arm/boot/dts/s3c2416.dtsi b/arch/arm/boot/dts/s3c2416.dtsi index 3c7385cab248..6adf64ea3ff2 100644 --- a/arch/arm/boot/dts/s3c2416.dtsi +++ b/arch/arm/boot/dts/s3c2416.dtsi @@ -18,9 +18,6 @@ }; cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu { compatible = "arm,arm926ej-s"; }; @@ -30,7 +27,7 @@ compatible = "samsung,s3c2416-irq"; }; - clocks: clock-controller@0x4c000000 { + clocks: clock-controller@4c000000 { compatible = "samsung,s3c2416-clock"; reg = <0x4c000000 0x40>; #clock-cells = <1>; @@ -69,7 +66,7 @@ <&clocks SCLK_UART>; }; - uart_3: serial@5000C000 { + uart_3: serial@5000c000 { compatible = "samsung,s3c2440-uart"; reg = <0x5000C000 0x4000>; interrupts = <1 18 24 4>, <1 18 25 4>; @@ -80,7 +77,7 @@ status = "disabled"; }; - sdhci_1: sdhci@4AC00000 { + sdhci_1: sdhci@4ac00000 { compatible = "samsung,s3c6410-sdhci"; reg = <0x4AC00000 0x100>; interrupts = <0 0 21 3>; @@ -91,7 +88,7 @@ status = "disabled"; }; - sdhci_0: sdhci@4A800000 { + sdhci_0: sdhci@4a800000 { compatible = "samsung,s3c6410-sdhci"; reg = <0x4A800000 0x100>; interrupts = <0 0 20 3>; diff --git a/arch/arm/boot/dts/s3c24xx.dtsi b/arch/arm/boot/dts/s3c24xx.dtsi index 34c7fe6751cf..6d8dd3cdd3c0 100644 --- a/arch/arm/boot/dts/s3c24xx.dtsi +++ b/arch/arm/boot/dts/s3c24xx.dtsi @@ -5,11 +5,11 @@ * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de> */ -#include "skeleton.dtsi" - / { compatible = "samsung,s3c24xx"; interrupt-parent = <&intc>; + #address-cells = <1>; + #size-cells = <1>; aliases { pinctrl0 = &pinctrl_0; diff --git a/arch/arm/boot/dts/s3c6410-mini6410.dts b/arch/arm/boot/dts/s3c6410-mini6410.dts index f68601bd9c91..0e159c884f97 100644 --- a/arch/arm/boot/dts/s3c6410-mini6410.dts +++ b/arch/arm/boot/dts/s3c6410-mini6410.dts @@ -19,7 +19,8 @@ model = "FriendlyARM Mini6410 board based on S3C6410"; compatible = "friendlyarm,mini6410", "samsung,s3c6410"; - memory { + memory@50000000 { + device_type = "memory"; reg = <0x50000000 0x10000000>; }; diff --git a/arch/arm/boot/dts/s3c6410-smdk6410.dts b/arch/arm/boot/dts/s3c6410-smdk6410.dts index b6b5afcd7602..a9a5689dc462 100644 --- a/arch/arm/boot/dts/s3c6410-smdk6410.dts +++ b/arch/arm/boot/dts/s3c6410-smdk6410.dts @@ -19,7 +19,8 @@ model = "SAMSUNG SMDK6410 board based on S3C6410"; compatible = "samsung,mini6410", "samsung,s3c6410"; - memory { + memory@50000000 { + device_type = "memory"; reg = <0x50000000 0x8000000>; }; diff --git a/arch/arm/boot/dts/s3c64xx.dtsi b/arch/arm/boot/dts/s3c64xx.dtsi index e2be3fbdd3f3..2e611df37911 100644 --- a/arch/arm/boot/dts/s3c64xx.dtsi +++ b/arch/arm/boot/dts/s3c64xx.dtsi @@ -13,10 +13,12 @@ * nodes can be added to this file. */ -#include "skeleton.dtsi" #include <dt-bindings/clock/samsung,s3c64xx-clock.h> / { + #address-cells = <1>; + #size-cells = <1>; + aliases { i2c0 = &i2c0; pinctrl0 = &pinctrl0; |