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-rw-r--r--Documentation/devicetree/bindings/ddr/lpddr2-timings.txt (renamed from Documentation/devicetree/bindings/lpddr2/lpddr2-timings.txt)0
-rw-r--r--Documentation/devicetree/bindings/ddr/lpddr2.txt (renamed from Documentation/devicetree/bindings/lpddr2/lpddr2.txt)2
-rw-r--r--Documentation/devicetree/bindings/ddr/lpddr3-timings.txt58
-rw-r--r--Documentation/devicetree/bindings/ddr/lpddr3.txt101
-rw-r--r--Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt84
-rw-r--r--arch/arm/boot/dts/exynos5420.dtsi76
-rw-r--r--arch/arm/boot/dts/exynos5422-odroid-core.dtsi117
-rw-r--r--arch/arm/boot/dts/exynos5800.dtsi2
8 files changed, 437 insertions, 3 deletions
diff --git a/Documentation/devicetree/bindings/lpddr2/lpddr2-timings.txt b/Documentation/devicetree/bindings/ddr/lpddr2-timings.txt
index 9ceb19e0c7fd..9ceb19e0c7fd 100644
--- a/Documentation/devicetree/bindings/lpddr2/lpddr2-timings.txt
+++ b/Documentation/devicetree/bindings/ddr/lpddr2-timings.txt
diff --git a/Documentation/devicetree/bindings/lpddr2/lpddr2.txt b/Documentation/devicetree/bindings/ddr/lpddr2.txt
index 58354a075e13..ddd40121e6f6 100644
--- a/Documentation/devicetree/bindings/lpddr2/lpddr2.txt
+++ b/Documentation/devicetree/bindings/ddr/lpddr2.txt
@@ -36,7 +36,7 @@ Child nodes:
"lpddr2-timings" provides AC timing parameters of the device for
a given speed-bin. The user may provide the timings for as many
speed-bins as is required. Please see Documentation/devicetree/
- bindings/lpddr2/lpddr2-timings.txt for more information on "lpddr2-timings"
+ bindings/ddr/lpddr2-timings.txt for more information on "lpddr2-timings"
Example:
diff --git a/Documentation/devicetree/bindings/ddr/lpddr3-timings.txt b/Documentation/devicetree/bindings/ddr/lpddr3-timings.txt
new file mode 100644
index 000000000000..84705e50a3fd
--- /dev/null
+++ b/Documentation/devicetree/bindings/ddr/lpddr3-timings.txt
@@ -0,0 +1,58 @@
+* AC timing parameters of LPDDR3 memories for a given speed-bin.
+
+The structures are based on LPDDR2 and extended where needed.
+
+Required properties:
+- compatible : Should be "jedec,lpddr3-timings"
+- min-freq : minimum DDR clock frequency for the speed-bin. Type is <u32>
+- reg : maximum DDR clock frequency for the speed-bin. Type is <u32>
+
+Optional properties:
+
+The following properties represent AC timing parameters from the memory
+data-sheet of the device for a given speed-bin. All these properties are
+of type <u32> and the default unit is ps (pico seconds).
+- tRFC
+- tRRD
+- tRPab
+- tRPpb
+- tRCD
+- tRC
+- tRAS
+- tWTR
+- tWR
+- tRTP
+- tW2W-C2C
+- tR2R-C2C
+- tFAW
+- tXSR
+- tXP
+- tCKE
+- tCKESR
+- tMRD
+
+Example:
+
+timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 {
+ compatible = "jedec,lpddr3-timings";
+ reg = <800000000>; /* workaround: it shows max-freq */
+ min-freq = <100000000>;
+ tRFC = <65000>;
+ tRRD = <6000>;
+ tRPab = <12000>;
+ tRPpb = <12000>;
+ tRCD = <10000>;
+ tRC = <33750>;
+ tRAS = <23000>;
+ tWTR = <3750>;
+ tWR = <7500>;
+ tRTP = <3750>;
+ tW2W-C2C = <0>;
+ tR2R-C2C = <0>;
+ tFAW = <25000>;
+ tXSR = <70000>;
+ tXP = <3750>;
+ tCKE = <3750>;
+ tCKESR = <3750>;
+ tMRD = <7000>;
+};
diff --git a/Documentation/devicetree/bindings/ddr/lpddr3.txt b/Documentation/devicetree/bindings/ddr/lpddr3.txt
new file mode 100644
index 000000000000..a0eda35a86ee
--- /dev/null
+++ b/Documentation/devicetree/bindings/ddr/lpddr3.txt
@@ -0,0 +1,101 @@
+* LPDDR3 SDRAM memories compliant to JEDEC JESD209-3C
+
+Required properties:
+- compatible : Should be "<vendor>,<type>", and generic value "jedec,lpddr3".
+ Example "<vendor>,<type>" values:
+ "samsung,K3QF2F20DB"
+
+- density : <u32> representing density in Mb (Mega bits)
+- io-width : <u32> representing bus width. Possible values are 8, 16, 32, 64
+- #address-cells: Must be set to 1
+- #size-cells: Must be set to 0
+
+Optional properties:
+
+The following optional properties represent the minimum value of some AC
+timing parameters of the DDR device in terms of number of clock cycles.
+These values shall be obtained from the device data-sheet.
+- tRFC-min-tck
+- tRRD-min-tck
+- tRPab-min-tck
+- tRPpb-min-tck
+- tRCD-min-tck
+- tRC-min-tck
+- tRAS-min-tck
+- tWTR-min-tck
+- tWR-min-tck
+- tRTP-min-tck
+- tW2W-C2C-min-tck
+- tR2R-C2C-min-tck
+- tWL-min-tck
+- tDQSCK-min-tck
+- tRL-min-tck
+- tFAW-min-tck
+- tXSR-min-tck
+- tXP-min-tck
+- tCKE-min-tck
+- tCKESR-min-tck
+- tMRD-min-tck
+
+Child nodes:
+- The lpddr3 node may have one or more child nodes of type "lpddr3-timings".
+ "lpddr3-timings" provides AC timing parameters of the device for
+ a given speed-bin. Please see Documentation/devicetree/
+ bindings/ddr/lpddr3-timings.txt for more information on "lpddr3-timings"
+
+Example:
+
+samsung_K3QF2F20DB: lpddr3 {
+ compatible = "samsung,K3QF2F20DB", "jedec,lpddr3";
+ density = <16384>;
+ io-width = <32>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tRFC-min-tck = <17>;
+ tRRD-min-tck = <2>;
+ tRPab-min-tck = <2>;
+ tRPpb-min-tck = <2>;
+ tRCD-min-tck = <3>;
+ tRC-min-tck = <6>;
+ tRAS-min-tck = <5>;
+ tWTR-min-tck = <2>;
+ tWR-min-tck = <7>;
+ tRTP-min-tck = <2>;
+ tW2W-C2C-min-tck = <0>;
+ tR2R-C2C-min-tck = <0>;
+ tWL-min-tck = <8>;
+ tDQSCK-min-tck = <5>;
+ tRL-min-tck = <14>;
+ tFAW-min-tck = <5>;
+ tXSR-min-tck = <12>;
+ tXP-min-tck = <2>;
+ tCKE-min-tck = <2>;
+ tCKESR-min-tck = <2>;
+ tMRD-min-tck = <5>;
+
+ timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 {
+ compatible = "jedec,lpddr3-timings";
+ /* workaround: 'reg' shows max-freq */
+ reg = <800000000>;
+ min-freq = <100000000>;
+ tRFC = <65000>;
+ tRRD = <6000>;
+ tRPab = <12000>;
+ tRPpb = <12000>;
+ tRCD = <10000>;
+ tRC = <33750>;
+ tRAS = <23000>;
+ tWTR = <3750>;
+ tWR = <7500>;
+ tRTP = <3750>;
+ tW2W-C2C = <0>;
+ tR2R-C2C = <0>;
+ tFAW = <25000>;
+ tXSR = <70000>;
+ tXP = <3750>;
+ tCKE = <3750>;
+ tCKESR = <3750>;
+ tMRD = <7000>;
+ };
+}
diff --git a/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt b/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt
new file mode 100644
index 000000000000..02e4a1f862f1
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt
@@ -0,0 +1,84 @@
+* Exynos5422 frequency and voltage scaling for Dynamic Memory Controller device
+
+The Samsung Exynos5422 SoC has DMC (Dynamic Memory Controller) to which the DRAM
+memory chips are connected. The driver is to monitor the controller in runtime
+and switch frequency and voltage. To monitor the usage of the controller in
+runtime, the driver uses the PPMU (Platform Performance Monitoring Unit), which
+is able to measure the current load of the memory.
+When 'userspace' governor is used for the driver, an application is able to
+switch the DMC and memory frequency.
+
+Required properties for DMC device for Exynos5422:
+- compatible: Should be "samsung,exynos5422-dmc".
+- clocks : list of clock specifiers, must contain an entry for each
+ required entry in clock-names for CLK_FOUT_SPLL, CLK_MOUT_SCLK_SPLL,
+ CLK_FF_DOUT_SPLL2, CLK_FOUT_BPLL, CLK_MOUT_BPLL, CLK_SCLK_BPLL,
+ CLK_MOUT_MX_MSPLL_CCORE, CLK_MOUT_MX_MSPLL_CCORE_PHY, CLK_MOUT_MCLK_CDREX,
+- clock-names : should include "fout_spll", "mout_sclk_spll", "ff_dout_spll2",
+ "fout_bpll", "mout_bpll", "sclk_bpll", "mout_mx_mspll_ccore",
+ "mout_mclk_cdrex" entries
+- devfreq-events : phandles for PPMU devices connected to this DMC.
+- vdd-supply : phandle for voltage regulator which is connected.
+- reg : registers of two CDREX controllers.
+- operating-points-v2 : phandle for OPPs described in v2 definition.
+- device-handle : phandle of the connected DRAM memory device. For more
+ information please refer to documentation file:
+ Documentation/devicetree/bindings/ddr/lpddr3.txt
+- devfreq-events : phandles of the PPMU events used by the controller.
+- samsung,syscon-clk : phandle of the clock register set used by the controller,
+ these registers are used for enabling a 'pause' feature and are not
+ exposed by clock framework but they must be used in a safe way.
+ The register offsets are in the driver code and specyfic for this SoC
+ type.
+
+Optional properties for DMC device for Exynos5422:
+- interrupt-parent : The parent interrupt controller.
+- interrupts : Contains the IRQ line numbers for the DMC internal performance
+ event counters in DREX0 and DREX1 channels. Align with specification of the
+ interrupt line(s) in the interrupt-parent controller.
+- interrupt-names : IRQ names "drex_0" and "drex_1", the order should be the
+ same as in the 'interrupts' list above.
+
+Example:
+
+ ppmu_dmc0_0: ppmu@10d00000 {
+ compatible = "samsung,exynos-ppmu";
+ reg = <0x10d00000 0x2000>;
+ clocks = <&clock CLK_PCLK_PPMU_DREX0_0>;
+ clock-names = "ppmu";
+ events {
+ ppmu_event_dmc0_0: ppmu-event3-dmc0_0 {
+ event-name = "ppmu-event3-dmc0_0";
+ };
+ };
+ };
+
+ dmc: memory-controller@10c20000 {
+ compatible = "samsung,exynos5422-dmc";
+ reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>;
+ clocks = <&clock CLK_FOUT_SPLL>,
+ <&clock CLK_MOUT_SCLK_SPLL>,
+ <&clock CLK_FF_DOUT_SPLL2>,
+ <&clock CLK_FOUT_BPLL>,
+ <&clock CLK_MOUT_BPLL>,
+ <&clock CLK_SCLK_BPLL>,
+ <&clock CLK_MOUT_MX_MSPLL_CCORE>,
+ <&clock CLK_MOUT_MCLK_CDREX>;
+ clock-names = "fout_spll",
+ "mout_sclk_spll",
+ "ff_dout_spll2",
+ "fout_bpll",
+ "mout_bpll",
+ "sclk_bpll",
+ "mout_mx_mspll_ccore",
+ "mout_mclk_cdrex";
+ operating-points-v2 = <&dmc_opp_table>;
+ devfreq-events = <&ppmu_event3_dmc0_0>, <&ppmu_event3_dmc0_1>,
+ <&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>;
+ device-handle = <&samsung_K3QF2F20DB>;
+ vdd-supply = <&buck1_reg>;
+ samsung,syscon-clk = <&clock>;
+ interrupt-parent = <&combiner>;
+ interrupts = <16 0>, <16 1>;
+ interrupt-names = "drex_0", "drex_1";
+ };
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 2c131ad78c09..d39907a41f78 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -175,7 +175,7 @@
};
clock: clock-controller@10010000 {
- compatible = "samsung,exynos5420-clock";
+ compatible = "samsung,exynos5420-clock", "syscon";
reg = <0x10010000 0x30000>;
#clock-cells = <1>;
};
@@ -237,6 +237,32 @@
status = "disabled";
};
+ dmc: memory-controller@10c20000 {
+ compatible = "samsung,exynos5422-dmc";
+ reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>;
+ interrupt-parent = <&combiner>;
+ interrupts = <16 0>, <16 1>;
+ interrupt-names = "drex_0", "drex_1";
+ clocks = <&clock CLK_FOUT_SPLL>,
+ <&clock CLK_MOUT_SCLK_SPLL>,
+ <&clock CLK_FF_DOUT_SPLL2>,
+ <&clock CLK_FOUT_BPLL>,
+ <&clock CLK_MOUT_BPLL>,
+ <&clock CLK_SCLK_BPLL>,
+ <&clock CLK_MOUT_MX_MSPLL_CCORE>,
+ <&clock CLK_MOUT_MCLK_CDREX>;
+ clock-names = "fout_spll",
+ "mout_sclk_spll",
+ "ff_dout_spll2",
+ "fout_bpll",
+ "mout_bpll",
+ "sclk_bpll",
+ "mout_mx_mspll_ccore",
+ "mout_mclk_cdrex";
+ samsung,syscon-clk = <&clock>;
+ status = "disabled";
+ };
+
nocp_mem0_0: nocp@10ca1000 {
compatible = "samsung,exynos5420-nocp";
reg = <0x10CA1000 0x200>;
@@ -273,6 +299,54 @@
status = "disabled";
};
+ ppmu_dmc0_0: ppmu@10d00000 {
+ compatible = "samsung,exynos-ppmu";
+ reg = <0x10d00000 0x2000>;
+ clocks = <&clock CLK_PCLK_PPMU_DREX0_0>;
+ clock-names = "ppmu";
+ events {
+ ppmu_event3_dmc0_0: ppmu-event3-dmc0_0 {
+ event-name = "ppmu-event3-dmc0_0";
+ };
+ };
+ };
+
+ ppmu_dmc0_1: ppmu@10d10000 {
+ compatible = "samsung,exynos-ppmu";
+ reg = <0x10d10000 0x2000>;
+ clocks = <&clock CLK_PCLK_PPMU_DREX0_1>;
+ clock-names = "ppmu";
+ events {
+ ppmu_event3_dmc0_1: ppmu-event3-dmc0_1 {
+ event-name = "ppmu-event3-dmc0_1";
+ };
+ };
+ };
+
+ ppmu_dmc1_0: ppmu@10d60000 {
+ compatible = "samsung,exynos-ppmu";
+ reg = <0x10d60000 0x2000>;
+ clocks = <&clock CLK_PCLK_PPMU_DREX1_0>;
+ clock-names = "ppmu";
+ events {
+ ppmu_event3_dmc1_0: ppmu-event3-dmc1_0 {
+ event-name = "ppmu-event3-dmc1_0";
+ };
+ };
+ };
+
+ ppmu_dmc1_1: ppmu@10d70000 {
+ compatible = "samsung,exynos-ppmu";
+ reg = <0x10d70000 0x2000>;
+ clocks = <&clock CLK_PCLK_PPMU_DREX1_1>;
+ clock-names = "ppmu";
+ events {
+ ppmu_event3_dmc1_1: ppmu-event3-dmc1_1 {
+ event-name = "ppmu-event3-dmc1_1";
+ };
+ };
+ };
+
gsc_pd: power-domain@10044000 {
compatible = "samsung,exynos4210-pd";
reg = <0x10044000 0x20>;
diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
index 829147e320e0..059fa32d1a8f 100644
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
@@ -34,6 +34,98 @@
clock-frequency = <24000000>;
};
};
+
+ dmc_opp_table: opp_table2 {
+ compatible = "operating-points-v2";
+
+ opp00 {
+ opp-hz = /bits/ 64 <165000000>;
+ opp-microvolt = <875000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <206000000>;
+ opp-microvolt = <875000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <275000000>;
+ opp-microvolt = <875000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <413000000>;
+ opp-microvolt = <887500>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <543000000>;
+ opp-microvolt = <937500>;
+ };
+ opp05 {
+ opp-hz = /bits/ 64 <633000000>;
+ opp-microvolt = <1012500>;
+ };
+ opp06 {
+ opp-hz = /bits/ 64 <728000000>;
+ opp-microvolt = <1037500>;
+ };
+ opp07 {
+ opp-hz = /bits/ 64 <825000000>;
+ opp-microvolt = <1050000>;
+ };
+ };
+
+ samsung_K3QF2F20DB: lpddr3 {
+ compatible = "samsung,K3QF2F20DB", "jedec,lpddr3";
+ density = <16384>;
+ io-width = <32>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tRFC-min-tck = <17>;
+ tRRD-min-tck = <2>;
+ tRPab-min-tck = <2>;
+ tRPpb-min-tck = <2>;
+ tRCD-min-tck = <3>;
+ tRC-min-tck = <6>;
+ tRAS-min-tck = <5>;
+ tWTR-min-tck = <2>;
+ tWR-min-tck = <7>;
+ tRTP-min-tck = <2>;
+ tW2W-C2C-min-tck = <0>;
+ tR2R-C2C-min-tck = <0>;
+ tWL-min-tck = <8>;
+ tDQSCK-min-tck = <5>;
+ tRL-min-tck = <14>;
+ tFAW-min-tck = <5>;
+ tXSR-min-tck = <12>;
+ tXP-min-tck = <2>;
+ tCKE-min-tck = <2>;
+ tCKESR-min-tck = <2>;
+ tMRD-min-tck = <5>;
+
+ timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 {
+ compatible = "jedec,lpddr3-timings";
+ /* workaround: 'reg' shows max-freq */
+ reg = <800000000>;
+ min-freq = <100000000>;
+ tRFC = <65000>;
+ tRRD = <6000>;
+ tRPab = <12000>;
+ tRPpb = <12000>;
+ tRCD = <10000>;
+ tRC = <33750>;
+ tRAS = <23000>;
+ tWTR = <3750>;
+ tWR = <7500>;
+ tRTP = <3750>;
+ tW2W-C2C = <0>;
+ tR2R-C2C = <0>;
+ tFAW = <25000>;
+ tXSR = <70000>;
+ tXP = <3750>;
+ tCKE = <3750>;
+ tCKESR = <3750>;
+ tMRD = <7000>;
+ };
+ };
};
&adc {
@@ -132,6 +224,15 @@
cpu-supply = <&buck2_reg>;
};
+&dmc {
+ devfreq-events = <&ppmu_event3_dmc0_0>, <&ppmu_event3_dmc0_1>,
+ <&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>;
+ device-handle = <&samsung_K3QF2F20DB>;
+ operating-points-v2 = <&dmc_opp_table>;
+ vdd-supply = <&buck1_reg>;
+ status = "okay";
+};
+
&hsi2c_4 {
status = "okay";
@@ -634,6 +735,22 @@
};
};
+&ppmu_dmc0_0 {
+ status = "okay";
+};
+
+&ppmu_dmc0_1 {
+ status = "okay";
+};
+
+&ppmu_dmc1_0 {
+ status = "okay";
+};
+
+&ppmu_dmc1_1 {
+ status = "okay";
+};
+
&tmu_cpu0 {
vtmu-supply = <&ldo7_reg>;
};
diff --git a/arch/arm/boot/dts/exynos5800.dtsi b/arch/arm/boot/dts/exynos5800.dtsi
index de639eecc5c9..16177d815ee4 100644
--- a/arch/arm/boot/dts/exynos5800.dtsi
+++ b/arch/arm/boot/dts/exynos5800.dtsi
@@ -17,7 +17,7 @@
};
&clock {
- compatible = "samsung,exynos5800-clock";
+ compatible = "samsung,exynos5800-clock", "syscon";
};
&cluster_a15_opp_table {
generated by cgit v1.2.3 (git 2.39.0) at 2024-12-03 21:32:45 +0300