diff options
| -rw-r--r-- | drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c | 12 |
1 files changed, 4 insertions, 8 deletions
diff --git a/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c b/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c index abfc077fb0a8..caa953780bee 100644 --- a/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c +++ b/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c @@ -213,7 +213,7 @@ static int mtk_hdmi_pll_calc(struct mtk_hdmi_phy *hdmi_phy, struct clk_hw *hw, u64 tmds_clk, pixel_clk, da_hdmitx21_ref_ck, ns_hdmipll_ck, pcw; u8 txpredivs[4] = { 2, 4, 6, 12 }; u32 fbkdiv_low; - int i, ret; + int i; pixel_clk = rate; tmds_clk = pixel_clk; @@ -271,7 +271,7 @@ static int mtk_hdmi_pll_calc(struct mtk_hdmi_phy *hdmi_phy, struct clk_hw *hw, * [32,24] 9bit integer, [23,0]:24bit fraction */ pcw = div_u64(((u64)ns_hdmipll_ck) << PCW_DECIMAL_WIDTH, - da_hdmitx21_ref_ck / PLL_FBKDIV_HS3); + da_hdmitx21_ref_ck * PLL_FBKDIV_HS3); if (pcw > GENMASK_ULL(32, 0)) return -EINVAL; @@ -288,17 +288,13 @@ static int mtk_hdmi_pll_calc(struct mtk_hdmi_phy *hdmi_phy, struct clk_hw *hw, posdiv2 = 1; /* Digital clk divider, max /32 */ - digital_div = div_u64((u64)ns_hdmipll_ck, posdiv1 / posdiv2 / pixel_clk); + digital_div = div_u64(ns_hdmipll_ck, posdiv1 * posdiv2 * pixel_clk); if (!(digital_div <= 32 && digital_div >= 1)) return -EINVAL; - mtk_hdmi_pll_set_hw(hw, PLL_PREDIV, fbkdiv_high, fbkdiv_low, + return mtk_hdmi_pll_set_hw(hw, PLL_PREDIV, fbkdiv_high, fbkdiv_low, PLL_FBKDIV_HS3, posdiv1, posdiv2, txprediv, txposdiv, digital_div); - if (ret) - return -EINVAL; - - return 0; } static int mtk_hdmi_pll_drv_setting(struct clk_hw *hw) |