diff options
| -rwxr-xr-x | arch/riscv/boot/dts/starfive/jh7110.dtsi | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index efae173a6f92..bd6b4ec809c5 100755 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -66,7 +66,7 @@ }; cpu0: cpu@0 { - compatible = "sifive,u74-mc", "riscv"; + compatible = "sifive,s7", "riscv"; reg = <0>; d-cache-block-size = <64>; d-cache-sets = <64>; @@ -81,7 +81,7 @@ i-tlb-size = <40>; mmu-type = "riscv,sv39"; next-level-cache = <&cachectrl>; - riscv,isa = "rv64imac"; + riscv,isa = "rv64imac_zba_zbb"; tlb-split; #cooling-cells = <2>; status = "disabled"; @@ -109,7 +109,7 @@ i-tlb-size = <40>; mmu-type = "riscv,sv39"; next-level-cache = <&cachectrl>; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zba_zbb"; tlb-split; #cooling-cells = <2>; status = "okay"; @@ -138,7 +138,7 @@ i-tlb-size = <40>; mmu-type = "riscv,sv39"; next-level-cache = <&cachectrl>; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zba_zbb"; tlb-split; #cooling-cells = <2>; status = "okay"; @@ -167,7 +167,7 @@ i-tlb-size = <40>; mmu-type = "riscv,sv39"; next-level-cache = <&cachectrl>; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zba_zbb"; tlb-split; #cooling-cells = <2>; status = "okay"; @@ -196,7 +196,7 @@ i-tlb-size = <40>; mmu-type = "riscv,sv39"; next-level-cache = <&cachectrl>; - riscv,isa = "rv64imafdc"; + riscv,isa = "rv64imafdc_zba_zbb"; tlb-split; #cooling-cells = <2>; status = "okay"; |