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| author | Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> | 2023-02-23 17:36:46 +0300 |
|---|---|---|
| committer | Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> | 2023-03-22 23:41:17 +0300 |
| commit | 2c00056f54299983009c13a8790fa004e5337d16 (patch) | |
| tree | f3f9cc7f65e07f9054f43f4c36029ee4b9770e35 /tools/power | |
| parent | 1d54b139f43482a5d394f26ce47aa9949dec6e76 (diff) | |
| download | linux-2c00056f54299983009c13a8790fa004e5337d16.tar.xz | |
tools/power/x86/intel-speed-select: Change TRL display for Emerald Rapids
Emerald Rapids doesn't specify TRL (Turbo Ratio Limits) based instruction
types. Instead it specifies 5 TRL levels, which can be anyone of the
instruction types.
Increase TRL levels to 5 for Emerald Rapids. Also change display to show
by level number. Show only non zero level values.
Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
Diffstat (limited to 'tools/power')
| -rw-r--r-- | tools/power/x86/intel-speed-select/isst-core-mbox.c | 15 | ||||
| -rw-r--r-- | tools/power/x86/intel-speed-select/isst-display.c | 9 |
2 files changed, 21 insertions, 3 deletions
diff --git a/tools/power/x86/intel-speed-select/isst-core-mbox.c b/tools/power/x86/intel-speed-select/isst-core-mbox.c index c860be30fe5e..24bea57f4ff5 100644 --- a/tools/power/x86/intel-speed-select/isst-core-mbox.c +++ b/tools/power/x86/intel-speed-select/isst-core-mbox.c @@ -8,6 +8,8 @@ static int mbox_delay; static int mbox_retries = 3; +#define MAX_TRL_LEVELS_EMR 5 + static int mbox_get_disp_freq_multiplier(void) { return DISP_FREQ_MULTIPLIER; @@ -15,11 +17,24 @@ static int mbox_get_disp_freq_multiplier(void) static int mbox_get_trl_max_levels(void) { + if (is_emr_platform()) + return MAX_TRL_LEVELS_EMR; + return 3; } static char *mbox_get_trl_level_name(int level) { + if (is_emr_platform()) { + static char level_str[18]; + + if (level >= MAX_TRL_LEVELS_EMR) + return NULL; + + snprintf(level_str, sizeof(level_str), "level-%d", level); + return level_str; + } + switch (level) { case 0: return "sse"; diff --git a/tools/power/x86/intel-speed-select/isst-display.c b/tools/power/x86/intel-speed-select/isst-display.c index 0e364b35f093..0403d42ab1ba 100644 --- a/tools/power/x86/intel-speed-select/isst-display.c +++ b/tools/power/x86/intel-speed-select/isst-display.c @@ -283,9 +283,9 @@ static void _isst_fact_display_information(struct isst_id *id, FILE *outf, int l bucket_info[j].hp_cores); format_and_print(outf, base_level + 2, header, value); for (i = 0; i < trl_max_levels; i++) { - if (fact_avx != 0xFF && !(fact_avx & (1 << i))) + if (!bucket_info[j].hp_ratios[i] || (fact_avx != 0xFF && !(fact_avx & (1 << i)))) continue; - if (i == 0 && api_version() == 1) + if (i == 0 && api_version() == 1 && !is_emr_platform()) snprintf(header, sizeof(header), "high-priority-max-frequency(MHz)"); else @@ -301,8 +301,11 @@ static void _isst_fact_display_information(struct isst_id *id, FILE *outf, int l format_and_print(outf, base_level + 1, header, NULL); for (j = 0; j < trl_max_levels; j++) { + if (!fact_info->lp_ratios[j]) + continue; + /* No AVX level name for SSE to be consistent with previous formatting */ - if (j == 0 && api_version() == 1) + if (j == 0 && api_version() == 1 && !is_emr_platform()) snprintf(header, sizeof(header), "low-priority-max-frequency(MHz)"); else snprintf(header, sizeof(header), "low-priority-max-%s-frequency(MHz)", |