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| author | Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> | 2018-06-12 08:52:17 +0300 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2018-06-18 14:26:43 +0300 |
| commit | 203cdf51f28820bee7893b4be392847418e6f4ec (patch) | |
| tree | 2ecad8a3ec2b6fdd1ffd9af44a0dc521495cb1f4 /tools/perf/scripts/python | |
| parent | 7cc90a5cadb1733d95d3c2bc147cbcf7843aa585 (diff) | |
| download | linux-203cdf51f28820bee7893b4be392847418e6f4ec.tar.xz | |
ASoC: rsnd: SSI parent cares SWSP bit
SSICR has SWSP bit (= Serial WS Polarity) which decides WS pin 1st
channel polarity (low or hi). This bit shouldn't exchange after running.
Current SSI "parent" doesn't care SSICR, just controls clock only.
Because of this behavior, if platform uses SSI0 as playback,
SSI1 as capture, and if user starts capture -> playback order,
SSI0 SSICR::SWSP bit exchanged 0 -> 1 during captureing, and it makes
capture noise.
This patch cares SSICR on SSI parent, too.
Special thanks to Yokoyama-san
Reported-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Tested-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions