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authorCharles Keepax <ckeepax@opensource.wolfsonmicro.com>2014-08-13 14:42:47 +0400
committerLee Jones <lee.jones@linaro.org>2014-09-26 11:15:39 +0400
commite569d937af96bc1ec00e33285fff33ae9c1e42d6 (patch)
tree1611190581e14d1d80967a7e2781c40e4ad3d4f4 /tools/perf/scripts/python
parent48018943eb906d81e48f40675c17b92abfeafcf1 (diff)
downloadlinux-e569d937af96bc1ec00e33285fff33ae9c1e42d6.tar.xz
mfd: arizona: Mark additional registers as volatile
Mark some additional registers as volatile. The write sequencer control registers should not be cached, as we don't ever want their value synchronised as this might cause a write sequence to be accidentally initiated. Additionally, the DAC_COMP registers require special preconditions to write so there values wouldn't be updated accurately during a register sync. Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
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