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| author | Stephen Boyd <sboyd@kernel.org> | 2018-10-01 20:56:17 +0300 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2018-10-01 20:56:17 +0300 |
| commit | be783cc8d72bb1e48b50c1838a3afeafad4c91c7 (patch) | |
| tree | 528ed82428d6c745f0de4b8a7921067f86133d91 /tools/perf/scripts/python/syscall-counts.py | |
| parent | f676d8612cd64af98e65134473917155c5080839 (diff) | |
| parent | a53a28dca4124048c90b4a8de457668ede57e67c (diff) | |
| download | linux-be783cc8d72bb1e48b50c1838a3afeafad4c91c7.tar.xz | |
Merge tag 'clk-renesas-for-v4.20-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull Renesas clk driver updates from Geert Uytterhoeven:
- Add support for CMT timer clocks on R-Car V3H
- Add support for SHDI and various timer clocks on R-Car V3M
- Add support for the new RZ/A2 (R7S9210) SoC, including early clock
support for the Renesas CPG/MSSR driver
- Add support for the new RZ/G1N (R8A7744) and RZ/G2E (R8A774C0) SoCs
- Convert DT binding includes to SPDX license identifiers
* tag 'clk-renesas-for-v4.20-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
clk: renesas: r7s9210: Add SPI clocks
clk: renesas: r7s9210: Move table update to separate function
clk: renesas: r7s9210: Convert some clocks to early
clk: renesas: cpg-mssr: Add early clock support
clk: renesas: r8a77970: Add TPU clock
clk: renesas: r8a77990: Fix incorrect PLL0 divider in comment
dt-bindings: clock: renesas: cpg-mssr: Document r8a774c0
clk: renesas: cpg-mssr: Add r8a774c0 support
clk: renesas: Add r8a774c0 CPG Core Clock Definitions
clk: renesas: r8a7743: Add r8a7744 support
clk: renesas: Add r8a7744 CPG Core Clock Definitions
dt-bindings: clock: renesas: cpg-mssr: Document r8a7744 binding
dt-bindings: clock: renesas: Convert to SPDX identifiers
clk: renesas: cpg-mssr: Add R7S9210 support
clk: renesas: r8a77970: Add TMU clocks
clk: renesas: r8a77970: Add CMT clocks
clk: renesas: r9a06g032: Fix UART34567 clock rate
clk: renesas: r8a77970: Add SD0H/SD0 clocks for SDHI
clk: renesas: r8a77980: Add CMT clocks
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts.py')
0 files changed, 0 insertions, 0 deletions