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authorVille Syrjälä <ville.syrjala@linux.intel.com>2024-09-30 20:04:13 +0300
committerVille Syrjälä <ville.syrjala@linux.intel.com>2024-10-04 00:33:28 +0300
commit01389846f7d61d262cc92d42ad4d1a25730e3eff (patch)
tree660a73d8aae17dd61b0cf9a9ae71a0d7858f5a35 /tools/perf/scripts/python/export-to-sqlite.py
parentdd6ec895bac91035fdcb065d39c5d920a539ebc7 (diff)
downloadlinux-01389846f7d61d262cc92d42ad4d1a25730e3eff.tar.xz
drm/i915: Plumb 'dsb' all way to the plane hooks
We need to be able to do both MMIO and DSB based pipe/plane programming. To that end plumb the 'dsb' all way from the top into the plane commit hooks. The compiler appears smart enough to combine the branches from all the back-to-back register writes into a single branch. So the generated asm ends up looking more or less like this: plane_hook() { if (dsb) { intel_dsb_reg_write(); intel_dsb_reg_write(); ... } else { intel_de_write_fw(); intel_de_write_fw(); ... } } which seems like a reasonably efficient way to do this. An alternative I was also considering is some kind of closure (register write function + display vs. dsb pointer passed to it). That does result is smaller code as there are no branches anymore, but having each register access go via function pointer sounds less efficient. Not that I actually measured the overhead of either approach yet. Also the reg_rw tracepoint seems to be making a huge mess of the generated code for the mmio path. And additionally there's some kind of IS_GSI_REG() hack in __raw_uncore_read() which ends up generating a pointless branch for every mmio register access. So looks like there might be quite a bit of room for improvement in the mmio path still. Reviewed-by: Animesh Manna <animesh.manna@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240930170415.23841-12-ville.syrjala@linux.intel.com
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