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| author | Mahesh Kumar <mahesh1.kumar@intel.com> | 2018-06-12 03:25:11 +0300 |
|---|---|---|
| committer | Paulo Zanoni <paulo.r.zanoni@intel.com> | 2018-06-13 00:12:34 +0300 |
| commit | af1f1b81130e82a1ee62fe48aa09e6bdab6e68f4 (patch) | |
| tree | ee1f6eec9d783453e173701674a5240b79e716c3 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | dccc7228b5de7658f79ad0074a57a8798462c533 (diff) | |
| download | linux-af1f1b81130e82a1ee62fe48aa09e6bdab6e68f4.tar.xz | |
drm/i915/icl: fix gmbus gpio pin mapping
ICP has GPIO pin 1/2 mapped to combo-phy ports & GPIO pins 9/10/11/12
mapped to tc ports[1-4].
This patch defines GPIOCTL registers for GPIO pins 9-12 & uses them in GPIO
pin mapping table.
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Madhav Chauhan <madhav.chauhan@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180612002512.29783-1-paulo.r.zanoni@intel.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions