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| author | Owen Chen <owen.chen@mediatek.com> | 2019-03-05 08:05:40 +0300 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2019-04-11 23:13:08 +0300 |
| commit | 9d7e1a82b7d195f901c2a18dd5602a1c11e9eefb (patch) | |
| tree | c64502c6a88052a8b1857af5516b68af1d461f8d /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | a3ae549917f1634f85c62984617521801505eb1e (diff) | |
| download | linux-9d7e1a82b7d195f901c2a18dd5602a1c11e9eefb.tar.xz | |
clk: mediatek: Add configurable pcwibits and fmin to mtk_pll_data
1. pcwibits: The integer bits of pcw for PLLs is extend to 8 bits,
add a variable to indicate this change and
backward-compatible.
2. fmin: The PLL frequency lower-bound is vary from 1GHz to
1.5GHz, add a variable to indicate platform-dependent.
Signed-off-by: Owen Chen <owen.chen@mediatek.com>
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Acked-by: Sean Wang <sean.wang@kernel.org>
Reviewed-by: James Liao <jamesjj.liao@mediatek.com>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions